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Rev	Author	Line No.	Line
5	mjames	1	;****************** (C) COPYRIGHT 2016 STMicroelectronics ******************
2	mjames	2	; File Name : startup_stm32f101xb.s*
		3	; Author : MCD Application Team*
5	mjames	4	; Version : V4.1.0*
		5	; Date : 29-April-2016*
2	mjames	6	; Description : STM32F101xB Devices vector table for MDK-ARM toolchain.*
		7	; This module performs:*
		8	; - Set the initial SP*
		9	; - Set the initial PC == Reset_Handler*
		10	; - Set the vector table entries with the exceptions ISR address*
		11	; - Configure the clock system*
		12	; - Branches to __main in the C library (which eventually*
		13	; calls main()).*
		14	; After Reset the Cortex-M3 processor is in Thread mode,*
		15	; priority is Privileged, and the Stack is set to Main.*
		16	;********************************************************************************
		17	;*
5	mjames	18	; COPYRIGHT(c) 2016 STMicroelectronics*
2	mjames	19	;*
		20	; Redistribution and use in source and binary forms, with or without modification,*
		21	; are permitted provided that the following conditions are met:*
		22	; 1. Redistributions of source code must retain the above copyright notice,*
		23	; this list of conditions and the following disclaimer.*
		24	; 2. Redistributions in binary form must reproduce the above copyright notice,*
		25	; this list of conditions and the following disclaimer in the documentation*
		26	; and/or other materials provided with the distribution.*
		27	; 3. Neither the name of STMicroelectronics nor the names of its contributors*
		28	; may be used to endorse or promote products derived from this software*
		29	; without specific prior written permission.*
		30	;*
		31	; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"*
		32	; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE*
		33	; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE*
		34	; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE*
		35	; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL*
		36	; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR*
		37	; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER*
		38	; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,*
		39	; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE*
		40	; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*
		41	;
		42	;*******************************************************************************
		43
		44	; Amount of memory (in bytes) allocated for Stack
		45	; Tailor this value to your application needs
		46	; <h> Stack Configuration
		47	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
		48	; </h>
		49
		50	Stack_Size EQU 0x00000400
		51
		52	AREA STACK, NOINIT, READWRITE, ALIGN=3
		53	Stack_Mem SPACE Stack_Size
		54	__initial_sp
		55
		56
		57	; <h> Heap Configuration
		58	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
		59	; </h>
		60
		61	Heap_Size EQU 0x00000200
		62
		63	AREA HEAP, NOINIT, READWRITE, ALIGN=3
		64	__heap_base
		65	Heap_Mem SPACE Heap_Size
		66	__heap_limit
		67
		68	PRESERVE8
		69	THUMB
		70
		71
		72	; Vector Table Mapped to Address 0 at Reset
		73	AREA RESET, DATA, READONLY
		74	EXPORT __Vectors
		75	EXPORT __Vectors_End
		76	EXPORT __Vectors_Size
		77
		78	__Vectors DCD __initial_sp ; Top of Stack
		79	DCD Reset_Handler ; Reset Handler
		80	DCD NMI_Handler ; NMI Handler
		81	DCD HardFault_Handler ; Hard Fault Handler
		82	DCD MemManage_Handler ; MPU Fault Handler
		83	DCD BusFault_Handler ; Bus Fault Handler
		84	DCD UsageFault_Handler ; Usage Fault Handler
		85	DCD 0 ; Reserved
		86	DCD 0 ; Reserved
		87	DCD 0 ; Reserved
		88	DCD 0 ; Reserved
		89	DCD SVC_Handler ; SVCall Handler
		90	DCD DebugMon_Handler ; Debug Monitor Handler
		91	DCD 0 ; Reserved
		92	DCD PendSV_Handler ; PendSV Handler
		93	DCD SysTick_Handler ; SysTick Handler
		94
		95	; External Interrupts
		96	DCD WWDG_IRQHandler ; Window Watchdog
		97	DCD PVD_IRQHandler ; PVD through EXTI Line detect
		98	DCD TAMPER_IRQHandler ; Tamper
		99	DCD RTC_IRQHandler ; RTC
		100	DCD FLASH_IRQHandler ; Flash
		101	DCD RCC_IRQHandler ; RCC
		102	DCD EXTI0_IRQHandler ; EXTI Line 0
		103	DCD EXTI1_IRQHandler ; EXTI Line 1
		104	DCD EXTI2_IRQHandler ; EXTI Line 2
		105	DCD EXTI3_IRQHandler ; EXTI Line 3
		106	DCD EXTI4_IRQHandler ; EXTI Line 4
		107	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		108	DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
		109	DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
		110	DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
		111	DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
		112	DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
		113	DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
		114	DCD ADC1_IRQHandler ; ADC1
		115	DCD 0 ; Reserved
		116	DCD 0 ; Reserved
		117	DCD 0 ; Reserved
		118	DCD 0 ; Reserved
		119	DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
		120	DCD 0 ; Reserved
		121	DCD 0 ; Reserved
		122	DCD 0 ; Reserved
		123	DCD 0 ; Reserved
		124	DCD TIM2_IRQHandler ; TIM2
		125	DCD TIM3_IRQHandler ; TIM3
		126	DCD TIM4_IRQHandler ; TIM4
		127	DCD I2C1_EV_IRQHandler ; I2C1 Event
		128	DCD I2C1_ER_IRQHandler ; I2C1 Error
		129	DCD I2C2_EV_IRQHandler ; I2C2 Event
		130	DCD I2C2_ER_IRQHandler ; I2C2 Error
		131	DCD SPI1_IRQHandler ; SPI1
		132	DCD SPI2_IRQHandler ; SPI2
		133	DCD USART1_IRQHandler ; USART1
		134	DCD USART2_IRQHandler ; USART2
		135	DCD USART3_IRQHandler ; USART3
		136	DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
		137	DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
		138	__Vectors_End
		139
		140	__Vectors_Size EQU __Vectors_End - __Vectors
		141
		142	AREA \|.text\|, CODE, READONLY
		143
		144	; Reset handler
		145	Reset_Handler PROC
		146	EXPORT Reset_Handler [WEAK]
		147	IMPORT __main
		148	IMPORT SystemInit
		149	LDR R0, =SystemInit
		150	BLX R0
		151	LDR R0, =__main
		152	BX R0
		153	ENDP
		154
		155	; Dummy Exception Handlers (infinite loops which can be modified)
		156
		157	NMI_Handler PROC
		158	EXPORT NMI_Handler [WEAK]
		159	B .
		160	ENDP
		161	HardFault_Handler\
		162	PROC
		163	EXPORT HardFault_Handler [WEAK]
		164	B .
		165	ENDP
		166	MemManage_Handler\
		167	PROC
		168	EXPORT MemManage_Handler [WEAK]
		169	B .
		170	ENDP
		171	BusFault_Handler\
		172	PROC
		173	EXPORT BusFault_Handler [WEAK]
		174	B .
		175	ENDP
		176	UsageFault_Handler\
		177	PROC
		178	EXPORT UsageFault_Handler [WEAK]
		179	B .
		180	ENDP
		181	SVC_Handler PROC
		182	EXPORT SVC_Handler [WEAK]
		183	B .
		184	ENDP
		185	DebugMon_Handler\
		186	PROC
		187	EXPORT DebugMon_Handler [WEAK]
		188	B .
		189	ENDP
		190	PendSV_Handler PROC
		191	EXPORT PendSV_Handler [WEAK]
		192	B .
		193	ENDP
		194	SysTick_Handler PROC
		195	EXPORT SysTick_Handler [WEAK]
		196	B .
		197	ENDP
		198
		199	Default_Handler PROC
		200
		201	EXPORT WWDG_IRQHandler [WEAK]
		202	EXPORT PVD_IRQHandler [WEAK]
		203	EXPORT TAMPER_IRQHandler [WEAK]
		204	EXPORT RTC_IRQHandler [WEAK]
		205	EXPORT FLASH_IRQHandler [WEAK]
		206	EXPORT RCC_IRQHandler [WEAK]
		207	EXPORT EXTI0_IRQHandler [WEAK]
		208	EXPORT EXTI1_IRQHandler [WEAK]
		209	EXPORT EXTI2_IRQHandler [WEAK]
		210	EXPORT EXTI3_IRQHandler [WEAK]
		211	EXPORT EXTI4_IRQHandler [WEAK]
		212	EXPORT DMA1_Channel1_IRQHandler [WEAK]
		213	EXPORT DMA1_Channel2_IRQHandler [WEAK]
		214	EXPORT DMA1_Channel3_IRQHandler [WEAK]
		215	EXPORT DMA1_Channel4_IRQHandler [WEAK]
		216	EXPORT DMA1_Channel5_IRQHandler [WEAK]
		217	EXPORT DMA1_Channel6_IRQHandler [WEAK]
		218	EXPORT DMA1_Channel7_IRQHandler [WEAK]
		219	EXPORT ADC1_IRQHandler [WEAK]
		220	EXPORT EXTI9_5_IRQHandler [WEAK]
		221	EXPORT TIM2_IRQHandler [WEAK]
		222	EXPORT TIM3_IRQHandler [WEAK]
		223	EXPORT TIM4_IRQHandler [WEAK]
		224	EXPORT I2C1_EV_IRQHandler [WEAK]
		225	EXPORT I2C1_ER_IRQHandler [WEAK]
		226	EXPORT I2C2_EV_IRQHandler [WEAK]
		227	EXPORT I2C2_ER_IRQHandler [WEAK]
		228	EXPORT SPI1_IRQHandler [WEAK]
		229	EXPORT SPI2_IRQHandler [WEAK]
		230	EXPORT USART1_IRQHandler [WEAK]
		231	EXPORT USART2_IRQHandler [WEAK]
		232	EXPORT USART3_IRQHandler [WEAK]
		233	EXPORT EXTI15_10_IRQHandler [WEAK]
		234	EXPORT RTC_Alarm_IRQHandler [WEAK]
		235
		236	WWDG_IRQHandler
		237	PVD_IRQHandler
		238	TAMPER_IRQHandler
		239	RTC_IRQHandler
		240	FLASH_IRQHandler
		241	RCC_IRQHandler
		242	EXTI0_IRQHandler
		243	EXTI1_IRQHandler
		244	EXTI2_IRQHandler
		245	EXTI3_IRQHandler
		246	EXTI4_IRQHandler
		247	DMA1_Channel1_IRQHandler
		248	DMA1_Channel2_IRQHandler
		249	DMA1_Channel3_IRQHandler
		250	DMA1_Channel4_IRQHandler
		251	DMA1_Channel5_IRQHandler
		252	DMA1_Channel6_IRQHandler
		253	DMA1_Channel7_IRQHandler
		254	ADC1_IRQHandler
		255	EXTI9_5_IRQHandler
		256	TIM2_IRQHandler
		257	TIM3_IRQHandler
		258	TIM4_IRQHandler
		259	I2C1_EV_IRQHandler
		260	I2C1_ER_IRQHandler
		261	I2C2_EV_IRQHandler
		262	I2C2_ER_IRQHandler
		263	SPI1_IRQHandler
		264	SPI2_IRQHandler
		265	USART1_IRQHandler
		266	USART2_IRQHandler
		267	USART3_IRQHandler
		268	EXTI15_10_IRQHandler
		269	RTC_Alarm_IRQHandler
		270
		271	B .
		272
		273	ENDP
		274
		275	ALIGN
		276
		277	;*******************************************************************************
		278	; User Stack and Heap initialization
		279	;*******************************************************************************
		280	IF :DEF:__MICROLIB
		281
		282	EXPORT __initial_sp
		283	EXPORT __heap_base
		284	EXPORT __heap_limit
		285
		286	ELSE
		287
		288	IMPORT __use_two_region_memory
		289	EXPORT __user_initial_stackheap
		290
		291	__user_initial_stackheap
		292
		293	LDR R0, = Heap_Mem
		294	LDR R1, =(Stack_Mem + Stack_Size)
		295	LDR R2, = (Heap_Mem + Heap_Size)
		296	LDR R3, = Stack_Mem
		297	BX LR
		298
		299	ALIGN
		300
		301	ENDIF
		302
		303	END
		304
		305	;********************** (C) COPYRIGHT STMicroelectronics *END OF FILE***

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