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Rev	Author	Line No.	Line
2	mjames	1	;****************** (C) COPYRIGHT 2015 STMicroelectronics ******************
		2	; File Name : startup_stm32f100xe.s*
		3	; Author : MCD Application Team*
		4	; Version : V4.0.1*
		5	; Date : 31-July-2015*
		6	; Description : STM32F100xE Devices vector table for MDK-ARM toolchain.*
		7	; This module performs:*
		8	; - Set the initial SP*
		9	; - Set the initial PC == Reset_Handler*
		10	; - Set the vector table entries with the exceptions ISR address*
		11	; - Configure the clock system and also configure the external*
		12	; SRAM mounted on STM32100E-EVAL board to be used as data*
		13	; memory (optional, to be enabled by user)*
		14	; - Branches to __main in the C library (which eventually*
		15	; calls main()).*
		16	; After Reset the Cortex-M3 processor is in Thread mode,*
		17	; priority is Privileged, and the Stack is set to Main.*
		18	;********************************************************************************
		19	;*
		20	; COPYRIGHT(c) 2015 STMicroelectronics*
		21	;*
		22	; Redistribution and use in source and binary forms, with or without modification,*
		23	; are permitted provided that the following conditions are met:*
		24	; 1. Redistributions of source code must retain the above copyright notice,*
		25	; this list of conditions and the following disclaimer.*
		26	; 2. Redistributions in binary form must reproduce the above copyright notice,*
		27	; this list of conditions and the following disclaimer in the documentation*
		28	; and/or other materials provided with the distribution.*
		29	; 3. Neither the name of STMicroelectronics nor the names of its contributors*
		30	; may be used to endorse or promote products derived from this software*
		31	; without specific prior written permission.*
		32	;*
		33	; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"*
		34	; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE*
		35	; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE*
		36	; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE*
		37	; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL*
		38	; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR*
		39	; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER*
		40	; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,*
		41	; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE*
		42	; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*
		43	;
		44	;*******************************************************************************
		45
		46	; Amount of memory (in bytes) allocated for Stack
		47	; Tailor this value to your application needs
		48	; <h> Stack Configuration
		49	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
		50	; </h>
		51
		52	Stack_Size EQU 0x00000400
		53
		54	AREA STACK, NOINIT, READWRITE, ALIGN=3
		55	Stack_Mem SPACE Stack_Size
		56	__initial_sp
		57
		58
		59	; <h> Heap Configuration
		60	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
		61	; </h>
		62
		63	Heap_Size EQU 0x00000200
		64
		65	AREA HEAP, NOINIT, READWRITE, ALIGN=3
		66	__heap_base
		67	Heap_Mem SPACE Heap_Size
		68	__heap_limit
		69
		70	PRESERVE8
		71	THUMB
		72
		73
		74	; Vector Table Mapped to Address 0 at Reset
		75	AREA RESET, DATA, READONLY
		76	EXPORT __Vectors
		77	EXPORT __Vectors_End
		78	EXPORT __Vectors_Size
		79
		80	__Vectors DCD __initial_sp ; Top of Stack
		81	DCD Reset_Handler ; Reset Handler
		82	DCD NMI_Handler ; NMI Handler
		83	DCD HardFault_Handler ; Hard Fault Handler
		84	DCD MemManage_Handler ; MPU Fault Handler
		85	DCD BusFault_Handler ; Bus Fault Handler
		86	DCD UsageFault_Handler ; Usage Fault Handler
		87	DCD 0 ; Reserved
		88	DCD 0 ; Reserved
		89	DCD 0 ; Reserved
		90	DCD 0 ; Reserved
		91	DCD SVC_Handler ; SVCall Handler
		92	DCD DebugMon_Handler ; Debug Monitor Handler
		93	DCD 0 ; Reserved
		94	DCD PendSV_Handler ; PendSV Handler
		95	DCD SysTick_Handler ; SysTick Handler
		96
		97	; External Interrupts
		98	DCD WWDG_IRQHandler ; Window Watchdog
		99	DCD PVD_IRQHandler ; PVD through EXTI Line detect
		100	DCD TAMPER_IRQHandler ; Tamper
		101	DCD RTC_IRQHandler ; RTC
		102	DCD FLASH_IRQHandler ; Flash
		103	DCD RCC_IRQHandler ; RCC
		104	DCD EXTI0_IRQHandler ; EXTI Line 0
		105	DCD EXTI1_IRQHandler ; EXTI Line 1
		106	DCD EXTI2_IRQHandler ; EXTI Line 2
		107	DCD EXTI3_IRQHandler ; EXTI Line 3
		108	DCD EXTI4_IRQHandler ; EXTI Line 4
		109	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		110	DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
		111	DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
		112	DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
		113	DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
		114	DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
		115	DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
		116	DCD ADC1_IRQHandler ; ADC1
		117	DCD 0 ; Reserved
		118	DCD 0 ; Reserved
		119	DCD 0 ; Reserved
		120	DCD 0 ; Reserved
		121	DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
		122	DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
		123	DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
		124	DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
		125	DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
		126	DCD TIM2_IRQHandler ; TIM2
		127	DCD TIM3_IRQHandler ; TIM3
		128	DCD TIM4_IRQHandler ; TIM4
		129	DCD I2C1_EV_IRQHandler ; I2C1 Event
		130	DCD I2C1_ER_IRQHandler ; I2C1 Error
		131	DCD I2C2_EV_IRQHandler ; I2C2 Event
		132	DCD I2C2_ER_IRQHandler ; I2C2 Error
		133	DCD SPI1_IRQHandler ; SPI1
		134	DCD SPI2_IRQHandler ; SPI2
		135	DCD USART1_IRQHandler ; USART1
		136	DCD USART2_IRQHandler ; USART2
		137	DCD USART3_IRQHandler ; USART3
		138	DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
		139	DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
		140	DCD CEC_IRQHandler ; HDMI CEC
		141	DCD TIM12_IRQHandler ; TIM12
		142	DCD TIM13_IRQHandler ; TIM13
		143	DCD TIM14_IRQHandler ; TIM14
		144	DCD 0 ; Reserved
		145	DCD 0 ; Reserved
		146	DCD 0 ; Reserved
		147	DCD 0 ; Reserved
		148	DCD TIM5_IRQHandler ; TIM5
		149	DCD SPI3_IRQHandler ; SPI3
		150	DCD UART4_IRQHandler ; UART4
		151	DCD UART5_IRQHandler ; UART5
		152	DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
		153	DCD TIM7_IRQHandler ; TIM7
		154	DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
		155	DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
		156	DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
		157	DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
		158	DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
		159	__Vectors_End
		160
		161	__Vectors_Size EQU __Vectors_End - __Vectors
		162
		163	AREA \|.text\|, CODE, READONLY
		164
		165	; Reset handler
		166	Reset_Handler PROC
		167	EXPORT Reset_Handler [WEAK]
		168	IMPORT __main
		169	IMPORT SystemInit
		170	LDR R0, =SystemInit
		171	BLX R0
		172	LDR R0, =__main
		173	BX R0
		174	ENDP
		175
		176	; Dummy Exception Handlers (infinite loops which can be modified)
		177
		178	NMI_Handler PROC
		179	EXPORT NMI_Handler [WEAK]
		180	B .
		181	ENDP
		182	HardFault_Handler\
		183	PROC
		184	EXPORT HardFault_Handler [WEAK]
		185	B .
		186	ENDP
		187	MemManage_Handler\
		188	PROC
		189	EXPORT MemManage_Handler [WEAK]
		190	B .
		191	ENDP
		192	BusFault_Handler\
		193	PROC
		194	EXPORT BusFault_Handler [WEAK]
		195	B .
		196	ENDP
		197	UsageFault_Handler\
		198	PROC
		199	EXPORT UsageFault_Handler [WEAK]
		200	B .
		201	ENDP
		202	SVC_Handler PROC
		203	EXPORT SVC_Handler [WEAK]
		204	B .
		205	ENDP
		206	DebugMon_Handler\
		207	PROC
		208	EXPORT DebugMon_Handler [WEAK]
		209	B .
		210	ENDP
		211	PendSV_Handler PROC
		212	EXPORT PendSV_Handler [WEAK]
		213	B .
		214	ENDP
		215	SysTick_Handler PROC
		216	EXPORT SysTick_Handler [WEAK]
		217	B .
		218	ENDP
		219
		220	Default_Handler PROC
		221
		222	EXPORT WWDG_IRQHandler [WEAK]
		223	EXPORT PVD_IRQHandler [WEAK]
		224	EXPORT TAMPER_IRQHandler [WEAK]
		225	EXPORT RTC_IRQHandler [WEAK]
		226	EXPORT FLASH_IRQHandler [WEAK]
		227	EXPORT RCC_IRQHandler [WEAK]
		228	EXPORT EXTI0_IRQHandler [WEAK]
		229	EXPORT EXTI1_IRQHandler [WEAK]
		230	EXPORT EXTI2_IRQHandler [WEAK]
		231	EXPORT EXTI3_IRQHandler [WEAK]
		232	EXPORT EXTI4_IRQHandler [WEAK]
		233	EXPORT DMA1_Channel1_IRQHandler [WEAK]
		234	EXPORT DMA1_Channel2_IRQHandler [WEAK]
		235	EXPORT DMA1_Channel3_IRQHandler [WEAK]
		236	EXPORT DMA1_Channel4_IRQHandler [WEAK]
		237	EXPORT DMA1_Channel5_IRQHandler [WEAK]
		238	EXPORT DMA1_Channel6_IRQHandler [WEAK]
		239	EXPORT DMA1_Channel7_IRQHandler [WEAK]
		240	EXPORT ADC1_IRQHandler [WEAK]
		241	EXPORT EXTI9_5_IRQHandler [WEAK]
		242	EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
		243	EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
		244	EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
		245	EXPORT TIM1_CC_IRQHandler [WEAK]
		246	EXPORT TIM2_IRQHandler [WEAK]
		247	EXPORT TIM3_IRQHandler [WEAK]
		248	EXPORT TIM4_IRQHandler [WEAK]
		249	EXPORT I2C1_EV_IRQHandler [WEAK]
		250	EXPORT I2C1_ER_IRQHandler [WEAK]
		251	EXPORT I2C2_EV_IRQHandler [WEAK]
		252	EXPORT I2C2_ER_IRQHandler [WEAK]
		253	EXPORT SPI1_IRQHandler [WEAK]
		254	EXPORT SPI2_IRQHandler [WEAK]
		255	EXPORT USART1_IRQHandler [WEAK]
		256	EXPORT USART2_IRQHandler [WEAK]
		257	EXPORT USART3_IRQHandler [WEAK]
		258	EXPORT EXTI15_10_IRQHandler [WEAK]
		259	EXPORT RTC_Alarm_IRQHandler [WEAK]
		260	EXPORT CEC_IRQHandler [WEAK]
		261	EXPORT TIM12_IRQHandler [WEAK]
		262	EXPORT TIM13_IRQHandler [WEAK]
		263	EXPORT TIM14_IRQHandler [WEAK]
		264	EXPORT TIM5_IRQHandler [WEAK]
		265	EXPORT SPI3_IRQHandler [WEAK]
		266	EXPORT UART4_IRQHandler [WEAK]
		267	EXPORT UART5_IRQHandler [WEAK]
		268	EXPORT TIM6_DAC_IRQHandler [WEAK]
		269	EXPORT TIM7_IRQHandler [WEAK]
		270	EXPORT DMA2_Channel1_IRQHandler [WEAK]
		271	EXPORT DMA2_Channel2_IRQHandler [WEAK]
		272	EXPORT DMA2_Channel3_IRQHandler [WEAK]
		273	EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
		274	EXPORT DMA2_Channel5_IRQHandler [WEAK]
		275
		276	WWDG_IRQHandler
		277	PVD_IRQHandler
		278	TAMPER_IRQHandler
		279	RTC_IRQHandler
		280	FLASH_IRQHandler
		281	RCC_IRQHandler
		282	EXTI0_IRQHandler
		283	EXTI1_IRQHandler
		284	EXTI2_IRQHandler
		285	EXTI3_IRQHandler
		286	EXTI4_IRQHandler
		287	DMA1_Channel1_IRQHandler
		288	DMA1_Channel2_IRQHandler
		289	DMA1_Channel3_IRQHandler
		290	DMA1_Channel4_IRQHandler
		291	DMA1_Channel5_IRQHandler
		292	DMA1_Channel6_IRQHandler
		293	DMA1_Channel7_IRQHandler
		294	ADC1_IRQHandler
		295	EXTI9_5_IRQHandler
		296	TIM1_BRK_TIM15_IRQHandler
		297	TIM1_UP_TIM16_IRQHandler
		298	TIM1_TRG_COM_TIM17_IRQHandler
		299	TIM1_CC_IRQHandler
		300	TIM2_IRQHandler
		301	TIM3_IRQHandler
		302	TIM4_IRQHandler
		303	I2C1_EV_IRQHandler
		304	I2C1_ER_IRQHandler
		305	I2C2_EV_IRQHandler
		306	I2C2_ER_IRQHandler
		307	SPI1_IRQHandler
		308	SPI2_IRQHandler
		309	USART1_IRQHandler
		310	USART2_IRQHandler
		311	USART3_IRQHandler
		312	EXTI15_10_IRQHandler
		313	RTC_Alarm_IRQHandler
		314	CEC_IRQHandler
		315	TIM12_IRQHandler
		316	TIM13_IRQHandler
		317	TIM14_IRQHandler
		318	TIM5_IRQHandler
		319	SPI3_IRQHandler
		320	UART4_IRQHandler
		321	UART5_IRQHandler
		322	TIM6_DAC_IRQHandler
		323	TIM7_IRQHandler
		324	DMA2_Channel1_IRQHandler
		325	DMA2_Channel2_IRQHandler
		326	DMA2_Channel3_IRQHandler
		327	DMA2_Channel4_5_IRQHandler
		328	DMA2_Channel5_IRQHandler
		329	B .
		330
		331	ENDP
		332
		333	ALIGN
		334
		335	;*******************************************************************************
		336	; User Stack and Heap initialization
		337	;*******************************************************************************
		338	IF :DEF:__MICROLIB
		339
		340	EXPORT __initial_sp
		341	EXPORT __heap_base
		342	EXPORT __heap_limit
		343
		344	ELSE
		345
		346	IMPORT __use_two_region_memory
		347	EXPORT __user_initial_stackheap
		348
		349	__user_initial_stackheap
		350
		351	LDR R0, = Heap_Mem
		352	LDR R1, =(Stack_Mem + Stack_Size)
		353	LDR R2, = (Heap_Mem + Heap_Size)
		354	LDR R3, = Stack_Mem
		355	BX LR
		356
		357	ALIGN
		358
		359	ENDIF
		360
		361	END
		362
		363	;********************** (C) COPYRIGHT STMicroelectronics *END OF FILE***

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f100xe.s – Rev 2