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Rev	Author	Line No.	Line
2	mjames	1	;****************** (C) COPYRIGHT 2017 STMicroelectronics ******************
		2	; File Name : startup_stm32f100xb.s*
		3	; Author : MCD Application Team*
		4	; Description : STM32F100xB Devices vector table for MDK-ARM toolchain.*
		5	; This module performs:*
		6	; - Set the initial SP*
		7	; - Set the initial PC == Reset_Handler*
		8	; - Set the vector table entries with the exceptions ISR address*
		9	; - Configure the clock system*
		10	; - Branches to __main in the C library (which eventually*
		11	; calls main()).*
		12	; After Reset the Cortex-M3 processor is in Thread mode,*
		13	; priority is Privileged, and the Stack is set to Main.*
		14	;******************************************************************************
		15	; @attention*
		16	;*
		17	; Copyright (c) 2017-2021 STMicroelectronics.*
		18	; All rights reserved.*
		19	;*
		20	; This software is licensed under terms that can be found in the LICENSE file*
		21	; in the root directory of this software component.*
		22	; If no LICENSE file comes with this software, it is provided AS-IS.*
		23	;*
		24	;******************************************************************************
		25
		26	; Amount of memory (in bytes) allocated for Stack
		27	; Tailor this value to your application needs
		28	; <h> Stack Configuration
		29	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
		30	; </h>
		31
		32	Stack_Size EQU 0x00000400
		33
		34	AREA STACK, NOINIT, READWRITE, ALIGN=3
		35	Stack_Mem SPACE Stack_Size
		36	__initial_sp
		37
		38
		39	; <h> Heap Configuration
		40	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
		41	; </h>
		42
		43	Heap_Size EQU 0x00000200
		44
		45	AREA HEAP, NOINIT, READWRITE, ALIGN=3
		46	__heap_base
		47	Heap_Mem SPACE Heap_Size
		48	__heap_limit
		49
		50	PRESERVE8
		51	THUMB
		52
		53
		54	; Vector Table Mapped to Address 0 at Reset
		55	AREA RESET, DATA, READONLY
		56	EXPORT __Vectors
		57	EXPORT __Vectors_End
		58	EXPORT __Vectors_Size
		59
		60	__Vectors DCD __initial_sp ; Top of Stack
		61	DCD Reset_Handler ; Reset Handler
		62	DCD NMI_Handler ; NMI Handler
		63	DCD HardFault_Handler ; Hard Fault Handler
		64	DCD MemManage_Handler ; MPU Fault Handler
		65	DCD BusFault_Handler ; Bus Fault Handler
		66	DCD UsageFault_Handler ; Usage Fault Handler
		67	DCD 0 ; Reserved
		68	DCD 0 ; Reserved
		69	DCD 0 ; Reserved
		70	DCD 0 ; Reserved
		71	DCD SVC_Handler ; SVCall Handler
		72	DCD DebugMon_Handler ; Debug Monitor Handler
		73	DCD 0 ; Reserved
		74	DCD PendSV_Handler ; PendSV Handler
		75	DCD SysTick_Handler ; SysTick Handler
		76
		77	; External Interrupts
		78	DCD WWDG_IRQHandler ; Window Watchdog
		79	DCD PVD_IRQHandler ; PVD through EXTI Line detect
		80	DCD TAMPER_IRQHandler ; Tamper
		81	DCD RTC_IRQHandler ; RTC
		82	DCD FLASH_IRQHandler ; Flash
		83	DCD RCC_IRQHandler ; RCC
		84	DCD EXTI0_IRQHandler ; EXTI Line 0
		85	DCD EXTI1_IRQHandler ; EXTI Line 1
		86	DCD EXTI2_IRQHandler ; EXTI Line 2
		87	DCD EXTI3_IRQHandler ; EXTI Line 3
		88	DCD EXTI4_IRQHandler ; EXTI Line 4
		89	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		90	DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
		91	DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
		92	DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
		93	DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
		94	DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
		95	DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
		96	DCD ADC1_IRQHandler ; ADC1
		97	DCD 0 ; Reserved
		98	DCD 0 ; Reserved
		99	DCD 0 ; Reserved
		100	DCD 0 ; Reserved
		101	DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
		102	DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
		103	DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
		104	DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
		105	DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
		106	DCD TIM2_IRQHandler ; TIM2
		107	DCD TIM3_IRQHandler ; TIM3
		108	DCD TIM4_IRQHandler ; TIM4
		109	DCD I2C1_EV_IRQHandler ; I2C1 Event
		110	DCD I2C1_ER_IRQHandler ; I2C1 Error
		111	DCD I2C2_EV_IRQHandler ; I2C2 Event
		112	DCD I2C2_ER_IRQHandler ; I2C2 Error
		113	DCD SPI1_IRQHandler ; SPI1
		114	DCD SPI2_IRQHandler ; SPI2
		115	DCD USART1_IRQHandler ; USART1
		116	DCD USART2_IRQHandler ; USART2
		117	DCD USART3_IRQHandler ; USART3
		118	DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
		119	DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
		120	DCD CEC_IRQHandler ; HDMI-CEC
		121	DCD 0 ; Reserved
		122	DCD 0 ; Reserved
		123	DCD 0 ; Reserved
		124	DCD 0 ; Reserved
		125	DCD 0 ; Reserved
		126	DCD 0 ; Reserved
		127	DCD 0 ; Reserved
		128	DCD 0 ; Reserved
		129	DCD 0 ; Reserved
		130	DCD 0 ; Reserved
		131	DCD 0 ; Reserved
		132	DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
		133	DCD TIM7_IRQHandler ; TIM7
		134	__Vectors_End
		135
		136	__Vectors_Size EQU __Vectors_End - __Vectors
		137
		138	AREA \|.text\|, CODE, READONLY
		139
		140	; Reset handler
		141	Reset_Handler PROC
		142	EXPORT Reset_Handler [WEAK]
		143	IMPORT __main
		144	IMPORT SystemInit
		145	LDR R0, =SystemInit
		146	BLX R0
		147	LDR R0, =__main
		148	BX R0
		149	ENDP
		150
		151	; Dummy Exception Handlers (infinite loops which can be modified)
		152
		153	NMI_Handler PROC
		154	EXPORT NMI_Handler [WEAK]
		155	B .
		156	ENDP
		157	HardFault_Handler\
		158	PROC
		159	EXPORT HardFault_Handler [WEAK]
		160	B .
		161	ENDP
		162	MemManage_Handler\
		163	PROC
		164	EXPORT MemManage_Handler [WEAK]
		165	B .
		166	ENDP
		167	BusFault_Handler\
		168	PROC
		169	EXPORT BusFault_Handler [WEAK]
		170	B .
		171	ENDP
		172	UsageFault_Handler\
		173	PROC
		174	EXPORT UsageFault_Handler [WEAK]
		175	B .
		176	ENDP
		177	SVC_Handler PROC
		178	EXPORT SVC_Handler [WEAK]
		179	B .
		180	ENDP
		181	DebugMon_Handler\
		182	PROC
		183	EXPORT DebugMon_Handler [WEAK]
		184	B .
		185	ENDP
		186	PendSV_Handler PROC
		187	EXPORT PendSV_Handler [WEAK]
		188	B .
		189	ENDP
		190	SysTick_Handler PROC
		191	EXPORT SysTick_Handler [WEAK]
		192	B .
		193	ENDP
		194
		195	Default_Handler PROC
		196
		197	EXPORT WWDG_IRQHandler [WEAK]
		198	EXPORT PVD_IRQHandler [WEAK]
		199	EXPORT TAMPER_IRQHandler [WEAK]
		200	EXPORT RTC_IRQHandler [WEAK]
		201	EXPORT FLASH_IRQHandler [WEAK]
		202	EXPORT RCC_IRQHandler [WEAK]
		203	EXPORT EXTI0_IRQHandler [WEAK]
		204	EXPORT EXTI1_IRQHandler [WEAK]
		205	EXPORT EXTI2_IRQHandler [WEAK]
		206	EXPORT EXTI3_IRQHandler [WEAK]
		207	EXPORT EXTI4_IRQHandler [WEAK]
		208	EXPORT DMA1_Channel1_IRQHandler [WEAK]
		209	EXPORT DMA1_Channel2_IRQHandler [WEAK]
		210	EXPORT DMA1_Channel3_IRQHandler [WEAK]
		211	EXPORT DMA1_Channel4_IRQHandler [WEAK]
		212	EXPORT DMA1_Channel5_IRQHandler [WEAK]
		213	EXPORT DMA1_Channel6_IRQHandler [WEAK]
		214	EXPORT DMA1_Channel7_IRQHandler [WEAK]
		215	EXPORT ADC1_IRQHandler [WEAK]
		216	EXPORT EXTI9_5_IRQHandler [WEAK]
		217	EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
		218	EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
		219	EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
		220	EXPORT TIM1_CC_IRQHandler [WEAK]
		221	EXPORT TIM2_IRQHandler [WEAK]
		222	EXPORT TIM3_IRQHandler [WEAK]
		223	EXPORT TIM4_IRQHandler [WEAK]
		224	EXPORT I2C1_EV_IRQHandler [WEAK]
		225	EXPORT I2C1_ER_IRQHandler [WEAK]
		226	EXPORT I2C2_EV_IRQHandler [WEAK]
		227	EXPORT I2C2_ER_IRQHandler [WEAK]
		228	EXPORT SPI1_IRQHandler [WEAK]
		229	EXPORT SPI2_IRQHandler [WEAK]
		230	EXPORT USART1_IRQHandler [WEAK]
		231	EXPORT USART2_IRQHandler [WEAK]
		232	EXPORT USART3_IRQHandler [WEAK]
		233	EXPORT EXTI15_10_IRQHandler [WEAK]
		234	EXPORT RTC_Alarm_IRQHandler [WEAK]
		235	EXPORT CEC_IRQHandler [WEAK]
		236	EXPORT TIM6_DAC_IRQHandler [WEAK]
		237	EXPORT TIM7_IRQHandler [WEAK]
		238
		239	WWDG_IRQHandler
		240	PVD_IRQHandler
		241	TAMPER_IRQHandler
		242	RTC_IRQHandler
		243	FLASH_IRQHandler
		244	RCC_IRQHandler
		245	EXTI0_IRQHandler
		246	EXTI1_IRQHandler
		247	EXTI2_IRQHandler
		248	EXTI3_IRQHandler
		249	EXTI4_IRQHandler
		250	DMA1_Channel1_IRQHandler
		251	DMA1_Channel2_IRQHandler
		252	DMA1_Channel3_IRQHandler
		253	DMA1_Channel4_IRQHandler
		254	DMA1_Channel5_IRQHandler
		255	DMA1_Channel6_IRQHandler
		256	DMA1_Channel7_IRQHandler
		257	ADC1_IRQHandler
		258	EXTI9_5_IRQHandler
		259	TIM1_BRK_TIM15_IRQHandler
		260	TIM1_UP_TIM16_IRQHandler
		261	TIM1_TRG_COM_TIM17_IRQHandler
		262	TIM1_CC_IRQHandler
		263	TIM2_IRQHandler
		264	TIM3_IRQHandler
		265	TIM4_IRQHandler
		266	I2C1_EV_IRQHandler
		267	I2C1_ER_IRQHandler
		268	I2C2_EV_IRQHandler
		269	I2C2_ER_IRQHandler
		270	SPI1_IRQHandler
		271	SPI2_IRQHandler
		272	USART1_IRQHandler
		273	USART2_IRQHandler
		274	USART3_IRQHandler
		275	EXTI15_10_IRQHandler
		276	RTC_Alarm_IRQHandler
		277	CEC_IRQHandler
		278	TIM6_DAC_IRQHandler
		279	TIM7_IRQHandler
		280	B .
		281
		282	ENDP
		283
		284	ALIGN
		285
		286	;*******************************************************************************
		287	; User Stack and Heap initialization
		288	;*******************************************************************************
		289	IF :DEF:__MICROLIB
		290
		291	EXPORT __initial_sp
		292	EXPORT __heap_base
		293	EXPORT __heap_limit
		294
		295	ELSE
		296
		297	IMPORT __use_two_region_memory
		298	EXPORT __user_initial_stackheap
		299
		300	__user_initial_stackheap
		301
		302	LDR R0, = Heap_Mem
		303	LDR R1, =(Stack_Mem + Stack_Size)
		304	LDR R2, = (Heap_Mem + Heap_Size)
		305	LDR R3, = Stack_Mem
		306	BX LR
		307
		308	ALIGN
		309
		310	ENDIF
		311
		312	END
		313

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f100xb.s – Rev 2