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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f107xc.h
		4	* @author MCD Application Team
		5	* @version V4.0.1
		6	* @date 31-July-2015
		7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		8	* This file contains all the peripheral register's definitions, bits
		9	* definitions and memory mapping for STM32F1xx devices.
		10	*
		11	* This file contains:
		12	* - Data structures and the address mapping for all peripherals
		13	* - Peripheral's registers declarations and bits definition
		14	* - Macros to access peripheral�s registers hardware
		15	*
		16	******************************************************************************
		17	* @attention
		18	*
		19	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
		20	*
		21	* Redistribution and use in source and binary forms, with or without modification,
		22	* are permitted provided that the following conditions are met:
		23	* 1. Redistributions of source code must retain the above copyright notice,
		24	* this list of conditions and the following disclaimer.
		25	* 2. Redistributions in binary form must reproduce the above copyright notice,
		26	* this list of conditions and the following disclaimer in the documentation
		27	* and/or other materials provided with the distribution.
		28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		29	* may be used to endorse or promote products derived from this software
		30	* without specific prior written permission.
		31	*
		32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		42	*
		43	******************************************************************************
		44	*/
		45
		46
		47	/** @addtogroup CMSIS
		48	* @{
		49	*/
		50
		51	/** @addtogroup stm32f107xc
		52	* @{
		53	*/
		54
		55	#ifndef __STM32F107xC_H
		56	#define __STM32F107xC_H
		57
		58	#ifdef __cplusplus
		59	extern "C" {
		60	#endif
		61
		62	/** @addtogroup Configuration_section_for_CMSIS
		63	* @{
		64	*/
		65	/**
		66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		67	*/
		68	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
		69	#define __CM3_REV 0x0200 /!< Core Revision r2p0 /
		70	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
		71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
		72
		73	/**
		74	* @}
		75	*/
		76
		77	/** @addtogroup Peripheral_interrupt_number_definition
		78	* @{
		79	*/
		80
		81	/**
		82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
		83	* in @ref Library_configuration_section
		84	*/
		85
		86	/!< Interrupt Number Definition /
		87	typedef enum
		88	{
		89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
		90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
		91	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		92	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		93	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		94	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		95	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		96	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		97	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		98
		99	/**** STM32 specific Interrupt Numbers *******************************************************/
		100	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		101	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		102	TAMPER_IRQn = 2, /!< Tamper Interrupt /
		103	RTC_IRQn = 3, /!< RTC global Interrupt /
		104	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		105	RCC_IRQn = 5, /!< RCC global Interrupt /
		106	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		107	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		108	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		109	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		110	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		111	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		112	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		113	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		114	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		115	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		116	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		117	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		118	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
		119	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupts /
		120	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupts /
		121	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
		122	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
		123	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		124	TIM1_BRK_IRQn = 24, /!< TIM1 Break Interrupt /
		125	TIM1_UP_IRQn = 25, /!< TIM1 Update Interrupt /
		126	TIM1_TRG_COM_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt /
		127	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
		128	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		129	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		130	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		131	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		132	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		133	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		134	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		135	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		136	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		137	USART1_IRQn = 37, /!< USART1 global Interrupt /
		138	USART2_IRQn = 38, /!< USART2 global Interrupt /
		139	USART3_IRQn = 39, /!< USART3 global Interrupt /
		140	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		141	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		142	OTG_FS_WKUP_IRQn = 42, /!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt /
		143	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
		144	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
		145	UART4_IRQn = 52, /!< UART4 global Interrupt /
		146	UART5_IRQn = 53, /!< UART5 global Interrupt /
		147	TIM6_IRQn = 54, /!< TIM6 global Interrupt /
		148	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
		149	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
		150	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
		151	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
		152	DMA2_Channel4_IRQn = 59, /!< DMA2 Channel 4 global Interrupt /
		153	DMA2_Channel5_IRQn = 60, /!< DMA2 Channel 5 global Interrupt /
		154	ETH_IRQn = 61, /!< Ethernet global Interrupt /
		155	ETH_WKUP_IRQn = 62, /!< Ethernet Wakeup through EXTI line Interrupt /
		156	CAN2_TX_IRQn = 63, /!< CAN2 TX Interrupt /
		157	CAN2_RX0_IRQn = 64, /!< CAN2 RX0 Interrupt /
		158	CAN2_RX1_IRQn = 65, /!< CAN2 RX1 Interrupt /
		159	CAN2_SCE_IRQn = 66, /!< CAN2 SCE Interrupt /
		160	OTG_FS_IRQn = 67 /!< USB OTG FS global Interrupt /
		161	} IRQn_Type;
		162
		163
		164	/**
		165	* @}
		166	*/
		167
		168	#include "core_cm3.h"
		169	#include "system_stm32f1xx.h"
		170	#include <stdint.h>
		171
		172	/** @addtogroup Peripheral_registers_structures
		173	* @{
		174	*/
		175
		176	/**
		177	* @brief Analog to Digital Converter
		178	*/
		179
		180	typedef struct
		181	{
		182	__IO uint32_t SR;
		183	__IO uint32_t CR1;
		184	__IO uint32_t CR2;
		185	__IO uint32_t SMPR1;
		186	__IO uint32_t SMPR2;
		187	__IO uint32_t JOFR1;
		188	__IO uint32_t JOFR2;
		189	__IO uint32_t JOFR3;
		190	__IO uint32_t JOFR4;
		191	__IO uint32_t HTR;
		192	__IO uint32_t LTR;
		193	__IO uint32_t SQR1;
		194	__IO uint32_t SQR2;
		195	__IO uint32_t SQR3;
		196	__IO uint32_t JSQR;
		197	__IO uint32_t JDR1;
		198	__IO uint32_t JDR2;
		199	__IO uint32_t JDR3;
		200	__IO uint32_t JDR4;
		201	__IO uint32_t DR;
		202	} ADC_TypeDef;
		203
		204	/**
		205	* @brief Backup Registers
		206	*/
		207
		208	typedef struct
		209	{
		210	uint32_t RESERVED0;
		211	__IO uint32_t DR1;
		212	__IO uint32_t DR2;
		213	__IO uint32_t DR3;
		214	__IO uint32_t DR4;
		215	__IO uint32_t DR5;
		216	__IO uint32_t DR6;
		217	__IO uint32_t DR7;
		218	__IO uint32_t DR8;
		219	__IO uint32_t DR9;
		220	__IO uint32_t DR10;
		221	__IO uint32_t RTCCR;
		222	__IO uint32_t CR;
		223	__IO uint32_t CSR;
		224	uint32_t RESERVED13[2];
		225	__IO uint32_t DR11;
		226	__IO uint32_t DR12;
		227	__IO uint32_t DR13;
		228	__IO uint32_t DR14;
		229	__IO uint32_t DR15;
		230	__IO uint32_t DR16;
		231	__IO uint32_t DR17;
		232	__IO uint32_t DR18;
		233	__IO uint32_t DR19;
		234	__IO uint32_t DR20;
		235	__IO uint32_t DR21;
		236	__IO uint32_t DR22;
		237	__IO uint32_t DR23;
		238	__IO uint32_t DR24;
		239	__IO uint32_t DR25;
		240	__IO uint32_t DR26;
		241	__IO uint32_t DR27;
		242	__IO uint32_t DR28;
		243	__IO uint32_t DR29;
		244	__IO uint32_t DR30;
		245	__IO uint32_t DR31;
		246	__IO uint32_t DR32;
		247	__IO uint32_t DR33;
		248	__IO uint32_t DR34;
		249	__IO uint32_t DR35;
		250	__IO uint32_t DR36;
		251	__IO uint32_t DR37;
		252	__IO uint32_t DR38;
		253	__IO uint32_t DR39;
		254	__IO uint32_t DR40;
		255	__IO uint32_t DR41;
		256	__IO uint32_t DR42;
		257	} BKP_TypeDef;
		258
		259	/**
		260	* @brief Controller Area Network TxMailBox
		261	*/
		262
		263	typedef struct
		264	{
		265	__IO uint32_t TIR;
		266	__IO uint32_t TDTR;
		267	__IO uint32_t TDLR;
		268	__IO uint32_t TDHR;
		269	} CAN_TxMailBox_TypeDef;
		270
		271	/**
		272	* @brief Controller Area Network FIFOMailBox
		273	*/
		274
		275	typedef struct
		276	{
		277	__IO uint32_t RIR;
		278	__IO uint32_t RDTR;
		279	__IO uint32_t RDLR;
		280	__IO uint32_t RDHR;
		281	} CAN_FIFOMailBox_TypeDef;
		282
		283	/**
		284	* @brief Controller Area Network FilterRegister
		285	*/
		286
		287	typedef struct
		288	{
		289	__IO uint32_t FR1;
		290	__IO uint32_t FR2;
		291	} CAN_FilterRegister_TypeDef;
		292
		293	/**
		294	* @brief Controller Area Network
		295	*/
		296
		297	typedef struct
		298	{
		299	__IO uint32_t MCR;
		300	__IO uint32_t MSR;
		301	__IO uint32_t TSR;
		302	__IO uint32_t RF0R;
		303	__IO uint32_t RF1R;
		304	__IO uint32_t IER;
		305	__IO uint32_t ESR;
		306	__IO uint32_t BTR;
		307	uint32_t RESERVED0[88];
		308	CAN_TxMailBox_TypeDef sTxMailBox[3];
		309	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
		310	uint32_t RESERVED1[12];
		311	__IO uint32_t FMR;
		312	__IO uint32_t FM1R;
		313	uint32_t RESERVED2;
		314	__IO uint32_t FS1R;
		315	uint32_t RESERVED3;
		316	__IO uint32_t FFA1R;
		317	uint32_t RESERVED4;
		318	__IO uint32_t FA1R;
		319	uint32_t RESERVED5[8];
		320	CAN_FilterRegister_TypeDef sFilterRegister[28];
		321	} CAN_TypeDef;
		322
		323	/**
		324	* @brief CRC calculation unit
		325	*/
		326
		327	typedef struct
		328	{
		329	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		330	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		331	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		332	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		333	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		334	} CRC_TypeDef;
		335
		336	/**
		337	* @brief Digital to Analog Converter
		338	*/
		339
		340	typedef struct
		341	{
		342	__IO uint32_t CR;
		343	__IO uint32_t SWTRIGR;
		344	__IO uint32_t DHR12R1;
		345	__IO uint32_t DHR12L1;
		346	__IO uint32_t DHR8R1;
		347	__IO uint32_t DHR12R2;
		348	__IO uint32_t DHR12L2;
		349	__IO uint32_t DHR8R2;
		350	__IO uint32_t DHR12RD;
		351	__IO uint32_t DHR12LD;
		352	__IO uint32_t DHR8RD;
		353	__IO uint32_t DOR1;
		354	__IO uint32_t DOR2;
		355	} DAC_TypeDef;
		356
		357	/**
		358	* @brief Debug MCU
		359	*/
		360
		361	typedef struct
		362	{
		363	__IO uint32_t IDCODE;
		364	__IO uint32_t CR;
		365	}DBGMCU_TypeDef;
		366
		367	/**
		368	* @brief DMA Controller
		369	*/
		370
		371	typedef struct
		372	{
		373	__IO uint32_t CCR;
		374	__IO uint32_t CNDTR;
		375	__IO uint32_t CPAR;
		376	__IO uint32_t CMAR;
		377	} DMA_Channel_TypeDef;
		378
		379	typedef struct
		380	{
		381	__IO uint32_t ISR;
		382	__IO uint32_t IFCR;
		383	} DMA_TypeDef;
		384
		385
		386
		387	/**
		388	* @brief Ethernet MAC
		389	*/
		390
		391	typedef struct
		392	{
		393	__IO uint32_t MACCR;
		394	__IO uint32_t MACFFR;
		395	__IO uint32_t MACHTHR;
		396	__IO uint32_t MACHTLR;
		397	__IO uint32_t MACMIIAR;
		398	__IO uint32_t MACMIIDR;
		399	__IO uint32_t MACFCR;
		400	__IO uint32_t MACVLANTR; /* 8 */
		401	uint32_t RESERVED0[2];
		402	__IO uint32_t MACRWUFFR; /* 11 */
		403	__IO uint32_t MACPMTCSR;
		404	uint32_t RESERVED1[2];
		405	__IO uint32_t MACSR; /* 15 */
		406	__IO uint32_t MACIMR;
		407	__IO uint32_t MACA0HR;
		408	__IO uint32_t MACA0LR;
		409	__IO uint32_t MACA1HR;
		410	__IO uint32_t MACA1LR;
		411	__IO uint32_t MACA2HR;
		412	__IO uint32_t MACA2LR;
		413	__IO uint32_t MACA3HR;
		414	__IO uint32_t MACA3LR; /* 24 */
		415	uint32_t RESERVED2[40];
		416	__IO uint32_t MMCCR; /* 65 */
		417	__IO uint32_t MMCRIR;
		418	__IO uint32_t MMCTIR;
		419	__IO uint32_t MMCRIMR;
		420	__IO uint32_t MMCTIMR; /* 69 */
		421	uint32_t RESERVED3[14];
		422	__IO uint32_t MMCTGFSCCR; /* 84 */
		423	__IO uint32_t MMCTGFMSCCR;
		424	uint32_t RESERVED4[5];
		425	__IO uint32_t MMCTGFCR;
		426	uint32_t RESERVED5[10];
		427	__IO uint32_t MMCRFCECR;
		428	__IO uint32_t MMCRFAECR;
		429	uint32_t RESERVED6[10];
		430	__IO uint32_t MMCRGUFCR;
		431	uint32_t RESERVED7[334];
		432	__IO uint32_t PTPTSCR;
		433	__IO uint32_t PTPSSIR;
		434	__IO uint32_t PTPTSHR;
		435	__IO uint32_t PTPTSLR;
		436	__IO uint32_t PTPTSHUR;
		437	__IO uint32_t PTPTSLUR;
		438	__IO uint32_t PTPTSAR;
		439	__IO uint32_t PTPTTHR;
		440	__IO uint32_t PTPTTLR;
		441	uint32_t RESERVED8[567];
		442	__IO uint32_t DMABMR;
		443	__IO uint32_t DMATPDR;
		444	__IO uint32_t DMARPDR;
		445	__IO uint32_t DMARDLAR;
		446	__IO uint32_t DMATDLAR;
		447	__IO uint32_t DMASR;
		448	__IO uint32_t DMAOMR;
		449	__IO uint32_t DMAIER;
		450	__IO uint32_t DMAMFBOCR;
		451	uint32_t RESERVED9[9];
		452	__IO uint32_t DMACHTDR;
		453	__IO uint32_t DMACHRDR;
		454	__IO uint32_t DMACHTBAR;
		455	__IO uint32_t DMACHRBAR;
		456	} ETH_TypeDef;
		457
		458
		459	/**
		460	* @brief External Interrupt/Event Controller
		461	*/
		462
		463	typedef struct
		464	{
		465	__IO uint32_t IMR;
		466	__IO uint32_t EMR;
		467	__IO uint32_t RTSR;
		468	__IO uint32_t FTSR;
		469	__IO uint32_t SWIER;
		470	__IO uint32_t PR;
		471	} EXTI_TypeDef;
		472
		473	/**
		474	* @brief FLASH Registers
		475	*/
		476
		477	typedef struct
		478	{
		479	__IO uint32_t ACR;
		480	__IO uint32_t KEYR;
		481	__IO uint32_t OPTKEYR;
		482	__IO uint32_t SR;
		483	__IO uint32_t CR;
		484	__IO uint32_t AR;
		485	__IO uint32_t RESERVED;
		486	__IO uint32_t OBR;
		487	__IO uint32_t WRPR;
		488	} FLASH_TypeDef;
		489
		490	/**
		491	* @brief Option Bytes Registers
		492	*/
		493
		494	typedef struct
		495	{
		496	__IO uint16_t RDP;
		497	__IO uint16_t USER;
		498	__IO uint16_t Data0;
		499	__IO uint16_t Data1;
		500	__IO uint16_t WRP0;
		501	__IO uint16_t WRP1;
		502	__IO uint16_t WRP2;
		503	__IO uint16_t WRP3;
		504	} OB_TypeDef;
		505
		506	/**
		507	* @brief General Purpose I/O
		508	*/
		509
		510	typedef struct
		511	{
		512	__IO uint32_t CRL;
		513	__IO uint32_t CRH;
		514	__IO uint32_t IDR;
		515	__IO uint32_t ODR;
		516	__IO uint32_t BSRR;
		517	__IO uint32_t BRR;
		518	__IO uint32_t LCKR;
		519	} GPIO_TypeDef;
		520
		521	/**
		522	* @brief Alternate Function I/O
		523	*/
		524
		525	typedef struct
		526	{
		527	__IO uint32_t EVCR;
		528	__IO uint32_t MAPR;
		529	__IO uint32_t EXTICR[4];
		530	uint32_t RESERVED0;
		531	__IO uint32_t MAPR2;
		532	} AFIO_TypeDef;
		533	/**
		534	* @brief Inter Integrated Circuit Interface
		535	*/
		536
		537	typedef struct
		538	{
		539	__IO uint32_t CR1;
		540	__IO uint32_t CR2;
		541	__IO uint32_t OAR1;
		542	__IO uint32_t OAR2;
		543	__IO uint32_t DR;
		544	__IO uint32_t SR1;
		545	__IO uint32_t SR2;
		546	__IO uint32_t CCR;
		547	__IO uint32_t TRISE;
		548	} I2C_TypeDef;
		549
		550	/**
		551	* @brief Independent WATCHDOG
		552	*/
		553
		554	typedef struct
		555	{
		556	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		557	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		558	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		559	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		560	} IWDG_TypeDef;
		561
		562	/**
		563	* @brief Power Control
		564	*/
		565
		566	typedef struct
		567	{
		568	__IO uint32_t CR;
		569	__IO uint32_t CSR;
		570	} PWR_TypeDef;
		571
		572	/**
		573	* @brief Reset and Clock Control
		574	*/
		575
		576	typedef struct
		577	{
		578	__IO uint32_t CR;
		579	__IO uint32_t CFGR;
		580	__IO uint32_t CIR;
		581	__IO uint32_t APB2RSTR;
		582	__IO uint32_t APB1RSTR;
		583	__IO uint32_t AHBENR;
		584	__IO uint32_t APB2ENR;
		585	__IO uint32_t APB1ENR;
		586	__IO uint32_t BDCR;
		587	__IO uint32_t CSR;
		588
		589	__IO uint32_t AHBRSTR;
		590	__IO uint32_t CFGR2;
		591
		592	} RCC_TypeDef;
		593
		594	/**
		595	* @brief Real-Time Clock
		596	*/
		597
		598	typedef struct
		599	{
		600	__IO uint32_t CRH;
		601	__IO uint32_t CRL;
		602	__IO uint32_t PRLH;
		603	__IO uint32_t PRLL;
		604	__IO uint32_t DIVH;
		605	__IO uint32_t DIVL;
		606	__IO uint32_t CNTH;
		607	__IO uint32_t CNTL;
		608	__IO uint32_t ALRH;
		609	__IO uint32_t ALRL;
		610	} RTC_TypeDef;
		611
		612	/**
		613	* @brief SD host Interface
		614	*/
		615
		616	typedef struct
		617	{
		618	__IO uint32_t POWER;
		619	__IO uint32_t CLKCR;
		620	__IO uint32_t ARG;
		621	__IO uint32_t CMD;
		622	__I uint32_t RESPCMD;
		623	__I uint32_t RESP1;
		624	__I uint32_t RESP2;
		625	__I uint32_t RESP3;
		626	__I uint32_t RESP4;
		627	__IO uint32_t DTIMER;
		628	__IO uint32_t DLEN;
		629	__IO uint32_t DCTRL;
		630	__I uint32_t DCOUNT;
		631	__I uint32_t STA;
		632	__IO uint32_t ICR;
		633	__IO uint32_t MASK;
		634	uint32_t RESERVED0[2];
		635	__I uint32_t FIFOCNT;
		636	uint32_t RESERVED1[13];
		637	__IO uint32_t FIFO;
		638	} SDIO_TypeDef;
		639
		640	/**
		641	* @brief Serial Peripheral Interface
		642	*/
		643
		644	typedef struct
		645	{
		646	__IO uint32_t CR1;
		647	__IO uint32_t CR2;
		648	__IO uint32_t SR;
		649	__IO uint32_t DR;
		650	__IO uint32_t CRCPR;
		651	__IO uint32_t RXCRCR;
		652	__IO uint32_t TXCRCR;
		653	__IO uint32_t I2SCFGR;
		654	__IO uint32_t I2SPR;
		655	} SPI_TypeDef;
		656
		657	/**
		658	* @brief TIM Timers
		659	*/
		660	typedef struct
		661	{
		662	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		663	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		664	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		665	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		666	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		667	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		668	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		669	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		670	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		671	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		672	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		673	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		674	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
		675	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		676	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		677	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		678	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		679	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
		680	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		681	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
		682	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		683	}TIM_TypeDef;
		684
		685
		686	/**
		687	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		688	*/
		689
		690	typedef struct
		691	{
		692	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		693	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		694	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		695	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		696	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		697	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		698	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		699	} USART_TypeDef;
		700
		701
		702	/**
		703	* @brief __USB_OTG_Core_register
		704	*/
		705
		706	typedef struct
		707	{
		708	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register Address offset: 000h /
		709	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register Address offset: 004h /
		710	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register Address offset: 008h /
		711	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register Address offset: 00Ch /
		712	__IO uint32_t GRSTCTL; /!< Core Reset Register Address offset: 010h /
		713	__IO uint32_t GINTSTS; /!< Core Interrupt Register Address offset: 014h /
		714	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register Address offset: 018h /
		715	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register Address offset: 01Ch /
		716	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register Address offset: 020h /
		717	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register Address offset: 024h /
		718	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h /
		719	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch /
		720	uint32_t Reserved30[2]; /!< Reserved 030h/
		721	__IO uint32_t GCCFG; /!< General Purpose IO Register Address offset: 038h /
		722	__IO uint32_t CID; /!< User ID Register Address offset: 03Ch /
		723	uint32_t Reserved40[48]; /!< Reserved 040h-0FFh /
		724	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg Address offset: 100h /
		725	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO Address offset: 0x104 /
		726	} USB_OTG_GlobalTypeDef;
		727
		728	/**
		729	* @brief __device_Registers
		730	*/
		731
		732	typedef struct
		733	{
		734	__IO uint32_t DCFG; /!< dev Configuration Register Address offset: 800h/
		735	__IO uint32_t DCTL; /!< dev Control Register Address offset: 804h/
		736	__IO uint32_t DSTS; /!< dev Status Register (RO) Address offset: 808h/
		737	uint32_t Reserved0C; /!< Reserved 80Ch/
		738	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask Address offset: 810h/
		739	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask Address offset: 814h/
		740	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg Address offset: 818h/
		741	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask Address offset: 81Ch/
		742	uint32_t Reserved20; /!< Reserved 820h/
		743	uint32_t Reserved9; /!< Reserved 824h/
		744	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register Address offset: 828h/
		745	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register Address offset: 82Ch/
		746	__IO uint32_t DTHRCTL; /!< dev thr Address offset: 830h/
		747	__IO uint32_t DIEPEMPMSK; /!< dev empty msk Address offset: 834h/
		748	__IO uint32_t DEACHINT; /!< dedicated EP interrupt Address offset: 838h/
		749	__IO uint32_t DEACHMSK; /!< dedicated EP msk Address offset: 83Ch/
		750	uint32_t Reserved40; /!< dedicated EP mask Address offset: 840h/
		751	__IO uint32_t DINEP1MSK; /!< dedicated EP mask Address offset: 844h/
		752	uint32_t Reserved44[15]; /!< Reserved 844-87Ch/
		753	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk Address offset: 884h/
		754	} USB_OTG_DeviceTypeDef;
		755
		756	/**
		757	* @brief __IN_Endpoint-Specific_Register
		758	*/
		759
		760	typedef struct
		761	{
		762	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h*/
		763	uint32_t Reserved04; /!< Reserved 900h + (ep_num 20h) + 04h*/
		764	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h*/
		765	uint32_t Reserved0C; /!< Reserved 900h + (ep_num 20h) + 0Ch*/
		766	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h*/
		767	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h*/
		768	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h*/
		769	uint32_t Reserved18; /!< Reserved 900h+(ep_num20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
		770	} USB_OTG_INEndpointTypeDef;
		771
		772	/**
		773	* @brief __OUT_Endpoint-Specific_Registers
		774	*/
		775
		776	typedef struct
		777	{
		778	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h*/
		779	uint32_t Reserved04; /!< Reserved B00h + (ep_num 20h) + 04h*/
		780	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h*/
		781	uint32_t Reserved0C; /!< Reserved B00h + (ep_num 20h) + 0Ch*/
		782	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h*/
		783	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h*/
		784	uint32_t Reserved18[2]; /!< Reserved B00h + (ep_num 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
		785	} USB_OTG_OUTEndpointTypeDef;
		786
		787	/**
		788	* @brief __Host_Mode_Register_Structures
		789	*/
		790
		791	typedef struct
		792	{
		793	__IO uint32_t HCFG; /!< Host Configuration Register 400h/
		794	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h/
		795	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h/
		796	uint32_t Reserved40C; /!< Reserved 40Ch/
		797	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h/
		798	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h/
		799	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h/
		800	} USB_OTG_HostTypeDef;
		801
		802	/**
		803	* @brief __Host_Channel_Specific_Registers
		804	*/
		805
		806	typedef struct
		807	{
		808	__IO uint32_t HCCHAR;
		809	__IO uint32_t HCSPLT;
		810	__IO uint32_t HCINT;
		811	__IO uint32_t HCINTMSK;
		812	__IO uint32_t HCTSIZ;
		813	__IO uint32_t HCDMA;
		814	uint32_t Reserved[2];
		815	} USB_OTG_HostChannelTypeDef;
		816
		817	/**
		818	* @brief Window WATCHDOG
		819	*/
		820
		821	typedef struct
		822	{
		823	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		824	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		825	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		826	} WWDG_TypeDef;
		827
		828	/**
		829	* @}
		830	*/
		831
		832	/** @addtogroup Peripheral_memory_map
		833	* @{
		834	*/
		835
		836
		837	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
		838	#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /!< FLASH END address of bank1 /
		839	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
		840	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
		841
		842	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
		843	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
		844
		845
		846	/!< Peripheral memory map /
		847	#define APB1PERIPH_BASE PERIPH_BASE
		848	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
		849	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
		850
		851	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
		852	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
		853	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
		854	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
		855	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
		856	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
		857	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
		858	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
		859	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
		860	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
		861	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
		862	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
		863	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
		864	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
		865	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
		866	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
		867	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
		868	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
		869	#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
		870	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
		871	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
		872	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
		873	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
		874	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
		875	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
		876	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
		877	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
		878	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
		879	#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
		880	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
		881	#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
		882	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
		883	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
		884	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
		885
		886	#define SDIO_BASE (PERIPH_BASE + 0x18000)
		887
		888	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
		889	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
		890	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
		891	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
		892	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
		893	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
		894	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
		895	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
		896	#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
		897	#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
		898	#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
		899	#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
		900	#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
		901	#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
		902	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
		903	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
		904
		905	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
		906	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
		907
		908	#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
		909	#define ETH_MAC_BASE (ETH_BASE)
		910	#define ETH_MMC_BASE (ETH_BASE + 0x0100)
		911	#define ETH_PTP_BASE (ETH_BASE + 0x0700)
		912	#define ETH_DMA_BASE (ETH_BASE + 0x1000)
		913
		914
		915	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
		916
		917
		918	/!< USB registers base address /
		919	#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
		920
		921	#define USB_OTG_GLOBAL_BASE ((uint32_t )0x00000000)
		922	#define USB_OTG_DEVICE_BASE ((uint32_t )0x00000800)
		923	#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x00000900)
		924	#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0x00000B00)
		925	#define USB_OTG_EP_REG_SIZE ((uint32_t )0x00000020)
		926	#define USB_OTG_HOST_BASE ((uint32_t )0x00000400)
		927	#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x00000440)
		928	#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x00000500)
		929	#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x00000020)
		930	#define USB_OTG_PCGCCTL_BASE ((uint32_t )0x00000E00)
		931	#define USB_OTG_FIFO_BASE ((uint32_t )0x00001000)
		932	#define USB_OTG_FIFO_SIZE ((uint32_t )0x00001000)
		933
		934	/**
		935	* @}
		936	*/
		937
		938	/** @addtogroup Peripheral_declaration
		939	* @{
		940	*/
		941
		942	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
		943	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
		944	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
		945	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
		946	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
		947	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
		948	#define RTC ((RTC_TypeDef *) RTC_BASE)
		949	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
		950	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
		951	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
		952	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
		953	#define USART2 ((USART_TypeDef *) USART2_BASE)
		954	#define USART3 ((USART_TypeDef *) USART3_BASE)
		955	#define UART4 ((USART_TypeDef *) UART4_BASE)
		956	#define UART5 ((USART_TypeDef *) UART5_BASE)
		957	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
		958	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
		959	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
		960	#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
		961	#define BKP ((BKP_TypeDef *) BKP_BASE)
		962	#define PWR ((PWR_TypeDef *) PWR_BASE)
		963	#define DAC ((DAC_TypeDef *) DAC_BASE)
		964	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
		965	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
		966	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
		967	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
		968	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
		969	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
		970	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
		971	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
		972	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
		973	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
		974	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
		975	#define USART1 ((USART_TypeDef *) USART1_BASE)
		976	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
		977	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
		978	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
		979	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
		980	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
		981	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
		982	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
		983	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
		984	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
		985	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
		986	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
		987	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
		988	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
		989	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
		990	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
		991	#define RCC ((RCC_TypeDef *) RCC_BASE)
		992	#define CRC ((CRC_TypeDef *) CRC_BASE)
		993	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
		994	#define OB ((OB_TypeDef *) OB_BASE)
		995	#define ETH ((ETH_TypeDef *) ETH_BASE)
		996	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
		997
		998	#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
		999
		1000	/**
		1001	* @}
		1002	*/
		1003
		1004	/** @addtogroup Exported_constants
		1005	* @{
		1006	*/
		1007
		1008	/** @addtogroup Peripheral_Registers_Bits_Definition
		1009	* @{
		1010	*/
		1011
		1012	/******************************************************************************/
		1013	/* Peripheral Registers_Bits_Definition */
		1014	/******************************************************************************/
		1015
		1016	/******************************************************************************/
		1017	/* */
		1018	/* CRC calculation unit (CRC) */
		1019	/* */
		1020	/******************************************************************************/
		1021
		1022	/***************** Bit definition for CRC_DR register *******************/
		1023	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
		1024
		1025	/***************** Bit definition for CRC_IDR register ******************/
		1026	#define CRC_IDR_IDR ((uint32_t)0xFF) /!< General-purpose 8-bit data register bits /
		1027
		1028	/****************** Bit definition for CRC_CR register ******************/
		1029	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
		1030
		1031	/******************************************************************************/
		1032	/* */
		1033	/* Power Control */
		1034	/* */
		1035	/******************************************************************************/
		1036
		1037	/****************** Bit definition for PWR_CR register ******************/
		1038	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
		1039	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
		1040	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
		1041	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
		1042	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
		1043
		1044	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
		1045	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
		1046	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
		1047	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
		1048
		1049	/!< PVD level configuration /
		1050	#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /!< PVD level 2.2V /
		1051	#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /!< PVD level 2.3V /
		1052	#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /!< PVD level 2.4V /
		1053	#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /!< PVD level 2.5V /
		1054	#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /!< PVD level 2.6V /
		1055	#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /!< PVD level 2.7V /
		1056	#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /!< PVD level 2.8V /
		1057	#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /!< PVD level 2.9V /
		1058
		1059	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
		1060
		1061
		1062	/***************** Bit definition for PWR_CSR register ******************/
		1063	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
		1064	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
		1065	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
		1066	#define PWR_CSR_EWUP ((uint32_t)0x00000100) /!< Enable WKUP pin /
		1067
		1068	/******************************************************************************/
		1069	/* */
		1070	/* Backup registers */
		1071	/* */
		1072	/******************************************************************************/
		1073
		1074	/***************** Bit definition for BKP_DR1 register ******************/
		1075	#define BKP_DR1_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1076
		1077	/***************** Bit definition for BKP_DR2 register ******************/
		1078	#define BKP_DR2_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1079
		1080	/***************** Bit definition for BKP_DR3 register ******************/
		1081	#define BKP_DR3_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1082
		1083	/***************** Bit definition for BKP_DR4 register ******************/
		1084	#define BKP_DR4_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1085
		1086	/***************** Bit definition for BKP_DR5 register ******************/
		1087	#define BKP_DR5_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1088
		1089	/***************** Bit definition for BKP_DR6 register ******************/
		1090	#define BKP_DR6_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1091
		1092	/***************** Bit definition for BKP_DR7 register ******************/
		1093	#define BKP_DR7_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1094
		1095	/***************** Bit definition for BKP_DR8 register ******************/
		1096	#define BKP_DR8_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1097
		1098	/***************** Bit definition for BKP_DR9 register ******************/
		1099	#define BKP_DR9_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1100
		1101	/***************** Bit definition for BKP_DR10 register *****************/
		1102	#define BKP_DR10_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1103
		1104	/***************** Bit definition for BKP_DR11 register *****************/
		1105	#define BKP_DR11_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1106
		1107	/***************** Bit definition for BKP_DR12 register *****************/
		1108	#define BKP_DR12_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1109
		1110	/***************** Bit definition for BKP_DR13 register *****************/
		1111	#define BKP_DR13_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1112
		1113	/***************** Bit definition for BKP_DR14 register *****************/
		1114	#define BKP_DR14_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1115
		1116	/***************** Bit definition for BKP_DR15 register *****************/
		1117	#define BKP_DR15_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1118
		1119	/***************** Bit definition for BKP_DR16 register *****************/
		1120	#define BKP_DR16_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1121
		1122	/***************** Bit definition for BKP_DR17 register *****************/
		1123	#define BKP_DR17_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1124
		1125	/**************** Bit definition for BKP_DR18 register ******************/
		1126	#define BKP_DR18_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1127
		1128	/***************** Bit definition for BKP_DR19 register *****************/
		1129	#define BKP_DR19_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1130
		1131	/***************** Bit definition for BKP_DR20 register *****************/
		1132	#define BKP_DR20_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1133
		1134	/***************** Bit definition for BKP_DR21 register *****************/
		1135	#define BKP_DR21_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1136
		1137	/***************** Bit definition for BKP_DR22 register *****************/
		1138	#define BKP_DR22_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1139
		1140	/***************** Bit definition for BKP_DR23 register *****************/
		1141	#define BKP_DR23_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1142
		1143	/***************** Bit definition for BKP_DR24 register *****************/
		1144	#define BKP_DR24_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1145
		1146	/***************** Bit definition for BKP_DR25 register *****************/
		1147	#define BKP_DR25_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1148
		1149	/***************** Bit definition for BKP_DR26 register *****************/
		1150	#define BKP_DR26_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1151
		1152	/***************** Bit definition for BKP_DR27 register *****************/
		1153	#define BKP_DR27_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1154
		1155	/***************** Bit definition for BKP_DR28 register *****************/
		1156	#define BKP_DR28_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1157
		1158	/***************** Bit definition for BKP_DR29 register *****************/
		1159	#define BKP_DR29_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1160
		1161	/***************** Bit definition for BKP_DR30 register *****************/
		1162	#define BKP_DR30_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1163
		1164	/***************** Bit definition for BKP_DR31 register *****************/
		1165	#define BKP_DR31_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1166
		1167	/***************** Bit definition for BKP_DR32 register *****************/
		1168	#define BKP_DR32_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1169
		1170	/***************** Bit definition for BKP_DR33 register *****************/
		1171	#define BKP_DR33_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1172
		1173	/***************** Bit definition for BKP_DR34 register *****************/
		1174	#define BKP_DR34_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1175
		1176	/***************** Bit definition for BKP_DR35 register *****************/
		1177	#define BKP_DR35_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1178
		1179	/***************** Bit definition for BKP_DR36 register *****************/
		1180	#define BKP_DR36_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1181
		1182	/***************** Bit definition for BKP_DR37 register *****************/
		1183	#define BKP_DR37_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1184
		1185	/***************** Bit definition for BKP_DR38 register *****************/
		1186	#define BKP_DR38_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1187
		1188	/***************** Bit definition for BKP_DR39 register *****************/
		1189	#define BKP_DR39_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1190
		1191	/***************** Bit definition for BKP_DR40 register *****************/
		1192	#define BKP_DR40_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1193
		1194	/***************** Bit definition for BKP_DR41 register *****************/
		1195	#define BKP_DR41_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1196
		1197	/***************** Bit definition for BKP_DR42 register *****************/
		1198	#define BKP_DR42_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1199
		1200	#define RTC_BKP_NUMBER 42
		1201
		1202	/**************** Bit definition for BKP_RTCCR register *****************/
		1203	#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /!< Calibration value /
		1204	#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /!< Calibration Clock Output /
		1205	#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /!< Alarm or Second Output Enable /
		1206	#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /!< Alarm or Second Output Selection /
		1207
		1208	/****************** Bit definition for BKP_CR register ******************/
		1209	#define BKP_CR_TPE ((uint32_t)0x00000001) /!< TAMPER pin enable /
		1210	#define BKP_CR_TPAL ((uint32_t)0x00000002) /!< TAMPER pin active level /
		1211
		1212	/***************** Bit definition for BKP_CSR register ******************/
		1213	#define BKP_CSR_CTE ((uint32_t)0x00000001) /!< Clear Tamper event /
		1214	#define BKP_CSR_CTI ((uint32_t)0x00000002) /!< Clear Tamper Interrupt /
		1215	#define BKP_CSR_TPIE ((uint32_t)0x00000004) /!< TAMPER Pin interrupt enable /
		1216	#define BKP_CSR_TEF ((uint32_t)0x00000100) /!< Tamper Event Flag /
		1217	#define BKP_CSR_TIF ((uint32_t)0x00000200) /!< Tamper Interrupt Flag /
		1218
		1219	/******************************************************************************/
		1220	/* */
		1221	/* Reset and Clock Control */
		1222	/* */
		1223	/******************************************************************************/
		1224
		1225	/****************** Bit definition for RCC_CR register ******************/
		1226	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
		1227	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
		1228	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
		1229	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
		1230	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
		1231	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
		1232	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
		1233	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
		1234	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
		1235	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
		1236
		1237	#define RCC_CR_PLL2ON ((uint32_t)0x04000000) /!< PLL2 enable /
		1238	#define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /!< PLL2 clock ready flag /
		1239	#define RCC_CR_PLL3ON ((uint32_t)0x10000000) /!< PLL3 enable /
		1240	#define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /!< PLL3 clock ready flag /
		1241
		1242	/***************** Bit definition for RCC_CFGR register *****************/
		1243	/!< SW configuration /
		1244	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
		1245	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1246	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1247
		1248	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
		1249	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
		1250	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
		1251
		1252	/!< SWS configuration /
		1253	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
		1254	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1255	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1256
		1257	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
		1258	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
		1259	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
		1260
		1261	/!< HPRE configuration /
		1262	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
		1263	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1264	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1265	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
		1266	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
		1267
		1268	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
		1269	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
		1270	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
		1271	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
		1272	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
		1273	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
		1274	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
		1275	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
		1276	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
		1277
		1278	/!< PPRE1 configuration /
		1279	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
		1280	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1281	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1282	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
		1283
		1284	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		1285	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
		1286	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
		1287	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
		1288	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
		1289
		1290	/!< PPRE2 configuration /
		1291	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
		1292	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
		1293	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
		1294	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
		1295
		1296	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		1297	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
		1298	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
		1299	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
		1300	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
		1301
		1302	/!< ADCPPRE configuration /
		1303	#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /!< ADCPRE[1:0] bits (ADC prescaler) /
		1304	#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1305	#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1306
		1307	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
		1308	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
		1309	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
		1310	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
		1311
		1312	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
		1313
		1314	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
		1315
		1316	/!< PLLMUL configuration /
		1317	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
		1318	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1319	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1320	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
		1321	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
		1322
		1323	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
		1324	#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
		1325
		1326	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock 4 */
		1327	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock 5 */
		1328	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock 6 */
		1329	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock 7 */
		1330	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock 8 */
		1331	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock 9 */
		1332	#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /!< PLL input clock 6.5 */
		1333
		1334	#define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /!< USB OTG FS prescaler /
		1335
		1336	/!< MCO configuration /
		1337	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
		1338	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1339	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1340	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
		1341	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
		1342
		1343	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1344	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
		1345	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
		1346	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
		1347	#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
		1348	#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /!< PLL2 clock selected as MCO source/
		1349	#define RCC_CFGR_MCO_PLL3CLK_DIV2 ((uint32_t)0x09000000) /!< PLL3 clock divided by 2 selected as MCO source/
		1350	#define RCC_CFGR_MCO_EXT_HSE ((uint32_t)0x0A000000) /!< XT1 external 3-25 MHz oscillator clock selected as MCO source /
		1351	#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /!< PLL3 clock selected as MCO source /
		1352
		1353	/!<*************** Bit definition for RCC_CIR register ******************/
		1354	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
		1355	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
		1356	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
		1357	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
		1358	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
		1359	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
		1360	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
		1361	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
		1362	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
		1363	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
		1364	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
		1365	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
		1366	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
		1367	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
		1368	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
		1369	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
		1370	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
		1371
		1372	#define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /!< PLL2 Ready Interrupt flag /
		1373	#define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /!< PLL3 Ready Interrupt flag /
		1374	#define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /!< PLL2 Ready Interrupt Enable /
		1375	#define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /!< PLL3 Ready Interrupt Enable /
		1376	#define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /!< PLL2 Ready Interrupt Clear /
		1377	#define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /!< PLL3 Ready Interrupt Clear /
		1378
		1379	/*************** Bit definition for RCC_APB2RSTR register ***************/
		1380	#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /!< Alternate Function I/O reset /
		1381	#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /!< I/O port A reset /
		1382	#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /!< I/O port B reset /
		1383	#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /!< I/O port C reset /
		1384	#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /!< I/O port D reset /
		1385	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC 1 interface reset /
		1386
		1387	#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /!< ADC 2 interface reset /
		1388
		1389	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 Timer reset /
		1390	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI 1 reset /
		1391	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
		1392
		1393
		1394	#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /!< I/O port E reset /
		1395
		1396
		1397
		1398
		1399	/*************** Bit definition for RCC_APB1RSTR register ***************/
		1400	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
		1401	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
		1402	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
		1403	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
		1404	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
		1405
		1406	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /!< CAN1 reset /
		1407
		1408	#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /!< Backup interface reset /
		1409	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
		1410
		1411	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
		1412	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
		1413	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
		1414	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
		1415
		1416
		1417	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /!< Timer 5 reset /
		1418	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
		1419	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
		1420	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI 3 reset /
		1421	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /!< UART 4 reset /
		1422	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /!< UART 5 reset /
		1423
		1424
		1425
		1426	#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /!< CAN2 reset /
		1427
		1428	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC interface reset /
		1429
		1430	/**************** Bit definition for RCC_AHBENR register ****************/
		1431	#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /!< DMA1 clock enable /
		1432	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
		1433	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
		1434	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
		1435
		1436	#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /!< DMA2 clock enable /
		1437
		1438
		1439	#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /!< USB OTG FS clock enable /
		1440	#define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /!< ETHERNET MAC clock enable /
		1441	#define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /!< ETHERNET MAC Tx clock enable /
		1442	#define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /!< ETHERNET MAC Rx clock enable /
		1443
		1444	/**************** Bit definition for RCC_APB2ENR register ***************/
		1445	#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /!< Alternate Function I/O clock enable /
		1446	#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /!< I/O port A clock enable /
		1447	#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /!< I/O port B clock enable /
		1448	#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /!< I/O port C clock enable /
		1449	#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /!< I/O port D clock enable /
		1450	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC 1 interface clock enable /
		1451
		1452	#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /!< ADC 2 interface clock enable /
		1453
		1454	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 Timer clock enable /
		1455	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI 1 clock enable /
		1456	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
		1457
		1458
		1459	#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /!< I/O port E clock enable /
		1460
		1461
		1462
		1463
		1464	/*************** Bit definition for RCC_APB1ENR register ****************/
		1465	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
		1466	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
		1467	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
		1468	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
		1469	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
		1470
		1471	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /!< CAN1 clock enable /
		1472
		1473	#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /!< Backup interface clock enable /
		1474	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
		1475
		1476	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
		1477	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
		1478	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
		1479	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
		1480
		1481
		1482	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /!< Timer 5 clock enable /
		1483	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
		1484	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
		1485	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI 3 clock enable /
		1486	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /!< UART 4 clock enable /
		1487	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /!< UART 5 clock enable /
		1488
		1489
		1490
		1491	#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /!< CAN2 clock enable /
		1492
		1493	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC interface clock enable /
		1494
		1495	/***************** Bit definition for RCC_BDCR register *****************/
		1496	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
		1497	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
		1498	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
		1499
		1500	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
		1501	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1502	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1503
		1504	/!< RTC congiguration /
		1505	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1506	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
		1507	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
		1508	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
		1509
		1510	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
		1511	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
		1512
		1513	/***************** Bit definition for RCC_CSR register ******************/
		1514	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
		1515	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
		1516	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
		1517	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
		1518	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
		1519	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
		1520	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
		1521	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
		1522	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
		1523
		1524	/***************** Bit definition for RCC_AHBRSTR register **************/
		1525	#define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /!< USB OTG FS reset /
		1526	#define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /!< ETHERNET MAC reset /
		1527
		1528	/***************** Bit definition for RCC_CFGR2 register ****************/
		1529	/!< PREDIV1 configuration /
		1530	#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /!< PREDIV1[3:0] bits /
		1531	#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1532	#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1533	#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		1534	#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		1535
		1536	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
		1537	#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /!< PREDIV1 input clock divided by 2 /
		1538	#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /!< PREDIV1 input clock divided by 3 /
		1539	#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /!< PREDIV1 input clock divided by 4 /
		1540	#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /!< PREDIV1 input clock divided by 5 /
		1541	#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /!< PREDIV1 input clock divided by 6 /
		1542	#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /!< PREDIV1 input clock divided by 7 /
		1543	#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /!< PREDIV1 input clock divided by 8 /
		1544	#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /!< PREDIV1 input clock divided by 9 /
		1545	#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /!< PREDIV1 input clock divided by 10 /
		1546	#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /!< PREDIV1 input clock divided by 11 /
		1547	#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /!< PREDIV1 input clock divided by 12 /
		1548	#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /!< PREDIV1 input clock divided by 13 /
		1549	#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /!< PREDIV1 input clock divided by 14 /
		1550	#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /!< PREDIV1 input clock divided by 15 /
		1551	#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /!< PREDIV1 input clock divided by 16 /
		1552
		1553	/!< PREDIV2 configuration /
		1554	#define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /!< PREDIV2[3:0] bits /
		1555	#define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1556	#define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1557	#define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /!< Bit 2 /
		1558	#define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /!< Bit 3 /
		1559
		1560	#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /!< PREDIV2 input clock not divided /
		1561	#define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /!< PREDIV2 input clock divided by 2 /
		1562	#define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /!< PREDIV2 input clock divided by 3 /
		1563	#define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /!< PREDIV2 input clock divided by 4 /
		1564	#define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /!< PREDIV2 input clock divided by 5 /
		1565	#define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /!< PREDIV2 input clock divided by 6 /
		1566	#define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /!< PREDIV2 input clock divided by 7 /
		1567	#define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /!< PREDIV2 input clock divided by 8 /
		1568	#define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /!< PREDIV2 input clock divided by 9 /
		1569	#define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /!< PREDIV2 input clock divided by 10 /
		1570	#define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /!< PREDIV2 input clock divided by 11 /
		1571	#define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /!< PREDIV2 input clock divided by 12 /
		1572	#define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /!< PREDIV2 input clock divided by 13 /
		1573	#define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /!< PREDIV2 input clock divided by 14 /
		1574	#define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /!< PREDIV2 input clock divided by 15 /
		1575	#define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /!< PREDIV2 input clock divided by 16 /
		1576
		1577	/!< PLL2MUL configuration /
		1578	#define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /!< PLL2MUL[3:0] bits /
		1579	#define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1580	#define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1581	#define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /!< Bit 2 /
		1582	#define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /!< Bit 3 /
		1583
		1584	#define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /!< PLL2 input clock 8 */
		1585	#define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /!< PLL2 input clock 9 */
		1586	#define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /!< PLL2 input clock 10 */
		1587	#define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /!< PLL2 input clock 11 */
		1588	#define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /!< PLL2 input clock 12 */
		1589	#define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /!< PLL2 input clock 13 */
		1590	#define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /!< PLL2 input clock 14 */
		1591	#define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /!< PLL2 input clock 16 */
		1592	#define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /!< PLL2 input clock 20 */
		1593
		1594	/!< PLL3MUL configuration /
		1595	#define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /!< PLL3MUL[3:0] bits /
		1596	#define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /!< Bit 0 /
		1597	#define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /!< Bit 1 /
		1598	#define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /!< Bit 2 /
		1599	#define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /!< Bit 3 /
		1600
		1601	#define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /!< PLL3 input clock 8 */
		1602	#define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /!< PLL3 input clock 9 */
		1603	#define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /!< PLL3 input clock 10 */
		1604	#define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /!< PLL3 input clock 11 */
		1605	#define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /!< PLL3 input clock 12 */
		1606	#define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /!< PLL3 input clock 13 */
		1607	#define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /!< PLL3 input clock 14 */
		1608	#define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /!< PLL3 input clock 16 */
		1609	#define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /!< PLL3 input clock 20 */
		1610
		1611	#define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /!< PREDIV1 entry clock source /
		1612	#define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /!< PLL2 selected as PREDIV1 entry clock source /
		1613	#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /!< HSE selected as PREDIV1 entry clock source /
		1614	#define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /!< I2S2 entry clock source /
		1615	#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /!< I2S3 clock source /
		1616
		1617
		1618	/******************************************************************************/
		1619	/* */
		1620	/* General Purpose and Alternate Function I/O */
		1621	/* */
		1622	/******************************************************************************/
		1623
		1624	/***************** Bit definition for GPIO_CRL register *****************/
		1625	#define GPIO_CRL_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
		1626
		1627	#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
		1628	#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1629	#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1630
		1631	#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
		1632	#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1633	#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1634
		1635	#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
		1636	#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1637	#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1638
		1639	#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
		1640	#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /!< Bit 0 /
		1641	#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /!< Bit 1 /
		1642
		1643	#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
		1644	#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /!< Bit 0 /
		1645	#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /!< Bit 1 /
		1646
		1647	#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
		1648	#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /!< Bit 0 /
		1649	#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /!< Bit 1 /
		1650
		1651	#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
		1652	#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1653	#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1654
		1655	#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
		1656	#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /!< Bit 0 /
		1657	#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /!< Bit 1 /
		1658
		1659	#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
		1660
		1661	#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
		1662	#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1663	#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1664
		1665	#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
		1666	#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1667	#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1668
		1669	#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
		1670	#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1671	#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1672
		1673	#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
		1674	#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1675	#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1676
		1677	#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
		1678	#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1679	#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1680
		1681	#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
		1682	#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /!< Bit 0 /
		1683	#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /!< Bit 1 /
		1684
		1685	#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
		1686	#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /!< Bit 0 /
		1687	#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /!< Bit 1 /
		1688
		1689	#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
		1690	#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /!< Bit 0 /
		1691	#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /!< Bit 1 /
		1692
		1693	/***************** Bit definition for GPIO_CRH register *****************/
		1694	#define GPIO_CRH_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
		1695
		1696	#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
		1697	#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1698	#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1699
		1700	#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
		1701	#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1702	#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1703
		1704	#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
		1705	#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1706	#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1707
		1708	#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
		1709	#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /!< Bit 0 /
		1710	#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /!< Bit 1 /
		1711
		1712	#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
		1713	#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /!< Bit 0 /
		1714	#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /!< Bit 1 /
		1715
		1716	#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
		1717	#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /!< Bit 0 /
		1718	#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /!< Bit 1 /
		1719
		1720	#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
		1721	#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1722	#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1723
		1724	#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
		1725	#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /!< Bit 0 /
		1726	#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /!< Bit 1 /
		1727
		1728	#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
		1729
		1730	#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
		1731	#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1732	#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1733
		1734	#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
		1735	#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1736	#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1737
		1738	#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
		1739	#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1740	#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1741
		1742	#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
		1743	#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1744	#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1745
		1746	#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
		1747	#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1748	#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1749
		1750	#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
		1751	#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /!< Bit 0 /
		1752	#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /!< Bit 1 /
		1753
		1754	#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
		1755	#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /!< Bit 0 /
		1756	#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /!< Bit 1 /
		1757
		1758	#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
		1759	#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /!< Bit 0 /
		1760	#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /!< Bit 1 /
		1761
		1762	/!<*************** Bit definition for GPIO_IDR register *****************/
		1763	#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /!< Port input data, bit 0 /
		1764	#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /!< Port input data, bit 1 /
		1765	#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /!< Port input data, bit 2 /
		1766	#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /!< Port input data, bit 3 /
		1767	#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /!< Port input data, bit 4 /
		1768	#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /!< Port input data, bit 5 /
		1769	#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /!< Port input data, bit 6 /
		1770	#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /!< Port input data, bit 7 /
		1771	#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /!< Port input data, bit 8 /
		1772	#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /!< Port input data, bit 9 /
		1773	#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /!< Port input data, bit 10 /
		1774	#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /!< Port input data, bit 11 /
		1775	#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /!< Port input data, bit 12 /
		1776	#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /!< Port input data, bit 13 /
		1777	#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /!< Port input data, bit 14 /
		1778	#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /!< Port input data, bit 15 /
		1779
		1780	/***************** Bit definition for GPIO_ODR register *****************/
		1781	#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /!< Port output data, bit 0 /
		1782	#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /!< Port output data, bit 1 /
		1783	#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /!< Port output data, bit 2 /
		1784	#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /!< Port output data, bit 3 /
		1785	#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /!< Port output data, bit 4 /
		1786	#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /!< Port output data, bit 5 /
		1787	#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /!< Port output data, bit 6 /
		1788	#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /!< Port output data, bit 7 /
		1789	#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /!< Port output data, bit 8 /
		1790	#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /!< Port output data, bit 9 /
		1791	#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /!< Port output data, bit 10 /
		1792	#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /!< Port output data, bit 11 /
		1793	#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /!< Port output data, bit 12 /
		1794	#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /!< Port output data, bit 13 /
		1795	#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /!< Port output data, bit 14 /
		1796	#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /!< Port output data, bit 15 /
		1797
		1798	/**************** Bit definition for GPIO_BSRR register *****************/
		1799	#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /!< Port x Set bit 0 /
		1800	#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /!< Port x Set bit 1 /
		1801	#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /!< Port x Set bit 2 /
		1802	#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /!< Port x Set bit 3 /
		1803	#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /!< Port x Set bit 4 /
		1804	#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /!< Port x Set bit 5 /
		1805	#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /!< Port x Set bit 6 /
		1806	#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /!< Port x Set bit 7 /
		1807	#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /!< Port x Set bit 8 /
		1808	#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /!< Port x Set bit 9 /
		1809	#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /!< Port x Set bit 10 /
		1810	#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /!< Port x Set bit 11 /
		1811	#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /!< Port x Set bit 12 /
		1812	#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /!< Port x Set bit 13 /
		1813	#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /!< Port x Set bit 14 /
		1814	#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /!< Port x Set bit 15 /
		1815
		1816	#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /!< Port x Reset bit 0 /
		1817	#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /!< Port x Reset bit 1 /
		1818	#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /!< Port x Reset bit 2 /
		1819	#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /!< Port x Reset bit 3 /
		1820	#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /!< Port x Reset bit 4 /
		1821	#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /!< Port x Reset bit 5 /
		1822	#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /!< Port x Reset bit 6 /
		1823	#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /!< Port x Reset bit 7 /
		1824	#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /!< Port x Reset bit 8 /
		1825	#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /!< Port x Reset bit 9 /
		1826	#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /!< Port x Reset bit 10 /
		1827	#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /!< Port x Reset bit 11 /
		1828	#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /!< Port x Reset bit 12 /
		1829	#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /!< Port x Reset bit 13 /
		1830	#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /!< Port x Reset bit 14 /
		1831	#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /!< Port x Reset bit 15 /
		1832
		1833	/***************** Bit definition for GPIO_BRR register *****************/
		1834	#define GPIO_BRR_BR0 ((uint32_t)0x0001) /!< Port x Reset bit 0 /
		1835	#define GPIO_BRR_BR1 ((uint32_t)0x0002) /!< Port x Reset bit 1 /
		1836	#define GPIO_BRR_BR2 ((uint32_t)0x0004) /!< Port x Reset bit 2 /
		1837	#define GPIO_BRR_BR3 ((uint32_t)0x0008) /!< Port x Reset bit 3 /
		1838	#define GPIO_BRR_BR4 ((uint32_t)0x0010) /!< Port x Reset bit 4 /
		1839	#define GPIO_BRR_BR5 ((uint32_t)0x0020) /!< Port x Reset bit 5 /
		1840	#define GPIO_BRR_BR6 ((uint32_t)0x0040) /!< Port x Reset bit 6 /
		1841	#define GPIO_BRR_BR7 ((uint32_t)0x0080) /!< Port x Reset bit 7 /
		1842	#define GPIO_BRR_BR8 ((uint32_t)0x0100) /!< Port x Reset bit 8 /
		1843	#define GPIO_BRR_BR9 ((uint32_t)0x0200) /!< Port x Reset bit 9 /
		1844	#define GPIO_BRR_BR10 ((uint32_t)0x0400) /!< Port x Reset bit 10 /
		1845	#define GPIO_BRR_BR11 ((uint32_t)0x0800) /!< Port x Reset bit 11 /
		1846	#define GPIO_BRR_BR12 ((uint32_t)0x1000) /!< Port x Reset bit 12 /
		1847	#define GPIO_BRR_BR13 ((uint32_t)0x2000) /!< Port x Reset bit 13 /
		1848	#define GPIO_BRR_BR14 ((uint32_t)0x4000) /!< Port x Reset bit 14 /
		1849	#define GPIO_BRR_BR15 ((uint32_t)0x8000) /!< Port x Reset bit 15 /
		1850
		1851	/**************** Bit definition for GPIO_LCKR register *****************/
		1852	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /!< Port x Lock bit 0 /
		1853	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /!< Port x Lock bit 1 /
		1854	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /!< Port x Lock bit 2 /
		1855	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /!< Port x Lock bit 3 /
		1856	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /!< Port x Lock bit 4 /
		1857	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /!< Port x Lock bit 5 /
		1858	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /!< Port x Lock bit 6 /
		1859	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /!< Port x Lock bit 7 /
		1860	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /!< Port x Lock bit 8 /
		1861	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /!< Port x Lock bit 9 /
		1862	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /!< Port x Lock bit 10 /
		1863	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /!< Port x Lock bit 11 /
		1864	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /!< Port x Lock bit 12 /
		1865	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /!< Port x Lock bit 13 /
		1866	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /!< Port x Lock bit 14 /
		1867	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /!< Port x Lock bit 15 /
		1868	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /!< Lock key /
		1869
		1870	/----------------------------------------------------------------------------/
		1871
		1872	/**************** Bit definition for AFIO_EVCR register *****************/
		1873	#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /!< PIN[3:0] bits (Pin selection) /
		1874	#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1875	#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1876	#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /!< Bit 2 /
		1877	#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /!< Bit 3 /
		1878
		1879	/!< PIN configuration /
		1880	#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /!< Pin 0 selected /
		1881	#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /!< Pin 1 selected /
		1882	#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /!< Pin 2 selected /
		1883	#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /!< Pin 3 selected /
		1884	#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /!< Pin 4 selected /
		1885	#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /!< Pin 5 selected /
		1886	#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /!< Pin 6 selected /
		1887	#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /!< Pin 7 selected /
		1888	#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /!< Pin 8 selected /
		1889	#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /!< Pin 9 selected /
		1890	#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /!< Pin 10 selected /
		1891	#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /!< Pin 11 selected /
		1892	#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /!< Pin 12 selected /
		1893	#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /!< Pin 13 selected /
		1894	#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /!< Pin 14 selected /
		1895	#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /!< Pin 15 selected /
		1896
		1897	#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /!< PORT[2:0] bits (Port selection) /
		1898	#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1899	#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1900	#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /!< Bit 2 /
		1901
		1902	/!< PORT configuration /
		1903	#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /!< Port A selected /
		1904	#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /!< Port B selected /
		1905	#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /!< Port C selected /
		1906	#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /!< Port D selected /
		1907	#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /!< Port E selected /
		1908
		1909	#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /!< Event Output Enable /
		1910
		1911	/**************** Bit definition for AFIO_MAPR register *****************/
		1912	#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /!< SPI1 remapping /
		1913	#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /!< I2C1 remapping /
		1914	#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /!< USART1 remapping /
		1915	#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /!< USART2 remapping /
		1916
		1917	#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /!< USART3_REMAP[1:0] bits (USART3 remapping) /
		1918	#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1919	#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1920
		1921	/* USART3_REMAP configuration */
		1922	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
		1923	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
		1924	#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
		1925
		1926	#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
		1927	#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1928	#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1929
		1930	/!< TIM1_REMAP configuration /
		1931	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
		1932	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
		1933	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
		1934
		1935	#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
		1936	#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1937	#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1938
		1939	/!< TIM2_REMAP configuration /
		1940	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
		1941	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
		1942	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
		1943	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
		1944
		1945	#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
		1946	#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1947	#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1948
		1949	/!< TIM3_REMAP configuration /
		1950	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
		1951	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
		1952	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
		1953
		1954	#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /!< TIM4_REMAP bit (TIM4 remapping) /
		1955
		1956	#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) /
		1957	#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /!< Bit 0 /
		1958	#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /!< Bit 1 /
		1959
		1960	/!< CAN_REMAP configuration /
		1961	#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /!< CANRX mapped to PA11, CANTX mapped to PA12 /
		1962	#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /!< CANRX mapped to PB8, CANTX mapped to PB9 /
		1963	#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /!< CANRX mapped to PD0, CANTX mapped to PD1 /
		1964
		1965	#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
		1966	#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /!< TIM5 Channel4 Internal Remap /
		1967
		1968	/!< SWJ_CFG configuration /
		1969	#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
		1970	#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1971	#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1972	#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /!< Bit 2 /
		1973
		1974	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
		1975	#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
		1976	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /!< JTAG-DP Disabled and SW-DP Enabled /
		1977	#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /!< JTAG-DP Disabled and SW-DP Disabled /
		1978
		1979	/!< ETH_REMAP configuration /
		1980	#define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /!< SPI3_REMAP bit (Ethernet MAC I/O remapping) /
		1981
		1982	/!< CAN2_REMAP configuration /
		1983	#define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /!< CAN2_REMAP bit (CAN2 I/O remapping) /
		1984
		1985	/!< MII_RMII_SEL configuration /
		1986	#define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /!< MII_RMII_SEL bit (Ethernet MII or RMII selection) /
		1987
		1988	/!< SPI3_REMAP configuration /
		1989	#define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /!< SPI3_REMAP bit (SPI3 remapping) /
		1990
		1991	/!< TIM2ITR1_IREMAP configuration /
		1992	#define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) /
		1993
		1994	/!< PTP_PPS_REMAP configuration /
		1995	#define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) /
		1996
		1997	/*************** Bit definition for AFIO_EXTICR1 register ***************/
		1998	#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
		1999	#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
		2000	#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
		2001	#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
		2002
		2003	/!< EXTI0 configuration /
		2004	#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
		2005	#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
		2006	#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
		2007	#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
		2008	#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
		2009	#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
		2010	#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /!< PG[0] pin /
		2011
		2012	/!< EXTI1 configuration /
		2013	#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
		2014	#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
		2015	#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
		2016	#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
		2017	#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
		2018	#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
		2019	#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /!< PG[1] pin /
		2020
		2021	/!< EXTI2 configuration /
		2022	#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
		2023	#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
		2024	#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
		2025	#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
		2026	#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
		2027	#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
		2028	#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /!< PG[2] pin /
		2029
		2030	/!< EXTI3 configuration /
		2031	#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
		2032	#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
		2033	#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
		2034	#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
		2035	#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
		2036	#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
		2037	#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /!< PG[3] pin /
		2038
		2039	/*************** Bit definition for AFIO_EXTICR2 register ***************/
		2040	#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
		2041	#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
		2042	#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
		2043	#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
		2044
		2045	/!< EXTI4 configuration /
		2046	#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
		2047	#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
		2048	#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
		2049	#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
		2050	#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
		2051	#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
		2052	#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /!< PG[4] pin /
		2053
		2054	/* EXTI5 configuration */
		2055	#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
		2056	#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
		2057	#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
		2058	#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
		2059	#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
		2060	#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
		2061	#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /!< PG[5] pin /
		2062
		2063	/!< EXTI6 configuration /
		2064	#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
		2065	#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
		2066	#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
		2067	#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
		2068	#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
		2069	#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
		2070	#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /!< PG[6] pin /
		2071
		2072	/!< EXTI7 configuration /
		2073	#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
		2074	#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
		2075	#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
		2076	#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
		2077	#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
		2078	#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
		2079	#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /!< PG[7] pin /
		2080
		2081	/*************** Bit definition for AFIO_EXTICR3 register ***************/
		2082	#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
		2083	#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
		2084	#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
		2085	#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
		2086
		2087	/!< EXTI8 configuration /
		2088	#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
		2089	#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
		2090	#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
		2091	#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
		2092	#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
		2093	#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!< PF[8] pin /
		2094	#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /!< PG[8] pin /
		2095
		2096	/!< EXTI9 configuration /
		2097	#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
		2098	#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
		2099	#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
		2100	#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
		2101	#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
		2102	#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
		2103	#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /!< PG[9] pin /
		2104
		2105	/!< EXTI10 configuration /
		2106	#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
		2107	#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
		2108	#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
		2109	#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
		2110	#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PE[10] pin /
		2111	#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
		2112	#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /!< PG[10] pin /
		2113
		2114	/!< EXTI11 configuration /
		2115	#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
		2116	#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
		2117	#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
		2118	#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
		2119	#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
		2120	#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!< PF[11] pin /
		2121	#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /!< PG[11] pin /
		2122
		2123	/*************** Bit definition for AFIO_EXTICR4 register ***************/
		2124	#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
		2125	#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
		2126	#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
		2127	#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
		2128
		2129	/* EXTI12 configuration */
		2130	#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
		2131	#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
		2132	#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
		2133	#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
		2134	#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
		2135	#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!< PF[12] pin /
		2136	#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /!< PG[12] pin /
		2137
		2138	/* EXTI13 configuration */
		2139	#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
		2140	#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
		2141	#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
		2142	#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
		2143	#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
		2144	#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!< PF[13] pin /
		2145	#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /!< PG[13] pin /
		2146
		2147	/!< EXTI14 configuration /
		2148	#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
		2149	#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
		2150	#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
		2151	#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
		2152	#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
		2153	#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!< PF[14] pin /
		2154	#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /!< PG[14] pin /
		2155
		2156	/!< EXTI15 configuration /
		2157	#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
		2158	#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
		2159	#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
		2160	#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
		2161	#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
		2162	#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!< PF[15] pin /
		2163	#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /!< PG[15] pin /
		2164
		2165	/**************** Bit definition for AFIO_MAPR2 register ****************/
		2166
		2167
		2168
		2169	/******************************************************************************/
		2170	/* */
		2171	/* SystemTick */
		2172	/* */
		2173	/******************************************************************************/
		2174
		2175	/*************** Bit definition for SysTick_CTRL register ***************/
		2176	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
		2177	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
		2178	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
		2179	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
		2180
		2181	/*************** Bit definition for SysTick_LOAD register ***************/
		2182	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
		2183
		2184	/*************** Bit definition for SysTick_VAL register ****************/
		2185	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
		2186
		2187	/*************** Bit definition for SysTick_CALIB register **************/
		2188	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
		2189	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
		2190	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
		2191
		2192	/******************************************************************************/
		2193	/* */
		2194	/* Nested Vectored Interrupt Controller */
		2195	/* */
		2196	/******************************************************************************/
		2197
		2198	/**************** Bit definition for NVIC_ISER register *****************/
		2199	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
		2200	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
		2201	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
		2202	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
		2203	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
		2204	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
		2205	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
		2206	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
		2207	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
		2208	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
		2209	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
		2210	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
		2211	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
		2212	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
		2213	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
		2214	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
		2215	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
		2216	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
		2217	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
		2218	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
		2219	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
		2220	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
		2221	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
		2222	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
		2223	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
		2224	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
		2225	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
		2226	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
		2227	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
		2228	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
		2229	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
		2230	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
		2231	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
		2232
		2233	/**************** Bit definition for NVIC_ICER register *****************/
		2234	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
		2235	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
		2236	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
		2237	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
		2238	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
		2239	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
		2240	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
		2241	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
		2242	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
		2243	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
		2244	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
		2245	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
		2246	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
		2247	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
		2248	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
		2249	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
		2250	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
		2251	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
		2252	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
		2253	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
		2254	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
		2255	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
		2256	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
		2257	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
		2258	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
		2259	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
		2260	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
		2261	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
		2262	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
		2263	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
		2264	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
		2265	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
		2266	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
		2267
		2268	/**************** Bit definition for NVIC_ISPR register *****************/
		2269	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
		2270	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
		2271	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
		2272	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
		2273	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
		2274	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
		2275	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
		2276	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
		2277	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
		2278	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
		2279	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
		2280	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
		2281	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
		2282	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
		2283	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
		2284	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
		2285	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
		2286	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
		2287	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
		2288	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
		2289	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
		2290	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
		2291	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
		2292	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
		2293	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
		2294	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
		2295	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
		2296	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
		2297	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
		2298	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
		2299	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
		2300	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
		2301	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
		2302
		2303	/**************** Bit definition for NVIC_ICPR register *****************/
		2304	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
		2305	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
		2306	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
		2307	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
		2308	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
		2309	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
		2310	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
		2311	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
		2312	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
		2313	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
		2314	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
		2315	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
		2316	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
		2317	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
		2318	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
		2319	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
		2320	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
		2321	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
		2322	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
		2323	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
		2324	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
		2325	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
		2326	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
		2327	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
		2328	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
		2329	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
		2330	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
		2331	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
		2332	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
		2333	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
		2334	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
		2335	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
		2336	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
		2337
		2338	/**************** Bit definition for NVIC_IABR register *****************/
		2339	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
		2340	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
		2341	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
		2342	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
		2343	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
		2344	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
		2345	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
		2346	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
		2347	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
		2348	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
		2349	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
		2350	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
		2351	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
		2352	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
		2353	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
		2354	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
		2355	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
		2356	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
		2357	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
		2358	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
		2359	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
		2360	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
		2361	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
		2362	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
		2363	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
		2364	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
		2365	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
		2366	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
		2367	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
		2368	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
		2369	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
		2370	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
		2371	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
		2372
		2373	/**************** Bit definition for NVIC_PRI0 register *****************/
		2374	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
		2375	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
		2376	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
		2377	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
		2378
		2379	/**************** Bit definition for NVIC_PRI1 register *****************/
		2380	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
		2381	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
		2382	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
		2383	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
		2384
		2385	/**************** Bit definition for NVIC_PRI2 register *****************/
		2386	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
		2387	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
		2388	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
		2389	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
		2390
		2391	/**************** Bit definition for NVIC_PRI3 register *****************/
		2392	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
		2393	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
		2394	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
		2395	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
		2396
		2397	/**************** Bit definition for NVIC_PRI4 register *****************/
		2398	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
		2399	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
		2400	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
		2401	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
		2402
		2403	/**************** Bit definition for NVIC_PRI5 register *****************/
		2404	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
		2405	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
		2406	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
		2407	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
		2408
		2409	/**************** Bit definition for NVIC_PRI6 register *****************/
		2410	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
		2411	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
		2412	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
		2413	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
		2414
		2415	/**************** Bit definition for NVIC_PRI7 register *****************/
		2416	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
		2417	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
		2418	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
		2419	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
		2420
		2421	/**************** Bit definition for SCB_CPUID register *****************/
		2422	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
		2423	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
		2424	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
		2425	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
		2426	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
		2427
		2428	/***************** Bit definition for SCB_ICSR register *****************/
		2429	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
		2430	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
		2431	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
		2432	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
		2433	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
		2434	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
		2435	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
		2436	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
		2437	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
		2438	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
		2439
		2440	/***************** Bit definition for SCB_VTOR register *****************/
		2441	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
		2442	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
		2443
		2444	/!<************** Bit definition for SCB_AIRCR register *****************/
		2445	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
		2446	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
		2447	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
		2448
		2449	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
		2450	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2451	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2452	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
		2453
		2454	/* prority group configuration */
		2455	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
		2456	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
		2457	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
		2458	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
		2459	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
		2460	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
		2461	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
		2462	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
		2463
		2464	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
		2465	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
		2466
		2467	/***************** Bit definition for SCB_SCR register ******************/
		2468	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
		2469	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
		2470	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
		2471
		2472	/****************** Bit definition for SCB_CCR register *****************/
		2473	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
		2474	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
		2475	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
		2476	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
		2477	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
		2478	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
		2479
		2480	/***************** Bit definition for SCB_SHPR register ******************/
		2481	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
		2482	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
		2483	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
		2484	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
		2485
		2486	/**************** Bit definition for SCB_SHCSR register *****************/
		2487	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
		2488	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
		2489	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
		2490	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
		2491	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
		2492	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
		2493	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
		2494	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
		2495	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
		2496	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
		2497	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
		2498	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
		2499	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
		2500	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
		2501
		2502	/***************** Bit definition for SCB_CFSR register *****************/
		2503	/!< MFSR /
		2504	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
		2505	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
		2506	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
		2507	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
		2508	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
		2509	/!< BFSR /
		2510	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
		2511	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
		2512	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
		2513	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
		2514	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
		2515	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
		2516	/!< UFSR /
		2517	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to execute an undefined instruction /
		2518	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
		2519	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
		2520	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
		2521	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
		2522	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
		2523
		2524	/***************** Bit definition for SCB_HFSR register *****************/
		2525	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
		2526	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
		2527	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
		2528
		2529	/***************** Bit definition for SCB_DFSR register *****************/
		2530	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
		2531	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
		2532	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
		2533	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
		2534	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
		2535
		2536	/***************** Bit definition for SCB_MMFAR register ****************/
		2537	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
		2538
		2539	/***************** Bit definition for SCB_BFAR register *****************/
		2540	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
		2541
		2542	/***************** Bit definition for SCB_afsr register *****************/
		2543	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
		2544
		2545	/******************************************************************************/
		2546	/* */
		2547	/* External Interrupt/Event Controller */
		2548	/* */
		2549	/******************************************************************************/
		2550
		2551	/***************** Bit definition for EXTI_IMR register *****************/
		2552	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
		2553	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
		2554	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
		2555	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
		2556	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
		2557	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
		2558	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
		2559	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
		2560	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
		2561	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
		2562	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
		2563	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
		2564	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
		2565	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
		2566	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
		2567	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
		2568	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
		2569	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
		2570	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
		2571	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
		2572
		2573	/***************** Bit definition for EXTI_EMR register *****************/
		2574	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
		2575	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
		2576	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
		2577	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
		2578	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
		2579	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
		2580	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
		2581	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
		2582	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
		2583	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
		2584	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
		2585	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
		2586	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
		2587	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
		2588	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
		2589	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
		2590	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
		2591	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
		2592	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
		2593	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
		2594
		2595	/**************** Bit definition for EXTI_RTSR register *****************/
		2596	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
		2597	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
		2598	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
		2599	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
		2600	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
		2601	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
		2602	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
		2603	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
		2604	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
		2605	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
		2606	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
		2607	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
		2608	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
		2609	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
		2610	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
		2611	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
		2612	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
		2613	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
		2614	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
		2615	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
		2616
		2617	/**************** Bit definition for EXTI_FTSR register *****************/
		2618	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
		2619	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
		2620	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
		2621	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
		2622	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
		2623	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
		2624	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
		2625	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
		2626	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
		2627	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
		2628	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
		2629	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
		2630	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
		2631	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
		2632	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
		2633	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
		2634	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
		2635	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
		2636	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
		2637	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
		2638
		2639	/**************** Bit definition for EXTI_SWIER register ****************/
		2640	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
		2641	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
		2642	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
		2643	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
		2644	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
		2645	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
		2646	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
		2647	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
		2648	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
		2649	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
		2650	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
		2651	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
		2652	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
		2653	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
		2654	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
		2655	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
		2656	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
		2657	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
		2658	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
		2659	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
		2660
		2661	/***************** Bit definition for EXTI_PR register ******************/
		2662	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
		2663	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
		2664	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
		2665	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
		2666	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
		2667	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
		2668	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
		2669	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
		2670	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
		2671	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
		2672	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
		2673	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
		2674	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
		2675	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
		2676	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
		2677	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
		2678	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
		2679	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
		2680	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
		2681	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
		2682
		2683	/******************************************************************************/
		2684	/* */
		2685	/* DMA Controller */
		2686	/* */
		2687	/******************************************************************************/
		2688
		2689	/***************** Bit definition for DMA_ISR register ******************/
		2690	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
		2691	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
		2692	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
		2693	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
		2694	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
		2695	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
		2696	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
		2697	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
		2698	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
		2699	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
		2700	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
		2701	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
		2702	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
		2703	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
		2704	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
		2705	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
		2706	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
		2707	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
		2708	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
		2709	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
		2710	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
		2711	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
		2712	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
		2713	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
		2714	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
		2715	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
		2716	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
		2717	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
		2718
		2719	/***************** Bit definition for DMA_IFCR register *****************/
		2720	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
		2721	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
		2722	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
		2723	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
		2724	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
		2725	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
		2726	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
		2727	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
		2728	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
		2729	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
		2730	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
		2731	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
		2732	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
		2733	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
		2734	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
		2735	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
		2736	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
		2737	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
		2738	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
		2739	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
		2740	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
		2741	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
		2742	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
		2743	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
		2744	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
		2745	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
		2746	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
		2747	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
		2748
		2749	/***************** Bit definition for DMA_CCR register *****************/
		2750	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
		2751	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
		2752	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
		2753	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
		2754	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
		2755	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
		2756	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
		2757	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
		2758
		2759	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
		2760	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2761	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2762
		2763	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
		2764	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2765	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2766
		2767	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level) /
		2768	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2769	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2770
		2771	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
		2772
		2773	/**************** Bit definition for DMA_CNDTR register ****************/
		2774	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
		2775
		2776	/**************** Bit definition for DMA_CPAR register *****************/
		2777	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
		2778
		2779	/**************** Bit definition for DMA_CMAR register *****************/
		2780	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
		2781
		2782	/******************************************************************************/
		2783	/* */
		2784	/* Analog to Digital Converter */
		2785	/* */
		2786	/******************************************************************************/
		2787
		2788	/****************** Bit definition for ADC_SR register ******************/
		2789	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
		2790	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
		2791	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
		2792	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
		2793	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
		2794
		2795	/***************** Bit definition for ADC_CR1 register ******************/
		2796	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
		2797	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2798	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2799	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2800	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2801	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2802
		2803	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
		2804	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
		2805	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
		2806	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
		2807	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
		2808	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
		2809	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
		2810	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
		2811
		2812	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
		2813	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
		2814	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
		2815	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
		2816
		2817	#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /!< DUALMOD[3:0] bits (Dual mode selection) /
		2818	#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /!< Bit 0 /
		2819	#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /!< Bit 1 /
		2820	#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /!< Bit 2 /
		2821	#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /!< Bit 3 /
		2822
		2823	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
		2824	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
		2825
		2826
		2827	/***************** Bit definition for ADC_CR2 register ******************/
		2828	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
		2829	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
		2830	#define ADC_CR2_CAL ((uint32_t)0x00000004) /!< A/D Calibration /
		2831	#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /!< Reset Calibration /
		2832	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
		2833	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
		2834
		2835	#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /!< JEXTSEL[2:0] bits (External event select for injected group) /
		2836	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2837	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2838	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2839
		2840	#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /!< External Trigger Conversion mode for injected channels /
		2841
		2842	#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
		2843	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /!< Bit 0 /
		2844	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /!< Bit 1 /
		2845	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /!< Bit 2 /
		2846
		2847	#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /!< External Trigger Conversion mode for regular channels /
		2848	#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /!< Start Conversion of injected channels /
		2849	#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /!< Start Conversion of regular channels /
		2850	#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
		2851
		2852	/**************** Bit definition for ADC_SMPR1 register *****************/
		2853	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
		2854	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2855	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2856	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2857
		2858	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
		2859	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2860	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2861	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2862
		2863	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
		2864	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2865	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2866	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
		2867
		2868	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
		2869	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
		2870	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
		2871	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
		2872
		2873	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
		2874	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2875	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2876	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2877
		2878	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 15 Sample time selection) /
		2879	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2880	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2881	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2882
		2883	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
		2884	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
		2885	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
		2886	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
		2887
		2888	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
		2889	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
		2890	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
		2891	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
		2892
		2893	/**************** Bit definition for ADC_SMPR2 register *****************/
		2894	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
		2895	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2896	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2897	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2898
		2899	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
		2900	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2901	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2902	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2903
		2904	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
		2905	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2906	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2907	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
		2908
		2909	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
		2910	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
		2911	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
		2912	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
		2913
		2914	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
		2915	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2916	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2917	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2918
		2919	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
		2920	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2921	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2922	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2923
		2924	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
		2925	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
		2926	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
		2927	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
		2928
		2929	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
		2930	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
		2931	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
		2932	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
		2933
		2934	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
		2935	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
		2936	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
		2937	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
		2938
		2939	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
		2940	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
		2941	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
		2942	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
		2943
		2944	/**************** Bit definition for ADC_JOFR1 register *****************/
		2945	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
		2946
		2947	/**************** Bit definition for ADC_JOFR2 register *****************/
		2948	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
		2949
		2950	/**************** Bit definition for ADC_JOFR3 register *****************/
		2951	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
		2952
		2953	/**************** Bit definition for ADC_JOFR4 register *****************/
		2954	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
		2955
		2956	/***************** Bit definition for ADC_HTR register ******************/
		2957	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
		2958
		2959	/***************** Bit definition for ADC_LTR register ******************/
		2960	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
		2961
		2962	/***************** Bit definition for ADC_SQR1 register *****************/
		2963	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
		2964	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2965	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2966	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2967	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2968	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2969
		2970	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
		2971	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2972	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2973	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2974	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2975	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2976
		2977	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
		2978	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2979	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2980	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2981	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2982	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2983
		2984	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
		2985	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2986	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2987	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2988	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2989	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2990
		2991	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!< L[3:0] bits (Regular channel sequence length) /
		2992	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2993	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2994	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2995	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2996
		2997	/***************** Bit definition for ADC_SQR2 register *****************/
		2998	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
		2999	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3000	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3001	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3002	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3003	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
		3004
		3005	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
		3006	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
		3007	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
		3008	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
		3009	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
		3010	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
		3011
		3012	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
		3013	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3014	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3015	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3016	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3017	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3018
		3019	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
		3020	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
		3021	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
		3022	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
		3023	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
		3024	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
		3025
		3026	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
		3027	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
		3028	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
		3029	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
		3030	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
		3031	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
		3032
		3033	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
		3034	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
		3035	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
		3036	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
		3037	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
		3038	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
		3039
		3040	/***************** Bit definition for ADC_SQR3 register *****************/
		3041	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
		3042	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3043	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3044	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3045	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3046	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
		3047
		3048	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
		3049	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
		3050	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
		3051	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
		3052	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
		3053	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
		3054
		3055	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
		3056	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3057	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3058	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3059	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3060	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3061
		3062	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
		3063	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
		3064	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
		3065	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
		3066	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
		3067	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
		3068
		3069	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
		3070	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
		3071	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
		3072	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
		3073	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
		3074	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
		3075
		3076	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
		3077	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
		3078	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
		3079	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
		3080	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
		3081	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
		3082
		3083	/***************** Bit definition for ADC_JSQR register *****************/
		3084	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
		3085	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3086	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3087	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3088	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3089	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
		3090
		3091	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
		3092	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
		3093	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
		3094	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
		3095	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
		3096	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
		3097
		3098	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
		3099	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3100	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3101	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3102	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3103	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3104
		3105	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
		3106	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
		3107	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
		3108	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
		3109	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
		3110	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
		3111
		3112	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
		3113	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
		3114	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
		3115
		3116	/***************** Bit definition for ADC_JDR1 register *****************/
		3117	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		3118
		3119	/***************** Bit definition for ADC_JDR2 register *****************/
		3120	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		3121
		3122	/***************** Bit definition for ADC_JDR3 register *****************/
		3123	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		3124
		3125	/***************** Bit definition for ADC_JDR4 register *****************/
		3126	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		3127
		3128	/****************** Bit definition for ADC_DR register ******************/
		3129	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
		3130	#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /!< ADC2 data /
		3131	/******************************************************************************/
		3132	/* */
		3133	/* Digital to Analog Converter */
		3134	/* */
		3135	/******************************************************************************/
		3136
		3137	/****************** Bit definition for DAC_CR register ******************/
		3138	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
		3139	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
		3140	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
		3141
		3142	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
		3143	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
		3144	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
		3145	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
		3146
		3147	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
		3148	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
		3149	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
		3150
		3151	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
		3152	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
		3153	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
		3154	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
		3155	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
		3156
		3157	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
		3158	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
		3159	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
		3160	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
		3161
		3162	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
		3163	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
		3164	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
		3165	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
		3166
		3167	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
		3168	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
		3169	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
		3170
		3171	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
		3172	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
		3173	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
		3174	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
		3175	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
		3176
		3177	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
		3178
		3179
		3180	/*************** Bit definition for DAC_SWTRIGR register ****************/
		3181	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!< DAC channel1 software trigger /
		3182	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!< DAC channel2 software trigger /
		3183
		3184	/*************** Bit definition for DAC_DHR12R1 register ****************/
		3185	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
		3186
		3187	/*************** Bit definition for DAC_DHR12L1 register ****************/
		3188	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
		3189
		3190	/**************** Bit definition for DAC_DHR8R1 register ****************/
		3191	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
		3192
		3193	/*************** Bit definition for DAC_DHR12R2 register ****************/
		3194	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!< DAC channel2 12-bit Right aligned data /
		3195
		3196	/*************** Bit definition for DAC_DHR12L2 register ****************/
		3197	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!< DAC channel2 12-bit Left aligned data /
		3198
		3199	/**************** Bit definition for DAC_DHR8R2 register ****************/
		3200	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!< DAC channel2 8-bit Right aligned data /
		3201
		3202	/*************** Bit definition for DAC_DHR12RD register ****************/
		3203	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
		3204	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!< DAC channel2 12-bit Right aligned data /
		3205
		3206	/*************** Bit definition for DAC_DHR12LD register ****************/
		3207	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
		3208	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!< DAC channel2 12-bit Left aligned data /
		3209
		3210	/**************** Bit definition for DAC_DHR8RD register ****************/
		3211	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
		3212	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!< DAC channel2 8-bit Right aligned data /
		3213
		3214	/***************** Bit definition for DAC_DOR1 register *****************/
		3215	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!< DAC channel1 data output /
		3216
		3217	/***************** Bit definition for DAC_DOR2 register *****************/
		3218	#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /!< DAC channel2 data output /
		3219
		3220
		3221
		3222	/*****************************************************************************/
		3223	/* */
		3224	/* Timers (TIM) */
		3225	/* */
		3226	/*****************************************************************************/
		3227	/***************** Bit definition for TIM_CR1 register *****************/
		3228	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
		3229	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
		3230	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
		3231	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
		3232	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
		3233
		3234	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
		3235	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
		3236	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
		3237
		3238	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
		3239
		3240	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
		3241	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3242	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3243
		3244	/***************** Bit definition for TIM_CR2 register *****************/
		3245	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
		3246	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
		3247	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
		3248
		3249	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
		3250	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3251	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3252	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3253
		3254	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
		3255	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
		3256	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
		3257	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
		3258	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
		3259	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
		3260	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
		3261	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
		3262
		3263	/***************** Bit definition for TIM_SMCR register ****************/
		3264	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
		3265	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3266	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3267	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
		3268
		3269	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
		3270
		3271	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
		3272	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3273	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3274	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3275
		3276	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
		3277
		3278	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
		3279	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3280	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3281	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
		3282	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
		3283
		3284	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
		3285	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3286	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3287
		3288	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
		3289	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
		3290
		3291	/***************** Bit definition for TIM_DIER register ****************/
		3292	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
		3293	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
		3294	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
		3295	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
		3296	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
		3297	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
		3298	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
		3299	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
		3300	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
		3301	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
		3302	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
		3303	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
		3304	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
		3305	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
		3306	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
		3307
		3308	/****************** Bit definition for TIM_SR register *****************/
		3309	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
		3310	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
		3311	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
		3312	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
		3313	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
		3314	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
		3315	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
		3316	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
		3317	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
		3318	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
		3319	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
		3320	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
		3321
		3322	/***************** Bit definition for TIM_EGR register *****************/
		3323	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
		3324	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
		3325	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
		3326	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
		3327	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
		3328	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
		3329	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
		3330	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
		3331
		3332	/**************** Bit definition for TIM_CCMR1 register ****************/
		3333	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
		3334	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3335	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3336
		3337	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
		3338	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
		3339
		3340	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
		3341	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3342	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3343	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3344
		3345	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
		3346
		3347	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
		3348	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3349	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3350
		3351	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
		3352	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
		3353
		3354	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
		3355	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3356	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3357	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3358
		3359	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
		3360
		3361	/---------------------------------------------------------------------------/
		3362
		3363	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
		3364	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
		3365	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
		3366
		3367	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
		3368	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3369	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3370	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3371	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
		3372
		3373	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
		3374	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
		3375	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
		3376
		3377	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
		3378	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3379	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3380	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3381	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
		3382
		3383	/**************** Bit definition for TIM_CCMR2 register ****************/
		3384	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
		3385	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3386	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3387
		3388	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
		3389	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
		3390
		3391	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
		3392	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3393	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3394	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3395
		3396	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
		3397
		3398	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
		3399	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3400	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3401
		3402	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
		3403	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
		3404
		3405	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
		3406	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3407	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3408	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3409
		3410	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
		3411
		3412	/---------------------------------------------------------------------------/
		3413
		3414	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
		3415	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
		3416	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
		3417
		3418	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
		3419	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3420	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3421	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3422	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
		3423
		3424	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
		3425	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
		3426	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
		3427
		3428	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
		3429	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3430	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3431	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3432	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
		3433
		3434	/***************** Bit definition for TIM_CCER register ****************/
		3435	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
		3436	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
		3437	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
		3438	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
		3439	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
		3440	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
		3441	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
		3442	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
		3443	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
		3444	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
		3445	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
		3446	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
		3447	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
		3448	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
		3449	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
		3450
		3451	/***************** Bit definition for TIM_CNT register *****************/
		3452	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
		3453
		3454	/***************** Bit definition for TIM_PSC register *****************/
		3455	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
		3456
		3457	/***************** Bit definition for TIM_ARR register *****************/
		3458	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
		3459
		3460	/***************** Bit definition for TIM_RCR register *****************/
		3461	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
		3462
		3463	/***************** Bit definition for TIM_CCR1 register ****************/
		3464	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
		3465
		3466	/***************** Bit definition for TIM_CCR2 register ****************/
		3467	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
		3468
		3469	/***************** Bit definition for TIM_CCR3 register ****************/
		3470	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
		3471
		3472	/***************** Bit definition for TIM_CCR4 register ****************/
		3473	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
		3474
		3475	/***************** Bit definition for TIM_BDTR register ****************/
		3476	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
		3477	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3478	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3479	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
		3480	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
		3481	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
		3482	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
		3483	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
		3484	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
		3485
		3486	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
		3487	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3488	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3489
		3490	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
		3491	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
		3492	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
		3493	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
		3494	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
		3495	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
		3496
		3497	/***************** Bit definition for TIM_DCR register *****************/
		3498	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
		3499	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3500	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3501	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
		3502	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
		3503	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
		3504
		3505	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
		3506	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3507	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3508	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
		3509	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
		3510	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
		3511
		3512	/***************** Bit definition for TIM_DMAR register ****************/
		3513	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
		3514
		3515	/***************** Bit definition for TIM_OR register ******************/
		3516
		3517	/******************************************************************************/
		3518	/* */
		3519	/* Real-Time Clock */
		3520	/* */
		3521	/******************************************************************************/
		3522
		3523	/***************** Bit definition for RTC_CRH register ******************/
		3524	#define RTC_CRH_SECIE ((uint32_t)0x00000001) /!< Second Interrupt Enable /
		3525	#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /!< Alarm Interrupt Enable /
		3526	#define RTC_CRH_OWIE ((uint32_t)0x00000004) /!< OverfloW Interrupt Enable /
		3527
		3528	/***************** Bit definition for RTC_CRL register ******************/
		3529	#define RTC_CRL_SECF ((uint32_t)0x00000001) /!< Second Flag /
		3530	#define RTC_CRL_ALRF ((uint32_t)0x00000002) /!< Alarm Flag /
		3531	#define RTC_CRL_OWF ((uint32_t)0x00000004) /!< OverfloW Flag /
		3532	#define RTC_CRL_RSF ((uint32_t)0x00000008) /!< Registers Synchronized Flag /
		3533	#define RTC_CRL_CNF ((uint32_t)0x00000010) /!< Configuration Flag /
		3534	#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /!< RTC operation OFF /
		3535
		3536	/***************** Bit definition for RTC_PRLH register *****************/
		3537	#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /!< RTC Prescaler Reload Value High /
		3538
		3539	/***************** Bit definition for RTC_PRLL register *****************/
		3540	#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /!< RTC Prescaler Reload Value Low /
		3541
		3542	/***************** Bit definition for RTC_DIVH register *****************/
		3543	#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /!< RTC Clock Divider High /
		3544
		3545	/***************** Bit definition for RTC_DIVL register *****************/
		3546	#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /!< RTC Clock Divider Low /
		3547
		3548	/***************** Bit definition for RTC_CNTH register *****************/
		3549	#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter High /
		3550
		3551	/***************** Bit definition for RTC_CNTL register *****************/
		3552	#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter Low /
		3553
		3554	/***************** Bit definition for RTC_ALRH register *****************/
		3555	#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm High /
		3556
		3557	/***************** Bit definition for RTC_ALRL register *****************/
		3558	#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm Low /
		3559
		3560	/******************************************************************************/
		3561	/* */
		3562	/* Independent WATCHDOG (IWDG) */
		3563	/* */
		3564	/******************************************************************************/
		3565
		3566	/***************** Bit definition for IWDG_KR register ******************/
		3567	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!< Key value (write only, read 0000h) /
		3568
		3569	/***************** Bit definition for IWDG_PR register ******************/
		3570	#define IWDG_PR_PR ((uint32_t)0x00000007) /!< PR[2:0] (Prescaler divider) /
		3571	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3572	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3573	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3574
		3575	/***************** Bit definition for IWDG_RLR register *****************/
		3576	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!< Watchdog counter reload value /
		3577
		3578	/***************** Bit definition for IWDG_SR register ******************/
		3579	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
		3580	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
		3581
		3582	/******************************************************************************/
		3583	/* */
		3584	/* Window WATCHDOG */
		3585	/* */
		3586	/******************************************************************************/
		3587
		3588	/***************** Bit definition for WWDG_CR register ******************/
		3589	#define WWDG_CR_T ((uint32_t)0x0000007F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
		3590	#define WWDG_CR_T0 ((uint32_t)0x00000001) /!< Bit 0 /
		3591	#define WWDG_CR_T1 ((uint32_t)0x00000002) /!< Bit 1 /
		3592	#define WWDG_CR_T2 ((uint32_t)0x00000004) /!< Bit 2 /
		3593	#define WWDG_CR_T3 ((uint32_t)0x00000008) /!< Bit 3 /
		3594	#define WWDG_CR_T4 ((uint32_t)0x00000010) /!< Bit 4 /
		3595	#define WWDG_CR_T5 ((uint32_t)0x00000020) /!< Bit 5 /
		3596	#define WWDG_CR_T6 ((uint32_t)0x00000040) /!< Bit 6 /
		3597
		3598	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!< Activation bit /
		3599
		3600	/***************** Bit definition for WWDG_CFR register *****************/
		3601	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!< W[6:0] bits (7-bit window value) /
		3602	#define WWDG_CFR_W0 ((uint32_t)0x00000001) /!< Bit 0 /
		3603	#define WWDG_CFR_W1 ((uint32_t)0x00000002) /!< Bit 1 /
		3604	#define WWDG_CFR_W2 ((uint32_t)0x00000004) /!< Bit 2 /
		3605	#define WWDG_CFR_W3 ((uint32_t)0x00000008) /!< Bit 3 /
		3606	#define WWDG_CFR_W4 ((uint32_t)0x00000010) /!< Bit 4 /
		3607	#define WWDG_CFR_W5 ((uint32_t)0x00000020) /!< Bit 5 /
		3608	#define WWDG_CFR_W6 ((uint32_t)0x00000040) /!< Bit 6 /
		3609
		3610	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!< WDGTB[1:0] bits (Timer Base) /
		3611	#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /!< Bit 0 /
		3612	#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /!< Bit 1 /
		3613
		3614	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!< Early Wakeup Interrupt /
		3615
		3616	/***************** Bit definition for WWDG_SR register ******************/
		3617	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!< Early Wakeup Interrupt Flag /
		3618
		3619
		3620	/******************************************************************************/
		3621	/* */
		3622	/* SD host Interface */
		3623	/* */
		3624	/******************************************************************************/
		3625
		3626	/**************** Bit definition for SDIO_POWER register ****************/
		3627	#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /!< PWRCTRL[1:0] bits (Power supply control bits) /
		3628	#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /!< Bit 0 /
		3629	#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /!< Bit 1 /
		3630
		3631	/**************** Bit definition for SDIO_CLKCR register ****************/
		3632	#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /!< Clock divide factor /
		3633	#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /!< Clock enable bit /
		3634	#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /!< Power saving configuration bit /
		3635	#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /!< Clock divider bypass enable bit /
		3636
		3637	#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
		3638	#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /!< Bit 0 /
		3639	#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /!< Bit 1 /
		3640
		3641	#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /!< SDIO_CK dephasing selection bit /
		3642	#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /!< HW Flow Control enable /
		3643
		3644	/***************** Bit definition for SDIO_ARG register *****************/
		3645	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!< Command argument /
		3646
		3647	/***************** Bit definition for SDIO_CMD register *****************/
		3648	#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /!< Command Index /
		3649
		3650	#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /!< WAITRESP[1:0] bits (Wait for response bits) /
		3651	#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /!< Bit 0 /
		3652	#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /!< Bit 1 /
		3653
		3654	#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /!< CPSM Waits for Interrupt Request /
		3655	#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
		3656	#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /!< Command path state machine (CPSM) Enable bit /
		3657	#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /!< SD I/O suspend command /
		3658	#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /!< Enable CMD completion /
		3659	#define SDIO_CMD_NIEN ((uint32_t)0x2000) /!< Not Interrupt Enable /
		3660	#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /!< CE-ATA command /
		3661
		3662	/*************** Bit definition for SDIO_RESPCMD register ***************/
		3663	#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /!< Response command index /
		3664
		3665	/**************** Bit definition for SDIO_RESP0 register ****************/
		3666	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3667
		3668	/**************** Bit definition for SDIO_RESP1 register ****************/
		3669	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3670
		3671	/**************** Bit definition for SDIO_RESP2 register ****************/
		3672	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3673
		3674	/**************** Bit definition for SDIO_RESP3 register ****************/
		3675	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3676
		3677	/**************** Bit definition for SDIO_RESP4 register ****************/
		3678	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3679
		3680	/**************** Bit definition for SDIO_DTIMER register ***************/
		3681	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!< Data timeout period. /
		3682
		3683	/**************** Bit definition for SDIO_DLEN register *****************/
		3684	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!< Data length value /
		3685
		3686	/**************** Bit definition for SDIO_DCTRL register ****************/
		3687	#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /!< Data transfer enabled bit /
		3688	#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /!< Data transfer direction selection /
		3689	#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /!< Data transfer mode selection /
		3690	#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /!< DMA enabled bit /
		3691
		3692	#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /!< DBLOCKSIZE[3:0] bits (Data block size) /
		3693	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /!< Bit 0 /
		3694	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /!< Bit 1 /
		3695	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /!< Bit 2 /
		3696	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /!< Bit 3 /
		3697
		3698	#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /!< Read wait start /
		3699	#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /!< Read wait stop /
		3700	#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /!< Read wait mode /
		3701	#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /!< SD I/O enable functions /
		3702
		3703	/**************** Bit definition for SDIO_DCOUNT register ***************/
		3704	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!< Data count value /
		3705
		3706	/**************** Bit definition for SDIO_STA register ******************/
		3707	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!< Command response received (CRC check failed) /
		3708	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!< Data block sent/received (CRC check failed) /
		3709	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!< Command response timeout /
		3710	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!< Data timeout /
		3711	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!< Transmit FIFO underrun error /
		3712	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!< Received FIFO overrun error /
		3713	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!< Command response received (CRC check passed) /
		3714	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!< Command sent (no response required) /
		3715	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!< Data end (data counter, SDIDCOUNT, is zero) /
		3716	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!< Start bit not detected on all data signals in wide bus mode /
		3717	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!< Data block sent/received (CRC check passed) /
		3718	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!< Command transfer in progress /
		3719	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!< Data transmit in progress /
		3720	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!< Data receive in progress /
		3721	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
		3722	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
		3723	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!< Transmit FIFO full /
		3724	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!< Receive FIFO full /
		3725	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!< Transmit FIFO empty /
		3726	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!< Receive FIFO empty /
		3727	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!< Data available in transmit FIFO /
		3728	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!< Data available in receive FIFO /
		3729	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!< SDIO interrupt received /
		3730	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!< CE-ATA command completion signal received for CMD61 /
		3731
		3732	/***************** Bit definition for SDIO_ICR register *****************/
		3733	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!< CCRCFAIL flag clear bit /
		3734	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!< DCRCFAIL flag clear bit /
		3735	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!< CTIMEOUT flag clear bit /
		3736	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!< DTIMEOUT flag clear bit /
		3737	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!< TXUNDERR flag clear bit /
		3738	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!< RXOVERR flag clear bit /
		3739	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!< CMDREND flag clear bit /
		3740	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!< CMDSENT flag clear bit /
		3741	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!< DATAEND flag clear bit /
		3742	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!< STBITERR flag clear bit /
		3743	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!< DBCKEND flag clear bit /
		3744	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!< SDIOIT flag clear bit /
		3745	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!< CEATAEND flag clear bit /
		3746
		3747	/**************** Bit definition for SDIO_MASK register *****************/
		3748	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!< Command CRC Fail Interrupt Enable /
		3749	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!< Data CRC Fail Interrupt Enable /
		3750	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!< Command TimeOut Interrupt Enable /
		3751	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!< Data TimeOut Interrupt Enable /
		3752	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!< Tx FIFO UnderRun Error Interrupt Enable /
		3753	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!< Rx FIFO OverRun Error Interrupt Enable /
		3754	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!< Command Response Received Interrupt Enable /
		3755	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!< Command Sent Interrupt Enable /
		3756	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!< Data End Interrupt Enable /
		3757	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!< Start Bit Error Interrupt Enable /
		3758	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!< Data Block End Interrupt Enable /
		3759	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!< Command Acting Interrupt Enable /
		3760	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!< Data Transmit Acting Interrupt Enable /
		3761	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!< Data receive acting interrupt enabled /
		3762	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!< Tx FIFO Half Empty interrupt Enable /
		3763	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!< Rx FIFO Half Full interrupt Enable /
		3764	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!< Tx FIFO Full interrupt Enable /
		3765	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!< Rx FIFO Full interrupt Enable /
		3766	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!< Tx FIFO Empty interrupt Enable /
		3767	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!< Rx FIFO Empty interrupt Enable /
		3768	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!< Data available in Tx FIFO interrupt Enable /
		3769	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!< Data available in Rx FIFO interrupt Enable /
		3770	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!< SDIO Mode Interrupt Received interrupt Enable /
		3771	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!< CE-ATA command completion signal received Interrupt Enable /
		3772
		3773	/*************** Bit definition for SDIO_FIFOCNT register ***************/
		3774	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!< Remaining number of words to be written to or read from the FIFO /
		3775
		3776	/**************** Bit definition for SDIO_FIFO register *****************/
		3777	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!< Receive and transmit FIFO data /
		3778
		3779
		3780	/******************************************************************************/
		3781	/* */
		3782	/* Controller Area Network */
		3783	/* */
		3784	/******************************************************************************/
		3785
		3786	/!< CAN control and status registers /
		3787	/***************** Bit definition for CAN_MCR register ******************/
		3788	#define CAN_MCR_INRQ ((uint32_t)0x00000001) /!< Initialization Request /
		3789	#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /!< Sleep Mode Request /
		3790	#define CAN_MCR_TXFP ((uint32_t)0x00000004) /!< Transmit FIFO Priority /
		3791	#define CAN_MCR_RFLM ((uint32_t)0x00000008) /!< Receive FIFO Locked Mode /
		3792	#define CAN_MCR_NART ((uint32_t)0x00000010) /!< No Automatic Retransmission /
		3793	#define CAN_MCR_AWUM ((uint32_t)0x00000020) /!< Automatic Wakeup Mode /
		3794	#define CAN_MCR_ABOM ((uint32_t)0x00000040) /!< Automatic Bus-Off Management /
		3795	#define CAN_MCR_TTCM ((uint32_t)0x00000080) /!< Time Triggered Communication Mode /
		3796	#define CAN_MCR_RESET ((uint32_t)0x00008000) /!< CAN software master reset /
		3797	#define CAN_MCR_DBF ((uint32_t)0x00010000) /!< CAN Debug freeze /
		3798
		3799	/***************** Bit definition for CAN_MSR register ******************/
		3800	#define CAN_MSR_INAK ((uint32_t)0x00000001) /!< Initialization Acknowledge /
		3801	#define CAN_MSR_SLAK ((uint32_t)0x00000002) /!< Sleep Acknowledge /
		3802	#define CAN_MSR_ERRI ((uint32_t)0x00000004) /!< Error Interrupt /
		3803	#define CAN_MSR_WKUI ((uint32_t)0x00000008) /!< Wakeup Interrupt /
		3804	#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /!< Sleep Acknowledge Interrupt /
		3805	#define CAN_MSR_TXM ((uint32_t)0x00000100) /!< Transmit Mode /
		3806	#define CAN_MSR_RXM ((uint32_t)0x00000200) /!< Receive Mode /
		3807	#define CAN_MSR_SAMP ((uint32_t)0x00000400) /!< Last Sample Point /
		3808	#define CAN_MSR_RX ((uint32_t)0x00000800) /!< CAN Rx Signal /
		3809
		3810	/***************** Bit definition for CAN_TSR register ******************/
		3811	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!< Request Completed Mailbox0 /
		3812	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!< Transmission OK of Mailbox0 /
		3813	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!< Arbitration Lost for Mailbox0 /
		3814	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!< Transmission Error of Mailbox0 /
		3815	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!< Abort Request for Mailbox0 /
		3816	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!< Request Completed Mailbox1 /
		3817	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!< Transmission OK of Mailbox1 /
		3818	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!< Arbitration Lost for Mailbox1 /
		3819	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!< Transmission Error of Mailbox1 /
		3820	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!< Abort Request for Mailbox 1 /
		3821	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!< Request Completed Mailbox2 /
		3822	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!< Transmission OK of Mailbox 2 /
		3823	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!< Arbitration Lost for mailbox 2 /
		3824	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!< Transmission Error of Mailbox 2 /
		3825	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!< Abort Request for Mailbox 2 /
		3826	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!< Mailbox Code /
		3827
		3828	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!< TME[2:0] bits /
		3829	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!< Transmit Mailbox 0 Empty /
		3830	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!< Transmit Mailbox 1 Empty /
		3831	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!< Transmit Mailbox 2 Empty /
		3832
		3833	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!< LOW[2:0] bits /
		3834	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!< Lowest Priority Flag for Mailbox 0 /
		3835	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!< Lowest Priority Flag for Mailbox 1 /
		3836	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!< Lowest Priority Flag for Mailbox 2 /
		3837
		3838	/***************** Bit definition for CAN_RF0R register *****************/
		3839	#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /!< FIFO 0 Message Pending /
		3840	#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /!< FIFO 0 Full /
		3841	#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /!< FIFO 0 Overrun /
		3842	#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /!< Release FIFO 0 Output Mailbox /
		3843
		3844	/***************** Bit definition for CAN_RF1R register *****************/
		3845	#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /!< FIFO 1 Message Pending /
		3846	#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /!< FIFO 1 Full /
		3847	#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /!< FIFO 1 Overrun /
		3848	#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /!< Release FIFO 1 Output Mailbox /
		3849
		3850	/****************** Bit definition for CAN_IER register *****************/
		3851	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!< Transmit Mailbox Empty Interrupt Enable /
		3852	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!< FIFO Message Pending Interrupt Enable /
		3853	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!< FIFO Full Interrupt Enable /
		3854	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!< FIFO Overrun Interrupt Enable /
		3855	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!< FIFO Message Pending Interrupt Enable /
		3856	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!< FIFO Full Interrupt Enable /
		3857	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!< FIFO Overrun Interrupt Enable /
		3858	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!< Error Warning Interrupt Enable /
		3859	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!< Error Passive Interrupt Enable /
		3860	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!< Bus-Off Interrupt Enable /
		3861	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!< Last Error Code Interrupt Enable /
		3862	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!< Error Interrupt Enable /
		3863	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!< Wakeup Interrupt Enable /
		3864	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!< Sleep Interrupt Enable /
		3865
		3866	/****************** Bit definition for CAN_ESR register *****************/
		3867	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!< Error Warning Flag /
		3868	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!< Error Passive Flag /
		3869	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!< Bus-Off Flag /
		3870
		3871	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!< LEC[2:0] bits (Last Error Code) /
		3872	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3873	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3874	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!< Bit 2 /
		3875
		3876	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!< Least significant byte of the 9-bit Transmit Error Counter /
		3877	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!< Receive Error Counter /
		3878
		3879	/***************** Bit definition for CAN_BTR register ******************/
		3880	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
		3881	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
		3882	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Time Segment 1 (Bit 0) /
		3883	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Time Segment 1 (Bit 1) /
		3884	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Time Segment 1 (Bit 2) /
		3885	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Time Segment 1 (Bit 3) /
		3886	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
		3887	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Time Segment 2 (Bit 0) /
		3888	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Time Segment 2 (Bit 1) /
		3889	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Time Segment 2 (Bit 2) /
		3890	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
		3891	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Resynchronization Jump Width (Bit 0) /
		3892	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Resynchronization Jump Width (Bit 1) /
		3893	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
		3894	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
		3895
		3896	/!< Mailbox registers /
		3897	/**************** Bit definition for CAN_TI0R register ******************/
		3898	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
		3899	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		3900	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		3901	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
		3902	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		3903
		3904	/**************** Bit definition for CAN_TDT0R register *****************/
		3905	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		3906	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
		3907	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		3908
		3909	/**************** Bit definition for CAN_TDL0R register *****************/
		3910	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		3911	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		3912	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		3913	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		3914
		3915	/**************** Bit definition for CAN_TDH0R register *****************/
		3916	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		3917	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		3918	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		3919	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		3920
		3921	/***************** Bit definition for CAN_TI1R register *****************/
		3922	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
		3923	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		3924	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		3925	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
		3926	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		3927
		3928	/***************** Bit definition for CAN_TDT1R register ****************/
		3929	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		3930	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
		3931	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		3932
		3933	/***************** Bit definition for CAN_TDL1R register ****************/
		3934	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		3935	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		3936	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		3937	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		3938
		3939	/***************** Bit definition for CAN_TDH1R register ****************/
		3940	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		3941	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		3942	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		3943	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		3944
		3945	/***************** Bit definition for CAN_TI2R register *****************/
		3946	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
		3947	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		3948	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		3949	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
		3950	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		3951
		3952	/***************** Bit definition for CAN_TDT2R register ****************/
		3953	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		3954	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
		3955	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		3956
		3957	/***************** Bit definition for CAN_TDL2R register ****************/
		3958	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		3959	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		3960	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		3961	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		3962
		3963	/***************** Bit definition for CAN_TDH2R register ****************/
		3964	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		3965	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		3966	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		3967	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		3968
		3969	/***************** Bit definition for CAN_RI0R register *****************/
		3970	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		3971	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		3972	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
		3973	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		3974
		3975	/***************** Bit definition for CAN_RDT0R register ****************/
		3976	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		3977	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
		3978	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		3979
		3980	/***************** Bit definition for CAN_RDL0R register ****************/
		3981	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		3982	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		3983	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		3984	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		3985
		3986	/***************** Bit definition for CAN_RDH0R register ****************/
		3987	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		3988	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		3989	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		3990	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		3991
		3992	/***************** Bit definition for CAN_RI1R register *****************/
		3993	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		3994	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		3995	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
		3996	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		3997
		3998	/***************** Bit definition for CAN_RDT1R register ****************/
		3999	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		4000	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
		4001	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		4002
		4003	/***************** Bit definition for CAN_RDL1R register ****************/
		4004	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		4005	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		4006	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		4007	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		4008
		4009	/***************** Bit definition for CAN_RDH1R register ****************/
		4010	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		4011	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		4012	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		4013	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		4014
		4015	/!< CAN filter registers /
		4016	/***************** Bit definition for CAN_FMR register ******************/
		4017	#define CAN_FMR_FINIT ((uint32_t)0x00000001) /!< Filter Init Mode /
		4018	#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /!< CAN2 start bank /
		4019
		4020	/***************** Bit definition for CAN_FM1R register *****************/
		4021	#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /!< Filter Mode /
		4022	#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /!< Filter Init Mode for filter 0 /
		4023	#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /!< Filter Init Mode for filter 1 /
		4024	#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /!< Filter Init Mode for filter 2 /
		4025	#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /!< Filter Init Mode for filter 3 /
		4026	#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /!< Filter Init Mode for filter 4 /
		4027	#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /!< Filter Init Mode for filter 5 /
		4028	#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /!< Filter Init Mode for filter 6 /
		4029	#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /!< Filter Init Mode for filter 7 /
		4030	#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /!< Filter Init Mode for filter 8 /
		4031	#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /!< Filter Init Mode for filter 9 /
		4032	#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /!< Filter Init Mode for filter 10 /
		4033	#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /!< Filter Init Mode for filter 11 /
		4034	#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /!< Filter Init Mode for filter 12 /
		4035	#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /!< Filter Init Mode for filter 13 /
		4036	#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /!< Filter Init Mode for filter 14 /
		4037	#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /!< Filter Init Mode for filter 15 /
		4038	#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /!< Filter Init Mode for filter 16 /
		4039	#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /!< Filter Init Mode for filter 17 /
		4040	#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /!< Filter Init Mode for filter 18 /
		4041	#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /!< Filter Init Mode for filter 19 /
		4042	#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /!< Filter Init Mode for filter 20 /
		4043	#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /!< Filter Init Mode for filter 21 /
		4044	#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /!< Filter Init Mode for filter 22 /
		4045	#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /!< Filter Init Mode for filter 23 /
		4046	#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /!< Filter Init Mode for filter 24 /
		4047	#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /!< Filter Init Mode for filter 25 /
		4048	#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /!< Filter Init Mode for filter 26 /
		4049	#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /!< Filter Init Mode for filter 27 /
		4050
		4051	/***************** Bit definition for CAN_FS1R register *****************/
		4052	#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /!< Filter Scale Configuration /
		4053	#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /!< Filter Scale Configuration for filter 0 /
		4054	#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /!< Filter Scale Configuration for filter 1 /
		4055	#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /!< Filter Scale Configuration for filter 2 /
		4056	#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /!< Filter Scale Configuration for filter 3 /
		4057	#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /!< Filter Scale Configuration for filter 4 /
		4058	#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /!< Filter Scale Configuration for filter 5 /
		4059	#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /!< Filter Scale Configuration for filter 6 /
		4060	#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /!< Filter Scale Configuration for filter 7 /
		4061	#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /!< Filter Scale Configuration for filter 8 /
		4062	#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /!< Filter Scale Configuration for filter 9 /
		4063	#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /!< Filter Scale Configuration for filter 10 /
		4064	#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /!< Filter Scale Configuration for filter 11 /
		4065	#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /!< Filter Scale Configuration for filter 12 /
		4066	#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /!< Filter Scale Configuration for filter 13 /
		4067	#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /!< Filter Scale Configuration for filter 14 /
		4068	#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /!< Filter Scale Configuration for filter 15 /
		4069	#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /!< Filter Scale Configuration for filter 16 /
		4070	#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /!< Filter Scale Configuration for filter 17 /
		4071	#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /!< Filter Scale Configuration for filter 18 /
		4072	#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /!< Filter Scale Configuration for filter 19 /
		4073	#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /!< Filter Scale Configuration for filter 20 /
		4074	#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /!< Filter Scale Configuration for filter 21 /
		4075	#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /!< Filter Scale Configuration for filter 22 /
		4076	#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /!< Filter Scale Configuration for filter 23 /
		4077	#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /!< Filter Scale Configuration for filter 24 /
		4078	#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /!< Filter Scale Configuration for filter 25 /
		4079	#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /!< Filter Scale Configuration for filter 26 /
		4080	#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /!< Filter Scale Configuration for filter 27 /
		4081
		4082	/**************** Bit definition for CAN_FFA1R register *****************/
		4083	#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /!< Filter FIFO Assignment /
		4084	#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /!< Filter FIFO Assignment for filter 0 /
		4085	#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /!< Filter FIFO Assignment for filter 1 /
		4086	#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /!< Filter FIFO Assignment for filter 2 /
		4087	#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /!< Filter FIFO Assignment for filter 3 /
		4088	#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /!< Filter FIFO Assignment for filter 4 /
		4089	#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /!< Filter FIFO Assignment for filter 5 /
		4090	#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /!< Filter FIFO Assignment for filter 6 /
		4091	#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /!< Filter FIFO Assignment for filter 7 /
		4092	#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /!< Filter FIFO Assignment for filter 8 /
		4093	#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /!< Filter FIFO Assignment for filter 9 /
		4094	#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /!< Filter FIFO Assignment for filter 10 /
		4095	#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /!< Filter FIFO Assignment for filter 11 /
		4096	#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /!< Filter FIFO Assignment for filter 12 /
		4097	#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /!< Filter FIFO Assignment for filter 13 /
		4098	#define CAN_FFA1_FFA14 ((uint32_t)0x00004000) /!< Filter FIFO Assignment for filter 14 /
		4099	#define CAN_FFA1_FFA15 ((uint32_t)0x00008000) /!< Filter FIFO Assignment for filter 15 /
		4100	#define CAN_FFA1_FFA16 ((uint32_t)0x00010000) /!< Filter FIFO Assignment for filter 16 /
		4101	#define CAN_FFA1_FFA17 ((uint32_t)0x00020000) /!< Filter FIFO Assignment for filter 17 /
		4102	#define CAN_FFA1_FFA18 ((uint32_t)0x00040000) /!< Filter FIFO Assignment for filter 18 /
		4103	#define CAN_FFA1_FFA19 ((uint32_t)0x00080000) /!< Filter FIFO Assignment for filter 19 /
		4104	#define CAN_FFA1_FFA20 ((uint32_t)0x00100000) /!< Filter FIFO Assignment for filter 20 /
		4105	#define CAN_FFA1_FFA21 ((uint32_t)0x00200000) /!< Filter FIFO Assignment for filter 21 /
		4106	#define CAN_FFA1_FFA22 ((uint32_t)0x00400000) /!< Filter FIFO Assignment for filter 22 /
		4107	#define CAN_FFA1_FFA23 ((uint32_t)0x00800000) /!< Filter FIFO Assignment for filter 23 /
		4108	#define CAN_FFA1_FFA24 ((uint32_t)0x01000000) /!< Filter FIFO Assignment for filter 24 /
		4109	#define CAN_FFA1_FFA25 ((uint32_t)0x02000000) /!< Filter FIFO Assignment for filter 25 /
		4110	#define CAN_FFA1_FFA26 ((uint32_t)0x04000000) /!< Filter FIFO Assignment for filter 26 /
		4111	#define CAN_FFA1_FFA27 ((uint32_t)0x08000000) /!< Filter FIFO Assignment for filter 27 /
		4112
		4113	/***************** Bit definition for CAN_FA1R register *****************/
		4114	#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /!< Filter Active /
		4115	#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /!< Filter 0 Active /
		4116	#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /!< Filter 1 Active /
		4117	#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /!< Filter 2 Active /
		4118	#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /!< Filter 3 Active /
		4119	#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /!< Filter 4 Active /
		4120	#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /!< Filter 5 Active /
		4121	#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /!< Filter 6 Active /
		4122	#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /!< Filter 7 Active /
		4123	#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /!< Filter 8 Active /
		4124	#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /!< Filter 9 Active /
		4125	#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /!< Filter 10 Active /
		4126	#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /!< Filter 11 Active /
		4127	#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /!< Filter 12 Active /
		4128	#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /!< Filter 13 Active /
		4129	#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /!< Filter 14 Active /
		4130	#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /!< Filter 15 Active /
		4131	#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /!< Filter 16 Active /
		4132	#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /!< Filter 17 Active /
		4133	#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /!< Filter 18 Active /
		4134	#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /!< Filter 19 Active /
		4135	#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /!< Filter 20 Active /
		4136	#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /!< Filter 21 Active /
		4137	#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /!< Filter 22 Active /
		4138	#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /!< Filter 23 Active /
		4139	#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /!< Filter 24 Active /
		4140	#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /!< Filter 25 Active /
		4141	#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /!< Filter 26 Active /
		4142	#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /!< Filter 27 Active /
		4143
		4144	/***************** Bit definition for CAN_F0R1 register *****************/
		4145	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4146	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4147	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4148	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4149	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4150	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4151	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4152	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4153	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4154	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4155	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4156	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4157	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4158	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4159	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4160	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4161	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4162	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4163	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4164	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4165	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4166	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4167	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4168	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4169	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4170	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4171	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4172	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4173	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4174	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4175	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4176	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4177
		4178	/***************** Bit definition for CAN_F1R1 register *****************/
		4179	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4180	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4181	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4182	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4183	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4184	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4185	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4186	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4187	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4188	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4189	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4190	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4191	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4192	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4193	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4194	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4195	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4196	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4197	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4198	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4199	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4200	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4201	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4202	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4203	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4204	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4205	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4206	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4207	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4208	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4209	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4210	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4211
		4212	/***************** Bit definition for CAN_F2R1 register *****************/
		4213	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4214	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4215	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4216	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4217	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4218	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4219	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4220	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4221	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4222	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4223	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4224	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4225	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4226	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4227	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4228	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4229	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4230	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4231	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4232	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4233	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4234	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4235	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4236	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4237	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4238	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4239	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4240	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4241	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4242	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4243	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4244	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4245
		4246	/***************** Bit definition for CAN_F3R1 register *****************/
		4247	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4248	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4249	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4250	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4251	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4252	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4253	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4254	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4255	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4256	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4257	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4258	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4259	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4260	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4261	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4262	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4263	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4264	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4265	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4266	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4267	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4268	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4269	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4270	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4271	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4272	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4273	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4274	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4275	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4276	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4277	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4278	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4279
		4280	/***************** Bit definition for CAN_F4R1 register *****************/
		4281	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4282	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4283	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4284	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4285	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4286	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4287	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4288	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4289	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4290	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4291	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4292	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4293	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4294	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4295	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4296	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4297	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4298	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4299	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4300	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4301	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4302	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4303	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4304	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4305	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4306	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4307	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4308	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4309	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4310	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4311	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4312	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4313
		4314	/***************** Bit definition for CAN_F5R1 register *****************/
		4315	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4316	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4317	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4318	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4319	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4320	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4321	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4322	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4323	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4324	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4325	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4326	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4327	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4328	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4329	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4330	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4331	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4332	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4333	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4334	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4335	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4336	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4337	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4338	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4339	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4340	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4341	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4342	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4343	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4344	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4345	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4346	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4347
		4348	/***************** Bit definition for CAN_F6R1 register *****************/
		4349	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4350	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4351	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4352	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4353	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4354	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4355	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4356	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4357	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4358	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4359	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4360	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4361	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4362	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4363	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4364	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4365	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4366	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4367	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4368	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4369	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4370	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4371	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4372	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4373	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4374	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4375	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4376	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4377	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4378	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4379	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4380	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4381
		4382	/***************** Bit definition for CAN_F7R1 register *****************/
		4383	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4384	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4385	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4386	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4387	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4388	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4389	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4390	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4391	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4392	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4393	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4394	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4395	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4396	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4397	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4398	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4399	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4400	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4401	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4402	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4403	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4404	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4405	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4406	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4407	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4408	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4409	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4410	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4411	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4412	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4413	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4414	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4415
		4416	/***************** Bit definition for CAN_F8R1 register *****************/
		4417	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4418	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4419	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4420	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4421	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4422	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4423	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4424	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4425	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4426	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4427	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4428	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4429	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4430	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4431	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4432	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4433	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4434	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4435	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4436	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4437	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4438	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4439	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4440	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4441	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4442	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4443	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4444	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4445	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4446	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4447	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4448	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4449
		4450	/***************** Bit definition for CAN_F9R1 register *****************/
		4451	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4452	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4453	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4454	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4455	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4456	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4457	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4458	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4459	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4460	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4461	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4462	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4463	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4464	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4465	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4466	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4467	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4468	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4469	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4470	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4471	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4472	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4473	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4474	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4475	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4476	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4477	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4478	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4479	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4480	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4481	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4482	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4483
		4484	/***************** Bit definition for CAN_F10R1 register ****************/
		4485	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4486	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4487	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4488	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4489	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4490	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4491	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4492	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4493	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4494	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4495	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4496	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4497	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4498	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4499	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4500	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4501	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4502	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4503	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4504	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4505	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4506	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4507	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4508	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4509	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4510	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4511	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4512	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4513	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4514	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4515	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4516	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4517
		4518	/***************** Bit definition for CAN_F11R1 register ****************/
		4519	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4520	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4521	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4522	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4523	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4524	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4525	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4526	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4527	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4528	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4529	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4530	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4531	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4532	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4533	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4534	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4535	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4536	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4537	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4538	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4539	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4540	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4541	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4542	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4543	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4544	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4545	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4546	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4547	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4548	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4549	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4550	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4551
		4552	/***************** Bit definition for CAN_F12R1 register ****************/
		4553	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4554	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4555	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4556	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4557	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4558	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4559	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4560	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4561	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4562	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4563	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4564	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4565	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4566	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4567	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4568	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4569	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4570	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4571	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4572	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4573	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4574	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4575	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4576	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4577	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4578	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4579	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4580	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4581	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4582	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4583	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4584	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4585
		4586	/***************** Bit definition for CAN_F13R1 register ****************/
		4587	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4588	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4589	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4590	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4591	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4592	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4593	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4594	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4595	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4596	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4597	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4598	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4599	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4600	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4601	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4602	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4603	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4604	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4605	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4606	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4607	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4608	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4609	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4610	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4611	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4612	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4613	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4614	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4615	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4616	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4617	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4618	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4619
		4620	/***************** Bit definition for CAN_F14R1 register ****************/
		4621	#define CAN_F14R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4622	#define CAN_F14R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4623	#define CAN_F14R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4624	#define CAN_F14R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4625	#define CAN_F14R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4626	#define CAN_F14R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4627	#define CAN_F14R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4628	#define CAN_F14R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4629	#define CAN_F14R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4630	#define CAN_F14R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4631	#define CAN_F14R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4632	#define CAN_F14R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4633	#define CAN_F14R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4634	#define CAN_F14R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4635	#define CAN_F14R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4636	#define CAN_F14R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4637	#define CAN_F14R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4638	#define CAN_F14R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4639	#define CAN_F14R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4640	#define CAN_F14R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4641	#define CAN_F14R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4642	#define CAN_F14R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4643	#define CAN_F14R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4644	#define CAN_F14R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4645	#define CAN_F14R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4646	#define CAN_F14R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4647	#define CAN_F14R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4648	#define CAN_F14R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4649	#define CAN_F14R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4650	#define CAN_F14R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4651	#define CAN_F14R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4652	#define CAN_F14R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4653
		4654	/***************** Bit definition for CAN_F15R1 register ****************/
		4655	#define CAN_F15R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4656	#define CAN_F15R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4657	#define CAN_F15R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4658	#define CAN_F15R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4659	#define CAN_F15R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4660	#define CAN_F15R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4661	#define CAN_F15R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4662	#define CAN_F15R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4663	#define CAN_F15R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4664	#define CAN_F15R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4665	#define CAN_F15R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4666	#define CAN_F15R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4667	#define CAN_F15R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4668	#define CAN_F15R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4669	#define CAN_F15R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4670	#define CAN_F15R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4671	#define CAN_F15R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4672	#define CAN_F15R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4673	#define CAN_F15R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4674	#define CAN_F15R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4675	#define CAN_F15R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4676	#define CAN_F15R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4677	#define CAN_F15R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4678	#define CAN_F15R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4679	#define CAN_F15R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4680	#define CAN_F15R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4681	#define CAN_F15R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4682	#define CAN_F15R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4683	#define CAN_F15R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4684	#define CAN_F15R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4685	#define CAN_F15R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4686	#define CAN_F15R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4687
		4688	/***************** Bit definition for CAN_F16R1 register ****************/
		4689	#define CAN_F16R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4690	#define CAN_F16R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4691	#define CAN_F16R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4692	#define CAN_F16R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4693	#define CAN_F16R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4694	#define CAN_F16R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4695	#define CAN_F16R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4696	#define CAN_F16R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4697	#define CAN_F16R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4698	#define CAN_F16R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4699	#define CAN_F16R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4700	#define CAN_F16R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4701	#define CAN_F16R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4702	#define CAN_F16R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4703	#define CAN_F16R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4704	#define CAN_F16R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4705	#define CAN_F16R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4706	#define CAN_F16R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4707	#define CAN_F16R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4708	#define CAN_F16R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4709	#define CAN_F16R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4710	#define CAN_F16R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4711	#define CAN_F16R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4712	#define CAN_F16R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4713	#define CAN_F16R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4714	#define CAN_F16R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4715	#define CAN_F16R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4716	#define CAN_F16R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4717	#define CAN_F16R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4718	#define CAN_F16R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4719	#define CAN_F16R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4720	#define CAN_F16R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4721
		4722	/***************** Bit definition for CAN_F17R1 register ****************/
		4723	#define CAN_F17R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4724	#define CAN_F17R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4725	#define CAN_F17R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4726	#define CAN_F17R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4727	#define CAN_F17R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4728	#define CAN_F17R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4729	#define CAN_F17R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4730	#define CAN_F17R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4731	#define CAN_F17R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4732	#define CAN_F17R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4733	#define CAN_F17R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4734	#define CAN_F17R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4735	#define CAN_F17R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4736	#define CAN_F17R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4737	#define CAN_F17R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4738	#define CAN_F17R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4739	#define CAN_F17R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4740	#define CAN_F17R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4741	#define CAN_F17R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4742	#define CAN_F17R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4743	#define CAN_F17R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4744	#define CAN_F17R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4745	#define CAN_F17R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4746	#define CAN_F17R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4747	#define CAN_F17R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4748	#define CAN_F17R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4749	#define CAN_F17R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4750	#define CAN_F17R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4751	#define CAN_F17R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4752	#define CAN_F17R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4753	#define CAN_F17R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4754	#define CAN_F17R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4755
		4756	/***************** Bit definition for CAN_F18R1 register ****************/
		4757	#define CAN_F18R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4758	#define CAN_F18R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4759	#define CAN_F18R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4760	#define CAN_F18R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4761	#define CAN_F18R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4762	#define CAN_F18R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4763	#define CAN_F18R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4764	#define CAN_F18R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4765	#define CAN_F18R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4766	#define CAN_F18R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4767	#define CAN_F18R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4768	#define CAN_F18R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4769	#define CAN_F18R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4770	#define CAN_F18R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4771	#define CAN_F18R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4772	#define CAN_F18R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4773	#define CAN_F18R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4774	#define CAN_F18R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4775	#define CAN_F18R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4776	#define CAN_F18R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4777	#define CAN_F18R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4778	#define CAN_F18R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4779	#define CAN_F18R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4780	#define CAN_F18R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4781	#define CAN_F18R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4782	#define CAN_F18R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4783	#define CAN_F18R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4784	#define CAN_F18R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4785	#define CAN_F18R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4786	#define CAN_F18R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4787	#define CAN_F18R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4788	#define CAN_F18R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4789
		4790	/***************** Bit definition for CAN_F19R1 register ****************/
		4791	#define CAN_F19R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4792	#define CAN_F19R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4793	#define CAN_F19R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4794	#define CAN_F19R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4795	#define CAN_F19R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4796	#define CAN_F19R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4797	#define CAN_F19R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4798	#define CAN_F19R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4799	#define CAN_F19R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4800	#define CAN_F19R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4801	#define CAN_F19R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4802	#define CAN_F19R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4803	#define CAN_F19R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4804	#define CAN_F19R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4805	#define CAN_F19R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4806	#define CAN_F19R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4807	#define CAN_F19R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4808	#define CAN_F19R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4809	#define CAN_F19R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4810	#define CAN_F19R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4811	#define CAN_F19R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4812	#define CAN_F19R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4813	#define CAN_F19R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4814	#define CAN_F19R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4815	#define CAN_F19R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4816	#define CAN_F19R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4817	#define CAN_F19R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4818	#define CAN_F19R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4819	#define CAN_F19R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4820	#define CAN_F19R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4821	#define CAN_F19R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4822	#define CAN_F19R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4823
		4824	/***************** Bit definition for CAN_F20R1 register ****************/
		4825	#define CAN_F20R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4826	#define CAN_F20R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4827	#define CAN_F20R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4828	#define CAN_F20R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4829	#define CAN_F20R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4830	#define CAN_F20R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4831	#define CAN_F20R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4832	#define CAN_F20R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4833	#define CAN_F20R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4834	#define CAN_F20R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4835	#define CAN_F20R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4836	#define CAN_F20R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4837	#define CAN_F20R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4838	#define CAN_F20R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4839	#define CAN_F20R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4840	#define CAN_F20R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4841	#define CAN_F20R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4842	#define CAN_F20R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4843	#define CAN_F20R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4844	#define CAN_F20R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4845	#define CAN_F20R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4846	#define CAN_F20R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4847	#define CAN_F20R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4848	#define CAN_F20R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4849	#define CAN_F20R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4850	#define CAN_F20R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4851	#define CAN_F20R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4852	#define CAN_F20R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4853	#define CAN_F20R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4854	#define CAN_F20R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4855	#define CAN_F20R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4856	#define CAN_F20R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4857
		4858	/***************** Bit definition for CAN_F21R1 register ****************/
		4859	#define CAN_F21R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4860	#define CAN_F21R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4861	#define CAN_F21R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4862	#define CAN_F21R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4863	#define CAN_F21R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4864	#define CAN_F21R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4865	#define CAN_F21R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4866	#define CAN_F21R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4867	#define CAN_F21R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4868	#define CAN_F21R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4869	#define CAN_F21R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4870	#define CAN_F21R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4871	#define CAN_F21R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4872	#define CAN_F21R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4873	#define CAN_F21R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4874	#define CAN_F21R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4875	#define CAN_F21R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4876	#define CAN_F21R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4877	#define CAN_F21R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4878	#define CAN_F21R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4879	#define CAN_F21R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4880	#define CAN_F21R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4881	#define CAN_F21R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4882	#define CAN_F21R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4883	#define CAN_F21R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4884	#define CAN_F21R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4885	#define CAN_F21R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4886	#define CAN_F21R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4887	#define CAN_F21R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4888	#define CAN_F21R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4889	#define CAN_F21R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4890	#define CAN_F21R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4891
		4892	/***************** Bit definition for CAN_F22R1 register ****************/
		4893	#define CAN_F22R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4894	#define CAN_F22R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4895	#define CAN_F22R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4896	#define CAN_F22R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4897	#define CAN_F22R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4898	#define CAN_F22R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4899	#define CAN_F22R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4900	#define CAN_F22R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4901	#define CAN_F22R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4902	#define CAN_F22R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4903	#define CAN_F22R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4904	#define CAN_F22R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4905	#define CAN_F22R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4906	#define CAN_F22R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4907	#define CAN_F22R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4908	#define CAN_F22R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4909	#define CAN_F22R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4910	#define CAN_F22R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4911	#define CAN_F22R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4912	#define CAN_F22R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4913	#define CAN_F22R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4914	#define CAN_F22R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4915	#define CAN_F22R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4916	#define CAN_F22R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4917	#define CAN_F22R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4918	#define CAN_F22R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4919	#define CAN_F22R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4920	#define CAN_F22R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4921	#define CAN_F22R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4922	#define CAN_F22R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4923	#define CAN_F22R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4924	#define CAN_F22R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4925
		4926	/***************** Bit definition for CAN_F23R1 register ****************/
		4927	#define CAN_F23R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4928	#define CAN_F23R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4929	#define CAN_F23R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4930	#define CAN_F23R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4931	#define CAN_F23R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4932	#define CAN_F23R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4933	#define CAN_F23R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4934	#define CAN_F23R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4935	#define CAN_F23R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4936	#define CAN_F23R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4937	#define CAN_F23R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4938	#define CAN_F23R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4939	#define CAN_F23R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4940	#define CAN_F23R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4941	#define CAN_F23R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4942	#define CAN_F23R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4943	#define CAN_F23R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4944	#define CAN_F23R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4945	#define CAN_F23R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4946	#define CAN_F23R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4947	#define CAN_F23R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4948	#define CAN_F23R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4949	#define CAN_F23R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4950	#define CAN_F23R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4951	#define CAN_F23R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4952	#define CAN_F23R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4953	#define CAN_F23R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4954	#define CAN_F23R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4955	#define CAN_F23R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4956	#define CAN_F23R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4957	#define CAN_F23R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4958	#define CAN_F23R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4959
		4960	/***************** Bit definition for CAN_F24R1 register ****************/
		4961	#define CAN_F24R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4962	#define CAN_F24R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4963	#define CAN_F24R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4964	#define CAN_F24R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4965	#define CAN_F24R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4966	#define CAN_F24R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4967	#define CAN_F24R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4968	#define CAN_F24R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4969	#define CAN_F24R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4970	#define CAN_F24R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4971	#define CAN_F24R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4972	#define CAN_F24R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4973	#define CAN_F24R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4974	#define CAN_F24R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4975	#define CAN_F24R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4976	#define CAN_F24R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4977	#define CAN_F24R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4978	#define CAN_F24R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4979	#define CAN_F24R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4980	#define CAN_F24R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4981	#define CAN_F24R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4982	#define CAN_F24R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4983	#define CAN_F24R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4984	#define CAN_F24R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4985	#define CAN_F24R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4986	#define CAN_F24R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4987	#define CAN_F24R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4988	#define CAN_F24R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4989	#define CAN_F24R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4990	#define CAN_F24R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4991	#define CAN_F24R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4992	#define CAN_F24R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4993
		4994	/***************** Bit definition for CAN_F25R1 register ****************/
		4995	#define CAN_F25R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4996	#define CAN_F25R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4997	#define CAN_F25R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4998	#define CAN_F25R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4999	#define CAN_F25R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5000	#define CAN_F25R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5001	#define CAN_F25R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5002	#define CAN_F25R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5003	#define CAN_F25R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5004	#define CAN_F25R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5005	#define CAN_F25R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5006	#define CAN_F25R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5007	#define CAN_F25R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5008	#define CAN_F25R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5009	#define CAN_F25R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5010	#define CAN_F25R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5011	#define CAN_F25R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5012	#define CAN_F25R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5013	#define CAN_F25R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5014	#define CAN_F25R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5015	#define CAN_F25R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5016	#define CAN_F25R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5017	#define CAN_F25R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5018	#define CAN_F25R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5019	#define CAN_F25R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5020	#define CAN_F25R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5021	#define CAN_F25R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5022	#define CAN_F25R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5023	#define CAN_F25R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5024	#define CAN_F25R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5025	#define CAN_F25R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5026	#define CAN_F25R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5027
		5028	/***************** Bit definition for CAN_F26R1 register ****************/
		5029	#define CAN_F26R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5030	#define CAN_F26R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5031	#define CAN_F26R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5032	#define CAN_F26R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5033	#define CAN_F26R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5034	#define CAN_F26R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5035	#define CAN_F26R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5036	#define CAN_F26R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5037	#define CAN_F26R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5038	#define CAN_F26R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5039	#define CAN_F26R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5040	#define CAN_F26R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5041	#define CAN_F26R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5042	#define CAN_F26R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5043	#define CAN_F26R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5044	#define CAN_F26R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5045	#define CAN_F26R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5046	#define CAN_F26R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5047	#define CAN_F26R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5048	#define CAN_F26R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5049	#define CAN_F26R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5050	#define CAN_F26R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5051	#define CAN_F26R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5052	#define CAN_F26R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5053	#define CAN_F26R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5054	#define CAN_F26R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5055	#define CAN_F26R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5056	#define CAN_F26R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5057	#define CAN_F26R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5058	#define CAN_F26R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5059	#define CAN_F26R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5060	#define CAN_F26R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5061
		5062	/***************** Bit definition for CAN_F27R1 register ****************/
		5063	#define CAN_F27R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5064	#define CAN_F27R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5065	#define CAN_F27R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5066	#define CAN_F27R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5067	#define CAN_F27R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5068	#define CAN_F27R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5069	#define CAN_F27R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5070	#define CAN_F27R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5071	#define CAN_F27R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5072	#define CAN_F27R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5073	#define CAN_F27R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5074	#define CAN_F27R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5075	#define CAN_F27R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5076	#define CAN_F27R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5077	#define CAN_F27R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5078	#define CAN_F27R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5079	#define CAN_F27R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5080	#define CAN_F27R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5081	#define CAN_F27R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5082	#define CAN_F27R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5083	#define CAN_F27R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5084	#define CAN_F27R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5085	#define CAN_F27R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5086	#define CAN_F27R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5087	#define CAN_F27R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5088	#define CAN_F27R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5089	#define CAN_F27R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5090	#define CAN_F27R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5091	#define CAN_F27R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5092	#define CAN_F27R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5093	#define CAN_F27R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5094	#define CAN_F27R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5095
		5096	/***************** Bit definition for CAN_F0R2 register *****************/
		5097	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5098	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5099	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5100	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5101	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5102	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5103	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5104	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5105	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5106	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5107	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5108	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5109	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5110	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5111	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5112	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5113	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5114	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5115	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5116	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5117	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5118	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5119	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5120	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5121	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5122	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5123	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5124	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5125	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5126	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5127	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5128	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5129
		5130	/***************** Bit definition for CAN_F1R2 register *****************/
		5131	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5132	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5133	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5134	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5135	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5136	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5137	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5138	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5139	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5140	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5141	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5142	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5143	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5144	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5145	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5146	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5147	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5148	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5149	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5150	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5151	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5152	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5153	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5154	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5155	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5156	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5157	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5158	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5159	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5160	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5161	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5162	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5163
		5164	/***************** Bit definition for CAN_F2R2 register *****************/
		5165	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5166	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5167	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5168	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5169	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5170	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5171	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5172	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5173	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5174	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5175	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5176	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5177	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5178	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5179	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5180	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5181	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5182	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5183	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5184	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5185	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5186	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5187	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5188	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5189	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5190	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5191	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5192	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5193	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5194	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5195	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5196	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5197
		5198	/***************** Bit definition for CAN_F3R2 register *****************/
		5199	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5200	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5201	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5202	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5203	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5204	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5205	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5206	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5207	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5208	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5209	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5210	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5211	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5212	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5213	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5214	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5215	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5216	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5217	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5218	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5219	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5220	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5221	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5222	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5223	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5224	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5225	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5226	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5227	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5228	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5229	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5230	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5231
		5232	/***************** Bit definition for CAN_F4R2 register *****************/
		5233	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5234	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5235	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5236	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5237	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5238	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5239	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5240	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5241	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5242	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5243	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5244	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5245	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5246	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5247	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5248	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5249	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5250	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5251	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5252	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5253	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5254	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5255	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5256	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5257	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5258	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5259	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5260	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5261	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5262	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5263	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5264	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5265
		5266	/***************** Bit definition for CAN_F5R2 register *****************/
		5267	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5268	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5269	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5270	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5271	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5272	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5273	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5274	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5275	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5276	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5277	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5278	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5279	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5280	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5281	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5282	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5283	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5284	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5285	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5286	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5287	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5288	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5289	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5290	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5291	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5292	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5293	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5294	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5295	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5296	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5297	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5298	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5299
		5300	/***************** Bit definition for CAN_F6R2 register *****************/
		5301	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5302	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5303	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5304	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5305	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5306	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5307	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5308	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5309	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5310	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5311	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5312	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5313	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5314	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5315	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5316	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5317	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5318	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5319	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5320	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5321	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5322	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5323	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5324	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5325	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5326	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5327	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5328	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5329	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5330	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5331	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5332	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5333
		5334	/***************** Bit definition for CAN_F7R2 register *****************/
		5335	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5336	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5337	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5338	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5339	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5340	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5341	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5342	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5343	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5344	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5345	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5346	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5347	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5348	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5349	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5350	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5351	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5352	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5353	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5354	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5355	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5356	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5357	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5358	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5359	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5360	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5361	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5362	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5363	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5364	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5365	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5366	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5367
		5368	/***************** Bit definition for CAN_F8R2 register *****************/
		5369	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5370	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5371	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5372	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5373	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5374	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5375	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5376	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5377	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5378	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5379	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5380	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5381	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5382	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5383	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5384	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5385	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5386	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5387	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5388	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5389	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5390	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5391	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5392	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5393	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5394	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5395	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5396	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5397	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5398	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5399	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5400	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5401
		5402	/***************** Bit definition for CAN_F9R2 register *****************/
		5403	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5404	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5405	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5406	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5407	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5408	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5409	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5410	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5411	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5412	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5413	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5414	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5415	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5416	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5417	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5418	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5419	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5420	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5421	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5422	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5423	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5424	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5425	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5426	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5427	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5428	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5429	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5430	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5431	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5432	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5433	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5434	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5435
		5436	/***************** Bit definition for CAN_F10R2 register ****************/
		5437	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5438	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5439	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5440	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5441	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5442	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5443	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5444	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5445	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5446	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5447	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5448	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5449	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5450	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5451	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5452	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5453	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5454	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5455	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5456	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5457	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5458	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5459	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5460	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5461	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5462	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5463	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5464	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5465	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5466	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5467	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5468	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5469
		5470	/***************** Bit definition for CAN_F11R2 register ****************/
		5471	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5472	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5473	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5474	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5475	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5476	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5477	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5478	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5479	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5480	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5481	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5482	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5483	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5484	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5485	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5486	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5487	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5488	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5489	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5490	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5491	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5492	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5493	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5494	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5495	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5496	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5497	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5498	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5499	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5500	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5501	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5502	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5503
		5504	/***************** Bit definition for CAN_F12R2 register ****************/
		5505	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5506	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5507	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5508	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5509	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5510	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5511	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5512	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5513	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5514	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5515	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5516	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5517	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5518	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5519	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5520	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5521	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5522	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5523	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5524	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5525	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5526	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5527	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5528	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5529	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5530	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5531	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5532	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5533	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5534	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5535	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5536	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5537
		5538	/***************** Bit definition for CAN_F13R2 register ****************/
		5539	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5540	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5541	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5542	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5543	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5544	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5545	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5546	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5547	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5548	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5549	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5550	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5551	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5552	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5553	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5554	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5555	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5556	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5557	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5558	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5559	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5560	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5561	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5562	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5563	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5564	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5565	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5566	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5567	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5568	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5569	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5570	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5571
		5572	/***************** Bit definition for CAN_F14R2 register ****************/
		5573	#define CAN_F14R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5574	#define CAN_F14R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5575	#define CAN_F14R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5576	#define CAN_F14R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5577	#define CAN_F14R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5578	#define CAN_F14R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5579	#define CAN_F14R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5580	#define CAN_F14R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5581	#define CAN_F14R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5582	#define CAN_F14R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5583	#define CAN_F14R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5584	#define CAN_F14R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5585	#define CAN_F14R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5586	#define CAN_F14R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5587	#define CAN_F14R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5588	#define CAN_F14R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5589	#define CAN_F14R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5590	#define CAN_F14R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5591	#define CAN_F14R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5592	#define CAN_F14R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5593	#define CAN_F14R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5594	#define CAN_F14R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5595	#define CAN_F14R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5596	#define CAN_F14R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5597	#define CAN_F14R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5598	#define CAN_F14R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5599	#define CAN_F14R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5600	#define CAN_F14R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5601	#define CAN_F14R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5602	#define CAN_F14R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5603	#define CAN_F14R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5604	#define CAN_F14R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5605
		5606	/***************** Bit definition for CAN_F15R2 register ****************/
		5607	#define CAN_F15R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5608	#define CAN_F15R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5609	#define CAN_F15R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5610	#define CAN_F15R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5611	#define CAN_F15R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5612	#define CAN_F15R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5613	#define CAN_F15R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5614	#define CAN_F15R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5615	#define CAN_F15R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5616	#define CAN_F15R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5617	#define CAN_F15R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5618	#define CAN_F15R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5619	#define CAN_F15R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5620	#define CAN_F15R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5621	#define CAN_F15R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5622	#define CAN_F15R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5623	#define CAN_F15R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5624	#define CAN_F15R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5625	#define CAN_F15R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5626	#define CAN_F15R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5627	#define CAN_F15R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5628	#define CAN_F15R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5629	#define CAN_F15R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5630	#define CAN_F15R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5631	#define CAN_F15R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5632	#define CAN_F15R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5633	#define CAN_F15R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5634	#define CAN_F15R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5635	#define CAN_F15R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5636	#define CAN_F15R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5637	#define CAN_F15R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5638	#define CAN_F15R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5639
		5640	/***************** Bit definition for CAN_F16R2 register ****************/
		5641	#define CAN_F16R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5642	#define CAN_F16R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5643	#define CAN_F16R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5644	#define CAN_F16R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5645	#define CAN_F16R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5646	#define CAN_F16R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5647	#define CAN_F16R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5648	#define CAN_F16R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5649	#define CAN_F16R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5650	#define CAN_F16R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5651	#define CAN_F16R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5652	#define CAN_F16R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5653	#define CAN_F16R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5654	#define CAN_F16R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5655	#define CAN_F16R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5656	#define CAN_F16R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5657	#define CAN_F16R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5658	#define CAN_F16R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5659	#define CAN_F16R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5660	#define CAN_F16R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5661	#define CAN_F16R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5662	#define CAN_F16R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5663	#define CAN_F16R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5664	#define CAN_F16R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5665	#define CAN_F16R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5666	#define CAN_F16R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5667	#define CAN_F16R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5668	#define CAN_F16R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5669	#define CAN_F16R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5670	#define CAN_F16R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5671	#define CAN_F16R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5672	#define CAN_F16R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5673
		5674	/***************** Bit definition for CAN_F17R2 register ****************/
		5675	#define CAN_F17R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5676	#define CAN_F17R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5677	#define CAN_F17R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5678	#define CAN_F17R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5679	#define CAN_F17R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5680	#define CAN_F17R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5681	#define CAN_F17R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5682	#define CAN_F17R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5683	#define CAN_F17R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5684	#define CAN_F17R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5685	#define CAN_F17R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5686	#define CAN_F17R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5687	#define CAN_F17R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5688	#define CAN_F17R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5689	#define CAN_F17R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5690	#define CAN_F17R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5691	#define CAN_F17R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5692	#define CAN_F17R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5693	#define CAN_F17R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5694	#define CAN_F17R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5695	#define CAN_F17R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5696	#define CAN_F17R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5697	#define CAN_F17R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5698	#define CAN_F17R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5699	#define CAN_F17R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5700	#define CAN_F17R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5701	#define CAN_F17R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5702	#define CAN_F17R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5703	#define CAN_F17R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5704	#define CAN_F17R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5705	#define CAN_F17R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5706	#define CAN_F17R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5707
		5708	/***************** Bit definition for CAN_F18R2 register ****************/
		5709	#define CAN_F18R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5710	#define CAN_F18R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5711	#define CAN_F18R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5712	#define CAN_F18R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5713	#define CAN_F18R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5714	#define CAN_F18R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5715	#define CAN_F18R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5716	#define CAN_F18R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5717	#define CAN_F18R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5718	#define CAN_F18R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5719	#define CAN_F18R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5720	#define CAN_F18R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5721	#define CAN_F18R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5722	#define CAN_F18R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5723	#define CAN_F18R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5724	#define CAN_F18R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5725	#define CAN_F18R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5726	#define CAN_F18R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5727	#define CAN_F18R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5728	#define CAN_F18R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5729	#define CAN_F18R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5730	#define CAN_F18R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5731	#define CAN_F18R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5732	#define CAN_F18R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5733	#define CAN_F18R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5734	#define CAN_F18R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5735	#define CAN_F18R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5736	#define CAN_F18R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5737	#define CAN_F18R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5738	#define CAN_F18R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5739	#define CAN_F18R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5740	#define CAN_F18R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5741
		5742	/***************** Bit definition for CAN_F19R2 register ****************/
		5743	#define CAN_F19R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5744	#define CAN_F19R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5745	#define CAN_F19R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5746	#define CAN_F19R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5747	#define CAN_F19R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5748	#define CAN_F19R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5749	#define CAN_F19R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5750	#define CAN_F19R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5751	#define CAN_F19R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5752	#define CAN_F19R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5753	#define CAN_F19R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5754	#define CAN_F19R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5755	#define CAN_F19R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5756	#define CAN_F19R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5757	#define CAN_F19R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5758	#define CAN_F19R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5759	#define CAN_F19R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5760	#define CAN_F19R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5761	#define CAN_F19R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5762	#define CAN_F19R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5763	#define CAN_F19R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5764	#define CAN_F19R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5765	#define CAN_F19R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5766	#define CAN_F19R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5767	#define CAN_F19R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5768	#define CAN_F19R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5769	#define CAN_F19R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5770	#define CAN_F19R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5771	#define CAN_F19R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5772	#define CAN_F19R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5773	#define CAN_F19R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5774	#define CAN_F19R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5775
		5776	/***************** Bit definition for CAN_F20R2 register ****************/
		5777	#define CAN_F20R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5778	#define CAN_F20R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5779	#define CAN_F20R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5780	#define CAN_F20R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5781	#define CAN_F20R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5782	#define CAN_F20R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5783	#define CAN_F20R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5784	#define CAN_F20R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5785	#define CAN_F20R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5786	#define CAN_F20R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5787	#define CAN_F20R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5788	#define CAN_F20R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5789	#define CAN_F20R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5790	#define CAN_F20R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5791	#define CAN_F20R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5792	#define CAN_F20R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5793	#define CAN_F20R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5794	#define CAN_F20R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5795	#define CAN_F20R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5796	#define CAN_F20R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5797	#define CAN_F20R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5798	#define CAN_F20R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5799	#define CAN_F20R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5800	#define CAN_F20R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5801	#define CAN_F20R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5802	#define CAN_F20R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5803	#define CAN_F20R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5804	#define CAN_F20R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5805	#define CAN_F20R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5806	#define CAN_F20R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5807	#define CAN_F20R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5808	#define CAN_F20R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5809
		5810	/***************** Bit definition for CAN_F21R2 register ****************/
		5811	#define CAN_F21R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5812	#define CAN_F21R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5813	#define CAN_F21R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5814	#define CAN_F21R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5815	#define CAN_F21R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5816	#define CAN_F21R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5817	#define CAN_F21R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5818	#define CAN_F21R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5819	#define CAN_F21R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5820	#define CAN_F21R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5821	#define CAN_F21R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5822	#define CAN_F21R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5823	#define CAN_F21R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5824	#define CAN_F21R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5825	#define CAN_F21R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5826	#define CAN_F21R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5827	#define CAN_F21R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5828	#define CAN_F21R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5829	#define CAN_F21R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5830	#define CAN_F21R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5831	#define CAN_F21R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5832	#define CAN_F21R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5833	#define CAN_F21R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5834	#define CAN_F21R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5835	#define CAN_F21R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5836	#define CAN_F21R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5837	#define CAN_F21R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5838	#define CAN_F21R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5839	#define CAN_F21R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5840	#define CAN_F21R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5841	#define CAN_F21R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5842	#define CAN_F21R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5843
		5844	/***************** Bit definition for CAN_F22R2 register ****************/
		5845	#define CAN_F22R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5846	#define CAN_F22R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5847	#define CAN_F22R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5848	#define CAN_F22R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5849	#define CAN_F22R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5850	#define CAN_F22R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5851	#define CAN_F22R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5852	#define CAN_F22R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5853	#define CAN_F22R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5854	#define CAN_F22R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5855	#define CAN_F22R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5856	#define CAN_F22R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5857	#define CAN_F22R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5858	#define CAN_F22R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5859	#define CAN_F22R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5860	#define CAN_F22R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5861	#define CAN_F22R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5862	#define CAN_F22R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5863	#define CAN_F22R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5864	#define CAN_F22R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5865	#define CAN_F22R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5866	#define CAN_F22R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5867	#define CAN_F22R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5868	#define CAN_F22R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5869	#define CAN_F22R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5870	#define CAN_F22R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5871	#define CAN_F22R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5872	#define CAN_F22R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5873	#define CAN_F22R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5874	#define CAN_F22R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5875	#define CAN_F22R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5876	#define CAN_F22R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5877
		5878	/***************** Bit definition for CAN_F23R2 register ****************/
		5879	#define CAN_F23R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5880	#define CAN_F23R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5881	#define CAN_F23R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5882	#define CAN_F23R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5883	#define CAN_F23R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5884	#define CAN_F23R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5885	#define CAN_F23R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5886	#define CAN_F23R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5887	#define CAN_F23R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5888	#define CAN_F23R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5889	#define CAN_F23R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5890	#define CAN_F23R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5891	#define CAN_F23R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5892	#define CAN_F23R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5893	#define CAN_F23R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5894	#define CAN_F23R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5895	#define CAN_F23R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5896	#define CAN_F23R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5897	#define CAN_F23R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5898	#define CAN_F23R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5899	#define CAN_F23R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5900	#define CAN_F23R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5901	#define CAN_F23R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5902	#define CAN_F23R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5903	#define CAN_F23R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5904	#define CAN_F23R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5905	#define CAN_F23R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5906	#define CAN_F23R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5907	#define CAN_F23R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5908	#define CAN_F23R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5909	#define CAN_F23R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5910	#define CAN_F23R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5911
		5912	/***************** Bit definition for CAN_F24R2 register ****************/
		5913	#define CAN_F24R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5914	#define CAN_F24R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5915	#define CAN_F24R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5916	#define CAN_F24R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5917	#define CAN_F24R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5918	#define CAN_F24R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5919	#define CAN_F24R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5920	#define CAN_F24R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5921	#define CAN_F24R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5922	#define CAN_F24R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5923	#define CAN_F24R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5924	#define CAN_F24R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5925	#define CAN_F24R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5926	#define CAN_F24R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5927	#define CAN_F24R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5928	#define CAN_F24R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5929	#define CAN_F24R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5930	#define CAN_F24R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5931	#define CAN_F24R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5932	#define CAN_F24R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5933	#define CAN_F24R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5934	#define CAN_F24R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5935	#define CAN_F24R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5936	#define CAN_F24R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5937	#define CAN_F24R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5938	#define CAN_F24R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5939	#define CAN_F24R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5940	#define CAN_F24R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5941	#define CAN_F24R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5942	#define CAN_F24R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5943	#define CAN_F24R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5944	#define CAN_F24R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5945
		5946	/***************** Bit definition for CAN_F25R2 register ****************/
		5947	#define CAN_F25R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5948	#define CAN_F25R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5949	#define CAN_F25R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5950	#define CAN_F25R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5951	#define CAN_F25R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5952	#define CAN_F25R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5953	#define CAN_F25R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5954	#define CAN_F25R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5955	#define CAN_F25R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5956	#define CAN_F25R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5957	#define CAN_F25R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5958	#define CAN_F25R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5959	#define CAN_F25R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5960	#define CAN_F25R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5961	#define CAN_F25R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5962	#define CAN_F25R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5963	#define CAN_F25R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5964	#define CAN_F25R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5965	#define CAN_F25R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5966	#define CAN_F25R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5967	#define CAN_F25R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5968	#define CAN_F25R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5969	#define CAN_F25R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5970	#define CAN_F25R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5971	#define CAN_F25R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5972	#define CAN_F25R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5973	#define CAN_F25R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5974	#define CAN_F25R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5975	#define CAN_F25R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5976	#define CAN_F25R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5977	#define CAN_F25R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5978	#define CAN_F25R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5979
		5980	/***************** Bit definition for CAN_F26R2 register ****************/
		5981	#define CAN_F26R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5982	#define CAN_F26R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5983	#define CAN_F26R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5984	#define CAN_F26R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5985	#define CAN_F26R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5986	#define CAN_F26R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5987	#define CAN_F26R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5988	#define CAN_F26R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5989	#define CAN_F26R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5990	#define CAN_F26R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5991	#define CAN_F26R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5992	#define CAN_F26R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5993	#define CAN_F26R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5994	#define CAN_F26R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5995	#define CAN_F26R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5996	#define CAN_F26R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5997	#define CAN_F26R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5998	#define CAN_F26R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5999	#define CAN_F26R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		6000	#define CAN_F26R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		6001	#define CAN_F26R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		6002	#define CAN_F26R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		6003	#define CAN_F26R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		6004	#define CAN_F26R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		6005	#define CAN_F26R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		6006	#define CAN_F26R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		6007	#define CAN_F26R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		6008	#define CAN_F26R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		6009	#define CAN_F26R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		6010	#define CAN_F26R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		6011	#define CAN_F26R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		6012	#define CAN_F26R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		6013
		6014	/***************** Bit definition for CAN_F27R2 register ****************/
		6015	#define CAN_F27R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		6016	#define CAN_F27R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		6017	#define CAN_F27R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		6018	#define CAN_F27R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		6019	#define CAN_F27R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		6020	#define CAN_F27R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		6021	#define CAN_F27R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		6022	#define CAN_F27R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		6023	#define CAN_F27R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		6024	#define CAN_F27R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		6025	#define CAN_F27R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		6026	#define CAN_F27R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		6027	#define CAN_F27R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		6028	#define CAN_F27R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		6029	#define CAN_F27R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		6030	#define CAN_F27R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		6031	#define CAN_F27R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		6032	#define CAN_F27R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		6033	#define CAN_F27R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		6034	#define CAN_F27R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		6035	#define CAN_F27R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		6036	#define CAN_F27R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		6037	#define CAN_F27R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		6038	#define CAN_F27R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		6039	#define CAN_F27R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		6040	#define CAN_F27R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		6041	#define CAN_F27R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		6042	#define CAN_F27R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		6043	#define CAN_F27R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		6044	#define CAN_F27R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		6045	#define CAN_F27R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		6046	#define CAN_F27R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		6047
		6048	/******************************************************************************/
		6049	/* */
		6050	/* Serial Peripheral Interface */
		6051	/* */
		6052	/******************************************************************************/
		6053
		6054	/***************** Bit definition for SPI_CR1 register ******************/
		6055	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
		6056	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
		6057	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
		6058
		6059	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
		6060	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
		6061	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
		6062	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
		6063
		6064	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
		6065	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
		6066	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
		6067	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
		6068	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
		6069	#define SPI_CR1_DFF ((uint32_t)0x00000800) /!< Data Frame Format /
		6070	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
		6071	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
		6072	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
		6073	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
		6074
		6075	/***************** Bit definition for SPI_CR2 register ******************/
		6076	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
		6077	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
		6078	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
		6079	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
		6080	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
		6081	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
		6082
		6083	/****************** Bit definition for SPI_SR register ******************/
		6084	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
		6085	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
		6086	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
		6087	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
		6088	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
		6089	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
		6090	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
		6091	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
		6092
		6093	/****************** Bit definition for SPI_DR register ******************/
		6094	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!< Data Register /
		6095
		6096	/***************** Bit definition for SPI_CRCPR register ****************/
		6097	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!< CRC polynomial register /
		6098
		6099	/**************** Bit definition for SPI_RXCRCR register ****************/
		6100	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!< Rx CRC Register /
		6101
		6102	/**************** Bit definition for SPI_TXCRCR register ****************/
		6103	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!< Tx CRC Register /
		6104
		6105	/**************** Bit definition for SPI_I2SCFGR register ***************/
		6106	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!< Channel length (number of bits per audio channel) /
		6107
		6108	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!< DATLEN[1:0] bits (Data length to be transferred) /
		6109	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!< Bit 0 /
		6110	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!< Bit 1 /
		6111
		6112	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!< steady state clock polarity /
		6113
		6114	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!< I2SSTD[1:0] bits (I2S standard selection) /
		6115	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!< Bit 0 /
		6116	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!< Bit 1 /
		6117
		6118	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!< PCM frame synchronization /
		6119
		6120	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!< I2SCFG[1:0] bits (I2S configuration mode) /
		6121	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!< Bit 0 /
		6122	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!< Bit 1 /
		6123
		6124	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!< I2S Enable /
		6125	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!< I2S mode selection /
		6126
		6127	/**************** Bit definition for SPI_I2SPR register *****************/
		6128	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!< I2S Linear prescaler /
		6129	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!< Odd factor for the prescaler /
		6130	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!< Master Clock Output Enable /
		6131
		6132	/******************************************************************************/
		6133	/* */
		6134	/* Inter-integrated Circuit Interface */
		6135	/* */
		6136	/******************************************************************************/
		6137
		6138	/***************** Bit definition for I2C_CR1 register ******************/
		6139	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
		6140	#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /!< SMBus Mode /
		6141	#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /!< SMBus Type /
		6142	#define I2C_CR1_ENARP ((uint32_t)0x00000010) /!< ARP Enable /
		6143	#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /!< PEC Enable /
		6144	#define I2C_CR1_ENGC ((uint32_t)0x00000040) /!< General Call Enable /
		6145	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /!< Clock Stretching Disable (Slave mode) /
		6146	#define I2C_CR1_START ((uint32_t)0x00000100) /!< Start Generation /
		6147	#define I2C_CR1_STOP ((uint32_t)0x00000200) /!< Stop Generation /
		6148	#define I2C_CR1_ACK ((uint32_t)0x00000400) /!< Acknowledge Enable /
		6149	#define I2C_CR1_POS ((uint32_t)0x00000800) /!< Acknowledge/PEC Position (for data reception) /
		6150	#define I2C_CR1_PEC ((uint32_t)0x00001000) /!< Packet Error Checking /
		6151	#define I2C_CR1_ALERT ((uint32_t)0x00002000) /!< SMBus Alert /
		6152	#define I2C_CR1_SWRST ((uint32_t)0x00008000) /!< Software Reset /
		6153
		6154	/***************** Bit definition for I2C_CR2 register ******************/
		6155	#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
		6156	#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /!< Bit 0 /
		6157	#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /!< Bit 1 /
		6158	#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /!< Bit 2 /
		6159	#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /!< Bit 3 /
		6160	#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /!< Bit 4 /
		6161	#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /!< Bit 5 /
		6162
		6163	#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /!< Error Interrupt Enable /
		6164	#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /!< Event Interrupt Enable /
		6165	#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /!< Buffer Interrupt Enable /
		6166	#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /!< DMA Requests Enable /
		6167	#define I2C_CR2_LAST ((uint32_t)0x00001000) /!< DMA Last Transfer /
		6168
		6169	/***************** Bit definition for I2C_OAR1 register *****************/
		6170	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
		6171	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
		6172
		6173	#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
		6174	#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
		6175	#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
		6176	#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
		6177	#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
		6178	#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
		6179	#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
		6180	#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /!< Bit 7 /
		6181	#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /!< Bit 8 /
		6182	#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /!< Bit 9 /
		6183
		6184	#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /!< Addressing Mode (Slave mode) /
		6185
		6186	/***************** Bit definition for I2C_OAR2 register *****************/
		6187	#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /!< Dual addressing mode enable /
		6188	#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /!< Interface address /
		6189
		6190	/***************** Bit definition for I2C_SR1 register ******************/
		6191	#define I2C_SR1_SB ((uint32_t)0x00000001) /!< Start Bit (Master mode) /
		6192	#define I2C_SR1_ADDR ((uint32_t)0x00000002) /!< Address sent (master mode)/matched (slave mode) /
		6193	#define I2C_SR1_BTF ((uint32_t)0x00000004) /!< Byte Transfer Finished /
		6194	#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /!< 10-bit header sent (Master mode) /
		6195	#define I2C_SR1_STOPF ((uint32_t)0x00000010) /!< Stop detection (Slave mode) /
		6196	#define I2C_SR1_RXNE ((uint32_t)0x00000040) /!< Data Register not Empty (receivers) /
		6197	#define I2C_SR1_TXE ((uint32_t)0x00000080) /!< Data Register Empty (transmitters) /
		6198	#define I2C_SR1_BERR ((uint32_t)0x00000100) /!< Bus Error /
		6199	#define I2C_SR1_ARLO ((uint32_t)0x00000200) /!< Arbitration Lost (master mode) /
		6200	#define I2C_SR1_AF ((uint32_t)0x00000400) /!< Acknowledge Failure /
		6201	#define I2C_SR1_OVR ((uint32_t)0x00000800) /!< Overrun/Underrun /
		6202	#define I2C_SR1_PECERR ((uint32_t)0x00001000) /!< PEC Error in reception /
		6203	#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /!< Timeout or Tlow Error /
		6204	#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /!< SMBus Alert /
		6205
		6206	/***************** Bit definition for I2C_SR2 register ******************/
		6207	#define I2C_SR2_MSL ((uint32_t)0x00000001) /!< Master/Slave /
		6208	#define I2C_SR2_BUSY ((uint32_t)0x00000002) /!< Bus Busy /
		6209	#define I2C_SR2_TRA ((uint32_t)0x00000004) /!< Transmitter/Receiver /
		6210	#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /!< General Call Address (Slave mode) /
		6211	#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /!< SMBus Device Default Address (Slave mode) /
		6212	#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /!< SMBus Host Header (Slave mode) /
		6213	#define I2C_SR2_DUALF ((uint32_t)0x00000080) /!< Dual Flag (Slave mode) /
		6214	#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /!< Packet Error Checking Register /
		6215
		6216	/***************** Bit definition for I2C_CCR register ******************/
		6217	#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
		6218	#define I2C_CCR_DUTY ((uint32_t)0x00004000) /!< Fast Mode Duty Cycle /
		6219	#define I2C_CCR_FS ((uint32_t)0x00008000) /!< I2C Master Mode Selection /
		6220
		6221	/**************** Bit definition for I2C_TRISE register *****************/
		6222	#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
		6223
		6224	/******************************************************************************/
		6225	/* */
		6226	/* Universal Synchronous Asynchronous Receiver Transmitter */
		6227	/* */
		6228	/******************************************************************************/
		6229
		6230	/***************** Bit definition for USART_SR register *****************/
		6231	#define USART_SR_PE ((uint32_t)0x00000001) /!< Parity Error /
		6232	#define USART_SR_FE ((uint32_t)0x00000002) /!< Framing Error /
		6233	#define USART_SR_NE ((uint32_t)0x00000004) /!< Noise Error Flag /
		6234	#define USART_SR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
		6235	#define USART_SR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
		6236	#define USART_SR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
		6237	#define USART_SR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
		6238	#define USART_SR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
		6239	#define USART_SR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
		6240	#define USART_SR_CTS ((uint32_t)0x00000200) /!< CTS Flag /
		6241
		6242	/***************** Bit definition for USART_DR register *****************/
		6243	#define USART_DR_DR ((uint32_t)0x000001FF) /!< Data value /
		6244
		6245	/**************** Bit definition for USART_BRR register *****************/
		6246	#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
		6247	#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
		6248
		6249	/**************** Bit definition for USART_CR1 register *****************/
		6250	#define USART_CR1_SBK ((uint32_t)0x00000001) /!< Send Break /
		6251	#define USART_CR1_RWU ((uint32_t)0x00000002) /!< Receiver wakeup /
		6252	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
		6253	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
		6254	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
		6255	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
		6256	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
		6257	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< PE Interrupt Enable /
		6258	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
		6259	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
		6260	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
		6261	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Wakeup method /
		6262	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
		6263	#define USART_CR1_UE ((uint32_t)0x00002000) /!< USART Enable /
		6264
		6265	/**************** Bit definition for USART_CR2 register *****************/
		6266	#define USART_CR2_ADD ((uint32_t)0x0000000F) /!< Address of the USART node /
		6267	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
		6268	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
		6269	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
		6270	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
		6271	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
		6272	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
		6273
		6274	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
		6275	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
		6276	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
		6277
		6278	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
		6279
		6280	/**************** Bit definition for USART_CR3 register *****************/
		6281	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
		6282	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
		6283	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
		6284	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
		6285	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< Smartcard NACK enable /
		6286	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Smartcard mode enable /
		6287	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
		6288	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
		6289	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
		6290	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
		6291	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
		6292
		6293	/**************** Bit definition for USART_GTPR register ****************/
		6294	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
		6295	#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /!< Bit 0 /
		6296	#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /!< Bit 1 /
		6297	#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /!< Bit 2 /
		6298	#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /!< Bit 3 /
		6299	#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /!< Bit 4 /
		6300	#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /!< Bit 5 /
		6301	#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /!< Bit 6 /
		6302	#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /!< Bit 7 /
		6303
		6304	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< Guard time value /
		6305
		6306	/******************************************************************************/
		6307	/* */
		6308	/* Debug MCU */
		6309	/* */
		6310	/******************************************************************************/
		6311
		6312	/************** Bit definition for DBGMCU_IDCODE register ***************/
		6313	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
		6314
		6315	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
		6316	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
		6317	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
		6318	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
		6319	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
		6320	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
		6321	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
		6322	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
		6323	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
		6324	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
		6325	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
		6326	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
		6327	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
		6328	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
		6329	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
		6330	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
		6331	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
		6332
		6333	/**************** Bit definition for DBGMCU_CR register *****************/
		6334	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
		6335	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
		6336	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
		6337	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
		6338
		6339	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
		6340	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
		6341	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
		6342
		6343	#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /!< Debug Independent Watchdog stopped when Core is halted /
		6344	#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /!< Debug Window Watchdog stopped when Core is halted /
		6345	#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /!< TIM1 counter stopped when core is halted /
		6346	#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /!< TIM2 counter stopped when core is halted /
		6347	#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /!< TIM3 counter stopped when core is halted /
		6348	#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /!< TIM4 counter stopped when core is halted /
		6349	#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /!< Debug CAN1 stopped when Core is halted /
		6350	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /!< SMBUS timeout mode stopped when Core is halted /
		6351	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /!< SMBUS timeout mode stopped when Core is halted /
		6352	#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /!< TIM5 counter stopped when core is halted /
		6353	#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /!< TIM6 counter stopped when core is halted /
		6354	#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /!< TIM7 counter stopped when core is halted /
		6355	#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /!< Debug CAN2 stopped when Core is halted /
		6356	#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /!< Debug TIM9 stopped when Core is halted /
		6357	#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /!< Debug TIM10 stopped when Core is halted /
		6358	#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /!< Debug TIM11 stopped when Core is halted /
		6359
		6360	/******************************************************************************/
		6361	/* */
		6362	/* FLASH and Option Bytes Registers */
		6363	/* */
		6364	/******************************************************************************/
		6365	/***************** Bit definition for FLASH_ACR register ****************/
		6366	#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /!< LATENCY[2:0] bits (Latency) /
		6367	#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /!< Bit 0 /
		6368	#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /!< Bit 1 /
		6369	#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /!< Bit 2 /
		6370
		6371	#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /!< Flash Half Cycle Access Enable /
		6372	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
		6373	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
		6374
		6375	/**************** Bit definition for FLASH_KEYR register ****************/
		6376	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
		6377
		6378	#define RDP_KEY ((uint32_t)0x000000A5) /!< RDP Key /
		6379	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< FPEC Key1 /
		6380	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /!< FPEC Key2 /
		6381
		6382	/*************** Bit definition for FLASH_OPTKEYR register **************/
		6383	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
		6384
		6385	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
		6386	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
		6387
		6388	/**************** Bit definition for FLASH_SR register ******************/
		6389	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
		6390	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
		6391	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
		6392	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
		6393
		6394	/***************** Bit definition for FLASH_CR register *****************/
		6395	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
		6396	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
		6397	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
		6398	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
		6399	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
		6400	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
		6401	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
		6402	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
		6403	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
		6404	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
		6405
		6406	/***************** Bit definition for FLASH_AR register *****************/
		6407	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
		6408
		6409	/**************** Bit definition for FLASH_OBR register *****************/
		6410	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
		6411	#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /!< Read protection /
		6412
		6413	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /!< IWDG SW /
		6414	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /!< nRST_STOP /
		6415	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /!< nRST_STDBY /
		6416	#define FLASH_OBR_USER ((uint32_t)0x0000001C) /!< User Option Bytes /
		6417
		6418	/**************** Bit definition for FLASH_WRPR register ****************/
		6419	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
		6420
		6421	/----------------------------------------------------------------------------/
		6422
		6423	/**************** Bit definition for FLASH_RDP register *****************/
		6424	#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
		6425	#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
		6426
		6427	/**************** Bit definition for FLASH_USER register ****************/
		6428	#define FLASH_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
		6429	#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
		6430
		6431	/**************** Bit definition for FLASH_Data0 register ***************/
		6432	#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /!< User data storage option byte /
		6433	#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /!< User data storage complemented option byte /
		6434
		6435	/**************** Bit definition for FLASH_Data1 register ***************/
		6436	#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /!< User data storage option byte /
		6437	#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /!< User data storage complemented option byte /
		6438
		6439	/**************** Bit definition for FLASH_WRP0 register ****************/
		6440	#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
		6441	#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
		6442
		6443	/**************** Bit definition for FLASH_WRP1 register ****************/
		6444	#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
		6445	#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
		6446
		6447	/**************** Bit definition for FLASH_WRP2 register ****************/
		6448	#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
		6449	#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
		6450
		6451	/**************** Bit definition for FLASH_WRP3 register ****************/
		6452	#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
		6453	#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
		6454
		6455	/******************************************************************************/
		6456	/* Ethernet MAC Registers bits definitions */
		6457	/******************************************************************************/
		6458	/* Bit definition for Ethernet MAC Control Register register */
		6459	#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
		6460	#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
		6461	#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
		6462	#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
		6463	#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
		6464	#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
		6465	#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
		6466	#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
		6467	#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
		6468	#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
		6469	#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
		6470	#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
		6471	#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
		6472	#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
		6473	#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
		6474	#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
		6475	#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
		6476	#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
		6477	#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
		6478	#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
		6479	a transmission attempt during retries after a collision: 0 =< r <2^k */
		6480	#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
		6481	#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
		6482	#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
		6483	#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
		6484	#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
		6485	#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
		6486	#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
		6487
		6488	/* Bit definition for Ethernet MAC Frame Filter Register */
		6489	#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
		6490	#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
		6491	#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
		6492	#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
		6493	#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
		6494	#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
		6495	#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
		6496	#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
		6497	#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
		6498	#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
		6499	#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
		6500	#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
		6501	#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
		6502	#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
		6503
		6504	/* Bit definition for Ethernet MAC Hash Table High Register */
		6505	#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
		6506
		6507	/* Bit definition for Ethernet MAC Hash Table Low Register */
		6508	#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
		6509
		6510	/* Bit definition for Ethernet MAC MII Address Register */
		6511	#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
		6512	#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
		6513	#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
		6514	#define ETH_MACMIIAR_CR_DIV42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
		6515	#define ETH_MACMIIAR_CR_DIV16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
		6516	#define ETH_MACMIIAR_CR_DIV26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
		6517	#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
		6518	#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
		6519
		6520	/* Bit definition for Ethernet MAC MII Data Register */
		6521	#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
		6522
		6523	/* Bit definition for Ethernet MAC Flow Control Register */
		6524	#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
		6525	#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
		6526	#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
		6527	#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
		6528	#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
		6529	#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
		6530	#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
		6531	#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
		6532	#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
		6533	#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
		6534	#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
		6535
		6536	/* Bit definition for Ethernet MAC VLAN Tag Register */
		6537	#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
		6538	#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
		6539
		6540	/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
		6541	#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
		6542	/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
		6543	Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
		6544	/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
		6545	Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
		6546	Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
		6547	Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
		6548	Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
		6549	RSVD - Filter1 Command - RSVD - Filter0 Command
		6550	Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
		6551	Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
		6552	Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
		6553
		6554	/* Bit definition for Ethernet MAC PMT Control and Status Register */
		6555	#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
		6556	#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
		6557	#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
		6558	#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
		6559	#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
		6560	#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
		6561	#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
		6562
		6563	/* Bit definition for Ethernet MAC Status Register */
		6564	#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
		6565	#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
		6566	#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
		6567	#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
		6568	#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
		6569
		6570	/* Bit definition for Ethernet MAC Interrupt Mask Register */
		6571	#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
		6572	#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
		6573
		6574	/* Bit definition for Ethernet MAC Address0 High Register */
		6575	#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
		6576
		6577	/* Bit definition for Ethernet MAC Address0 Low Register */
		6578	#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
		6579
		6580	/* Bit definition for Ethernet MAC Address1 High Register */
		6581	#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
		6582	#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
		6583	#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
		6584	#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
		6585	#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
		6586	#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
		6587	#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
		6588	#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
		6589	#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
		6590	#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
		6591
		6592	/* Bit definition for Ethernet MAC Address1 Low Register */
		6593	#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
		6594
		6595	/* Bit definition for Ethernet MAC Address2 High Register */
		6596	#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
		6597	#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
		6598	#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
		6599	#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
		6600	#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
		6601	#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
		6602	#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
		6603	#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
		6604	#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
		6605	#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
		6606
		6607	/* Bit definition for Ethernet MAC Address2 Low Register */
		6608	#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
		6609
		6610	/* Bit definition for Ethernet MAC Address3 High Register */
		6611	#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
		6612	#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
		6613	#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
		6614	#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
		6615	#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
		6616	#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
		6617	#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
		6618	#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
		6619	#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
		6620	#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
		6621
		6622	/* Bit definition for Ethernet MAC Address3 Low Register */
		6623	#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
		6624
		6625	/******************************************************************************/
		6626	/* Ethernet MMC Registers bits definition */
		6627	/******************************************************************************/
		6628
		6629	/* Bit definition for Ethernet MMC Contol Register */
		6630	#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
		6631	#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
		6632	#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
		6633	#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
		6634
		6635	/* Bit definition for Ethernet MMC Receive Interrupt Register */
		6636	#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
		6637	#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
		6638	#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
		6639
		6640	/* Bit definition for Ethernet MMC Transmit Interrupt Register */
		6641	#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
		6642	#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
		6643	#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
		6644
		6645	/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
		6646	#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
		6647	#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
		6648	#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
		6649
		6650	/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
		6651	#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
		6652	#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
		6653	#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
		6654
		6655	/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
		6656	#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
		6657
		6658	/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
		6659	#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
		6660
		6661	/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
		6662	#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
		6663
		6664	/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
		6665	#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
		6666
		6667	/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
		6668	#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
		6669
		6670	/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
		6671	#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
		6672
		6673	/******************************************************************************/
		6674	/* Ethernet PTP Registers bits definition */
		6675	/******************************************************************************/
		6676
		6677	/* Bit definition for Ethernet PTP Time Stamp Contol Register */
		6678	#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
		6679	#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
		6680	#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
		6681	#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
		6682	#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
		6683	#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
		6684
		6685	/* Bit definition for Ethernet PTP Sub-Second Increment Register */
		6686	#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
		6687
		6688	/* Bit definition for Ethernet PTP Time Stamp High Register */
		6689	#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
		6690
		6691	/* Bit definition for Ethernet PTP Time Stamp Low Register */
		6692	#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
		6693	#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
		6694
		6695	/* Bit definition for Ethernet PTP Time Stamp High Update Register */
		6696	#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
		6697
		6698	/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
		6699	#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
		6700	#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
		6701
		6702	/* Bit definition for Ethernet PTP Time Stamp Addend Register */
		6703	#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
		6704
		6705	/* Bit definition for Ethernet PTP Target Time High Register */
		6706	#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
		6707
		6708	/* Bit definition for Ethernet PTP Target Time Low Register */
		6709	#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
		6710
		6711	/******************************************************************************/
		6712	/* Ethernet DMA Registers bits definition */
		6713	/******************************************************************************/
		6714
		6715	/* Bit definition for Ethernet DMA Bus Mode Register */
		6716	#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
		6717	#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
		6718	#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
		6719	#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
		6720	#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
		6721	#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
		6722	#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
		6723	#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
		6724	#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
		6725	#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
		6726	#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
		6727	#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
		6728	#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
		6729	#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
		6730	#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
		6731	#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
		6732	#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
		6733	#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
		6734	#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
		6735	#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
		6736	#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
		6737	#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
		6738	#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
		6739	#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
		6740	#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
		6741	#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
		6742	#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
		6743	#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
		6744	#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
		6745	#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
		6746	#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
		6747	#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
		6748	#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
		6749	#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
		6750	#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
		6751	#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
		6752	#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
		6753	#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
		6754
		6755	/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
		6756	#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
		6757
		6758	/* Bit definition for Ethernet DMA Receive Poll Demand Register */
		6759	#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
		6760
		6761	/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
		6762	#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
		6763
		6764	/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
		6765	#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
		6766
		6767	/* Bit definition for Ethernet DMA Status Register */
		6768	#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
		6769	#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
		6770	#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
		6771	#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
		6772	/* combination with EBS[2:0] for GetFlagStatus function */
		6773	#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
		6774	#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
		6775	#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
		6776	#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
		6777	#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
		6778	#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
		6779	#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
		6780	#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
		6781	#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
		6782	#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
		6783	#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
		6784	#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
		6785	#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
		6786	#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
		6787	#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
		6788	#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
		6789	#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
		6790	#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
		6791	#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
		6792	#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
		6793	#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
		6794	#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
		6795	#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
		6796	#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
		6797	#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
		6798	#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
		6799	#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
		6800	#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
		6801	#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
		6802	#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
		6803	#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
		6804	#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
		6805
		6806	/* Bit definition for Ethernet DMA Operation Mode Register */
		6807	#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
		6808	#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
		6809	#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
		6810	#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
		6811	#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
		6812	#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
		6813	#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
		6814	#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
		6815	#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
		6816	#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
		6817	#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
		6818	#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
		6819	#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
		6820	#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
		6821	#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
		6822	#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
		6823	#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
		6824	#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
		6825	#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
		6826	#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
		6827	#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
		6828	#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
		6829	#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
		6830	#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
		6831
		6832	/* Bit definition for Ethernet DMA Interrupt Enable Register */
		6833	#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
		6834	#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
		6835	#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
		6836	#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
		6837	#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
		6838	#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
		6839	#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
		6840	#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
		6841	#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
		6842	#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
		6843	#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
		6844	#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
		6845	#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
		6846	#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
		6847	#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
		6848
		6849	/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
		6850	#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
		6851	#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
		6852	#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
		6853	#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
		6854
		6855	/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
		6856	#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
		6857
		6858	/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
		6859	#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
		6860
		6861	/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
		6862	#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
		6863
		6864	/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
		6865	#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
		6866
		6867	/******************************************************************************/
		6868	/* */
		6869	/* USB_OTG */
		6870	/* */
		6871	/******************************************************************************/
		6872
		6873	/****************** Bit definition forUSB_OTG_GOTGCTL register ******************/
		6874	#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /!< Session request success /
		6875	#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /!< Session request /
		6876	#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /!< Host negotiation success /
		6877	#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /!< HNP request /
		6878	#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /!< Host set HNP enable /
		6879	#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /!< Device HNP enabled /
		6880	#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /!< Connector ID status /
		6881	#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /!< Long/short debounce time /
		6882	#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /!< A-session valid /
		6883	#define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /!< B-session valid /
		6884
		6885	/****************** Bit definition forUSB_OTG_HCFG register ******************/
		6886
		6887	#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /!< FS/LS PHY clock select /
		6888	#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /!<Bit 0 /
		6889	#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /!<Bit 1 /
		6890	#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /!< FS- and LS-only support /
		6891
		6892	/****************** Bit definition forUSB_OTG_DCFG register ******************/
		6893
		6894	#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /!< Device speed /
		6895	#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /!<Bit 0 /
		6896	#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /!<Bit 1 /
		6897	#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /!< Nonzero-length status OUT handshake /
		6898
		6899	#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /!< Device address /
		6900	#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /!<Bit 0 /
		6901	#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /!<Bit 1 /
		6902	#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /!<Bit 2 /
		6903	#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /!<Bit 3 /
		6904	#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /!<Bit 4 /
		6905	#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /!<Bit 5 /
		6906	#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /!<Bit 6 /
		6907
		6908	#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /!< Periodic (micro)frame interval /
		6909	#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /!<Bit 0 /
		6910	#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /!<Bit 1 /
		6911
		6912	#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /!< Periodic scheduling interval /
		6913	#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /!<Bit 0 /
		6914	#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /!<Bit 1 /
		6915
		6916	/****************** Bit definition forUSB_OTG_PCGCR register ******************/
		6917	#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /!< Stop PHY clock /
		6918	#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /!< Gate HCLK /
		6919	#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /!< PHY suspended /
		6920
		6921	/****************** Bit definition forUSB_OTG_GOTGINT register ****************/
		6922	#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /!< Session end detected /
		6923	#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /!< Session request success status change /
		6924	#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /!< Host negotiation success status change /
		6925	#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /!< Host negotiation detected /
		6926	#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /!< A-device timeout change /
		6927	#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /!< Debounce done /
		6928
		6929	/****************** Bit definition forUSB_OTG_DCTL register ******************/
		6930	#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /!< Remote wakeup signaling /
		6931	#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /!< Soft disconnect /
		6932	#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /!< Global IN NAK status /
		6933	#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /!< Global OUT NAK status /
		6934
		6935	#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /!< Test control /
		6936	#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /!<Bit 0 /
		6937	#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /!<Bit 1 /
		6938	#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /!<Bit 2 /
		6939	#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /!< Set global IN NAK /
		6940	#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /!< Clear global IN NAK /
		6941	#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /!< Set global OUT NAK /
		6942	#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /!< Clear global OUT NAK /
		6943	#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /!< Power-on programming done /
		6944
		6945	/****************** Bit definition forUSB_OTG_HFIR register ******************/
		6946	#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /!< Frame interval /
		6947
		6948	/****************** Bit definition forUSB_OTG_HFNUM register ******************/
		6949	#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /!< Frame number /
		6950	#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /!< Frame time remaining /
		6951
		6952	/****************** Bit definition forUSB_OTG_DSTS register ******************/
		6953	#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /!< Suspend status /
		6954
		6955	#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /!< Enumerated speed /
		6956	#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /!<Bit 0 /
		6957	#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /!<Bit 1 /
		6958	#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /!< Erratic error /
		6959	#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /!< Frame number of the received SOF /
		6960
		6961	/****************** Bit definition forUSB_OTG_GAHBCFG register ***************/
		6962	#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /!< Global interrupt mask /
		6963
		6964	#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /!< Burst length/type /
		6965	#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
		6966	#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
		6967	#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /!<Bit 2 /
		6968	#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /!<Bit 3 /
		6969	#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /!< DMA enable /
		6970	#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /!< TxFIFO empty level /
		6971	#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /!< Periodic TxFIFO empty level /
		6972
		6973	/****************** Bit definition forUSB_OTG_GUSBCFG register ***************/
		6974
		6975	#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /!< FS timeout calibration /
		6976	#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /!<Bit 0 /
		6977	#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /!<Bit 1 /
		6978	#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /!<Bit 2 /
		6979	#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select /
		6980	#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /!< SRP-capable /
		6981	#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /!< HNP-capable /
		6982
		6983	#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /!< USB turnaround time /
		6984	#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /!<Bit 0 /
		6985	#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /!<Bit 1 /
		6986	#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /!<Bit 2 /
		6987	#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /!<Bit 3 /
		6988	#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /!< PHY Low-power clock select /
		6989	#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /!< ULPI FS/LS select /
		6990	#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /!< ULPI Auto-resume /
		6991	#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /!< ULPI Clock SuspendM /
		6992	#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /!< ULPI External VBUS Drive /
		6993	#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /!< ULPI external VBUS indicator /
		6994	#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /!< TermSel DLine pulsing selection /
		6995	#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /!< Indicator complement /
		6996	#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /!< Indicator pass through /
		6997	#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /!< ULPI interface protect disable /
		6998	#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /!< Forced host mode /
		6999	#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /!< Forced peripheral mode /
		7000	#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /!< Corrupt Tx packet /
		7001
		7002	/****************** Bit definition forUSB_OTG_GRSTCTL register ***************/
		7003	#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /!< Core soft reset /
		7004	#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /!< HCLK soft reset /
		7005	#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /!< Host frame counter reset /
		7006	#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /!< RxFIFO flush /
		7007	#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /!< TxFIFO flush /
		7008
		7009	#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /!< TxFIFO number /
		7010	#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /!<Bit 0 /
		7011	#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /!<Bit 1 /
		7012	#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /!<Bit 2 /
		7013	#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /!<Bit 3 /
		7014	#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /!<Bit 4 /
		7015	#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /!< DMA request signal /
		7016	#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /!< AHB master idle /
		7017
		7018	/****************** Bit definition forUSB_OTG_DIEPMSK register ***************/
		7019	#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
		7020	#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
		7021	#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
		7022	#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
		7023	#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
		7024	#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
		7025	#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
		7026	#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
		7027
		7028	/****************** Bit definition forUSB_OTG_HPTXSTS register ***************/
		7029	#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /!< Periodic transmit data FIFO space available /
		7030
		7031	#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /!< Periodic transmit request queue space available /
		7032	#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
		7033	#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
		7034	#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
		7035	#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
		7036	#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
		7037	#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
		7038	#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
		7039	#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
		7040
		7041	#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /!< Top of the periodic transmit request queue /
		7042	#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
		7043	#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
		7044	#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
		7045	#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
		7046	#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
		7047	#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
		7048	#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
		7049	#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /!<Bit 7 /
		7050
		7051	/****************** Bit definition forUSB_OTG_HAINT register *****************/
		7052	#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /!< Channel interrupts /
		7053
		7054	/****************** Bit definition forUSB_OTG_DOEPMSK register ***************/
		7055	#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
		7056	#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
		7057	#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /!< SETUP phase done mask /
		7058	#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled mask /
		7059	#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received mask /
		7060	#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /!< OUT packet error mask /
		7061	#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
		7062
		7063	/****************** Bit definition forUSB_OTG_GINTSTS register ***************/
		7064	#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /!< Current mode of operation /
		7065	#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /!< Mode mismatch interrupt /
		7066	#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt /
		7067	#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /!< Start of frame /
		7068	#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /!< RxFIFO nonempty /
		7069	#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty /
		7070	#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /!< Global IN nonperiodic NAK effective /
		7071	#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /!< Global OUT NAK effective /
		7072	#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /!< Early suspend /
		7073	#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /!< USB suspend /
		7074	#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /!< USB reset /
		7075	#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /!< Enumeration done /
		7076	#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt /
		7077	#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /!< End of periodic frame interrupt /
		7078	#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /!< IN endpoint interrupt /
		7079	#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /!< OUT endpoint interrupt /
		7080	#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer /
		7081	#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /!< Incomplete periodic transfer /
		7082	#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /!< Data fetch suspended /
		7083	#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /!< Host port interrupt /
		7084	#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /!< Host channels interrupt /
		7085	#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /!< Periodic TxFIFO empty /
		7086	#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /!< Connector ID status change /
		7087	#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt /
		7088	#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /!< Session request/new session detected interrupt /
		7089	#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt /
		7090
		7091	/****************** Bit definition forUSB_OTG_GINTMSK register ***************/
		7092	#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /!< Mode mismatch interrupt mask /
		7093	#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt mask /
		7094	#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /!< Start of frame mask /
		7095	#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /!< Receive FIFO nonempty mask /
		7096	#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty mask /
		7097	#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /!< Global nonperiodic IN NAK effective mask /
		7098	#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /!< Global OUT NAK effective mask /
		7099	#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /!< Early suspend mask /
		7100	#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /!< USB suspend mask /
		7101	#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /!< USB reset mask /
		7102	#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /!< Enumeration done mask /
		7103	#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt mask /
		7104	#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /!< End of periodic frame interrupt mask /
		7105	#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /!< Endpoint mismatch interrupt mask /
		7106	#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /!< IN endpoints interrupt mask /
		7107	#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /!< OUT endpoints interrupt mask /
		7108	#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer mask /
		7109	#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /!< Incomplete periodic transfer mask /
		7110	#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /!< Data fetch suspended mask /
		7111	#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /!< Host port interrupt mask /
		7112	#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /!< Host channels interrupt mask /
		7113	#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /!< Periodic TxFIFO empty mask /
		7114	#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /!< Connector ID status change mask /
		7115	#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt mask /
		7116	#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /!< Session request/new session detected interrupt mask /
		7117	#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt mask /
		7118
		7119	/****************** Bit definition forUSB_OTG_DAINT register *****************/
		7120	#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /!< IN endpoint interrupt bits /
		7121	#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /!< OUT endpoint interrupt bits /
		7122
		7123	/****************** Bit definition forUSB_OTG_HAINTMSK register **************/
		7124	#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /!< Channel interrupt mask /
		7125
		7126	/****************** Bit definition for USB_OTG_GRXSTSP register **************/
		7127	#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /!< IN EP interrupt mask bits /
		7128	#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /!< OUT EP interrupt mask bits /
		7129	#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /!< OUT EP interrupt mask bits /
		7130	#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /!< OUT EP interrupt mask bits /
		7131
		7132	/****************** Bit definition forUSB_OTG_DAINTMSK register **************/
		7133	#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /!< IN EP interrupt mask bits /
		7134	#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /!< OUT EP interrupt mask bits /
		7135
		7136	/****************** Bit definition for OTG register **************************/
		7137	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
		7138	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
		7139	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
		7140	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
		7141	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
		7142	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
		7143
		7144	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
		7145	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
		7146	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
		7147
		7148	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
		7149	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
		7150	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
		7151	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
		7152	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
		7153
		7154	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
		7155	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
		7156	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
		7157	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
		7158	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
		7159
		7160	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
		7161	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
		7162	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
		7163	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
		7164	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
		7165
		7166	/****************** Bit definition for OTG register **************************/
		7167	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
		7168	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
		7169	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
		7170	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
		7171	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
		7172	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
		7173
		7174	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
		7175	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
		7176	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
		7177
		7178	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
		7179	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
		7180	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
		7181	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
		7182	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
		7183
		7184	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
		7185	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
		7186	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
		7187	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
		7188	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
		7189
		7190	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
		7191	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
		7192	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
		7193	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
		7194	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
		7195
		7196	/****************** Bit definition forUSB_OTG_GRXFSIZ register ***************/
		7197	#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /!< RxFIFO depth /
		7198
		7199	/****************** Bit definition forUSB_OTG_DVBUSDIS register **************/
		7200	#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /!< Device VBUS discharge time /
		7201
		7202	/****************** Bit definition for OTG register **************************/
		7203	#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /!< Nonperiodic transmit RAM start address /
		7204	#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /!< Nonperiodic TxFIFO depth /
		7205	#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /!< Endpoint 0 transmit RAM start address /
		7206	#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /!< Endpoint 0 TxFIFO depth /
		7207
		7208	/****************** Bit definition forUSB_OTG_DVBUSPULSE register ************/
		7209	#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /!< Device VBUS pulsing time /
		7210
		7211	/****************** Bit definition forUSB_OTG_GNPTXSTS register **************/
		7212	#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /!< Nonperiodic TxFIFO space available /
		7213
		7214	#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /!< Nonperiodic transmit request queue space available /
		7215	#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
		7216	#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
		7217	#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
		7218	#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
		7219	#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
		7220	#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
		7221	#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
		7222	#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
		7223
		7224	#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /!< Top of the nonperiodic transmit request queue /
		7225	#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
		7226	#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
		7227	#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
		7228	#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
		7229	#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
		7230	#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
		7231	#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
		7232
		7233	/****************** Bit definition forUSB_OTG_DTHRCTL register ***************/
		7234	#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /!< Nonisochronous IN endpoints threshold enable /
		7235	#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /!< ISO IN endpoint threshold enable /
		7236
		7237	#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /!< Transmit threshold length /
		7238	#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /!<Bit 0 /
		7239	#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /!<Bit 1 /
		7240	#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /!<Bit 2 /
		7241	#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /!<Bit 3 /
		7242	#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /!<Bit 4 /
		7243	#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /!<Bit 5 /
		7244	#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /!<Bit 6 /
		7245	#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /!<Bit 7 /
		7246	#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /!<Bit 8 /
		7247	#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /!< Receive threshold enable /
		7248
		7249	#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /!< Receive threshold length /
		7250	#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /!<Bit 0 /
		7251	#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /!<Bit 1 /
		7252	#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /!<Bit 2 /
		7253	#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /!<Bit 3 /
		7254	#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /!<Bit 4 /
		7255	#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /!<Bit 5 /
		7256	#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /!<Bit 6 /
		7257	#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /!<Bit 7 /
		7258	#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /!<Bit 8 /
		7259	#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /!< Arbiter parking enable /
		7260
		7261	/****************** Bit definition forUSB_OTG_DIEPEMPMSK register ************/
		7262	#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /!< IN EP Tx FIFO empty interrupt mask bits /
		7263
		7264	/****************** Bit definition forUSB_OTG_DEACHINT register **************/
		7265	#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /!< IN endpoint 1interrupt bit /
		7266	#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /!< OUT endpoint 1 interrupt bit /
		7267
		7268	/****************** Bit definition forUSB_OTG_GCCFG register *****************/
		7269	#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /!< Power down /
		7270	#define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /!< Enable I2C bus connection for the external I2C PHY interface /
		7271	#define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /!< Enable the VBUS sensing device /
		7272	#define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /!< Enable the VBUS sensing device /
		7273	#define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /!< SOF output enable /
		7274	#define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /!< VBUS sensing disable option /
		7275
		7276	/****************** Bit definition forUSB_OTG_DEACHINTMSK register ***********/
		7277	#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /!< IN Endpoint 1 interrupt mask bit /
		7278	#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /!< OUT Endpoint 1 interrupt mask bit /
		7279
		7280	/****************** Bit definition forUSB_OTG_CID register *******************/
		7281	#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /!< Product ID field /
		7282
		7283	/****************** Bit definition forUSB_OTG_DIEPEACHMSK1 register **********/
		7284	#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
		7285	#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
		7286	#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
		7287	#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
		7288	#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
		7289	#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
		7290	#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
		7291	#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
		7292	#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
		7293
		7294	/****************** Bit definition forUSB_OTG_HPRT register ******************/
		7295	#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /!< Port connect status /
		7296	#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /!< Port connect detected /
		7297	#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /!< Port enable /
		7298	#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /!< Port enable/disable change /
		7299	#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /!< Port overcurrent active /
		7300	#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /!< Port overcurrent change /
		7301	#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /!< Port resume /
		7302	#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /!< Port suspend /
		7303	#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /!< Port reset /
		7304
		7305	#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /!< Port line status /
		7306	#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /!<Bit 0 /
		7307	#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /!<Bit 1 /
		7308	#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /!< Port power /
		7309
		7310	#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /!< Port test control /
		7311	#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /!<Bit 0 /
		7312	#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /!<Bit 1 /
		7313	#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /!<Bit 2 /
		7314	#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /!<Bit 3 /
		7315
		7316	#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /!< Port speed /
		7317	#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /!<Bit 0 /
		7318	#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /!<Bit 1 /
		7319
		7320	/****************** Bit definition forUSB_OTG_DOEPEACHMSK1 register **********/
		7321	#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
		7322	#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
		7323	#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask /
		7324	#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
		7325	#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
		7326	#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
		7327	#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< OUT packet error mask /
		7328	#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
		7329	#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /!< Bubble error interrupt mask /
		7330	#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
		7331	#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /!< NYET interrupt mask /
		7332
		7333	/****************** Bit definition forUSB_OTG_HPTXFSIZ register **************/
		7334	#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /!< Host periodic TxFIFO start address /
		7335	#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /!< Host periodic TxFIFO depth /
		7336
		7337	/****************** Bit definition forUSB_OTG_DIEPCTL register ***************/
		7338	#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
		7339	#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
		7340	#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /!< Even/odd frame /
		7341	#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
		7342
		7343	#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
		7344	#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
		7345	#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
		7346	#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
		7347
		7348	#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /!< TxFIFO number /
		7349	#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /!<Bit 0 /
		7350	#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /!<Bit 1 /
		7351	#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /!<Bit 2 /
		7352	#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /!<Bit 3 /
		7353	#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
		7354	#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
		7355	#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
		7356	#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
		7357	#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
		7358	#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
		7359
		7360	/****************** Bit definition forUSB_OTG_HCCHAR register ****************/
		7361	#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
		7362
		7363	#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /!< Endpoint number /
		7364	#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /!<Bit 0 /
		7365	#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /!<Bit 1 /
		7366	#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /!<Bit 2 /
		7367	#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /!<Bit 3 /
		7368	#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /!< Endpoint direction /
		7369	#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /!< Low-speed device /
		7370
		7371	#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
		7372	#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
		7373	#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
		7374
		7375	#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /!< Multi Count (MC) / Error Count (EC) /
		7376	#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /!<Bit 0 /
		7377	#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /!<Bit 1 /
		7378
		7379	#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /!< Device address /
		7380	#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /!<Bit 0 /
		7381	#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /!<Bit 1 /
		7382	#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /!<Bit 2 /
		7383	#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /!<Bit 3 /
		7384	#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /!<Bit 4 /
		7385	#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /!<Bit 5 /
		7386	#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /!<Bit 6 /
		7387	#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /!< Odd frame /
		7388	#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /!< Channel disable /
		7389	#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /!< Channel enable /
		7390
		7391	/****************** Bit definition forUSB_OTG_HCSPLT register ****************/
		7392
		7393	#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /!< Port address /
		7394	#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /!<Bit 0 /
		7395	#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /!<Bit 1 /
		7396	#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /!<Bit 2 /
		7397	#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /!<Bit 3 /
		7398	#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /!<Bit 4 /
		7399	#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /!<Bit 5 /
		7400	#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /!<Bit 6 /
		7401
		7402	#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /!< Hub address /
		7403	#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /!<Bit 0 /
		7404	#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /!<Bit 1 /
		7405	#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /!<Bit 2 /
		7406	#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /!<Bit 3 /
		7407	#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /!<Bit 4 /
		7408	#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /!<Bit 5 /
		7409	#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /!<Bit 6 /
		7410
		7411	#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /!< XACTPOS /
		7412	#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /!<Bit 0 /
		7413	#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /!<Bit 1 /
		7414	#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /!< Do complete split /
		7415	#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /!< Split enable /
		7416
		7417	/****************** Bit definition forUSB_OTG_HCINT register *****************/
		7418	#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed /
		7419	#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /!< Channel halted /
		7420	#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /!< AHB error /
		7421	#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /!< STALL response received interrupt /
		7422	#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /!< NAK response received interrupt /
		7423	#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt /
		7424	#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /!< Response received interrupt /
		7425	#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /!< Transaction error /
		7426	#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /!< Babble error /
		7427	#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /!< Frame overrun /
		7428	#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /!< Data toggle error /
		7429
		7430	/****************** Bit definition forUSB_OTG_DIEPINT register ***************/
		7431	#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
		7432	#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
		7433	#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /!< Timeout condition /
		7434	#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /!< IN token received when TxFIFO is empty /
		7435	#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /!< IN endpoint NAK effective /
		7436	#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /!< Transmit FIFO empty /
		7437	#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /!< Transmit Fifo Underrun /
		7438	#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /!< Buffer not available interrupt /
		7439	#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /!< Packet dropped status /
		7440	#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /!< Babble error interrupt /
		7441	#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /!< NAK interrupt /
		7442
		7443	/****************** Bit definition forUSB_OTG_HCINTMSK register **************/
		7444	#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed mask /
		7445	#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /!< Channel halted mask /
		7446	#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /!< AHB error /
		7447	#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /!< STALL response received interrupt mask /
		7448	#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /!< NAK response received interrupt mask /
		7449	#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt mask /
		7450	#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /!< response received interrupt mask /
		7451	#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /!< Transaction error mask /
		7452	#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /!< Babble error mask /
		7453	#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /!< Frame overrun mask /
		7454	#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /!< Data toggle error mask /
		7455
		7456	/****************** Bit definition for USB_OTG_DIEPTSIZ register *************/
		7457	#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
		7458	#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
		7459	#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /!< Packet count /
		7460
		7461	/****************** Bit definition forUSB_OTG_HCTSIZ register ****************/
		7462	#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
		7463	#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
		7464	#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /!< Do PING /
		7465	#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /!< Data PID /
		7466	#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /!<Bit 0 /
		7467	#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /!<Bit 1 /
		7468
		7469	/****************** Bit definition forUSB_OTG_DIEPDMA register ***************/
		7470	#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
		7471
		7472	/****************** Bit definition forUSB_OTG_HCDMA register *****************/
		7473	#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
		7474
		7475	/****************** Bit definition forUSB_OTG_DTXFSTS register ***************/
		7476	#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /!< IN endpoint TxFIFO space avail /
		7477
		7478	/****************** Bit definition forUSB_OTG_DIEPTXF register ***************/
		7479	#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /!< IN endpoint FIFOx transmit RAM start address /
		7480	#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /!< IN endpoint TxFIFO depth /
		7481
		7482	/****************** Bit definition forUSB_OTG_DOEPCTL register ***************/
		7483	#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
		7484	#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
		7485	#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
		7486	#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
		7487	#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
		7488	#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
		7489	#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
		7490	#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
		7491	#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /!< Snoop mode /
		7492	#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
		7493	#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
		7494	#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
		7495	#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
		7496	#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
		7497
		7498	/****************** Bit definition forUSB_OTG_DOEPINT register ***************/
		7499	#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
		7500	#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
		7501	#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /!< SETUP phase done /
		7502	#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled /
		7503	#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received /
		7504	#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /!< NYET interrupt /
		7505
		7506	/****************** Bit definition forUSB_OTG_DOEPTSIZ register **************/
		7507	#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
		7508	#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
		7509
		7510	#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /!< SETUP packet count /
		7511	#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /!<Bit 0 /
		7512	#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /!<Bit 1 /
		7513
		7514	/****************** Bit definition for PCGCCTL register **********************/
		7515	#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /!< SETUP packet count /
		7516	#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /!<Bit 0 /
		7517	#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /!<Bit 1 /
		7518
		7519	/**
		7520	* @}
		7521	*/
		7522
		7523	/**
		7524	* @}
		7525	*/
		7526
		7527	/** @addtogroup Exported_macro
		7528	* @{
		7529	*/
		7530
		7531	/**************************** ADC Instances *******************************/
		7532	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \|\| \
		7533	((INSTANCE) == ADC2))
		7534
		7535	#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		7536
		7537	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		7538
		7539
		7540	/**************************** CAN Instances *******************************/
		7541	#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) \|\| \
		7542	((INSTANCE) == CAN2))
		7543
		7544	/**************************** CRC Instances *******************************/
		7545	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		7546
		7547	/**************************** DAC Instances *******************************/
		7548	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
		7549
		7550	/**************************** DMA Instances *******************************/
		7551	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		7552	((INSTANCE) == DMA1_Channel2) \|\| \
		7553	((INSTANCE) == DMA1_Channel3) \|\| \
		7554	((INSTANCE) == DMA1_Channel4) \|\| \
		7555	((INSTANCE) == DMA1_Channel5) \|\| \
		7556	((INSTANCE) == DMA1_Channel6) \|\| \
		7557	((INSTANCE) == DMA1_Channel7) \|\| \
		7558	((INSTANCE) == DMA2_Channel1) \|\| \
		7559	((INSTANCE) == DMA2_Channel2) \|\| \
		7560	((INSTANCE) == DMA2_Channel3) \|\| \
		7561	((INSTANCE) == DMA2_Channel4) \|\| \
		7562	((INSTANCE) == DMA2_Channel5))
		7563
		7564	/***************************** GPIO Instances *****************************/
		7565	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		7566	((INSTANCE) == GPIOB) \|\| \
		7567	((INSTANCE) == GPIOC) \|\| \
		7568	((INSTANCE) == GPIOD) \|\| \
		7569	((INSTANCE) == GPIOE))
		7570
		7571	/************************** GPIO Alternate Function Instances *************/
		7572	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		7573
		7574	/************************** GPIO Lock Instances ***************************/
		7575	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		7576
		7577	/****************************** I2C Instances *****************************/
		7578	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		7579	((INSTANCE) == I2C2))
		7580
		7581	/****************************** I2S Instances *****************************/
		7582	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) \|\| \
		7583	((INSTANCE) == SPI3))
		7584
		7585	/**************************** IWDG Instances ******************************/
		7586	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		7587
		7588	/****************************** SPI Instances *****************************/
		7589	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		7590	((INSTANCE) == SPI2) \|\| \
		7591	((INSTANCE) == SPI3))
		7592
		7593	/**************************** START TIM Instances *************************/
		7594	/**************************** TIM Instances *******************************/
		7595	#define IS_TIM_INSTANCE(INSTANCE)\
		7596	(((INSTANCE) == TIM1) \|\| \
		7597	((INSTANCE) == TIM2) \|\| \
		7598	((INSTANCE) == TIM3) \|\| \
		7599	((INSTANCE) == TIM4) \|\| \
		7600	((INSTANCE) == TIM5) \|\| \
		7601	((INSTANCE) == TIM6) \|\| \
		7602	((INSTANCE) == TIM7))
		7603
		7604	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
		7605	(((INSTANCE) == TIM1) \|\| \
		7606	((INSTANCE) == TIM2) \|\| \
		7607	((INSTANCE) == TIM3) \|\| \
		7608	((INSTANCE) == TIM4) \|\| \
		7609	((INSTANCE) == TIM5))
		7610
		7611	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
		7612	(((INSTANCE) == TIM1) \|\| \
		7613	((INSTANCE) == TIM2) \|\| \
		7614	((INSTANCE) == TIM3) \|\| \
		7615	((INSTANCE) == TIM4) \|\| \
		7616	((INSTANCE) == TIM5))
		7617
		7618	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
		7619	(((INSTANCE) == TIM1) \|\| \
		7620	((INSTANCE) == TIM2) \|\| \
		7621	((INSTANCE) == TIM3) \|\| \
		7622	((INSTANCE) == TIM4) \|\| \
		7623	((INSTANCE) == TIM5))
		7624
		7625	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
		7626	(((INSTANCE) == TIM1) \|\| \
		7627	((INSTANCE) == TIM2) \|\| \
		7628	((INSTANCE) == TIM3) \|\| \
		7629	((INSTANCE) == TIM4) \|\| \
		7630	((INSTANCE) == TIM5))
		7631
		7632	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
		7633	(((INSTANCE) == TIM1) \|\| \
		7634	((INSTANCE) == TIM2) \|\| \
		7635	((INSTANCE) == TIM3) \|\| \
		7636	((INSTANCE) == TIM4) \|\| \
		7637	((INSTANCE) == TIM5))
		7638
		7639	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
		7640	(((INSTANCE) == TIM1) \|\| \
		7641	((INSTANCE) == TIM2) \|\| \
		7642	((INSTANCE) == TIM3) \|\| \
		7643	((INSTANCE) == TIM4) \|\| \
		7644	((INSTANCE) == TIM5))
		7645
		7646	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
		7647	(((INSTANCE) == TIM1) \|\| \
		7648	((INSTANCE) == TIM2) \|\| \
		7649	((INSTANCE) == TIM3) \|\| \
		7650	((INSTANCE) == TIM4) \|\| \
		7651	((INSTANCE) == TIM5))
		7652
		7653	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
		7654	(((INSTANCE) == TIM1) \|\| \
		7655	((INSTANCE) == TIM2) \|\| \
		7656	((INSTANCE) == TIM3) \|\| \
		7657	((INSTANCE) == TIM4) \|\| \
		7658	((INSTANCE) == TIM5))
		7659
		7660	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
		7661	(((INSTANCE) == TIM1) \|\| \
		7662	((INSTANCE) == TIM2) \|\| \
		7663	((INSTANCE) == TIM3) \|\| \
		7664	((INSTANCE) == TIM4) \|\| \
		7665	((INSTANCE) == TIM5))
		7666
		7667	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
		7668	(((INSTANCE) == TIM1) \|\| \
		7669	((INSTANCE) == TIM2) \|\| \
		7670	((INSTANCE) == TIM3) \|\| \
		7671	((INSTANCE) == TIM4) \|\| \
		7672	((INSTANCE) == TIM5))
		7673
		7674	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
		7675	(((INSTANCE) == TIM1) \|\| \
		7676	((INSTANCE) == TIM2) \|\| \
		7677	((INSTANCE) == TIM3) \|\| \
		7678	((INSTANCE) == TIM4) \|\| \
		7679	((INSTANCE) == TIM5))
		7680
		7681	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
		7682	(((INSTANCE) == TIM1) \|\| \
		7683	((INSTANCE) == TIM2) \|\| \
		7684	((INSTANCE) == TIM3) \|\| \
		7685	((INSTANCE) == TIM4) \|\| \
		7686	((INSTANCE) == TIM5) \|\| \
		7687	((INSTANCE) == TIM6) \|\| \
		7688	((INSTANCE) == TIM7))
		7689
		7690	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
		7691	(((INSTANCE) == TIM1) \|\| \
		7692	((INSTANCE) == TIM2) \|\| \
		7693	((INSTANCE) == TIM3) \|\| \
		7694	((INSTANCE) == TIM4) \|\| \
		7695	((INSTANCE) == TIM5))
		7696
		7697	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
		7698	(((INSTANCE) == TIM1) \|\| \
		7699	((INSTANCE) == TIM2) \|\| \
		7700	((INSTANCE) == TIM3) \|\| \
		7701	((INSTANCE) == TIM4) \|\| \
		7702	((INSTANCE) == TIM5))
		7703
		7704	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
		7705	((INSTANCE) == TIM1)
		7706
		7707	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		7708	((((INSTANCE) == TIM1) && \
		7709	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7710	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7711	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7712	((CHANNEL) == TIM_CHANNEL_4))) \
		7713	\|\| \
		7714	(((INSTANCE) == TIM2) && \
		7715	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7716	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7717	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7718	((CHANNEL) == TIM_CHANNEL_4))) \
		7719	\|\| \
		7720	(((INSTANCE) == TIM3) && \
		7721	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7722	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7723	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7724	((CHANNEL) == TIM_CHANNEL_4))) \
		7725	\|\| \
		7726	(((INSTANCE) == TIM4) && \
		7727	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7728	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7729	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7730	((CHANNEL) == TIM_CHANNEL_4))) \
		7731	\|\| \
		7732	(((INSTANCE) == TIM5) && \
		7733	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7734	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7735	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7736	((CHANNEL) == TIM_CHANNEL_4))))
		7737
		7738	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
		7739	(((INSTANCE) == TIM1) && \
		7740	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7741	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7742	((CHANNEL) == TIM_CHANNEL_3)))
		7743
		7744	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
		7745	(((INSTANCE) == TIM1) \|\| \
		7746	((INSTANCE) == TIM2) \|\| \
		7747	((INSTANCE) == TIM3) \|\| \
		7748	((INSTANCE) == TIM4) \|\| \
		7749	((INSTANCE) == TIM5))
		7750
		7751	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
		7752	((INSTANCE) == TIM1)
		7753
		7754	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
		7755	(((INSTANCE) == TIM1) \|\| \
		7756	((INSTANCE) == TIM2) \|\| \
		7757	((INSTANCE) == TIM3) \|\| \
		7758	((INSTANCE) == TIM4) \|\| \
		7759	((INSTANCE) == TIM5))
		7760
		7761	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
		7762	(((INSTANCE) == TIM1) \|\| \
		7763	((INSTANCE) == TIM2) \|\| \
		7764	((INSTANCE) == TIM3) \|\| \
		7765	((INSTANCE) == TIM4) \|\| \
		7766	((INSTANCE) == TIM5) \|\| \
		7767	((INSTANCE) == TIM6) \|\| \
		7768	((INSTANCE) == TIM7))
		7769
		7770	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
		7771	(((INSTANCE) == TIM1) \|\| \
		7772	((INSTANCE) == TIM2) \|\| \
		7773	((INSTANCE) == TIM3) \|\| \
		7774	((INSTANCE) == TIM4) \|\| \
		7775	((INSTANCE) == TIM5))
		7776
		7777	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
		7778	((INSTANCE) == TIM1)
		7779
		7780	/**************************** END TIM Instances ***************************/
		7781
		7782
		7783	/****************** USART Instances : Synchronous mode ********************/
		7784	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7785	((INSTANCE) == USART2) \|\| \
		7786	((INSTANCE) == USART3))
		7787
		7788	/****************** UART Instances : Asynchronous mode ********************/
		7789	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7790	((INSTANCE) == USART2) \|\| \
		7791	((INSTANCE) == USART3) \|\| \
		7792	((INSTANCE) == UART4) \|\| \
		7793	((INSTANCE) == UART5))
		7794
		7795	/****************** UART Instances : Half-Duplex mode ********************/
		7796	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7797	((INSTANCE) == USART2) \|\| \
		7798	((INSTANCE) == USART3) \|\| \
		7799	((INSTANCE) == UART4) \|\| \
		7800	((INSTANCE) == UART5))
		7801
		7802	/****************** UART Instances : LIN mode ********************/
		7803	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7804	((INSTANCE) == USART2) \|\| \
		7805	((INSTANCE) == USART3) \|\| \
		7806	((INSTANCE) == UART4) \|\| \
		7807	((INSTANCE) == UART5))
		7808
		7809	/**************** UART Instances : Hardware Flow control ******************/
		7810	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7811	((INSTANCE) == USART2) \|\| \
		7812	((INSTANCE) == USART3))
		7813
		7814	/******************* UART Instances : Smard card mode *********************/
		7815	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7816	((INSTANCE) == USART2) \|\| \
		7817	((INSTANCE) == USART3))
		7818
		7819	/********************* UART Instances : IRDA mode *************************/
		7820	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7821	((INSTANCE) == USART2) \|\| \
		7822	((INSTANCE) == USART3) \|\| \
		7823	((INSTANCE) == UART4) \|\| \
		7824	((INSTANCE) == UART5))
		7825
		7826	/*************** UART Instances : Multi-Processor mode ********************/
		7827	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7828	((INSTANCE) == USART2) \|\| \
		7829	((INSTANCE) == USART3) \|\| \
		7830	((INSTANCE) == UART4) \|\| \
		7831	((INSTANCE) == UART5))
		7832
		7833	/*************** UART Instances : DMA mode available ********************/
		7834	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7835	((INSTANCE) == USART2) \|\| \
		7836	((INSTANCE) == USART3) \|\| \
		7837	((INSTANCE) == UART4))
		7838
		7839	/**************************** RTC Instances *******************************/
		7840	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		7841
		7842	/************************** WWDG Instances ***************************/
		7843	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		7844
		7845
		7846	/**************************** USB Instances ******************************/
		7847	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
		7848
		7849	/**************************** USB Instances ******************************/
		7850	#define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH)
		7851
		7852
		7853	/**
		7854	* @}
		7855	*/
		7856	/******************************************************************************/
		7857	/* For a painless codes migration between the STM32F1xx device product */
		7858	/* lines, the aliases defined below are put in place to overcome the */
		7859	/* differences in the interrupt handlers and IRQn definitions. */
		7860	/* No need to update developed interrupt code when moving across */
		7861	/* product lines within the same STM32F1 Family */
		7862	/******************************************************************************/
		7863
		7864	/* Aliases for __IRQn */
		7865	#define ADC1_IRQn ADC1_2_IRQn
		7866	#define USB_LP_IRQn CAN1_RX0_IRQn
		7867	#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
		7868	#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
		7869	#define USB_HP_IRQn CAN1_TX_IRQn
		7870	#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
		7871	#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
		7872	#define CEC_IRQn OTG_FS_WKUP_IRQn
		7873	#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
		7874	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
		7875	#define TIM9_IRQn TIM1_BRK_IRQn
		7876	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
		7877	#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
		7878	#define TIM11_IRQn TIM1_TRG_COM_IRQn
		7879	#define TIM10_IRQn TIM1_UP_IRQn
		7880	#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
		7881	#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
		7882	#define TIM6_DAC_IRQn TIM6_IRQn
		7883
		7884
		7885	/* Aliases for __IRQHandler */
		7886	#define ADC1_IRQHandler ADC1_2_IRQHandler
		7887	#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
		7888	#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
		7889	#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
		7890	#define USB_HP_IRQHandler CAN1_TX_IRQHandler
		7891	#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
		7892	#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
		7893	#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
		7894	#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
		7895	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
		7896	#define TIM9_IRQHandler TIM1_BRK_IRQHandler
		7897	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
		7898	#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
		7899	#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
		7900	#define TIM10_IRQHandler TIM1_UP_IRQHandler
		7901	#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
		7902	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
		7903	#define TIM6_DAC_IRQHandler TIM6_IRQHandler
		7904
		7905
		7906	/**
		7907	* @}
		7908	*/
		7909
		7910	/**
		7911	* @}
		7912	*/
		7913
		7914
		7915	#ifdef __cplusplus
		7916	}
		7917	#endif /* __cplusplus */
		7918
		7919	#endif /* __STM32F107xC_H */
		7920
		7921
		7922
		7923	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h – Rev 2