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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f103xg.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V4.0.1 |
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| 6 | * @date 31-July-2015 |
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| 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
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| 8 | * This file contains all the peripheral register's definitions, bits |
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| 9 | * definitions and memory mapping for STM32F1xx devices. |
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| 10 | * |
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| 11 | * This file contains: |
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| 12 | * - Data structures and the address mapping for all peripherals |
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| 13 | * - Peripheral's registers declarations and bits definition |
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| 14 | * - Macros to access peripheral’s registers hardware |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | * @attention |
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| 18 | * |
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| 19 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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| 20 | * |
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| 21 | * Redistribution and use in source and binary forms, with or without modification, |
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| 22 | * are permitted provided that the following conditions are met: |
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| 23 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 24 | * this list of conditions and the following disclaimer. |
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| 25 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 26 | * this list of conditions and the following disclaimer in the documentation |
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| 27 | * and/or other materials provided with the distribution. |
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| 28 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 29 | * may be used to endorse or promote products derived from this software |
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| 30 | * without specific prior written permission. |
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| 31 | * |
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| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 33 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 34 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 35 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 36 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 37 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 38 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 39 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 40 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 41 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 42 | * |
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| 43 | ****************************************************************************** |
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| 44 | */ |
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| 45 | |||
| 46 | |||
| 47 | /** @addtogroup CMSIS |
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| 48 | * @{ |
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| 49 | */ |
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| 50 | |||
| 51 | /** @addtogroup stm32f103xg |
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| 52 | * @{ |
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| 53 | */ |
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| 54 | |||
| 55 | #ifndef __STM32F103xG_H |
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| 56 | #define __STM32F103xG_H |
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| 57 | |||
| 58 | #ifdef __cplusplus |
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| 59 | extern "C" { |
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| 60 | #endif |
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| 61 | |||
| 62 | /** @addtogroup Configuration_section_for_CMSIS |
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| 63 | * @{ |
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| 64 | */ |
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| 65 | /** |
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| 66 | * @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
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| 67 | */ |
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| 68 | #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ |
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| 69 | #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ |
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| 70 | #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ |
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| 71 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
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| 72 | |||
| 73 | /** |
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| 74 | * @} |
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| 75 | */ |
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| 76 | |||
| 77 | /** @addtogroup Peripheral_interrupt_number_definition |
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| 78 | * @{ |
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| 79 | */ |
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| 80 | |||
| 81 | /** |
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| 82 | * @brief STM32F10x Interrupt Number Definition, according to the selected device |
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| 83 | * in @ref Library_configuration_section |
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| 84 | */ |
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| 85 | |||
| 86 | /*!< Interrupt Number Definition */ |
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| 87 | typedef enum |
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| 88 | { |
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| 89 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
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| 90 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
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| 91 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
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| 92 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
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| 93 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
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| 94 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
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| 95 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
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| 96 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
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| 97 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
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| 98 | |||
| 99 | /****** STM32 specific Interrupt Numbers *********************************************************/ |
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| 100 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
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| 101 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
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| 102 | TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
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| 103 | RTC_IRQn = 3, /*!< RTC global Interrupt */ |
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| 104 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
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| 105 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
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| 106 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
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| 107 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
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| 108 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
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| 109 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
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| 110 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
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| 111 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
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| 112 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
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| 113 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
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| 114 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
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| 115 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
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| 116 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
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| 117 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
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| 118 | ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
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| 119 | USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ |
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| 120 | USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ |
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| 121 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
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| 122 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
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| 123 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
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| 124 | TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ |
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| 125 | TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ |
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| 126 | TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
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| 127 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
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| 128 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
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| 129 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
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| 130 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
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| 131 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
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| 132 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
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| 133 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
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| 134 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
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| 135 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
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| 136 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
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| 137 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
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| 138 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
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| 139 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
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| 140 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
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| 141 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
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| 142 | USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ |
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| 143 | TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ |
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| 144 | TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ |
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| 145 | TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ |
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| 146 | TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
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| 147 | ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
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| 148 | FSMC_IRQn = 48, /*!< FSMC global Interrupt */ |
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| 149 | SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
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| 150 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
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| 151 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
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| 152 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
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| 153 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
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| 154 | TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
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| 155 | TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
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| 156 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
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| 157 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
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| 158 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
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| 159 | DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ |
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| 160 | } IRQn_Type; |
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| 161 | |||
| 162 | |||
| 163 | /** |
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| 164 | * @} |
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| 165 | */ |
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| 166 | |||
| 167 | #include "core_cm3.h" |
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| 168 | #include "system_stm32f1xx.h" |
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| 169 | #include <stdint.h> |
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| 170 | |||
| 171 | /** @addtogroup Peripheral_registers_structures |
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| 172 | * @{ |
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| 173 | */ |
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| 174 | |||
| 175 | /** |
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| 176 | * @brief Analog to Digital Converter |
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| 177 | */ |
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| 178 | |||
| 179 | typedef struct |
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| 180 | { |
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| 181 | __IO uint32_t SR; |
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| 182 | __IO uint32_t CR1; |
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| 183 | __IO uint32_t CR2; |
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| 184 | __IO uint32_t SMPR1; |
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| 185 | __IO uint32_t SMPR2; |
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| 186 | __IO uint32_t JOFR1; |
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| 187 | __IO uint32_t JOFR2; |
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| 188 | __IO uint32_t JOFR3; |
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| 189 | __IO uint32_t JOFR4; |
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| 190 | __IO uint32_t HTR; |
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| 191 | __IO uint32_t LTR; |
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| 192 | __IO uint32_t SQR1; |
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| 193 | __IO uint32_t SQR2; |
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| 194 | __IO uint32_t SQR3; |
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| 195 | __IO uint32_t JSQR; |
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| 196 | __IO uint32_t JDR1; |
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| 197 | __IO uint32_t JDR2; |
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| 198 | __IO uint32_t JDR3; |
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| 199 | __IO uint32_t JDR4; |
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| 200 | __IO uint32_t DR; |
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| 201 | } ADC_TypeDef; |
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| 202 | |||
| 203 | /** |
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| 204 | * @brief Backup Registers |
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| 205 | */ |
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| 206 | |||
| 207 | typedef struct |
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| 208 | { |
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| 209 | uint32_t RESERVED0; |
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| 210 | __IO uint32_t DR1; |
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| 211 | __IO uint32_t DR2; |
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| 212 | __IO uint32_t DR3; |
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| 213 | __IO uint32_t DR4; |
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| 214 | __IO uint32_t DR5; |
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| 215 | __IO uint32_t DR6; |
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| 216 | __IO uint32_t DR7; |
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| 217 | __IO uint32_t DR8; |
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| 218 | __IO uint32_t DR9; |
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| 219 | __IO uint32_t DR10; |
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| 220 | __IO uint32_t RTCCR; |
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| 221 | __IO uint32_t CR; |
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| 222 | __IO uint32_t CSR; |
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| 223 | uint32_t RESERVED13[2]; |
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| 224 | __IO uint32_t DR11; |
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| 225 | __IO uint32_t DR12; |
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| 226 | __IO uint32_t DR13; |
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| 227 | __IO uint32_t DR14; |
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| 228 | __IO uint32_t DR15; |
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| 229 | __IO uint32_t DR16; |
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| 230 | __IO uint32_t DR17; |
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| 231 | __IO uint32_t DR18; |
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| 232 | __IO uint32_t DR19; |
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| 233 | __IO uint32_t DR20; |
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| 234 | __IO uint32_t DR21; |
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| 235 | __IO uint32_t DR22; |
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| 236 | __IO uint32_t DR23; |
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| 237 | __IO uint32_t DR24; |
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| 238 | __IO uint32_t DR25; |
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| 239 | __IO uint32_t DR26; |
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| 240 | __IO uint32_t DR27; |
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| 241 | __IO uint32_t DR28; |
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| 242 | __IO uint32_t DR29; |
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| 243 | __IO uint32_t DR30; |
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| 244 | __IO uint32_t DR31; |
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| 245 | __IO uint32_t DR32; |
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| 246 | __IO uint32_t DR33; |
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| 247 | __IO uint32_t DR34; |
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| 248 | __IO uint32_t DR35; |
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| 249 | __IO uint32_t DR36; |
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| 250 | __IO uint32_t DR37; |
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| 251 | __IO uint32_t DR38; |
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| 252 | __IO uint32_t DR39; |
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| 253 | __IO uint32_t DR40; |
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| 254 | __IO uint32_t DR41; |
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| 255 | __IO uint32_t DR42; |
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| 256 | } BKP_TypeDef; |
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| 257 | |||
| 258 | /** |
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| 259 | * @brief Controller Area Network TxMailBox |
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| 260 | */ |
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| 261 | |||
| 262 | typedef struct |
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| 263 | { |
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| 264 | __IO uint32_t TIR; |
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| 265 | __IO uint32_t TDTR; |
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| 266 | __IO uint32_t TDLR; |
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| 267 | __IO uint32_t TDHR; |
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| 268 | } CAN_TxMailBox_TypeDef; |
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| 269 | |||
| 270 | /** |
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| 271 | * @brief Controller Area Network FIFOMailBox |
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| 272 | */ |
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| 273 | |||
| 274 | typedef struct |
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| 275 | { |
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| 276 | __IO uint32_t RIR; |
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| 277 | __IO uint32_t RDTR; |
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| 278 | __IO uint32_t RDLR; |
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| 279 | __IO uint32_t RDHR; |
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| 280 | } CAN_FIFOMailBox_TypeDef; |
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| 281 | |||
| 282 | /** |
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| 283 | * @brief Controller Area Network FilterRegister |
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| 284 | */ |
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| 285 | |||
| 286 | typedef struct |
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| 287 | { |
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| 288 | __IO uint32_t FR1; |
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| 289 | __IO uint32_t FR2; |
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| 290 | } CAN_FilterRegister_TypeDef; |
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| 291 | |||
| 292 | /** |
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| 293 | * @brief Controller Area Network |
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| 294 | */ |
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| 295 | |||
| 296 | typedef struct |
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| 297 | { |
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| 298 | __IO uint32_t MCR; |
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| 299 | __IO uint32_t MSR; |
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| 300 | __IO uint32_t TSR; |
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| 301 | __IO uint32_t RF0R; |
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| 302 | __IO uint32_t RF1R; |
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| 303 | __IO uint32_t IER; |
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| 304 | __IO uint32_t ESR; |
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| 305 | __IO uint32_t BTR; |
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| 306 | uint32_t RESERVED0[88]; |
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| 307 | CAN_TxMailBox_TypeDef sTxMailBox[3]; |
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| 308 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; |
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| 309 | uint32_t RESERVED1[12]; |
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| 310 | __IO uint32_t FMR; |
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| 311 | __IO uint32_t FM1R; |
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| 312 | uint32_t RESERVED2; |
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| 313 | __IO uint32_t FS1R; |
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| 314 | uint32_t RESERVED3; |
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| 315 | __IO uint32_t FFA1R; |
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| 316 | uint32_t RESERVED4; |
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| 317 | __IO uint32_t FA1R; |
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| 318 | uint32_t RESERVED5[8]; |
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| 319 | CAN_FilterRegister_TypeDef sFilterRegister[14]; |
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| 320 | } CAN_TypeDef; |
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| 321 | |||
| 322 | /** |
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| 323 | * @brief CRC calculation unit |
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| 324 | */ |
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| 325 | |||
| 326 | typedef struct |
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| 327 | { |
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| 328 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
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| 329 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
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| 330 | uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ |
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| 331 | uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ |
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| 332 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
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| 333 | } CRC_TypeDef; |
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| 334 | |||
| 335 | /** |
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| 336 | * @brief Digital to Analog Converter |
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| 337 | */ |
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| 338 | |||
| 339 | typedef struct |
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| 340 | { |
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| 341 | __IO uint32_t CR; |
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| 342 | __IO uint32_t SWTRIGR; |
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| 343 | __IO uint32_t DHR12R1; |
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| 344 | __IO uint32_t DHR12L1; |
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| 345 | __IO uint32_t DHR8R1; |
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| 346 | __IO uint32_t DHR12R2; |
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| 347 | __IO uint32_t DHR12L2; |
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| 348 | __IO uint32_t DHR8R2; |
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| 349 | __IO uint32_t DHR12RD; |
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| 350 | __IO uint32_t DHR12LD; |
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| 351 | __IO uint32_t DHR8RD; |
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| 352 | __IO uint32_t DOR1; |
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| 353 | __IO uint32_t DOR2; |
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| 354 | } DAC_TypeDef; |
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| 355 | |||
| 356 | /** |
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| 357 | * @brief Debug MCU |
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| 358 | */ |
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| 359 | |||
| 360 | typedef struct |
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| 361 | { |
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| 362 | __IO uint32_t IDCODE; |
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| 363 | __IO uint32_t CR; |
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| 364 | }DBGMCU_TypeDef; |
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| 365 | |||
| 366 | /** |
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| 367 | * @brief DMA Controller |
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| 368 | */ |
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| 369 | |||
| 370 | typedef struct |
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| 371 | { |
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| 372 | __IO uint32_t CCR; |
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| 373 | __IO uint32_t CNDTR; |
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| 374 | __IO uint32_t CPAR; |
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| 375 | __IO uint32_t CMAR; |
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| 376 | } DMA_Channel_TypeDef; |
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| 377 | |||
| 378 | typedef struct |
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| 379 | { |
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| 380 | __IO uint32_t ISR; |
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| 381 | __IO uint32_t IFCR; |
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| 382 | } DMA_TypeDef; |
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| 383 | |||
| 384 | |||
| 385 | |||
| 386 | /** |
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| 387 | * @brief External Interrupt/Event Controller |
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| 388 | */ |
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| 389 | |||
| 390 | typedef struct |
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| 391 | { |
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| 392 | __IO uint32_t IMR; |
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| 393 | __IO uint32_t EMR; |
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| 394 | __IO uint32_t RTSR; |
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| 395 | __IO uint32_t FTSR; |
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| 396 | __IO uint32_t SWIER; |
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| 397 | __IO uint32_t PR; |
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| 398 | } EXTI_TypeDef; |
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| 399 | |||
| 400 | /** |
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| 401 | * @brief FLASH Registers |
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| 402 | */ |
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| 403 | |||
| 404 | typedef struct |
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| 405 | { |
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| 406 | __IO uint32_t ACR; |
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| 407 | __IO uint32_t KEYR; |
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| 408 | __IO uint32_t OPTKEYR; |
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| 409 | __IO uint32_t SR; |
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| 410 | __IO uint32_t CR; |
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| 411 | __IO uint32_t AR; |
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| 412 | __IO uint32_t RESERVED; |
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| 413 | __IO uint32_t OBR; |
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| 414 | __IO uint32_t WRPR; |
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| 415 | uint32_t RESERVED1[8]; |
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| 416 | __IO uint32_t KEYR2; |
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| 417 | uint32_t RESERVED2; |
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| 418 | __IO uint32_t SR2; |
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| 419 | __IO uint32_t CR2; |
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| 420 | __IO uint32_t AR2; |
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| 421 | } FLASH_TypeDef; |
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| 422 | |||
| 423 | /** |
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| 424 | * @brief Option Bytes Registers |
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| 425 | */ |
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| 426 | |||
| 427 | typedef struct |
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| 428 | { |
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| 429 | __IO uint16_t RDP; |
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| 430 | __IO uint16_t USER; |
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| 431 | __IO uint16_t Data0; |
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| 432 | __IO uint16_t Data1; |
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| 433 | __IO uint16_t WRP0; |
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| 434 | __IO uint16_t WRP1; |
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| 435 | __IO uint16_t WRP2; |
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| 436 | __IO uint16_t WRP3; |
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| 437 | } OB_TypeDef; |
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| 438 | |||
| 439 | /** |
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| 440 | * @brief Flexible Static Memory Controller |
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| 441 | */ |
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| 442 | |||
| 443 | typedef struct |
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| 444 | { |
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| 445 | __IO uint32_t BTCR[8]; |
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| 446 | } FSMC_Bank1_TypeDef; |
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| 447 | |||
| 448 | /** |
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| 449 | * @brief Flexible Static Memory Controller Bank1E |
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| 450 | */ |
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| 451 | |||
| 452 | typedef struct |
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| 453 | { |
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| 454 | __IO uint32_t BWTR[7]; |
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| 455 | } FSMC_Bank1E_TypeDef; |
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| 456 | |||
| 457 | /** |
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| 458 | * @brief Flexible Static Memory Controller Bank2 |
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| 459 | */ |
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| 460 | |||
| 461 | typedef struct |
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| 462 | { |
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| 463 | __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ |
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| 464 | __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ |
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| 465 | __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ |
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| 466 | __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ |
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| 467 | uint32_t RESERVED0; /*!< Reserved, 0x70 */ |
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| 468 | __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ |
||
| 469 | uint32_t RESERVED1; /*!< Reserved, 0x78 */ |
||
| 470 | uint32_t RESERVED2; /*!< Reserved, 0x7C */ |
||
| 471 | __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ |
||
| 472 | __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ |
||
| 473 | __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ |
||
| 474 | __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ |
||
| 475 | uint32_t RESERVED3; /*!< Reserved, 0x90 */ |
||
| 476 | __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ |
||
| 477 | } FSMC_Bank2_3_TypeDef; |
||
| 478 | |||
| 479 | /** |
||
| 480 | * @brief Flexible Static Memory Controller Bank4 |
||
| 481 | */ |
||
| 482 | |||
| 483 | typedef struct |
||
| 484 | { |
||
| 485 | __IO uint32_t PCR4; |
||
| 486 | __IO uint32_t SR4; |
||
| 487 | __IO uint32_t PMEM4; |
||
| 488 | __IO uint32_t PATT4; |
||
| 489 | __IO uint32_t PIO4; |
||
| 490 | } FSMC_Bank4_TypeDef; |
||
| 491 | |||
| 492 | /** |
||
| 493 | * @brief General Purpose I/O |
||
| 494 | */ |
||
| 495 | |||
| 496 | typedef struct |
||
| 497 | { |
||
| 498 | __IO uint32_t CRL; |
||
| 499 | __IO uint32_t CRH; |
||
| 500 | __IO uint32_t IDR; |
||
| 501 | __IO uint32_t ODR; |
||
| 502 | __IO uint32_t BSRR; |
||
| 503 | __IO uint32_t BRR; |
||
| 504 | __IO uint32_t LCKR; |
||
| 505 | } GPIO_TypeDef; |
||
| 506 | |||
| 507 | /** |
||
| 508 | * @brief Alternate Function I/O |
||
| 509 | */ |
||
| 510 | |||
| 511 | typedef struct |
||
| 512 | { |
||
| 513 | __IO uint32_t EVCR; |
||
| 514 | __IO uint32_t MAPR; |
||
| 515 | __IO uint32_t EXTICR[4]; |
||
| 516 | uint32_t RESERVED0; |
||
| 517 | __IO uint32_t MAPR2; |
||
| 518 | } AFIO_TypeDef; |
||
| 519 | /** |
||
| 520 | * @brief Inter Integrated Circuit Interface |
||
| 521 | */ |
||
| 522 | |||
| 523 | typedef struct |
||
| 524 | { |
||
| 525 | __IO uint32_t CR1; |
||
| 526 | __IO uint32_t CR2; |
||
| 527 | __IO uint32_t OAR1; |
||
| 528 | __IO uint32_t OAR2; |
||
| 529 | __IO uint32_t DR; |
||
| 530 | __IO uint32_t SR1; |
||
| 531 | __IO uint32_t SR2; |
||
| 532 | __IO uint32_t CCR; |
||
| 533 | __IO uint32_t TRISE; |
||
| 534 | } I2C_TypeDef; |
||
| 535 | |||
| 536 | /** |
||
| 537 | * @brief Independent WATCHDOG |
||
| 538 | */ |
||
| 539 | |||
| 540 | typedef struct |
||
| 541 | { |
||
| 542 | __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ |
||
| 543 | __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ |
||
| 544 | __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ |
||
| 545 | __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ |
||
| 546 | } IWDG_TypeDef; |
||
| 547 | |||
| 548 | /** |
||
| 549 | * @brief Power Control |
||
| 550 | */ |
||
| 551 | |||
| 552 | typedef struct |
||
| 553 | { |
||
| 554 | __IO uint32_t CR; |
||
| 555 | __IO uint32_t CSR; |
||
| 556 | } PWR_TypeDef; |
||
| 557 | |||
| 558 | /** |
||
| 559 | * @brief Reset and Clock Control |
||
| 560 | */ |
||
| 561 | |||
| 562 | typedef struct |
||
| 563 | { |
||
| 564 | __IO uint32_t CR; |
||
| 565 | __IO uint32_t CFGR; |
||
| 566 | __IO uint32_t CIR; |
||
| 567 | __IO uint32_t APB2RSTR; |
||
| 568 | __IO uint32_t APB1RSTR; |
||
| 569 | __IO uint32_t AHBENR; |
||
| 570 | __IO uint32_t APB2ENR; |
||
| 571 | __IO uint32_t APB1ENR; |
||
| 572 | __IO uint32_t BDCR; |
||
| 573 | __IO uint32_t CSR; |
||
| 574 | |||
| 575 | |||
| 576 | } RCC_TypeDef; |
||
| 577 | |||
| 578 | /** |
||
| 579 | * @brief Real-Time Clock |
||
| 580 | */ |
||
| 581 | |||
| 582 | typedef struct |
||
| 583 | { |
||
| 584 | __IO uint32_t CRH; |
||
| 585 | __IO uint32_t CRL; |
||
| 586 | __IO uint32_t PRLH; |
||
| 587 | __IO uint32_t PRLL; |
||
| 588 | __IO uint32_t DIVH; |
||
| 589 | __IO uint32_t DIVL; |
||
| 590 | __IO uint32_t CNTH; |
||
| 591 | __IO uint32_t CNTL; |
||
| 592 | __IO uint32_t ALRH; |
||
| 593 | __IO uint32_t ALRL; |
||
| 594 | } RTC_TypeDef; |
||
| 595 | |||
| 596 | /** |
||
| 597 | * @brief SD host Interface |
||
| 598 | */ |
||
| 599 | |||
| 600 | typedef struct |
||
| 601 | { |
||
| 602 | __IO uint32_t POWER; |
||
| 603 | __IO uint32_t CLKCR; |
||
| 604 | __IO uint32_t ARG; |
||
| 605 | __IO uint32_t CMD; |
||
| 606 | __I uint32_t RESPCMD; |
||
| 607 | __I uint32_t RESP1; |
||
| 608 | __I uint32_t RESP2; |
||
| 609 | __I uint32_t RESP3; |
||
| 610 | __I uint32_t RESP4; |
||
| 611 | __IO uint32_t DTIMER; |
||
| 612 | __IO uint32_t DLEN; |
||
| 613 | __IO uint32_t DCTRL; |
||
| 614 | __I uint32_t DCOUNT; |
||
| 615 | __I uint32_t STA; |
||
| 616 | __IO uint32_t ICR; |
||
| 617 | __IO uint32_t MASK; |
||
| 618 | uint32_t RESERVED0[2]; |
||
| 619 | __I uint32_t FIFOCNT; |
||
| 620 | uint32_t RESERVED1[13]; |
||
| 621 | __IO uint32_t FIFO; |
||
| 622 | } SDIO_TypeDef; |
||
| 623 | |||
| 624 | /** |
||
| 625 | * @brief Serial Peripheral Interface |
||
| 626 | */ |
||
| 627 | |||
| 628 | typedef struct |
||
| 629 | { |
||
| 630 | __IO uint32_t CR1; |
||
| 631 | __IO uint32_t CR2; |
||
| 632 | __IO uint32_t SR; |
||
| 633 | __IO uint32_t DR; |
||
| 634 | __IO uint32_t CRCPR; |
||
| 635 | __IO uint32_t RXCRCR; |
||
| 636 | __IO uint32_t TXCRCR; |
||
| 637 | __IO uint32_t I2SCFGR; |
||
| 638 | __IO uint32_t I2SPR; |
||
| 639 | } SPI_TypeDef; |
||
| 640 | |||
| 641 | /** |
||
| 642 | * @brief TIM Timers |
||
| 643 | */ |
||
| 644 | typedef struct |
||
| 645 | { |
||
| 646 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
||
| 647 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
||
| 648 | __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
||
| 649 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
||
| 650 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
||
| 651 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
||
| 652 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
||
| 653 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
||
| 654 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
||
| 655 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
||
| 656 | __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
||
| 657 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
||
| 658 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
||
| 659 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
||
| 660 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
||
| 661 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
||
| 662 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
||
| 663 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
||
| 664 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
||
| 665 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ |
||
| 666 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
||
| 667 | }TIM_TypeDef; |
||
| 668 | |||
| 669 | |||
| 670 | /** |
||
| 671 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
||
| 672 | */ |
||
| 673 | |||
| 674 | typedef struct |
||
| 675 | { |
||
| 676 | __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
||
| 677 | __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
||
| 678 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
||
| 679 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
||
| 680 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
||
| 681 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
||
| 682 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
||
| 683 | } USART_TypeDef; |
||
| 684 | |||
| 685 | /** |
||
| 686 | * @brief Universal Serial Bus Full Speed Device |
||
| 687 | */ |
||
| 688 | |||
| 689 | typedef struct |
||
| 690 | { |
||
| 691 | __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ |
||
| 692 | __IO uint16_t RESERVED0; /*!< Reserved */ |
||
| 693 | __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ |
||
| 694 | __IO uint16_t RESERVED1; /*!< Reserved */ |
||
| 695 | __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ |
||
| 696 | __IO uint16_t RESERVED2; /*!< Reserved */ |
||
| 697 | __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ |
||
| 698 | __IO uint16_t RESERVED3; /*!< Reserved */ |
||
| 699 | __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ |
||
| 700 | __IO uint16_t RESERVED4; /*!< Reserved */ |
||
| 701 | __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ |
||
| 702 | __IO uint16_t RESERVED5; /*!< Reserved */ |
||
| 703 | __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ |
||
| 704 | __IO uint16_t RESERVED6; /*!< Reserved */ |
||
| 705 | __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ |
||
| 706 | __IO uint16_t RESERVED7[17]; /*!< Reserved */ |
||
| 707 | __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ |
||
| 708 | __IO uint16_t RESERVED8; /*!< Reserved */ |
||
| 709 | __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ |
||
| 710 | __IO uint16_t RESERVED9; /*!< Reserved */ |
||
| 711 | __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ |
||
| 712 | __IO uint16_t RESERVEDA; /*!< Reserved */ |
||
| 713 | __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ |
||
| 714 | __IO uint16_t RESERVEDB; /*!< Reserved */ |
||
| 715 | __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ |
||
| 716 | __IO uint16_t RESERVEDC; /*!< Reserved */ |
||
| 717 | } USB_TypeDef; |
||
| 718 | |||
| 719 | |||
| 720 | /** |
||
| 721 | * @brief Window WATCHDOG |
||
| 722 | */ |
||
| 723 | |||
| 724 | typedef struct |
||
| 725 | { |
||
| 726 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
||
| 727 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
||
| 728 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
||
| 729 | } WWDG_TypeDef; |
||
| 730 | |||
| 731 | /** |
||
| 732 | * @} |
||
| 733 | */ |
||
| 734 | |||
| 735 | /** @addtogroup Peripheral_memory_map |
||
| 736 | * @{ |
||
| 737 | */ |
||
| 738 | |||
| 739 | |||
| 740 | #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ |
||
| 741 | #define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */ |
||
| 742 | #define FLASH_BANK2_END ((uint32_t)0x080FFFFF) /*!< FLASH END address of bank2 */ |
||
| 743 | #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ |
||
| 744 | #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
||
| 745 | |||
| 746 | #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ |
||
| 747 | #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
||
| 748 | |||
| 749 | #define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */ |
||
| 750 | #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ |
||
| 751 | |||
| 752 | /*!< Peripheral memory map */ |
||
| 753 | #define APB1PERIPH_BASE PERIPH_BASE |
||
| 754 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
||
| 755 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
||
| 756 | |||
| 757 | #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
||
| 758 | #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
||
| 759 | #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
||
| 760 | #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
||
| 761 | #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
||
| 762 | #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
||
| 763 | #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
||
| 764 | #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
||
| 765 | #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
||
| 766 | #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
||
| 767 | #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
||
| 768 | #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
||
| 769 | #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
||
| 770 | #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
||
| 771 | #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
||
| 772 | #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
||
| 773 | #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
||
| 774 | #define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
||
| 775 | #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
||
| 776 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
||
| 777 | #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
||
| 778 | #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
||
| 779 | #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
||
| 780 | #define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
||
| 781 | #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
||
| 782 | #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
||
| 783 | #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
||
| 784 | #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
||
| 785 | #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
||
| 786 | #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
||
| 787 | #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
||
| 788 | #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
||
| 789 | #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
||
| 790 | #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
||
| 791 | #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
||
| 792 | #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
||
| 793 | #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
||
| 794 | #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
||
| 795 | #define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
||
| 796 | #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
||
| 797 | #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
||
| 798 | #define TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
||
| 799 | #define TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
||
| 800 | |||
| 801 | #define SDIO_BASE (PERIPH_BASE + 0x18000) |
||
| 802 | |||
| 803 | #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
||
| 804 | #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
||
| 805 | #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
||
| 806 | #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
||
| 807 | #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
||
| 808 | #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
||
| 809 | #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
||
| 810 | #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
||
| 811 | #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
||
| 812 | #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
||
| 813 | #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
||
| 814 | #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
||
| 815 | #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
||
| 816 | #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
||
| 817 | #define RCC_BASE (AHBPERIPH_BASE + 0x1000) |
||
| 818 | #define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
||
| 819 | |||
| 820 | #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ |
||
| 821 | #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ |
||
| 822 | |||
| 823 | |||
| 824 | #define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */ |
||
| 825 | #define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */ |
||
| 826 | #define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */ |
||
| 827 | #define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */ |
||
| 828 | #define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */ |
||
| 829 | |||
| 830 | #define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */ |
||
| 831 | #define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */ |
||
| 832 | #define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */ |
||
| 833 | |||
| 834 | #define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ |
||
| 835 | #define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ |
||
| 836 | #define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2/Bank3 registers base address */ |
||
| 837 | #define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ |
||
| 838 | |||
| 839 | #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ |
||
| 840 | |||
| 841 | /* USB device FS */ |
||
| 842 | #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ |
||
| 843 | #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ |
||
| 844 | |||
| 845 | |||
| 846 | /** |
||
| 847 | * @} |
||
| 848 | */ |
||
| 849 | |||
| 850 | /** @addtogroup Peripheral_declaration |
||
| 851 | * @{ |
||
| 852 | */ |
||
| 853 | |||
| 854 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
||
| 855 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
||
| 856 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
||
| 857 | #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
||
| 858 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
||
| 859 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
||
| 860 | #define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
||
| 861 | #define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
||
| 862 | #define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
||
| 863 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
||
| 864 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
||
| 865 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
||
| 866 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
||
| 867 | #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
||
| 868 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
||
| 869 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
||
| 870 | #define UART4 ((USART_TypeDef *) UART4_BASE) |
||
| 871 | #define UART5 ((USART_TypeDef *) UART5_BASE) |
||
| 872 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
||
| 873 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
||
| 874 | #define USB ((USB_TypeDef *) USB_BASE) |
||
| 875 | #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
||
| 876 | #define BKP ((BKP_TypeDef *) BKP_BASE) |
||
| 877 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
||
| 878 | #define DAC ((DAC_TypeDef *) DAC_BASE) |
||
| 879 | #define AFIO ((AFIO_TypeDef *) AFIO_BASE) |
||
| 880 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
||
| 881 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
||
| 882 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
||
| 883 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
||
| 884 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
||
| 885 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
||
| 886 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
||
| 887 | #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
||
| 888 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
||
| 889 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
||
| 890 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
||
| 891 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
||
| 892 | #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
||
| 893 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
||
| 894 | #define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
||
| 895 | #define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
||
| 896 | #define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
||
| 897 | #define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
||
| 898 | #define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
||
| 899 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
||
| 900 | #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
||
| 901 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
||
| 902 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
||
| 903 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
||
| 904 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
||
| 905 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
||
| 906 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
||
| 907 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
||
| 908 | #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
||
| 909 | #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
||
| 910 | #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
||
| 911 | #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
||
| 912 | #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
||
| 913 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
||
| 914 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
||
| 915 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
||
| 916 | #define OB ((OB_TypeDef *) OB_BASE) |
||
| 917 | #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE) |
||
| 918 | #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE) |
||
| 919 | #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE) |
||
| 920 | #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE) |
||
| 921 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
||
| 922 | |||
| 923 | |||
| 924 | /** |
||
| 925 | * @} |
||
| 926 | */ |
||
| 927 | |||
| 928 | /** @addtogroup Exported_constants |
||
| 929 | * @{ |
||
| 930 | */ |
||
| 931 | |||
| 932 | /** @addtogroup Peripheral_Registers_Bits_Definition |
||
| 933 | * @{ |
||
| 934 | */ |
||
| 935 | |||
| 936 | /******************************************************************************/ |
||
| 937 | /* Peripheral Registers_Bits_Definition */ |
||
| 938 | /******************************************************************************/ |
||
| 939 | |||
| 940 | /******************************************************************************/ |
||
| 941 | /* */ |
||
| 942 | /* CRC calculation unit (CRC) */ |
||
| 943 | /* */ |
||
| 944 | /******************************************************************************/ |
||
| 945 | |||
| 946 | /******************* Bit definition for CRC_DR register *********************/ |
||
| 947 | #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
||
| 948 | |||
| 949 | /******************* Bit definition for CRC_IDR register ********************/ |
||
| 950 | #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
||
| 951 | |||
| 952 | /******************** Bit definition for CRC_CR register ********************/ |
||
| 953 | #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ |
||
| 954 | |||
| 955 | /******************************************************************************/ |
||
| 956 | /* */ |
||
| 957 | /* Power Control */ |
||
| 958 | /* */ |
||
| 959 | /******************************************************************************/ |
||
| 960 | |||
| 961 | /******************** Bit definition for PWR_CR register ********************/ |
||
| 962 | #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */ |
||
| 963 | #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */ |
||
| 964 | #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */ |
||
| 965 | #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */ |
||
| 966 | #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */ |
||
| 967 | |||
| 968 | #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */ |
||
| 969 | #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 970 | #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 971 | #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 972 | |||
| 973 | /*!< PVD level configuration */ |
||
| 974 | #define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */ |
||
| 975 | #define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */ |
||
| 976 | #define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */ |
||
| 977 | #define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */ |
||
| 978 | #define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */ |
||
| 979 | #define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */ |
||
| 980 | #define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */ |
||
| 981 | #define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */ |
||
| 982 | |||
| 983 | #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ |
||
| 984 | |||
| 985 | |||
| 986 | /******************* Bit definition for PWR_CSR register ********************/ |
||
| 987 | #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */ |
||
| 988 | #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */ |
||
| 989 | #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */ |
||
| 990 | #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */ |
||
| 991 | |||
| 992 | /******************************************************************************/ |
||
| 993 | /* */ |
||
| 994 | /* Backup registers */ |
||
| 995 | /* */ |
||
| 996 | /******************************************************************************/ |
||
| 997 | |||
| 998 | /******************* Bit definition for BKP_DR1 register ********************/ |
||
| 999 | #define BKP_DR1_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1000 | |||
| 1001 | /******************* Bit definition for BKP_DR2 register ********************/ |
||
| 1002 | #define BKP_DR2_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1003 | |||
| 1004 | /******************* Bit definition for BKP_DR3 register ********************/ |
||
| 1005 | #define BKP_DR3_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1006 | |||
| 1007 | /******************* Bit definition for BKP_DR4 register ********************/ |
||
| 1008 | #define BKP_DR4_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1009 | |||
| 1010 | /******************* Bit definition for BKP_DR5 register ********************/ |
||
| 1011 | #define BKP_DR5_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1012 | |||
| 1013 | /******************* Bit definition for BKP_DR6 register ********************/ |
||
| 1014 | #define BKP_DR6_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1015 | |||
| 1016 | /******************* Bit definition for BKP_DR7 register ********************/ |
||
| 1017 | #define BKP_DR7_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1018 | |||
| 1019 | /******************* Bit definition for BKP_DR8 register ********************/ |
||
| 1020 | #define BKP_DR8_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1021 | |||
| 1022 | /******************* Bit definition for BKP_DR9 register ********************/ |
||
| 1023 | #define BKP_DR9_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1024 | |||
| 1025 | /******************* Bit definition for BKP_DR10 register *******************/ |
||
| 1026 | #define BKP_DR10_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1027 | |||
| 1028 | /******************* Bit definition for BKP_DR11 register *******************/ |
||
| 1029 | #define BKP_DR11_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1030 | |||
| 1031 | /******************* Bit definition for BKP_DR12 register *******************/ |
||
| 1032 | #define BKP_DR12_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1033 | |||
| 1034 | /******************* Bit definition for BKP_DR13 register *******************/ |
||
| 1035 | #define BKP_DR13_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1036 | |||
| 1037 | /******************* Bit definition for BKP_DR14 register *******************/ |
||
| 1038 | #define BKP_DR14_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1039 | |||
| 1040 | /******************* Bit definition for BKP_DR15 register *******************/ |
||
| 1041 | #define BKP_DR15_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1042 | |||
| 1043 | /******************* Bit definition for BKP_DR16 register *******************/ |
||
| 1044 | #define BKP_DR16_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1045 | |||
| 1046 | /******************* Bit definition for BKP_DR17 register *******************/ |
||
| 1047 | #define BKP_DR17_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1048 | |||
| 1049 | /****************** Bit definition for BKP_DR18 register ********************/ |
||
| 1050 | #define BKP_DR18_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1051 | |||
| 1052 | /******************* Bit definition for BKP_DR19 register *******************/ |
||
| 1053 | #define BKP_DR19_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1054 | |||
| 1055 | /******************* Bit definition for BKP_DR20 register *******************/ |
||
| 1056 | #define BKP_DR20_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1057 | |||
| 1058 | /******************* Bit definition for BKP_DR21 register *******************/ |
||
| 1059 | #define BKP_DR21_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1060 | |||
| 1061 | /******************* Bit definition for BKP_DR22 register *******************/ |
||
| 1062 | #define BKP_DR22_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1063 | |||
| 1064 | /******************* Bit definition for BKP_DR23 register *******************/ |
||
| 1065 | #define BKP_DR23_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1066 | |||
| 1067 | /******************* Bit definition for BKP_DR24 register *******************/ |
||
| 1068 | #define BKP_DR24_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1069 | |||
| 1070 | /******************* Bit definition for BKP_DR25 register *******************/ |
||
| 1071 | #define BKP_DR25_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1072 | |||
| 1073 | /******************* Bit definition for BKP_DR26 register *******************/ |
||
| 1074 | #define BKP_DR26_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1075 | |||
| 1076 | /******************* Bit definition for BKP_DR27 register *******************/ |
||
| 1077 | #define BKP_DR27_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1078 | |||
| 1079 | /******************* Bit definition for BKP_DR28 register *******************/ |
||
| 1080 | #define BKP_DR28_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1081 | |||
| 1082 | /******************* Bit definition for BKP_DR29 register *******************/ |
||
| 1083 | #define BKP_DR29_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1084 | |||
| 1085 | /******************* Bit definition for BKP_DR30 register *******************/ |
||
| 1086 | #define BKP_DR30_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1087 | |||
| 1088 | /******************* Bit definition for BKP_DR31 register *******************/ |
||
| 1089 | #define BKP_DR31_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1090 | |||
| 1091 | /******************* Bit definition for BKP_DR32 register *******************/ |
||
| 1092 | #define BKP_DR32_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1093 | |||
| 1094 | /******************* Bit definition for BKP_DR33 register *******************/ |
||
| 1095 | #define BKP_DR33_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1096 | |||
| 1097 | /******************* Bit definition for BKP_DR34 register *******************/ |
||
| 1098 | #define BKP_DR34_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1099 | |||
| 1100 | /******************* Bit definition for BKP_DR35 register *******************/ |
||
| 1101 | #define BKP_DR35_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1102 | |||
| 1103 | /******************* Bit definition for BKP_DR36 register *******************/ |
||
| 1104 | #define BKP_DR36_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1105 | |||
| 1106 | /******************* Bit definition for BKP_DR37 register *******************/ |
||
| 1107 | #define BKP_DR37_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1108 | |||
| 1109 | /******************* Bit definition for BKP_DR38 register *******************/ |
||
| 1110 | #define BKP_DR38_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1111 | |||
| 1112 | /******************* Bit definition for BKP_DR39 register *******************/ |
||
| 1113 | #define BKP_DR39_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1114 | |||
| 1115 | /******************* Bit definition for BKP_DR40 register *******************/ |
||
| 1116 | #define BKP_DR40_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1117 | |||
| 1118 | /******************* Bit definition for BKP_DR41 register *******************/ |
||
| 1119 | #define BKP_DR41_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1120 | |||
| 1121 | /******************* Bit definition for BKP_DR42 register *******************/ |
||
| 1122 | #define BKP_DR42_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 1123 | |||
| 1124 | #define RTC_BKP_NUMBER 42 |
||
| 1125 | |||
| 1126 | /****************** Bit definition for BKP_RTCCR register *******************/ |
||
| 1127 | #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /*!< Calibration value */ |
||
| 1128 | #define BKP_RTCCR_CCO ((uint32_t)0x00000080) /*!< Calibration Clock Output */ |
||
| 1129 | #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /*!< Alarm or Second Output Enable */ |
||
| 1130 | #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /*!< Alarm or Second Output Selection */ |
||
| 1131 | |||
| 1132 | /******************** Bit definition for BKP_CR register ********************/ |
||
| 1133 | #define BKP_CR_TPE ((uint32_t)0x00000001) /*!< TAMPER pin enable */ |
||
| 1134 | #define BKP_CR_TPAL ((uint32_t)0x00000002) /*!< TAMPER pin active level */ |
||
| 1135 | |||
| 1136 | /******************* Bit definition for BKP_CSR register ********************/ |
||
| 1137 | #define BKP_CSR_CTE ((uint32_t)0x00000001) /*!< Clear Tamper event */ |
||
| 1138 | #define BKP_CSR_CTI ((uint32_t)0x00000002) /*!< Clear Tamper Interrupt */ |
||
| 1139 | #define BKP_CSR_TPIE ((uint32_t)0x00000004) /*!< TAMPER Pin interrupt enable */ |
||
| 1140 | #define BKP_CSR_TEF ((uint32_t)0x00000100) /*!< Tamper Event Flag */ |
||
| 1141 | #define BKP_CSR_TIF ((uint32_t)0x00000200) /*!< Tamper Interrupt Flag */ |
||
| 1142 | |||
| 1143 | /******************************************************************************/ |
||
| 1144 | /* */ |
||
| 1145 | /* Reset and Clock Control */ |
||
| 1146 | /* */ |
||
| 1147 | /******************************************************************************/ |
||
| 1148 | |||
| 1149 | /******************** Bit definition for RCC_CR register ********************/ |
||
| 1150 | #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ |
||
| 1151 | #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ |
||
| 1152 | #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ |
||
| 1153 | #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ |
||
| 1154 | #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ |
||
| 1155 | #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ |
||
| 1156 | #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ |
||
| 1157 | #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ |
||
| 1158 | #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ |
||
| 1159 | #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ |
||
| 1160 | |||
| 1161 | |||
| 1162 | /******************* Bit definition for RCC_CFGR register *******************/ |
||
| 1163 | /*!< SW configuration */ |
||
| 1164 | #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
||
| 1165 | #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 1166 | #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 1167 | |||
| 1168 | #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
||
| 1169 | #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
||
| 1170 | #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ |
||
| 1171 | |||
| 1172 | /*!< SWS configuration */ |
||
| 1173 | #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
||
| 1174 | #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
||
| 1175 | #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
||
| 1176 | |||
| 1177 | #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
||
| 1178 | #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
||
| 1179 | #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ |
||
| 1180 | |||
| 1181 | /*!< HPRE configuration */ |
||
| 1182 | #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
||
| 1183 | #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 1184 | #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 1185 | #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
||
| 1186 | #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
||
| 1187 | |||
| 1188 | #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
||
| 1189 | #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
||
| 1190 | #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
||
| 1191 | #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
||
| 1192 | #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
||
| 1193 | #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
||
| 1194 | #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
||
| 1195 | #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
||
| 1196 | #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
||
| 1197 | |||
| 1198 | /*!< PPRE1 configuration */ |
||
| 1199 | #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ |
||
| 1200 | #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 1201 | #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 1202 | #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 1203 | |||
| 1204 | #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
||
| 1205 | #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ |
||
| 1206 | #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ |
||
| 1207 | #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ |
||
| 1208 | #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ |
||
| 1209 | |||
| 1210 | /*!< PPRE2 configuration */ |
||
| 1211 | #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
||
| 1212 | #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ |
||
| 1213 | #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ |
||
| 1214 | #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ |
||
| 1215 | |||
| 1216 | #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
||
| 1217 | #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ |
||
| 1218 | #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ |
||
| 1219 | #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ |
||
| 1220 | #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ |
||
| 1221 | |||
| 1222 | /*!< ADCPPRE configuration */ |
||
| 1223 | #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
||
| 1224 | #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
||
| 1225 | #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
||
| 1226 | |||
| 1227 | #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ |
||
| 1228 | #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ |
||
| 1229 | #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ |
||
| 1230 | #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ |
||
| 1231 | |||
| 1232 | #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ |
||
| 1233 | |||
| 1234 | #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ |
||
| 1235 | |||
| 1236 | /*!< PLLMUL configuration */ |
||
| 1237 | #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
||
| 1238 | #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 1239 | #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 1240 | #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
||
| 1241 | #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ |
||
| 1242 | |||
| 1243 | #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ |
||
| 1244 | #define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ |
||
| 1245 | |||
| 1246 | #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
||
| 1247 | #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
||
| 1248 | #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
||
| 1249 | #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
||
| 1250 | #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
||
| 1251 | #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
||
| 1252 | #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
||
| 1253 | #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
||
| 1254 | #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
||
| 1255 | #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
||
| 1256 | #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
||
| 1257 | #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
||
| 1258 | #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
||
| 1259 | #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
||
| 1260 | #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
||
| 1261 | #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ |
||
| 1262 | |||
| 1263 | /*!< MCO configuration */ |
||
| 1264 | #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
||
| 1265 | #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 1266 | #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 1267 | #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 1268 | |||
| 1269 | #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
||
| 1270 | #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
||
| 1271 | #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
||
| 1272 | #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
||
| 1273 | #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
||
| 1274 | |||
| 1275 | /*!<****************** Bit definition for RCC_CIR register ********************/ |
||
| 1276 | #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ |
||
| 1277 | #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ |
||
| 1278 | #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ |
||
| 1279 | #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ |
||
| 1280 | #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ |
||
| 1281 | #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ |
||
| 1282 | #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ |
||
| 1283 | #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ |
||
| 1284 | #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ |
||
| 1285 | #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ |
||
| 1286 | #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ |
||
| 1287 | #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ |
||
| 1288 | #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ |
||
| 1289 | #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ |
||
| 1290 | #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ |
||
| 1291 | #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ |
||
| 1292 | #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ |
||
| 1293 | |||
| 1294 | |||
| 1295 | /***************** Bit definition for RCC_APB2RSTR register *****************/ |
||
| 1296 | #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ |
||
| 1297 | #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ |
||
| 1298 | #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ |
||
| 1299 | #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ |
||
| 1300 | #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ |
||
| 1301 | #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ |
||
| 1302 | |||
| 1303 | #define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ |
||
| 1304 | |||
| 1305 | #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ |
||
| 1306 | #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ |
||
| 1307 | #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ |
||
| 1308 | |||
| 1309 | |||
| 1310 | #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ |
||
| 1311 | |||
| 1312 | #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ |
||
| 1313 | #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ |
||
| 1314 | #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ |
||
| 1315 | #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ |
||
| 1316 | |||
| 1317 | |||
| 1318 | #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ |
||
| 1319 | #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ |
||
| 1320 | #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ |
||
| 1321 | |||
| 1322 | /***************** Bit definition for RCC_APB1RSTR register *****************/ |
||
| 1323 | #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ |
||
| 1324 | #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ |
||
| 1325 | #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ |
||
| 1326 | #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ |
||
| 1327 | #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ |
||
| 1328 | |||
| 1329 | #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ |
||
| 1330 | |||
| 1331 | #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ |
||
| 1332 | #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ |
||
| 1333 | |||
| 1334 | #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ |
||
| 1335 | #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ |
||
| 1336 | #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ |
||
| 1337 | #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ |
||
| 1338 | |||
| 1339 | #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ |
||
| 1340 | |||
| 1341 | #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ |
||
| 1342 | #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
||
| 1343 | #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
||
| 1344 | #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ |
||
| 1345 | #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ |
||
| 1346 | #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ |
||
| 1347 | |||
| 1348 | |||
| 1349 | |||
| 1350 | |||
| 1351 | #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ |
||
| 1352 | #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ |
||
| 1353 | #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ |
||
| 1354 | #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ |
||
| 1355 | |||
| 1356 | /****************** Bit definition for RCC_AHBENR register ******************/ |
||
| 1357 | #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ |
||
| 1358 | #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ |
||
| 1359 | #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ |
||
| 1360 | #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ |
||
| 1361 | |||
| 1362 | #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */ |
||
| 1363 | |||
| 1364 | #define RCC_AHBENR_FSMCEN ((uint32_t)0x00000100) /*!< FSMC clock enable */ |
||
| 1365 | #define RCC_AHBENR_SDIOEN ((uint32_t)0x00000400) /*!< SDIO clock enable */ |
||
| 1366 | |||
| 1367 | |||
| 1368 | /****************** Bit definition for RCC_APB2ENR register *****************/ |
||
| 1369 | #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ |
||
| 1370 | #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ |
||
| 1371 | #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ |
||
| 1372 | #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ |
||
| 1373 | #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ |
||
| 1374 | #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ |
||
| 1375 | |||
| 1376 | #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ |
||
| 1377 | |||
| 1378 | #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ |
||
| 1379 | #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ |
||
| 1380 | #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ |
||
| 1381 | |||
| 1382 | |||
| 1383 | #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ |
||
| 1384 | |||
| 1385 | #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ |
||
| 1386 | #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ |
||
| 1387 | #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ |
||
| 1388 | #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ |
||
| 1389 | |||
| 1390 | |||
| 1391 | #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ |
||
| 1392 | #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ |
||
| 1393 | #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ |
||
| 1394 | |||
| 1395 | /***************** Bit definition for RCC_APB1ENR register ******************/ |
||
| 1396 | #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ |
||
| 1397 | #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ |
||
| 1398 | #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ |
||
| 1399 | #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ |
||
| 1400 | #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ |
||
| 1401 | |||
| 1402 | #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ |
||
| 1403 | |||
| 1404 | #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ |
||
| 1405 | #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ |
||
| 1406 | |||
| 1407 | #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ |
||
| 1408 | #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ |
||
| 1409 | #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ |
||
| 1410 | #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ |
||
| 1411 | |||
| 1412 | #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ |
||
| 1413 | |||
| 1414 | #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ |
||
| 1415 | #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
||
| 1416 | #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
||
| 1417 | #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ |
||
| 1418 | #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ |
||
| 1419 | #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ |
||
| 1420 | |||
| 1421 | |||
| 1422 | |||
| 1423 | |||
| 1424 | #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ |
||
| 1425 | #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ |
||
| 1426 | #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ |
||
| 1427 | #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ |
||
| 1428 | |||
| 1429 | /******************* Bit definition for RCC_BDCR register *******************/ |
||
| 1430 | #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ |
||
| 1431 | #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ |
||
| 1432 | #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ |
||
| 1433 | |||
| 1434 | #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
||
| 1435 | #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 1436 | #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 1437 | |||
| 1438 | /*!< RTC congiguration */ |
||
| 1439 | #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
||
| 1440 | #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ |
||
| 1441 | #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ |
||
| 1442 | #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
||
| 1443 | |||
| 1444 | #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ |
||
| 1445 | #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ |
||
| 1446 | |||
| 1447 | /******************* Bit definition for RCC_CSR register ********************/ |
||
| 1448 | #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ |
||
| 1449 | #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ |
||
| 1450 | #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ |
||
| 1451 | #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ |
||
| 1452 | #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ |
||
| 1453 | #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ |
||
| 1454 | #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ |
||
| 1455 | #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ |
||
| 1456 | #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ |
||
| 1457 | |||
| 1458 | |||
| 1459 | |||
| 1460 | /******************************************************************************/ |
||
| 1461 | /* */ |
||
| 1462 | /* General Purpose and Alternate Function I/O */ |
||
| 1463 | /* */ |
||
| 1464 | /******************************************************************************/ |
||
| 1465 | |||
| 1466 | /******************* Bit definition for GPIO_CRL register *******************/ |
||
| 1467 | #define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
||
| 1468 | |||
| 1469 | #define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
||
| 1470 | #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 1471 | #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 1472 | |||
| 1473 | #define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
||
| 1474 | #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 1475 | #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 1476 | |||
| 1477 | #define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
||
| 1478 | #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 1479 | #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 1480 | |||
| 1481 | #define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
||
| 1482 | #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 1483 | #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 1484 | |||
| 1485 | #define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
||
| 1486 | #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 1487 | #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 1488 | |||
| 1489 | #define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
||
| 1490 | #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 1491 | #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 1492 | |||
| 1493 | #define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
||
| 1494 | #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 1495 | #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 1496 | |||
| 1497 | #define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
||
| 1498 | #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
||
| 1499 | #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
||
| 1500 | |||
| 1501 | #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
||
| 1502 | |||
| 1503 | #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
||
| 1504 | #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
||
| 1505 | #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
||
| 1506 | |||
| 1507 | #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
||
| 1508 | #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 1509 | #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 1510 | |||
| 1511 | #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
||
| 1512 | #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 1513 | #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 1514 | |||
| 1515 | #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
||
| 1516 | #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
||
| 1517 | #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
||
| 1518 | |||
| 1519 | #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
||
| 1520 | #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 1521 | #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 1522 | |||
| 1523 | #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
||
| 1524 | #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
||
| 1525 | #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
||
| 1526 | |||
| 1527 | #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
||
| 1528 | #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 1529 | #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 1530 | |||
| 1531 | #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
||
| 1532 | #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
||
| 1533 | #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
||
| 1534 | |||
| 1535 | /******************* Bit definition for GPIO_CRH register *******************/ |
||
| 1536 | #define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
||
| 1537 | |||
| 1538 | #define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
||
| 1539 | #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 1540 | #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 1541 | |||
| 1542 | #define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
||
| 1543 | #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 1544 | #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 1545 | |||
| 1546 | #define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
||
| 1547 | #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 1548 | #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 1549 | |||
| 1550 | #define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
||
| 1551 | #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 1552 | #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 1553 | |||
| 1554 | #define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
||
| 1555 | #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 1556 | #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 1557 | |||
| 1558 | #define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
||
| 1559 | #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 1560 | #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 1561 | |||
| 1562 | #define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
||
| 1563 | #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 1564 | #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 1565 | |||
| 1566 | #define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
||
| 1567 | #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
||
| 1568 | #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
||
| 1569 | |||
| 1570 | #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
||
| 1571 | |||
| 1572 | #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
||
| 1573 | #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
||
| 1574 | #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
||
| 1575 | |||
| 1576 | #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
||
| 1577 | #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 1578 | #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 1579 | |||
| 1580 | #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
||
| 1581 | #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 1582 | #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 1583 | |||
| 1584 | #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
||
| 1585 | #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
||
| 1586 | #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
||
| 1587 | |||
| 1588 | #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
||
| 1589 | #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 1590 | #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 1591 | |||
| 1592 | #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
||
| 1593 | #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
||
| 1594 | #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
||
| 1595 | |||
| 1596 | #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
||
| 1597 | #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 1598 | #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 1599 | |||
| 1600 | #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
||
| 1601 | #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
||
| 1602 | #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
||
| 1603 | |||
| 1604 | /*!<****************** Bit definition for GPIO_IDR register *******************/ |
||
| 1605 | #define GPIO_IDR_IDR0 ((uint32_t)0x0001) /*!< Port input data, bit 0 */ |
||
| 1606 | #define GPIO_IDR_IDR1 ((uint32_t)0x0002) /*!< Port input data, bit 1 */ |
||
| 1607 | #define GPIO_IDR_IDR2 ((uint32_t)0x0004) /*!< Port input data, bit 2 */ |
||
| 1608 | #define GPIO_IDR_IDR3 ((uint32_t)0x0008) /*!< Port input data, bit 3 */ |
||
| 1609 | #define GPIO_IDR_IDR4 ((uint32_t)0x0010) /*!< Port input data, bit 4 */ |
||
| 1610 | #define GPIO_IDR_IDR5 ((uint32_t)0x0020) /*!< Port input data, bit 5 */ |
||
| 1611 | #define GPIO_IDR_IDR6 ((uint32_t)0x0040) /*!< Port input data, bit 6 */ |
||
| 1612 | #define GPIO_IDR_IDR7 ((uint32_t)0x0080) /*!< Port input data, bit 7 */ |
||
| 1613 | #define GPIO_IDR_IDR8 ((uint32_t)0x0100) /*!< Port input data, bit 8 */ |
||
| 1614 | #define GPIO_IDR_IDR9 ((uint32_t)0x0200) /*!< Port input data, bit 9 */ |
||
| 1615 | #define GPIO_IDR_IDR10 ((uint32_t)0x0400) /*!< Port input data, bit 10 */ |
||
| 1616 | #define GPIO_IDR_IDR11 ((uint32_t)0x0800) /*!< Port input data, bit 11 */ |
||
| 1617 | #define GPIO_IDR_IDR12 ((uint32_t)0x1000) /*!< Port input data, bit 12 */ |
||
| 1618 | #define GPIO_IDR_IDR13 ((uint32_t)0x2000) /*!< Port input data, bit 13 */ |
||
| 1619 | #define GPIO_IDR_IDR14 ((uint32_t)0x4000) /*!< Port input data, bit 14 */ |
||
| 1620 | #define GPIO_IDR_IDR15 ((uint32_t)0x8000) /*!< Port input data, bit 15 */ |
||
| 1621 | |||
| 1622 | /******************* Bit definition for GPIO_ODR register *******************/ |
||
| 1623 | #define GPIO_ODR_ODR0 ((uint32_t)0x0001) /*!< Port output data, bit 0 */ |
||
| 1624 | #define GPIO_ODR_ODR1 ((uint32_t)0x0002) /*!< Port output data, bit 1 */ |
||
| 1625 | #define GPIO_ODR_ODR2 ((uint32_t)0x0004) /*!< Port output data, bit 2 */ |
||
| 1626 | #define GPIO_ODR_ODR3 ((uint32_t)0x0008) /*!< Port output data, bit 3 */ |
||
| 1627 | #define GPIO_ODR_ODR4 ((uint32_t)0x0010) /*!< Port output data, bit 4 */ |
||
| 1628 | #define GPIO_ODR_ODR5 ((uint32_t)0x0020) /*!< Port output data, bit 5 */ |
||
| 1629 | #define GPIO_ODR_ODR6 ((uint32_t)0x0040) /*!< Port output data, bit 6 */ |
||
| 1630 | #define GPIO_ODR_ODR7 ((uint32_t)0x0080) /*!< Port output data, bit 7 */ |
||
| 1631 | #define GPIO_ODR_ODR8 ((uint32_t)0x0100) /*!< Port output data, bit 8 */ |
||
| 1632 | #define GPIO_ODR_ODR9 ((uint32_t)0x0200) /*!< Port output data, bit 9 */ |
||
| 1633 | #define GPIO_ODR_ODR10 ((uint32_t)0x0400) /*!< Port output data, bit 10 */ |
||
| 1634 | #define GPIO_ODR_ODR11 ((uint32_t)0x0800) /*!< Port output data, bit 11 */ |
||
| 1635 | #define GPIO_ODR_ODR12 ((uint32_t)0x1000) /*!< Port output data, bit 12 */ |
||
| 1636 | #define GPIO_ODR_ODR13 ((uint32_t)0x2000) /*!< Port output data, bit 13 */ |
||
| 1637 | #define GPIO_ODR_ODR14 ((uint32_t)0x4000) /*!< Port output data, bit 14 */ |
||
| 1638 | #define GPIO_ODR_ODR15 ((uint32_t)0x8000) /*!< Port output data, bit 15 */ |
||
| 1639 | |||
| 1640 | /****************** Bit definition for GPIO_BSRR register *******************/ |
||
| 1641 | #define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ |
||
| 1642 | #define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ |
||
| 1643 | #define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ |
||
| 1644 | #define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ |
||
| 1645 | #define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ |
||
| 1646 | #define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ |
||
| 1647 | #define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ |
||
| 1648 | #define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ |
||
| 1649 | #define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ |
||
| 1650 | #define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ |
||
| 1651 | #define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ |
||
| 1652 | #define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ |
||
| 1653 | #define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ |
||
| 1654 | #define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ |
||
| 1655 | #define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ |
||
| 1656 | #define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ |
||
| 1657 | |||
| 1658 | #define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ |
||
| 1659 | #define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ |
||
| 1660 | #define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ |
||
| 1661 | #define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ |
||
| 1662 | #define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ |
||
| 1663 | #define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ |
||
| 1664 | #define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ |
||
| 1665 | #define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ |
||
| 1666 | #define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ |
||
| 1667 | #define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ |
||
| 1668 | #define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ |
||
| 1669 | #define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ |
||
| 1670 | #define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ |
||
| 1671 | #define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ |
||
| 1672 | #define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ |
||
| 1673 | #define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ |
||
| 1674 | |||
| 1675 | /******************* Bit definition for GPIO_BRR register *******************/ |
||
| 1676 | #define GPIO_BRR_BR0 ((uint32_t)0x0001) /*!< Port x Reset bit 0 */ |
||
| 1677 | #define GPIO_BRR_BR1 ((uint32_t)0x0002) /*!< Port x Reset bit 1 */ |
||
| 1678 | #define GPIO_BRR_BR2 ((uint32_t)0x0004) /*!< Port x Reset bit 2 */ |
||
| 1679 | #define GPIO_BRR_BR3 ((uint32_t)0x0008) /*!< Port x Reset bit 3 */ |
||
| 1680 | #define GPIO_BRR_BR4 ((uint32_t)0x0010) /*!< Port x Reset bit 4 */ |
||
| 1681 | #define GPIO_BRR_BR5 ((uint32_t)0x0020) /*!< Port x Reset bit 5 */ |
||
| 1682 | #define GPIO_BRR_BR6 ((uint32_t)0x0040) /*!< Port x Reset bit 6 */ |
||
| 1683 | #define GPIO_BRR_BR7 ((uint32_t)0x0080) /*!< Port x Reset bit 7 */ |
||
| 1684 | #define GPIO_BRR_BR8 ((uint32_t)0x0100) /*!< Port x Reset bit 8 */ |
||
| 1685 | #define GPIO_BRR_BR9 ((uint32_t)0x0200) /*!< Port x Reset bit 9 */ |
||
| 1686 | #define GPIO_BRR_BR10 ((uint32_t)0x0400) /*!< Port x Reset bit 10 */ |
||
| 1687 | #define GPIO_BRR_BR11 ((uint32_t)0x0800) /*!< Port x Reset bit 11 */ |
||
| 1688 | #define GPIO_BRR_BR12 ((uint32_t)0x1000) /*!< Port x Reset bit 12 */ |
||
| 1689 | #define GPIO_BRR_BR13 ((uint32_t)0x2000) /*!< Port x Reset bit 13 */ |
||
| 1690 | #define GPIO_BRR_BR14 ((uint32_t)0x4000) /*!< Port x Reset bit 14 */ |
||
| 1691 | #define GPIO_BRR_BR15 ((uint32_t)0x8000) /*!< Port x Reset bit 15 */ |
||
| 1692 | |||
| 1693 | /****************** Bit definition for GPIO_LCKR register *******************/ |
||
| 1694 | #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ |
||
| 1695 | #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ |
||
| 1696 | #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ |
||
| 1697 | #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ |
||
| 1698 | #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ |
||
| 1699 | #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ |
||
| 1700 | #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ |
||
| 1701 | #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ |
||
| 1702 | #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ |
||
| 1703 | #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ |
||
| 1704 | #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ |
||
| 1705 | #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ |
||
| 1706 | #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ |
||
| 1707 | #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ |
||
| 1708 | #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ |
||
| 1709 | #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ |
||
| 1710 | #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ |
||
| 1711 | |||
| 1712 | /*----------------------------------------------------------------------------*/ |
||
| 1713 | |||
| 1714 | /****************** Bit definition for AFIO_EVCR register *******************/ |
||
| 1715 | #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /*!< PIN[3:0] bits (Pin selection) */ |
||
| 1716 | #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 1717 | #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 1718 | #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 1719 | #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 1720 | |||
| 1721 | /*!< PIN configuration */ |
||
| 1722 | #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */ |
||
| 1723 | #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /*!< Pin 1 selected */ |
||
| 1724 | #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /*!< Pin 2 selected */ |
||
| 1725 | #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /*!< Pin 3 selected */ |
||
| 1726 | #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /*!< Pin 4 selected */ |
||
| 1727 | #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /*!< Pin 5 selected */ |
||
| 1728 | #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /*!< Pin 6 selected */ |
||
| 1729 | #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /*!< Pin 7 selected */ |
||
| 1730 | #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /*!< Pin 8 selected */ |
||
| 1731 | #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /*!< Pin 9 selected */ |
||
| 1732 | #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /*!< Pin 10 selected */ |
||
| 1733 | #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /*!< Pin 11 selected */ |
||
| 1734 | #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /*!< Pin 12 selected */ |
||
| 1735 | #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /*!< Pin 13 selected */ |
||
| 1736 | #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /*!< Pin 14 selected */ |
||
| 1737 | #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /*!< Pin 15 selected */ |
||
| 1738 | |||
| 1739 | #define AFIO_EVCR_PORT ((uint32_t)0x00000070) /*!< PORT[2:0] bits (Port selection) */ |
||
| 1740 | #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 1741 | #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 1742 | #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
||
| 1743 | |||
| 1744 | /*!< PORT configuration */ |
||
| 1745 | #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */ |
||
| 1746 | #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /*!< Port B selected */ |
||
| 1747 | #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /*!< Port C selected */ |
||
| 1748 | #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /*!< Port D selected */ |
||
| 1749 | #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /*!< Port E selected */ |
||
| 1750 | |||
| 1751 | #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /*!< Event Output Enable */ |
||
| 1752 | |||
| 1753 | /****************** Bit definition for AFIO_MAPR register *******************/ |
||
| 1754 | #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ |
||
| 1755 | #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ |
||
| 1756 | #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ |
||
| 1757 | #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ |
||
| 1758 | |||
| 1759 | #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
||
| 1760 | #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 1761 | #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 1762 | |||
| 1763 | /* USART3_REMAP configuration */ |
||
| 1764 | #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
||
| 1765 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
||
| 1766 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
||
| 1767 | |||
| 1768 | #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
||
| 1769 | #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 1770 | #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 1771 | |||
| 1772 | /*!< TIM1_REMAP configuration */ |
||
| 1773 | #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
||
| 1774 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
||
| 1775 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
||
| 1776 | |||
| 1777 | #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
||
| 1778 | #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 1779 | #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 1780 | |||
| 1781 | /*!< TIM2_REMAP configuration */ |
||
| 1782 | #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
||
| 1783 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
||
| 1784 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
||
| 1785 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
||
| 1786 | |||
| 1787 | #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
||
| 1788 | #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 1789 | #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 1790 | |||
| 1791 | /*!< TIM3_REMAP configuration */ |
||
| 1792 | #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
||
| 1793 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
||
| 1794 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
||
| 1795 | |||
| 1796 | #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ |
||
| 1797 | |||
| 1798 | #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ |
||
| 1799 | #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
||
| 1800 | #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
||
| 1801 | |||
| 1802 | /*!< CAN_REMAP configuration */ |
||
| 1803 | #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ |
||
| 1804 | #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ |
||
| 1805 | #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ |
||
| 1806 | |||
| 1807 | #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
||
| 1808 | #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ |
||
| 1809 | #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ |
||
| 1810 | #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ |
||
| 1811 | #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ |
||
| 1812 | #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ |
||
| 1813 | |||
| 1814 | /*!< SWJ_CFG configuration */ |
||
| 1815 | #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
||
| 1816 | #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 1817 | #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 1818 | #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 1819 | |||
| 1820 | #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
||
| 1821 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
||
| 1822 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ |
||
| 1823 | #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ |
||
| 1824 | |||
| 1825 | |||
| 1826 | /***************** Bit definition for AFIO_EXTICR1 register *****************/ |
||
| 1827 | #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */ |
||
| 1828 | #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */ |
||
| 1829 | #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */ |
||
| 1830 | #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */ |
||
| 1831 | |||
| 1832 | /*!< EXTI0 configuration */ |
||
| 1833 | #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ |
||
| 1834 | #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */ |
||
| 1835 | #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */ |
||
| 1836 | #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */ |
||
| 1837 | #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */ |
||
| 1838 | #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */ |
||
| 1839 | #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */ |
||
| 1840 | |||
| 1841 | /*!< EXTI1 configuration */ |
||
| 1842 | #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ |
||
| 1843 | #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */ |
||
| 1844 | #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */ |
||
| 1845 | #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */ |
||
| 1846 | #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */ |
||
| 1847 | #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */ |
||
| 1848 | #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */ |
||
| 1849 | |||
| 1850 | /*!< EXTI2 configuration */ |
||
| 1851 | #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ |
||
| 1852 | #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */ |
||
| 1853 | #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */ |
||
| 1854 | #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */ |
||
| 1855 | #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */ |
||
| 1856 | #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */ |
||
| 1857 | #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */ |
||
| 1858 | |||
| 1859 | /*!< EXTI3 configuration */ |
||
| 1860 | #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ |
||
| 1861 | #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */ |
||
| 1862 | #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */ |
||
| 1863 | #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */ |
||
| 1864 | #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */ |
||
| 1865 | #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */ |
||
| 1866 | #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */ |
||
| 1867 | |||
| 1868 | /***************** Bit definition for AFIO_EXTICR2 register *****************/ |
||
| 1869 | #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */ |
||
| 1870 | #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */ |
||
| 1871 | #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */ |
||
| 1872 | #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */ |
||
| 1873 | |||
| 1874 | /*!< EXTI4 configuration */ |
||
| 1875 | #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ |
||
| 1876 | #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */ |
||
| 1877 | #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */ |
||
| 1878 | #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */ |
||
| 1879 | #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */ |
||
| 1880 | #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */ |
||
| 1881 | #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */ |
||
| 1882 | |||
| 1883 | /* EXTI5 configuration */ |
||
| 1884 | #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ |
||
| 1885 | #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */ |
||
| 1886 | #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */ |
||
| 1887 | #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */ |
||
| 1888 | #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */ |
||
| 1889 | #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */ |
||
| 1890 | #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */ |
||
| 1891 | |||
| 1892 | /*!< EXTI6 configuration */ |
||
| 1893 | #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ |
||
| 1894 | #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */ |
||
| 1895 | #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */ |
||
| 1896 | #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */ |
||
| 1897 | #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */ |
||
| 1898 | #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */ |
||
| 1899 | #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */ |
||
| 1900 | |||
| 1901 | /*!< EXTI7 configuration */ |
||
| 1902 | #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ |
||
| 1903 | #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */ |
||
| 1904 | #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */ |
||
| 1905 | #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */ |
||
| 1906 | #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */ |
||
| 1907 | #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */ |
||
| 1908 | #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */ |
||
| 1909 | |||
| 1910 | /***************** Bit definition for AFIO_EXTICR3 register *****************/ |
||
| 1911 | #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */ |
||
| 1912 | #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */ |
||
| 1913 | #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */ |
||
| 1914 | #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */ |
||
| 1915 | |||
| 1916 | /*!< EXTI8 configuration */ |
||
| 1917 | #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ |
||
| 1918 | #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */ |
||
| 1919 | #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */ |
||
| 1920 | #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */ |
||
| 1921 | #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */ |
||
| 1922 | #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */ |
||
| 1923 | #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */ |
||
| 1924 | |||
| 1925 | /*!< EXTI9 configuration */ |
||
| 1926 | #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ |
||
| 1927 | #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */ |
||
| 1928 | #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */ |
||
| 1929 | #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */ |
||
| 1930 | #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */ |
||
| 1931 | #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */ |
||
| 1932 | #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */ |
||
| 1933 | |||
| 1934 | /*!< EXTI10 configuration */ |
||
| 1935 | #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ |
||
| 1936 | #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */ |
||
| 1937 | #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */ |
||
| 1938 | #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */ |
||
| 1939 | #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */ |
||
| 1940 | #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */ |
||
| 1941 | #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */ |
||
| 1942 | |||
| 1943 | /*!< EXTI11 configuration */ |
||
| 1944 | #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ |
||
| 1945 | #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */ |
||
| 1946 | #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */ |
||
| 1947 | #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */ |
||
| 1948 | #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */ |
||
| 1949 | #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */ |
||
| 1950 | #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */ |
||
| 1951 | |||
| 1952 | /***************** Bit definition for AFIO_EXTICR4 register *****************/ |
||
| 1953 | #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */ |
||
| 1954 | #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */ |
||
| 1955 | #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */ |
||
| 1956 | #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */ |
||
| 1957 | |||
| 1958 | /* EXTI12 configuration */ |
||
| 1959 | #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ |
||
| 1960 | #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */ |
||
| 1961 | #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */ |
||
| 1962 | #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */ |
||
| 1963 | #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */ |
||
| 1964 | #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */ |
||
| 1965 | #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */ |
||
| 1966 | |||
| 1967 | /* EXTI13 configuration */ |
||
| 1968 | #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ |
||
| 1969 | #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */ |
||
| 1970 | #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */ |
||
| 1971 | #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */ |
||
| 1972 | #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */ |
||
| 1973 | #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */ |
||
| 1974 | #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */ |
||
| 1975 | |||
| 1976 | /*!< EXTI14 configuration */ |
||
| 1977 | #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ |
||
| 1978 | #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */ |
||
| 1979 | #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */ |
||
| 1980 | #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */ |
||
| 1981 | #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */ |
||
| 1982 | #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */ |
||
| 1983 | #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */ |
||
| 1984 | |||
| 1985 | /*!< EXTI15 configuration */ |
||
| 1986 | #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ |
||
| 1987 | #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */ |
||
| 1988 | #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */ |
||
| 1989 | #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */ |
||
| 1990 | #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */ |
||
| 1991 | #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */ |
||
| 1992 | #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */ |
||
| 1993 | |||
| 1994 | /****************** Bit definition for AFIO_MAPR2 register ******************/ |
||
| 1995 | |||
| 1996 | |||
| 1997 | #define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ |
||
| 1998 | #define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ |
||
| 1999 | #define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ |
||
| 2000 | #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ |
||
| 2001 | #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ |
||
| 2002 | #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ |
||
| 2003 | |||
| 2004 | /******************************************************************************/ |
||
| 2005 | /* */ |
||
| 2006 | /* SystemTick */ |
||
| 2007 | /* */ |
||
| 2008 | /******************************************************************************/ |
||
| 2009 | |||
| 2010 | /***************** Bit definition for SysTick_CTRL register *****************/ |
||
| 2011 | #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ |
||
| 2012 | #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ |
||
| 2013 | #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ |
||
| 2014 | #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ |
||
| 2015 | |||
| 2016 | /***************** Bit definition for SysTick_LOAD register *****************/ |
||
| 2017 | #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ |
||
| 2018 | |||
| 2019 | /***************** Bit definition for SysTick_VAL register ******************/ |
||
| 2020 | #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ |
||
| 2021 | |||
| 2022 | /***************** Bit definition for SysTick_CALIB register ****************/ |
||
| 2023 | #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ |
||
| 2024 | #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ |
||
| 2025 | #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ |
||
| 2026 | |||
| 2027 | /******************************************************************************/ |
||
| 2028 | /* */ |
||
| 2029 | /* Nested Vectored Interrupt Controller */ |
||
| 2030 | /* */ |
||
| 2031 | /******************************************************************************/ |
||
| 2032 | |||
| 2033 | /****************** Bit definition for NVIC_ISER register *******************/ |
||
| 2034 | #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ |
||
| 2035 | #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 2036 | #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 2037 | #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 2038 | #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 2039 | #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 2040 | #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 2041 | #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 2042 | #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 2043 | #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 2044 | #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 2045 | #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 2046 | #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 2047 | #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 2048 | #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 2049 | #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 2050 | #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 2051 | #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 2052 | #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 2053 | #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 2054 | #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 2055 | #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 2056 | #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 2057 | #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 2058 | #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 2059 | #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 2060 | #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 2061 | #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 2062 | #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 2063 | #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 2064 | #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 2065 | #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 2066 | #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 2067 | |||
| 2068 | /****************** Bit definition for NVIC_ICER register *******************/ |
||
| 2069 | #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ |
||
| 2070 | #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 2071 | #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 2072 | #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 2073 | #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 2074 | #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 2075 | #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 2076 | #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 2077 | #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 2078 | #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 2079 | #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 2080 | #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 2081 | #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 2082 | #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 2083 | #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 2084 | #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 2085 | #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 2086 | #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 2087 | #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 2088 | #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 2089 | #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 2090 | #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 2091 | #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 2092 | #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 2093 | #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 2094 | #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 2095 | #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 2096 | #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 2097 | #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 2098 | #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 2099 | #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 2100 | #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 2101 | #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 2102 | |||
| 2103 | /****************** Bit definition for NVIC_ISPR register *******************/ |
||
| 2104 | #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ |
||
| 2105 | #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 2106 | #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 2107 | #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 2108 | #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 2109 | #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 2110 | #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 2111 | #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 2112 | #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 2113 | #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 2114 | #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 2115 | #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 2116 | #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 2117 | #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 2118 | #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 2119 | #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 2120 | #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 2121 | #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 2122 | #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 2123 | #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 2124 | #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 2125 | #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 2126 | #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 2127 | #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 2128 | #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 2129 | #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 2130 | #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 2131 | #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 2132 | #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 2133 | #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 2134 | #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 2135 | #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 2136 | #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 2137 | |||
| 2138 | /****************** Bit definition for NVIC_ICPR register *******************/ |
||
| 2139 | #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ |
||
| 2140 | #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 2141 | #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 2142 | #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 2143 | #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 2144 | #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 2145 | #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 2146 | #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 2147 | #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 2148 | #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 2149 | #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 2150 | #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 2151 | #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 2152 | #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 2153 | #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 2154 | #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 2155 | #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 2156 | #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 2157 | #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 2158 | #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 2159 | #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 2160 | #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 2161 | #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 2162 | #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 2163 | #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 2164 | #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 2165 | #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 2166 | #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 2167 | #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 2168 | #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 2169 | #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 2170 | #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 2171 | #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 2172 | |||
| 2173 | /****************** Bit definition for NVIC_IABR register *******************/ |
||
| 2174 | #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ |
||
| 2175 | #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 2176 | #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 2177 | #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 2178 | #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 2179 | #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 2180 | #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 2181 | #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 2182 | #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 2183 | #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 2184 | #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 2185 | #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 2186 | #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 2187 | #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 2188 | #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 2189 | #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 2190 | #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 2191 | #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 2192 | #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 2193 | #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 2194 | #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 2195 | #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 2196 | #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 2197 | #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 2198 | #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 2199 | #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 2200 | #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 2201 | #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 2202 | #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 2203 | #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 2204 | #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 2205 | #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 2206 | #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 2207 | |||
| 2208 | /****************** Bit definition for NVIC_PRI0 register *******************/ |
||
| 2209 | #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ |
||
| 2210 | #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ |
||
| 2211 | #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ |
||
| 2212 | #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ |
||
| 2213 | |||
| 2214 | /****************** Bit definition for NVIC_PRI1 register *******************/ |
||
| 2215 | #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ |
||
| 2216 | #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ |
||
| 2217 | #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ |
||
| 2218 | #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ |
||
| 2219 | |||
| 2220 | /****************** Bit definition for NVIC_PRI2 register *******************/ |
||
| 2221 | #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ |
||
| 2222 | #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ |
||
| 2223 | #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ |
||
| 2224 | #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ |
||
| 2225 | |||
| 2226 | /****************** Bit definition for NVIC_PRI3 register *******************/ |
||
| 2227 | #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ |
||
| 2228 | #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ |
||
| 2229 | #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ |
||
| 2230 | #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ |
||
| 2231 | |||
| 2232 | /****************** Bit definition for NVIC_PRI4 register *******************/ |
||
| 2233 | #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ |
||
| 2234 | #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ |
||
| 2235 | #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ |
||
| 2236 | #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ |
||
| 2237 | |||
| 2238 | /****************** Bit definition for NVIC_PRI5 register *******************/ |
||
| 2239 | #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ |
||
| 2240 | #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ |
||
| 2241 | #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ |
||
| 2242 | #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ |
||
| 2243 | |||
| 2244 | /****************** Bit definition for NVIC_PRI6 register *******************/ |
||
| 2245 | #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ |
||
| 2246 | #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ |
||
| 2247 | #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ |
||
| 2248 | #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ |
||
| 2249 | |||
| 2250 | /****************** Bit definition for NVIC_PRI7 register *******************/ |
||
| 2251 | #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ |
||
| 2252 | #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ |
||
| 2253 | #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ |
||
| 2254 | #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ |
||
| 2255 | |||
| 2256 | /****************** Bit definition for SCB_CPUID register *******************/ |
||
| 2257 | #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ |
||
| 2258 | #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ |
||
| 2259 | #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ |
||
| 2260 | #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ |
||
| 2261 | #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ |
||
| 2262 | |||
| 2263 | /******************* Bit definition for SCB_ICSR register *******************/ |
||
| 2264 | #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ |
||
| 2265 | #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ |
||
| 2266 | #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ |
||
| 2267 | #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ |
||
| 2268 | #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ |
||
| 2269 | #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ |
||
| 2270 | #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ |
||
| 2271 | #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ |
||
| 2272 | #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ |
||
| 2273 | #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ |
||
| 2274 | |||
| 2275 | /******************* Bit definition for SCB_VTOR register *******************/ |
||
| 2276 | #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ |
||
| 2277 | #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ |
||
| 2278 | |||
| 2279 | /*!<***************** Bit definition for SCB_AIRCR register *******************/ |
||
| 2280 | #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ |
||
| 2281 | #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ |
||
| 2282 | #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ |
||
| 2283 | |||
| 2284 | #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ |
||
| 2285 | #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 2286 | #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 2287 | #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 2288 | |||
| 2289 | /* prority group configuration */ |
||
| 2290 | #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ |
||
| 2291 | #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ |
||
| 2292 | #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ |
||
| 2293 | #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ |
||
| 2294 | #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ |
||
| 2295 | #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ |
||
| 2296 | #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ |
||
| 2297 | #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ |
||
| 2298 | |||
| 2299 | #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ |
||
| 2300 | #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ |
||
| 2301 | |||
| 2302 | /******************* Bit definition for SCB_SCR register ********************/ |
||
| 2303 | #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */ |
||
| 2304 | #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */ |
||
| 2305 | #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */ |
||
| 2306 | |||
| 2307 | /******************** Bit definition for SCB_CCR register *******************/ |
||
| 2308 | #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ |
||
| 2309 | #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ |
||
| 2310 | #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */ |
||
| 2311 | #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */ |
||
| 2312 | #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */ |
||
| 2313 | #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ |
||
| 2314 | |||
| 2315 | /******************* Bit definition for SCB_SHPR register ********************/ |
||
| 2316 | #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ |
||
| 2317 | #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ |
||
| 2318 | #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ |
||
| 2319 | #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ |
||
| 2320 | |||
| 2321 | /****************** Bit definition for SCB_SHCSR register *******************/ |
||
| 2322 | #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ |
||
| 2323 | #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ |
||
| 2324 | #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ |
||
| 2325 | #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ |
||
| 2326 | #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ |
||
| 2327 | #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ |
||
| 2328 | #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ |
||
| 2329 | #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ |
||
| 2330 | #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ |
||
| 2331 | #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ |
||
| 2332 | #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ |
||
| 2333 | #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ |
||
| 2334 | #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ |
||
| 2335 | #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ |
||
| 2336 | |||
| 2337 | /******************* Bit definition for SCB_CFSR register *******************/ |
||
| 2338 | /*!< MFSR */ |
||
| 2339 | #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ |
||
| 2340 | #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ |
||
| 2341 | #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ |
||
| 2342 | #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ |
||
| 2343 | #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ |
||
| 2344 | /*!< BFSR */ |
||
| 2345 | #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ |
||
| 2346 | #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ |
||
| 2347 | #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ |
||
| 2348 | #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ |
||
| 2349 | #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ |
||
| 2350 | #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ |
||
| 2351 | /*!< UFSR */ |
||
| 2352 | #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ |
||
| 2353 | #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ |
||
| 2354 | #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ |
||
| 2355 | #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ |
||
| 2356 | #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ |
||
| 2357 | #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ |
||
| 2358 | |||
| 2359 | /******************* Bit definition for SCB_HFSR register *******************/ |
||
| 2360 | #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ |
||
| 2361 | #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ |
||
| 2362 | #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ |
||
| 2363 | |||
| 2364 | /******************* Bit definition for SCB_DFSR register *******************/ |
||
| 2365 | #define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */ |
||
| 2366 | #define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */ |
||
| 2367 | #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */ |
||
| 2368 | #define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */ |
||
| 2369 | #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */ |
||
| 2370 | |||
| 2371 | /******************* Bit definition for SCB_MMFAR register ******************/ |
||
| 2372 | #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ |
||
| 2373 | |||
| 2374 | /******************* Bit definition for SCB_BFAR register *******************/ |
||
| 2375 | #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ |
||
| 2376 | |||
| 2377 | /******************* Bit definition for SCB_afsr register *******************/ |
||
| 2378 | #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ |
||
| 2379 | |||
| 2380 | /******************************************************************************/ |
||
| 2381 | /* */ |
||
| 2382 | /* External Interrupt/Event Controller */ |
||
| 2383 | /* */ |
||
| 2384 | /******************************************************************************/ |
||
| 2385 | |||
| 2386 | /******************* Bit definition for EXTI_IMR register *******************/ |
||
| 2387 | #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
||
| 2388 | #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
||
| 2389 | #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
||
| 2390 | #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
||
| 2391 | #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
||
| 2392 | #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
||
| 2393 | #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
||
| 2394 | #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
||
| 2395 | #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
||
| 2396 | #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
||
| 2397 | #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
||
| 2398 | #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
||
| 2399 | #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
||
| 2400 | #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
||
| 2401 | #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
||
| 2402 | #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
||
| 2403 | #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
||
| 2404 | #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
||
| 2405 | #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
||
| 2406 | #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
||
| 2407 | |||
| 2408 | /******************* Bit definition for EXTI_EMR register *******************/ |
||
| 2409 | #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
||
| 2410 | #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
||
| 2411 | #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
||
| 2412 | #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
||
| 2413 | #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
||
| 2414 | #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
||
| 2415 | #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
||
| 2416 | #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
||
| 2417 | #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
||
| 2418 | #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
||
| 2419 | #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
||
| 2420 | #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
||
| 2421 | #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
||
| 2422 | #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
||
| 2423 | #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
||
| 2424 | #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
||
| 2425 | #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
||
| 2426 | #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
||
| 2427 | #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
||
| 2428 | #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
||
| 2429 | |||
| 2430 | /****************** Bit definition for EXTI_RTSR register *******************/ |
||
| 2431 | #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
||
| 2432 | #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
||
| 2433 | #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
||
| 2434 | #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
||
| 2435 | #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
||
| 2436 | #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
||
| 2437 | #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
||
| 2438 | #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
||
| 2439 | #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
||
| 2440 | #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
||
| 2441 | #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
||
| 2442 | #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
||
| 2443 | #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
||
| 2444 | #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
||
| 2445 | #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
||
| 2446 | #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
||
| 2447 | #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
||
| 2448 | #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ |
||
| 2449 | #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
||
| 2450 | #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
||
| 2451 | |||
| 2452 | /****************** Bit definition for EXTI_FTSR register *******************/ |
||
| 2453 | #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
||
| 2454 | #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
||
| 2455 | #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
||
| 2456 | #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
||
| 2457 | #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
||
| 2458 | #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
||
| 2459 | #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
||
| 2460 | #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
||
| 2461 | #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
||
| 2462 | #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
||
| 2463 | #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
||
| 2464 | #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
||
| 2465 | #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
||
| 2466 | #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
||
| 2467 | #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
||
| 2468 | #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
||
| 2469 | #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
||
| 2470 | #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ |
||
| 2471 | #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
||
| 2472 | #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
||
| 2473 | |||
| 2474 | /****************** Bit definition for EXTI_SWIER register ******************/ |
||
| 2475 | #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
||
| 2476 | #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
||
| 2477 | #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
||
| 2478 | #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
||
| 2479 | #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
||
| 2480 | #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
||
| 2481 | #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
||
| 2482 | #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
||
| 2483 | #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
||
| 2484 | #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
||
| 2485 | #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
||
| 2486 | #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
||
| 2487 | #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
||
| 2488 | #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
||
| 2489 | #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
||
| 2490 | #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
||
| 2491 | #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
||
| 2492 | #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ |
||
| 2493 | #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
||
| 2494 | #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
||
| 2495 | |||
| 2496 | /******************* Bit definition for EXTI_PR register ********************/ |
||
| 2497 | #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
||
| 2498 | #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
||
| 2499 | #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
||
| 2500 | #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
||
| 2501 | #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
||
| 2502 | #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
||
| 2503 | #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
||
| 2504 | #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
||
| 2505 | #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
||
| 2506 | #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
||
| 2507 | #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
||
| 2508 | #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
||
| 2509 | #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
||
| 2510 | #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
||
| 2511 | #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
||
| 2512 | #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
||
| 2513 | #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
||
| 2514 | #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ |
||
| 2515 | #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
||
| 2516 | #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
||
| 2517 | |||
| 2518 | /******************************************************************************/ |
||
| 2519 | /* */ |
||
| 2520 | /* DMA Controller */ |
||
| 2521 | /* */ |
||
| 2522 | /******************************************************************************/ |
||
| 2523 | |||
| 2524 | /******************* Bit definition for DMA_ISR register ********************/ |
||
| 2525 | #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ |
||
| 2526 | #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ |
||
| 2527 | #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ |
||
| 2528 | #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ |
||
| 2529 | #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ |
||
| 2530 | #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ |
||
| 2531 | #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ |
||
| 2532 | #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ |
||
| 2533 | #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ |
||
| 2534 | #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ |
||
| 2535 | #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ |
||
| 2536 | #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ |
||
| 2537 | #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ |
||
| 2538 | #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ |
||
| 2539 | #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ |
||
| 2540 | #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ |
||
| 2541 | #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ |
||
| 2542 | #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ |
||
| 2543 | #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ |
||
| 2544 | #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ |
||
| 2545 | #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ |
||
| 2546 | #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ |
||
| 2547 | #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ |
||
| 2548 | #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ |
||
| 2549 | #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ |
||
| 2550 | #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ |
||
| 2551 | #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ |
||
| 2552 | #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ |
||
| 2553 | |||
| 2554 | /******************* Bit definition for DMA_IFCR register *******************/ |
||
| 2555 | #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ |
||
| 2556 | #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ |
||
| 2557 | #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ |
||
| 2558 | #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ |
||
| 2559 | #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ |
||
| 2560 | #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ |
||
| 2561 | #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ |
||
| 2562 | #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ |
||
| 2563 | #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ |
||
| 2564 | #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ |
||
| 2565 | #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ |
||
| 2566 | #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ |
||
| 2567 | #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ |
||
| 2568 | #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ |
||
| 2569 | #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ |
||
| 2570 | #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ |
||
| 2571 | #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ |
||
| 2572 | #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ |
||
| 2573 | #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ |
||
| 2574 | #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ |
||
| 2575 | #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ |
||
| 2576 | #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ |
||
| 2577 | #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ |
||
| 2578 | #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ |
||
| 2579 | #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ |
||
| 2580 | #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ |
||
| 2581 | #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ |
||
| 2582 | #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ |
||
| 2583 | |||
| 2584 | /******************* Bit definition for DMA_CCR register *******************/ |
||
| 2585 | #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ |
||
| 2586 | #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ |
||
| 2587 | #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ |
||
| 2588 | #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ |
||
| 2589 | #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ |
||
| 2590 | #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ |
||
| 2591 | #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ |
||
| 2592 | #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ |
||
| 2593 | |||
| 2594 | #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
||
| 2595 | #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 2596 | #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 2597 | |||
| 2598 | #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ |
||
| 2599 | #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2600 | #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2601 | |||
| 2602 | #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */ |
||
| 2603 | #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 2604 | #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 2605 | |||
| 2606 | #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ |
||
| 2607 | |||
| 2608 | /****************** Bit definition for DMA_CNDTR register ******************/ |
||
| 2609 | #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ |
||
| 2610 | |||
| 2611 | /****************** Bit definition for DMA_CPAR register *******************/ |
||
| 2612 | #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
||
| 2613 | |||
| 2614 | /****************** Bit definition for DMA_CMAR register *******************/ |
||
| 2615 | #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
||
| 2616 | |||
| 2617 | /******************************************************************************/ |
||
| 2618 | /* */ |
||
| 2619 | /* Analog to Digital Converter */ |
||
| 2620 | /* */ |
||
| 2621 | /******************************************************************************/ |
||
| 2622 | |||
| 2623 | /******************** Bit definition for ADC_SR register ********************/ |
||
| 2624 | #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ |
||
| 2625 | #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ |
||
| 2626 | #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ |
||
| 2627 | #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ |
||
| 2628 | #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ |
||
| 2629 | |||
| 2630 | /******************* Bit definition for ADC_CR1 register ********************/ |
||
| 2631 | #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
||
| 2632 | #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2633 | #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2634 | #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2635 | #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2636 | #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2637 | |||
| 2638 | #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ |
||
| 2639 | #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ |
||
| 2640 | #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ |
||
| 2641 | #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ |
||
| 2642 | #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ |
||
| 2643 | #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ |
||
| 2644 | #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ |
||
| 2645 | #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ |
||
| 2646 | |||
| 2647 | #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
||
| 2648 | #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
||
| 2649 | #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
||
| 2650 | #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
||
| 2651 | |||
| 2652 | #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ |
||
| 2653 | #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 2654 | #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 2655 | #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
||
| 2656 | #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
||
| 2657 | |||
| 2658 | #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ |
||
| 2659 | #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ |
||
| 2660 | |||
| 2661 | |||
| 2662 | /******************* Bit definition for ADC_CR2 register ********************/ |
||
| 2663 | #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ |
||
| 2664 | #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ |
||
| 2665 | #define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ |
||
| 2666 | #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ |
||
| 2667 | #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ |
||
| 2668 | #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ |
||
| 2669 | |||
| 2670 | #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ |
||
| 2671 | #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 2672 | #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 2673 | #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
||
| 2674 | |||
| 2675 | #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ |
||
| 2676 | |||
| 2677 | #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ |
||
| 2678 | #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
||
| 2679 | #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
||
| 2680 | #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
||
| 2681 | |||
| 2682 | #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ |
||
| 2683 | #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ |
||
| 2684 | #define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ |
||
| 2685 | #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ |
||
| 2686 | |||
| 2687 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
||
| 2688 | #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ |
||
| 2689 | #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2690 | #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2691 | #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2692 | |||
| 2693 | #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ |
||
| 2694 | #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
||
| 2695 | #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
||
| 2696 | #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
||
| 2697 | |||
| 2698 | #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ |
||
| 2699 | #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 2700 | #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 2701 | #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ |
||
| 2702 | |||
| 2703 | #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ |
||
| 2704 | #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 2705 | #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 2706 | #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
||
| 2707 | |||
| 2708 | #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ |
||
| 2709 | #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 2710 | #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 2711 | #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
||
| 2712 | |||
| 2713 | #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ |
||
| 2714 | #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2715 | #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2716 | #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2717 | |||
| 2718 | #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ |
||
| 2719 | #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 2720 | #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 2721 | #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
||
| 2722 | |||
| 2723 | #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ |
||
| 2724 | #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
||
| 2725 | #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
||
| 2726 | #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ |
||
| 2727 | |||
| 2728 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
||
| 2729 | #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ |
||
| 2730 | #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2731 | #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2732 | #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2733 | |||
| 2734 | #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ |
||
| 2735 | #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
||
| 2736 | #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
||
| 2737 | #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
||
| 2738 | |||
| 2739 | #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ |
||
| 2740 | #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 2741 | #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 2742 | #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ |
||
| 2743 | |||
| 2744 | #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ |
||
| 2745 | #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 2746 | #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 2747 | #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
||
| 2748 | |||
| 2749 | #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ |
||
| 2750 | #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 2751 | #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 2752 | #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
||
| 2753 | |||
| 2754 | #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ |
||
| 2755 | #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2756 | #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2757 | #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2758 | |||
| 2759 | #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ |
||
| 2760 | #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 2761 | #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 2762 | #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
||
| 2763 | |||
| 2764 | #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ |
||
| 2765 | #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
||
| 2766 | #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
||
| 2767 | #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ |
||
| 2768 | |||
| 2769 | #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ |
||
| 2770 | #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 2771 | #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 2772 | #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 2773 | |||
| 2774 | #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ |
||
| 2775 | #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ |
||
| 2776 | #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ |
||
| 2777 | #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ |
||
| 2778 | |||
| 2779 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
||
| 2780 | #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ |
||
| 2781 | |||
| 2782 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
||
| 2783 | #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ |
||
| 2784 | |||
| 2785 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
||
| 2786 | #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ |
||
| 2787 | |||
| 2788 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
||
| 2789 | #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ |
||
| 2790 | |||
| 2791 | /******************* Bit definition for ADC_HTR register ********************/ |
||
| 2792 | #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ |
||
| 2793 | |||
| 2794 | /******************* Bit definition for ADC_LTR register ********************/ |
||
| 2795 | #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ |
||
| 2796 | |||
| 2797 | /******************* Bit definition for ADC_SQR1 register *******************/ |
||
| 2798 | #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ |
||
| 2799 | #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2800 | #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2801 | #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2802 | #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2803 | #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2804 | |||
| 2805 | #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ |
||
| 2806 | #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 2807 | #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 2808 | #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 2809 | #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
||
| 2810 | #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
||
| 2811 | |||
| 2812 | #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ |
||
| 2813 | #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2814 | #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2815 | #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 2816 | #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 2817 | #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 2818 | |||
| 2819 | #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ |
||
| 2820 | #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2821 | #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2822 | #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2823 | #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
||
| 2824 | #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
||
| 2825 | |||
| 2826 | #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ |
||
| 2827 | #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 2828 | #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 2829 | #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
||
| 2830 | #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
||
| 2831 | |||
| 2832 | /******************* Bit definition for ADC_SQR2 register *******************/ |
||
| 2833 | #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ |
||
| 2834 | #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2835 | #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2836 | #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2837 | #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2838 | #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2839 | |||
| 2840 | #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ |
||
| 2841 | #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 2842 | #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 2843 | #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 2844 | #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
||
| 2845 | #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
||
| 2846 | |||
| 2847 | #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ |
||
| 2848 | #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2849 | #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2850 | #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 2851 | #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 2852 | #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 2853 | |||
| 2854 | #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ |
||
| 2855 | #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2856 | #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2857 | #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2858 | #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
||
| 2859 | #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
||
| 2860 | |||
| 2861 | #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ |
||
| 2862 | #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 2863 | #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 2864 | #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
||
| 2865 | #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
||
| 2866 | #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ |
||
| 2867 | |||
| 2868 | #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ |
||
| 2869 | #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ |
||
| 2870 | #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ |
||
| 2871 | #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ |
||
| 2872 | #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ |
||
| 2873 | #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ |
||
| 2874 | |||
| 2875 | /******************* Bit definition for ADC_SQR3 register *******************/ |
||
| 2876 | #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ |
||
| 2877 | #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2878 | #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2879 | #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2880 | #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2881 | #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2882 | |||
| 2883 | #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ |
||
| 2884 | #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 2885 | #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 2886 | #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 2887 | #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
||
| 2888 | #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
||
| 2889 | |||
| 2890 | #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ |
||
| 2891 | #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2892 | #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2893 | #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 2894 | #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 2895 | #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 2896 | |||
| 2897 | #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ |
||
| 2898 | #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2899 | #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2900 | #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2901 | #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
||
| 2902 | #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
||
| 2903 | |||
| 2904 | #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ |
||
| 2905 | #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 2906 | #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 2907 | #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
||
| 2908 | #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
||
| 2909 | #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ |
||
| 2910 | |||
| 2911 | #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ |
||
| 2912 | #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ |
||
| 2913 | #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ |
||
| 2914 | #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ |
||
| 2915 | #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ |
||
| 2916 | #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ |
||
| 2917 | |||
| 2918 | /******************* Bit definition for ADC_JSQR register *******************/ |
||
| 2919 | #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ |
||
| 2920 | #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2921 | #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2922 | #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2923 | #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2924 | #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2925 | |||
| 2926 | #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
||
| 2927 | #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 2928 | #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 2929 | #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 2930 | #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
||
| 2931 | #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
||
| 2932 | |||
| 2933 | #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
||
| 2934 | #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2935 | #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2936 | #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 2937 | #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 2938 | #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 2939 | |||
| 2940 | #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ |
||
| 2941 | #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2942 | #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2943 | #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2944 | #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
||
| 2945 | #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
||
| 2946 | |||
| 2947 | #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ |
||
| 2948 | #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 2949 | #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 2950 | |||
| 2951 | /******************* Bit definition for ADC_JDR1 register *******************/ |
||
| 2952 | #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ |
||
| 2953 | |||
| 2954 | /******************* Bit definition for ADC_JDR2 register *******************/ |
||
| 2955 | #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ |
||
| 2956 | |||
| 2957 | /******************* Bit definition for ADC_JDR3 register *******************/ |
||
| 2958 | #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ |
||
| 2959 | |||
| 2960 | /******************* Bit definition for ADC_JDR4 register *******************/ |
||
| 2961 | #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ |
||
| 2962 | |||
| 2963 | /******************** Bit definition for ADC_DR register ********************/ |
||
| 2964 | #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ |
||
| 2965 | #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ |
||
| 2966 | /******************************************************************************/ |
||
| 2967 | /* */ |
||
| 2968 | /* Digital to Analog Converter */ |
||
| 2969 | /* */ |
||
| 2970 | /******************************************************************************/ |
||
| 2971 | |||
| 2972 | /******************** Bit definition for DAC_CR register ********************/ |
||
| 2973 | #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ |
||
| 2974 | #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ |
||
| 2975 | #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ |
||
| 2976 | |||
| 2977 | #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ |
||
| 2978 | #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
||
| 2979 | #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
||
| 2980 | #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
||
| 2981 | |||
| 2982 | #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
||
| 2983 | #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 2984 | #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 2985 | |||
| 2986 | #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
||
| 2987 | #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 2988 | #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 2989 | #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 2990 | #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
||
| 2991 | |||
| 2992 | #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ |
||
| 2993 | #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ |
||
| 2994 | #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ |
||
| 2995 | #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ |
||
| 2996 | |||
| 2997 | #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ |
||
| 2998 | #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ |
||
| 2999 | #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ |
||
| 3000 | #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ |
||
| 3001 | |||
| 3002 | #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
||
| 3003 | #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
||
| 3004 | #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
||
| 3005 | |||
| 3006 | #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
||
| 3007 | #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 3008 | #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 3009 | #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 3010 | #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
||
| 3011 | |||
| 3012 | #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ |
||
| 3013 | |||
| 3014 | |||
| 3015 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
||
| 3016 | #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */ |
||
| 3017 | #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */ |
||
| 3018 | |||
| 3019 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
||
| 3020 | #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ |
||
| 3021 | |||
| 3022 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
||
| 3023 | #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ |
||
| 3024 | |||
| 3025 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
||
| 3026 | #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ |
||
| 3027 | |||
| 3028 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
||
| 3029 | #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */ |
||
| 3030 | |||
| 3031 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
||
| 3032 | #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */ |
||
| 3033 | |||
| 3034 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
||
| 3035 | #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */ |
||
| 3036 | |||
| 3037 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
||
| 3038 | #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ |
||
| 3039 | #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ |
||
| 3040 | |||
| 3041 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
||
| 3042 | #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ |
||
| 3043 | #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ |
||
| 3044 | |||
| 3045 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
||
| 3046 | #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ |
||
| 3047 | #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */ |
||
| 3048 | |||
| 3049 | /******************* Bit definition for DAC_DOR1 register *******************/ |
||
| 3050 | #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */ |
||
| 3051 | |||
| 3052 | /******************* Bit definition for DAC_DOR2 register *******************/ |
||
| 3053 | #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */ |
||
| 3054 | |||
| 3055 | |||
| 3056 | |||
| 3057 | /*****************************************************************************/ |
||
| 3058 | /* */ |
||
| 3059 | /* Timers (TIM) */ |
||
| 3060 | /* */ |
||
| 3061 | /*****************************************************************************/ |
||
| 3062 | /******************* Bit definition for TIM_CR1 register *******************/ |
||
| 3063 | #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */ |
||
| 3064 | #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */ |
||
| 3065 | #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */ |
||
| 3066 | #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */ |
||
| 3067 | #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */ |
||
| 3068 | |||
| 3069 | #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
||
| 3070 | #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
||
| 3071 | #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
||
| 3072 | |||
| 3073 | #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */ |
||
| 3074 | |||
| 3075 | #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */ |
||
| 3076 | #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 3077 | #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 3078 | |||
| 3079 | /******************* Bit definition for TIM_CR2 register *******************/ |
||
| 3080 | #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */ |
||
| 3081 | #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */ |
||
| 3082 | #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */ |
||
| 3083 | |||
| 3084 | #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */ |
||
| 3085 | #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 3086 | #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 3087 | #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 3088 | |||
| 3089 | #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */ |
||
| 3090 | #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */ |
||
| 3091 | #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */ |
||
| 3092 | #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */ |
||
| 3093 | #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */ |
||
| 3094 | #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */ |
||
| 3095 | #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */ |
||
| 3096 | #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */ |
||
| 3097 | |||
| 3098 | /******************* Bit definition for TIM_SMCR register ******************/ |
||
| 3099 | #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */ |
||
| 3100 | #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 3101 | #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 3102 | #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
||
| 3103 | |||
| 3104 | #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */ |
||
| 3105 | |||
| 3106 | #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */ |
||
| 3107 | #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 3108 | #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 3109 | #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 3110 | |||
| 3111 | #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */ |
||
| 3112 | |||
| 3113 | #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */ |
||
| 3114 | #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 3115 | #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 3116 | #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
||
| 3117 | #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
||
| 3118 | |||
| 3119 | #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */ |
||
| 3120 | #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 3121 | #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 3122 | |||
| 3123 | #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */ |
||
| 3124 | #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */ |
||
| 3125 | |||
| 3126 | /******************* Bit definition for TIM_DIER register ******************/ |
||
| 3127 | #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */ |
||
| 3128 | #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */ |
||
| 3129 | #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */ |
||
| 3130 | #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */ |
||
| 3131 | #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */ |
||
| 3132 | #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */ |
||
| 3133 | #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */ |
||
| 3134 | #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */ |
||
| 3135 | #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */ |
||
| 3136 | #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */ |
||
| 3137 | #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */ |
||
| 3138 | #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */ |
||
| 3139 | #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */ |
||
| 3140 | #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */ |
||
| 3141 | #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */ |
||
| 3142 | |||
| 3143 | /******************** Bit definition for TIM_SR register *******************/ |
||
| 3144 | #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */ |
||
| 3145 | #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */ |
||
| 3146 | #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */ |
||
| 3147 | #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */ |
||
| 3148 | #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */ |
||
| 3149 | #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */ |
||
| 3150 | #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */ |
||
| 3151 | #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */ |
||
| 3152 | #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */ |
||
| 3153 | #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */ |
||
| 3154 | #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */ |
||
| 3155 | #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */ |
||
| 3156 | |||
| 3157 | /******************* Bit definition for TIM_EGR register *******************/ |
||
| 3158 | #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */ |
||
| 3159 | #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */ |
||
| 3160 | #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */ |
||
| 3161 | #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */ |
||
| 3162 | #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */ |
||
| 3163 | #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */ |
||
| 3164 | #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */ |
||
| 3165 | #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */ |
||
| 3166 | |||
| 3167 | /****************** Bit definition for TIM_CCMR1 register ******************/ |
||
| 3168 | #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
||
| 3169 | #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 3170 | #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 3171 | |||
| 3172 | #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */ |
||
| 3173 | #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */ |
||
| 3174 | |||
| 3175 | #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
||
| 3176 | #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 3177 | #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 3178 | #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 3179 | |||
| 3180 | #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */ |
||
| 3181 | |||
| 3182 | #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
||
| 3183 | #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 3184 | #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 3185 | |||
| 3186 | #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */ |
||
| 3187 | #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */ |
||
| 3188 | |||
| 3189 | #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
||
| 3190 | #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 3191 | #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 3192 | #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
||
| 3193 | |||
| 3194 | #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */ |
||
| 3195 | |||
| 3196 | /*---------------------------------------------------------------------------*/ |
||
| 3197 | |||
| 3198 | #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
||
| 3199 | #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
||
| 3200 | #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
||
| 3201 | |||
| 3202 | #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
||
| 3203 | #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 3204 | #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 3205 | #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 3206 | #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
||
| 3207 | |||
| 3208 | #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
||
| 3209 | #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
||
| 3210 | #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
||
| 3211 | |||
| 3212 | #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
||
| 3213 | #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 3214 | #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 3215 | #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
||
| 3216 | #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ |
||
| 3217 | |||
| 3218 | /****************** Bit definition for TIM_CCMR2 register ******************/ |
||
| 3219 | #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
||
| 3220 | #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 3221 | #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 3222 | |||
| 3223 | #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */ |
||
| 3224 | #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */ |
||
| 3225 | |||
| 3226 | #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
||
| 3227 | #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 3228 | #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 3229 | #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 3230 | |||
| 3231 | #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */ |
||
| 3232 | |||
| 3233 | #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
||
| 3234 | #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 3235 | #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 3236 | |||
| 3237 | #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ |
||
| 3238 | #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ |
||
| 3239 | |||
| 3240 | #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
||
| 3241 | #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 3242 | #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 3243 | #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
||
| 3244 | |||
| 3245 | #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ |
||
| 3246 | |||
| 3247 | /*---------------------------------------------------------------------------*/ |
||
| 3248 | |||
| 3249 | #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
||
| 3250 | #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
||
| 3251 | #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
||
| 3252 | |||
| 3253 | #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
||
| 3254 | #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 3255 | #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 3256 | #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 3257 | #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
||
| 3258 | |||
| 3259 | #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
||
| 3260 | #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
||
| 3261 | #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
||
| 3262 | |||
| 3263 | #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
||
| 3264 | #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 3265 | #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 3266 | #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
||
| 3267 | #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ |
||
| 3268 | |||
| 3269 | /******************* Bit definition for TIM_CCER register ******************/ |
||
| 3270 | #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */ |
||
| 3271 | #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */ |
||
| 3272 | #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */ |
||
| 3273 | #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */ |
||
| 3274 | #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */ |
||
| 3275 | #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */ |
||
| 3276 | #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */ |
||
| 3277 | #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */ |
||
| 3278 | #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */ |
||
| 3279 | #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */ |
||
| 3280 | #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */ |
||
| 3281 | #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */ |
||
| 3282 | #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */ |
||
| 3283 | #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */ |
||
| 3284 | #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */ |
||
| 3285 | |||
| 3286 | /******************* Bit definition for TIM_CNT register *******************/ |
||
| 3287 | #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ |
||
| 3288 | |||
| 3289 | /******************* Bit definition for TIM_PSC register *******************/ |
||
| 3290 | #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */ |
||
| 3291 | |||
| 3292 | /******************* Bit definition for TIM_ARR register *******************/ |
||
| 3293 | #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */ |
||
| 3294 | |||
| 3295 | /******************* Bit definition for TIM_RCR register *******************/ |
||
| 3296 | #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */ |
||
| 3297 | |||
| 3298 | /******************* Bit definition for TIM_CCR1 register ******************/ |
||
| 3299 | #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */ |
||
| 3300 | |||
| 3301 | /******************* Bit definition for TIM_CCR2 register ******************/ |
||
| 3302 | #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */ |
||
| 3303 | |||
| 3304 | /******************* Bit definition for TIM_CCR3 register ******************/ |
||
| 3305 | #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */ |
||
| 3306 | |||
| 3307 | /******************* Bit definition for TIM_CCR4 register ******************/ |
||
| 3308 | #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */ |
||
| 3309 | |||
| 3310 | /******************* Bit definition for TIM_BDTR register ******************/ |
||
| 3311 | #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
||
| 3312 | #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 3313 | #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 3314 | #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
||
| 3315 | #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
||
| 3316 | #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
||
| 3317 | #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
||
| 3318 | #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
||
| 3319 | #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
||
| 3320 | |||
| 3321 | #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */ |
||
| 3322 | #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 3323 | #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 3324 | |||
| 3325 | #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */ |
||
| 3326 | #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */ |
||
| 3327 | #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */ |
||
| 3328 | #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */ |
||
| 3329 | #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */ |
||
| 3330 | #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */ |
||
| 3331 | |||
| 3332 | /******************* Bit definition for TIM_DCR register *******************/ |
||
| 3333 | #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */ |
||
| 3334 | #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 3335 | #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 3336 | #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
||
| 3337 | #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
||
| 3338 | #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
||
| 3339 | |||
| 3340 | #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */ |
||
| 3341 | #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 3342 | #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 3343 | #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
||
| 3344 | #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
||
| 3345 | #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
||
| 3346 | |||
| 3347 | /******************* Bit definition for TIM_DMAR register ******************/ |
||
| 3348 | #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */ |
||
| 3349 | |||
| 3350 | /******************* Bit definition for TIM_OR register ********************/ |
||
| 3351 | |||
| 3352 | /******************************************************************************/ |
||
| 3353 | /* */ |
||
| 3354 | /* Real-Time Clock */ |
||
| 3355 | /* */ |
||
| 3356 | /******************************************************************************/ |
||
| 3357 | |||
| 3358 | /******************* Bit definition for RTC_CRH register ********************/ |
||
| 3359 | #define RTC_CRH_SECIE ((uint32_t)0x00000001) /*!< Second Interrupt Enable */ |
||
| 3360 | #define RTC_CRH_ALRIE ((uint32_t)0x00000002) /*!< Alarm Interrupt Enable */ |
||
| 3361 | #define RTC_CRH_OWIE ((uint32_t)0x00000004) /*!< OverfloW Interrupt Enable */ |
||
| 3362 | |||
| 3363 | /******************* Bit definition for RTC_CRL register ********************/ |
||
| 3364 | #define RTC_CRL_SECF ((uint32_t)0x00000001) /*!< Second Flag */ |
||
| 3365 | #define RTC_CRL_ALRF ((uint32_t)0x00000002) /*!< Alarm Flag */ |
||
| 3366 | #define RTC_CRL_OWF ((uint32_t)0x00000004) /*!< OverfloW Flag */ |
||
| 3367 | #define RTC_CRL_RSF ((uint32_t)0x00000008) /*!< Registers Synchronized Flag */ |
||
| 3368 | #define RTC_CRL_CNF ((uint32_t)0x00000010) /*!< Configuration Flag */ |
||
| 3369 | #define RTC_CRL_RTOFF ((uint32_t)0x00000020) /*!< RTC operation OFF */ |
||
| 3370 | |||
| 3371 | /******************* Bit definition for RTC_PRLH register *******************/ |
||
| 3372 | #define RTC_PRLH_PRL ((uint32_t)0x0000000F) /*!< RTC Prescaler Reload Value High */ |
||
| 3373 | |||
| 3374 | /******************* Bit definition for RTC_PRLL register *******************/ |
||
| 3375 | #define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /*!< RTC Prescaler Reload Value Low */ |
||
| 3376 | |||
| 3377 | /******************* Bit definition for RTC_DIVH register *******************/ |
||
| 3378 | #define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /*!< RTC Clock Divider High */ |
||
| 3379 | |||
| 3380 | /******************* Bit definition for RTC_DIVL register *******************/ |
||
| 3381 | #define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /*!< RTC Clock Divider Low */ |
||
| 3382 | |||
| 3383 | /******************* Bit definition for RTC_CNTH register *******************/ |
||
| 3384 | #define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter High */ |
||
| 3385 | |||
| 3386 | /******************* Bit definition for RTC_CNTL register *******************/ |
||
| 3387 | #define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter Low */ |
||
| 3388 | |||
| 3389 | /******************* Bit definition for RTC_ALRH register *******************/ |
||
| 3390 | #define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm High */ |
||
| 3391 | |||
| 3392 | /******************* Bit definition for RTC_ALRL register *******************/ |
||
| 3393 | #define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm Low */ |
||
| 3394 | |||
| 3395 | /******************************************************************************/ |
||
| 3396 | /* */ |
||
| 3397 | /* Independent WATCHDOG (IWDG) */ |
||
| 3398 | /* */ |
||
| 3399 | /******************************************************************************/ |
||
| 3400 | |||
| 3401 | /******************* Bit definition for IWDG_KR register ********************/ |
||
| 3402 | #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */ |
||
| 3403 | |||
| 3404 | /******************* Bit definition for IWDG_PR register ********************/ |
||
| 3405 | #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */ |
||
| 3406 | #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3407 | #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3408 | #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3409 | |||
| 3410 | /******************* Bit definition for IWDG_RLR register *******************/ |
||
| 3411 | #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */ |
||
| 3412 | |||
| 3413 | /******************* Bit definition for IWDG_SR register ********************/ |
||
| 3414 | #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */ |
||
| 3415 | #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */ |
||
| 3416 | |||
| 3417 | /******************************************************************************/ |
||
| 3418 | /* */ |
||
| 3419 | /* Window WATCHDOG */ |
||
| 3420 | /* */ |
||
| 3421 | /******************************************************************************/ |
||
| 3422 | |||
| 3423 | /******************* Bit definition for WWDG_CR register ********************/ |
||
| 3424 | #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
||
| 3425 | #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3426 | #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3427 | #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3428 | #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3429 | #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 3430 | #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 3431 | #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 3432 | |||
| 3433 | #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */ |
||
| 3434 | |||
| 3435 | /******************* Bit definition for WWDG_CFR register *******************/ |
||
| 3436 | #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */ |
||
| 3437 | #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3438 | #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3439 | #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3440 | #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3441 | #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 3442 | #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 3443 | #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 3444 | |||
| 3445 | #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */ |
||
| 3446 | #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */ |
||
| 3447 | #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */ |
||
| 3448 | |||
| 3449 | #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */ |
||
| 3450 | |||
| 3451 | /******************* Bit definition for WWDG_SR register ********************/ |
||
| 3452 | #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */ |
||
| 3453 | |||
| 3454 | /******************************************************************************/ |
||
| 3455 | /* */ |
||
| 3456 | /* Flexible Static Memory Controller */ |
||
| 3457 | /* */ |
||
| 3458 | /******************************************************************************/ |
||
| 3459 | |||
| 3460 | /****************** Bit definition for FSMC_BCRx (x=1..4) register **********/ |
||
| 3461 | #define FSMC_BCRx_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ |
||
| 3462 | #define FSMC_BCRx_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ |
||
| 3463 | |||
| 3464 | #define FSMC_BCRx_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ |
||
| 3465 | #define FSMC_BCRx_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
||
| 3466 | #define FSMC_BCRx_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
||
| 3467 | |||
| 3468 | #define FSMC_BCRx_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ |
||
| 3469 | #define FSMC_BCRx_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 3470 | #define FSMC_BCRx_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 3471 | |||
| 3472 | #define FSMC_BCRx_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ |
||
| 3473 | #define FSMC_BCRx_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ |
||
| 3474 | #define FSMC_BCRx_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ |
||
| 3475 | #define FSMC_BCRx_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ |
||
| 3476 | #define FSMC_BCRx_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ |
||
| 3477 | #define FSMC_BCRx_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ |
||
| 3478 | #define FSMC_BCRx_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ |
||
| 3479 | #define FSMC_BCRx_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ |
||
| 3480 | #define FSMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ |
||
| 3481 | #define FSMC_BCRx_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ |
||
| 3482 | |||
| 3483 | /****************** Bit definition for FSMC_BTRx (x=1..4) register ******/ |
||
| 3484 | #define FSMC_BTRx_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
||
| 3485 | #define FSMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3486 | #define FSMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3487 | #define FSMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3488 | #define FSMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3489 | |||
| 3490 | #define FSMC_BTRx_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
||
| 3491 | #define FSMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 3492 | #define FSMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 3493 | #define FSMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
||
| 3494 | #define FSMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
||
| 3495 | |||
| 3496 | #define FSMC_BTRx_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
||
| 3497 | #define FSMC_BTRx_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 3498 | #define FSMC_BTRx_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 3499 | #define FSMC_BTRx_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 3500 | #define FSMC_BTRx_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
||
| 3501 | #define FSMC_BTRx_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
||
| 3502 | #define FSMC_BTRx_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
||
| 3503 | #define FSMC_BTRx_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
||
| 3504 | #define FSMC_BTRx_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
||
| 3505 | |||
| 3506 | #define FSMC_BTRx_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
||
| 3507 | #define FSMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 3508 | #define FSMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 3509 | #define FSMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
||
| 3510 | #define FSMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
||
| 3511 | |||
| 3512 | #define FSMC_BTRx_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
||
| 3513 | #define FSMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 3514 | #define FSMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 3515 | #define FSMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
||
| 3516 | #define FSMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
||
| 3517 | |||
| 3518 | #define FSMC_BTRx_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ |
||
| 3519 | #define FSMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 3520 | #define FSMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 3521 | #define FSMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 3522 | #define FSMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
||
| 3523 | |||
| 3524 | #define FSMC_BTRx_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
||
| 3525 | #define FSMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
||
| 3526 | #define FSMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
||
| 3527 | |||
| 3528 | /****************** Bit definition for FSMC_BWTRx (x=1..4) register ******/ |
||
| 3529 | #define FSMC_BWTRx_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
||
| 3530 | #define FSMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3531 | #define FSMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3532 | #define FSMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3533 | #define FSMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3534 | |||
| 3535 | #define FSMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
||
| 3536 | #define FSMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 3537 | #define FSMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 3538 | #define FSMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
||
| 3539 | #define FSMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
||
| 3540 | |||
| 3541 | #define FSMC_BWTRx_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ |
||
| 3542 | #define FSMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 3543 | #define FSMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 3544 | #define FSMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 3545 | #define FSMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
||
| 3546 | #define FSMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
||
| 3547 | #define FSMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
||
| 3548 | #define FSMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
||
| 3549 | #define FSMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
||
| 3550 | |||
| 3551 | #define FSMC_BWTRx_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
||
| 3552 | #define FSMC_BWTRx_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 3553 | #define FSMC_BWTRx_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 3554 | #define FSMC_BWTRx_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
||
| 3555 | #define FSMC_BWTRx_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
||
| 3556 | |||
| 3557 | #define FSMC_BWTRx_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ |
||
| 3558 | #define FSMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
||
| 3559 | #define FSMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
||
| 3560 | |||
| 3561 | /****************** Bit definition for FSMC_PCRx (x = 2 to 4) register *******************/ |
||
| 3562 | #define FSMC_PCRx_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ |
||
| 3563 | #define FSMC_PCRx_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ |
||
| 3564 | #define FSMC_PCRx_PTYP ((uint32_t)0x00000008) /*!< Memory type */ |
||
| 3565 | |||
| 3566 | #define FSMC_PCRx_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ |
||
| 3567 | #define FSMC_PCRx_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 3568 | #define FSMC_PCRx_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 3569 | |||
| 3570 | #define FSMC_PCRx_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ |
||
| 3571 | |||
| 3572 | #define FSMC_PCRx_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ |
||
| 3573 | #define FSMC_PCRx_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 3574 | #define FSMC_PCRx_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 3575 | #define FSMC_PCRx_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
||
| 3576 | #define FSMC_PCRx_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ |
||
| 3577 | |||
| 3578 | #define FSMC_PCRx_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ |
||
| 3579 | #define FSMC_PCRx_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
||
| 3580 | #define FSMC_PCRx_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
||
| 3581 | #define FSMC_PCRx_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
||
| 3582 | #define FSMC_PCRx_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ |
||
| 3583 | |||
| 3584 | #define FSMC_PCRx_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ |
||
| 3585 | #define FSMC_PCRx_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
||
| 3586 | #define FSMC_PCRx_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
||
| 3587 | #define FSMC_PCRx_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
||
| 3588 | |||
| 3589 | /******************* Bit definition for FSMC_SRx (x = 2 to 4) register *******************/ |
||
| 3590 | #define FSMC_SRx_IRS ((uint32_t)0x00000001) /*!< Interrupt Rising Edge status */ |
||
| 3591 | #define FSMC_SRx_ILS ((uint32_t)0x00000002) /*!< Interrupt Level status */ |
||
| 3592 | #define FSMC_SRx_IFS ((uint32_t)0x00000004) /*!< Interrupt Falling Edge status */ |
||
| 3593 | #define FSMC_SRx_IREN ((uint32_t)0x00000008) /*!< Interrupt Rising Edge detection Enable bit */ |
||
| 3594 | #define FSMC_SRx_ILEN ((uint32_t)0x00000010) /*!< Interrupt Level detection Enable bit */ |
||
| 3595 | #define FSMC_SRx_IFEN ((uint32_t)0x00000020) /*!< Interrupt Falling Edge detection Enable bit */ |
||
| 3596 | #define FSMC_SRx_FEMPT ((uint32_t)0x00000040) /*!< FIFO empty */ |
||
| 3597 | |||
| 3598 | /****************** Bit definition for FSMC_PMEMx (x = 2 to 4) register ******************/ |
||
| 3599 | #define FSMC_PMEMx_MEMSETx ((uint32_t)0x000000FF) /*!< MEMSETx[7:0] bits (Common memory x setup time) */ |
||
| 3600 | #define FSMC_PMEMx_MEMSETx_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3601 | #define FSMC_PMEMx_MEMSETx_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3602 | #define FSMC_PMEMx_MEMSETx_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3603 | #define FSMC_PMEMx_MEMSETx_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3604 | #define FSMC_PMEMx_MEMSETx_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 3605 | #define FSMC_PMEMx_MEMSETx_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 3606 | #define FSMC_PMEMx_MEMSETx_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 3607 | #define FSMC_PMEMx_MEMSETx_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
||
| 3608 | |||
| 3609 | #define FSMC_PMEMx_MEMWAITx ((uint32_t)0x0000FF00) /*!< MEMWAITx[7:0] bits (Common memory x wait time) */ |
||
| 3610 | #define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 3611 | #define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 3612 | #define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 3613 | #define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
||
| 3614 | #define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
||
| 3615 | #define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
||
| 3616 | #define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
||
| 3617 | #define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
||
| 3618 | |||
| 3619 | #define FSMC_PMEMx_MEMHOLDx ((uint32_t)0x00FF0000) /*!< MEMHOLDx[7:0] bits (Common memory x hold time) */ |
||
| 3620 | #define FSMC_PMEMx_MEMHOLDx_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 3621 | #define FSMC_PMEMx_MEMHOLDx_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 3622 | #define FSMC_PMEMx_MEMHOLDx_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
||
| 3623 | #define FSMC_PMEMx_MEMHOLDx_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
||
| 3624 | #define FSMC_PMEMx_MEMHOLDx_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
||
| 3625 | #define FSMC_PMEMx_MEMHOLDx_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
||
| 3626 | #define FSMC_PMEMx_MEMHOLDx_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
||
| 3627 | #define FSMC_PMEMx_MEMHOLDx_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
||
| 3628 | |||
| 3629 | #define FSMC_PMEMx_MEMHIZx ((uint32_t)0xFF000000) /*!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) */ |
||
| 3630 | #define FSMC_PMEMx_MEMHIZx_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 3631 | #define FSMC_PMEMx_MEMHIZx_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 3632 | #define FSMC_PMEMx_MEMHIZx_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 3633 | #define FSMC_PMEMx_MEMHIZx_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
||
| 3634 | #define FSMC_PMEMx_MEMHIZx_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
||
| 3635 | #define FSMC_PMEMx_MEMHIZx_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
||
| 3636 | #define FSMC_PMEMx_MEMHIZx_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
||
| 3637 | #define FSMC_PMEMx_MEMHIZx_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
||
| 3638 | |||
| 3639 | /****************** Bit definition for FSMC_PATTx (x = 2 to 4) register ******************/ |
||
| 3640 | #define FSMC_PATTx_ATTSETx ((uint32_t)0x000000FF) /*!< ATTSETx[7:0] bits (Attribute memory x setup time) */ |
||
| 3641 | #define FSMC_PATTx_ATTSETx_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3642 | #define FSMC_PATTx_ATTSETx_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3643 | #define FSMC_PATTx_ATTSETx_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3644 | #define FSMC_PATTx_ATTSETx_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3645 | #define FSMC_PATTx_ATTSETx_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 3646 | #define FSMC_PATTx_ATTSETx_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 3647 | #define FSMC_PATTx_ATTSETx_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 3648 | #define FSMC_PATTx_ATTSETx_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
||
| 3649 | |||
| 3650 | #define FSMC_PATTx_ATTWAITx ((uint32_t)0x0000FF00) /*!< ATTWAITx[7:0] bits (Attribute memory x wait time) */ |
||
| 3651 | #define FSMC_PATTx_ATTWAITx_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 3652 | #define FSMC_PATTx_ATTWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 3653 | #define FSMC_PATTx_ATTWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 3654 | #define FSMC_PATTx_ATTWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
||
| 3655 | #define FSMC_PATTx_ATTWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
||
| 3656 | #define FSMC_PATTx_ATTWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
||
| 3657 | #define FSMC_PATTx_ATTWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
||
| 3658 | #define FSMC_PATTx_ATTWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
||
| 3659 | |||
| 3660 | #define FSMC_PATTx_ATTHOLDx ((uint32_t)0x00FF0000) /*!< ATTHOLDx[7:0] bits (Attribute memory x hold time) */ |
||
| 3661 | #define FSMC_PATTx_ATTHOLDx_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 3662 | #define FSMC_PATTx_ATTHOLDx_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 3663 | #define FSMC_PATTx_ATTHOLDx_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
||
| 3664 | #define FSMC_PATTx_ATTHOLDx_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
||
| 3665 | #define FSMC_PATTx_ATTHOLDx_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
||
| 3666 | #define FSMC_PATTx_ATTHOLDx_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
||
| 3667 | #define FSMC_PATTx_ATTHOLDx_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
||
| 3668 | #define FSMC_PATTx_ATTHOLDx_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
||
| 3669 | |||
| 3670 | #define FSMC_PATTx_ATTHIZx ((uint32_t)0xFF000000) /*!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */ |
||
| 3671 | #define FSMC_PATTx_ATTHIZx_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 3672 | #define FSMC_PATTx_ATTHIZx_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 3673 | #define FSMC_PATTx_ATTHIZx_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 3674 | #define FSMC_PATTx_ATTHIZx_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
||
| 3675 | #define FSMC_PATTx_ATTHIZx_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
||
| 3676 | #define FSMC_PATTx_ATTHIZx_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
||
| 3677 | #define FSMC_PATTx_ATTHIZx_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
||
| 3678 | #define FSMC_PATTx_ATTHIZx_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
||
| 3679 | |||
| 3680 | /****************** Bit definition for FSMC_PIO4 register *******************/ |
||
| 3681 | #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ |
||
| 3682 | #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3683 | #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3684 | #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3685 | #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3686 | #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 3687 | #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 3688 | #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 3689 | #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
||
| 3690 | |||
| 3691 | #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ |
||
| 3692 | #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 3693 | #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 3694 | #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 3695 | #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
||
| 3696 | #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
||
| 3697 | #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ |
||
| 3698 | #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ |
||
| 3699 | #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ |
||
| 3700 | |||
| 3701 | #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ |
||
| 3702 | #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 3703 | #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 3704 | #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
||
| 3705 | #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
||
| 3706 | #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
||
| 3707 | #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
||
| 3708 | #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
||
| 3709 | #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
||
| 3710 | |||
| 3711 | #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ |
||
| 3712 | #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 3713 | #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 3714 | #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 3715 | #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
||
| 3716 | #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
||
| 3717 | #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
||
| 3718 | #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
||
| 3719 | #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
||
| 3720 | |||
| 3721 | /****************** Bit definition for FSMC_ECCR2 register ******************/ |
||
| 3722 | #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ |
||
| 3723 | |||
| 3724 | /****************** Bit definition for FSMC_ECCR3 register ******************/ |
||
| 3725 | #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ |
||
| 3726 | |||
| 3727 | /******************************************************************************/ |
||
| 3728 | /* */ |
||
| 3729 | /* SD host Interface */ |
||
| 3730 | /* */ |
||
| 3731 | /******************************************************************************/ |
||
| 3732 | |||
| 3733 | /****************** Bit definition for SDIO_POWER register ******************/ |
||
| 3734 | #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ |
||
| 3735 | #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!< Bit 0 */ |
||
| 3736 | #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!< Bit 1 */ |
||
| 3737 | |||
| 3738 | /****************** Bit definition for SDIO_CLKCR register ******************/ |
||
| 3739 | #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!< Clock divide factor */ |
||
| 3740 | #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!< Clock enable bit */ |
||
| 3741 | #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!< Power saving configuration bit */ |
||
| 3742 | #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!< Clock divider bypass enable bit */ |
||
| 3743 | |||
| 3744 | #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
||
| 3745 | #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!< Bit 0 */ |
||
| 3746 | #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!< Bit 1 */ |
||
| 3747 | |||
| 3748 | #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!< SDIO_CK dephasing selection bit */ |
||
| 3749 | #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!< HW Flow Control enable */ |
||
| 3750 | |||
| 3751 | /******************* Bit definition for SDIO_ARG register *******************/ |
||
| 3752 | #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ |
||
| 3753 | |||
| 3754 | /******************* Bit definition for SDIO_CMD register *******************/ |
||
| 3755 | #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!< Command Index */ |
||
| 3756 | |||
| 3757 | #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ |
||
| 3758 | #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */ |
||
| 3759 | #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */ |
||
| 3760 | |||
| 3761 | #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!< CPSM Waits for Interrupt Request */ |
||
| 3762 | #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
||
| 3763 | #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ |
||
| 3764 | #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!< SD I/O suspend command */ |
||
| 3765 | #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!< Enable CMD completion */ |
||
| 3766 | #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!< Not Interrupt Enable */ |
||
| 3767 | #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!< CE-ATA command */ |
||
| 3768 | |||
| 3769 | /***************** Bit definition for SDIO_RESPCMD register *****************/ |
||
| 3770 | #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!< Response command index */ |
||
| 3771 | |||
| 3772 | /****************** Bit definition for SDIO_RESP0 register ******************/ |
||
| 3773 | #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 3774 | |||
| 3775 | /****************** Bit definition for SDIO_RESP1 register ******************/ |
||
| 3776 | #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 3777 | |||
| 3778 | /****************** Bit definition for SDIO_RESP2 register ******************/ |
||
| 3779 | #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 3780 | |||
| 3781 | /****************** Bit definition for SDIO_RESP3 register ******************/ |
||
| 3782 | #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 3783 | |||
| 3784 | /****************** Bit definition for SDIO_RESP4 register ******************/ |
||
| 3785 | #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 3786 | |||
| 3787 | /****************** Bit definition for SDIO_DTIMER register *****************/ |
||
| 3788 | #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ |
||
| 3789 | |||
| 3790 | /****************** Bit definition for SDIO_DLEN register *******************/ |
||
| 3791 | #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ |
||
| 3792 | |||
| 3793 | /****************** Bit definition for SDIO_DCTRL register ******************/ |
||
| 3794 | #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!< Data transfer enabled bit */ |
||
| 3795 | #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!< Data transfer direction selection */ |
||
| 3796 | #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!< Data transfer mode selection */ |
||
| 3797 | #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!< DMA enabled bit */ |
||
| 3798 | |||
| 3799 | #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ |
||
| 3800 | #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!< Bit 0 */ |
||
| 3801 | #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!< Bit 1 */ |
||
| 3802 | #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!< Bit 2 */ |
||
| 3803 | #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!< Bit 3 */ |
||
| 3804 | |||
| 3805 | #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!< Read wait start */ |
||
| 3806 | #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!< Read wait stop */ |
||
| 3807 | #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!< Read wait mode */ |
||
| 3808 | #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!< SD I/O enable functions */ |
||
| 3809 | |||
| 3810 | /****************** Bit definition for SDIO_DCOUNT register *****************/ |
||
| 3811 | #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ |
||
| 3812 | |||
| 3813 | /****************** Bit definition for SDIO_STA register ********************/ |
||
| 3814 | #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ |
||
| 3815 | #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ |
||
| 3816 | #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ |
||
| 3817 | #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ |
||
| 3818 | #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ |
||
| 3819 | #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ |
||
| 3820 | #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ |
||
| 3821 | #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ |
||
| 3822 | #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ |
||
| 3823 | #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ |
||
| 3824 | #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ |
||
| 3825 | #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ |
||
| 3826 | #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ |
||
| 3827 | #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ |
||
| 3828 | #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
||
| 3829 | #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
||
| 3830 | #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ |
||
| 3831 | #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ |
||
| 3832 | #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ |
||
| 3833 | #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ |
||
| 3834 | #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ |
||
| 3835 | #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ |
||
| 3836 | #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ |
||
| 3837 | #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ |
||
| 3838 | |||
| 3839 | /******************* Bit definition for SDIO_ICR register *******************/ |
||
| 3840 | #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ |
||
| 3841 | #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ |
||
| 3842 | #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ |
||
| 3843 | #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ |
||
| 3844 | #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ |
||
| 3845 | #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ |
||
| 3846 | #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ |
||
| 3847 | #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ |
||
| 3848 | #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ |
||
| 3849 | #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ |
||
| 3850 | #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ |
||
| 3851 | #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ |
||
| 3852 | #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ |
||
| 3853 | |||
| 3854 | /****************** Bit definition for SDIO_MASK register *******************/ |
||
| 3855 | #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ |
||
| 3856 | #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ |
||
| 3857 | #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ |
||
| 3858 | #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ |
||
| 3859 | #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ |
||
| 3860 | #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ |
||
| 3861 | #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ |
||
| 3862 | #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ |
||
| 3863 | #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ |
||
| 3864 | #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ |
||
| 3865 | #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ |
||
| 3866 | #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ |
||
| 3867 | #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ |
||
| 3868 | #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ |
||
| 3869 | #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ |
||
| 3870 | #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ |
||
| 3871 | #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ |
||
| 3872 | #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ |
||
| 3873 | #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ |
||
| 3874 | #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ |
||
| 3875 | #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ |
||
| 3876 | #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ |
||
| 3877 | #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ |
||
| 3878 | #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ |
||
| 3879 | |||
| 3880 | /***************** Bit definition for SDIO_FIFOCNT register *****************/ |
||
| 3881 | #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ |
||
| 3882 | |||
| 3883 | /****************** Bit definition for SDIO_FIFO register *******************/ |
||
| 3884 | #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ |
||
| 3885 | |||
| 3886 | /******************************************************************************/ |
||
| 3887 | /* */ |
||
| 3888 | /* USB Device FS */ |
||
| 3889 | /* */ |
||
| 3890 | /******************************************************************************/ |
||
| 3891 | |||
| 3892 | /*!< Endpoint-specific registers */ |
||
| 3893 | #define USB_EP0R USB_BASE /*!< Endpoint 0 register address */ |
||
| 3894 | #define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */ |
||
| 3895 | #define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */ |
||
| 3896 | #define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */ |
||
| 3897 | #define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */ |
||
| 3898 | #define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */ |
||
| 3899 | #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ |
||
| 3900 | #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ |
||
| 3901 | |||
| 3902 | /* bit positions */ |
||
| 3903 | #define USB_EP_CTR_RX ((uint32_t)0x00008000) /*!< EndPoint Correct TRansfer RX */ |
||
| 3904 | #define USB_EP_DTOG_RX ((uint32_t)0x00004000) /*!< EndPoint Data TOGGLE RX */ |
||
| 3905 | #define USB_EPRX_STAT ((uint32_t)0x00003000) /*!< EndPoint RX STATus bit field */ |
||
| 3906 | #define USB_EP_SETUP ((uint32_t)0x00000800) /*!< EndPoint SETUP */ |
||
| 3907 | #define USB_EP_T_FIELD ((uint32_t)0x00000600) /*!< EndPoint TYPE */ |
||
| 3908 | #define USB_EP_KIND ((uint32_t)0x00000100) /*!< EndPoint KIND */ |
||
| 3909 | #define USB_EP_CTR_TX ((uint32_t)0x00000080) /*!< EndPoint Correct TRansfer TX */ |
||
| 3910 | #define USB_EP_DTOG_TX ((uint32_t)0x00000040) /*!< EndPoint Data TOGGLE TX */ |
||
| 3911 | #define USB_EPTX_STAT ((uint32_t)0x00000030) /*!< EndPoint TX STATus bit field */ |
||
| 3912 | #define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /*!< EndPoint ADDRess FIELD */ |
||
| 3913 | |||
| 3914 | /* EndPoint REGister MASK (no toggle fields) */ |
||
| 3915 | #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
||
| 3916 | /*!< EP_TYPE[1:0] EndPoint TYPE */ |
||
| 3917 | #define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /*!< EndPoint TYPE Mask */ |
||
| 3918 | #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */ |
||
| 3919 | #define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */ |
||
| 3920 | #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */ |
||
| 3921 | #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */ |
||
| 3922 | #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) |
||
| 3923 | |||
| 3924 | #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ |
||
| 3925 | /*!< STAT_TX[1:0] STATus for TX transfer */ |
||
| 3926 | #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */ |
||
| 3927 | #define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */ |
||
| 3928 | #define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */ |
||
| 3929 | #define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */ |
||
| 3930 | #define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */ |
||
| 3931 | #define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */ |
||
| 3932 | #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
||
| 3933 | /*!< STAT_RX[1:0] STATus for RX transfer */ |
||
| 3934 | #define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */ |
||
| 3935 | #define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */ |
||
| 3936 | #define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */ |
||
| 3937 | #define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */ |
||
| 3938 | #define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */ |
||
| 3939 | #define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */ |
||
| 3940 | #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
||
| 3941 | |||
| 3942 | /******************* Bit definition for USB_EP0R register *******************/ |
||
| 3943 | #define USB_EP0R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */ |
||
| 3944 | |||
| 3945 | #define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 3946 | #define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 3947 | #define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 3948 | |||
| 3949 | #define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */ |
||
| 3950 | #define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */ |
||
| 3951 | #define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */ |
||
| 3952 | |||
| 3953 | #define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 3954 | #define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 3955 | #define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 3956 | |||
| 3957 | #define USB_EP0R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */ |
||
| 3958 | |||
| 3959 | #define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 3960 | #define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 3961 | #define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 3962 | |||
| 3963 | #define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */ |
||
| 3964 | #define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */ |
||
| 3965 | |||
| 3966 | /******************* Bit definition for USB_EP1R register *******************/ |
||
| 3967 | #define USB_EP1R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */ |
||
| 3968 | |||
| 3969 | #define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 3970 | #define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 3971 | #define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 3972 | |||
| 3973 | #define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */ |
||
| 3974 | #define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */ |
||
| 3975 | #define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */ |
||
| 3976 | |||
| 3977 | #define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 3978 | #define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 3979 | #define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 3980 | |||
| 3981 | #define USB_EP1R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */ |
||
| 3982 | |||
| 3983 | #define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 3984 | #define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 3985 | #define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 3986 | |||
| 3987 | #define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */ |
||
| 3988 | #define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */ |
||
| 3989 | |||
| 3990 | /******************* Bit definition for USB_EP2R register *******************/ |
||
| 3991 | #define USB_EP2R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */ |
||
| 3992 | |||
| 3993 | #define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 3994 | #define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 3995 | #define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 3996 | |||
| 3997 | #define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */ |
||
| 3998 | #define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */ |
||
| 3999 | #define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */ |
||
| 4000 | |||
| 4001 | #define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 4002 | #define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 4003 | #define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 4004 | |||
| 4005 | #define USB_EP2R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */ |
||
| 4006 | |||
| 4007 | #define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 4008 | #define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 4009 | #define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 4010 | |||
| 4011 | #define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */ |
||
| 4012 | #define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */ |
||
| 4013 | |||
| 4014 | /******************* Bit definition for USB_EP3R register *******************/ |
||
| 4015 | #define USB_EP3R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */ |
||
| 4016 | |||
| 4017 | #define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 4018 | #define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 4019 | #define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 4020 | |||
| 4021 | #define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */ |
||
| 4022 | #define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */ |
||
| 4023 | #define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */ |
||
| 4024 | |||
| 4025 | #define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 4026 | #define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 4027 | #define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 4028 | |||
| 4029 | #define USB_EP3R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */ |
||
| 4030 | |||
| 4031 | #define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 4032 | #define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 4033 | #define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 4034 | |||
| 4035 | #define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */ |
||
| 4036 | #define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */ |
||
| 4037 | |||
| 4038 | /******************* Bit definition for USB_EP4R register *******************/ |
||
| 4039 | #define USB_EP4R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */ |
||
| 4040 | |||
| 4041 | #define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 4042 | #define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 4043 | #define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 4044 | |||
| 4045 | #define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */ |
||
| 4046 | #define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */ |
||
| 4047 | #define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */ |
||
| 4048 | |||
| 4049 | #define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 4050 | #define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 4051 | #define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 4052 | |||
| 4053 | #define USB_EP4R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */ |
||
| 4054 | |||
| 4055 | #define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 4056 | #define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 4057 | #define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 4058 | |||
| 4059 | #define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */ |
||
| 4060 | #define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */ |
||
| 4061 | |||
| 4062 | /******************* Bit definition for USB_EP5R register *******************/ |
||
| 4063 | #define USB_EP5R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */ |
||
| 4064 | |||
| 4065 | #define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 4066 | #define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 4067 | #define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 4068 | |||
| 4069 | #define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */ |
||
| 4070 | #define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */ |
||
| 4071 | #define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */ |
||
| 4072 | |||
| 4073 | #define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 4074 | #define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 4075 | #define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 4076 | |||
| 4077 | #define USB_EP5R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */ |
||
| 4078 | |||
| 4079 | #define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 4080 | #define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 4081 | #define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 4082 | |||
| 4083 | #define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */ |
||
| 4084 | #define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */ |
||
| 4085 | |||
| 4086 | /******************* Bit definition for USB_EP6R register *******************/ |
||
| 4087 | #define USB_EP6R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */ |
||
| 4088 | |||
| 4089 | #define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 4090 | #define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 4091 | #define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 4092 | |||
| 4093 | #define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */ |
||
| 4094 | #define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */ |
||
| 4095 | #define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */ |
||
| 4096 | |||
| 4097 | #define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 4098 | #define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 4099 | #define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 4100 | |||
| 4101 | #define USB_EP6R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */ |
||
| 4102 | |||
| 4103 | #define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 4104 | #define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 4105 | #define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 4106 | |||
| 4107 | #define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */ |
||
| 4108 | #define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */ |
||
| 4109 | |||
| 4110 | /******************* Bit definition for USB_EP7R register *******************/ |
||
| 4111 | #define USB_EP7R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */ |
||
| 4112 | |||
| 4113 | #define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 4114 | #define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 4115 | #define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 4116 | |||
| 4117 | #define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */ |
||
| 4118 | #define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */ |
||
| 4119 | #define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */ |
||
| 4120 | |||
| 4121 | #define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 4122 | #define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 4123 | #define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 4124 | |||
| 4125 | #define USB_EP7R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */ |
||
| 4126 | |||
| 4127 | #define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 4128 | #define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 4129 | #define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 4130 | |||
| 4131 | #define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */ |
||
| 4132 | #define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */ |
||
| 4133 | |||
| 4134 | /*!< Common registers */ |
||
| 4135 | /******************* Bit definition for USB_CNTR register *******************/ |
||
| 4136 | #define USB_CNTR_FRES ((uint32_t)0x00000001) /*!< Force USB Reset */ |
||
| 4137 | #define USB_CNTR_PDWN ((uint32_t)0x00000002) /*!< Power down */ |
||
| 4138 | #define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /*!< Low-power mode */ |
||
| 4139 | #define USB_CNTR_FSUSP ((uint32_t)0x00000008) /*!< Force suspend */ |
||
| 4140 | #define USB_CNTR_RESUME ((uint32_t)0x00000010) /*!< Resume request */ |
||
| 4141 | #define USB_CNTR_ESOFM ((uint32_t)0x00000100) /*!< Expected Start Of Frame Interrupt Mask */ |
||
| 4142 | #define USB_CNTR_SOFM ((uint32_t)0x00000200) /*!< Start Of Frame Interrupt Mask */ |
||
| 4143 | #define USB_CNTR_RESETM ((uint32_t)0x00000400) /*!< RESET Interrupt Mask */ |
||
| 4144 | #define USB_CNTR_SUSPM ((uint32_t)0x00000800) /*!< Suspend mode Interrupt Mask */ |
||
| 4145 | #define USB_CNTR_WKUPM ((uint32_t)0x00001000) /*!< Wakeup Interrupt Mask */ |
||
| 4146 | #define USB_CNTR_ERRM ((uint32_t)0x00002000) /*!< Error Interrupt Mask */ |
||
| 4147 | #define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ |
||
| 4148 | #define USB_CNTR_CTRM ((uint32_t)0x00008000) /*!< Correct Transfer Interrupt Mask */ |
||
| 4149 | |||
| 4150 | /******************* Bit definition for USB_ISTR register *******************/ |
||
| 4151 | #define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /*!< Endpoint Identifier */ |
||
| 4152 | #define USB_ISTR_DIR ((uint32_t)0x00000010) /*!< Direction of transaction */ |
||
| 4153 | #define USB_ISTR_ESOF ((uint32_t)0x00000100) /*!< Expected Start Of Frame */ |
||
| 4154 | #define USB_ISTR_SOF ((uint32_t)0x00000200) /*!< Start Of Frame */ |
||
| 4155 | #define USB_ISTR_RESET ((uint32_t)0x00000400) /*!< USB RESET request */ |
||
| 4156 | #define USB_ISTR_SUSP ((uint32_t)0x00000800) /*!< Suspend mode request */ |
||
| 4157 | #define USB_ISTR_WKUP ((uint32_t)0x00001000) /*!< Wake up */ |
||
| 4158 | #define USB_ISTR_ERR ((uint32_t)0x00002000) /*!< Error */ |
||
| 4159 | #define USB_ISTR_PMAOVR ((uint32_t)0x00004000) /*!< Packet Memory Area Over / Underrun */ |
||
| 4160 | #define USB_ISTR_CTR ((uint32_t)0x00008000) /*!< Correct Transfer */ |
||
| 4161 | |||
| 4162 | /******************* Bit definition for USB_FNR register ********************/ |
||
| 4163 | #define USB_FNR_FN ((uint32_t)0x000007FF) /*!< Frame Number */ |
||
| 4164 | #define USB_FNR_LSOF ((uint32_t)0x00001800) /*!< Lost SOF */ |
||
| 4165 | #define USB_FNR_LCK ((uint32_t)0x00002000) /*!< Locked */ |
||
| 4166 | #define USB_FNR_RXDM ((uint32_t)0x00004000) /*!< Receive Data - Line Status */ |
||
| 4167 | #define USB_FNR_RXDP ((uint32_t)0x00008000) /*!< Receive Data + Line Status */ |
||
| 4168 | |||
| 4169 | /****************** Bit definition for USB_DADDR register *******************/ |
||
| 4170 | #define USB_DADDR_ADD ((uint32_t)0x0000007F) /*!< ADD[6:0] bits (Device Address) */ |
||
| 4171 | #define USB_DADDR_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 4172 | #define USB_DADDR_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 4173 | #define USB_DADDR_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 4174 | #define USB_DADDR_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 4175 | #define USB_DADDR_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 4176 | #define USB_DADDR_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 4177 | #define USB_DADDR_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 4178 | |||
| 4179 | #define USB_DADDR_EF ((uint32_t)0x00000080) /*!< Enable Function */ |
||
| 4180 | |||
| 4181 | /****************** Bit definition for USB_BTABLE register ******************/ |
||
| 4182 | #define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /*!< Buffer Table */ |
||
| 4183 | |||
| 4184 | /*!< Buffer descriptor table */ |
||
| 4185 | /***************** Bit definition for USB_ADDR0_TX register *****************/ |
||
| 4186 | #define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 0 */ |
||
| 4187 | |||
| 4188 | /***************** Bit definition for USB_ADDR1_TX register *****************/ |
||
| 4189 | #define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 1 */ |
||
| 4190 | |||
| 4191 | /***************** Bit definition for USB_ADDR2_TX register *****************/ |
||
| 4192 | #define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 2 */ |
||
| 4193 | |||
| 4194 | /***************** Bit definition for USB_ADDR3_TX register *****************/ |
||
| 4195 | #define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 3 */ |
||
| 4196 | |||
| 4197 | /***************** Bit definition for USB_ADDR4_TX register *****************/ |
||
| 4198 | #define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 4 */ |
||
| 4199 | |||
| 4200 | /***************** Bit definition for USB_ADDR5_TX register *****************/ |
||
| 4201 | #define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 5 */ |
||
| 4202 | |||
| 4203 | /***************** Bit definition for USB_ADDR6_TX register *****************/ |
||
| 4204 | #define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 6 */ |
||
| 4205 | |||
| 4206 | /***************** Bit definition for USB_ADDR7_TX register *****************/ |
||
| 4207 | #define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 7 */ |
||
| 4208 | |||
| 4209 | /*----------------------------------------------------------------------------*/ |
||
| 4210 | |||
| 4211 | /***************** Bit definition for USB_COUNT0_TX register ****************/ |
||
| 4212 | #define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 */ |
||
| 4213 | |||
| 4214 | /***************** Bit definition for USB_COUNT1_TX register ****************/ |
||
| 4215 | #define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 */ |
||
| 4216 | |||
| 4217 | /***************** Bit definition for USB_COUNT2_TX register ****************/ |
||
| 4218 | #define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 */ |
||
| 4219 | |||
| 4220 | /***************** Bit definition for USB_COUNT3_TX register ****************/ |
||
| 4221 | #define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 */ |
||
| 4222 | |||
| 4223 | /***************** Bit definition for USB_COUNT4_TX register ****************/ |
||
| 4224 | #define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 */ |
||
| 4225 | |||
| 4226 | /***************** Bit definition for USB_COUNT5_TX register ****************/ |
||
| 4227 | #define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 */ |
||
| 4228 | |||
| 4229 | /***************** Bit definition for USB_COUNT6_TX register ****************/ |
||
| 4230 | #define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 */ |
||
| 4231 | |||
| 4232 | /***************** Bit definition for USB_COUNT7_TX register ****************/ |
||
| 4233 | #define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 */ |
||
| 4234 | |||
| 4235 | /*----------------------------------------------------------------------------*/ |
||
| 4236 | |||
| 4237 | /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ |
||
| 4238 | #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ |
||
| 4239 | |||
| 4240 | /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ |
||
| 4241 | #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ |
||
| 4242 | |||
| 4243 | /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ |
||
| 4244 | #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ |
||
| 4245 | |||
| 4246 | /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ |
||
| 4247 | #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ |
||
| 4248 | |||
| 4249 | /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ |
||
| 4250 | #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ |
||
| 4251 | |||
| 4252 | /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ |
||
| 4253 | #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ |
||
| 4254 | |||
| 4255 | /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ |
||
| 4256 | #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ |
||
| 4257 | |||
| 4258 | /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ |
||
| 4259 | #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ |
||
| 4260 | |||
| 4261 | /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ |
||
| 4262 | #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ |
||
| 4263 | |||
| 4264 | /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ |
||
| 4265 | #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ |
||
| 4266 | |||
| 4267 | /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ |
||
| 4268 | #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ |
||
| 4269 | |||
| 4270 | /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ |
||
| 4271 | #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ |
||
| 4272 | |||
| 4273 | /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ |
||
| 4274 | #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ |
||
| 4275 | |||
| 4276 | /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ |
||
| 4277 | #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ |
||
| 4278 | |||
| 4279 | /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ |
||
| 4280 | #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ |
||
| 4281 | |||
| 4282 | /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ |
||
| 4283 | #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ |
||
| 4284 | |||
| 4285 | /*----------------------------------------------------------------------------*/ |
||
| 4286 | |||
| 4287 | /***************** Bit definition for USB_ADDR0_RX register *****************/ |
||
| 4288 | #define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 0 */ |
||
| 4289 | |||
| 4290 | /***************** Bit definition for USB_ADDR1_RX register *****************/ |
||
| 4291 | #define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 1 */ |
||
| 4292 | |||
| 4293 | /***************** Bit definition for USB_ADDR2_RX register *****************/ |
||
| 4294 | #define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 2 */ |
||
| 4295 | |||
| 4296 | /***************** Bit definition for USB_ADDR3_RX register *****************/ |
||
| 4297 | #define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 3 */ |
||
| 4298 | |||
| 4299 | /***************** Bit definition for USB_ADDR4_RX register *****************/ |
||
| 4300 | #define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 4 */ |
||
| 4301 | |||
| 4302 | /***************** Bit definition for USB_ADDR5_RX register *****************/ |
||
| 4303 | #define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 5 */ |
||
| 4304 | |||
| 4305 | /***************** Bit definition for USB_ADDR6_RX register *****************/ |
||
| 4306 | #define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 6 */ |
||
| 4307 | |||
| 4308 | /***************** Bit definition for USB_ADDR7_RX register *****************/ |
||
| 4309 | #define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 7 */ |
||
| 4310 | |||
| 4311 | /*----------------------------------------------------------------------------*/ |
||
| 4312 | |||
| 4313 | /***************** Bit definition for USB_COUNT0_RX register ****************/ |
||
| 4314 | #define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */ |
||
| 4315 | |||
| 4316 | #define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 4317 | #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4318 | #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4319 | #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4320 | #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4321 | #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4322 | |||
| 4323 | #define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */ |
||
| 4324 | |||
| 4325 | /***************** Bit definition for USB_COUNT1_RX register ****************/ |
||
| 4326 | #define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */ |
||
| 4327 | |||
| 4328 | #define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 4329 | #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4330 | #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4331 | #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4332 | #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4333 | #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4334 | |||
| 4335 | #define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */ |
||
| 4336 | |||
| 4337 | /***************** Bit definition for USB_COUNT2_RX register ****************/ |
||
| 4338 | #define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */ |
||
| 4339 | |||
| 4340 | #define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 4341 | #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4342 | #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4343 | #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4344 | #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4345 | #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4346 | |||
| 4347 | #define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */ |
||
| 4348 | |||
| 4349 | /***************** Bit definition for USB_COUNT3_RX register ****************/ |
||
| 4350 | #define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */ |
||
| 4351 | |||
| 4352 | #define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 4353 | #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4354 | #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4355 | #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4356 | #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4357 | #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4358 | |||
| 4359 | #define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */ |
||
| 4360 | |||
| 4361 | /***************** Bit definition for USB_COUNT4_RX register ****************/ |
||
| 4362 | #define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */ |
||
| 4363 | |||
| 4364 | #define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 4365 | #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4366 | #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4367 | #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4368 | #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4369 | #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4370 | |||
| 4371 | #define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */ |
||
| 4372 | |||
| 4373 | /***************** Bit definition for USB_COUNT5_RX register ****************/ |
||
| 4374 | #define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */ |
||
| 4375 | |||
| 4376 | #define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 4377 | #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4378 | #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4379 | #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4380 | #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4381 | #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4382 | |||
| 4383 | #define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */ |
||
| 4384 | |||
| 4385 | /***************** Bit definition for USB_COUNT6_RX register ****************/ |
||
| 4386 | #define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */ |
||
| 4387 | |||
| 4388 | #define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 4389 | #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4390 | #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4391 | #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4392 | #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4393 | #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4394 | |||
| 4395 | #define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */ |
||
| 4396 | |||
| 4397 | /***************** Bit definition for USB_COUNT7_RX register ****************/ |
||
| 4398 | #define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */ |
||
| 4399 | |||
| 4400 | #define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 4401 | #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4402 | #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4403 | #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4404 | #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4405 | #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4406 | |||
| 4407 | #define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */ |
||
| 4408 | |||
| 4409 | /*----------------------------------------------------------------------------*/ |
||
| 4410 | |||
| 4411 | /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ |
||
| 4412 | #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
||
| 4413 | |||
| 4414 | #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 4415 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4416 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4417 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4418 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4419 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4420 | |||
| 4421 | #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
||
| 4422 | |||
| 4423 | /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ |
||
| 4424 | #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
||
| 4425 | |||
| 4426 | #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 4427 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ |
||
| 4428 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 4429 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
||
| 4430 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
||
| 4431 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
||
| 4432 | |||
| 4433 | #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
||
| 4434 | |||
| 4435 | /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ |
||
| 4436 | #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
||
| 4437 | |||
| 4438 | #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 4439 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4440 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4441 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4442 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4443 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4444 | |||
| 4445 | #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
||
| 4446 | |||
| 4447 | /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ |
||
| 4448 | #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
||
| 4449 | |||
| 4450 | #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 4451 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 4452 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 4453 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
||
| 4454 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
||
| 4455 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
||
| 4456 | |||
| 4457 | #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
||
| 4458 | |||
| 4459 | /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ |
||
| 4460 | #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
||
| 4461 | |||
| 4462 | #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 4463 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4464 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4465 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4466 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4467 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4468 | |||
| 4469 | #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
||
| 4470 | |||
| 4471 | /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ |
||
| 4472 | #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
||
| 4473 | |||
| 4474 | #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 4475 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 4476 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 4477 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
||
| 4478 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
||
| 4479 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
||
| 4480 | |||
| 4481 | #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
||
| 4482 | |||
| 4483 | /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ |
||
| 4484 | #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
||
| 4485 | |||
| 4486 | #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 4487 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4488 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4489 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4490 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4491 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4492 | |||
| 4493 | #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
||
| 4494 | |||
| 4495 | /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ |
||
| 4496 | #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
||
| 4497 | |||
| 4498 | #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 4499 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 4500 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 4501 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
||
| 4502 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
||
| 4503 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
||
| 4504 | |||
| 4505 | #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
||
| 4506 | |||
| 4507 | /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ |
||
| 4508 | #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
||
| 4509 | |||
| 4510 | #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 4511 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4512 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4513 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4514 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4515 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4516 | |||
| 4517 | #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
||
| 4518 | |||
| 4519 | /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ |
||
| 4520 | #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
||
| 4521 | |||
| 4522 | #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 4523 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 4524 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 4525 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
||
| 4526 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
||
| 4527 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
||
| 4528 | |||
| 4529 | #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
||
| 4530 | |||
| 4531 | /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ |
||
| 4532 | #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
||
| 4533 | |||
| 4534 | #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 4535 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4536 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4537 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4538 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4539 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4540 | |||
| 4541 | #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
||
| 4542 | |||
| 4543 | /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ |
||
| 4544 | #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
||
| 4545 | |||
| 4546 | #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 4547 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 4548 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 4549 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
||
| 4550 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
||
| 4551 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
||
| 4552 | |||
| 4553 | #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
||
| 4554 | |||
| 4555 | /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ |
||
| 4556 | #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
||
| 4557 | |||
| 4558 | #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 4559 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4560 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4561 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4562 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4563 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4564 | |||
| 4565 | #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
||
| 4566 | |||
| 4567 | /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ |
||
| 4568 | #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
||
| 4569 | |||
| 4570 | #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 4571 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 4572 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 4573 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
||
| 4574 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
||
| 4575 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
||
| 4576 | |||
| 4577 | #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
||
| 4578 | |||
| 4579 | /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ |
||
| 4580 | #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ |
||
| 4581 | |||
| 4582 | #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 4583 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 4584 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 4585 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 4586 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 4587 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 4588 | |||
| 4589 | #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ |
||
| 4590 | |||
| 4591 | /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ |
||
| 4592 | #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ |
||
| 4593 | |||
| 4594 | #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 4595 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 4596 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 4597 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ |
||
| 4598 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ |
||
| 4599 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ |
||
| 4600 | |||
| 4601 | #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ |
||
| 4602 | |||
| 4603 | /******************************************************************************/ |
||
| 4604 | /* */ |
||
| 4605 | /* Controller Area Network */ |
||
| 4606 | /* */ |
||
| 4607 | /******************************************************************************/ |
||
| 4608 | |||
| 4609 | /*!< CAN control and status registers */ |
||
| 4610 | /******************* Bit definition for CAN_MCR register ********************/ |
||
| 4611 | #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!< Initialization Request */ |
||
| 4612 | #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!< Sleep Mode Request */ |
||
| 4613 | #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!< Transmit FIFO Priority */ |
||
| 4614 | #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!< Receive FIFO Locked Mode */ |
||
| 4615 | #define CAN_MCR_NART ((uint32_t)0x00000010) /*!< No Automatic Retransmission */ |
||
| 4616 | #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!< Automatic Wakeup Mode */ |
||
| 4617 | #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!< Automatic Bus-Off Management */ |
||
| 4618 | #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!< Time Triggered Communication Mode */ |
||
| 4619 | #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!< CAN software master reset */ |
||
| 4620 | #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!< CAN Debug freeze */ |
||
| 4621 | |||
| 4622 | /******************* Bit definition for CAN_MSR register ********************/ |
||
| 4623 | #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!< Initialization Acknowledge */ |
||
| 4624 | #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!< Sleep Acknowledge */ |
||
| 4625 | #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!< Error Interrupt */ |
||
| 4626 | #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!< Wakeup Interrupt */ |
||
| 4627 | #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!< Sleep Acknowledge Interrupt */ |
||
| 4628 | #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!< Transmit Mode */ |
||
| 4629 | #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!< Receive Mode */ |
||
| 4630 | #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!< Last Sample Point */ |
||
| 4631 | #define CAN_MSR_RX ((uint32_t)0x00000800) /*!< CAN Rx Signal */ |
||
| 4632 | |||
| 4633 | /******************* Bit definition for CAN_TSR register ********************/ |
||
| 4634 | #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ |
||
| 4635 | #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ |
||
| 4636 | #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ |
||
| 4637 | #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ |
||
| 4638 | #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ |
||
| 4639 | #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ |
||
| 4640 | #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ |
||
| 4641 | #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ |
||
| 4642 | #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ |
||
| 4643 | #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ |
||
| 4644 | #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ |
||
| 4645 | #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ |
||
| 4646 | #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ |
||
| 4647 | #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ |
||
| 4648 | #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ |
||
| 4649 | #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ |
||
| 4650 | |||
| 4651 | #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ |
||
| 4652 | #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ |
||
| 4653 | #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ |
||
| 4654 | #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ |
||
| 4655 | |||
| 4656 | #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ |
||
| 4657 | #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ |
||
| 4658 | #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ |
||
| 4659 | #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ |
||
| 4660 | |||
| 4661 | /******************* Bit definition for CAN_RF0R register *******************/ |
||
| 4662 | #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!< FIFO 0 Message Pending */ |
||
| 4663 | #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!< FIFO 0 Full */ |
||
| 4664 | #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!< FIFO 0 Overrun */ |
||
| 4665 | #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!< Release FIFO 0 Output Mailbox */ |
||
| 4666 | |||
| 4667 | /******************* Bit definition for CAN_RF1R register *******************/ |
||
| 4668 | #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!< FIFO 1 Message Pending */ |
||
| 4669 | #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!< FIFO 1 Full */ |
||
| 4670 | #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!< FIFO 1 Overrun */ |
||
| 4671 | #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!< Release FIFO 1 Output Mailbox */ |
||
| 4672 | |||
| 4673 | /******************** Bit definition for CAN_IER register *******************/ |
||
| 4674 | #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ |
||
| 4675 | #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ |
||
| 4676 | #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ |
||
| 4677 | #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ |
||
| 4678 | #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ |
||
| 4679 | #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ |
||
| 4680 | #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ |
||
| 4681 | #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ |
||
| 4682 | #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ |
||
| 4683 | #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ |
||
| 4684 | #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ |
||
| 4685 | #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ |
||
| 4686 | #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ |
||
| 4687 | #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ |
||
| 4688 | |||
| 4689 | /******************** Bit definition for CAN_ESR register *******************/ |
||
| 4690 | #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ |
||
| 4691 | #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ |
||
| 4692 | #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ |
||
| 4693 | |||
| 4694 | #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ |
||
| 4695 | #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 4696 | #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 4697 | #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
||
| 4698 | |||
| 4699 | #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ |
||
| 4700 | #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ |
||
| 4701 | |||
| 4702 | /******************* Bit definition for CAN_BTR register ********************/ |
||
| 4703 | #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ |
||
| 4704 | #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ |
||
| 4705 | #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */ |
||
| 4706 | #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */ |
||
| 4707 | #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */ |
||
| 4708 | #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */ |
||
| 4709 | #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ |
||
| 4710 | #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */ |
||
| 4711 | #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */ |
||
| 4712 | #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */ |
||
| 4713 | #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ |
||
| 4714 | #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */ |
||
| 4715 | #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */ |
||
| 4716 | #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ |
||
| 4717 | #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ |
||
| 4718 | |||
| 4719 | /*!< Mailbox registers */ |
||
| 4720 | /****************** Bit definition for CAN_TI0R register ********************/ |
||
| 4721 | #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ |
||
| 4722 | #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
||
| 4723 | #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
||
| 4724 | #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ |
||
| 4725 | #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
||
| 4726 | |||
| 4727 | /****************** Bit definition for CAN_TDT0R register *******************/ |
||
| 4728 | #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
||
| 4729 | #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ |
||
| 4730 | #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
||
| 4731 | |||
| 4732 | /****************** Bit definition for CAN_TDL0R register *******************/ |
||
| 4733 | #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
||
| 4734 | #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
||
| 4735 | #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
||
| 4736 | #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
||
| 4737 | |||
| 4738 | /****************** Bit definition for CAN_TDH0R register *******************/ |
||
| 4739 | #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
||
| 4740 | #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
||
| 4741 | #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
||
| 4742 | #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
||
| 4743 | |||
| 4744 | /******************* Bit definition for CAN_TI1R register *******************/ |
||
| 4745 | #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ |
||
| 4746 | #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
||
| 4747 | #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
||
| 4748 | #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ |
||
| 4749 | #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
||
| 4750 | |||
| 4751 | /******************* Bit definition for CAN_TDT1R register ******************/ |
||
| 4752 | #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
||
| 4753 | #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ |
||
| 4754 | #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
||
| 4755 | |||
| 4756 | /******************* Bit definition for CAN_TDL1R register ******************/ |
||
| 4757 | #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
||
| 4758 | #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
||
| 4759 | #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
||
| 4760 | #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
||
| 4761 | |||
| 4762 | /******************* Bit definition for CAN_TDH1R register ******************/ |
||
| 4763 | #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
||
| 4764 | #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
||
| 4765 | #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
||
| 4766 | #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
||
| 4767 | |||
| 4768 | /******************* Bit definition for CAN_TI2R register *******************/ |
||
| 4769 | #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ |
||
| 4770 | #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
||
| 4771 | #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
||
| 4772 | #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ |
||
| 4773 | #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
||
| 4774 | |||
| 4775 | /******************* Bit definition for CAN_TDT2R register ******************/ |
||
| 4776 | #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
||
| 4777 | #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ |
||
| 4778 | #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
||
| 4779 | |||
| 4780 | /******************* Bit definition for CAN_TDL2R register ******************/ |
||
| 4781 | #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
||
| 4782 | #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
||
| 4783 | #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
||
| 4784 | #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
||
| 4785 | |||
| 4786 | /******************* Bit definition for CAN_TDH2R register ******************/ |
||
| 4787 | #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
||
| 4788 | #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
||
| 4789 | #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
||
| 4790 | #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
||
| 4791 | |||
| 4792 | /******************* Bit definition for CAN_RI0R register *******************/ |
||
| 4793 | #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
||
| 4794 | #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
||
| 4795 | #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ |
||
| 4796 | #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
||
| 4797 | |||
| 4798 | /******************* Bit definition for CAN_RDT0R register ******************/ |
||
| 4799 | #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
||
| 4800 | #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ |
||
| 4801 | #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
||
| 4802 | |||
| 4803 | /******************* Bit definition for CAN_RDL0R register ******************/ |
||
| 4804 | #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
||
| 4805 | #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
||
| 4806 | #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
||
| 4807 | #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
||
| 4808 | |||
| 4809 | /******************* Bit definition for CAN_RDH0R register ******************/ |
||
| 4810 | #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
||
| 4811 | #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
||
| 4812 | #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
||
| 4813 | #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
||
| 4814 | |||
| 4815 | /******************* Bit definition for CAN_RI1R register *******************/ |
||
| 4816 | #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ |
||
| 4817 | #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ |
||
| 4818 | #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ |
||
| 4819 | #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ |
||
| 4820 | |||
| 4821 | /******************* Bit definition for CAN_RDT1R register ******************/ |
||
| 4822 | #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ |
||
| 4823 | #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ |
||
| 4824 | #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ |
||
| 4825 | |||
| 4826 | /******************* Bit definition for CAN_RDL1R register ******************/ |
||
| 4827 | #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ |
||
| 4828 | #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ |
||
| 4829 | #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ |
||
| 4830 | #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ |
||
| 4831 | |||
| 4832 | /******************* Bit definition for CAN_RDH1R register ******************/ |
||
| 4833 | #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ |
||
| 4834 | #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ |
||
| 4835 | #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ |
||
| 4836 | #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ |
||
| 4837 | |||
| 4838 | /*!< CAN filter registers */ |
||
| 4839 | /******************* Bit definition for CAN_FMR register ********************/ |
||
| 4840 | #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!< Filter Init Mode */ |
||
| 4841 | #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!< CAN2 start bank */ |
||
| 4842 | |||
| 4843 | /******************* Bit definition for CAN_FM1R register *******************/ |
||
| 4844 | #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!< Filter Mode */ |
||
| 4845 | #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!< Filter Init Mode for filter 0 */ |
||
| 4846 | #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!< Filter Init Mode for filter 1 */ |
||
| 4847 | #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!< Filter Init Mode for filter 2 */ |
||
| 4848 | #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!< Filter Init Mode for filter 3 */ |
||
| 4849 | #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!< Filter Init Mode for filter 4 */ |
||
| 4850 | #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!< Filter Init Mode for filter 5 */ |
||
| 4851 | #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!< Filter Init Mode for filter 6 */ |
||
| 4852 | #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!< Filter Init Mode for filter 7 */ |
||
| 4853 | #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!< Filter Init Mode for filter 8 */ |
||
| 4854 | #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!< Filter Init Mode for filter 9 */ |
||
| 4855 | #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!< Filter Init Mode for filter 10 */ |
||
| 4856 | #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!< Filter Init Mode for filter 11 */ |
||
| 4857 | #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!< Filter Init Mode for filter 12 */ |
||
| 4858 | #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!< Filter Init Mode for filter 13 */ |
||
| 4859 | |||
| 4860 | /******************* Bit definition for CAN_FS1R register *******************/ |
||
| 4861 | #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!< Filter Scale Configuration */ |
||
| 4862 | #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!< Filter Scale Configuration for filter 0 */ |
||
| 4863 | #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!< Filter Scale Configuration for filter 1 */ |
||
| 4864 | #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!< Filter Scale Configuration for filter 2 */ |
||
| 4865 | #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!< Filter Scale Configuration for filter 3 */ |
||
| 4866 | #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!< Filter Scale Configuration for filter 4 */ |
||
| 4867 | #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!< Filter Scale Configuration for filter 5 */ |
||
| 4868 | #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!< Filter Scale Configuration for filter 6 */ |
||
| 4869 | #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!< Filter Scale Configuration for filter 7 */ |
||
| 4870 | #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!< Filter Scale Configuration for filter 8 */ |
||
| 4871 | #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!< Filter Scale Configuration for filter 9 */ |
||
| 4872 | #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!< Filter Scale Configuration for filter 10 */ |
||
| 4873 | #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!< Filter Scale Configuration for filter 11 */ |
||
| 4874 | #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!< Filter Scale Configuration for filter 12 */ |
||
| 4875 | #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!< Filter Scale Configuration for filter 13 */ |
||
| 4876 | |||
| 4877 | /****************** Bit definition for CAN_FFA1R register *******************/ |
||
| 4878 | #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!< Filter FIFO Assignment */ |
||
| 4879 | #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!< Filter FIFO Assignment for filter 0 */ |
||
| 4880 | #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!< Filter FIFO Assignment for filter 1 */ |
||
| 4881 | #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!< Filter FIFO Assignment for filter 2 */ |
||
| 4882 | #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!< Filter FIFO Assignment for filter 3 */ |
||
| 4883 | #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!< Filter FIFO Assignment for filter 4 */ |
||
| 4884 | #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!< Filter FIFO Assignment for filter 5 */ |
||
| 4885 | #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!< Filter FIFO Assignment for filter 6 */ |
||
| 4886 | #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!< Filter FIFO Assignment for filter 7 */ |
||
| 4887 | #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!< Filter FIFO Assignment for filter 8 */ |
||
| 4888 | #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!< Filter FIFO Assignment for filter 9 */ |
||
| 4889 | #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!< Filter FIFO Assignment for filter 10 */ |
||
| 4890 | #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!< Filter FIFO Assignment for filter 11 */ |
||
| 4891 | #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!< Filter FIFO Assignment for filter 12 */ |
||
| 4892 | #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!< Filter FIFO Assignment for filter 13 */ |
||
| 4893 | |||
| 4894 | /******************* Bit definition for CAN_FA1R register *******************/ |
||
| 4895 | #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!< Filter Active */ |
||
| 4896 | #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!< Filter 0 Active */ |
||
| 4897 | #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!< Filter 1 Active */ |
||
| 4898 | #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!< Filter 2 Active */ |
||
| 4899 | #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!< Filter 3 Active */ |
||
| 4900 | #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!< Filter 4 Active */ |
||
| 4901 | #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!< Filter 5 Active */ |
||
| 4902 | #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!< Filter 6 Active */ |
||
| 4903 | #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!< Filter 7 Active */ |
||
| 4904 | #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!< Filter 8 Active */ |
||
| 4905 | #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!< Filter 9 Active */ |
||
| 4906 | #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!< Filter 10 Active */ |
||
| 4907 | #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!< Filter 11 Active */ |
||
| 4908 | #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!< Filter 12 Active */ |
||
| 4909 | #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!< Filter 13 Active */ |
||
| 4910 | |||
| 4911 | /******************* Bit definition for CAN_F0R1 register *******************/ |
||
| 4912 | #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 4913 | #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 4914 | #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 4915 | #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 4916 | #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 4917 | #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 4918 | #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 4919 | #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 4920 | #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 4921 | #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 4922 | #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 4923 | #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 4924 | #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 4925 | #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 4926 | #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 4927 | #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 4928 | #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 4929 | #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 4930 | #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 4931 | #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 4932 | #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 4933 | #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 4934 | #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 4935 | #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 4936 | #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 4937 | #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 4938 | #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 4939 | #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 4940 | #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 4941 | #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 4942 | #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 4943 | #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 4944 | |||
| 4945 | /******************* Bit definition for CAN_F1R1 register *******************/ |
||
| 4946 | #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 4947 | #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 4948 | #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 4949 | #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 4950 | #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 4951 | #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 4952 | #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 4953 | #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 4954 | #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 4955 | #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 4956 | #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 4957 | #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 4958 | #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 4959 | #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 4960 | #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 4961 | #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 4962 | #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 4963 | #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 4964 | #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 4965 | #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 4966 | #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 4967 | #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 4968 | #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 4969 | #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 4970 | #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 4971 | #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 4972 | #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 4973 | #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 4974 | #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 4975 | #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 4976 | #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 4977 | #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 4978 | |||
| 4979 | /******************* Bit definition for CAN_F2R1 register *******************/ |
||
| 4980 | #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 4981 | #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 4982 | #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 4983 | #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 4984 | #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 4985 | #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 4986 | #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 4987 | #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 4988 | #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 4989 | #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 4990 | #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 4991 | #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 4992 | #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 4993 | #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 4994 | #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 4995 | #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 4996 | #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 4997 | #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 4998 | #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 4999 | #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5000 | #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5001 | #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5002 | #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5003 | #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5004 | #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5005 | #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5006 | #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5007 | #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5008 | #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5009 | #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5010 | #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5011 | #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5012 | |||
| 5013 | /******************* Bit definition for CAN_F3R1 register *******************/ |
||
| 5014 | #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5015 | #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5016 | #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5017 | #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5018 | #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5019 | #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5020 | #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5021 | #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5022 | #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5023 | #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5024 | #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5025 | #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5026 | #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5027 | #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5028 | #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5029 | #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5030 | #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5031 | #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5032 | #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5033 | #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5034 | #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5035 | #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5036 | #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5037 | #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5038 | #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5039 | #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5040 | #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5041 | #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5042 | #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5043 | #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5044 | #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5045 | #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5046 | |||
| 5047 | /******************* Bit definition for CAN_F4R1 register *******************/ |
||
| 5048 | #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5049 | #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5050 | #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5051 | #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5052 | #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5053 | #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5054 | #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5055 | #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5056 | #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5057 | #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5058 | #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5059 | #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5060 | #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5061 | #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5062 | #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5063 | #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5064 | #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5065 | #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5066 | #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5067 | #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5068 | #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5069 | #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5070 | #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5071 | #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5072 | #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5073 | #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5074 | #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5075 | #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5076 | #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5077 | #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5078 | #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5079 | #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5080 | |||
| 5081 | /******************* Bit definition for CAN_F5R1 register *******************/ |
||
| 5082 | #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5083 | #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5084 | #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5085 | #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5086 | #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5087 | #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5088 | #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5089 | #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5090 | #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5091 | #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5092 | #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5093 | #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5094 | #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5095 | #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5096 | #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5097 | #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5098 | #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5099 | #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5100 | #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5101 | #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5102 | #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5103 | #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5104 | #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5105 | #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5106 | #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5107 | #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5108 | #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5109 | #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5110 | #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5111 | #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5112 | #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5113 | #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5114 | |||
| 5115 | /******************* Bit definition for CAN_F6R1 register *******************/ |
||
| 5116 | #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5117 | #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5118 | #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5119 | #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5120 | #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5121 | #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5122 | #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5123 | #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5124 | #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5125 | #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5126 | #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5127 | #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5128 | #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5129 | #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5130 | #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5131 | #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5132 | #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5133 | #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5134 | #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5135 | #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5136 | #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5137 | #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5138 | #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5139 | #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5140 | #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5141 | #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5142 | #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5143 | #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5144 | #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5145 | #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5146 | #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5147 | #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5148 | |||
| 5149 | /******************* Bit definition for CAN_F7R1 register *******************/ |
||
| 5150 | #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5151 | #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5152 | #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5153 | #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5154 | #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5155 | #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5156 | #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5157 | #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5158 | #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5159 | #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5160 | #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5161 | #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5162 | #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5163 | #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5164 | #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5165 | #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5166 | #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5167 | #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5168 | #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5169 | #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5170 | #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5171 | #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5172 | #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5173 | #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5174 | #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5175 | #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5176 | #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5177 | #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5178 | #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5179 | #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5180 | #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5181 | #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5182 | |||
| 5183 | /******************* Bit definition for CAN_F8R1 register *******************/ |
||
| 5184 | #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5185 | #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5186 | #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5187 | #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5188 | #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5189 | #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5190 | #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5191 | #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5192 | #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5193 | #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5194 | #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5195 | #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5196 | #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5197 | #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5198 | #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5199 | #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5200 | #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5201 | #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5202 | #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5203 | #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5204 | #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5205 | #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5206 | #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5207 | #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5208 | #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5209 | #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5210 | #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5211 | #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5212 | #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5213 | #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5214 | #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5215 | #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5216 | |||
| 5217 | /******************* Bit definition for CAN_F9R1 register *******************/ |
||
| 5218 | #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5219 | #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5220 | #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5221 | #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5222 | #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5223 | #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5224 | #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5225 | #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5226 | #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5227 | #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5228 | #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5229 | #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5230 | #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5231 | #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5232 | #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5233 | #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5234 | #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5235 | #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5236 | #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5237 | #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5238 | #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5239 | #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5240 | #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5241 | #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5242 | #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5243 | #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5244 | #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5245 | #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5246 | #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5247 | #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5248 | #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5249 | #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5250 | |||
| 5251 | /******************* Bit definition for CAN_F10R1 register ******************/ |
||
| 5252 | #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5253 | #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5254 | #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5255 | #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5256 | #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5257 | #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5258 | #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5259 | #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5260 | #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5261 | #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5262 | #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5263 | #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5264 | #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5265 | #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5266 | #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5267 | #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5268 | #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5269 | #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5270 | #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5271 | #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5272 | #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5273 | #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5274 | #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5275 | #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5276 | #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5277 | #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5278 | #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5279 | #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5280 | #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5281 | #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5282 | #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5283 | #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5284 | |||
| 5285 | /******************* Bit definition for CAN_F11R1 register ******************/ |
||
| 5286 | #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5287 | #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5288 | #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5289 | #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5290 | #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5291 | #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5292 | #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5293 | #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5294 | #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5295 | #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5296 | #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5297 | #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5298 | #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5299 | #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5300 | #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5301 | #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5302 | #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5303 | #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5304 | #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5305 | #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5306 | #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5307 | #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5308 | #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5309 | #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5310 | #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5311 | #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5312 | #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5313 | #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5314 | #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5315 | #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5316 | #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5317 | #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5318 | |||
| 5319 | /******************* Bit definition for CAN_F12R1 register ******************/ |
||
| 5320 | #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5321 | #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5322 | #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5323 | #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5324 | #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5325 | #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5326 | #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5327 | #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5328 | #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5329 | #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5330 | #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5331 | #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5332 | #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5333 | #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5334 | #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5335 | #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5336 | #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5337 | #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5338 | #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5339 | #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5340 | #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5341 | #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5342 | #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5343 | #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5344 | #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5345 | #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5346 | #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5347 | #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5348 | #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5349 | #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5350 | #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5351 | #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5352 | |||
| 5353 | /******************* Bit definition for CAN_F13R1 register ******************/ |
||
| 5354 | #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5355 | #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5356 | #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5357 | #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5358 | #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5359 | #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5360 | #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5361 | #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5362 | #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5363 | #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5364 | #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5365 | #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5366 | #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5367 | #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5368 | #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5369 | #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5370 | #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5371 | #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5372 | #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5373 | #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5374 | #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5375 | #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5376 | #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5377 | #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5378 | #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5379 | #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5380 | #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5381 | #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5382 | #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5383 | #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5384 | #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5385 | #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5386 | |||
| 5387 | /******************* Bit definition for CAN_F0R2 register *******************/ |
||
| 5388 | #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5389 | #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5390 | #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5391 | #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5392 | #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5393 | #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5394 | #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5395 | #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5396 | #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5397 | #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5398 | #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5399 | #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5400 | #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5401 | #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5402 | #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5403 | #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5404 | #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5405 | #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5406 | #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5407 | #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5408 | #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5409 | #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5410 | #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5411 | #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5412 | #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5413 | #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5414 | #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5415 | #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5416 | #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5417 | #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5418 | #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5419 | #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5420 | |||
| 5421 | /******************* Bit definition for CAN_F1R2 register *******************/ |
||
| 5422 | #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5423 | #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5424 | #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5425 | #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5426 | #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5427 | #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5428 | #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5429 | #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5430 | #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5431 | #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5432 | #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5433 | #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5434 | #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5435 | #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5436 | #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5437 | #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5438 | #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5439 | #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5440 | #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5441 | #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5442 | #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5443 | #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5444 | #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5445 | #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5446 | #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5447 | #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5448 | #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5449 | #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5450 | #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5451 | #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5452 | #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5453 | #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5454 | |||
| 5455 | /******************* Bit definition for CAN_F2R2 register *******************/ |
||
| 5456 | #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5457 | #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5458 | #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5459 | #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5460 | #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5461 | #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5462 | #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5463 | #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5464 | #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5465 | #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5466 | #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5467 | #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5468 | #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5469 | #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5470 | #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5471 | #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5472 | #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5473 | #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5474 | #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5475 | #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5476 | #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5477 | #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5478 | #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5479 | #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5480 | #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5481 | #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5482 | #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5483 | #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5484 | #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5485 | #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5486 | #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5487 | #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5488 | |||
| 5489 | /******************* Bit definition for CAN_F3R2 register *******************/ |
||
| 5490 | #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5491 | #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5492 | #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5493 | #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5494 | #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5495 | #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5496 | #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5497 | #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5498 | #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5499 | #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5500 | #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5501 | #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5502 | #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5503 | #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5504 | #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5505 | #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5506 | #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5507 | #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5508 | #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5509 | #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5510 | #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5511 | #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5512 | #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5513 | #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5514 | #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5515 | #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5516 | #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5517 | #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5518 | #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5519 | #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5520 | #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5521 | #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5522 | |||
| 5523 | /******************* Bit definition for CAN_F4R2 register *******************/ |
||
| 5524 | #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5525 | #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5526 | #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5527 | #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5528 | #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5529 | #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5530 | #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5531 | #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5532 | #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5533 | #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5534 | #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5535 | #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5536 | #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5537 | #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5538 | #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5539 | #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5540 | #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5541 | #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5542 | #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5543 | #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5544 | #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5545 | #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5546 | #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5547 | #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5548 | #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5549 | #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5550 | #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5551 | #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5552 | #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5553 | #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5554 | #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5555 | #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5556 | |||
| 5557 | /******************* Bit definition for CAN_F5R2 register *******************/ |
||
| 5558 | #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5559 | #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5560 | #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5561 | #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5562 | #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5563 | #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5564 | #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5565 | #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5566 | #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5567 | #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5568 | #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5569 | #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5570 | #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5571 | #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5572 | #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5573 | #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5574 | #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5575 | #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5576 | #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5577 | #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5578 | #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5579 | #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5580 | #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5581 | #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5582 | #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5583 | #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5584 | #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5585 | #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5586 | #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5587 | #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5588 | #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5589 | #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5590 | |||
| 5591 | /******************* Bit definition for CAN_F6R2 register *******************/ |
||
| 5592 | #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5593 | #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5594 | #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5595 | #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5596 | #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5597 | #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5598 | #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5599 | #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5600 | #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5601 | #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5602 | #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5603 | #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5604 | #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5605 | #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5606 | #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5607 | #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5608 | #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5609 | #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5610 | #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5611 | #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5612 | #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5613 | #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5614 | #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5615 | #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5616 | #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5617 | #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5618 | #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5619 | #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5620 | #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5621 | #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5622 | #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5623 | #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5624 | |||
| 5625 | /******************* Bit definition for CAN_F7R2 register *******************/ |
||
| 5626 | #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5627 | #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5628 | #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5629 | #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5630 | #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5631 | #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5632 | #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5633 | #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5634 | #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5635 | #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5636 | #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5637 | #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5638 | #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5639 | #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5640 | #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5641 | #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5642 | #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5643 | #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5644 | #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5645 | #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5646 | #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5647 | #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5648 | #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5649 | #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5650 | #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5651 | #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5652 | #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5653 | #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5654 | #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5655 | #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5656 | #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5657 | #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5658 | |||
| 5659 | /******************* Bit definition for CAN_F8R2 register *******************/ |
||
| 5660 | #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5661 | #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5662 | #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5663 | #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5664 | #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5665 | #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5666 | #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5667 | #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5668 | #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5669 | #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5670 | #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5671 | #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5672 | #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5673 | #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5674 | #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5675 | #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5676 | #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5677 | #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5678 | #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5679 | #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5680 | #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5681 | #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5682 | #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5683 | #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5684 | #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5685 | #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5686 | #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5687 | #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5688 | #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5689 | #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5690 | #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5691 | #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5692 | |||
| 5693 | /******************* Bit definition for CAN_F9R2 register *******************/ |
||
| 5694 | #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5695 | #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5696 | #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5697 | #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5698 | #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5699 | #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5700 | #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5701 | #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5702 | #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5703 | #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5704 | #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5705 | #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5706 | #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5707 | #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5708 | #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5709 | #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5710 | #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5711 | #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5712 | #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5713 | #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5714 | #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5715 | #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5716 | #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5717 | #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5718 | #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5719 | #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5720 | #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5721 | #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5722 | #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5723 | #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5724 | #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5725 | #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5726 | |||
| 5727 | /******************* Bit definition for CAN_F10R2 register ******************/ |
||
| 5728 | #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5729 | #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5730 | #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5731 | #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5732 | #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5733 | #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5734 | #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5735 | #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5736 | #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5737 | #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5738 | #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5739 | #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5740 | #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5741 | #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5742 | #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5743 | #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5744 | #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5745 | #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5746 | #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5747 | #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5748 | #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5749 | #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5750 | #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5751 | #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5752 | #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5753 | #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5754 | #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5755 | #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5756 | #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5757 | #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5758 | #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5759 | #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5760 | |||
| 5761 | /******************* Bit definition for CAN_F11R2 register ******************/ |
||
| 5762 | #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5763 | #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5764 | #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5765 | #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5766 | #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5767 | #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5768 | #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5769 | #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5770 | #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5771 | #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5772 | #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5773 | #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5774 | #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5775 | #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5776 | #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5777 | #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5778 | #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5779 | #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5780 | #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5781 | #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5782 | #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5783 | #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5784 | #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5785 | #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5786 | #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5787 | #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5788 | #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5789 | #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5790 | #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5791 | #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5792 | #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5793 | #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5794 | |||
| 5795 | /******************* Bit definition for CAN_F12R2 register ******************/ |
||
| 5796 | #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5797 | #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5798 | #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5799 | #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5800 | #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5801 | #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5802 | #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5803 | #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5804 | #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5805 | #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5806 | #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5807 | #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5808 | #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5809 | #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5810 | #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5811 | #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5812 | #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5813 | #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5814 | #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5815 | #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5816 | #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5817 | #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5818 | #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5819 | #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5820 | #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5821 | #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5822 | #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5823 | #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5824 | #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5825 | #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5826 | #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5827 | #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5828 | |||
| 5829 | /******************* Bit definition for CAN_F13R2 register ******************/ |
||
| 5830 | #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ |
||
| 5831 | #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ |
||
| 5832 | #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ |
||
| 5833 | #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ |
||
| 5834 | #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ |
||
| 5835 | #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ |
||
| 5836 | #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ |
||
| 5837 | #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ |
||
| 5838 | #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ |
||
| 5839 | #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ |
||
| 5840 | #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ |
||
| 5841 | #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ |
||
| 5842 | #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ |
||
| 5843 | #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ |
||
| 5844 | #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ |
||
| 5845 | #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ |
||
| 5846 | #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ |
||
| 5847 | #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ |
||
| 5848 | #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ |
||
| 5849 | #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ |
||
| 5850 | #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ |
||
| 5851 | #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ |
||
| 5852 | #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ |
||
| 5853 | #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ |
||
| 5854 | #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ |
||
| 5855 | #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ |
||
| 5856 | #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ |
||
| 5857 | #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ |
||
| 5858 | #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ |
||
| 5859 | #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ |
||
| 5860 | #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ |
||
| 5861 | #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ |
||
| 5862 | |||
| 5863 | /******************************************************************************/ |
||
| 5864 | /* */ |
||
| 5865 | /* Serial Peripheral Interface */ |
||
| 5866 | /* */ |
||
| 5867 | /******************************************************************************/ |
||
| 5868 | |||
| 5869 | /******************* Bit definition for SPI_CR1 register ********************/ |
||
| 5870 | #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */ |
||
| 5871 | #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */ |
||
| 5872 | #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */ |
||
| 5873 | |||
| 5874 | #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */ |
||
| 5875 | #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
||
| 5876 | #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
||
| 5877 | #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
||
| 5878 | |||
| 5879 | #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */ |
||
| 5880 | #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */ |
||
| 5881 | #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */ |
||
| 5882 | #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */ |
||
| 5883 | #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */ |
||
| 5884 | #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */ |
||
| 5885 | #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */ |
||
| 5886 | #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */ |
||
| 5887 | #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */ |
||
| 5888 | #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */ |
||
| 5889 | |||
| 5890 | /******************* Bit definition for SPI_CR2 register ********************/ |
||
| 5891 | #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */ |
||
| 5892 | #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */ |
||
| 5893 | #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */ |
||
| 5894 | #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */ |
||
| 5895 | #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */ |
||
| 5896 | #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */ |
||
| 5897 | |||
| 5898 | /******************** Bit definition for SPI_SR register ********************/ |
||
| 5899 | #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */ |
||
| 5900 | #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */ |
||
| 5901 | #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */ |
||
| 5902 | #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */ |
||
| 5903 | #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */ |
||
| 5904 | #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */ |
||
| 5905 | #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */ |
||
| 5906 | #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */ |
||
| 5907 | |||
| 5908 | /******************** Bit definition for SPI_DR register ********************/ |
||
| 5909 | #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */ |
||
| 5910 | |||
| 5911 | /******************* Bit definition for SPI_CRCPR register ******************/ |
||
| 5912 | #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */ |
||
| 5913 | |||
| 5914 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
||
| 5915 | #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */ |
||
| 5916 | |||
| 5917 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
||
| 5918 | #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */ |
||
| 5919 | |||
| 5920 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
||
| 5921 | #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!< Channel length (number of bits per audio channel) */ |
||
| 5922 | |||
| 5923 | #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ |
||
| 5924 | #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!< Bit 0 */ |
||
| 5925 | #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!< Bit 1 */ |
||
| 5926 | |||
| 5927 | #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!< steady state clock polarity */ |
||
| 5928 | |||
| 5929 | #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ |
||
| 5930 | #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 5931 | #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 5932 | |||
| 5933 | #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!< PCM frame synchronization */ |
||
| 5934 | |||
| 5935 | #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ |
||
| 5936 | #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 5937 | #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 5938 | |||
| 5939 | #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!< I2S Enable */ |
||
| 5940 | #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!< I2S mode selection */ |
||
| 5941 | |||
| 5942 | /****************** Bit definition for SPI_I2SPR register *******************/ |
||
| 5943 | #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!< I2S Linear prescaler */ |
||
| 5944 | #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!< Odd factor for the prescaler */ |
||
| 5945 | #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!< Master Clock Output Enable */ |
||
| 5946 | |||
| 5947 | /******************************************************************************/ |
||
| 5948 | /* */ |
||
| 5949 | /* Inter-integrated Circuit Interface */ |
||
| 5950 | /* */ |
||
| 5951 | /******************************************************************************/ |
||
| 5952 | |||
| 5953 | /******************* Bit definition for I2C_CR1 register ********************/ |
||
| 5954 | #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */ |
||
| 5955 | #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */ |
||
| 5956 | #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */ |
||
| 5957 | #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */ |
||
| 5958 | #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */ |
||
| 5959 | #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */ |
||
| 5960 | #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */ |
||
| 5961 | #define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */ |
||
| 5962 | #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */ |
||
| 5963 | #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */ |
||
| 5964 | #define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */ |
||
| 5965 | #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */ |
||
| 5966 | #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */ |
||
| 5967 | #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */ |
||
| 5968 | |||
| 5969 | /******************* Bit definition for I2C_CR2 register ********************/ |
||
| 5970 | #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ |
||
| 5971 | #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 5972 | #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 5973 | #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 5974 | #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 5975 | #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 5976 | #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 5977 | |||
| 5978 | #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */ |
||
| 5979 | #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */ |
||
| 5980 | #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */ |
||
| 5981 | #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */ |
||
| 5982 | #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */ |
||
| 5983 | |||
| 5984 | /******************* Bit definition for I2C_OAR1 register *******************/ |
||
| 5985 | #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */ |
||
| 5986 | #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */ |
||
| 5987 | |||
| 5988 | #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 5989 | #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 5990 | #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 5991 | #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 5992 | #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 5993 | #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 5994 | #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 5995 | #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
||
| 5996 | #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */ |
||
| 5997 | #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */ |
||
| 5998 | |||
| 5999 | #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */ |
||
| 6000 | |||
| 6001 | /******************* Bit definition for I2C_OAR2 register *******************/ |
||
| 6002 | #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */ |
||
| 6003 | #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */ |
||
| 6004 | |||
| 6005 | /******************* Bit definition for I2C_SR1 register ********************/ |
||
| 6006 | #define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */ |
||
| 6007 | #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */ |
||
| 6008 | #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */ |
||
| 6009 | #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */ |
||
| 6010 | #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */ |
||
| 6011 | #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */ |
||
| 6012 | #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */ |
||
| 6013 | #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */ |
||
| 6014 | #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */ |
||
| 6015 | #define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */ |
||
| 6016 | #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */ |
||
| 6017 | #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */ |
||
| 6018 | #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */ |
||
| 6019 | #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */ |
||
| 6020 | |||
| 6021 | /******************* Bit definition for I2C_SR2 register ********************/ |
||
| 6022 | #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */ |
||
| 6023 | #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */ |
||
| 6024 | #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */ |
||
| 6025 | #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */ |
||
| 6026 | #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */ |
||
| 6027 | #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */ |
||
| 6028 | #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */ |
||
| 6029 | #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */ |
||
| 6030 | |||
| 6031 | /******************* Bit definition for I2C_CCR register ********************/ |
||
| 6032 | #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ |
||
| 6033 | #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */ |
||
| 6034 | #define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */ |
||
| 6035 | |||
| 6036 | /****************** Bit definition for I2C_TRISE register *******************/ |
||
| 6037 | #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ |
||
| 6038 | |||
| 6039 | /******************************************************************************/ |
||
| 6040 | /* */ |
||
| 6041 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
||
| 6042 | /* */ |
||
| 6043 | /******************************************************************************/ |
||
| 6044 | |||
| 6045 | /******************* Bit definition for USART_SR register *******************/ |
||
| 6046 | #define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */ |
||
| 6047 | #define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */ |
||
| 6048 | #define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */ |
||
| 6049 | #define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */ |
||
| 6050 | #define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */ |
||
| 6051 | #define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */ |
||
| 6052 | #define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */ |
||
| 6053 | #define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */ |
||
| 6054 | #define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */ |
||
| 6055 | #define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */ |
||
| 6056 | |||
| 6057 | /******************* Bit definition for USART_DR register *******************/ |
||
| 6058 | #define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */ |
||
| 6059 | |||
| 6060 | /****************** Bit definition for USART_BRR register *******************/ |
||
| 6061 | #define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */ |
||
| 6062 | #define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */ |
||
| 6063 | |||
| 6064 | /****************** Bit definition for USART_CR1 register *******************/ |
||
| 6065 | #define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */ |
||
| 6066 | #define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */ |
||
| 6067 | #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */ |
||
| 6068 | #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */ |
||
| 6069 | #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */ |
||
| 6070 | #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */ |
||
| 6071 | #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */ |
||
| 6072 | #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */ |
||
| 6073 | #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */ |
||
| 6074 | #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */ |
||
| 6075 | #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */ |
||
| 6076 | #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */ |
||
| 6077 | #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */ |
||
| 6078 | #define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */ |
||
| 6079 | |||
| 6080 | /****************** Bit definition for USART_CR2 register *******************/ |
||
| 6081 | #define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */ |
||
| 6082 | #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */ |
||
| 6083 | #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */ |
||
| 6084 | #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */ |
||
| 6085 | #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */ |
||
| 6086 | #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */ |
||
| 6087 | #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */ |
||
| 6088 | |||
| 6089 | #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */ |
||
| 6090 | #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 6091 | #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 6092 | |||
| 6093 | #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */ |
||
| 6094 | |||
| 6095 | /****************** Bit definition for USART_CR3 register *******************/ |
||
| 6096 | #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */ |
||
| 6097 | #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */ |
||
| 6098 | #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */ |
||
| 6099 | #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */ |
||
| 6100 | #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */ |
||
| 6101 | #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */ |
||
| 6102 | #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */ |
||
| 6103 | #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */ |
||
| 6104 | #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */ |
||
| 6105 | #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */ |
||
| 6106 | #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */ |
||
| 6107 | |||
| 6108 | /****************** Bit definition for USART_GTPR register ******************/ |
||
| 6109 | #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */ |
||
| 6110 | #define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 6111 | #define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 6112 | #define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 6113 | #define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 6114 | #define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 6115 | #define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 6116 | #define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 6117 | #define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
||
| 6118 | |||
| 6119 | #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */ |
||
| 6120 | |||
| 6121 | /******************************************************************************/ |
||
| 6122 | /* */ |
||
| 6123 | /* Debug MCU */ |
||
| 6124 | /* */ |
||
| 6125 | /******************************************************************************/ |
||
| 6126 | |||
| 6127 | /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
||
| 6128 | #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ |
||
| 6129 | |||
| 6130 | #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ |
||
| 6131 | #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 6132 | #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 6133 | #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
||
| 6134 | #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
||
| 6135 | #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
||
| 6136 | #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
||
| 6137 | #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
||
| 6138 | #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
||
| 6139 | #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ |
||
| 6140 | #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ |
||
| 6141 | #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ |
||
| 6142 | #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ |
||
| 6143 | #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ |
||
| 6144 | #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ |
||
| 6145 | #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ |
||
| 6146 | #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ |
||
| 6147 | |||
| 6148 | /****************** Bit definition for DBGMCU_CR register *******************/ |
||
| 6149 | #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ |
||
| 6150 | #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ |
||
| 6151 | #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ |
||
| 6152 | #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ |
||
| 6153 | |||
| 6154 | #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
||
| 6155 | #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 6156 | #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 6157 | |||
| 6158 | #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ |
||
| 6159 | #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ |
||
| 6160 | #define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ |
||
| 6161 | #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ |
||
| 6162 | #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ |
||
| 6163 | #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ |
||
| 6164 | #define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ |
||
| 6165 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ |
||
| 6166 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ |
||
| 6167 | #define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ |
||
| 6168 | #define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ |
||
| 6169 | #define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ |
||
| 6170 | #define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ |
||
| 6171 | #define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ |
||
| 6172 | #define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ |
||
| 6173 | #define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ |
||
| 6174 | #define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ |
||
| 6175 | #define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ |
||
| 6176 | #define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ |
||
| 6177 | |||
| 6178 | /******************************************************************************/ |
||
| 6179 | /* */ |
||
| 6180 | /* FLASH and Option Bytes Registers */ |
||
| 6181 | /* */ |
||
| 6182 | /******************************************************************************/ |
||
| 6183 | /******************* Bit definition for FLASH_ACR register ******************/ |
||
| 6184 | #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */ |
||
| 6185 | #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 6186 | #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 6187 | #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 6188 | |||
| 6189 | #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */ |
||
| 6190 | #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */ |
||
| 6191 | #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */ |
||
| 6192 | |||
| 6193 | /****************** Bit definition for FLASH_KEYR register ******************/ |
||
| 6194 | #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ |
||
| 6195 | |||
| 6196 | #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */ |
||
| 6197 | #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */ |
||
| 6198 | #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */ |
||
| 6199 | |||
| 6200 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
||
| 6201 | #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ |
||
| 6202 | |||
| 6203 | #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ |
||
| 6204 | #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ |
||
| 6205 | |||
| 6206 | /****************** Bit definition for FLASH_SR register ********************/ |
||
| 6207 | #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ |
||
| 6208 | #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ |
||
| 6209 | #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */ |
||
| 6210 | #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */ |
||
| 6211 | |||
| 6212 | /******************* Bit definition for FLASH_CR register *******************/ |
||
| 6213 | #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */ |
||
| 6214 | #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */ |
||
| 6215 | #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */ |
||
| 6216 | #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ |
||
| 6217 | #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */ |
||
| 6218 | #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */ |
||
| 6219 | #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */ |
||
| 6220 | #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ |
||
| 6221 | #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ |
||
| 6222 | #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ |
||
| 6223 | |||
| 6224 | /******************* Bit definition for FLASH_AR register *******************/ |
||
| 6225 | #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ |
||
| 6226 | |||
| 6227 | /****************** Bit definition for FLASH_OBR register *******************/ |
||
| 6228 | #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */ |
||
| 6229 | #define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /*!< Read protection */ |
||
| 6230 | |||
| 6231 | #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /*!< IWDG SW */ |
||
| 6232 | #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /*!< nRST_STOP */ |
||
| 6233 | #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /*!< nRST_STDBY */ |
||
| 6234 | #define FLASH_OBR_BFB2 ((uint32_t)0x00000020) /*!< BFB2 */ |
||
| 6235 | #define FLASH_OBR_USER ((uint32_t)0x0000003C) /*!< User Option Bytes */ |
||
| 6236 | |||
| 6237 | /****************** Bit definition for FLASH_WRPR register ******************/ |
||
| 6238 | #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ |
||
| 6239 | |||
| 6240 | /***************** Bit definition for FLASH_OPTKEYR2 register ****************/ |
||
| 6241 | #define FLASH_OPTKEYR_OPTKEYR2 ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ |
||
| 6242 | |||
| 6243 | /****************** Bit definition for FLASH_SR2 register ********************/ |
||
| 6244 | #define FLASH_SR2_BSY ((uint32_t)0x00000001) /*!< Busy */ |
||
| 6245 | #define FLASH_SR2_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ |
||
| 6246 | #define FLASH_SR2_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */ |
||
| 6247 | #define FLASH_SR2_EOP ((uint32_t)0x00000020) /*!< End of operation */ |
||
| 6248 | |||
| 6249 | /******************* Bit definition for FLASH_CR2 register *******************/ |
||
| 6250 | #define FLASH_CR2_PG ((uint32_t)0x00000001) /*!< Programming */ |
||
| 6251 | #define FLASH_CR2_PER ((uint32_t)0x00000002) /*!< Page Erase */ |
||
| 6252 | #define FLASH_CR2_MER ((uint32_t)0x00000004) /*!< Mass Erase */ |
||
| 6253 | #define FLASH_CR2_STRT ((uint32_t)0x00000040) /*!< Start */ |
||
| 6254 | #define FLASH_CR2_LOCK ((uint32_t)0x00000080) /*!< Lock */ |
||
| 6255 | #define FLASH_CR2_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ |
||
| 6256 | #define FLASH_CR2_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ |
||
| 6257 | |||
| 6258 | /******************* Bit definition for FLASH_AR2 register *******************/ |
||
| 6259 | #define FLASH_AR_FAR2 ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ |
||
| 6260 | |||
| 6261 | /*----------------------------------------------------------------------------*/ |
||
| 6262 | |||
| 6263 | /****************** Bit definition for FLASH_RDP register *******************/ |
||
| 6264 | #define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ |
||
| 6265 | #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ |
||
| 6266 | |||
| 6267 | /****************** Bit definition for FLASH_USER register ******************/ |
||
| 6268 | #define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ |
||
| 6269 | #define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ |
||
| 6270 | |||
| 6271 | /****************** Bit definition for FLASH_Data0 register *****************/ |
||
| 6272 | #define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ |
||
| 6273 | #define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ |
||
| 6274 | |||
| 6275 | /****************** Bit definition for FLASH_Data1 register *****************/ |
||
| 6276 | #define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ |
||
| 6277 | #define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ |
||
| 6278 | |||
| 6279 | /****************** Bit definition for FLASH_WRP0 register ******************/ |
||
| 6280 | #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ |
||
| 6281 | #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ |
||
| 6282 | |||
| 6283 | /****************** Bit definition for FLASH_WRP1 register ******************/ |
||
| 6284 | #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ |
||
| 6285 | #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ |
||
| 6286 | |||
| 6287 | /****************** Bit definition for FLASH_WRP2 register ******************/ |
||
| 6288 | #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ |
||
| 6289 | #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ |
||
| 6290 | |||
| 6291 | /****************** Bit definition for FLASH_WRP3 register ******************/ |
||
| 6292 | #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ |
||
| 6293 | #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ |
||
| 6294 | |||
| 6295 | |||
| 6296 | |||
| 6297 | /** |
||
| 6298 | * @} |
||
| 6299 | */ |
||
| 6300 | |||
| 6301 | /** |
||
| 6302 | * @} |
||
| 6303 | */ |
||
| 6304 | |||
| 6305 | /** @addtogroup Exported_macro |
||
| 6306 | * @{ |
||
| 6307 | */ |
||
| 6308 | |||
| 6309 | /****************************** ADC Instances *********************************/ |
||
| 6310 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
||
| 6311 | ((INSTANCE) == ADC2) || \ |
||
| 6312 | ((INSTANCE) == ADC3)) |
||
| 6313 | |||
| 6314 | #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
||
| 6315 | |||
| 6316 | #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
||
| 6317 | ((INSTANCE) == ADC3)) |
||
| 6318 | |||
| 6319 | /****************************** CAN Instances *********************************/ |
||
| 6320 | #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) |
||
| 6321 | |||
| 6322 | /****************************** CRC Instances *********************************/ |
||
| 6323 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
||
| 6324 | |||
| 6325 | /****************************** DAC Instances *********************************/ |
||
| 6326 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) |
||
| 6327 | |||
| 6328 | /****************************** DMA Instances *********************************/ |
||
| 6329 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
||
| 6330 | ((INSTANCE) == DMA1_Channel2) || \ |
||
| 6331 | ((INSTANCE) == DMA1_Channel3) || \ |
||
| 6332 | ((INSTANCE) == DMA1_Channel4) || \ |
||
| 6333 | ((INSTANCE) == DMA1_Channel5) || \ |
||
| 6334 | ((INSTANCE) == DMA1_Channel6) || \ |
||
| 6335 | ((INSTANCE) == DMA1_Channel7) || \ |
||
| 6336 | ((INSTANCE) == DMA2_Channel1) || \ |
||
| 6337 | ((INSTANCE) == DMA2_Channel2) || \ |
||
| 6338 | ((INSTANCE) == DMA2_Channel3) || \ |
||
| 6339 | ((INSTANCE) == DMA2_Channel4) || \ |
||
| 6340 | ((INSTANCE) == DMA2_Channel5)) |
||
| 6341 | |||
| 6342 | /******************************* GPIO Instances *******************************/ |
||
| 6343 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
||
| 6344 | ((INSTANCE) == GPIOB) || \ |
||
| 6345 | ((INSTANCE) == GPIOC) || \ |
||
| 6346 | ((INSTANCE) == GPIOD) || \ |
||
| 6347 | ((INSTANCE) == GPIOE) || \ |
||
| 6348 | ((INSTANCE) == GPIOF) || \ |
||
| 6349 | ((INSTANCE) == GPIOG)) |
||
| 6350 | |||
| 6351 | /**************************** GPIO Alternate Function Instances ***************/ |
||
| 6352 | #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
||
| 6353 | |||
| 6354 | /**************************** GPIO Lock Instances *****************************/ |
||
| 6355 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
||
| 6356 | |||
| 6357 | /******************************** I2C Instances *******************************/ |
||
| 6358 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
||
| 6359 | ((INSTANCE) == I2C2)) |
||
| 6360 | |||
| 6361 | /******************************** I2S Instances *******************************/ |
||
| 6362 | #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ |
||
| 6363 | ((INSTANCE) == SPI3)) |
||
| 6364 | |||
| 6365 | /****************************** IWDG Instances ********************************/ |
||
| 6366 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
||
| 6367 | |||
| 6368 | /****************************** SDIO Instances *********************************/ |
||
| 6369 | #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) |
||
| 6370 | |||
| 6371 | /******************************** SPI Instances *******************************/ |
||
| 6372 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
||
| 6373 | ((INSTANCE) == SPI2) || \ |
||
| 6374 | ((INSTANCE) == SPI3)) |
||
| 6375 | |||
| 6376 | /****************************** START TIM Instances ***************************/ |
||
| 6377 | /****************************** TIM Instances *********************************/ |
||
| 6378 | #define IS_TIM_INSTANCE(INSTANCE)\ |
||
| 6379 | (((INSTANCE) == TIM1) || \ |
||
| 6380 | ((INSTANCE) == TIM8) || \ |
||
| 6381 | ((INSTANCE) == TIM2) || \ |
||
| 6382 | ((INSTANCE) == TIM3) || \ |
||
| 6383 | ((INSTANCE) == TIM4) || \ |
||
| 6384 | ((INSTANCE) == TIM5) || \ |
||
| 6385 | ((INSTANCE) == TIM6) || \ |
||
| 6386 | ((INSTANCE) == TIM7) || \ |
||
| 6387 | ((INSTANCE) == TIM9) || \ |
||
| 6388 | ((INSTANCE) == TIM10) || \ |
||
| 6389 | ((INSTANCE) == TIM11) || \ |
||
| 6390 | ((INSTANCE) == TIM12) || \ |
||
| 6391 | ((INSTANCE) == TIM13) || \ |
||
| 6392 | ((INSTANCE) == TIM14)) |
||
| 6393 | |||
| 6394 | #define IS_TIM_CC1_INSTANCE(INSTANCE)\ |
||
| 6395 | (((INSTANCE) == TIM1) || \ |
||
| 6396 | ((INSTANCE) == TIM8) || \ |
||
| 6397 | ((INSTANCE) == TIM2) || \ |
||
| 6398 | ((INSTANCE) == TIM3) || \ |
||
| 6399 | ((INSTANCE) == TIM4) || \ |
||
| 6400 | ((INSTANCE) == TIM5) || \ |
||
| 6401 | ((INSTANCE) == TIM9) || \ |
||
| 6402 | ((INSTANCE) == TIM10) || \ |
||
| 6403 | ((INSTANCE) == TIM11) || \ |
||
| 6404 | ((INSTANCE) == TIM12) || \ |
||
| 6405 | ((INSTANCE) == TIM13) || \ |
||
| 6406 | ((INSTANCE) == TIM14)) |
||
| 6407 | |||
| 6408 | #define IS_TIM_CC2_INSTANCE(INSTANCE)\ |
||
| 6409 | (((INSTANCE) == TIM1) || \ |
||
| 6410 | ((INSTANCE) == TIM8) || \ |
||
| 6411 | ((INSTANCE) == TIM2) || \ |
||
| 6412 | ((INSTANCE) == TIM3) || \ |
||
| 6413 | ((INSTANCE) == TIM4) || \ |
||
| 6414 | ((INSTANCE) == TIM5) || \ |
||
| 6415 | ((INSTANCE) == TIM9) || \ |
||
| 6416 | ((INSTANCE) == TIM12)) |
||
| 6417 | |||
| 6418 | #define IS_TIM_CC3_INSTANCE(INSTANCE)\ |
||
| 6419 | (((INSTANCE) == TIM1) || \ |
||
| 6420 | ((INSTANCE) == TIM8) || \ |
||
| 6421 | ((INSTANCE) == TIM2) || \ |
||
| 6422 | ((INSTANCE) == TIM3) || \ |
||
| 6423 | ((INSTANCE) == TIM4) || \ |
||
| 6424 | ((INSTANCE) == TIM5)) |
||
| 6425 | |||
| 6426 | #define IS_TIM_CC4_INSTANCE(INSTANCE)\ |
||
| 6427 | (((INSTANCE) == TIM1) || \ |
||
| 6428 | ((INSTANCE) == TIM8) || \ |
||
| 6429 | ((INSTANCE) == TIM2) || \ |
||
| 6430 | ((INSTANCE) == TIM3) || \ |
||
| 6431 | ((INSTANCE) == TIM4) || \ |
||
| 6432 | ((INSTANCE) == TIM5)) |
||
| 6433 | |||
| 6434 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ |
||
| 6435 | (((INSTANCE) == TIM1) || \ |
||
| 6436 | ((INSTANCE) == TIM8) || \ |
||
| 6437 | ((INSTANCE) == TIM2) || \ |
||
| 6438 | ((INSTANCE) == TIM3) || \ |
||
| 6439 | ((INSTANCE) == TIM4) || \ |
||
| 6440 | ((INSTANCE) == TIM5)) |
||
| 6441 | |||
| 6442 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ |
||
| 6443 | (((INSTANCE) == TIM1) || \ |
||
| 6444 | ((INSTANCE) == TIM8) || \ |
||
| 6445 | ((INSTANCE) == TIM2) || \ |
||
| 6446 | ((INSTANCE) == TIM3) || \ |
||
| 6447 | ((INSTANCE) == TIM4) || \ |
||
| 6448 | ((INSTANCE) == TIM5)) |
||
| 6449 | |||
| 6450 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ |
||
| 6451 | (((INSTANCE) == TIM1) || \ |
||
| 6452 | ((INSTANCE) == TIM8) || \ |
||
| 6453 | ((INSTANCE) == TIM2) || \ |
||
| 6454 | ((INSTANCE) == TIM3) || \ |
||
| 6455 | ((INSTANCE) == TIM4) || \ |
||
| 6456 | ((INSTANCE) == TIM5) || \ |
||
| 6457 | ((INSTANCE) == TIM9) || \ |
||
| 6458 | ((INSTANCE) == TIM12)) |
||
| 6459 | |||
| 6460 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ |
||
| 6461 | (((INSTANCE) == TIM1) || \ |
||
| 6462 | ((INSTANCE) == TIM8) || \ |
||
| 6463 | ((INSTANCE) == TIM2) || \ |
||
| 6464 | ((INSTANCE) == TIM3) || \ |
||
| 6465 | ((INSTANCE) == TIM4) || \ |
||
| 6466 | ((INSTANCE) == TIM5) || \ |
||
| 6467 | ((INSTANCE) == TIM9) || \ |
||
| 6468 | ((INSTANCE) == TIM12)) |
||
| 6469 | |||
| 6470 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ |
||
| 6471 | (((INSTANCE) == TIM1) || \ |
||
| 6472 | ((INSTANCE) == TIM8) || \ |
||
| 6473 | ((INSTANCE) == TIM2) || \ |
||
| 6474 | ((INSTANCE) == TIM3) || \ |
||
| 6475 | ((INSTANCE) == TIM4) || \ |
||
| 6476 | ((INSTANCE) == TIM5)) |
||
| 6477 | |||
| 6478 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ |
||
| 6479 | (((INSTANCE) == TIM1) || \ |
||
| 6480 | ((INSTANCE) == TIM8) || \ |
||
| 6481 | ((INSTANCE) == TIM2) || \ |
||
| 6482 | ((INSTANCE) == TIM3) || \ |
||
| 6483 | ((INSTANCE) == TIM4) || \ |
||
| 6484 | ((INSTANCE) == TIM5)) |
||
| 6485 | |||
| 6486 | #define IS_TIM_XOR_INSTANCE(INSTANCE)\ |
||
| 6487 | (((INSTANCE) == TIM1) || \ |
||
| 6488 | ((INSTANCE) == TIM8) || \ |
||
| 6489 | ((INSTANCE) == TIM2) || \ |
||
| 6490 | ((INSTANCE) == TIM3) || \ |
||
| 6491 | ((INSTANCE) == TIM4) || \ |
||
| 6492 | ((INSTANCE) == TIM5)) |
||
| 6493 | |||
| 6494 | #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ |
||
| 6495 | (((INSTANCE) == TIM1) || \ |
||
| 6496 | ((INSTANCE) == TIM8) || \ |
||
| 6497 | ((INSTANCE) == TIM2) || \ |
||
| 6498 | ((INSTANCE) == TIM3) || \ |
||
| 6499 | ((INSTANCE) == TIM4) || \ |
||
| 6500 | ((INSTANCE) == TIM5) || \ |
||
| 6501 | ((INSTANCE) == TIM6) || \ |
||
| 6502 | ((INSTANCE) == TIM7) || \ |
||
| 6503 | ((INSTANCE) == TIM12)) |
||
| 6504 | |||
| 6505 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ |
||
| 6506 | (((INSTANCE) == TIM1) || \ |
||
| 6507 | ((INSTANCE) == TIM8) || \ |
||
| 6508 | ((INSTANCE) == TIM2) || \ |
||
| 6509 | ((INSTANCE) == TIM3) || \ |
||
| 6510 | ((INSTANCE) == TIM4) || \ |
||
| 6511 | ((INSTANCE) == TIM5) || \ |
||
| 6512 | ((INSTANCE) == TIM12)) |
||
| 6513 | |||
| 6514 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ |
||
| 6515 | (((INSTANCE) == TIM1) || \ |
||
| 6516 | ((INSTANCE) == TIM8) || \ |
||
| 6517 | ((INSTANCE) == TIM2) || \ |
||
| 6518 | ((INSTANCE) == TIM3) || \ |
||
| 6519 | ((INSTANCE) == TIM4) || \ |
||
| 6520 | ((INSTANCE) == TIM5)) |
||
| 6521 | |||
| 6522 | #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ |
||
| 6523 | (((INSTANCE) == TIM1) || \ |
||
| 6524 | ((INSTANCE) == TIM8)) |
||
| 6525 | |||
| 6526 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
||
| 6527 | ((((INSTANCE) == TIM1) && \ |
||
| 6528 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6529 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6530 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6531 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6532 | || \ |
||
| 6533 | (((INSTANCE) == TIM8) && \ |
||
| 6534 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6535 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6536 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6537 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6538 | || \ |
||
| 6539 | (((INSTANCE) == TIM2) && \ |
||
| 6540 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6541 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6542 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6543 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6544 | || \ |
||
| 6545 | (((INSTANCE) == TIM3) && \ |
||
| 6546 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6547 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6548 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6549 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6550 | || \ |
||
| 6551 | (((INSTANCE) == TIM4) && \ |
||
| 6552 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6553 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6554 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6555 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6556 | || \ |
||
| 6557 | (((INSTANCE) == TIM5) && \ |
||
| 6558 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6559 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6560 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6561 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6562 | || \ |
||
| 6563 | (((INSTANCE) == TIM9) && \ |
||
| 6564 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6565 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
||
| 6566 | || \ |
||
| 6567 | (((INSTANCE) == TIM10) && \ |
||
| 6568 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
||
| 6569 | || \ |
||
| 6570 | (((INSTANCE) == TIM11) && \ |
||
| 6571 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
||
| 6572 | || \ |
||
| 6573 | (((INSTANCE) == TIM12) && \ |
||
| 6574 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6575 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
||
| 6576 | || \ |
||
| 6577 | (((INSTANCE) == TIM13) && \ |
||
| 6578 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
||
| 6579 | || \ |
||
| 6580 | (((INSTANCE) == TIM14) && \ |
||
| 6581 | (((CHANNEL) == TIM_CHANNEL_1)))) |
||
| 6582 | |||
| 6583 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
||
| 6584 | ((((INSTANCE) == TIM1) && \ |
||
| 6585 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6586 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6587 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
||
| 6588 | || \ |
||
| 6589 | (((INSTANCE) == TIM8) && \ |
||
| 6590 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6591 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6592 | ((CHANNEL) == TIM_CHANNEL_3)))) |
||
| 6593 | |||
| 6594 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ |
||
| 6595 | (((INSTANCE) == TIM1) || \ |
||
| 6596 | ((INSTANCE) == TIM8) || \ |
||
| 6597 | ((INSTANCE) == TIM2) || \ |
||
| 6598 | ((INSTANCE) == TIM3) || \ |
||
| 6599 | ((INSTANCE) == TIM4) || \ |
||
| 6600 | ((INSTANCE) == TIM5)) |
||
| 6601 | |||
| 6602 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ |
||
| 6603 | (((INSTANCE) == TIM1) || \ |
||
| 6604 | ((INSTANCE) == TIM8)) |
||
| 6605 | |||
| 6606 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ |
||
| 6607 | (((INSTANCE) == TIM1) || \ |
||
| 6608 | ((INSTANCE) == TIM8) || \ |
||
| 6609 | ((INSTANCE) == TIM2) || \ |
||
| 6610 | ((INSTANCE) == TIM3) || \ |
||
| 6611 | ((INSTANCE) == TIM4) || \ |
||
| 6612 | ((INSTANCE) == TIM5) || \ |
||
| 6613 | ((INSTANCE) == TIM9) || \ |
||
| 6614 | ((INSTANCE) == TIM10) || \ |
||
| 6615 | ((INSTANCE) == TIM11) || \ |
||
| 6616 | ((INSTANCE) == TIM12) || \ |
||
| 6617 | ((INSTANCE) == TIM13) || \ |
||
| 6618 | ((INSTANCE) == TIM14)) |
||
| 6619 | |||
| 6620 | #define IS_TIM_DMA_INSTANCE(INSTANCE)\ |
||
| 6621 | (((INSTANCE) == TIM1) || \ |
||
| 6622 | ((INSTANCE) == TIM8) || \ |
||
| 6623 | ((INSTANCE) == TIM2) || \ |
||
| 6624 | ((INSTANCE) == TIM3) || \ |
||
| 6625 | ((INSTANCE) == TIM4) || \ |
||
| 6626 | ((INSTANCE) == TIM5) || \ |
||
| 6627 | ((INSTANCE) == TIM6) || \ |
||
| 6628 | ((INSTANCE) == TIM7)) |
||
| 6629 | |||
| 6630 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ |
||
| 6631 | (((INSTANCE) == TIM1) || \ |
||
| 6632 | ((INSTANCE) == TIM8) || \ |
||
| 6633 | ((INSTANCE) == TIM2) || \ |
||
| 6634 | ((INSTANCE) == TIM3) || \ |
||
| 6635 | ((INSTANCE) == TIM4) || \ |
||
| 6636 | ((INSTANCE) == TIM5)) |
||
| 6637 | |||
| 6638 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ |
||
| 6639 | (((INSTANCE) == TIM1) || \ |
||
| 6640 | ((INSTANCE) == TIM8)) |
||
| 6641 | |||
| 6642 | /****************************** END TIM Instances *****************************/ |
||
| 6643 | |||
| 6644 | |||
| 6645 | /******************** USART Instances : Synchronous mode **********************/ |
||
| 6646 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6647 | ((INSTANCE) == USART2) || \ |
||
| 6648 | ((INSTANCE) == USART3)) |
||
| 6649 | |||
| 6650 | /******************** UART Instances : Asynchronous mode **********************/ |
||
| 6651 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6652 | ((INSTANCE) == USART2) || \ |
||
| 6653 | ((INSTANCE) == USART3) || \ |
||
| 6654 | ((INSTANCE) == UART4) || \ |
||
| 6655 | ((INSTANCE) == UART5)) |
||
| 6656 | |||
| 6657 | /******************** UART Instances : Half-Duplex mode **********************/ |
||
| 6658 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6659 | ((INSTANCE) == USART2) || \ |
||
| 6660 | ((INSTANCE) == USART3) || \ |
||
| 6661 | ((INSTANCE) == UART4) || \ |
||
| 6662 | ((INSTANCE) == UART5)) |
||
| 6663 | |||
| 6664 | /******************** UART Instances : LIN mode **********************/ |
||
| 6665 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6666 | ((INSTANCE) == USART2) || \ |
||
| 6667 | ((INSTANCE) == USART3) || \ |
||
| 6668 | ((INSTANCE) == UART4) || \ |
||
| 6669 | ((INSTANCE) == UART5)) |
||
| 6670 | |||
| 6671 | /****************** UART Instances : Hardware Flow control ********************/ |
||
| 6672 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6673 | ((INSTANCE) == USART2) || \ |
||
| 6674 | ((INSTANCE) == USART3)) |
||
| 6675 | |||
| 6676 | /********************* UART Instances : Smard card mode ***********************/ |
||
| 6677 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6678 | ((INSTANCE) == USART2) || \ |
||
| 6679 | ((INSTANCE) == USART3)) |
||
| 6680 | |||
| 6681 | /*********************** UART Instances : IRDA mode ***************************/ |
||
| 6682 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6683 | ((INSTANCE) == USART2) || \ |
||
| 6684 | ((INSTANCE) == USART3) || \ |
||
| 6685 | ((INSTANCE) == UART4) || \ |
||
| 6686 | ((INSTANCE) == UART5)) |
||
| 6687 | |||
| 6688 | /***************** UART Instances : Multi-Processor mode **********************/ |
||
| 6689 | #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6690 | ((INSTANCE) == USART2) || \ |
||
| 6691 | ((INSTANCE) == USART3) || \ |
||
| 6692 | ((INSTANCE) == UART4) || \ |
||
| 6693 | ((INSTANCE) == UART5)) |
||
| 6694 | |||
| 6695 | /***************** UART Instances : DMA mode available **********************/ |
||
| 6696 | #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6697 | ((INSTANCE) == USART2) || \ |
||
| 6698 | ((INSTANCE) == USART3) || \ |
||
| 6699 | ((INSTANCE) == UART4)) |
||
| 6700 | |||
| 6701 | /****************************** RTC Instances *********************************/ |
||
| 6702 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
||
| 6703 | |||
| 6704 | /**************************** WWDG Instances *****************************/ |
||
| 6705 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
||
| 6706 | |||
| 6707 | /****************************** USB Instances ********************************/ |
||
| 6708 | #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
||
| 6709 | |||
| 6710 | |||
| 6711 | |||
| 6712 | |||
| 6713 | /** |
||
| 6714 | * @} |
||
| 6715 | */ |
||
| 6716 | /******************************************************************************/ |
||
| 6717 | /* For a painless codes migration between the STM32F1xx device product */ |
||
| 6718 | /* lines, the aliases defined below are put in place to overcome the */ |
||
| 6719 | /* differences in the interrupt handlers and IRQn definitions. */ |
||
| 6720 | /* No need to update developed interrupt code when moving across */ |
||
| 6721 | /* product lines within the same STM32F1 Family */ |
||
| 6722 | /******************************************************************************/ |
||
| 6723 | |||
| 6724 | /* Aliases for __IRQn */ |
||
| 6725 | #define ADC1_IRQn ADC1_2_IRQn |
||
| 6726 | #define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn |
||
| 6727 | #define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn |
||
| 6728 | #define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn |
||
| 6729 | #define TIM9_IRQn TIM1_BRK_TIM9_IRQn |
||
| 6730 | #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn |
||
| 6731 | #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn |
||
| 6732 | #define TIM11_IRQn TIM1_TRG_COM_TIM11_IRQn |
||
| 6733 | #define TIM10_IRQn TIM1_UP_TIM10_IRQn |
||
| 6734 | #define TIM1_UP_TIM16_IRQn TIM1_UP_TIM10_IRQn |
||
| 6735 | #define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn |
||
| 6736 | #define TIM6_DAC_IRQn TIM6_IRQn |
||
| 6737 | #define TIM12_IRQn TIM8_BRK_TIM12_IRQn |
||
| 6738 | #define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn |
||
| 6739 | #define TIM14_IRQn TIM8_TRG_COM_TIM14_IRQn |
||
| 6740 | #define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn |
||
| 6741 | #define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn |
||
| 6742 | #define TIM13_IRQn TIM8_UP_TIM13_IRQn |
||
| 6743 | #define CEC_IRQn USBWakeUp_IRQn |
||
| 6744 | #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn |
||
| 6745 | #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn |
||
| 6746 | #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn |
||
| 6747 | #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn |
||
| 6748 | #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn |
||
| 6749 | |||
| 6750 | |||
| 6751 | /* Aliases for __IRQHandler */ |
||
| 6752 | #define ADC1_IRQHandler ADC1_2_IRQHandler |
||
| 6753 | #define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler |
||
| 6754 | #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler |
||
| 6755 | #define TIM1_BRK_IRQHandler TIM1_BRK_TIM9_IRQHandler |
||
| 6756 | #define TIM9_IRQHandler TIM1_BRK_TIM9_IRQHandler |
||
| 6757 | #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler |
||
| 6758 | #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler |
||
| 6759 | #define TIM11_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler |
||
| 6760 | #define TIM10_IRQHandler TIM1_UP_TIM10_IRQHandler |
||
| 6761 | #define TIM1_UP_TIM16_IRQHandler TIM1_UP_TIM10_IRQHandler |
||
| 6762 | #define TIM1_UP_IRQHandler TIM1_UP_TIM10_IRQHandler |
||
| 6763 | #define TIM6_DAC_IRQHandler TIM6_IRQHandler |
||
| 6764 | #define TIM12_IRQHandler TIM8_BRK_TIM12_IRQHandler |
||
| 6765 | #define TIM8_BRK_IRQHandler TIM8_BRK_TIM12_IRQHandler |
||
| 6766 | #define TIM14_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler |
||
| 6767 | #define TIM8_TRG_COM_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler |
||
| 6768 | #define TIM8_UP_IRQHandler TIM8_UP_TIM13_IRQHandler |
||
| 6769 | #define TIM13_IRQHandler TIM8_UP_TIM13_IRQHandler |
||
| 6770 | #define CEC_IRQHandler USBWakeUp_IRQHandler |
||
| 6771 | #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler |
||
| 6772 | #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler |
||
| 6773 | #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler |
||
| 6774 | #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler |
||
| 6775 | #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler |
||
| 6776 | |||
| 6777 | |||
| 6778 | /** |
||
| 6779 | * @} |
||
| 6780 | */ |
||
| 6781 | |||
| 6782 | /** |
||
| 6783 | * @} |
||
| 6784 | */ |
||
| 6785 | |||
| 6786 | |||
| 6787 | #ifdef __cplusplus |
||
| 6788 | } |
||
| 6789 | #endif /* __cplusplus */ |
||
| 6790 | |||
| 6791 | #endif /* __STM32F103xG_H */ |
||
| 6792 | |||
| 6793 | |||
| 6794 | |||
| 6795 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |