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/**

  ******************************************************************************

  * @file    stm32f103xe.h

  * @author  MCD Application Team

  * @version V4.1.0

  * @date    29-April-2016

  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.

  *          This file contains all the peripheral register's definitions, bits

  *          definitions and memory mapping for STM32F1xx devices.            

  *            

  *          This file contains:

  *           - Data structures and the address mapping for all peripherals

  *           - Peripheral's registers declarations and bits definition

  *           - Macros to access peripheral’s registers hardware

  *  

  ******************************************************************************

  * @attention

  *

  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

  *

  * Redistribution and use in source and binary forms, with or without modification,

  * are permitted provided that the following conditions are met:

  *   1. Redistributions of source code must retain the above copyright notice,

  *      this list of conditions and the following disclaimer.

  *   2. Redistributions in binary form must reproduce the above copyright notice,

  *      this list of conditions and the following disclaimer in the documentation

  *      and/or other materials provided with the distribution.

  *   3. Neither the name of STMicroelectronics nor the names of its contributors

  *      may be used to endorse or promote products derived from this software

  *      without specific prior written permission.

  *

  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  *

  ******************************************************************************

  */

/** @addtogroup CMSIS

  * @{

  */

/** @addtogroup stm32f103xe

  * @{

  */

#ifndef __STM32F103xE_H

#define __STM32F103xE_H

#ifdef __cplusplus

 extern "C" {

#endif 

/** @addtogroup Configuration_section_for_CMSIS

  * @{

  */

/**

  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals

 */

 #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

/**

  * @}

  */

/** @addtogroup Peripheral_interrupt_number_definition

  * @{

  */

/**

 * @brief STM32F10x Interrupt Number Definition, according to the selected device

 *        in @ref Library_configuration_section

 */

 /*!< Interrupt Number Definition */

typedef enum

{

/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/

  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */

  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                     */

  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */

  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */

  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */

  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */

  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */

  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */

  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */

/******  STM32 specific Interrupt Numbers *********************************************************/

  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */

  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */

  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */

  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */

  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */

  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */

  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */

  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */

  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */

  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */

  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */

  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */

  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */

  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */

  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */

  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */

  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */

  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */

  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */

  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */

  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */

  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */

  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */

  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */

  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */

  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */

  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */

  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */

  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */

  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */

  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */

  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */

  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */

  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */

  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */

  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */

  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */

  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */

  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */

  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */

  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */

  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */

  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */

  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */

  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */

  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */

  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */

  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */

  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */

  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */

  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */

  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */

  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */

  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */

  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */

  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */

  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */

  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */

  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */

  DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */

} IRQn_Type;

/**

  * @}

  */

#include "core_cm3.h"

#include "system_stm32f1xx.h"

#include <stdint.h>

/** @addtogroup Peripheral_registers_structures

  * @{

  */  

/**

  * @brief Analog to Digital Converter  

  */

typedef struct

{

  __IO uint32_t SR;

  __IO uint32_t CR1;

  __IO uint32_t CR2;

  __IO uint32_t SMPR1;

  __IO uint32_t SMPR2;

  __IO uint32_t JOFR1;

  __IO uint32_t JOFR2;

  __IO uint32_t JOFR3;

  __IO uint32_t JOFR4;

  __IO uint32_t HTR;

  __IO uint32_t LTR;

  __IO uint32_t SQR1;

  __IO uint32_t SQR2;

  __IO uint32_t SQR3;

  __IO uint32_t JSQR;

  __IO uint32_t JDR1;

  __IO uint32_t JDR2;

  __IO uint32_t JDR3;

  __IO uint32_t JDR4;

  __IO uint32_t DR;

} ADC_TypeDef;

typedef struct

{

  __IO uint32_t SR;               /*!< ADC status register,    used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address         */

  __IO uint32_t CR1;              /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04  */

  __IO uint32_t CR2;              /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08  */

  uint32_t  RESERVED[16];

  __IO uint32_t DR;               /*!< ADC data register,      used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C  */

} ADC_Common_TypeDef;

/**

  * @brief Backup Registers  

  */

typedef struct

{

  uint32_t  RESERVED0;

  __IO uint32_t DR1;

  __IO uint32_t DR2;

  __IO uint32_t DR3;

  __IO uint32_t DR4;

  __IO uint32_t DR5;

  __IO uint32_t DR6;

  __IO uint32_t DR7;

  __IO uint32_t DR8;

  __IO uint32_t DR9;

  __IO uint32_t DR10;

  __IO uint32_t RTCCR;

  __IO uint32_t CR;

  __IO uint32_t CSR;

  uint32_t  RESERVED13[2];

  __IO uint32_t DR11;

  __IO uint32_t DR12;

  __IO uint32_t DR13;

  __IO uint32_t DR14;

  __IO uint32_t DR15;

  __IO uint32_t DR16;

  __IO uint32_t DR17;

  __IO uint32_t DR18;

  __IO uint32_t DR19;

  __IO uint32_t DR20;

  __IO uint32_t DR21;

  __IO uint32_t DR22;

  __IO uint32_t DR23;

  __IO uint32_t DR24;

  __IO uint32_t DR25;

  __IO uint32_t DR26;

  __IO uint32_t DR27;

  __IO uint32_t DR28;

  __IO uint32_t DR29;

  __IO uint32_t DR30;

  __IO uint32_t DR31;

  __IO uint32_t DR32;

  __IO uint32_t DR33;

  __IO uint32_t DR34;

  __IO uint32_t DR35;

  __IO uint32_t DR36;

  __IO uint32_t DR37;

  __IO uint32_t DR38;

  __IO uint32_t DR39;

  __IO uint32_t DR40;

  __IO uint32_t DR41;

  __IO uint32_t DR42;

} BKP_TypeDef;

/**

  * @brief Controller Area Network TxMailBox

  */

typedef struct

{

  __IO uint32_t TIR;

  __IO uint32_t TDTR;

  __IO uint32_t TDLR;

  __IO uint32_t TDHR;

} CAN_TxMailBox_TypeDef;

/**

  * @brief Controller Area Network FIFOMailBox

  */

typedef struct

{

  __IO uint32_t RIR;

  __IO uint32_t RDTR;

  __IO uint32_t RDLR;

  __IO uint32_t RDHR;

} CAN_FIFOMailBox_TypeDef;

/**

  * @brief Controller Area Network FilterRegister

  */

typedef struct

{

  __IO uint32_t FR1;

  __IO uint32_t FR2;

} CAN_FilterRegister_TypeDef;

/**

  * @brief Controller Area Network

  */

typedef struct

{

  __IO uint32_t MCR;

  __IO uint32_t MSR;

  __IO uint32_t TSR;

  __IO uint32_t RF0R;

  __IO uint32_t RF1R;

  __IO uint32_t IER;

  __IO uint32_t ESR;

  __IO uint32_t BTR;

  uint32_t  RESERVED0[88];

  CAN_TxMailBox_TypeDef sTxMailBox[3];

  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];

  uint32_t  RESERVED1[12];

  __IO uint32_t FMR;

  __IO uint32_t FM1R;

  uint32_t  RESERVED2;

  __IO uint32_t FS1R;

  uint32_t  RESERVED3;

  __IO uint32_t FFA1R;

  uint32_t  RESERVED4;

  __IO uint32_t FA1R;

  uint32_t  RESERVED5[8];

  CAN_FilterRegister_TypeDef sFilterRegister[14];

} CAN_TypeDef;

/**

  * @brief CRC calculation unit

  */

typedef struct

{

  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */

  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */

  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */

  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */  

  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */

} CRC_TypeDef;

/**

  * @brief Digital to Analog Converter

  */

typedef struct

{

  __IO uint32_t CR;

  __IO uint32_t SWTRIGR;

  __IO uint32_t DHR12R1;

  __IO uint32_t DHR12L1;

  __IO uint32_t DHR8R1;

  __IO uint32_t DHR12R2;

  __IO uint32_t DHR12L2;

  __IO uint32_t DHR8R2;

  __IO uint32_t DHR12RD;

  __IO uint32_t DHR12LD;

  __IO uint32_t DHR8RD;

  __IO uint32_t DOR1;

  __IO uint32_t DOR2;

} DAC_TypeDef;

/**

  * @brief Debug MCU

  */

typedef struct

{

  __IO uint32_t IDCODE;

  __IO uint32_t CR;

}DBGMCU_TypeDef;

/**

  * @brief DMA Controller

  */

typedef struct

{

  __IO uint32_t CCR;

  __IO uint32_t CNDTR;

  __IO uint32_t CPAR;

  __IO uint32_t CMAR;

} DMA_Channel_TypeDef;

typedef struct

{

  __IO uint32_t ISR;

  __IO uint32_t IFCR;

} DMA_TypeDef;

/**

  * @brief External Interrupt/Event Controller

  */

typedef struct

{

  __IO uint32_t IMR;

  __IO uint32_t EMR;

  __IO uint32_t RTSR;

  __IO uint32_t FTSR;

  __IO uint32_t SWIER;

  __IO uint32_t PR;

} EXTI_TypeDef;

/**

  * @brief FLASH Registers

  */

typedef struct

{

  __IO uint32_t ACR;

  __IO uint32_t KEYR;

  __IO uint32_t OPTKEYR;

  __IO uint32_t SR;

  __IO uint32_t CR;

  __IO uint32_t AR;

  __IO uint32_t RESERVED;

  __IO uint32_t OBR;

  __IO uint32_t WRPR;

} FLASH_TypeDef;

/**

  * @brief Option Bytes Registers

  */

typedef struct

{

  __IO uint16_t RDP;

  __IO uint16_t USER;

  __IO uint16_t Data0;

  __IO uint16_t Data1;

  __IO uint16_t WRP0;

  __IO uint16_t WRP1;

  __IO uint16_t WRP2;

  __IO uint16_t WRP3;

} OB_TypeDef;

/**

  * @brief Flexible Static Memory Controller

  */

typedef struct

{

  __IO uint32_t BTCR[8];  

} FSMC_Bank1_TypeDef;

/**

  * @brief Flexible Static Memory Controller Bank1E

  */

typedef struct

{

  __IO uint32_t BWTR[7];

} FSMC_Bank1E_TypeDef;

/**

  * @brief Flexible Static Memory Controller Bank2

  */

typedef struct

{

  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */

  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */

  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */

  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

} FSMC_Bank2_3_TypeDef;  

/**

  * @brief Flexible Static Memory Controller Bank4

  */

typedef struct

{

  __IO uint32_t PCR4;

  __IO uint32_t SR4;

  __IO uint32_t PMEM4;

  __IO uint32_t PATT4;

  __IO uint32_t PIO4;

} FSMC_Bank4_TypeDef;

/**

  * @brief General Purpose I/O

  */

typedef struct

{

  __IO uint32_t CRL;

  __IO uint32_t CRH;

  __IO uint32_t IDR;

  __IO uint32_t ODR;

  __IO uint32_t BSRR;

  __IO uint32_t BRR;

  __IO uint32_t LCKR;

} GPIO_TypeDef;

/**

  * @brief Alternate Function I/O

  */

typedef struct

{

  __IO uint32_t EVCR;

  __IO uint32_t MAPR;

  __IO uint32_t EXTICR[4];

  uint32_t RESERVED0;

  __IO uint32_t MAPR2;  

} AFIO_TypeDef;

/**

  * @brief Inter Integrated Circuit Interface

  */

typedef struct

{

  __IO uint32_t CR1;

  __IO uint32_t CR2;

  __IO uint32_t OAR1;

  __IO uint32_t OAR2;

  __IO uint32_t DR;

  __IO uint32_t SR1;

  __IO uint32_t SR2;

  __IO uint32_t CCR;

  __IO uint32_t TRISE;

} I2C_TypeDef;

/**

  * @brief Independent WATCHDOG

  */

typedef struct

{

  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */

  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */

  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */

  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */

} IWDG_TypeDef;

/**

  * @brief Power Control

  */

typedef struct

{

  __IO uint32_t CR;

  __IO uint32_t CSR;

} PWR_TypeDef;

/**

  * @brief Reset and Clock Control

  */

typedef struct

{

  __IO uint32_t CR;

  __IO uint32_t CFGR;

  __IO uint32_t CIR;

  __IO uint32_t APB2RSTR;

  __IO uint32_t APB1RSTR;

  __IO uint32_t AHBENR;

  __IO uint32_t APB2ENR;

  __IO uint32_t APB1ENR;

  __IO uint32_t BDCR;

  __IO uint32_t CSR;

} RCC_TypeDef;

/**

  * @brief Real-Time Clock

  */

typedef struct

{

  __IO uint32_t CRH;

  __IO uint32_t CRL;

  __IO uint32_t PRLH;

  __IO uint32_t PRLL;

  __IO uint32_t DIVH;

  __IO uint32_t DIVL;

  __IO uint32_t CNTH;

  __IO uint32_t CNTL;

  __IO uint32_t ALRH;

  __IO uint32_t ALRL;

} RTC_TypeDef;

/**

  * @brief SD host Interface

  */

typedef struct

{

  __IO uint32_t POWER;

  __IO uint32_t CLKCR;

  __IO uint32_t ARG;

  __IO uint32_t CMD;

  __I uint32_t RESPCMD;

  __I uint32_t RESP1;

  __I uint32_t RESP2;

  __I uint32_t RESP3;

  __I uint32_t RESP4;

  __IO uint32_t DTIMER;

  __IO uint32_t DLEN;

  __IO uint32_t DCTRL;

  __I uint32_t DCOUNT;

  __I uint32_t STA;

  __IO uint32_t ICR;

  __IO uint32_t MASK;

  uint32_t  RESERVED0[2];

  __I uint32_t FIFOCNT;

  uint32_t  RESERVED1[13];

  __IO uint32_t FIFO;

} SDIO_TypeDef;

/**

  * @brief Serial Peripheral Interface

  */

typedef struct

{

  __IO uint32_t CR1;

  __IO uint32_t CR2;

  __IO uint32_t SR;

  __IO uint32_t DR;

  __IO uint32_t CRCPR;

  __IO uint32_t RXCRCR;

  __IO uint32_t TXCRCR;

  __IO uint32_t I2SCFGR;

  __IO uint32_t I2SPR;

} SPI_TypeDef;

/**

  * @brief TIM Timers

  */

typedef struct

{

  __IO uint32_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */

  __IO uint32_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */

  __IO uint32_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */

  __IO uint32_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */

  __IO uint32_t SR;              /*!< TIM status register,                         Address offset: 0x10 */

  __IO uint32_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */

  __IO uint32_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */

  __IO uint32_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */

  __IO uint32_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */

  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */

  __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */

  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */

  __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */

  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */

  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */

  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */

  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */

  __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */

  __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */

  __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */

  __IO uint32_t OR;              /*!< TIM option register,                         Address offset: 0x50 */

}TIM_TypeDef;

/**

  * @brief Universal Synchronous Asynchronous Receiver Transmitter

  */

typedef struct

{

  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */

  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */

  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */

  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */

  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */

  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */

  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */

} USART_TypeDef;

/**

  * @brief Universal Serial Bus Full Speed Device

  */

typedef struct

{

  __IO uint16_t EP0R;                 /*!< USB Endpoint 0 register,                   Address offset: 0x00 */

  __IO uint16_t RESERVED0;            /*!< Reserved */    

  __IO uint16_t EP1R;                 /*!< USB Endpoint 1 register,                   Address offset: 0x04 */

  __IO uint16_t RESERVED1;            /*!< Reserved */      

  __IO uint16_t EP2R;                 /*!< USB Endpoint 2 register,                   Address offset: 0x08 */

  __IO uint16_t RESERVED2;            /*!< Reserved */      

  __IO uint16_t EP3R;                 /*!< USB Endpoint 3 register,                   Address offset: 0x0C */

  __IO uint16_t RESERVED3;            /*!< Reserved */      

  __IO uint16_t EP4R;                 /*!< USB Endpoint 4 register,                   Address offset: 0x10 */

  __IO uint16_t RESERVED4;            /*!< Reserved */      

  __IO uint16_t EP5R;                 /*!< USB Endpoint 5 register,                   Address offset: 0x14 */

  __IO uint16_t RESERVED5;            /*!< Reserved */      

  __IO uint16_t EP6R;                 /*!< USB Endpoint 6 register,                   Address offset: 0x18 */

  __IO uint16_t RESERVED6;            /*!< Reserved */      

  __IO uint16_t EP7R;                 /*!< USB Endpoint 7 register,                   Address offset: 0x1C */

  __IO uint16_t RESERVED7[17];        /*!< Reserved */    

  __IO uint16_t CNTR;                 /*!< Control register,                          Address offset: 0x40 */

  __IO uint16_t RESERVED8;            /*!< Reserved */      

  __IO uint16_t ISTR;                 /*!< Interrupt status register,                 Address offset: 0x44 */

  __IO uint16_t RESERVED9;            /*!< Reserved */      

  __IO uint16_t FNR;                  /*!< Frame number register,                     Address offset: 0x48 */

  __IO uint16_t RESERVEDA;            /*!< Reserved */      

  __IO uint16_t DADDR;                /*!< Device address register,                   Address offset: 0x4C */

  __IO uint16_t RESERVEDB;            /*!< Reserved */      

  __IO uint16_t BTABLE;               /*!< Buffer Table address register,             Address offset: 0x50 */

  __IO uint16_t RESERVEDC;            /*!< Reserved */      

} USB_TypeDef;

/**

  * @brief Window WATCHDOG

  */

typedef struct

{

  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

} WWDG_TypeDef;

/**

  * @}

  */

/** @addtogroup Peripheral_memory_map

  * @{

  */

#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

#define FLASH_BANK1_END       ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */

#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

#define FSMC_BASE             ((uint32_t)0x60000000) /*!< FSMC base address */

#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */

/*!< Peripheral memory map */

#define APB1PERIPH_BASE       PERIPH_BASE

#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)

#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)

#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)

#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)

#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)

#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)

#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)

#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)

#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)

#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)

#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)

#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)

#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)

#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)

#define SDIO_BASE             (PERIPH_BASE + 0x18000)

#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)

#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)

#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)

#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)

#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)

#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

#define FSMC_BANK1            (FSMC_BASE)               /*!< FSMC Bank1 base address */

#define FSMC_BANK1_1          (FSMC_BANK1)              /*!< FSMC Bank1_1 base address */

#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */

#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */

#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */

#define FSMC_BANK2            (FSMC_BASE + 0x10000000)  /*!< FSMC Bank2 base address */

#define FSMC_BANK3            (FSMC_BASE + 0x20000000)  /*!< FSMC Bank3 base address */

#define FSMC_BANK4            (FSMC_BASE + 0x30000000)  /*!< FSMC Bank4 base address */

#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000)    /*!< FSMC Bank1 registers base address */

#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104)    /*!< FSMC Bank1E registers base address */

#define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x0060)    /*!< FSMC Bank2/Bank3 registers base address */

#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x00A0)    /*!< FSMC Bank4 registers base address */

#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

/* USB device FS */

#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */

#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */

/**

  * @}

  */

/** @addtogroup Peripheral_declaration

  * @{

  */  

#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

#define RTC                 ((RTC_TypeDef *) RTC_BASE)

#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

#define USART2              ((USART_TypeDef *) USART2_BASE)

#define USART3              ((USART_TypeDef *) USART3_BASE)

#define UART4               ((USART_TypeDef *) UART4_BASE)

#define UART5               ((USART_TypeDef *) UART5_BASE)

#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

#define USB                 ((USB_TypeDef *) USB_BASE)

#define CAN1                ((CAN_TypeDef *) CAN1_BASE)

#define BKP                 ((BKP_TypeDef *) BKP_BASE)

#define PWR                 ((PWR_TypeDef *) PWR_BASE)

#define DAC                 ((DAC_TypeDef *) DAC_BASE)

#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_BASE)

#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

#define USART1              ((USART_TypeDef *) USART1_BASE)

#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

#define RCC                 ((RCC_TypeDef *) RCC_BASE)

#define CRC                 ((CRC_TypeDef *) CRC_BASE)

#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

#define OB                  ((OB_TypeDef *) OB_BASE)

#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)

#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)

#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)

#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)

#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)