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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f103xe.h
		4	* @author MCD Application Team
		5	* @version V4.0.1
		6	* @date 31-July-2015
		7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		8	* This file contains all the peripheral register's definitions, bits
		9	* definitions and memory mapping for STM32F1xx devices.
		10	*
		11	* This file contains:
		12	* - Data structures and the address mapping for all peripherals
		13	* - Peripheral's registers declarations and bits definition
		14	* - Macros to access peripheral�s registers hardware
		15	*
		16	******************************************************************************
		17	* @attention
		18	*
		19	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
		20	*
		21	* Redistribution and use in source and binary forms, with or without modification,
		22	* are permitted provided that the following conditions are met:
		23	* 1. Redistributions of source code must retain the above copyright notice,
		24	* this list of conditions and the following disclaimer.
		25	* 2. Redistributions in binary form must reproduce the above copyright notice,
		26	* this list of conditions and the following disclaimer in the documentation
		27	* and/or other materials provided with the distribution.
		28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		29	* may be used to endorse or promote products derived from this software
		30	* without specific prior written permission.
		31	*
		32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		42	*
		43	******************************************************************************
		44	*/
		45
		46
		47	/** @addtogroup CMSIS
		48	* @{
		49	*/
		50
		51	/** @addtogroup stm32f103xe
		52	* @{
		53	*/
		54
		55	#ifndef __STM32F103xE_H
		56	#define __STM32F103xE_H
		57
		58	#ifdef __cplusplus
		59	extern "C" {
		60	#endif
		61
		62	/** @addtogroup Configuration_section_for_CMSIS
		63	* @{
		64	*/
		65	/**
		66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		67	*/
		68	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
		69	#define __CM3_REV 0x0200 /!< Core Revision r2p0 /
		70	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
		71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
		72
		73	/**
		74	* @}
		75	*/
		76
		77	/** @addtogroup Peripheral_interrupt_number_definition
		78	* @{
		79	*/
		80
		81	/**
		82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
		83	* in @ref Library_configuration_section
		84	*/
		85
		86	/!< Interrupt Number Definition /
		87	typedef enum
		88	{
		89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
		90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
		91	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		92	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		93	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		94	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		95	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		96	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		97	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		98
		99	/**** STM32 specific Interrupt Numbers *******************************************************/
		100	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		101	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		102	TAMPER_IRQn = 2, /!< Tamper Interrupt /
		103	RTC_IRQn = 3, /!< RTC global Interrupt /
		104	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		105	RCC_IRQn = 5, /!< RCC global Interrupt /
		106	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		107	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		108	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		109	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		110	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		111	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		112	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		113	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		114	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		115	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		116	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		117	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		118	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
		119	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
		120	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
		121	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
		122	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
		123	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		124	TIM1_BRK_IRQn = 24, /!< TIM1 Break Interrupt /
		125	TIM1_UP_IRQn = 25, /!< TIM1 Update Interrupt /
		126	TIM1_TRG_COM_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt /
		127	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
		128	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		129	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		130	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		131	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		132	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		133	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		134	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		135	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		136	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		137	USART1_IRQn = 37, /!< USART1 global Interrupt /
		138	USART2_IRQn = 38, /!< USART2 global Interrupt /
		139	USART3_IRQn = 39, /!< USART3 global Interrupt /
		140	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		141	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		142	USBWakeUp_IRQn = 42, /!< USB Device WakeUp from suspend through EXTI Line Interrupt /
		143	TIM8_BRK_IRQn = 43, /!< TIM8 Break Interrupt /
		144	TIM8_UP_IRQn = 44, /!< TIM8 Update Interrupt /
		145	TIM8_TRG_COM_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt /
		146	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
		147	ADC3_IRQn = 47, /!< ADC3 global Interrupt /
		148	FSMC_IRQn = 48, /!< FSMC global Interrupt /
		149	SDIO_IRQn = 49, /!< SDIO global Interrupt /
		150	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
		151	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
		152	UART4_IRQn = 52, /!< UART4 global Interrupt /
		153	UART5_IRQn = 53, /!< UART5 global Interrupt /
		154	TIM6_IRQn = 54, /!< TIM6 global Interrupt /
		155	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
		156	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
		157	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
		158	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
		159	DMA2_Channel4_5_IRQn = 59, /!< DMA2 Channel 4 and Channel 5 global Interrupt /
		160	} IRQn_Type;
		161
		162
		163	/**
		164	* @}
		165	*/
		166
		167	#include "core_cm3.h"
		168	#include "system_stm32f1xx.h"
		169	#include <stdint.h>
		170
		171	/** @addtogroup Peripheral_registers_structures
		172	* @{
		173	*/
		174
		175	/**
		176	* @brief Analog to Digital Converter
		177	*/
		178
		179	typedef struct
		180	{
		181	__IO uint32_t SR;
		182	__IO uint32_t CR1;
		183	__IO uint32_t CR2;
		184	__IO uint32_t SMPR1;
		185	__IO uint32_t SMPR2;
		186	__IO uint32_t JOFR1;
		187	__IO uint32_t JOFR2;
		188	__IO uint32_t JOFR3;
		189	__IO uint32_t JOFR4;
		190	__IO uint32_t HTR;
		191	__IO uint32_t LTR;
		192	__IO uint32_t SQR1;
		193	__IO uint32_t SQR2;
		194	__IO uint32_t SQR3;
		195	__IO uint32_t JSQR;
		196	__IO uint32_t JDR1;
		197	__IO uint32_t JDR2;
		198	__IO uint32_t JDR3;
		199	__IO uint32_t JDR4;
		200	__IO uint32_t DR;
		201	} ADC_TypeDef;
		202
		203	/**
		204	* @brief Backup Registers
		205	*/
		206
		207	typedef struct
		208	{
		209	uint32_t RESERVED0;
		210	__IO uint32_t DR1;
		211	__IO uint32_t DR2;
		212	__IO uint32_t DR3;
		213	__IO uint32_t DR4;
		214	__IO uint32_t DR5;
		215	__IO uint32_t DR6;
		216	__IO uint32_t DR7;
		217	__IO uint32_t DR8;
		218	__IO uint32_t DR9;
		219	__IO uint32_t DR10;
		220	__IO uint32_t RTCCR;
		221	__IO uint32_t CR;
		222	__IO uint32_t CSR;
		223	uint32_t RESERVED13[2];
		224	__IO uint32_t DR11;
		225	__IO uint32_t DR12;
		226	__IO uint32_t DR13;
		227	__IO uint32_t DR14;
		228	__IO uint32_t DR15;
		229	__IO uint32_t DR16;
		230	__IO uint32_t DR17;
		231	__IO uint32_t DR18;
		232	__IO uint32_t DR19;
		233	__IO uint32_t DR20;
		234	__IO uint32_t DR21;
		235	__IO uint32_t DR22;
		236	__IO uint32_t DR23;
		237	__IO uint32_t DR24;
		238	__IO uint32_t DR25;
		239	__IO uint32_t DR26;
		240	__IO uint32_t DR27;
		241	__IO uint32_t DR28;
		242	__IO uint32_t DR29;
		243	__IO uint32_t DR30;
		244	__IO uint32_t DR31;
		245	__IO uint32_t DR32;
		246	__IO uint32_t DR33;
		247	__IO uint32_t DR34;
		248	__IO uint32_t DR35;
		249	__IO uint32_t DR36;
		250	__IO uint32_t DR37;
		251	__IO uint32_t DR38;
		252	__IO uint32_t DR39;
		253	__IO uint32_t DR40;
		254	__IO uint32_t DR41;
		255	__IO uint32_t DR42;
		256	} BKP_TypeDef;
		257
		258	/**
		259	* @brief Controller Area Network TxMailBox
		260	*/
		261
		262	typedef struct
		263	{
		264	__IO uint32_t TIR;
		265	__IO uint32_t TDTR;
		266	__IO uint32_t TDLR;
		267	__IO uint32_t TDHR;
		268	} CAN_TxMailBox_TypeDef;
		269
		270	/**
		271	* @brief Controller Area Network FIFOMailBox
		272	*/
		273
		274	typedef struct
		275	{
		276	__IO uint32_t RIR;
		277	__IO uint32_t RDTR;
		278	__IO uint32_t RDLR;
		279	__IO uint32_t RDHR;
		280	} CAN_FIFOMailBox_TypeDef;
		281
		282	/**
		283	* @brief Controller Area Network FilterRegister
		284	*/
		285
		286	typedef struct
		287	{
		288	__IO uint32_t FR1;
		289	__IO uint32_t FR2;
		290	} CAN_FilterRegister_TypeDef;
		291
		292	/**
		293	* @brief Controller Area Network
		294	*/
		295
		296	typedef struct
		297	{
		298	__IO uint32_t MCR;
		299	__IO uint32_t MSR;
		300	__IO uint32_t TSR;
		301	__IO uint32_t RF0R;
		302	__IO uint32_t RF1R;
		303	__IO uint32_t IER;
		304	__IO uint32_t ESR;
		305	__IO uint32_t BTR;
		306	uint32_t RESERVED0[88];
		307	CAN_TxMailBox_TypeDef sTxMailBox[3];
		308	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
		309	uint32_t RESERVED1[12];
		310	__IO uint32_t FMR;
		311	__IO uint32_t FM1R;
		312	uint32_t RESERVED2;
		313	__IO uint32_t FS1R;
		314	uint32_t RESERVED3;
		315	__IO uint32_t FFA1R;
		316	uint32_t RESERVED4;
		317	__IO uint32_t FA1R;
		318	uint32_t RESERVED5[8];
		319	CAN_FilterRegister_TypeDef sFilterRegister[14];
		320	} CAN_TypeDef;
		321
		322	/**
		323	* @brief CRC calculation unit
		324	*/
		325
		326	typedef struct
		327	{
		328	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		329	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		330	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		331	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		332	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		333	} CRC_TypeDef;
		334
		335	/**
		336	* @brief Digital to Analog Converter
		337	*/
		338
		339	typedef struct
		340	{
		341	__IO uint32_t CR;
		342	__IO uint32_t SWTRIGR;
		343	__IO uint32_t DHR12R1;
		344	__IO uint32_t DHR12L1;
		345	__IO uint32_t DHR8R1;
		346	__IO uint32_t DHR12R2;
		347	__IO uint32_t DHR12L2;
		348	__IO uint32_t DHR8R2;
		349	__IO uint32_t DHR12RD;
		350	__IO uint32_t DHR12LD;
		351	__IO uint32_t DHR8RD;
		352	__IO uint32_t DOR1;
		353	__IO uint32_t DOR2;
		354	} DAC_TypeDef;
		355
		356	/**
		357	* @brief Debug MCU
		358	*/
		359
		360	typedef struct
		361	{
		362	__IO uint32_t IDCODE;
		363	__IO uint32_t CR;
		364	}DBGMCU_TypeDef;
		365
		366	/**
		367	* @brief DMA Controller
		368	*/
		369
		370	typedef struct
		371	{
		372	__IO uint32_t CCR;
		373	__IO uint32_t CNDTR;
		374	__IO uint32_t CPAR;
		375	__IO uint32_t CMAR;
		376	} DMA_Channel_TypeDef;
		377
		378	typedef struct
		379	{
		380	__IO uint32_t ISR;
		381	__IO uint32_t IFCR;
		382	} DMA_TypeDef;
		383
		384
		385
		386	/**
		387	* @brief External Interrupt/Event Controller
		388	*/
		389
		390	typedef struct
		391	{
		392	__IO uint32_t IMR;
		393	__IO uint32_t EMR;
		394	__IO uint32_t RTSR;
		395	__IO uint32_t FTSR;
		396	__IO uint32_t SWIER;
		397	__IO uint32_t PR;
		398	} EXTI_TypeDef;
		399
		400	/**
		401	* @brief FLASH Registers
		402	*/
		403
		404	typedef struct
		405	{
		406	__IO uint32_t ACR;
		407	__IO uint32_t KEYR;
		408	__IO uint32_t OPTKEYR;
		409	__IO uint32_t SR;
		410	__IO uint32_t CR;
		411	__IO uint32_t AR;
		412	__IO uint32_t RESERVED;
		413	__IO uint32_t OBR;
		414	__IO uint32_t WRPR;
		415	} FLASH_TypeDef;
		416
		417	/**
		418	* @brief Option Bytes Registers
		419	*/
		420
		421	typedef struct
		422	{
		423	__IO uint16_t RDP;
		424	__IO uint16_t USER;
		425	__IO uint16_t Data0;
		426	__IO uint16_t Data1;
		427	__IO uint16_t WRP0;
		428	__IO uint16_t WRP1;
		429	__IO uint16_t WRP2;
		430	__IO uint16_t WRP3;
		431	} OB_TypeDef;
		432
		433	/**
		434	* @brief Flexible Static Memory Controller
		435	*/
		436
		437	typedef struct
		438	{
		439	__IO uint32_t BTCR[8];
		440	} FSMC_Bank1_TypeDef;
		441
		442	/**
		443	* @brief Flexible Static Memory Controller Bank1E
		444	*/
		445
		446	typedef struct
		447	{
		448	__IO uint32_t BWTR[7];
		449	} FSMC_Bank1E_TypeDef;
		450
		451	/**
		452	* @brief Flexible Static Memory Controller Bank2
		453	*/
		454
		455	typedef struct
		456	{
		457	__IO uint32_t PCR2; /!< NAND Flash control register 2, Address offset: 0x60 /
		458	__IO uint32_t SR2; /!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 /
		459	__IO uint32_t PMEM2; /!< NAND Flash Common memory space timing register 2, Address offset: 0x68 /
		460	__IO uint32_t PATT2; /!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C /
		461	uint32_t RESERVED0; /!< Reserved, 0x70 /
		462	__IO uint32_t ECCR2; /!< NAND Flash ECC result registers 2, Address offset: 0x74 /
		463	uint32_t RESERVED1; /!< Reserved, 0x78 /
		464	uint32_t RESERVED2; /!< Reserved, 0x7C /
		465	__IO uint32_t PCR3; /!< NAND Flash control register 3, Address offset: 0x80 /
		466	__IO uint32_t SR3; /!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 /
		467	__IO uint32_t PMEM3; /!< NAND Flash Common memory space timing register 3, Address offset: 0x88 /
		468	__IO uint32_t PATT3; /!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C /
		469	uint32_t RESERVED3; /!< Reserved, 0x90 /
		470	__IO uint32_t ECCR3; /!< NAND Flash ECC result registers 3, Address offset: 0x94 /
		471	} FSMC_Bank2_3_TypeDef;
		472
		473	/**
		474	* @brief Flexible Static Memory Controller Bank4
		475	*/
		476
		477	typedef struct
		478	{
		479	__IO uint32_t PCR4;
		480	__IO uint32_t SR4;
		481	__IO uint32_t PMEM4;
		482	__IO uint32_t PATT4;
		483	__IO uint32_t PIO4;
		484	} FSMC_Bank4_TypeDef;
		485
		486	/**
		487	* @brief General Purpose I/O
		488	*/
		489
		490	typedef struct
		491	{
		492	__IO uint32_t CRL;
		493	__IO uint32_t CRH;
		494	__IO uint32_t IDR;
		495	__IO uint32_t ODR;
		496	__IO uint32_t BSRR;
		497	__IO uint32_t BRR;
		498	__IO uint32_t LCKR;
		499	} GPIO_TypeDef;
		500
		501	/**
		502	* @brief Alternate Function I/O
		503	*/
		504
		505	typedef struct
		506	{
		507	__IO uint32_t EVCR;
		508	__IO uint32_t MAPR;
		509	__IO uint32_t EXTICR[4];
		510	uint32_t RESERVED0;
		511	__IO uint32_t MAPR2;
		512	} AFIO_TypeDef;
		513	/**
		514	* @brief Inter Integrated Circuit Interface
		515	*/
		516
		517	typedef struct
		518	{
		519	__IO uint32_t CR1;
		520	__IO uint32_t CR2;
		521	__IO uint32_t OAR1;
		522	__IO uint32_t OAR2;
		523	__IO uint32_t DR;
		524	__IO uint32_t SR1;
		525	__IO uint32_t SR2;
		526	__IO uint32_t CCR;
		527	__IO uint32_t TRISE;
		528	} I2C_TypeDef;
		529
		530	/**
		531	* @brief Independent WATCHDOG
		532	*/
		533
		534	typedef struct
		535	{
		536	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		537	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		538	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		539	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		540	} IWDG_TypeDef;
		541
		542	/**
		543	* @brief Power Control
		544	*/
		545
		546	typedef struct
		547	{
		548	__IO uint32_t CR;
		549	__IO uint32_t CSR;
		550	} PWR_TypeDef;
		551
		552	/**
		553	* @brief Reset and Clock Control
		554	*/
		555
		556	typedef struct
		557	{
		558	__IO uint32_t CR;
		559	__IO uint32_t CFGR;
		560	__IO uint32_t CIR;
		561	__IO uint32_t APB2RSTR;
		562	__IO uint32_t APB1RSTR;
		563	__IO uint32_t AHBENR;
		564	__IO uint32_t APB2ENR;
		565	__IO uint32_t APB1ENR;
		566	__IO uint32_t BDCR;
		567	__IO uint32_t CSR;
		568
		569
		570	} RCC_TypeDef;
		571
		572	/**
		573	* @brief Real-Time Clock
		574	*/
		575
		576	typedef struct
		577	{
		578	__IO uint32_t CRH;
		579	__IO uint32_t CRL;
		580	__IO uint32_t PRLH;
		581	__IO uint32_t PRLL;
		582	__IO uint32_t DIVH;
		583	__IO uint32_t DIVL;
		584	__IO uint32_t CNTH;
		585	__IO uint32_t CNTL;
		586	__IO uint32_t ALRH;
		587	__IO uint32_t ALRL;
		588	} RTC_TypeDef;
		589
		590	/**
		591	* @brief SD host Interface
		592	*/
		593
		594	typedef struct
		595	{
		596	__IO uint32_t POWER;
		597	__IO uint32_t CLKCR;
		598	__IO uint32_t ARG;
		599	__IO uint32_t CMD;
		600	__I uint32_t RESPCMD;
		601	__I uint32_t RESP1;
		602	__I uint32_t RESP2;
		603	__I uint32_t RESP3;
		604	__I uint32_t RESP4;
		605	__IO uint32_t DTIMER;
		606	__IO uint32_t DLEN;
		607	__IO uint32_t DCTRL;
		608	__I uint32_t DCOUNT;
		609	__I uint32_t STA;
		610	__IO uint32_t ICR;
		611	__IO uint32_t MASK;
		612	uint32_t RESERVED0[2];
		613	__I uint32_t FIFOCNT;
		614	uint32_t RESERVED1[13];
		615	__IO uint32_t FIFO;
		616	} SDIO_TypeDef;
		617
		618	/**
		619	* @brief Serial Peripheral Interface
		620	*/
		621
		622	typedef struct
		623	{
		624	__IO uint32_t CR1;
		625	__IO uint32_t CR2;
		626	__IO uint32_t SR;
		627	__IO uint32_t DR;
		628	__IO uint32_t CRCPR;
		629	__IO uint32_t RXCRCR;
		630	__IO uint32_t TXCRCR;
		631	__IO uint32_t I2SCFGR;
		632	__IO uint32_t I2SPR;
		633	} SPI_TypeDef;
		634
		635	/**
		636	* @brief TIM Timers
		637	*/
		638	typedef struct
		639	{
		640	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		641	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		642	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		643	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		644	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		645	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		646	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		647	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		648	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		649	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		650	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		651	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		652	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
		653	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		654	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		655	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		656	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		657	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
		658	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		659	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
		660	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		661	}TIM_TypeDef;
		662
		663
		664	/**
		665	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		666	*/
		667
		668	typedef struct
		669	{
		670	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		671	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		672	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		673	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		674	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		675	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		676	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		677	} USART_TypeDef;
		678
		679	/**
		680	* @brief Universal Serial Bus Full Speed Device
		681	*/
		682
		683	typedef struct
		684	{
		685	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
		686	__IO uint16_t RESERVED0; /!< Reserved /
		687	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
		688	__IO uint16_t RESERVED1; /!< Reserved /
		689	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
		690	__IO uint16_t RESERVED2; /!< Reserved /
		691	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
		692	__IO uint16_t RESERVED3; /!< Reserved /
		693	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
		694	__IO uint16_t RESERVED4; /!< Reserved /
		695	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
		696	__IO uint16_t RESERVED5; /!< Reserved /
		697	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
		698	__IO uint16_t RESERVED6; /!< Reserved /
		699	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
		700	__IO uint16_t RESERVED7[17]; /!< Reserved /
		701	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
		702	__IO uint16_t RESERVED8; /!< Reserved /
		703	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
		704	__IO uint16_t RESERVED9; /!< Reserved /
		705	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
		706	__IO uint16_t RESERVEDA; /!< Reserved /
		707	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
		708	__IO uint16_t RESERVEDB; /!< Reserved /
		709	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
		710	__IO uint16_t RESERVEDC; /!< Reserved /
		711	} USB_TypeDef;
		712
		713
		714	/**
		715	* @brief Window WATCHDOG
		716	*/
		717
		718	typedef struct
		719	{
		720	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		721	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		722	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		723	} WWDG_TypeDef;
		724
		725	/**
		726	* @}
		727	*/
		728
		729	/** @addtogroup Peripheral_memory_map
		730	* @{
		731	*/
		732
		733
		734	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
		735	#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /!< FLASH END address of bank1 /
		736	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
		737	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
		738
		739	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
		740	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
		741
		742	#define FSMC_BASE ((uint32_t)0x60000000) /!< FSMC base address /
		743	#define FSMC_R_BASE ((uint32_t)0xA0000000) /!< FSMC registers base address /
		744
		745	/!< Peripheral memory map /
		746	#define APB1PERIPH_BASE PERIPH_BASE
		747	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
		748	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
		749
		750	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
		751	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
		752	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
		753	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
		754	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
		755	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
		756	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
		757	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
		758	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
		759	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
		760	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
		761	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
		762	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
		763	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
		764	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
		765	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
		766	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
		767	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
		768	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
		769	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
		770	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
		771	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
		772	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
		773	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
		774	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
		775	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
		776	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
		777	#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
		778	#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
		779	#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
		780	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
		781	#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
		782	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
		783	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
		784	#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
		785	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
		786	#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
		787
		788	#define SDIO_BASE (PERIPH_BASE + 0x18000)
		789
		790	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
		791	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
		792	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
		793	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
		794	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
		795	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
		796	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
		797	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
		798	#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
		799	#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
		800	#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
		801	#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
		802	#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
		803	#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
		804	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
		805	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
		806
		807	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
		808	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
		809
		810
		811	#define FSMC_BANK1 (FSMC_BASE) /!< FSMC Bank1 base address /
		812	#define FSMC_BANK1_1 (FSMC_BANK1) /!< FSMC Bank1_1 base address /
		813	#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /!< FSMC Bank1_2 base address /
		814	#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /!< FSMC Bank1_3 base address /
		815	#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /!< FSMC Bank1_4 base address /
		816
		817	#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /!< FSMC Bank2 base address /
		818	#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /!< FSMC Bank3 base address /
		819	#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /!< FSMC Bank4 base address /
		820
		821	#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /!< FSMC Bank1 registers base address /
		822	#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /!< FSMC Bank1E registers base address /
		823	#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /!< FSMC Bank2/Bank3 registers base address /
		824	#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /!< FSMC Bank4 registers base address /
		825
		826	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
		827
		828	/* USB device FS */
		829	#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
		830	#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
		831
		832
		833	/**
		834	* @}
		835	*/
		836
		837	/** @addtogroup Peripheral_declaration
		838	* @{
		839	*/
		840
		841	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
		842	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
		843	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
		844	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
		845	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
		846	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
		847	#define RTC ((RTC_TypeDef *) RTC_BASE)
		848	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
		849	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
		850	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
		851	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
		852	#define USART2 ((USART_TypeDef *) USART2_BASE)
		853	#define USART3 ((USART_TypeDef *) USART3_BASE)
		854	#define UART4 ((USART_TypeDef *) UART4_BASE)
		855	#define UART5 ((USART_TypeDef *) UART5_BASE)
		856	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
		857	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
		858	#define USB ((USB_TypeDef *) USB_BASE)
		859	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
		860	#define BKP ((BKP_TypeDef *) BKP_BASE)
		861	#define PWR ((PWR_TypeDef *) PWR_BASE)
		862	#define DAC ((DAC_TypeDef *) DAC_BASE)
		863	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
		864	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
		865	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
		866	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
		867	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
		868	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
		869	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
		870	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
		871	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
		872	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
		873	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
		874	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
		875	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
		876	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
		877	#define USART1 ((USART_TypeDef *) USART1_BASE)
		878	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
		879	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
		880	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
		881	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
		882	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
		883	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
		884	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
		885	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
		886	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
		887	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
		888	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
		889	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
		890	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
		891	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
		892	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
		893	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
		894	#define RCC ((RCC_TypeDef *) RCC_BASE)
		895	#define CRC ((CRC_TypeDef *) CRC_BASE)
		896	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
		897	#define OB ((OB_TypeDef *) OB_BASE)
		898	#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
		899	#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
		900	#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)
		901	#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)
		902	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
		903
		904
		905	/**
		906	* @}
		907	*/
		908
		909	/** @addtogroup Exported_constants
		910	* @{
		911	*/
		912
		913	/** @addtogroup Peripheral_Registers_Bits_Definition
		914	* @{
		915	*/
		916
		917	/******************************************************************************/
		918	/* Peripheral Registers_Bits_Definition */
		919	/******************************************************************************/
		920
		921	/******************************************************************************/
		922	/* */
		923	/* CRC calculation unit (CRC) */
		924	/* */
		925	/******************************************************************************/
		926
		927	/***************** Bit definition for CRC_DR register *******************/
		928	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
		929
		930	/***************** Bit definition for CRC_IDR register ******************/
		931	#define CRC_IDR_IDR ((uint32_t)0xFF) /!< General-purpose 8-bit data register bits /
		932
		933	/****************** Bit definition for CRC_CR register ******************/
		934	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
		935
		936	/******************************************************************************/
		937	/* */
		938	/* Power Control */
		939	/* */
		940	/******************************************************************************/
		941
		942	/****************** Bit definition for PWR_CR register ******************/
		943	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
		944	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
		945	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
		946	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
		947	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
		948
		949	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
		950	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
		951	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
		952	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
		953
		954	/!< PVD level configuration /
		955	#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /!< PVD level 2.2V /
		956	#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /!< PVD level 2.3V /
		957	#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /!< PVD level 2.4V /
		958	#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /!< PVD level 2.5V /
		959	#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /!< PVD level 2.6V /
		960	#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /!< PVD level 2.7V /
		961	#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /!< PVD level 2.8V /
		962	#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /!< PVD level 2.9V /
		963
		964	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
		965
		966
		967	/***************** Bit definition for PWR_CSR register ******************/
		968	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
		969	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
		970	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
		971	#define PWR_CSR_EWUP ((uint32_t)0x00000100) /!< Enable WKUP pin /
		972
		973	/******************************************************************************/
		974	/* */
		975	/* Backup registers */
		976	/* */
		977	/******************************************************************************/
		978
		979	/***************** Bit definition for BKP_DR1 register ******************/
		980	#define BKP_DR1_D ((uint32_t)0x0000FFFF) /!< Backup data /
		981
		982	/***************** Bit definition for BKP_DR2 register ******************/
		983	#define BKP_DR2_D ((uint32_t)0x0000FFFF) /!< Backup data /
		984
		985	/***************** Bit definition for BKP_DR3 register ******************/
		986	#define BKP_DR3_D ((uint32_t)0x0000FFFF) /!< Backup data /
		987
		988	/***************** Bit definition for BKP_DR4 register ******************/
		989	#define BKP_DR4_D ((uint32_t)0x0000FFFF) /!< Backup data /
		990
		991	/***************** Bit definition for BKP_DR5 register ******************/
		992	#define BKP_DR5_D ((uint32_t)0x0000FFFF) /!< Backup data /
		993
		994	/***************** Bit definition for BKP_DR6 register ******************/
		995	#define BKP_DR6_D ((uint32_t)0x0000FFFF) /!< Backup data /
		996
		997	/***************** Bit definition for BKP_DR7 register ******************/
		998	#define BKP_DR7_D ((uint32_t)0x0000FFFF) /!< Backup data /
		999
		1000	/***************** Bit definition for BKP_DR8 register ******************/
		1001	#define BKP_DR8_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1002
		1003	/***************** Bit definition for BKP_DR9 register ******************/
		1004	#define BKP_DR9_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1005
		1006	/***************** Bit definition for BKP_DR10 register *****************/
		1007	#define BKP_DR10_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1008
		1009	/***************** Bit definition for BKP_DR11 register *****************/
		1010	#define BKP_DR11_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1011
		1012	/***************** Bit definition for BKP_DR12 register *****************/
		1013	#define BKP_DR12_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1014
		1015	/***************** Bit definition for BKP_DR13 register *****************/
		1016	#define BKP_DR13_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1017
		1018	/***************** Bit definition for BKP_DR14 register *****************/
		1019	#define BKP_DR14_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1020
		1021	/***************** Bit definition for BKP_DR15 register *****************/
		1022	#define BKP_DR15_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1023
		1024	/***************** Bit definition for BKP_DR16 register *****************/
		1025	#define BKP_DR16_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1026
		1027	/***************** Bit definition for BKP_DR17 register *****************/
		1028	#define BKP_DR17_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1029
		1030	/**************** Bit definition for BKP_DR18 register ******************/
		1031	#define BKP_DR18_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1032
		1033	/***************** Bit definition for BKP_DR19 register *****************/
		1034	#define BKP_DR19_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1035
		1036	/***************** Bit definition for BKP_DR20 register *****************/
		1037	#define BKP_DR20_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1038
		1039	/***************** Bit definition for BKP_DR21 register *****************/
		1040	#define BKP_DR21_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1041
		1042	/***************** Bit definition for BKP_DR22 register *****************/
		1043	#define BKP_DR22_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1044
		1045	/***************** Bit definition for BKP_DR23 register *****************/
		1046	#define BKP_DR23_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1047
		1048	/***************** Bit definition for BKP_DR24 register *****************/
		1049	#define BKP_DR24_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1050
		1051	/***************** Bit definition for BKP_DR25 register *****************/
		1052	#define BKP_DR25_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1053
		1054	/***************** Bit definition for BKP_DR26 register *****************/
		1055	#define BKP_DR26_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1056
		1057	/***************** Bit definition for BKP_DR27 register *****************/
		1058	#define BKP_DR27_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1059
		1060	/***************** Bit definition for BKP_DR28 register *****************/
		1061	#define BKP_DR28_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1062
		1063	/***************** Bit definition for BKP_DR29 register *****************/
		1064	#define BKP_DR29_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1065
		1066	/***************** Bit definition for BKP_DR30 register *****************/
		1067	#define BKP_DR30_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1068
		1069	/***************** Bit definition for BKP_DR31 register *****************/
		1070	#define BKP_DR31_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1071
		1072	/***************** Bit definition for BKP_DR32 register *****************/
		1073	#define BKP_DR32_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1074
		1075	/***************** Bit definition for BKP_DR33 register *****************/
		1076	#define BKP_DR33_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1077
		1078	/***************** Bit definition for BKP_DR34 register *****************/
		1079	#define BKP_DR34_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1080
		1081	/***************** Bit definition for BKP_DR35 register *****************/
		1082	#define BKP_DR35_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1083
		1084	/***************** Bit definition for BKP_DR36 register *****************/
		1085	#define BKP_DR36_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1086
		1087	/***************** Bit definition for BKP_DR37 register *****************/
		1088	#define BKP_DR37_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1089
		1090	/***************** Bit definition for BKP_DR38 register *****************/
		1091	#define BKP_DR38_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1092
		1093	/***************** Bit definition for BKP_DR39 register *****************/
		1094	#define BKP_DR39_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1095
		1096	/***************** Bit definition for BKP_DR40 register *****************/
		1097	#define BKP_DR40_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1098
		1099	/***************** Bit definition for BKP_DR41 register *****************/
		1100	#define BKP_DR41_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1101
		1102	/***************** Bit definition for BKP_DR42 register *****************/
		1103	#define BKP_DR42_D ((uint32_t)0x0000FFFF) /!< Backup data /
		1104
		1105	#define RTC_BKP_NUMBER 42
		1106
		1107	/**************** Bit definition for BKP_RTCCR register *****************/
		1108	#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /!< Calibration value /
		1109	#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /!< Calibration Clock Output /
		1110	#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /!< Alarm or Second Output Enable /
		1111	#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /!< Alarm or Second Output Selection /
		1112
		1113	/****************** Bit definition for BKP_CR register ******************/
		1114	#define BKP_CR_TPE ((uint32_t)0x00000001) /!< TAMPER pin enable /
		1115	#define BKP_CR_TPAL ((uint32_t)0x00000002) /!< TAMPER pin active level /
		1116
		1117	/***************** Bit definition for BKP_CSR register ******************/
		1118	#define BKP_CSR_CTE ((uint32_t)0x00000001) /!< Clear Tamper event /
		1119	#define BKP_CSR_CTI ((uint32_t)0x00000002) /!< Clear Tamper Interrupt /
		1120	#define BKP_CSR_TPIE ((uint32_t)0x00000004) /!< TAMPER Pin interrupt enable /
		1121	#define BKP_CSR_TEF ((uint32_t)0x00000100) /!< Tamper Event Flag /
		1122	#define BKP_CSR_TIF ((uint32_t)0x00000200) /!< Tamper Interrupt Flag /
		1123
		1124	/******************************************************************************/
		1125	/* */
		1126	/* Reset and Clock Control */
		1127	/* */
		1128	/******************************************************************************/
		1129
		1130	/****************** Bit definition for RCC_CR register ******************/
		1131	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
		1132	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
		1133	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
		1134	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
		1135	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
		1136	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
		1137	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
		1138	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
		1139	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
		1140	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
		1141
		1142
		1143	/***************** Bit definition for RCC_CFGR register *****************/
		1144	/!< SW configuration /
		1145	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
		1146	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1147	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1148
		1149	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
		1150	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
		1151	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
		1152
		1153	/!< SWS configuration /
		1154	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
		1155	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1156	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1157
		1158	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
		1159	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
		1160	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
		1161
		1162	/!< HPRE configuration /
		1163	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
		1164	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1165	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1166	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
		1167	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
		1168
		1169	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
		1170	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
		1171	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
		1172	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
		1173	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
		1174	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
		1175	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
		1176	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
		1177	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
		1178
		1179	/!< PPRE1 configuration /
		1180	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
		1181	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1182	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1183	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
		1184
		1185	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		1186	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
		1187	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
		1188	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
		1189	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
		1190
		1191	/!< PPRE2 configuration /
		1192	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
		1193	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
		1194	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
		1195	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
		1196
		1197	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		1198	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
		1199	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
		1200	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
		1201	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
		1202
		1203	/!< ADCPPRE configuration /
		1204	#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /!< ADCPRE[1:0] bits (ADC prescaler) /
		1205	#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1206	#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1207
		1208	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
		1209	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
		1210	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
		1211	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
		1212
		1213	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
		1214
		1215	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
		1216
		1217	/!< PLLMUL configuration /
		1218	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
		1219	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1220	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1221	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
		1222	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
		1223
		1224	#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /!< HSE clock not divided for PLL entry /
		1225	#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /!< HSE clock divided by 2 for PLL entry /
		1226
		1227	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
		1228	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
		1229	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
		1230	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
		1231	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
		1232	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
		1233	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
		1234	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
		1235	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
		1236	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
		1237	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
		1238	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
		1239	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
		1240	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
		1241	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
		1242	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB Device prescaler /
		1243
		1244	/!< MCO configuration /
		1245	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
		1246	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1247	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1248	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
		1249
		1250	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1251	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
		1252	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
		1253	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
		1254	#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
		1255
		1256	/!<*************** Bit definition for RCC_CIR register ******************/
		1257	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
		1258	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
		1259	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
		1260	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
		1261	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
		1262	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
		1263	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
		1264	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
		1265	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
		1266	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
		1267	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
		1268	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
		1269	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
		1270	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
		1271	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
		1272	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
		1273	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
		1274
		1275
		1276	/*************** Bit definition for RCC_APB2RSTR register ***************/
		1277	#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /!< Alternate Function I/O reset /
		1278	#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /!< I/O port A reset /
		1279	#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /!< I/O port B reset /
		1280	#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /!< I/O port C reset /
		1281	#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /!< I/O port D reset /
		1282	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC 1 interface reset /
		1283
		1284	#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /!< ADC 2 interface reset /
		1285
		1286	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 Timer reset /
		1287	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI 1 reset /
		1288	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
		1289
		1290
		1291	#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /!< I/O port E reset /
		1292
		1293	#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /!< I/O port F reset /
		1294	#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /!< I/O port G reset /
		1295	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /!< TIM8 Timer reset /
		1296	#define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /!< ADC3 interface reset /
		1297
		1298
		1299
		1300	/*************** Bit definition for RCC_APB1RSTR register ***************/
		1301	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
		1302	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
		1303	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
		1304	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
		1305	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
		1306
		1307	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /!< CAN1 reset /
		1308
		1309	#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /!< Backup interface reset /
		1310	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
		1311
		1312	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
		1313	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
		1314	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
		1315	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
		1316
		1317	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB Device reset /
		1318
		1319	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /!< Timer 5 reset /
		1320	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
		1321	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
		1322	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI 3 reset /
		1323	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /!< UART 4 reset /
		1324	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /!< UART 5 reset /
		1325
		1326
		1327
		1328
		1329	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC interface reset /
		1330
		1331	/**************** Bit definition for RCC_AHBENR register ****************/
		1332	#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /!< DMA1 clock enable /
		1333	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
		1334	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
		1335	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
		1336
		1337	#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /!< DMA2 clock enable /
		1338
		1339	#define RCC_AHBENR_FSMCEN ((uint32_t)0x00000100) /!< FSMC clock enable /
		1340	#define RCC_AHBENR_SDIOEN ((uint32_t)0x00000400) /!< SDIO clock enable /
		1341
		1342
		1343	/**************** Bit definition for RCC_APB2ENR register ***************/
		1344	#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /!< Alternate Function I/O clock enable /
		1345	#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /!< I/O port A clock enable /
		1346	#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /!< I/O port B clock enable /
		1347	#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /!< I/O port C clock enable /
		1348	#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /!< I/O port D clock enable /
		1349	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC 1 interface clock enable /
		1350
		1351	#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /!< ADC 2 interface clock enable /
		1352
		1353	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 Timer clock enable /
		1354	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI 1 clock enable /
		1355	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
		1356
		1357
		1358	#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /!< I/O port E clock enable /
		1359
		1360	#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /!< I/O port F clock enable /
		1361	#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /!< I/O port G clock enable /
		1362	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /!< TIM8 Timer clock enable /
		1363	#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /!< DMA1 clock enable /
		1364
		1365
		1366
		1367	/*************** Bit definition for RCC_APB1ENR register ****************/
		1368	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
		1369	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
		1370	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
		1371	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
		1372	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
		1373
		1374	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /!< CAN1 clock enable /
		1375
		1376	#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /!< Backup interface clock enable /
		1377	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
		1378
		1379	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
		1380	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
		1381	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
		1382	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
		1383
		1384	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB Device clock enable /
		1385
		1386	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /!< Timer 5 clock enable /
		1387	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
		1388	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
		1389	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI 3 clock enable /
		1390	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /!< UART 4 clock enable /
		1391	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /!< UART 5 clock enable /
		1392
		1393
		1394
		1395
		1396	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC interface clock enable /
		1397
		1398	/***************** Bit definition for RCC_BDCR register *****************/
		1399	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
		1400	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
		1401	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
		1402
		1403	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
		1404	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1405	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1406
		1407	/!< RTC congiguration /
		1408	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1409	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
		1410	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
		1411	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
		1412
		1413	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
		1414	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
		1415
		1416	/***************** Bit definition for RCC_CSR register ******************/
		1417	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
		1418	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
		1419	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
		1420	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
		1421	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
		1422	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
		1423	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
		1424	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
		1425	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
		1426
		1427
		1428
		1429	/******************************************************************************/
		1430	/* */
		1431	/* General Purpose and Alternate Function I/O */
		1432	/* */
		1433	/******************************************************************************/
		1434
		1435	/***************** Bit definition for GPIO_CRL register *****************/
		1436	#define GPIO_CRL_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
		1437
		1438	#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
		1439	#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1440	#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1441
		1442	#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
		1443	#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1444	#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1445
		1446	#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
		1447	#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1448	#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1449
		1450	#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
		1451	#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /!< Bit 0 /
		1452	#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /!< Bit 1 /
		1453
		1454	#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
		1455	#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /!< Bit 0 /
		1456	#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /!< Bit 1 /
		1457
		1458	#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
		1459	#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /!< Bit 0 /
		1460	#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /!< Bit 1 /
		1461
		1462	#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
		1463	#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1464	#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1465
		1466	#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
		1467	#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /!< Bit 0 /
		1468	#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /!< Bit 1 /
		1469
		1470	#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
		1471
		1472	#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
		1473	#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1474	#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1475
		1476	#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
		1477	#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1478	#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1479
		1480	#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
		1481	#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1482	#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1483
		1484	#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
		1485	#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1486	#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1487
		1488	#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
		1489	#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1490	#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1491
		1492	#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
		1493	#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /!< Bit 0 /
		1494	#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /!< Bit 1 /
		1495
		1496	#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
		1497	#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /!< Bit 0 /
		1498	#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /!< Bit 1 /
		1499
		1500	#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
		1501	#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /!< Bit 0 /
		1502	#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /!< Bit 1 /
		1503
		1504	/***************** Bit definition for GPIO_CRH register *****************/
		1505	#define GPIO_CRH_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
		1506
		1507	#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
		1508	#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1509	#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1510
		1511	#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
		1512	#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1513	#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1514
		1515	#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
		1516	#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1517	#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1518
		1519	#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
		1520	#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /!< Bit 0 /
		1521	#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /!< Bit 1 /
		1522
		1523	#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
		1524	#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /!< Bit 0 /
		1525	#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /!< Bit 1 /
		1526
		1527	#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
		1528	#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /!< Bit 0 /
		1529	#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /!< Bit 1 /
		1530
		1531	#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
		1532	#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1533	#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1534
		1535	#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
		1536	#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /!< Bit 0 /
		1537	#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /!< Bit 1 /
		1538
		1539	#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
		1540
		1541	#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
		1542	#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1543	#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1544
		1545	#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
		1546	#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1547	#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1548
		1549	#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
		1550	#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1551	#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1552
		1553	#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
		1554	#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1555	#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1556
		1557	#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
		1558	#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1559	#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1560
		1561	#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
		1562	#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /!< Bit 0 /
		1563	#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /!< Bit 1 /
		1564
		1565	#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
		1566	#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /!< Bit 0 /
		1567	#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /!< Bit 1 /
		1568
		1569	#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
		1570	#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /!< Bit 0 /
		1571	#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /!< Bit 1 /
		1572
		1573	/!<*************** Bit definition for GPIO_IDR register *****************/
		1574	#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /!< Port input data, bit 0 /
		1575	#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /!< Port input data, bit 1 /
		1576	#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /!< Port input data, bit 2 /
		1577	#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /!< Port input data, bit 3 /
		1578	#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /!< Port input data, bit 4 /
		1579	#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /!< Port input data, bit 5 /
		1580	#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /!< Port input data, bit 6 /
		1581	#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /!< Port input data, bit 7 /
		1582	#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /!< Port input data, bit 8 /
		1583	#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /!< Port input data, bit 9 /
		1584	#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /!< Port input data, bit 10 /
		1585	#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /!< Port input data, bit 11 /
		1586	#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /!< Port input data, bit 12 /
		1587	#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /!< Port input data, bit 13 /
		1588	#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /!< Port input data, bit 14 /
		1589	#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /!< Port input data, bit 15 /
		1590
		1591	/***************** Bit definition for GPIO_ODR register *****************/
		1592	#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /!< Port output data, bit 0 /
		1593	#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /!< Port output data, bit 1 /
		1594	#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /!< Port output data, bit 2 /
		1595	#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /!< Port output data, bit 3 /
		1596	#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /!< Port output data, bit 4 /
		1597	#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /!< Port output data, bit 5 /
		1598	#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /!< Port output data, bit 6 /
		1599	#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /!< Port output data, bit 7 /
		1600	#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /!< Port output data, bit 8 /
		1601	#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /!< Port output data, bit 9 /
		1602	#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /!< Port output data, bit 10 /
		1603	#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /!< Port output data, bit 11 /
		1604	#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /!< Port output data, bit 12 /
		1605	#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /!< Port output data, bit 13 /
		1606	#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /!< Port output data, bit 14 /
		1607	#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /!< Port output data, bit 15 /
		1608
		1609	/**************** Bit definition for GPIO_BSRR register *****************/
		1610	#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /!< Port x Set bit 0 /
		1611	#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /!< Port x Set bit 1 /
		1612	#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /!< Port x Set bit 2 /
		1613	#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /!< Port x Set bit 3 /
		1614	#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /!< Port x Set bit 4 /
		1615	#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /!< Port x Set bit 5 /
		1616	#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /!< Port x Set bit 6 /
		1617	#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /!< Port x Set bit 7 /
		1618	#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /!< Port x Set bit 8 /
		1619	#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /!< Port x Set bit 9 /
		1620	#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /!< Port x Set bit 10 /
		1621	#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /!< Port x Set bit 11 /
		1622	#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /!< Port x Set bit 12 /
		1623	#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /!< Port x Set bit 13 /
		1624	#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /!< Port x Set bit 14 /
		1625	#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /!< Port x Set bit 15 /
		1626
		1627	#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /!< Port x Reset bit 0 /
		1628	#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /!< Port x Reset bit 1 /
		1629	#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /!< Port x Reset bit 2 /
		1630	#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /!< Port x Reset bit 3 /
		1631	#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /!< Port x Reset bit 4 /
		1632	#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /!< Port x Reset bit 5 /
		1633	#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /!< Port x Reset bit 6 /
		1634	#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /!< Port x Reset bit 7 /
		1635	#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /!< Port x Reset bit 8 /
		1636	#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /!< Port x Reset bit 9 /
		1637	#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /!< Port x Reset bit 10 /
		1638	#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /!< Port x Reset bit 11 /
		1639	#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /!< Port x Reset bit 12 /
		1640	#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /!< Port x Reset bit 13 /
		1641	#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /!< Port x Reset bit 14 /
		1642	#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /!< Port x Reset bit 15 /
		1643
		1644	/***************** Bit definition for GPIO_BRR register *****************/
		1645	#define GPIO_BRR_BR0 ((uint32_t)0x0001) /!< Port x Reset bit 0 /
		1646	#define GPIO_BRR_BR1 ((uint32_t)0x0002) /!< Port x Reset bit 1 /
		1647	#define GPIO_BRR_BR2 ((uint32_t)0x0004) /!< Port x Reset bit 2 /
		1648	#define GPIO_BRR_BR3 ((uint32_t)0x0008) /!< Port x Reset bit 3 /
		1649	#define GPIO_BRR_BR4 ((uint32_t)0x0010) /!< Port x Reset bit 4 /
		1650	#define GPIO_BRR_BR5 ((uint32_t)0x0020) /!< Port x Reset bit 5 /
		1651	#define GPIO_BRR_BR6 ((uint32_t)0x0040) /!< Port x Reset bit 6 /
		1652	#define GPIO_BRR_BR7 ((uint32_t)0x0080) /!< Port x Reset bit 7 /
		1653	#define GPIO_BRR_BR8 ((uint32_t)0x0100) /!< Port x Reset bit 8 /
		1654	#define GPIO_BRR_BR9 ((uint32_t)0x0200) /!< Port x Reset bit 9 /
		1655	#define GPIO_BRR_BR10 ((uint32_t)0x0400) /!< Port x Reset bit 10 /
		1656	#define GPIO_BRR_BR11 ((uint32_t)0x0800) /!< Port x Reset bit 11 /
		1657	#define GPIO_BRR_BR12 ((uint32_t)0x1000) /!< Port x Reset bit 12 /
		1658	#define GPIO_BRR_BR13 ((uint32_t)0x2000) /!< Port x Reset bit 13 /
		1659	#define GPIO_BRR_BR14 ((uint32_t)0x4000) /!< Port x Reset bit 14 /
		1660	#define GPIO_BRR_BR15 ((uint32_t)0x8000) /!< Port x Reset bit 15 /
		1661
		1662	/**************** Bit definition for GPIO_LCKR register *****************/
		1663	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /!< Port x Lock bit 0 /
		1664	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /!< Port x Lock bit 1 /
		1665	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /!< Port x Lock bit 2 /
		1666	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /!< Port x Lock bit 3 /
		1667	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /!< Port x Lock bit 4 /
		1668	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /!< Port x Lock bit 5 /
		1669	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /!< Port x Lock bit 6 /
		1670	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /!< Port x Lock bit 7 /
		1671	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /!< Port x Lock bit 8 /
		1672	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /!< Port x Lock bit 9 /
		1673	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /!< Port x Lock bit 10 /
		1674	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /!< Port x Lock bit 11 /
		1675	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /!< Port x Lock bit 12 /
		1676	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /!< Port x Lock bit 13 /
		1677	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /!< Port x Lock bit 14 /
		1678	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /!< Port x Lock bit 15 /
		1679	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /!< Lock key /
		1680
		1681	/----------------------------------------------------------------------------/
		1682
		1683	/**************** Bit definition for AFIO_EVCR register *****************/
		1684	#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /!< PIN[3:0] bits (Pin selection) /
		1685	#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1686	#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1687	#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /!< Bit 2 /
		1688	#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /!< Bit 3 /
		1689
		1690	/!< PIN configuration /
		1691	#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /!< Pin 0 selected /
		1692	#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /!< Pin 1 selected /
		1693	#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /!< Pin 2 selected /
		1694	#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /!< Pin 3 selected /
		1695	#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /!< Pin 4 selected /
		1696	#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /!< Pin 5 selected /
		1697	#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /!< Pin 6 selected /
		1698	#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /!< Pin 7 selected /
		1699	#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /!< Pin 8 selected /
		1700	#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /!< Pin 9 selected /
		1701	#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /!< Pin 10 selected /
		1702	#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /!< Pin 11 selected /
		1703	#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /!< Pin 12 selected /
		1704	#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /!< Pin 13 selected /
		1705	#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /!< Pin 14 selected /
		1706	#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /!< Pin 15 selected /
		1707
		1708	#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /!< PORT[2:0] bits (Port selection) /
		1709	#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1710	#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1711	#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /!< Bit 2 /
		1712
		1713	/!< PORT configuration /
		1714	#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /!< Port A selected /
		1715	#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /!< Port B selected /
		1716	#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /!< Port C selected /
		1717	#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /!< Port D selected /
		1718	#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /!< Port E selected /
		1719
		1720	#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /!< Event Output Enable /
		1721
		1722	/**************** Bit definition for AFIO_MAPR register *****************/
		1723	#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /!< SPI1 remapping /
		1724	#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /!< I2C1 remapping /
		1725	#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /!< USART1 remapping /
		1726	#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /!< USART2 remapping /
		1727
		1728	#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /!< USART3_REMAP[1:0] bits (USART3 remapping) /
		1729	#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1730	#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1731
		1732	/* USART3_REMAP configuration */
		1733	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
		1734	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
		1735	#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
		1736
		1737	#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
		1738	#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1739	#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1740
		1741	/!< TIM1_REMAP configuration /
		1742	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
		1743	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
		1744	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
		1745
		1746	#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
		1747	#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1748	#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1749
		1750	/!< TIM2_REMAP configuration /
		1751	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
		1752	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
		1753	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
		1754	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
		1755
		1756	#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
		1757	#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1758	#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1759
		1760	/!< TIM3_REMAP configuration /
		1761	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
		1762	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
		1763	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
		1764
		1765	#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /!< TIM4_REMAP bit (TIM4 remapping) /
		1766
		1767	#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) /
		1768	#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /!< Bit 0 /
		1769	#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /!< Bit 1 /
		1770
		1771	/!< CAN_REMAP configuration /
		1772	#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /!< CANRX mapped to PA11, CANTX mapped to PA12 /
		1773	#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /!< CANRX mapped to PB8, CANTX mapped to PB9 /
		1774	#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /!< CANRX mapped to PD0, CANTX mapped to PD1 /
		1775
		1776	#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
		1777	#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /!< TIM5 Channel4 Internal Remap /
		1778	#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /!< ADC 1 External Trigger Injected Conversion remapping /
		1779	#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /!< ADC 1 External Trigger Regular Conversion remapping /
		1780	#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /!< ADC 2 External Trigger Injected Conversion remapping /
		1781	#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /!< ADC 2 External Trigger Regular Conversion remapping /
		1782
		1783	/!< SWJ_CFG configuration /
		1784	#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
		1785	#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1786	#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1787	#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /!< Bit 2 /
		1788
		1789	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
		1790	#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
		1791	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /!< JTAG-DP Disabled and SW-DP Enabled /
		1792	#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /!< JTAG-DP Disabled and SW-DP Disabled /
		1793
		1794
		1795	/*************** Bit definition for AFIO_EXTICR1 register ***************/
		1796	#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
		1797	#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
		1798	#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
		1799	#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
		1800
		1801	/!< EXTI0 configuration /
		1802	#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
		1803	#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
		1804	#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
		1805	#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
		1806	#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
		1807	#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
		1808	#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /!< PG[0] pin /
		1809
		1810	/!< EXTI1 configuration /
		1811	#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
		1812	#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
		1813	#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
		1814	#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
		1815	#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
		1816	#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
		1817	#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /!< PG[1] pin /
		1818
		1819	/!< EXTI2 configuration /
		1820	#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
		1821	#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
		1822	#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
		1823	#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
		1824	#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
		1825	#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
		1826	#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /!< PG[2] pin /
		1827
		1828	/!< EXTI3 configuration /
		1829	#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
		1830	#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
		1831	#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
		1832	#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
		1833	#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
		1834	#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
		1835	#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /!< PG[3] pin /
		1836
		1837	/*************** Bit definition for AFIO_EXTICR2 register ***************/
		1838	#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
		1839	#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
		1840	#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
		1841	#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
		1842
		1843	/!< EXTI4 configuration /
		1844	#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
		1845	#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
		1846	#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
		1847	#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
		1848	#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
		1849	#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
		1850	#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /!< PG[4] pin /
		1851
		1852	/* EXTI5 configuration */
		1853	#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
		1854	#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
		1855	#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
		1856	#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
		1857	#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
		1858	#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
		1859	#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /!< PG[5] pin /
		1860
		1861	/!< EXTI6 configuration /
		1862	#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
		1863	#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
		1864	#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
		1865	#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
		1866	#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
		1867	#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
		1868	#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /!< PG[6] pin /
		1869
		1870	/!< EXTI7 configuration /
		1871	#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
		1872	#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
		1873	#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
		1874	#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
		1875	#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
		1876	#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
		1877	#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /!< PG[7] pin /
		1878
		1879	/*************** Bit definition for AFIO_EXTICR3 register ***************/
		1880	#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
		1881	#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
		1882	#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
		1883	#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
		1884
		1885	/!< EXTI8 configuration /
		1886	#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
		1887	#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
		1888	#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
		1889	#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
		1890	#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
		1891	#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!< PF[8] pin /
		1892	#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /!< PG[8] pin /
		1893
		1894	/!< EXTI9 configuration /
		1895	#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
		1896	#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
		1897	#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
		1898	#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
		1899	#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
		1900	#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
		1901	#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /!< PG[9] pin /
		1902
		1903	/!< EXTI10 configuration /
		1904	#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
		1905	#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
		1906	#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
		1907	#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
		1908	#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PE[10] pin /
		1909	#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
		1910	#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /!< PG[10] pin /
		1911
		1912	/!< EXTI11 configuration /
		1913	#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
		1914	#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
		1915	#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
		1916	#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
		1917	#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
		1918	#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!< PF[11] pin /
		1919	#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /!< PG[11] pin /
		1920
		1921	/*************** Bit definition for AFIO_EXTICR4 register ***************/
		1922	#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
		1923	#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
		1924	#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
		1925	#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
		1926
		1927	/* EXTI12 configuration */
		1928	#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
		1929	#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
		1930	#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
		1931	#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
		1932	#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
		1933	#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!< PF[12] pin /
		1934	#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /!< PG[12] pin /
		1935
		1936	/* EXTI13 configuration */
		1937	#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
		1938	#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
		1939	#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
		1940	#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
		1941	#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
		1942	#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!< PF[13] pin /
		1943	#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /!< PG[13] pin /
		1944
		1945	/!< EXTI14 configuration /
		1946	#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
		1947	#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
		1948	#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
		1949	#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
		1950	#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
		1951	#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!< PF[14] pin /
		1952	#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /!< PG[14] pin /
		1953
		1954	/!< EXTI15 configuration /
		1955	#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
		1956	#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
		1957	#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
		1958	#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
		1959	#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
		1960	#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!< PF[15] pin /
		1961	#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /!< PG[15] pin /
		1962
		1963	/**************** Bit definition for AFIO_MAPR2 register ****************/
		1964
		1965
		1966	#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /!< FSMC NADV remapping /
		1967
		1968	/******************************************************************************/
		1969	/* */
		1970	/* SystemTick */
		1971	/* */
		1972	/******************************************************************************/
		1973
		1974	/*************** Bit definition for SysTick_CTRL register ***************/
		1975	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
		1976	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
		1977	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
		1978	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
		1979
		1980	/*************** Bit definition for SysTick_LOAD register ***************/
		1981	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
		1982
		1983	/*************** Bit definition for SysTick_VAL register ****************/
		1984	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
		1985
		1986	/*************** Bit definition for SysTick_CALIB register **************/
		1987	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
		1988	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
		1989	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
		1990
		1991	/******************************************************************************/
		1992	/* */
		1993	/* Nested Vectored Interrupt Controller */
		1994	/* */
		1995	/******************************************************************************/
		1996
		1997	/**************** Bit definition for NVIC_ISER register *****************/
		1998	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
		1999	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
		2000	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
		2001	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
		2002	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
		2003	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
		2004	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
		2005	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
		2006	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
		2007	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
		2008	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
		2009	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
		2010	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
		2011	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
		2012	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
		2013	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
		2014	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
		2015	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
		2016	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
		2017	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
		2018	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
		2019	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
		2020	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
		2021	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
		2022	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
		2023	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
		2024	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
		2025	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
		2026	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
		2027	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
		2028	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
		2029	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
		2030	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
		2031
		2032	/**************** Bit definition for NVIC_ICER register *****************/
		2033	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
		2034	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
		2035	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
		2036	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
		2037	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
		2038	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
		2039	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
		2040	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
		2041	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
		2042	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
		2043	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
		2044	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
		2045	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
		2046	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
		2047	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
		2048	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
		2049	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
		2050	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
		2051	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
		2052	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
		2053	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
		2054	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
		2055	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
		2056	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
		2057	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
		2058	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
		2059	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
		2060	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
		2061	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
		2062	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
		2063	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
		2064	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
		2065	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
		2066
		2067	/**************** Bit definition for NVIC_ISPR register *****************/
		2068	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
		2069	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
		2070	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
		2071	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
		2072	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
		2073	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
		2074	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
		2075	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
		2076	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
		2077	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
		2078	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
		2079	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
		2080	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
		2081	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
		2082	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
		2083	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
		2084	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
		2085	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
		2086	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
		2087	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
		2088	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
		2089	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
		2090	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
		2091	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
		2092	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
		2093	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
		2094	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
		2095	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
		2096	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
		2097	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
		2098	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
		2099	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
		2100	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
		2101
		2102	/**************** Bit definition for NVIC_ICPR register *****************/
		2103	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
		2104	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
		2105	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
		2106	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
		2107	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
		2108	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
		2109	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
		2110	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
		2111	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
		2112	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
		2113	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
		2114	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
		2115	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
		2116	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
		2117	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
		2118	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
		2119	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
		2120	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
		2121	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
		2122	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
		2123	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
		2124	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
		2125	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
		2126	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
		2127	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
		2128	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
		2129	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
		2130	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
		2131	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
		2132	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
		2133	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
		2134	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
		2135	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
		2136
		2137	/**************** Bit definition for NVIC_IABR register *****************/
		2138	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
		2139	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
		2140	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
		2141	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
		2142	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
		2143	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
		2144	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
		2145	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
		2146	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
		2147	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
		2148	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
		2149	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
		2150	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
		2151	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
		2152	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
		2153	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
		2154	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
		2155	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
		2156	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
		2157	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
		2158	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
		2159	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
		2160	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
		2161	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
		2162	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
		2163	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
		2164	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
		2165	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
		2166	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
		2167	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
		2168	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
		2169	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
		2170	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
		2171
		2172	/**************** Bit definition for NVIC_PRI0 register *****************/
		2173	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
		2174	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
		2175	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
		2176	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
		2177
		2178	/**************** Bit definition for NVIC_PRI1 register *****************/
		2179	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
		2180	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
		2181	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
		2182	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
		2183
		2184	/**************** Bit definition for NVIC_PRI2 register *****************/
		2185	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
		2186	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
		2187	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
		2188	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
		2189
		2190	/**************** Bit definition for NVIC_PRI3 register *****************/
		2191	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
		2192	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
		2193	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
		2194	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
		2195
		2196	/**************** Bit definition for NVIC_PRI4 register *****************/
		2197	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
		2198	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
		2199	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
		2200	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
		2201
		2202	/**************** Bit definition for NVIC_PRI5 register *****************/
		2203	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
		2204	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
		2205	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
		2206	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
		2207
		2208	/**************** Bit definition for NVIC_PRI6 register *****************/
		2209	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
		2210	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
		2211	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
		2212	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
		2213
		2214	/**************** Bit definition for NVIC_PRI7 register *****************/
		2215	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
		2216	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
		2217	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
		2218	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
		2219
		2220	/**************** Bit definition for SCB_CPUID register *****************/
		2221	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
		2222	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
		2223	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
		2224	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
		2225	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
		2226
		2227	/***************** Bit definition for SCB_ICSR register *****************/
		2228	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
		2229	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
		2230	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
		2231	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
		2232	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
		2233	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
		2234	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
		2235	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
		2236	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
		2237	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
		2238
		2239	/***************** Bit definition for SCB_VTOR register *****************/
		2240	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
		2241	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
		2242
		2243	/!<************** Bit definition for SCB_AIRCR register *****************/
		2244	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
		2245	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
		2246	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
		2247
		2248	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
		2249	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2250	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2251	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
		2252
		2253	/* prority group configuration */
		2254	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
		2255	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
		2256	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
		2257	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
		2258	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
		2259	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
		2260	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
		2261	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
		2262
		2263	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
		2264	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
		2265
		2266	/***************** Bit definition for SCB_SCR register ******************/
		2267	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
		2268	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
		2269	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
		2270
		2271	/****************** Bit definition for SCB_CCR register *****************/
		2272	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
		2273	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
		2274	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
		2275	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
		2276	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
		2277	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
		2278
		2279	/***************** Bit definition for SCB_SHPR register ******************/
		2280	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
		2281	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
		2282	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
		2283	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
		2284
		2285	/**************** Bit definition for SCB_SHCSR register *****************/
		2286	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
		2287	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
		2288	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
		2289	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
		2290	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
		2291	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
		2292	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
		2293	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
		2294	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
		2295	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
		2296	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
		2297	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
		2298	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
		2299	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
		2300
		2301	/***************** Bit definition for SCB_CFSR register *****************/
		2302	/!< MFSR /
		2303	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
		2304	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
		2305	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
		2306	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
		2307	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
		2308	/!< BFSR /
		2309	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
		2310	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
		2311	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
		2312	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
		2313	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
		2314	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
		2315	/!< UFSR /
		2316	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to execute an undefined instruction /
		2317	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
		2318	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
		2319	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
		2320	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
		2321	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
		2322
		2323	/***************** Bit definition for SCB_HFSR register *****************/
		2324	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
		2325	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
		2326	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
		2327
		2328	/***************** Bit definition for SCB_DFSR register *****************/
		2329	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
		2330	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
		2331	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
		2332	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
		2333	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
		2334
		2335	/***************** Bit definition for SCB_MMFAR register ****************/
		2336	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
		2337
		2338	/***************** Bit definition for SCB_BFAR register *****************/
		2339	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
		2340
		2341	/***************** Bit definition for SCB_afsr register *****************/
		2342	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
		2343
		2344	/******************************************************************************/
		2345	/* */
		2346	/* External Interrupt/Event Controller */
		2347	/* */
		2348	/******************************************************************************/
		2349
		2350	/***************** Bit definition for EXTI_IMR register *****************/
		2351	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
		2352	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
		2353	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
		2354	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
		2355	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
		2356	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
		2357	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
		2358	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
		2359	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
		2360	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
		2361	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
		2362	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
		2363	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
		2364	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
		2365	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
		2366	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
		2367	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
		2368	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
		2369	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
		2370	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
		2371
		2372	/***************** Bit definition for EXTI_EMR register *****************/
		2373	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
		2374	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
		2375	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
		2376	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
		2377	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
		2378	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
		2379	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
		2380	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
		2381	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
		2382	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
		2383	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
		2384	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
		2385	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
		2386	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
		2387	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
		2388	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
		2389	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
		2390	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
		2391	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
		2392	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
		2393
		2394	/**************** Bit definition for EXTI_RTSR register *****************/
		2395	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
		2396	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
		2397	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
		2398	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
		2399	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
		2400	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
		2401	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
		2402	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
		2403	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
		2404	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
		2405	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
		2406	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
		2407	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
		2408	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
		2409	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
		2410	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
		2411	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
		2412	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
		2413	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
		2414	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
		2415
		2416	/**************** Bit definition for EXTI_FTSR register *****************/
		2417	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
		2418	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
		2419	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
		2420	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
		2421	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
		2422	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
		2423	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
		2424	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
		2425	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
		2426	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
		2427	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
		2428	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
		2429	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
		2430	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
		2431	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
		2432	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
		2433	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
		2434	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
		2435	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
		2436	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
		2437
		2438	/**************** Bit definition for EXTI_SWIER register ****************/
		2439	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
		2440	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
		2441	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
		2442	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
		2443	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
		2444	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
		2445	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
		2446	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
		2447	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
		2448	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
		2449	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
		2450	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
		2451	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
		2452	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
		2453	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
		2454	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
		2455	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
		2456	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
		2457	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
		2458	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
		2459
		2460	/***************** Bit definition for EXTI_PR register ******************/
		2461	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
		2462	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
		2463	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
		2464	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
		2465	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
		2466	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
		2467	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
		2468	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
		2469	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
		2470	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
		2471	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
		2472	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
		2473	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
		2474	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
		2475	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
		2476	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
		2477	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
		2478	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
		2479	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
		2480	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
		2481
		2482	/******************************************************************************/
		2483	/* */
		2484	/* DMA Controller */
		2485	/* */
		2486	/******************************************************************************/
		2487
		2488	/***************** Bit definition for DMA_ISR register ******************/
		2489	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
		2490	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
		2491	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
		2492	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
		2493	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
		2494	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
		2495	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
		2496	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
		2497	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
		2498	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
		2499	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
		2500	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
		2501	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
		2502	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
		2503	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
		2504	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
		2505	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
		2506	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
		2507	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
		2508	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
		2509	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
		2510	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
		2511	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
		2512	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
		2513	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
		2514	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
		2515	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
		2516	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
		2517
		2518	/***************** Bit definition for DMA_IFCR register *****************/
		2519	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
		2520	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
		2521	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
		2522	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
		2523	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
		2524	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
		2525	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
		2526	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
		2527	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
		2528	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
		2529	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
		2530	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
		2531	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
		2532	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
		2533	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
		2534	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
		2535	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
		2536	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
		2537	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
		2538	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
		2539	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
		2540	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
		2541	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
		2542	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
		2543	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
		2544	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
		2545	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
		2546	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
		2547
		2548	/***************** Bit definition for DMA_CCR register *****************/
		2549	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
		2550	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
		2551	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
		2552	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
		2553	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
		2554	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
		2555	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
		2556	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
		2557
		2558	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
		2559	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2560	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2561
		2562	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
		2563	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2564	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2565
		2566	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level) /
		2567	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2568	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2569
		2570	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
		2571
		2572	/**************** Bit definition for DMA_CNDTR register ****************/
		2573	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
		2574
		2575	/**************** Bit definition for DMA_CPAR register *****************/
		2576	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
		2577
		2578	/**************** Bit definition for DMA_CMAR register *****************/
		2579	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
		2580
		2581	/******************************************************************************/
		2582	/* */
		2583	/* Analog to Digital Converter */
		2584	/* */
		2585	/******************************************************************************/
		2586
		2587	/****************** Bit definition for ADC_SR register ******************/
		2588	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
		2589	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
		2590	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
		2591	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
		2592	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
		2593
		2594	/***************** Bit definition for ADC_CR1 register ******************/
		2595	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
		2596	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2597	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2598	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2599	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2600	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2601
		2602	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
		2603	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
		2604	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
		2605	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
		2606	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
		2607	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
		2608	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
		2609	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
		2610
		2611	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
		2612	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
		2613	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
		2614	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
		2615
		2616	#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /!< DUALMOD[3:0] bits (Dual mode selection) /
		2617	#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /!< Bit 0 /
		2618	#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /!< Bit 1 /
		2619	#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /!< Bit 2 /
		2620	#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /!< Bit 3 /
		2621
		2622	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
		2623	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
		2624
		2625
		2626	/***************** Bit definition for ADC_CR2 register ******************/
		2627	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
		2628	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
		2629	#define ADC_CR2_CAL ((uint32_t)0x00000004) /!< A/D Calibration /
		2630	#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /!< Reset Calibration /
		2631	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
		2632	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
		2633
		2634	#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /!< JEXTSEL[2:0] bits (External event select for injected group) /
		2635	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2636	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2637	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2638
		2639	#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /!< External Trigger Conversion mode for injected channels /
		2640
		2641	#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
		2642	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /!< Bit 0 /
		2643	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /!< Bit 1 /
		2644	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /!< Bit 2 /
		2645
		2646	#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /!< External Trigger Conversion mode for regular channels /
		2647	#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /!< Start Conversion of injected channels /
		2648	#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /!< Start Conversion of regular channels /
		2649	#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
		2650
		2651	/**************** Bit definition for ADC_SMPR1 register *****************/
		2652	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
		2653	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2654	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2655	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2656
		2657	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
		2658	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2659	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2660	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2661
		2662	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
		2663	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2664	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2665	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
		2666
		2667	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
		2668	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
		2669	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
		2670	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
		2671
		2672	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
		2673	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2674	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2675	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2676
		2677	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 15 Sample time selection) /
		2678	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2679	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2680	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2681
		2682	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
		2683	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
		2684	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
		2685	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
		2686
		2687	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
		2688	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
		2689	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
		2690	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
		2691
		2692	/**************** Bit definition for ADC_SMPR2 register *****************/
		2693	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
		2694	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2695	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2696	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2697
		2698	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
		2699	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2700	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2701	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2702
		2703	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
		2704	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2705	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2706	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
		2707
		2708	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
		2709	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
		2710	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
		2711	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
		2712
		2713	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
		2714	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2715	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2716	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2717
		2718	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
		2719	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2720	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2721	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2722
		2723	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
		2724	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
		2725	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
		2726	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
		2727
		2728	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
		2729	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
		2730	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
		2731	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
		2732
		2733	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
		2734	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
		2735	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
		2736	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
		2737
		2738	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
		2739	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
		2740	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
		2741	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
		2742
		2743	/**************** Bit definition for ADC_JOFR1 register *****************/
		2744	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
		2745
		2746	/**************** Bit definition for ADC_JOFR2 register *****************/
		2747	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
		2748
		2749	/**************** Bit definition for ADC_JOFR3 register *****************/
		2750	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
		2751
		2752	/**************** Bit definition for ADC_JOFR4 register *****************/
		2753	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
		2754
		2755	/***************** Bit definition for ADC_HTR register ******************/
		2756	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
		2757
		2758	/***************** Bit definition for ADC_LTR register ******************/
		2759	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
		2760
		2761	/***************** Bit definition for ADC_SQR1 register *****************/
		2762	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
		2763	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2764	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2765	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2766	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2767	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2768
		2769	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
		2770	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2771	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2772	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2773	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2774	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2775
		2776	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
		2777	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2778	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2779	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2780	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2781	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2782
		2783	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
		2784	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2785	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2786	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2787	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2788	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2789
		2790	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!< L[3:0] bits (Regular channel sequence length) /
		2791	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2792	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2793	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2794	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2795
		2796	/***************** Bit definition for ADC_SQR2 register *****************/
		2797	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
		2798	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2799	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2800	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2801	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2802	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2803
		2804	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
		2805	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2806	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2807	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2808	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2809	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2810
		2811	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
		2812	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2813	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2814	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2815	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2816	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2817
		2818	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
		2819	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2820	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2821	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2822	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2823	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2824
		2825	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
		2826	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2827	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2828	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2829	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2830	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
		2831
		2832	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
		2833	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
		2834	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
		2835	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
		2836	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
		2837	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
		2838
		2839	/***************** Bit definition for ADC_SQR3 register *****************/
		2840	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
		2841	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2842	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2843	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2844	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2845	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2846
		2847	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
		2848	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2849	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2850	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2851	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2852	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2853
		2854	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
		2855	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2856	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2857	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2858	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2859	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2860
		2861	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
		2862	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2863	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2864	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2865	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2866	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2867
		2868	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
		2869	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2870	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2871	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2872	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2873	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
		2874
		2875	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
		2876	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
		2877	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
		2878	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
		2879	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
		2880	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
		2881
		2882	/***************** Bit definition for ADC_JSQR register *****************/
		2883	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
		2884	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2885	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2886	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2887	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2888	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2889
		2890	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
		2891	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2892	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2893	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2894	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2895	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2896
		2897	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
		2898	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2899	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2900	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2901	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2902	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2903
		2904	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
		2905	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2906	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2907	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2908	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2909	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2910
		2911	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
		2912	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2913	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2914
		2915	/***************** Bit definition for ADC_JDR1 register *****************/
		2916	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2917
		2918	/***************** Bit definition for ADC_JDR2 register *****************/
		2919	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2920
		2921	/***************** Bit definition for ADC_JDR3 register *****************/
		2922	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2923
		2924	/***************** Bit definition for ADC_JDR4 register *****************/
		2925	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2926
		2927	/****************** Bit definition for ADC_DR register ******************/
		2928	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
		2929	#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /!< ADC2 data /
		2930	/******************************************************************************/
		2931	/* */
		2932	/* Digital to Analog Converter */
		2933	/* */
		2934	/******************************************************************************/
		2935
		2936	/****************** Bit definition for DAC_CR register ******************/
		2937	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
		2938	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
		2939	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
		2940
		2941	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
		2942	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2943	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2944	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2945
		2946	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
		2947	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2948	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2949
		2950	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
		2951	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2952	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2953	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
		2954	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
		2955
		2956	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
		2957	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
		2958	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
		2959	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
		2960
		2961	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
		2962	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
		2963	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
		2964	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
		2965
		2966	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
		2967	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
		2968	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
		2969
		2970	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
		2971	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
		2972	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
		2973	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
		2974	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
		2975
		2976	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
		2977
		2978
		2979	/*************** Bit definition for DAC_SWTRIGR register ****************/
		2980	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!< DAC channel1 software trigger /
		2981	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!< DAC channel2 software trigger /
		2982
		2983	/*************** Bit definition for DAC_DHR12R1 register ****************/
		2984	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
		2985
		2986	/*************** Bit definition for DAC_DHR12L1 register ****************/
		2987	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
		2988
		2989	/**************** Bit definition for DAC_DHR8R1 register ****************/
		2990	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
		2991
		2992	/*************** Bit definition for DAC_DHR12R2 register ****************/
		2993	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!< DAC channel2 12-bit Right aligned data /
		2994
		2995	/*************** Bit definition for DAC_DHR12L2 register ****************/
		2996	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!< DAC channel2 12-bit Left aligned data /
		2997
		2998	/**************** Bit definition for DAC_DHR8R2 register ****************/
		2999	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!< DAC channel2 8-bit Right aligned data /
		3000
		3001	/*************** Bit definition for DAC_DHR12RD register ****************/
		3002	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
		3003	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!< DAC channel2 12-bit Right aligned data /
		3004
		3005	/*************** Bit definition for DAC_DHR12LD register ****************/
		3006	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
		3007	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!< DAC channel2 12-bit Left aligned data /
		3008
		3009	/**************** Bit definition for DAC_DHR8RD register ****************/
		3010	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
		3011	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!< DAC channel2 8-bit Right aligned data /
		3012
		3013	/***************** Bit definition for DAC_DOR1 register *****************/
		3014	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!< DAC channel1 data output /
		3015
		3016	/***************** Bit definition for DAC_DOR2 register *****************/
		3017	#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /!< DAC channel2 data output /
		3018
		3019
		3020
		3021	/*****************************************************************************/
		3022	/* */
		3023	/* Timers (TIM) */
		3024	/* */
		3025	/*****************************************************************************/
		3026	/***************** Bit definition for TIM_CR1 register *****************/
		3027	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
		3028	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
		3029	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
		3030	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
		3031	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
		3032
		3033	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
		3034	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
		3035	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
		3036
		3037	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
		3038
		3039	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
		3040	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3041	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3042
		3043	/***************** Bit definition for TIM_CR2 register *****************/
		3044	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
		3045	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
		3046	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
		3047
		3048	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
		3049	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3050	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3051	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3052
		3053	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
		3054	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
		3055	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
		3056	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
		3057	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
		3058	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
		3059	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
		3060	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
		3061
		3062	/***************** Bit definition for TIM_SMCR register ****************/
		3063	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
		3064	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3065	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3066	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
		3067
		3068	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
		3069
		3070	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
		3071	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3072	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3073	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3074
		3075	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
		3076
		3077	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
		3078	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3079	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3080	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
		3081	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
		3082
		3083	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
		3084	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3085	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3086
		3087	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
		3088	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
		3089
		3090	/***************** Bit definition for TIM_DIER register ****************/
		3091	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
		3092	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
		3093	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
		3094	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
		3095	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
		3096	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
		3097	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
		3098	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
		3099	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
		3100	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
		3101	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
		3102	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
		3103	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
		3104	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
		3105	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
		3106
		3107	/****************** Bit definition for TIM_SR register *****************/
		3108	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
		3109	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
		3110	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
		3111	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
		3112	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
		3113	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
		3114	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
		3115	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
		3116	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
		3117	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
		3118	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
		3119	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
		3120
		3121	/***************** Bit definition for TIM_EGR register *****************/
		3122	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
		3123	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
		3124	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
		3125	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
		3126	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
		3127	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
		3128	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
		3129	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
		3130
		3131	/**************** Bit definition for TIM_CCMR1 register ****************/
		3132	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
		3133	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3134	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3135
		3136	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
		3137	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
		3138
		3139	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
		3140	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3141	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3142	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3143
		3144	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
		3145
		3146	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
		3147	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3148	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3149
		3150	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
		3151	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
		3152
		3153	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
		3154	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3155	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3156	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3157
		3158	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
		3159
		3160	/---------------------------------------------------------------------------/
		3161
		3162	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
		3163	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
		3164	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
		3165
		3166	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
		3167	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3168	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3169	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3170	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
		3171
		3172	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
		3173	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
		3174	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
		3175
		3176	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
		3177	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3178	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3179	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3180	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
		3181
		3182	/**************** Bit definition for TIM_CCMR2 register ****************/
		3183	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
		3184	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3185	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3186
		3187	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
		3188	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
		3189
		3190	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
		3191	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3192	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3193	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3194
		3195	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
		3196
		3197	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
		3198	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3199	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3200
		3201	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
		3202	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
		3203
		3204	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
		3205	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3206	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3207	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3208
		3209	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
		3210
		3211	/---------------------------------------------------------------------------/
		3212
		3213	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
		3214	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
		3215	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
		3216
		3217	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
		3218	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3219	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3220	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3221	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
		3222
		3223	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
		3224	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
		3225	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
		3226
		3227	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
		3228	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3229	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3230	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3231	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
		3232
		3233	/***************** Bit definition for TIM_CCER register ****************/
		3234	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
		3235	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
		3236	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
		3237	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
		3238	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
		3239	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
		3240	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
		3241	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
		3242	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
		3243	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
		3244	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
		3245	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
		3246	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
		3247	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
		3248	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
		3249
		3250	/***************** Bit definition for TIM_CNT register *****************/
		3251	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
		3252
		3253	/***************** Bit definition for TIM_PSC register *****************/
		3254	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
		3255
		3256	/***************** Bit definition for TIM_ARR register *****************/
		3257	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
		3258
		3259	/***************** Bit definition for TIM_RCR register *****************/
		3260	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
		3261
		3262	/***************** Bit definition for TIM_CCR1 register ****************/
		3263	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
		3264
		3265	/***************** Bit definition for TIM_CCR2 register ****************/
		3266	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
		3267
		3268	/***************** Bit definition for TIM_CCR3 register ****************/
		3269	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
		3270
		3271	/***************** Bit definition for TIM_CCR4 register ****************/
		3272	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
		3273
		3274	/***************** Bit definition for TIM_BDTR register ****************/
		3275	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
		3276	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3277	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3278	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
		3279	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
		3280	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
		3281	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
		3282	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
		3283	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
		3284
		3285	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
		3286	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3287	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3288
		3289	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
		3290	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
		3291	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
		3292	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
		3293	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
		3294	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
		3295
		3296	/***************** Bit definition for TIM_DCR register *****************/
		3297	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
		3298	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3299	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3300	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
		3301	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
		3302	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
		3303
		3304	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
		3305	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3306	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3307	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
		3308	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
		3309	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
		3310
		3311	/***************** Bit definition for TIM_DMAR register ****************/
		3312	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
		3313
		3314	/***************** Bit definition for TIM_OR register ******************/
		3315
		3316	/******************************************************************************/
		3317	/* */
		3318	/* Real-Time Clock */
		3319	/* */
		3320	/******************************************************************************/
		3321
		3322	/***************** Bit definition for RTC_CRH register ******************/
		3323	#define RTC_CRH_SECIE ((uint32_t)0x00000001) /!< Second Interrupt Enable /
		3324	#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /!< Alarm Interrupt Enable /
		3325	#define RTC_CRH_OWIE ((uint32_t)0x00000004) /!< OverfloW Interrupt Enable /
		3326
		3327	/***************** Bit definition for RTC_CRL register ******************/
		3328	#define RTC_CRL_SECF ((uint32_t)0x00000001) /!< Second Flag /
		3329	#define RTC_CRL_ALRF ((uint32_t)0x00000002) /!< Alarm Flag /
		3330	#define RTC_CRL_OWF ((uint32_t)0x00000004) /!< OverfloW Flag /
		3331	#define RTC_CRL_RSF ((uint32_t)0x00000008) /!< Registers Synchronized Flag /
		3332	#define RTC_CRL_CNF ((uint32_t)0x00000010) /!< Configuration Flag /
		3333	#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /!< RTC operation OFF /
		3334
		3335	/***************** Bit definition for RTC_PRLH register *****************/
		3336	#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /!< RTC Prescaler Reload Value High /
		3337
		3338	/***************** Bit definition for RTC_PRLL register *****************/
		3339	#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /!< RTC Prescaler Reload Value Low /
		3340
		3341	/***************** Bit definition for RTC_DIVH register *****************/
		3342	#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /!< RTC Clock Divider High /
		3343
		3344	/***************** Bit definition for RTC_DIVL register *****************/
		3345	#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /!< RTC Clock Divider Low /
		3346
		3347	/***************** Bit definition for RTC_CNTH register *****************/
		3348	#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter High /
		3349
		3350	/***************** Bit definition for RTC_CNTL register *****************/
		3351	#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter Low /
		3352
		3353	/***************** Bit definition for RTC_ALRH register *****************/
		3354	#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm High /
		3355
		3356	/***************** Bit definition for RTC_ALRL register *****************/
		3357	#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm Low /
		3358
		3359	/******************************************************************************/
		3360	/* */
		3361	/* Independent WATCHDOG (IWDG) */
		3362	/* */
		3363	/******************************************************************************/
		3364
		3365	/***************** Bit definition for IWDG_KR register ******************/
		3366	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!< Key value (write only, read 0000h) /
		3367
		3368	/***************** Bit definition for IWDG_PR register ******************/
		3369	#define IWDG_PR_PR ((uint32_t)0x00000007) /!< PR[2:0] (Prescaler divider) /
		3370	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3371	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3372	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3373
		3374	/***************** Bit definition for IWDG_RLR register *****************/
		3375	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!< Watchdog counter reload value /
		3376
		3377	/***************** Bit definition for IWDG_SR register ******************/
		3378	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
		3379	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
		3380
		3381	/******************************************************************************/
		3382	/* */
		3383	/* Window WATCHDOG */
		3384	/* */
		3385	/******************************************************************************/
		3386
		3387	/***************** Bit definition for WWDG_CR register ******************/
		3388	#define WWDG_CR_T ((uint32_t)0x0000007F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
		3389	#define WWDG_CR_T0 ((uint32_t)0x00000001) /!< Bit 0 /
		3390	#define WWDG_CR_T1 ((uint32_t)0x00000002) /!< Bit 1 /
		3391	#define WWDG_CR_T2 ((uint32_t)0x00000004) /!< Bit 2 /
		3392	#define WWDG_CR_T3 ((uint32_t)0x00000008) /!< Bit 3 /
		3393	#define WWDG_CR_T4 ((uint32_t)0x00000010) /!< Bit 4 /
		3394	#define WWDG_CR_T5 ((uint32_t)0x00000020) /!< Bit 5 /
		3395	#define WWDG_CR_T6 ((uint32_t)0x00000040) /!< Bit 6 /
		3396
		3397	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!< Activation bit /
		3398
		3399	/***************** Bit definition for WWDG_CFR register *****************/
		3400	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!< W[6:0] bits (7-bit window value) /
		3401	#define WWDG_CFR_W0 ((uint32_t)0x00000001) /!< Bit 0 /
		3402	#define WWDG_CFR_W1 ((uint32_t)0x00000002) /!< Bit 1 /
		3403	#define WWDG_CFR_W2 ((uint32_t)0x00000004) /!< Bit 2 /
		3404	#define WWDG_CFR_W3 ((uint32_t)0x00000008) /!< Bit 3 /
		3405	#define WWDG_CFR_W4 ((uint32_t)0x00000010) /!< Bit 4 /
		3406	#define WWDG_CFR_W5 ((uint32_t)0x00000020) /!< Bit 5 /
		3407	#define WWDG_CFR_W6 ((uint32_t)0x00000040) /!< Bit 6 /
		3408
		3409	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!< WDGTB[1:0] bits (Timer Base) /
		3410	#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /!< Bit 0 /
		3411	#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /!< Bit 1 /
		3412
		3413	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!< Early Wakeup Interrupt /
		3414
		3415	/***************** Bit definition for WWDG_SR register ******************/
		3416	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!< Early Wakeup Interrupt Flag /
		3417
		3418	/******************************************************************************/
		3419	/* */
		3420	/* Flexible Static Memory Controller */
		3421	/* */
		3422	/******************************************************************************/
		3423
		3424	/**************** Bit definition for FSMC_BCRx (x=1..4) register ********/
		3425	#define FSMC_BCRx_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
		3426	#define FSMC_BCRx_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
		3427
		3428	#define FSMC_BCRx_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
		3429	#define FSMC_BCRx_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
		3430	#define FSMC_BCRx_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
		3431
		3432	#define FSMC_BCRx_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
		3433	#define FSMC_BCRx_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3434	#define FSMC_BCRx_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3435
		3436	#define FSMC_BCRx_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
		3437	#define FSMC_BCRx_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
		3438	#define FSMC_BCRx_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit /
		3439	#define FSMC_BCRx_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
		3440	#define FSMC_BCRx_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
		3441	#define FSMC_BCRx_WREN ((uint32_t)0x00001000) /!< Write enable bit /
		3442	#define FSMC_BCRx_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
		3443	#define FSMC_BCRx_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
		3444	#define FSMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
		3445	#define FSMC_BCRx_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
		3446
		3447	/**************** Bit definition for FSMC_BTRx (x=1..4) register ****/
		3448	#define FSMC_BTRx_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
		3449	#define FSMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3450	#define FSMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3451	#define FSMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3452	#define FSMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3453
		3454	#define FSMC_BTRx_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		3455	#define FSMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3456	#define FSMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3457	#define FSMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
		3458	#define FSMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
		3459
		3460	#define FSMC_BTRx_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
		3461	#define FSMC_BTRx_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
		3462	#define FSMC_BTRx_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
		3463	#define FSMC_BTRx_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
		3464	#define FSMC_BTRx_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
		3465	#define FSMC_BTRx_DATAST_4 ((uint32_t)0x00001000) /!< Bit 4 /
		3466	#define FSMC_BTRx_DATAST_5 ((uint32_t)0x00002000) /!< Bit 5 /
		3467	#define FSMC_BTRx_DATAST_6 ((uint32_t)0x00004000) /!< Bit 6 /
		3468	#define FSMC_BTRx_DATAST_7 ((uint32_t)0x00008000) /!< Bit 7 /
		3469
		3470	#define FSMC_BTRx_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
		3471	#define FSMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
		3472	#define FSMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
		3473	#define FSMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
		3474	#define FSMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
		3475
		3476	#define FSMC_BTRx_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
		3477	#define FSMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
		3478	#define FSMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
		3479	#define FSMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
		3480	#define FSMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
		3481
		3482	#define FSMC_BTRx_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
		3483	#define FSMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
		3484	#define FSMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
		3485	#define FSMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
		3486	#define FSMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
		3487
		3488	#define FSMC_BTRx_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
		3489	#define FSMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
		3490	#define FSMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
		3491
		3492	/**************** Bit definition for FSMC_BWTRx (x=1..4) register ****/
		3493	#define FSMC_BWTRx_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
		3494	#define FSMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3495	#define FSMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3496	#define FSMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3497	#define FSMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3498
		3499	#define FSMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		3500	#define FSMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3501	#define FSMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3502	#define FSMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
		3503	#define FSMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
		3504
		3505	#define FSMC_BWTRx_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
		3506	#define FSMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
		3507	#define FSMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
		3508	#define FSMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
		3509	#define FSMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
		3510	#define FSMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) /!< Bit 4 /
		3511	#define FSMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) /!< Bit 5 /
		3512	#define FSMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) /!< Bit 6 /
		3513	#define FSMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) /!< Bit 7 /
		3514
		3515	#define FSMC_BWTRx_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
		3516	#define FSMC_BWTRx_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
		3517	#define FSMC_BWTRx_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
		3518	#define FSMC_BWTRx_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
		3519	#define FSMC_BWTRx_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
		3520
		3521	#define FSMC_BWTRx_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
		3522	#define FSMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
		3523	#define FSMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
		3524
		3525	/**************** Bit definition for FSMC_PCRx (x = 2 to 4) register *****************/
		3526	#define FSMC_PCRx_PWAITEN ((uint32_t)0x00000002) /!< Wait feature enable bit /
		3527	#define FSMC_PCRx_PBKEN ((uint32_t)0x00000004) /!< PC Card/NAND Flash memory bank enable bit /
		3528	#define FSMC_PCRx_PTYP ((uint32_t)0x00000008) /!< Memory type /
		3529
		3530	#define FSMC_PCRx_PWID ((uint32_t)0x00000030) /!< PWID[1:0] bits (NAND Flash databus width) /
		3531	#define FSMC_PCRx_PWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3532	#define FSMC_PCRx_PWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3533
		3534	#define FSMC_PCRx_ECCEN ((uint32_t)0x00000040) /!< ECC computation logic enable bit /
		3535
		3536	#define FSMC_PCRx_TCLR ((uint32_t)0x00001E00) /!< TCLR[3:0] bits (CLE to RE delay) /
		3537	#define FSMC_PCRx_TCLR_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3538	#define FSMC_PCRx_TCLR_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3539	#define FSMC_PCRx_TCLR_2 ((uint32_t)0x00000800) /!< Bit 2 /
		3540	#define FSMC_PCRx_TCLR_3 ((uint32_t)0x00001000) /!< Bit 3 /
		3541
		3542	#define FSMC_PCRx_TAR ((uint32_t)0x0001E000) /!< TAR[3:0] bits (ALE to RE delay) /
		3543	#define FSMC_PCRx_TAR_0 ((uint32_t)0x00002000) /!< Bit 0 /
		3544	#define FSMC_PCRx_TAR_1 ((uint32_t)0x00004000) /!< Bit 1 /
		3545	#define FSMC_PCRx_TAR_2 ((uint32_t)0x00008000) /!< Bit 2 /
		3546	#define FSMC_PCRx_TAR_3 ((uint32_t)0x00010000) /!< Bit 3 /
		3547
		3548	#define FSMC_PCRx_ECCPS ((uint32_t)0x000E0000) /!< ECCPS[1:0] bits (ECC page size) /
		3549	#define FSMC_PCRx_ECCPS_0 ((uint32_t)0x00020000) /!< Bit 0 /
		3550	#define FSMC_PCRx_ECCPS_1 ((uint32_t)0x00040000) /!< Bit 1 /
		3551	#define FSMC_PCRx_ECCPS_2 ((uint32_t)0x00080000) /!< Bit 2 /
		3552
		3553	/***************** Bit definition for FSMC_SRx (x = 2 to 4) register *****************/
		3554	#define FSMC_SRx_IRS ((uint32_t)0x00000001) /!< Interrupt Rising Edge status /
		3555	#define FSMC_SRx_ILS ((uint32_t)0x00000002) /!< Interrupt Level status /
		3556	#define FSMC_SRx_IFS ((uint32_t)0x00000004) /!< Interrupt Falling Edge status /
		3557	#define FSMC_SRx_IREN ((uint32_t)0x00000008) /!< Interrupt Rising Edge detection Enable bit /
		3558	#define FSMC_SRx_ILEN ((uint32_t)0x00000010) /!< Interrupt Level detection Enable bit /
		3559	#define FSMC_SRx_IFEN ((uint32_t)0x00000020) /!< Interrupt Falling Edge detection Enable bit /
		3560	#define FSMC_SRx_FEMPT ((uint32_t)0x00000040) /!< FIFO empty /
		3561
		3562	/**************** Bit definition for FSMC_PMEMx (x = 2 to 4) register ****************/
		3563	#define FSMC_PMEMx_MEMSETx ((uint32_t)0x000000FF) /!< MEMSETx[7:0] bits (Common memory x setup time) /
		3564	#define FSMC_PMEMx_MEMSETx_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3565	#define FSMC_PMEMx_MEMSETx_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3566	#define FSMC_PMEMx_MEMSETx_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3567	#define FSMC_PMEMx_MEMSETx_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3568	#define FSMC_PMEMx_MEMSETx_4 ((uint32_t)0x00000010) /!< Bit 4 /
		3569	#define FSMC_PMEMx_MEMSETx_5 ((uint32_t)0x00000020) /!< Bit 5 /
		3570	#define FSMC_PMEMx_MEMSETx_6 ((uint32_t)0x00000040) /!< Bit 6 /
		3571	#define FSMC_PMEMx_MEMSETx_7 ((uint32_t)0x00000080) /!< Bit 7 /
		3572
		3573	#define FSMC_PMEMx_MEMWAITx ((uint32_t)0x0000FF00) /!< MEMWAITx[7:0] bits (Common memory x wait time) /
		3574	#define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /!< Bit 0 /
		3575	#define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /!< Bit 1 /
		3576	#define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /!< Bit 2 /
		3577	#define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /!< Bit 3 /
		3578	#define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /!< Bit 4 /
		3579	#define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /!< Bit 5 /
		3580	#define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /!< Bit 6 /
		3581	#define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /!< Bit 7 /
		3582
		3583	#define FSMC_PMEMx_MEMHOLDx ((uint32_t)0x00FF0000) /!< MEMHOLDx[7:0] bits (Common memory x hold time) /
		3584	#define FSMC_PMEMx_MEMHOLDx_0 ((uint32_t)0x00010000) /!< Bit 0 /
		3585	#define FSMC_PMEMx_MEMHOLDx_1 ((uint32_t)0x00020000) /!< Bit 1 /
		3586	#define FSMC_PMEMx_MEMHOLDx_2 ((uint32_t)0x00040000) /!< Bit 2 /
		3587	#define FSMC_PMEMx_MEMHOLDx_3 ((uint32_t)0x00080000) /!< Bit 3 /
		3588	#define FSMC_PMEMx_MEMHOLDx_4 ((uint32_t)0x00100000) /!< Bit 4 /
		3589	#define FSMC_PMEMx_MEMHOLDx_5 ((uint32_t)0x00200000) /!< Bit 5 /
		3590	#define FSMC_PMEMx_MEMHOLDx_6 ((uint32_t)0x00400000) /!< Bit 6 /
		3591	#define FSMC_PMEMx_MEMHOLDx_7 ((uint32_t)0x00800000) /!< Bit 7 /
		3592
		3593	#define FSMC_PMEMx_MEMHIZx ((uint32_t)0xFF000000) /!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) /
		3594	#define FSMC_PMEMx_MEMHIZx_0 ((uint32_t)0x01000000) /!< Bit 0 /
		3595	#define FSMC_PMEMx_MEMHIZx_1 ((uint32_t)0x02000000) /!< Bit 1 /
		3596	#define FSMC_PMEMx_MEMHIZx_2 ((uint32_t)0x04000000) /!< Bit 2 /
		3597	#define FSMC_PMEMx_MEMHIZx_3 ((uint32_t)0x08000000) /!< Bit 3 /
		3598	#define FSMC_PMEMx_MEMHIZx_4 ((uint32_t)0x10000000) /!< Bit 4 /
		3599	#define FSMC_PMEMx_MEMHIZx_5 ((uint32_t)0x20000000) /!< Bit 5 /
		3600	#define FSMC_PMEMx_MEMHIZx_6 ((uint32_t)0x40000000) /!< Bit 6 /
		3601	#define FSMC_PMEMx_MEMHIZx_7 ((uint32_t)0x80000000) /!< Bit 7 /
		3602
		3603	/**************** Bit definition for FSMC_PATTx (x = 2 to 4) register ****************/
		3604	#define FSMC_PATTx_ATTSETx ((uint32_t)0x000000FF) /!< ATTSETx[7:0] bits (Attribute memory x setup time) /
		3605	#define FSMC_PATTx_ATTSETx_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3606	#define FSMC_PATTx_ATTSETx_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3607	#define FSMC_PATTx_ATTSETx_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3608	#define FSMC_PATTx_ATTSETx_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3609	#define FSMC_PATTx_ATTSETx_4 ((uint32_t)0x00000010) /!< Bit 4 /
		3610	#define FSMC_PATTx_ATTSETx_5 ((uint32_t)0x00000020) /!< Bit 5 /
		3611	#define FSMC_PATTx_ATTSETx_6 ((uint32_t)0x00000040) /!< Bit 6 /
		3612	#define FSMC_PATTx_ATTSETx_7 ((uint32_t)0x00000080) /!< Bit 7 /
		3613
		3614	#define FSMC_PATTx_ATTWAITx ((uint32_t)0x0000FF00) /!< ATTWAITx[7:0] bits (Attribute memory x wait time) /
		3615	#define FSMC_PATTx_ATTWAITx_0 ((uint32_t)0x00000100) /!< Bit 0 /
		3616	#define FSMC_PATTx_ATTWAITx_1 ((uint32_t)0x00000200) /!< Bit 1 /
		3617	#define FSMC_PATTx_ATTWAITx_2 ((uint32_t)0x00000400) /!< Bit 2 /
		3618	#define FSMC_PATTx_ATTWAITx_3 ((uint32_t)0x00000800) /!< Bit 3 /
		3619	#define FSMC_PATTx_ATTWAITx_4 ((uint32_t)0x00001000) /!< Bit 4 /
		3620	#define FSMC_PATTx_ATTWAITx_5 ((uint32_t)0x00002000) /!< Bit 5 /
		3621	#define FSMC_PATTx_ATTWAITx_6 ((uint32_t)0x00004000) /!< Bit 6 /
		3622	#define FSMC_PATTx_ATTWAITx_7 ((uint32_t)0x00008000) /!< Bit 7 /
		3623
		3624	#define FSMC_PATTx_ATTHOLDx ((uint32_t)0x00FF0000) /!< ATTHOLDx[7:0] bits (Attribute memory x hold time) /
		3625	#define FSMC_PATTx_ATTHOLDx_0 ((uint32_t)0x00010000) /!< Bit 0 /
		3626	#define FSMC_PATTx_ATTHOLDx_1 ((uint32_t)0x00020000) /!< Bit 1 /
		3627	#define FSMC_PATTx_ATTHOLDx_2 ((uint32_t)0x00040000) /!< Bit 2 /
		3628	#define FSMC_PATTx_ATTHOLDx_3 ((uint32_t)0x00080000) /!< Bit 3 /
		3629	#define FSMC_PATTx_ATTHOLDx_4 ((uint32_t)0x00100000) /!< Bit 4 /
		3630	#define FSMC_PATTx_ATTHOLDx_5 ((uint32_t)0x00200000) /!< Bit 5 /
		3631	#define FSMC_PATTx_ATTHOLDx_6 ((uint32_t)0x00400000) /!< Bit 6 /
		3632	#define FSMC_PATTx_ATTHOLDx_7 ((uint32_t)0x00800000) /!< Bit 7 /
		3633
		3634	#define FSMC_PATTx_ATTHIZx ((uint32_t)0xFF000000) /!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) /
		3635	#define FSMC_PATTx_ATTHIZx_0 ((uint32_t)0x01000000) /!< Bit 0 /
		3636	#define FSMC_PATTx_ATTHIZx_1 ((uint32_t)0x02000000) /!< Bit 1 /
		3637	#define FSMC_PATTx_ATTHIZx_2 ((uint32_t)0x04000000) /!< Bit 2 /
		3638	#define FSMC_PATTx_ATTHIZx_3 ((uint32_t)0x08000000) /!< Bit 3 /
		3639	#define FSMC_PATTx_ATTHIZx_4 ((uint32_t)0x10000000) /!< Bit 4 /
		3640	#define FSMC_PATTx_ATTHIZx_5 ((uint32_t)0x20000000) /!< Bit 5 /
		3641	#define FSMC_PATTx_ATTHIZx_6 ((uint32_t)0x40000000) /!< Bit 6 /
		3642	#define FSMC_PATTx_ATTHIZx_7 ((uint32_t)0x80000000) /!< Bit 7 /
		3643
		3644	/**************** Bit definition for FSMC_PIO4 register *****************/
		3645	#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /!< IOSET4[7:0] bits (I/O 4 setup time) /
		3646	#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3647	#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3648	#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3649	#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3650	#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /!< Bit 4 /
		3651	#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /!< Bit 5 /
		3652	#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /!< Bit 6 /
		3653	#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /!< Bit 7 /
		3654
		3655	#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /!< IOWAIT4[7:0] bits (I/O 4 wait time) /
		3656	#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /!< Bit 0 /
		3657	#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /!< Bit 1 /
		3658	#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /!< Bit 2 /
		3659	#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /!< Bit 3 /
		3660	#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /!< Bit 4 /
		3661	#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /!< Bit 5 /
		3662	#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /!< Bit 6 /
		3663	#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /!< Bit 7 /
		3664
		3665	#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /!< IOHOLD4[7:0] bits (I/O 4 hold time) /
		3666	#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /!< Bit 0 /
		3667	#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /!< Bit 1 /
		3668	#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /!< Bit 2 /
		3669	#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /!< Bit 3 /
		3670	#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /!< Bit 4 /
		3671	#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /!< Bit 5 /
		3672	#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /!< Bit 6 /
		3673	#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /!< Bit 7 /
		3674
		3675	#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) /
		3676	#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /!< Bit 0 /
		3677	#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /!< Bit 1 /
		3678	#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /!< Bit 2 /
		3679	#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /!< Bit 3 /
		3680	#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /!< Bit 4 /
		3681	#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /!< Bit 5 /
		3682	#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /!< Bit 6 /
		3683	#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /!< Bit 7 /
		3684
		3685	/**************** Bit definition for FSMC_ECCR2 register ****************/
		3686	#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /!< ECC result /
		3687
		3688	/**************** Bit definition for FSMC_ECCR3 register ****************/
		3689	#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /!< ECC result /
		3690
		3691	/******************************************************************************/
		3692	/* */
		3693	/* SD host Interface */
		3694	/* */
		3695	/******************************************************************************/
		3696
		3697	/**************** Bit definition for SDIO_POWER register ****************/
		3698	#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /!< PWRCTRL[1:0] bits (Power supply control bits) /
		3699	#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /!< Bit 0 /
		3700	#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /!< Bit 1 /
		3701
		3702	/**************** Bit definition for SDIO_CLKCR register ****************/
		3703	#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /!< Clock divide factor /
		3704	#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /!< Clock enable bit /
		3705	#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /!< Power saving configuration bit /
		3706	#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /!< Clock divider bypass enable bit /
		3707
		3708	#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
		3709	#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /!< Bit 0 /
		3710	#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /!< Bit 1 /
		3711
		3712	#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /!< SDIO_CK dephasing selection bit /
		3713	#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /!< HW Flow Control enable /
		3714
		3715	/***************** Bit definition for SDIO_ARG register *****************/
		3716	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!< Command argument /
		3717
		3718	/***************** Bit definition for SDIO_CMD register *****************/
		3719	#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /!< Command Index /
		3720
		3721	#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /!< WAITRESP[1:0] bits (Wait for response bits) /
		3722	#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /!< Bit 0 /
		3723	#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /!< Bit 1 /
		3724
		3725	#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /!< CPSM Waits for Interrupt Request /
		3726	#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
		3727	#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /!< Command path state machine (CPSM) Enable bit /
		3728	#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /!< SD I/O suspend command /
		3729	#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /!< Enable CMD completion /
		3730	#define SDIO_CMD_NIEN ((uint32_t)0x2000) /!< Not Interrupt Enable /
		3731	#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /!< CE-ATA command /
		3732
		3733	/*************** Bit definition for SDIO_RESPCMD register ***************/
		3734	#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /!< Response command index /
		3735
		3736	/**************** Bit definition for SDIO_RESP0 register ****************/
		3737	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3738
		3739	/**************** Bit definition for SDIO_RESP1 register ****************/
		3740	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3741
		3742	/**************** Bit definition for SDIO_RESP2 register ****************/
		3743	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3744
		3745	/**************** Bit definition for SDIO_RESP3 register ****************/
		3746	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3747
		3748	/**************** Bit definition for SDIO_RESP4 register ****************/
		3749	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3750
		3751	/**************** Bit definition for SDIO_DTIMER register ***************/
		3752	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!< Data timeout period. /
		3753
		3754	/**************** Bit definition for SDIO_DLEN register *****************/
		3755	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!< Data length value /
		3756
		3757	/**************** Bit definition for SDIO_DCTRL register ****************/
		3758	#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /!< Data transfer enabled bit /
		3759	#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /!< Data transfer direction selection /
		3760	#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /!< Data transfer mode selection /
		3761	#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /!< DMA enabled bit /
		3762
		3763	#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /!< DBLOCKSIZE[3:0] bits (Data block size) /
		3764	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /!< Bit 0 /
		3765	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /!< Bit 1 /
		3766	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /!< Bit 2 /
		3767	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /!< Bit 3 /
		3768
		3769	#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /!< Read wait start /
		3770	#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /!< Read wait stop /
		3771	#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /!< Read wait mode /
		3772	#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /!< SD I/O enable functions /
		3773
		3774	/**************** Bit definition for SDIO_DCOUNT register ***************/
		3775	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!< Data count value /
		3776
		3777	/**************** Bit definition for SDIO_STA register ******************/
		3778	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!< Command response received (CRC check failed) /
		3779	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!< Data block sent/received (CRC check failed) /
		3780	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!< Command response timeout /
		3781	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!< Data timeout /
		3782	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!< Transmit FIFO underrun error /
		3783	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!< Received FIFO overrun error /
		3784	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!< Command response received (CRC check passed) /
		3785	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!< Command sent (no response required) /
		3786	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!< Data end (data counter, SDIDCOUNT, is zero) /
		3787	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!< Start bit not detected on all data signals in wide bus mode /
		3788	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!< Data block sent/received (CRC check passed) /
		3789	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!< Command transfer in progress /
		3790	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!< Data transmit in progress /
		3791	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!< Data receive in progress /
		3792	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
		3793	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
		3794	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!< Transmit FIFO full /
		3795	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!< Receive FIFO full /
		3796	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!< Transmit FIFO empty /
		3797	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!< Receive FIFO empty /
		3798	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!< Data available in transmit FIFO /
		3799	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!< Data available in receive FIFO /
		3800	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!< SDIO interrupt received /
		3801	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!< CE-ATA command completion signal received for CMD61 /
		3802
		3803	/***************** Bit definition for SDIO_ICR register *****************/
		3804	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!< CCRCFAIL flag clear bit /
		3805	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!< DCRCFAIL flag clear bit /
		3806	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!< CTIMEOUT flag clear bit /
		3807	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!< DTIMEOUT flag clear bit /
		3808	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!< TXUNDERR flag clear bit /
		3809	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!< RXOVERR flag clear bit /
		3810	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!< CMDREND flag clear bit /
		3811	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!< CMDSENT flag clear bit /
		3812	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!< DATAEND flag clear bit /
		3813	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!< STBITERR flag clear bit /
		3814	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!< DBCKEND flag clear bit /
		3815	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!< SDIOIT flag clear bit /
		3816	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!< CEATAEND flag clear bit /
		3817
		3818	/**************** Bit definition for SDIO_MASK register *****************/
		3819	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!< Command CRC Fail Interrupt Enable /
		3820	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!< Data CRC Fail Interrupt Enable /
		3821	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!< Command TimeOut Interrupt Enable /
		3822	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!< Data TimeOut Interrupt Enable /
		3823	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!< Tx FIFO UnderRun Error Interrupt Enable /
		3824	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!< Rx FIFO OverRun Error Interrupt Enable /
		3825	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!< Command Response Received Interrupt Enable /
		3826	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!< Command Sent Interrupt Enable /
		3827	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!< Data End Interrupt Enable /
		3828	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!< Start Bit Error Interrupt Enable /
		3829	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!< Data Block End Interrupt Enable /
		3830	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!< Command Acting Interrupt Enable /
		3831	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!< Data Transmit Acting Interrupt Enable /
		3832	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!< Data receive acting interrupt enabled /
		3833	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!< Tx FIFO Half Empty interrupt Enable /
		3834	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!< Rx FIFO Half Full interrupt Enable /
		3835	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!< Tx FIFO Full interrupt Enable /
		3836	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!< Rx FIFO Full interrupt Enable /
		3837	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!< Tx FIFO Empty interrupt Enable /
		3838	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!< Rx FIFO Empty interrupt Enable /
		3839	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!< Data available in Tx FIFO interrupt Enable /
		3840	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!< Data available in Rx FIFO interrupt Enable /
		3841	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!< SDIO Mode Interrupt Received interrupt Enable /
		3842	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!< CE-ATA command completion signal received Interrupt Enable /
		3843
		3844	/*************** Bit definition for SDIO_FIFOCNT register ***************/
		3845	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!< Remaining number of words to be written to or read from the FIFO /
		3846
		3847	/**************** Bit definition for SDIO_FIFO register *****************/
		3848	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!< Receive and transmit FIFO data /
		3849
		3850	/******************************************************************************/
		3851	/* */
		3852	/* USB Device FS */
		3853	/* */
		3854	/******************************************************************************/
		3855
		3856	/!< Endpoint-specific registers /
		3857	#define USB_EP0R USB_BASE /!< Endpoint 0 register address /
		3858	#define USB_EP1R (USB_BASE + 0x00000004) /!< Endpoint 1 register address /
		3859	#define USB_EP2R (USB_BASE + 0x00000008) /!< Endpoint 2 register address /
		3860	#define USB_EP3R (USB_BASE + 0x0000000C) /!< Endpoint 3 register address /
		3861	#define USB_EP4R (USB_BASE + 0x00000010) /!< Endpoint 4 register address /
		3862	#define USB_EP5R (USB_BASE + 0x00000014) /!< Endpoint 5 register address /
		3863	#define USB_EP6R (USB_BASE + 0x00000018) /!< Endpoint 6 register address /
		3864	#define USB_EP7R (USB_BASE + 0x0000001C) /!< Endpoint 7 register address /
		3865
		3866	/* bit positions */
		3867	#define USB_EP_CTR_RX ((uint32_t)0x00008000) /!< EndPoint Correct TRansfer RX /
		3868	#define USB_EP_DTOG_RX ((uint32_t)0x00004000) /!< EndPoint Data TOGGLE RX /
		3869	#define USB_EPRX_STAT ((uint32_t)0x00003000) /!< EndPoint RX STATus bit field /
		3870	#define USB_EP_SETUP ((uint32_t)0x00000800) /!< EndPoint SETUP /
		3871	#define USB_EP_T_FIELD ((uint32_t)0x00000600) /!< EndPoint TYPE /
		3872	#define USB_EP_KIND ((uint32_t)0x00000100) /!< EndPoint KIND /
		3873	#define USB_EP_CTR_TX ((uint32_t)0x00000080) /!< EndPoint Correct TRansfer TX /
		3874	#define USB_EP_DTOG_TX ((uint32_t)0x00000040) /!< EndPoint Data TOGGLE TX /
		3875	#define USB_EPTX_STAT ((uint32_t)0x00000030) /!< EndPoint TX STATus bit field /
		3876	#define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /!< EndPoint ADDRess FIELD /
		3877
		3878	/* EndPoint REGister MASK (no toggle fields) */
		3879	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
		3880	/!< EP_TYPE[1:0] EndPoint TYPE /
		3881	#define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /!< EndPoint TYPE Mask /
		3882	#define USB_EP_BULK ((uint32_t)0x00000000) /!< EndPoint BULK /
		3883	#define USB_EP_CONTROL ((uint32_t)0x00000200) /!< EndPoint CONTROL /
		3884	#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /!< EndPoint ISOCHRONOUS /
		3885	#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /!< EndPoint INTERRUPT /
		3886	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
		3887
		3888	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
		3889	/!< STAT_TX[1:0] STATus for TX transfer /
		3890	#define USB_EP_TX_DIS ((uint32_t)0x00000000) /!< EndPoint TX DISabled /
		3891	#define USB_EP_TX_STALL ((uint32_t)0x00000010) /!< EndPoint TX STALLed /
		3892	#define USB_EP_TX_NAK ((uint32_t)0x00000020) /!< EndPoint TX NAKed /
		3893	#define USB_EP_TX_VALID ((uint32_t)0x00000030) /!< EndPoint TX VALID /
		3894	#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /!< EndPoint TX Data TOGgle bit1 /
		3895	#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /!< EndPoint TX Data TOGgle bit2 /
		3896	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
		3897	/!< STAT_RX[1:0] STATus for RX transfer /
		3898	#define USB_EP_RX_DIS ((uint32_t)0x00000000) /!< EndPoint RX DISabled /
		3899	#define USB_EP_RX_STALL ((uint32_t)0x00001000) /!< EndPoint RX STALLed /
		3900	#define USB_EP_RX_NAK ((uint32_t)0x00002000) /!< EndPoint RX NAKed /
		3901	#define USB_EP_RX_VALID ((uint32_t)0x00003000) /!< EndPoint RX VALID /
		3902	#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /!< EndPoint RX Data TOGgle bit1 /
		3903	#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /!< EndPoint RX Data TOGgle bit1 /
		3904	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
		3905
		3906	/***************** Bit definition for USB_EP0R register *****************/
		3907	#define USB_EP0R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3908
		3909	#define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3910	#define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3911	#define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3912
		3913	#define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3914	#define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3915	#define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3916
		3917	#define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3918	#define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3919	#define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3920
		3921	#define USB_EP0R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3922
		3923	#define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3924	#define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3925	#define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3926
		3927	#define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3928	#define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3929
		3930	/***************** Bit definition for USB_EP1R register *****************/
		3931	#define USB_EP1R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3932
		3933	#define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3934	#define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3935	#define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3936
		3937	#define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3938	#define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3939	#define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3940
		3941	#define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3942	#define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3943	#define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3944
		3945	#define USB_EP1R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3946
		3947	#define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3948	#define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3949	#define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3950
		3951	#define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3952	#define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3953
		3954	/***************** Bit definition for USB_EP2R register *****************/
		3955	#define USB_EP2R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3956
		3957	#define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3958	#define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3959	#define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3960
		3961	#define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3962	#define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3963	#define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3964
		3965	#define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3966	#define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3967	#define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3968
		3969	#define USB_EP2R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3970
		3971	#define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3972	#define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3973	#define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3974
		3975	#define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3976	#define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3977
		3978	/***************** Bit definition for USB_EP3R register *****************/
		3979	#define USB_EP3R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3980
		3981	#define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3982	#define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3983	#define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3984
		3985	#define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3986	#define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3987	#define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3988
		3989	#define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3990	#define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3991	#define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3992
		3993	#define USB_EP3R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3994
		3995	#define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3996	#define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3997	#define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3998
		3999	#define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		4000	#define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		4001
		4002	/***************** Bit definition for USB_EP4R register *****************/
		4003	#define USB_EP4R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		4004
		4005	#define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		4006	#define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		4007	#define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		4008
		4009	#define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		4010	#define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		4011	#define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		4012
		4013	#define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		4014	#define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		4015	#define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		4016
		4017	#define USB_EP4R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		4018
		4019	#define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		4020	#define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		4021	#define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		4022
		4023	#define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		4024	#define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		4025
		4026	/***************** Bit definition for USB_EP5R register *****************/
		4027	#define USB_EP5R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		4028
		4029	#define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		4030	#define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		4031	#define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		4032
		4033	#define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		4034	#define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		4035	#define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		4036
		4037	#define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		4038	#define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		4039	#define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		4040
		4041	#define USB_EP5R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		4042
		4043	#define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		4044	#define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		4045	#define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		4046
		4047	#define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		4048	#define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		4049
		4050	/***************** Bit definition for USB_EP6R register *****************/
		4051	#define USB_EP6R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		4052
		4053	#define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		4054	#define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		4055	#define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		4056
		4057	#define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		4058	#define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		4059	#define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		4060
		4061	#define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		4062	#define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		4063	#define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		4064
		4065	#define USB_EP6R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		4066
		4067	#define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		4068	#define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		4069	#define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		4070
		4071	#define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		4072	#define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		4073
		4074	/***************** Bit definition for USB_EP7R register *****************/
		4075	#define USB_EP7R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		4076
		4077	#define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		4078	#define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		4079	#define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		4080
		4081	#define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		4082	#define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		4083	#define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		4084
		4085	#define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		4086	#define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		4087	#define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		4088
		4089	#define USB_EP7R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		4090
		4091	#define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		4092	#define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		4093	#define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		4094
		4095	#define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		4096	#define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		4097
		4098	/!< Common registers /
		4099	/***************** Bit definition for USB_CNTR register *****************/
		4100	#define USB_CNTR_FRES ((uint32_t)0x00000001) /!< Force USB Reset /
		4101	#define USB_CNTR_PDWN ((uint32_t)0x00000002) /!< Power down /
		4102	#define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /!< Low-power mode /
		4103	#define USB_CNTR_FSUSP ((uint32_t)0x00000008) /!< Force suspend /
		4104	#define USB_CNTR_RESUME ((uint32_t)0x00000010) /!< Resume request /
		4105	#define USB_CNTR_ESOFM ((uint32_t)0x00000100) /!< Expected Start Of Frame Interrupt Mask /
		4106	#define USB_CNTR_SOFM ((uint32_t)0x00000200) /!< Start Of Frame Interrupt Mask /
		4107	#define USB_CNTR_RESETM ((uint32_t)0x00000400) /!< RESET Interrupt Mask /
		4108	#define USB_CNTR_SUSPM ((uint32_t)0x00000800) /!< Suspend mode Interrupt Mask /
		4109	#define USB_CNTR_WKUPM ((uint32_t)0x00001000) /!< Wakeup Interrupt Mask /
		4110	#define USB_CNTR_ERRM ((uint32_t)0x00002000) /!< Error Interrupt Mask /
		4111	#define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /!< Packet Memory Area Over / Underrun Interrupt Mask /
		4112	#define USB_CNTR_CTRM ((uint32_t)0x00008000) /!< Correct Transfer Interrupt Mask /
		4113
		4114	/***************** Bit definition for USB_ISTR register *****************/
		4115	#define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /!< Endpoint Identifier /
		4116	#define USB_ISTR_DIR ((uint32_t)0x00000010) /!< Direction of transaction /
		4117	#define USB_ISTR_ESOF ((uint32_t)0x00000100) /!< Expected Start Of Frame /
		4118	#define USB_ISTR_SOF ((uint32_t)0x00000200) /!< Start Of Frame /
		4119	#define USB_ISTR_RESET ((uint32_t)0x00000400) /!< USB RESET request /
		4120	#define USB_ISTR_SUSP ((uint32_t)0x00000800) /!< Suspend mode request /
		4121	#define USB_ISTR_WKUP ((uint32_t)0x00001000) /!< Wake up /
		4122	#define USB_ISTR_ERR ((uint32_t)0x00002000) /!< Error /
		4123	#define USB_ISTR_PMAOVR ((uint32_t)0x00004000) /!< Packet Memory Area Over / Underrun /
		4124	#define USB_ISTR_CTR ((uint32_t)0x00008000) /!< Correct Transfer /
		4125
		4126	/***************** Bit definition for USB_FNR register ******************/
		4127	#define USB_FNR_FN ((uint32_t)0x000007FF) /!< Frame Number /
		4128	#define USB_FNR_LSOF ((uint32_t)0x00001800) /!< Lost SOF /
		4129	#define USB_FNR_LCK ((uint32_t)0x00002000) /!< Locked /
		4130	#define USB_FNR_RXDM ((uint32_t)0x00004000) /!< Receive Data - Line Status /
		4131	#define USB_FNR_RXDP ((uint32_t)0x00008000) /!< Receive Data + Line Status /
		4132
		4133	/**************** Bit definition for USB_DADDR register *****************/
		4134	#define USB_DADDR_ADD ((uint32_t)0x0000007F) /!< ADD[6:0] bits (Device Address) /
		4135	#define USB_DADDR_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
		4136	#define USB_DADDR_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
		4137	#define USB_DADDR_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
		4138	#define USB_DADDR_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
		4139	#define USB_DADDR_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
		4140	#define USB_DADDR_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
		4141	#define USB_DADDR_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
		4142
		4143	#define USB_DADDR_EF ((uint32_t)0x00000080) /!< Enable Function /
		4144
		4145	/**************** Bit definition for USB_BTABLE register ****************/
		4146	#define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /!< Buffer Table /
		4147
		4148	/!< Buffer descriptor table /
		4149	/*************** Bit definition for USB_ADDR0_TX register ***************/
		4150	#define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 0 /
		4151
		4152	/*************** Bit definition for USB_ADDR1_TX register ***************/
		4153	#define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 1 /
		4154
		4155	/*************** Bit definition for USB_ADDR2_TX register ***************/
		4156	#define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 2 /
		4157
		4158	/*************** Bit definition for USB_ADDR3_TX register ***************/
		4159	#define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 3 /
		4160
		4161	/*************** Bit definition for USB_ADDR4_TX register ***************/
		4162	#define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 4 /
		4163
		4164	/*************** Bit definition for USB_ADDR5_TX register ***************/
		4165	#define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 5 /
		4166
		4167	/*************** Bit definition for USB_ADDR6_TX register ***************/
		4168	#define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 6 /
		4169
		4170	/*************** Bit definition for USB_ADDR7_TX register ***************/
		4171	#define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 7 /
		4172
		4173	/----------------------------------------------------------------------------/
		4174
		4175	/*************** Bit definition for USB_COUNT0_TX register **************/
		4176	#define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 /
		4177
		4178	/*************** Bit definition for USB_COUNT1_TX register **************/
		4179	#define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 /
		4180
		4181	/*************** Bit definition for USB_COUNT2_TX register **************/
		4182	#define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 /
		4183
		4184	/*************** Bit definition for USB_COUNT3_TX register **************/
		4185	#define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 /
		4186
		4187	/*************** Bit definition for USB_COUNT4_TX register **************/
		4188	#define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 /
		4189
		4190	/*************** Bit definition for USB_COUNT5_TX register **************/
		4191	#define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 /
		4192
		4193	/*************** Bit definition for USB_COUNT6_TX register **************/
		4194	#define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 /
		4195
		4196	/*************** Bit definition for USB_COUNT7_TX register **************/
		4197	#define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 /
		4198
		4199	/----------------------------------------------------------------------------/
		4200
		4201	/************** Bit definition for USB_COUNT0_TX_0 register *************/
		4202	#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 (low) /
		4203
		4204	/************** Bit definition for USB_COUNT0_TX_1 register *************/
		4205	#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 0 (high) /
		4206
		4207	/************** Bit definition for USB_COUNT1_TX_0 register *************/
		4208	#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 (low) /
		4209
		4210	/************** Bit definition for USB_COUNT1_TX_1 register *************/
		4211	#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 1 (high) /
		4212
		4213	/************** Bit definition for USB_COUNT2_TX_0 register *************/
		4214	#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 (low) /
		4215
		4216	/************** Bit definition for USB_COUNT2_TX_1 register *************/
		4217	#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 2 (high) /
		4218
		4219	/************** Bit definition for USB_COUNT3_TX_0 register *************/
		4220	#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 (low) /
		4221
		4222	/************** Bit definition for USB_COUNT3_TX_1 register *************/
		4223	#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 3 (high) /
		4224
		4225	/************** Bit definition for USB_COUNT4_TX_0 register *************/
		4226	#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 (low) /
		4227
		4228	/************** Bit definition for USB_COUNT4_TX_1 register *************/
		4229	#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 4 (high) /
		4230
		4231	/************** Bit definition for USB_COUNT5_TX_0 register *************/
		4232	#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 (low) /
		4233
		4234	/************** Bit definition for USB_COUNT5_TX_1 register *************/
		4235	#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 5 (high) /
		4236
		4237	/************** Bit definition for USB_COUNT6_TX_0 register *************/
		4238	#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 (low) /
		4239
		4240	/************** Bit definition for USB_COUNT6_TX_1 register *************/
		4241	#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 6 (high) /
		4242
		4243	/************** Bit definition for USB_COUNT7_TX_0 register *************/
		4244	#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 (low) /
		4245
		4246	/************** Bit definition for USB_COUNT7_TX_1 register *************/
		4247	#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 7 (high) /
		4248
		4249	/----------------------------------------------------------------------------/
		4250
		4251	/*************** Bit definition for USB_ADDR0_RX register ***************/
		4252	#define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 0 /
		4253
		4254	/*************** Bit definition for USB_ADDR1_RX register ***************/
		4255	#define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 1 /
		4256
		4257	/*************** Bit definition for USB_ADDR2_RX register ***************/
		4258	#define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 2 /
		4259
		4260	/*************** Bit definition for USB_ADDR3_RX register ***************/
		4261	#define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 3 /
		4262
		4263	/*************** Bit definition for USB_ADDR4_RX register ***************/
		4264	#define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 4 /
		4265
		4266	/*************** Bit definition for USB_ADDR5_RX register ***************/
		4267	#define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 5 /
		4268
		4269	/*************** Bit definition for USB_ADDR6_RX register ***************/
		4270	#define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 6 /
		4271
		4272	/*************** Bit definition for USB_ADDR7_RX register ***************/
		4273	#define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 7 /
		4274
		4275	/----------------------------------------------------------------------------/
		4276
		4277	/*************** Bit definition for USB_COUNT0_RX register **************/
		4278	#define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		4279
		4280	#define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		4281	#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4282	#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4283	#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4284	#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4285	#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4286
		4287	#define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		4288
		4289	/*************** Bit definition for USB_COUNT1_RX register **************/
		4290	#define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		4291
		4292	#define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		4293	#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4294	#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4295	#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4296	#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4297	#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4298
		4299	#define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		4300
		4301	/*************** Bit definition for USB_COUNT2_RX register **************/
		4302	#define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		4303
		4304	#define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		4305	#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4306	#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4307	#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4308	#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4309	#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4310
		4311	#define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		4312
		4313	/*************** Bit definition for USB_COUNT3_RX register **************/
		4314	#define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		4315
		4316	#define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		4317	#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4318	#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4319	#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4320	#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4321	#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4322
		4323	#define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		4324
		4325	/*************** Bit definition for USB_COUNT4_RX register **************/
		4326	#define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		4327
		4328	#define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		4329	#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4330	#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4331	#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4332	#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4333	#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4334
		4335	#define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		4336
		4337	/*************** Bit definition for USB_COUNT5_RX register **************/
		4338	#define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		4339
		4340	#define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		4341	#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4342	#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4343	#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4344	#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4345	#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4346
		4347	#define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		4348
		4349	/*************** Bit definition for USB_COUNT6_RX register **************/
		4350	#define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		4351
		4352	#define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		4353	#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4354	#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4355	#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4356	#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4357	#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4358
		4359	#define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		4360
		4361	/*************** Bit definition for USB_COUNT7_RX register **************/
		4362	#define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		4363
		4364	#define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		4365	#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4366	#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4367	#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4368	#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4369	#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4370
		4371	#define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		4372
		4373	/----------------------------------------------------------------------------/
		4374
		4375	/************** Bit definition for USB_COUNT0_RX_0 register *************/
		4376	#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		4377
		4378	#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		4379	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4380	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4381	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4382	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4383	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4384
		4385	#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		4386
		4387	/************** Bit definition for USB_COUNT0_RX_1 register *************/
		4388	#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		4389
		4390	#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		4391	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 1 /
		4392	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		4393	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		4394	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		4395	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		4396
		4397	#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		4398
		4399	/************** Bit definition for USB_COUNT1_RX_0 register *************/
		4400	#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		4401
		4402	#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		4403	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4404	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4405	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4406	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4407	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4408
		4409	#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		4410
		4411	/************** Bit definition for USB_COUNT1_RX_1 register *************/
		4412	#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		4413
		4414	#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		4415	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		4416	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		4417	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		4418	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		4419	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		4420
		4421	#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		4422
		4423	/************** Bit definition for USB_COUNT2_RX_0 register *************/
		4424	#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		4425
		4426	#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		4427	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4428	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4429	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4430	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4431	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4432
		4433	#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		4434
		4435	/************** Bit definition for USB_COUNT2_RX_1 register *************/
		4436	#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		4437
		4438	#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		4439	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		4440	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		4441	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		4442	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		4443	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		4444
		4445	#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		4446
		4447	/************** Bit definition for USB_COUNT3_RX_0 register *************/
		4448	#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		4449
		4450	#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		4451	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4452	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4453	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4454	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4455	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4456
		4457	#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		4458
		4459	/************** Bit definition for USB_COUNT3_RX_1 register *************/
		4460	#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		4461
		4462	#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		4463	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		4464	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		4465	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		4466	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		4467	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		4468
		4469	#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		4470
		4471	/************** Bit definition for USB_COUNT4_RX_0 register *************/
		4472	#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		4473
		4474	#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		4475	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4476	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4477	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4478	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4479	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4480
		4481	#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		4482
		4483	/************** Bit definition for USB_COUNT4_RX_1 register *************/
		4484	#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		4485
		4486	#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		4487	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		4488	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		4489	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		4490	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		4491	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		4492
		4493	#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		4494
		4495	/************** Bit definition for USB_COUNT5_RX_0 register *************/
		4496	#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		4497
		4498	#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		4499	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4500	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4501	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4502	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4503	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4504
		4505	#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		4506
		4507	/************** Bit definition for USB_COUNT5_RX_1 register *************/
		4508	#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		4509
		4510	#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		4511	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		4512	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		4513	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		4514	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		4515	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		4516
		4517	#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		4518
		4519	/************* Bit definition for USB_COUNT6_RX_0 register *************/
		4520	#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		4521
		4522	#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		4523	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4524	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4525	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4526	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4527	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4528
		4529	#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		4530
		4531	/************** Bit definition for USB_COUNT6_RX_1 register *************/
		4532	#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		4533
		4534	#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		4535	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		4536	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		4537	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		4538	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		4539	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		4540
		4541	#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		4542
		4543	/************* Bit definition for USB_COUNT7_RX_0 register **************/
		4544	#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		4545
		4546	#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		4547	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		4548	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		4549	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		4550	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		4551	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		4552
		4553	#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		4554
		4555	/************* Bit definition for USB_COUNT7_RX_1 register **************/
		4556	#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		4557
		4558	#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		4559	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		4560	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		4561	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		4562	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		4563	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		4564
		4565	#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		4566
		4567	/******************************************************************************/
		4568	/* */
		4569	/* Controller Area Network */
		4570	/* */
		4571	/******************************************************************************/
		4572
		4573	/!< CAN control and status registers /
		4574	/***************** Bit definition for CAN_MCR register ******************/
		4575	#define CAN_MCR_INRQ ((uint32_t)0x00000001) /!< Initialization Request /
		4576	#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /!< Sleep Mode Request /
		4577	#define CAN_MCR_TXFP ((uint32_t)0x00000004) /!< Transmit FIFO Priority /
		4578	#define CAN_MCR_RFLM ((uint32_t)0x00000008) /!< Receive FIFO Locked Mode /
		4579	#define CAN_MCR_NART ((uint32_t)0x00000010) /!< No Automatic Retransmission /
		4580	#define CAN_MCR_AWUM ((uint32_t)0x00000020) /!< Automatic Wakeup Mode /
		4581	#define CAN_MCR_ABOM ((uint32_t)0x00000040) /!< Automatic Bus-Off Management /
		4582	#define CAN_MCR_TTCM ((uint32_t)0x00000080) /!< Time Triggered Communication Mode /
		4583	#define CAN_MCR_RESET ((uint32_t)0x00008000) /!< CAN software master reset /
		4584	#define CAN_MCR_DBF ((uint32_t)0x00010000) /!< CAN Debug freeze /
		4585
		4586	/***************** Bit definition for CAN_MSR register ******************/
		4587	#define CAN_MSR_INAK ((uint32_t)0x00000001) /!< Initialization Acknowledge /
		4588	#define CAN_MSR_SLAK ((uint32_t)0x00000002) /!< Sleep Acknowledge /
		4589	#define CAN_MSR_ERRI ((uint32_t)0x00000004) /!< Error Interrupt /
		4590	#define CAN_MSR_WKUI ((uint32_t)0x00000008) /!< Wakeup Interrupt /
		4591	#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /!< Sleep Acknowledge Interrupt /
		4592	#define CAN_MSR_TXM ((uint32_t)0x00000100) /!< Transmit Mode /
		4593	#define CAN_MSR_RXM ((uint32_t)0x00000200) /!< Receive Mode /
		4594	#define CAN_MSR_SAMP ((uint32_t)0x00000400) /!< Last Sample Point /
		4595	#define CAN_MSR_RX ((uint32_t)0x00000800) /!< CAN Rx Signal /
		4596
		4597	/***************** Bit definition for CAN_TSR register ******************/
		4598	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!< Request Completed Mailbox0 /
		4599	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!< Transmission OK of Mailbox0 /
		4600	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!< Arbitration Lost for Mailbox0 /
		4601	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!< Transmission Error of Mailbox0 /
		4602	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!< Abort Request for Mailbox0 /
		4603	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!< Request Completed Mailbox1 /
		4604	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!< Transmission OK of Mailbox1 /
		4605	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!< Arbitration Lost for Mailbox1 /
		4606	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!< Transmission Error of Mailbox1 /
		4607	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!< Abort Request for Mailbox 1 /
		4608	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!< Request Completed Mailbox2 /
		4609	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!< Transmission OK of Mailbox 2 /
		4610	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!< Arbitration Lost for mailbox 2 /
		4611	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!< Transmission Error of Mailbox 2 /
		4612	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!< Abort Request for Mailbox 2 /
		4613	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!< Mailbox Code /
		4614
		4615	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!< TME[2:0] bits /
		4616	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!< Transmit Mailbox 0 Empty /
		4617	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!< Transmit Mailbox 1 Empty /
		4618	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!< Transmit Mailbox 2 Empty /
		4619
		4620	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!< LOW[2:0] bits /
		4621	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!< Lowest Priority Flag for Mailbox 0 /
		4622	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!< Lowest Priority Flag for Mailbox 1 /
		4623	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!< Lowest Priority Flag for Mailbox 2 /
		4624
		4625	/***************** Bit definition for CAN_RF0R register *****************/
		4626	#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /!< FIFO 0 Message Pending /
		4627	#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /!< FIFO 0 Full /
		4628	#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /!< FIFO 0 Overrun /
		4629	#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /!< Release FIFO 0 Output Mailbox /
		4630
		4631	/***************** Bit definition for CAN_RF1R register *****************/
		4632	#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /!< FIFO 1 Message Pending /
		4633	#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /!< FIFO 1 Full /
		4634	#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /!< FIFO 1 Overrun /
		4635	#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /!< Release FIFO 1 Output Mailbox /
		4636
		4637	/****************** Bit definition for CAN_IER register *****************/
		4638	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!< Transmit Mailbox Empty Interrupt Enable /
		4639	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!< FIFO Message Pending Interrupt Enable /
		4640	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!< FIFO Full Interrupt Enable /
		4641	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!< FIFO Overrun Interrupt Enable /
		4642	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!< FIFO Message Pending Interrupt Enable /
		4643	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!< FIFO Full Interrupt Enable /
		4644	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!< FIFO Overrun Interrupt Enable /
		4645	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!< Error Warning Interrupt Enable /
		4646	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!< Error Passive Interrupt Enable /
		4647	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!< Bus-Off Interrupt Enable /
		4648	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!< Last Error Code Interrupt Enable /
		4649	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!< Error Interrupt Enable /
		4650	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!< Wakeup Interrupt Enable /
		4651	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!< Sleep Interrupt Enable /
		4652
		4653	/****************** Bit definition for CAN_ESR register *****************/
		4654	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!< Error Warning Flag /
		4655	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!< Error Passive Flag /
		4656	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!< Bus-Off Flag /
		4657
		4658	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!< LEC[2:0] bits (Last Error Code) /
		4659	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!< Bit 0 /
		4660	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!< Bit 1 /
		4661	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!< Bit 2 /
		4662
		4663	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!< Least significant byte of the 9-bit Transmit Error Counter /
		4664	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!< Receive Error Counter /
		4665
		4666	/***************** Bit definition for CAN_BTR register ******************/
		4667	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
		4668	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
		4669	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Time Segment 1 (Bit 0) /
		4670	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Time Segment 1 (Bit 1) /
		4671	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Time Segment 1 (Bit 2) /
		4672	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Time Segment 1 (Bit 3) /
		4673	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
		4674	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Time Segment 2 (Bit 0) /
		4675	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Time Segment 2 (Bit 1) /
		4676	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Time Segment 2 (Bit 2) /
		4677	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
		4678	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Resynchronization Jump Width (Bit 0) /
		4679	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Resynchronization Jump Width (Bit 1) /
		4680	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
		4681	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
		4682
		4683	/!< Mailbox registers /
		4684	/**************** Bit definition for CAN_TI0R register ******************/
		4685	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
		4686	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		4687	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		4688	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
		4689	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		4690
		4691	/**************** Bit definition for CAN_TDT0R register *****************/
		4692	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		4693	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
		4694	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		4695
		4696	/**************** Bit definition for CAN_TDL0R register *****************/
		4697	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		4698	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		4699	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		4700	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		4701
		4702	/**************** Bit definition for CAN_TDH0R register *****************/
		4703	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		4704	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		4705	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		4706	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		4707
		4708	/***************** Bit definition for CAN_TI1R register *****************/
		4709	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
		4710	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		4711	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		4712	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
		4713	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		4714
		4715	/***************** Bit definition for CAN_TDT1R register ****************/
		4716	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		4717	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
		4718	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		4719
		4720	/***************** Bit definition for CAN_TDL1R register ****************/
		4721	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		4722	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		4723	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		4724	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		4725
		4726	/***************** Bit definition for CAN_TDH1R register ****************/
		4727	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		4728	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		4729	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		4730	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		4731
		4732	/***************** Bit definition for CAN_TI2R register *****************/
		4733	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
		4734	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		4735	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		4736	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
		4737	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		4738
		4739	/***************** Bit definition for CAN_TDT2R register ****************/
		4740	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		4741	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
		4742	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		4743
		4744	/***************** Bit definition for CAN_TDL2R register ****************/
		4745	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		4746	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		4747	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		4748	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		4749
		4750	/***************** Bit definition for CAN_TDH2R register ****************/
		4751	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		4752	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		4753	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		4754	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		4755
		4756	/***************** Bit definition for CAN_RI0R register *****************/
		4757	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		4758	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		4759	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
		4760	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		4761
		4762	/***************** Bit definition for CAN_RDT0R register ****************/
		4763	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		4764	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
		4765	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		4766
		4767	/***************** Bit definition for CAN_RDL0R register ****************/
		4768	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		4769	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		4770	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		4771	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		4772
		4773	/***************** Bit definition for CAN_RDH0R register ****************/
		4774	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		4775	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		4776	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		4777	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		4778
		4779	/***************** Bit definition for CAN_RI1R register *****************/
		4780	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
		4781	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
		4782	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
		4783	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
		4784
		4785	/***************** Bit definition for CAN_RDT1R register ****************/
		4786	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
		4787	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
		4788	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
		4789
		4790	/***************** Bit definition for CAN_RDL1R register ****************/
		4791	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
		4792	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
		4793	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
		4794	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
		4795
		4796	/***************** Bit definition for CAN_RDH1R register ****************/
		4797	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
		4798	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
		4799	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
		4800	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
		4801
		4802	/!< CAN filter registers /
		4803	/***************** Bit definition for CAN_FMR register ******************/
		4804	#define CAN_FMR_FINIT ((uint32_t)0x00000001) /!< Filter Init Mode /
		4805	#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /!< CAN2 start bank /
		4806
		4807	/***************** Bit definition for CAN_FM1R register *****************/
		4808	#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /!< Filter Mode /
		4809	#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /!< Filter Init Mode for filter 0 /
		4810	#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /!< Filter Init Mode for filter 1 /
		4811	#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /!< Filter Init Mode for filter 2 /
		4812	#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /!< Filter Init Mode for filter 3 /
		4813	#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /!< Filter Init Mode for filter 4 /
		4814	#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /!< Filter Init Mode for filter 5 /
		4815	#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /!< Filter Init Mode for filter 6 /
		4816	#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /!< Filter Init Mode for filter 7 /
		4817	#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /!< Filter Init Mode for filter 8 /
		4818	#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /!< Filter Init Mode for filter 9 /
		4819	#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /!< Filter Init Mode for filter 10 /
		4820	#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /!< Filter Init Mode for filter 11 /
		4821	#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /!< Filter Init Mode for filter 12 /
		4822	#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /!< Filter Init Mode for filter 13 /
		4823
		4824	/***************** Bit definition for CAN_FS1R register *****************/
		4825	#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /!< Filter Scale Configuration /
		4826	#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /!< Filter Scale Configuration for filter 0 /
		4827	#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /!< Filter Scale Configuration for filter 1 /
		4828	#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /!< Filter Scale Configuration for filter 2 /
		4829	#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /!< Filter Scale Configuration for filter 3 /
		4830	#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /!< Filter Scale Configuration for filter 4 /
		4831	#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /!< Filter Scale Configuration for filter 5 /
		4832	#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /!< Filter Scale Configuration for filter 6 /
		4833	#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /!< Filter Scale Configuration for filter 7 /
		4834	#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /!< Filter Scale Configuration for filter 8 /
		4835	#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /!< Filter Scale Configuration for filter 9 /
		4836	#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /!< Filter Scale Configuration for filter 10 /
		4837	#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /!< Filter Scale Configuration for filter 11 /
		4838	#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /!< Filter Scale Configuration for filter 12 /
		4839	#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /!< Filter Scale Configuration for filter 13 /
		4840
		4841	/**************** Bit definition for CAN_FFA1R register *****************/
		4842	#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /!< Filter FIFO Assignment /
		4843	#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /!< Filter FIFO Assignment for filter 0 /
		4844	#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /!< Filter FIFO Assignment for filter 1 /
		4845	#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /!< Filter FIFO Assignment for filter 2 /
		4846	#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /!< Filter FIFO Assignment for filter 3 /
		4847	#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /!< Filter FIFO Assignment for filter 4 /
		4848	#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /!< Filter FIFO Assignment for filter 5 /
		4849	#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /!< Filter FIFO Assignment for filter 6 /
		4850	#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /!< Filter FIFO Assignment for filter 7 /
		4851	#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /!< Filter FIFO Assignment for filter 8 /
		4852	#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /!< Filter FIFO Assignment for filter 9 /
		4853	#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /!< Filter FIFO Assignment for filter 10 /
		4854	#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /!< Filter FIFO Assignment for filter 11 /
		4855	#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /!< Filter FIFO Assignment for filter 12 /
		4856	#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /!< Filter FIFO Assignment for filter 13 /
		4857
		4858	/***************** Bit definition for CAN_FA1R register *****************/
		4859	#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /!< Filter Active /
		4860	#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /!< Filter 0 Active /
		4861	#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /!< Filter 1 Active /
		4862	#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /!< Filter 2 Active /
		4863	#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /!< Filter 3 Active /
		4864	#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /!< Filter 4 Active /
		4865	#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /!< Filter 5 Active /
		4866	#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /!< Filter 6 Active /
		4867	#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /!< Filter 7 Active /
		4868	#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /!< Filter 8 Active /
		4869	#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /!< Filter 9 Active /
		4870	#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /!< Filter 10 Active /
		4871	#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /!< Filter 11 Active /
		4872	#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /!< Filter 12 Active /
		4873	#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /!< Filter 13 Active /
		4874
		4875	/***************** Bit definition for CAN_F0R1 register *****************/
		4876	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4877	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4878	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4879	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4880	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4881	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4882	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4883	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4884	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4885	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4886	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4887	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4888	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4889	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4890	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4891	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4892	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4893	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4894	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4895	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4896	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4897	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4898	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4899	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4900	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4901	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4902	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4903	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4904	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4905	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4906	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4907	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4908
		4909	/***************** Bit definition for CAN_F1R1 register *****************/
		4910	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4911	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4912	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4913	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4914	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4915	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4916	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4917	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4918	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4919	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4920	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4921	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4922	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4923	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4924	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4925	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4926	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4927	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4928	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4929	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4930	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4931	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4932	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4933	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4934	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4935	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4936	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4937	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4938	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4939	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4940	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4941	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4942
		4943	/***************** Bit definition for CAN_F2R1 register *****************/
		4944	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4945	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4946	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4947	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4948	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4949	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4950	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4951	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4952	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4953	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4954	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4955	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4956	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4957	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4958	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4959	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4960	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4961	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4962	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4963	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4964	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4965	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		4966	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		4967	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		4968	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		4969	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		4970	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		4971	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		4972	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		4973	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		4974	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		4975	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		4976
		4977	/***************** Bit definition for CAN_F3R1 register *****************/
		4978	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		4979	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		4980	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		4981	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		4982	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		4983	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		4984	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		4985	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		4986	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		4987	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		4988	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		4989	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		4990	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		4991	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		4992	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		4993	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		4994	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		4995	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		4996	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		4997	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		4998	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		4999	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5000	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5001	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5002	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5003	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5004	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5005	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5006	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5007	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5008	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5009	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5010
		5011	/***************** Bit definition for CAN_F4R1 register *****************/
		5012	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5013	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5014	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5015	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5016	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5017	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5018	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5019	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5020	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5021	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5022	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5023	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5024	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5025	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5026	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5027	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5028	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5029	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5030	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5031	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5032	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5033	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5034	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5035	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5036	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5037	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5038	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5039	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5040	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5041	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5042	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5043	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5044
		5045	/***************** Bit definition for CAN_F5R1 register *****************/
		5046	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5047	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5048	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5049	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5050	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5051	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5052	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5053	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5054	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5055	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5056	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5057	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5058	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5059	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5060	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5061	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5062	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5063	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5064	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5065	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5066	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5067	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5068	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5069	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5070	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5071	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5072	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5073	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5074	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5075	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5076	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5077	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5078
		5079	/***************** Bit definition for CAN_F6R1 register *****************/
		5080	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5081	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5082	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5083	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5084	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5085	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5086	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5087	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5088	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5089	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5090	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5091	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5092	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5093	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5094	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5095	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5096	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5097	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5098	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5099	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5100	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5101	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5102	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5103	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5104	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5105	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5106	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5107	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5108	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5109	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5110	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5111	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5112
		5113	/***************** Bit definition for CAN_F7R1 register *****************/
		5114	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5115	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5116	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5117	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5118	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5119	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5120	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5121	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5122	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5123	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5124	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5125	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5126	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5127	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5128	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5129	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5130	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5131	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5132	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5133	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5134	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5135	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5136	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5137	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5138	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5139	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5140	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5141	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5142	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5143	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5144	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5145	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5146
		5147	/***************** Bit definition for CAN_F8R1 register *****************/
		5148	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5149	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5150	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5151	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5152	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5153	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5154	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5155	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5156	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5157	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5158	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5159	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5160	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5161	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5162	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5163	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5164	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5165	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5166	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5167	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5168	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5169	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5170	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5171	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5172	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5173	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5174	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5175	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5176	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5177	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5178	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5179	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5180
		5181	/***************** Bit definition for CAN_F9R1 register *****************/
		5182	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5183	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5184	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5185	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5186	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5187	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5188	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5189	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5190	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5191	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5192	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5193	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5194	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5195	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5196	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5197	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5198	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5199	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5200	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5201	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5202	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5203	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5204	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5205	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5206	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5207	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5208	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5209	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5210	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5211	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5212	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5213	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5214
		5215	/***************** Bit definition for CAN_F10R1 register ****************/
		5216	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5217	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5218	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5219	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5220	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5221	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5222	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5223	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5224	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5225	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5226	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5227	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5228	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5229	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5230	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5231	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5232	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5233	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5234	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5235	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5236	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5237	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5238	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5239	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5240	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5241	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5242	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5243	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5244	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5245	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5246	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5247	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5248
		5249	/***************** Bit definition for CAN_F11R1 register ****************/
		5250	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5251	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5252	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5253	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5254	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5255	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5256	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5257	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5258	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5259	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5260	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5261	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5262	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5263	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5264	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5265	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5266	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5267	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5268	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5269	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5270	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5271	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5272	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5273	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5274	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5275	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5276	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5277	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5278	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5279	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5280	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5281	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5282
		5283	/***************** Bit definition for CAN_F12R1 register ****************/
		5284	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5285	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5286	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5287	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5288	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5289	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5290	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5291	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5292	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5293	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5294	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5295	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5296	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5297	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5298	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5299	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5300	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5301	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5302	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5303	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5304	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5305	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5306	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5307	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5308	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5309	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5310	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5311	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5312	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5313	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5314	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5315	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5316
		5317	/***************** Bit definition for CAN_F13R1 register ****************/
		5318	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5319	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5320	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5321	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5322	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5323	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5324	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5325	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5326	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5327	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5328	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5329	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5330	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5331	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5332	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5333	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5334	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5335	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5336	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5337	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5338	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5339	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5340	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5341	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5342	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5343	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5344	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5345	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5346	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5347	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5348	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5349	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5350
		5351	/***************** Bit definition for CAN_F0R2 register *****************/
		5352	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5353	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5354	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5355	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5356	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5357	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5358	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5359	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5360	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5361	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5362	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5363	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5364	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5365	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5366	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5367	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5368	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5369	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5370	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5371	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5372	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5373	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5374	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5375	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5376	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5377	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5378	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5379	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5380	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5381	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5382	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5383	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5384
		5385	/***************** Bit definition for CAN_F1R2 register *****************/
		5386	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5387	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5388	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5389	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5390	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5391	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5392	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5393	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5394	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5395	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5396	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5397	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5398	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5399	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5400	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5401	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5402	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5403	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5404	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5405	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5406	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5407	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5408	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5409	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5410	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5411	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5412	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5413	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5414	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5415	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5416	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5417	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5418
		5419	/***************** Bit definition for CAN_F2R2 register *****************/
		5420	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5421	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5422	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5423	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5424	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5425	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5426	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5427	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5428	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5429	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5430	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5431	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5432	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5433	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5434	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5435	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5436	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5437	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5438	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5439	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5440	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5441	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5442	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5443	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5444	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5445	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5446	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5447	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5448	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5449	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5450	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5451	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5452
		5453	/***************** Bit definition for CAN_F3R2 register *****************/
		5454	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5455	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5456	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5457	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5458	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5459	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5460	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5461	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5462	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5463	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5464	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5465	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5466	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5467	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5468	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5469	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5470	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5471	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5472	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5473	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5474	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5475	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5476	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5477	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5478	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5479	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5480	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5481	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5482	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5483	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5484	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5485	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5486
		5487	/***************** Bit definition for CAN_F4R2 register *****************/
		5488	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5489	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5490	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5491	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5492	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5493	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5494	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5495	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5496	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5497	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5498	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5499	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5500	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5501	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5502	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5503	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5504	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5505	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5506	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5507	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5508	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5509	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5510	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5511	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5512	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5513	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5514	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5515	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5516	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5517	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5518	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5519	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5520
		5521	/***************** Bit definition for CAN_F5R2 register *****************/
		5522	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5523	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5524	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5525	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5526	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5527	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5528	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5529	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5530	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5531	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5532	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5533	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5534	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5535	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5536	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5537	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5538	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5539	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5540	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5541	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5542	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5543	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5544	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5545	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5546	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5547	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5548	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5549	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5550	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5551	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5552	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5553	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5554
		5555	/***************** Bit definition for CAN_F6R2 register *****************/
		5556	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5557	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5558	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5559	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5560	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5561	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5562	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5563	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5564	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5565	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5566	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5567	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5568	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5569	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5570	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5571	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5572	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5573	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5574	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5575	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5576	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5577	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5578	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5579	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5580	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5581	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5582	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5583	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5584	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5585	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5586	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5587	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5588
		5589	/***************** Bit definition for CAN_F7R2 register *****************/
		5590	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5591	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5592	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5593	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5594	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5595	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5596	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5597	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5598	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5599	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5600	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5601	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5602	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5603	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5604	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5605	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5606	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5607	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5608	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5609	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5610	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5611	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5612	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5613	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5614	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5615	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5616	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5617	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5618	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5619	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5620	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5621	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5622
		5623	/***************** Bit definition for CAN_F8R2 register *****************/
		5624	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5625	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5626	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5627	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5628	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5629	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5630	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5631	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5632	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5633	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5634	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5635	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5636	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5637	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5638	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5639	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5640	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5641	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5642	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5643	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5644	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5645	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5646	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5647	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5648	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5649	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5650	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5651	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5652	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5653	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5654	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5655	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5656
		5657	/***************** Bit definition for CAN_F9R2 register *****************/
		5658	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5659	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5660	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5661	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5662	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5663	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5664	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5665	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5666	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5667	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5668	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5669	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5670	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5671	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5672	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5673	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5674	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5675	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5676	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5677	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5678	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5679	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5680	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5681	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5682	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5683	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5684	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5685	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5686	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5687	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5688	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5689	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5690
		5691	/***************** Bit definition for CAN_F10R2 register ****************/
		5692	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5693	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5694	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5695	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5696	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5697	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5698	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5699	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5700	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5701	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5702	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5703	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5704	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5705	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5706	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5707	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5708	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5709	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5710	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5711	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5712	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5713	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5714	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5715	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5716	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5717	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5718	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5719	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5720	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5721	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5722	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5723	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5724
		5725	/***************** Bit definition for CAN_F11R2 register ****************/
		5726	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5727	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5728	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5729	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5730	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5731	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5732	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5733	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5734	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5735	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5736	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5737	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5738	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5739	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5740	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5741	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5742	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5743	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5744	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5745	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5746	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5747	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5748	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5749	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5750	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5751	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5752	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5753	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5754	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5755	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5756	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5757	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5758
		5759	/***************** Bit definition for CAN_F12R2 register ****************/
		5760	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5761	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5762	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5763	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5764	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5765	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5766	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5767	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5768	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5769	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5770	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5771	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5772	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5773	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5774	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5775	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5776	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5777	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5778	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5779	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5780	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5781	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5782	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5783	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5784	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5785	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5786	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5787	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5788	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5789	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5790	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5791	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5792
		5793	/***************** Bit definition for CAN_F13R2 register ****************/
		5794	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
		5795	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
		5796	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
		5797	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
		5798	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
		5799	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
		5800	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
		5801	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
		5802	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
		5803	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
		5804	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
		5805	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
		5806	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
		5807	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
		5808	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
		5809	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
		5810	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
		5811	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
		5812	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
		5813	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
		5814	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
		5815	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
		5816	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
		5817	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
		5818	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
		5819	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
		5820	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
		5821	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
		5822	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
		5823	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
		5824	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
		5825	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
		5826
		5827	/******************************************************************************/
		5828	/* */
		5829	/* Serial Peripheral Interface */
		5830	/* */
		5831	/******************************************************************************/
		5832
		5833	/***************** Bit definition for SPI_CR1 register ******************/
		5834	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
		5835	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
		5836	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
		5837
		5838	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
		5839	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
		5840	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
		5841	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
		5842
		5843	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
		5844	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
		5845	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
		5846	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
		5847	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
		5848	#define SPI_CR1_DFF ((uint32_t)0x00000800) /!< Data Frame Format /
		5849	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
		5850	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
		5851	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
		5852	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
		5853
		5854	/***************** Bit definition for SPI_CR2 register ******************/
		5855	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
		5856	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
		5857	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
		5858	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
		5859	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
		5860	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
		5861
		5862	/****************** Bit definition for SPI_SR register ******************/
		5863	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
		5864	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
		5865	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
		5866	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
		5867	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
		5868	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
		5869	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
		5870	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
		5871
		5872	/****************** Bit definition for SPI_DR register ******************/
		5873	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!< Data Register /
		5874
		5875	/***************** Bit definition for SPI_CRCPR register ****************/
		5876	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!< CRC polynomial register /
		5877
		5878	/**************** Bit definition for SPI_RXCRCR register ****************/
		5879	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!< Rx CRC Register /
		5880
		5881	/**************** Bit definition for SPI_TXCRCR register ****************/
		5882	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!< Tx CRC Register /
		5883
		5884	/**************** Bit definition for SPI_I2SCFGR register ***************/
		5885	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!< Channel length (number of bits per audio channel) /
		5886
		5887	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!< DATLEN[1:0] bits (Data length to be transferred) /
		5888	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!< Bit 0 /
		5889	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!< Bit 1 /
		5890
		5891	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!< steady state clock polarity /
		5892
		5893	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!< I2SSTD[1:0] bits (I2S standard selection) /
		5894	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!< Bit 0 /
		5895	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!< Bit 1 /
		5896
		5897	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!< PCM frame synchronization /
		5898
		5899	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!< I2SCFG[1:0] bits (I2S configuration mode) /
		5900	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!< Bit 0 /
		5901	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!< Bit 1 /
		5902
		5903	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!< I2S Enable /
		5904	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!< I2S mode selection /
		5905
		5906	/**************** Bit definition for SPI_I2SPR register *****************/
		5907	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!< I2S Linear prescaler /
		5908	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!< Odd factor for the prescaler /
		5909	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!< Master Clock Output Enable /
		5910
		5911	/******************************************************************************/
		5912	/* */
		5913	/* Inter-integrated Circuit Interface */
		5914	/* */
		5915	/******************************************************************************/
		5916
		5917	/***************** Bit definition for I2C_CR1 register ******************/
		5918	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
		5919	#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /!< SMBus Mode /
		5920	#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /!< SMBus Type /
		5921	#define I2C_CR1_ENARP ((uint32_t)0x00000010) /!< ARP Enable /
		5922	#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /!< PEC Enable /
		5923	#define I2C_CR1_ENGC ((uint32_t)0x00000040) /!< General Call Enable /
		5924	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /!< Clock Stretching Disable (Slave mode) /
		5925	#define I2C_CR1_START ((uint32_t)0x00000100) /!< Start Generation /
		5926	#define I2C_CR1_STOP ((uint32_t)0x00000200) /!< Stop Generation /
		5927	#define I2C_CR1_ACK ((uint32_t)0x00000400) /!< Acknowledge Enable /
		5928	#define I2C_CR1_POS ((uint32_t)0x00000800) /!< Acknowledge/PEC Position (for data reception) /
		5929	#define I2C_CR1_PEC ((uint32_t)0x00001000) /!< Packet Error Checking /
		5930	#define I2C_CR1_ALERT ((uint32_t)0x00002000) /!< SMBus Alert /
		5931	#define I2C_CR1_SWRST ((uint32_t)0x00008000) /!< Software Reset /
		5932
		5933	/***************** Bit definition for I2C_CR2 register ******************/
		5934	#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
		5935	#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /!< Bit 0 /
		5936	#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /!< Bit 1 /
		5937	#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /!< Bit 2 /
		5938	#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /!< Bit 3 /
		5939	#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /!< Bit 4 /
		5940	#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /!< Bit 5 /
		5941
		5942	#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /!< Error Interrupt Enable /
		5943	#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /!< Event Interrupt Enable /
		5944	#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /!< Buffer Interrupt Enable /
		5945	#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /!< DMA Requests Enable /
		5946	#define I2C_CR2_LAST ((uint32_t)0x00001000) /!< DMA Last Transfer /
		5947
		5948	/***************** Bit definition for I2C_OAR1 register *****************/
		5949	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
		5950	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
		5951
		5952	#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
		5953	#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
		5954	#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
		5955	#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
		5956	#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
		5957	#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
		5958	#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
		5959	#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /!< Bit 7 /
		5960	#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /!< Bit 8 /
		5961	#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /!< Bit 9 /
		5962
		5963	#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /!< Addressing Mode (Slave mode) /
		5964
		5965	/***************** Bit definition for I2C_OAR2 register *****************/
		5966	#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /!< Dual addressing mode enable /
		5967	#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /!< Interface address /
		5968
		5969	/***************** Bit definition for I2C_SR1 register ******************/
		5970	#define I2C_SR1_SB ((uint32_t)0x00000001) /!< Start Bit (Master mode) /
		5971	#define I2C_SR1_ADDR ((uint32_t)0x00000002) /!< Address sent (master mode)/matched (slave mode) /
		5972	#define I2C_SR1_BTF ((uint32_t)0x00000004) /!< Byte Transfer Finished /
		5973	#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /!< 10-bit header sent (Master mode) /
		5974	#define I2C_SR1_STOPF ((uint32_t)0x00000010) /!< Stop detection (Slave mode) /
		5975	#define I2C_SR1_RXNE ((uint32_t)0x00000040) /!< Data Register not Empty (receivers) /
		5976	#define I2C_SR1_TXE ((uint32_t)0x00000080) /!< Data Register Empty (transmitters) /
		5977	#define I2C_SR1_BERR ((uint32_t)0x00000100) /!< Bus Error /
		5978	#define I2C_SR1_ARLO ((uint32_t)0x00000200) /!< Arbitration Lost (master mode) /
		5979	#define I2C_SR1_AF ((uint32_t)0x00000400) /!< Acknowledge Failure /
		5980	#define I2C_SR1_OVR ((uint32_t)0x00000800) /!< Overrun/Underrun /
		5981	#define I2C_SR1_PECERR ((uint32_t)0x00001000) /!< PEC Error in reception /
		5982	#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /!< Timeout or Tlow Error /
		5983	#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /!< SMBus Alert /
		5984
		5985	/***************** Bit definition for I2C_SR2 register ******************/
		5986	#define I2C_SR2_MSL ((uint32_t)0x00000001) /!< Master/Slave /
		5987	#define I2C_SR2_BUSY ((uint32_t)0x00000002) /!< Bus Busy /
		5988	#define I2C_SR2_TRA ((uint32_t)0x00000004) /!< Transmitter/Receiver /
		5989	#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /!< General Call Address (Slave mode) /
		5990	#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /!< SMBus Device Default Address (Slave mode) /
		5991	#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /!< SMBus Host Header (Slave mode) /
		5992	#define I2C_SR2_DUALF ((uint32_t)0x00000080) /!< Dual Flag (Slave mode) /
		5993	#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /!< Packet Error Checking Register /
		5994
		5995	/***************** Bit definition for I2C_CCR register ******************/
		5996	#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
		5997	#define I2C_CCR_DUTY ((uint32_t)0x00004000) /!< Fast Mode Duty Cycle /
		5998	#define I2C_CCR_FS ((uint32_t)0x00008000) /!< I2C Master Mode Selection /
		5999
		6000	/**************** Bit definition for I2C_TRISE register *****************/
		6001	#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
		6002
		6003	/******************************************************************************/
		6004	/* */
		6005	/* Universal Synchronous Asynchronous Receiver Transmitter */
		6006	/* */
		6007	/******************************************************************************/
		6008
		6009	/***************** Bit definition for USART_SR register *****************/
		6010	#define USART_SR_PE ((uint32_t)0x00000001) /!< Parity Error /
		6011	#define USART_SR_FE ((uint32_t)0x00000002) /!< Framing Error /
		6012	#define USART_SR_NE ((uint32_t)0x00000004) /!< Noise Error Flag /
		6013	#define USART_SR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
		6014	#define USART_SR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
		6015	#define USART_SR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
		6016	#define USART_SR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
		6017	#define USART_SR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
		6018	#define USART_SR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
		6019	#define USART_SR_CTS ((uint32_t)0x00000200) /!< CTS Flag /
		6020
		6021	/***************** Bit definition for USART_DR register *****************/
		6022	#define USART_DR_DR ((uint32_t)0x000001FF) /!< Data value /
		6023
		6024	/**************** Bit definition for USART_BRR register *****************/
		6025	#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
		6026	#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
		6027
		6028	/**************** Bit definition for USART_CR1 register *****************/
		6029	#define USART_CR1_SBK ((uint32_t)0x00000001) /!< Send Break /
		6030	#define USART_CR1_RWU ((uint32_t)0x00000002) /!< Receiver wakeup /
		6031	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
		6032	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
		6033	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
		6034	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
		6035	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
		6036	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< PE Interrupt Enable /
		6037	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
		6038	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
		6039	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
		6040	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Wakeup method /
		6041	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
		6042	#define USART_CR1_UE ((uint32_t)0x00002000) /!< USART Enable /
		6043
		6044	/**************** Bit definition for USART_CR2 register *****************/
		6045	#define USART_CR2_ADD ((uint32_t)0x0000000F) /!< Address of the USART node /
		6046	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
		6047	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
		6048	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
		6049	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
		6050	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
		6051	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
		6052
		6053	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
		6054	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
		6055	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
		6056
		6057	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
		6058
		6059	/**************** Bit definition for USART_CR3 register *****************/
		6060	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
		6061	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
		6062	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
		6063	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
		6064	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< Smartcard NACK enable /
		6065	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Smartcard mode enable /
		6066	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
		6067	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
		6068	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
		6069	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
		6070	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
		6071
		6072	/**************** Bit definition for USART_GTPR register ****************/
		6073	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
		6074	#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /!< Bit 0 /
		6075	#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /!< Bit 1 /
		6076	#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /!< Bit 2 /
		6077	#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /!< Bit 3 /
		6078	#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /!< Bit 4 /
		6079	#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /!< Bit 5 /
		6080	#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /!< Bit 6 /
		6081	#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /!< Bit 7 /
		6082
		6083	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< Guard time value /
		6084
		6085	/******************************************************************************/
		6086	/* */
		6087	/* Debug MCU */
		6088	/* */
		6089	/******************************************************************************/
		6090
		6091	/************** Bit definition for DBGMCU_IDCODE register ***************/
		6092	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
		6093
		6094	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
		6095	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
		6096	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
		6097	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
		6098	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
		6099	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
		6100	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
		6101	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
		6102	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
		6103	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
		6104	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
		6105	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
		6106	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
		6107	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
		6108	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
		6109	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
		6110	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
		6111
		6112	/**************** Bit definition for DBGMCU_CR register *****************/
		6113	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
		6114	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
		6115	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
		6116	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
		6117
		6118	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
		6119	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
		6120	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
		6121
		6122	#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /!< Debug Independent Watchdog stopped when Core is halted /
		6123	#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /!< Debug Window Watchdog stopped when Core is halted /
		6124	#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /!< TIM1 counter stopped when core is halted /
		6125	#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /!< TIM2 counter stopped when core is halted /
		6126	#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /!< TIM3 counter stopped when core is halted /
		6127	#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /!< TIM4 counter stopped when core is halted /
		6128	#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /!< Debug CAN1 stopped when Core is halted /
		6129	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /!< SMBUS timeout mode stopped when Core is halted /
		6130	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /!< SMBUS timeout mode stopped when Core is halted /
		6131	#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /!< TIM8 counter stopped when core is halted /
		6132	#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /!< TIM5 counter stopped when core is halted /
		6133	#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /!< TIM6 counter stopped when core is halted /
		6134	#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /!< TIM7 counter stopped when core is halted /
		6135
		6136	/******************************************************************************/
		6137	/* */
		6138	/* FLASH and Option Bytes Registers */
		6139	/* */
		6140	/******************************************************************************/
		6141	/***************** Bit definition for FLASH_ACR register ****************/
		6142	#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /!< LATENCY[2:0] bits (Latency) /
		6143	#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /!< Bit 0 /
		6144	#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /!< Bit 1 /
		6145	#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /!< Bit 2 /
		6146
		6147	#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /!< Flash Half Cycle Access Enable /
		6148	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
		6149	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
		6150
		6151	/**************** Bit definition for FLASH_KEYR register ****************/
		6152	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
		6153
		6154	#define RDP_KEY ((uint32_t)0x000000A5) /!< RDP Key /
		6155	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< FPEC Key1 /
		6156	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /!< FPEC Key2 /
		6157
		6158	/*************** Bit definition for FLASH_OPTKEYR register **************/
		6159	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
		6160
		6161	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
		6162	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
		6163
		6164	/**************** Bit definition for FLASH_SR register ******************/
		6165	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
		6166	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
		6167	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
		6168	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
		6169
		6170	/***************** Bit definition for FLASH_CR register *****************/
		6171	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
		6172	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
		6173	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
		6174	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
		6175	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
		6176	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
		6177	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
		6178	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
		6179	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
		6180	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
		6181
		6182	/***************** Bit definition for FLASH_AR register *****************/
		6183	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
		6184
		6185	/**************** Bit definition for FLASH_OBR register *****************/
		6186	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
		6187	#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /!< Read protection /
		6188
		6189	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /!< IWDG SW /
		6190	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /!< nRST_STOP /
		6191	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /!< nRST_STDBY /
		6192	#define FLASH_OBR_USER ((uint32_t)0x0000001C) /!< User Option Bytes /
		6193
		6194	/**************** Bit definition for FLASH_WRPR register ****************/
		6195	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
		6196
		6197	/----------------------------------------------------------------------------/
		6198
		6199	/**************** Bit definition for FLASH_RDP register *****************/
		6200	#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
		6201	#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
		6202
		6203	/**************** Bit definition for FLASH_USER register ****************/
		6204	#define FLASH_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
		6205	#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
		6206
		6207	/**************** Bit definition for FLASH_Data0 register ***************/
		6208	#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /!< User data storage option byte /
		6209	#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /!< User data storage complemented option byte /
		6210
		6211	/**************** Bit definition for FLASH_Data1 register ***************/
		6212	#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /!< User data storage option byte /
		6213	#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /!< User data storage complemented option byte /
		6214
		6215	/**************** Bit definition for FLASH_WRP0 register ****************/
		6216	#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
		6217	#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
		6218
		6219	/**************** Bit definition for FLASH_WRP1 register ****************/
		6220	#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
		6221	#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
		6222
		6223	/**************** Bit definition for FLASH_WRP2 register ****************/
		6224	#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
		6225	#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
		6226
		6227	/**************** Bit definition for FLASH_WRP3 register ****************/
		6228	#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
		6229	#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
		6230
		6231
		6232
		6233	/**
		6234	* @}
		6235	*/
		6236
		6237	/**
		6238	* @}
		6239	*/
		6240
		6241	/** @addtogroup Exported_macro
		6242	* @{
		6243	*/
		6244
		6245	/**************************** ADC Instances *******************************/
		6246	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \|\| \
		6247	((INSTANCE) == ADC2) \|\| \
		6248	((INSTANCE) == ADC3))
		6249
		6250	#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		6251
		6252	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \|\| \
		6253	((INSTANCE) == ADC3))
		6254
		6255	/**************************** CAN Instances *******************************/
		6256	#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
		6257
		6258	/**************************** CRC Instances *******************************/
		6259	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		6260
		6261	/**************************** DAC Instances *******************************/
		6262	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
		6263
		6264	/**************************** DMA Instances *******************************/
		6265	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		6266	((INSTANCE) == DMA1_Channel2) \|\| \
		6267	((INSTANCE) == DMA1_Channel3) \|\| \
		6268	((INSTANCE) == DMA1_Channel4) \|\| \
		6269	((INSTANCE) == DMA1_Channel5) \|\| \
		6270	((INSTANCE) == DMA1_Channel6) \|\| \
		6271	((INSTANCE) == DMA1_Channel7) \|\| \
		6272	((INSTANCE) == DMA2_Channel1) \|\| \
		6273	((INSTANCE) == DMA2_Channel2) \|\| \
		6274	((INSTANCE) == DMA2_Channel3) \|\| \
		6275	((INSTANCE) == DMA2_Channel4) \|\| \
		6276	((INSTANCE) == DMA2_Channel5))
		6277
		6278	/***************************** GPIO Instances *****************************/
		6279	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		6280	((INSTANCE) == GPIOB) \|\| \
		6281	((INSTANCE) == GPIOC) \|\| \
		6282	((INSTANCE) == GPIOD) \|\| \
		6283	((INSTANCE) == GPIOE) \|\| \
		6284	((INSTANCE) == GPIOF) \|\| \
		6285	((INSTANCE) == GPIOG))
		6286
		6287	/************************** GPIO Alternate Function Instances *************/
		6288	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		6289
		6290	/************************** GPIO Lock Instances ***************************/
		6291	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		6292
		6293	/****************************** I2C Instances *****************************/
		6294	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		6295	((INSTANCE) == I2C2))
		6296
		6297	/****************************** I2S Instances *****************************/
		6298	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) \|\| \
		6299	((INSTANCE) == SPI3))
		6300
		6301	/**************************** IWDG Instances ******************************/
		6302	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		6303
		6304	/**************************** SDIO Instances *******************************/
		6305	#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
		6306
		6307	/****************************** SPI Instances *****************************/
		6308	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		6309	((INSTANCE) == SPI2) \|\| \
		6310	((INSTANCE) == SPI3))
		6311
		6312	/**************************** START TIM Instances *************************/
		6313	/**************************** TIM Instances *******************************/
		6314	#define IS_TIM_INSTANCE(INSTANCE)\
		6315	(((INSTANCE) == TIM1) \|\| \
		6316	((INSTANCE) == TIM8) \|\| \
		6317	((INSTANCE) == TIM2) \|\| \
		6318	((INSTANCE) == TIM3) \|\| \
		6319	((INSTANCE) == TIM4) \|\| \
		6320	((INSTANCE) == TIM5) \|\| \
		6321	((INSTANCE) == TIM6) \|\| \
		6322	((INSTANCE) == TIM7))
		6323
		6324	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
		6325	(((INSTANCE) == TIM1) \|\| \
		6326	((INSTANCE) == TIM8) \|\| \
		6327	((INSTANCE) == TIM2) \|\| \
		6328	((INSTANCE) == TIM3) \|\| \
		6329	((INSTANCE) == TIM4) \|\| \
		6330	((INSTANCE) == TIM5))
		6331
		6332	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
		6333	(((INSTANCE) == TIM1) \|\| \
		6334	((INSTANCE) == TIM8) \|\| \
		6335	((INSTANCE) == TIM2) \|\| \
		6336	((INSTANCE) == TIM3) \|\| \
		6337	((INSTANCE) == TIM4) \|\| \
		6338	((INSTANCE) == TIM5))
		6339
		6340	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
		6341	(((INSTANCE) == TIM1) \|\| \
		6342	((INSTANCE) == TIM8) \|\| \
		6343	((INSTANCE) == TIM2) \|\| \
		6344	((INSTANCE) == TIM3) \|\| \
		6345	((INSTANCE) == TIM4) \|\| \
		6346	((INSTANCE) == TIM5))
		6347
		6348	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
		6349	(((INSTANCE) == TIM1) \|\| \
		6350	((INSTANCE) == TIM8) \|\| \
		6351	((INSTANCE) == TIM2) \|\| \
		6352	((INSTANCE) == TIM3) \|\| \
		6353	((INSTANCE) == TIM4) \|\| \
		6354	((INSTANCE) == TIM5))
		6355
		6356	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
		6357	(((INSTANCE) == TIM1) \|\| \
		6358	((INSTANCE) == TIM8) \|\| \
		6359	((INSTANCE) == TIM2) \|\| \
		6360	((INSTANCE) == TIM3) \|\| \
		6361	((INSTANCE) == TIM4) \|\| \
		6362	((INSTANCE) == TIM5))
		6363
		6364	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
		6365	(((INSTANCE) == TIM1) \|\| \
		6366	((INSTANCE) == TIM8) \|\| \
		6367	((INSTANCE) == TIM2) \|\| \
		6368	((INSTANCE) == TIM3) \|\| \
		6369	((INSTANCE) == TIM4) \|\| \
		6370	((INSTANCE) == TIM5))
		6371
		6372	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
		6373	(((INSTANCE) == TIM1) \|\| \
		6374	((INSTANCE) == TIM8) \|\| \
		6375	((INSTANCE) == TIM2) \|\| \
		6376	((INSTANCE) == TIM3) \|\| \
		6377	((INSTANCE) == TIM4) \|\| \
		6378	((INSTANCE) == TIM5))
		6379
		6380	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
		6381	(((INSTANCE) == TIM1) \|\| \
		6382	((INSTANCE) == TIM8) \|\| \
		6383	((INSTANCE) == TIM2) \|\| \
		6384	((INSTANCE) == TIM3) \|\| \
		6385	((INSTANCE) == TIM4) \|\| \
		6386	((INSTANCE) == TIM5))
		6387
		6388	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
		6389	(((INSTANCE) == TIM1) \|\| \
		6390	((INSTANCE) == TIM8) \|\| \
		6391	((INSTANCE) == TIM2) \|\| \
		6392	((INSTANCE) == TIM3) \|\| \
		6393	((INSTANCE) == TIM4) \|\| \
		6394	((INSTANCE) == TIM5))
		6395
		6396	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
		6397	(((INSTANCE) == TIM1) \|\| \
		6398	((INSTANCE) == TIM8) \|\| \
		6399	((INSTANCE) == TIM2) \|\| \
		6400	((INSTANCE) == TIM3) \|\| \
		6401	((INSTANCE) == TIM4) \|\| \
		6402	((INSTANCE) == TIM5))
		6403
		6404	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
		6405	(((INSTANCE) == TIM1) \|\| \
		6406	((INSTANCE) == TIM8) \|\| \
		6407	((INSTANCE) == TIM2) \|\| \
		6408	((INSTANCE) == TIM3) \|\| \
		6409	((INSTANCE) == TIM4) \|\| \
		6410	((INSTANCE) == TIM5))
		6411
		6412	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
		6413	(((INSTANCE) == TIM1) \|\| \
		6414	((INSTANCE) == TIM8) \|\| \
		6415	((INSTANCE) == TIM2) \|\| \
		6416	((INSTANCE) == TIM3) \|\| \
		6417	((INSTANCE) == TIM4) \|\| \
		6418	((INSTANCE) == TIM5) \|\| \
		6419	((INSTANCE) == TIM6) \|\| \
		6420	((INSTANCE) == TIM7))
		6421
		6422	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
		6423	(((INSTANCE) == TIM1) \|\| \
		6424	((INSTANCE) == TIM8) \|\| \
		6425	((INSTANCE) == TIM2) \|\| \
		6426	((INSTANCE) == TIM3) \|\| \
		6427	((INSTANCE) == TIM4) \|\| \
		6428	((INSTANCE) == TIM5))
		6429
		6430	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
		6431	(((INSTANCE) == TIM1) \|\| \
		6432	((INSTANCE) == TIM8) \|\| \
		6433	((INSTANCE) == TIM2) \|\| \
		6434	((INSTANCE) == TIM3) \|\| \
		6435	((INSTANCE) == TIM4) \|\| \
		6436	((INSTANCE) == TIM5))
		6437
		6438	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
		6439	(((INSTANCE) == TIM1) \|\| \
		6440	((INSTANCE) == TIM8))
		6441
		6442	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		6443	((((INSTANCE) == TIM1) && \
		6444	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6445	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6446	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6447	((CHANNEL) == TIM_CHANNEL_4))) \
		6448	\|\| \
		6449	(((INSTANCE) == TIM8) && \
		6450	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6451	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6452	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6453	((CHANNEL) == TIM_CHANNEL_4))) \
		6454	\|\| \
		6455	(((INSTANCE) == TIM2) && \
		6456	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6457	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6458	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6459	((CHANNEL) == TIM_CHANNEL_4))) \
		6460	\|\| \
		6461	(((INSTANCE) == TIM3) && \
		6462	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6463	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6464	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6465	((CHANNEL) == TIM_CHANNEL_4))) \
		6466	\|\| \
		6467	(((INSTANCE) == TIM4) && \
		6468	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6469	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6470	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6471	((CHANNEL) == TIM_CHANNEL_4))) \
		6472	\|\| \
		6473	(((INSTANCE) == TIM5) && \
		6474	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6475	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6476	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6477	((CHANNEL) == TIM_CHANNEL_4))))
		6478
		6479	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
		6480	((((INSTANCE) == TIM1) && \
		6481	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6482	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6483	((CHANNEL) == TIM_CHANNEL_3))) \
		6484	\|\| \
		6485	(((INSTANCE) == TIM8) && \
		6486	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6487	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6488	((CHANNEL) == TIM_CHANNEL_3))))
		6489
		6490	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
		6491	(((INSTANCE) == TIM1) \|\| \
		6492	((INSTANCE) == TIM8) \|\| \
		6493	((INSTANCE) == TIM2) \|\| \
		6494	((INSTANCE) == TIM3) \|\| \
		6495	((INSTANCE) == TIM4) \|\| \
		6496	((INSTANCE) == TIM5))
		6497
		6498	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
		6499	(((INSTANCE) == TIM1) \|\| \
		6500	((INSTANCE) == TIM8))
		6501
		6502	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
		6503	(((INSTANCE) == TIM1) \|\| \
		6504	((INSTANCE) == TIM8) \|\| \
		6505	((INSTANCE) == TIM2) \|\| \
		6506	((INSTANCE) == TIM3) \|\| \
		6507	((INSTANCE) == TIM4) \|\| \
		6508	((INSTANCE) == TIM5))
		6509
		6510	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
		6511	(((INSTANCE) == TIM1) \|\| \
		6512	((INSTANCE) == TIM8) \|\| \
		6513	((INSTANCE) == TIM2) \|\| \
		6514	((INSTANCE) == TIM3) \|\| \
		6515	((INSTANCE) == TIM4) \|\| \
		6516	((INSTANCE) == TIM5) \|\| \
		6517	((INSTANCE) == TIM6) \|\| \
		6518	((INSTANCE) == TIM7))
		6519
		6520	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
		6521	(((INSTANCE) == TIM1) \|\| \
		6522	((INSTANCE) == TIM8) \|\| \
		6523	((INSTANCE) == TIM2) \|\| \
		6524	((INSTANCE) == TIM3) \|\| \
		6525	((INSTANCE) == TIM4) \|\| \
		6526	((INSTANCE) == TIM5))
		6527
		6528	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
		6529	(((INSTANCE) == TIM1) \|\| \
		6530	((INSTANCE) == TIM8))
		6531
		6532	/**************************** END TIM Instances ***************************/
		6533
		6534
		6535	/****************** USART Instances : Synchronous mode ********************/
		6536	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6537	((INSTANCE) == USART2) \|\| \
		6538	((INSTANCE) == USART3))
		6539
		6540	/****************** UART Instances : Asynchronous mode ********************/
		6541	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6542	((INSTANCE) == USART2) \|\| \
		6543	((INSTANCE) == USART3) \|\| \
		6544	((INSTANCE) == UART4) \|\| \
		6545	((INSTANCE) == UART5))
		6546
		6547	/****************** UART Instances : Half-Duplex mode ********************/
		6548	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6549	((INSTANCE) == USART2) \|\| \
		6550	((INSTANCE) == USART3) \|\| \
		6551	((INSTANCE) == UART4) \|\| \
		6552	((INSTANCE) == UART5))
		6553
		6554	/****************** UART Instances : LIN mode ********************/
		6555	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6556	((INSTANCE) == USART2) \|\| \
		6557	((INSTANCE) == USART3) \|\| \
		6558	((INSTANCE) == UART4) \|\| \
		6559	((INSTANCE) == UART5))
		6560
		6561	/**************** UART Instances : Hardware Flow control ******************/
		6562	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6563	((INSTANCE) == USART2) \|\| \
		6564	((INSTANCE) == USART3))
		6565
		6566	/******************* UART Instances : Smard card mode *********************/
		6567	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6568	((INSTANCE) == USART2) \|\| \
		6569	((INSTANCE) == USART3))
		6570
		6571	/********************* UART Instances : IRDA mode *************************/
		6572	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6573	((INSTANCE) == USART2) \|\| \
		6574	((INSTANCE) == USART3) \|\| \
		6575	((INSTANCE) == UART4) \|\| \
		6576	((INSTANCE) == UART5))
		6577
		6578	/*************** UART Instances : Multi-Processor mode ********************/
		6579	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6580	((INSTANCE) == USART2) \|\| \
		6581	((INSTANCE) == USART3) \|\| \
		6582	((INSTANCE) == UART4) \|\| \
		6583	((INSTANCE) == UART5))
		6584
		6585	/*************** UART Instances : DMA mode available ********************/
		6586	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6587	((INSTANCE) == USART2) \|\| \
		6588	((INSTANCE) == USART3) \|\| \
		6589	((INSTANCE) == UART4))
		6590
		6591	/**************************** RTC Instances *******************************/
		6592	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		6593
		6594	/************************** WWDG Instances ***************************/
		6595	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		6596
		6597	/**************************** USB Instances ******************************/
		6598	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
		6599
		6600
		6601
		6602
		6603	/**
		6604	* @}
		6605	*/
		6606	/******************************************************************************/
		6607	/* For a painless codes migration between the STM32F1xx device product */
		6608	/* lines, the aliases defined below are put in place to overcome the */
		6609	/* differences in the interrupt handlers and IRQn definitions. */
		6610	/* No need to update developed interrupt code when moving across */
		6611	/* product lines within the same STM32F1 Family */
		6612	/******************************************************************************/
		6613
		6614	/* Aliases for __IRQn */
		6615	#define ADC1_IRQn ADC1_2_IRQn
		6616	#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
		6617	#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
		6618	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
		6619	#define TIM9_IRQn TIM1_BRK_IRQn
		6620	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
		6621	#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
		6622	#define TIM11_IRQn TIM1_TRG_COM_IRQn
		6623	#define TIM10_IRQn TIM1_UP_IRQn
		6624	#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
		6625	#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
		6626	#define TIM6_DAC_IRQn TIM6_IRQn
		6627	#define TIM12_IRQn TIM8_BRK_IRQn
		6628	#define TIM8_BRK_TIM12_IRQn TIM8_BRK_IRQn
		6629	#define TIM14_IRQn TIM8_TRG_COM_IRQn
		6630	#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
		6631	#define TIM8_UP_TIM13_IRQn TIM8_UP_IRQn
		6632	#define TIM13_IRQn TIM8_UP_IRQn
		6633	#define CEC_IRQn USBWakeUp_IRQn
		6634	#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
		6635	#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
		6636	#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
		6637	#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
		6638	#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
		6639
		6640
		6641	/* Aliases for __IRQHandler */
		6642	#define ADC1_IRQHandler ADC1_2_IRQHandler
		6643	#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
		6644	#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
		6645	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
		6646	#define TIM9_IRQHandler TIM1_BRK_IRQHandler
		6647	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
		6648	#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
		6649	#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
		6650	#define TIM10_IRQHandler TIM1_UP_IRQHandler
		6651	#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
		6652	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
		6653	#define TIM6_DAC_IRQHandler TIM6_IRQHandler
		6654	#define TIM12_IRQHandler TIM8_BRK_IRQHandler
		6655	#define TIM8_BRK_TIM12_IRQHandler TIM8_BRK_IRQHandler
		6656	#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
		6657	#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
		6658	#define TIM8_UP_TIM13_IRQHandler TIM8_UP_IRQHandler
		6659	#define TIM13_IRQHandler TIM8_UP_IRQHandler
		6660	#define CEC_IRQHandler USBWakeUp_IRQHandler
		6661	#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
		6662	#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
		6663	#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
		6664	#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
		6665	#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
		6666
		6667
		6668	/**
		6669	* @}
		6670	*/
		6671
		6672	/**
		6673	* @}
		6674	*/
		6675
		6676
		6677	#ifdef __cplusplus
		6678	}
		6679	#endif /* __cplusplus */
		6680
		6681	#endif /* __STM32F103xE_H */
		6682
		6683
		6684
		6685	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h – Rev 2