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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f102xb.h
		4	* @author MCD Application Team
		5	* @version V4.0.1
		6	* @date 31-July-2015
		7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		8	* This file contains all the peripheral register's definitions, bits
		9	* definitions and memory mapping for STM32F1xx devices.
		10	*
		11	* This file contains:
		12	* - Data structures and the address mapping for all peripherals
		13	* - Peripheral's registers declarations and bits definition
		14	* - Macros to access peripheral�s registers hardware
		15	*
		16	******************************************************************************
		17	* @attention
		18	*
		19	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
		20	*
		21	* Redistribution and use in source and binary forms, with or without modification,
		22	* are permitted provided that the following conditions are met:
		23	* 1. Redistributions of source code must retain the above copyright notice,
		24	* this list of conditions and the following disclaimer.
		25	* 2. Redistributions in binary form must reproduce the above copyright notice,
		26	* this list of conditions and the following disclaimer in the documentation
		27	* and/or other materials provided with the distribution.
		28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		29	* may be used to endorse or promote products derived from this software
		30	* without specific prior written permission.
		31	*
		32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		42	*
		43	******************************************************************************
		44	*/
		45
		46
		47	/** @addtogroup CMSIS
		48	* @{
		49	*/
		50
		51	/** @addtogroup stm32f102xb
		52	* @{
		53	*/
		54
		55	#ifndef __STM32F102xB_H
		56	#define __STM32F102xB_H
		57
		58	#ifdef __cplusplus
		59	extern "C" {
		60	#endif
		61
		62	/** @addtogroup Configuration_section_for_CMSIS
		63	* @{
		64	*/
		65	/**
		66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		67	*/
		68	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
		69	#define __CM3_REV 0x0200 /!< Core Revision r2p0 /
		70	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
		71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
		72
		73	/**
		74	* @}
		75	*/
		76
		77	/** @addtogroup Peripheral_interrupt_number_definition
		78	* @{
		79	*/
		80
		81	/**
		82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
		83	* in @ref Library_configuration_section
		84	*/
		85
		86	/!< Interrupt Number Definition /
		87	typedef enum
		88	{
		89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
		90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
		91	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		92	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		93	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		94	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		95	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		96	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		97	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		98
		99	/**** STM32 specific Interrupt Numbers *******************************************************/
		100	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		101	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		102	TAMPER_IRQn = 2, /!< Tamper Interrupt /
		103	RTC_IRQn = 3, /!< RTC global Interrupt /
		104	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		105	RCC_IRQn = 5, /!< RCC global Interrupt /
		106	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		107	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		108	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		109	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		110	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		111	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		112	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		113	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		114	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		115	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		116	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		117	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		118	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
		119	USB_HP_IRQn = 19, /!< USB Device High Priority /
		120	USB_LP_IRQn = 20, /!< USB Device Low Priority /
		121	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		122	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		123	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		124	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		125	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		126	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		127	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		128	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		129	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		130	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		131	USART1_IRQn = 37, /!< USART1 global Interrupt /
		132	USART2_IRQn = 38, /!< USART2 global Interrupt /
		133	USART3_IRQn = 39, /!< USART3 global Interrupt /
		134	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		135	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		136	USBWakeUp_IRQn = 42, /!< USB Device WakeUp from suspend through EXTI Line Interrupt /
		137	} IRQn_Type;
		138
		139
		140	/**
		141	* @}
		142	*/
		143
		144	#include "core_cm3.h"
		145	#include "system_stm32f1xx.h"
		146	#include <stdint.h>
		147
		148	/** @addtogroup Peripheral_registers_structures
		149	* @{
		150	*/
		151
		152	/**
		153	* @brief Analog to Digital Converter
		154	*/
		155
		156	typedef struct
		157	{
		158	__IO uint32_t SR;
		159	__IO uint32_t CR1;
		160	__IO uint32_t CR2;
		161	__IO uint32_t SMPR1;
		162	__IO uint32_t SMPR2;
		163	__IO uint32_t JOFR1;
		164	__IO uint32_t JOFR2;
		165	__IO uint32_t JOFR3;
		166	__IO uint32_t JOFR4;
		167	__IO uint32_t HTR;
		168	__IO uint32_t LTR;
		169	__IO uint32_t SQR1;
		170	__IO uint32_t SQR2;
		171	__IO uint32_t SQR3;
		172	__IO uint32_t JSQR;
		173	__IO uint32_t JDR1;
		174	__IO uint32_t JDR2;
		175	__IO uint32_t JDR3;
		176	__IO uint32_t JDR4;
		177	__IO uint32_t DR;
		178	} ADC_TypeDef;
		179
		180	/**
		181	* @brief Backup Registers
		182	*/
		183
		184	typedef struct
		185	{
		186	uint32_t RESERVED0;
		187	__IO uint32_t DR1;
		188	__IO uint32_t DR2;
		189	__IO uint32_t DR3;
		190	__IO uint32_t DR4;
		191	__IO uint32_t DR5;
		192	__IO uint32_t DR6;
		193	__IO uint32_t DR7;
		194	__IO uint32_t DR8;
		195	__IO uint32_t DR9;
		196	__IO uint32_t DR10;
		197	__IO uint32_t RTCCR;
		198	__IO uint32_t CR;
		199	__IO uint32_t CSR;
		200	} BKP_TypeDef;
		201
		202
		203	/**
		204	* @brief CRC calculation unit
		205	*/
		206
		207	typedef struct
		208	{
		209	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		210	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		211	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		212	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		213	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		214	} CRC_TypeDef;
		215
		216
		217	/**
		218	* @brief Debug MCU
		219	*/
		220
		221	typedef struct
		222	{
		223	__IO uint32_t IDCODE;
		224	__IO uint32_t CR;
		225	}DBGMCU_TypeDef;
		226
		227	/**
		228	* @brief DMA Controller
		229	*/
		230
		231	typedef struct
		232	{
		233	__IO uint32_t CCR;
		234	__IO uint32_t CNDTR;
		235	__IO uint32_t CPAR;
		236	__IO uint32_t CMAR;
		237	} DMA_Channel_TypeDef;
		238
		239	typedef struct
		240	{
		241	__IO uint32_t ISR;
		242	__IO uint32_t IFCR;
		243	} DMA_TypeDef;
		244
		245
		246
		247	/**
		248	* @brief External Interrupt/Event Controller
		249	*/
		250
		251	typedef struct
		252	{
		253	__IO uint32_t IMR;
		254	__IO uint32_t EMR;
		255	__IO uint32_t RTSR;
		256	__IO uint32_t FTSR;
		257	__IO uint32_t SWIER;
		258	__IO uint32_t PR;
		259	} EXTI_TypeDef;
		260
		261	/**
		262	* @brief FLASH Registers
		263	*/
		264
		265	typedef struct
		266	{
		267	__IO uint32_t ACR;
		268	__IO uint32_t KEYR;
		269	__IO uint32_t OPTKEYR;
		270	__IO uint32_t SR;
		271	__IO uint32_t CR;
		272	__IO uint32_t AR;
		273	__IO uint32_t RESERVED;
		274	__IO uint32_t OBR;
		275	__IO uint32_t WRPR;
		276	} FLASH_TypeDef;
		277
		278	/**
		279	* @brief Option Bytes Registers
		280	*/
		281
		282	typedef struct
		283	{
		284	__IO uint16_t RDP;
		285	__IO uint16_t USER;
		286	__IO uint16_t Data0;
		287	__IO uint16_t Data1;
		288	__IO uint16_t WRP0;
		289	__IO uint16_t WRP1;
		290	__IO uint16_t WRP2;
		291	__IO uint16_t WRP3;
		292	} OB_TypeDef;
		293
		294	/**
		295	* @brief General Purpose I/O
		296	*/
		297
		298	typedef struct
		299	{
		300	__IO uint32_t CRL;
		301	__IO uint32_t CRH;
		302	__IO uint32_t IDR;
		303	__IO uint32_t ODR;
		304	__IO uint32_t BSRR;
		305	__IO uint32_t BRR;
		306	__IO uint32_t LCKR;
		307	} GPIO_TypeDef;
		308
		309	/**
		310	* @brief Alternate Function I/O
		311	*/
		312
		313	typedef struct
		314	{
		315	__IO uint32_t EVCR;
		316	__IO uint32_t MAPR;
		317	__IO uint32_t EXTICR[4];
		318	uint32_t RESERVED0;
		319	__IO uint32_t MAPR2;
		320	} AFIO_TypeDef;
		321	/**
		322	* @brief Inter Integrated Circuit Interface
		323	*/
		324
		325	typedef struct
		326	{
		327	__IO uint32_t CR1;
		328	__IO uint32_t CR2;
		329	__IO uint32_t OAR1;
		330	__IO uint32_t OAR2;
		331	__IO uint32_t DR;
		332	__IO uint32_t SR1;
		333	__IO uint32_t SR2;
		334	__IO uint32_t CCR;
		335	__IO uint32_t TRISE;
		336	} I2C_TypeDef;
		337
		338	/**
		339	* @brief Independent WATCHDOG
		340	*/
		341
		342	typedef struct
		343	{
		344	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		345	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		346	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		347	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		348	} IWDG_TypeDef;
		349
		350	/**
		351	* @brief Power Control
		352	*/
		353
		354	typedef struct
		355	{
		356	__IO uint32_t CR;
		357	__IO uint32_t CSR;
		358	} PWR_TypeDef;
		359
		360	/**
		361	* @brief Reset and Clock Control
		362	*/
		363
		364	typedef struct
		365	{
		366	__IO uint32_t CR;
		367	__IO uint32_t CFGR;
		368	__IO uint32_t CIR;
		369	__IO uint32_t APB2RSTR;
		370	__IO uint32_t APB1RSTR;
		371	__IO uint32_t AHBENR;
		372	__IO uint32_t APB2ENR;
		373	__IO uint32_t APB1ENR;
		374	__IO uint32_t BDCR;
		375	__IO uint32_t CSR;
		376
		377
		378	} RCC_TypeDef;
		379
		380	/**
		381	* @brief Real-Time Clock
		382	*/
		383
		384	typedef struct
		385	{
		386	__IO uint32_t CRH;
		387	__IO uint32_t CRL;
		388	__IO uint32_t PRLH;
		389	__IO uint32_t PRLL;
		390	__IO uint32_t DIVH;
		391	__IO uint32_t DIVL;
		392	__IO uint32_t CNTH;
		393	__IO uint32_t CNTL;
		394	__IO uint32_t ALRH;
		395	__IO uint32_t ALRL;
		396	} RTC_TypeDef;
		397
		398	/**
		399	* @brief SD host Interface
		400	*/
		401
		402	typedef struct
		403	{
		404	__IO uint32_t POWER;
		405	__IO uint32_t CLKCR;
		406	__IO uint32_t ARG;
		407	__IO uint32_t CMD;
		408	__I uint32_t RESPCMD;
		409	__I uint32_t RESP1;
		410	__I uint32_t RESP2;
		411	__I uint32_t RESP3;
		412	__I uint32_t RESP4;
		413	__IO uint32_t DTIMER;
		414	__IO uint32_t DLEN;
		415	__IO uint32_t DCTRL;
		416	__I uint32_t DCOUNT;
		417	__I uint32_t STA;
		418	__IO uint32_t ICR;
		419	__IO uint32_t MASK;
		420	uint32_t RESERVED0[2];
		421	__I uint32_t FIFOCNT;
		422	uint32_t RESERVED1[13];
		423	__IO uint32_t FIFO;
		424	} SDIO_TypeDef;
		425
		426	/**
		427	* @brief Serial Peripheral Interface
		428	*/
		429
		430	typedef struct
		431	{
		432	__IO uint32_t CR1;
		433	__IO uint32_t CR2;
		434	__IO uint32_t SR;
		435	__IO uint32_t DR;
		436	__IO uint32_t CRCPR;
		437	__IO uint32_t RXCRCR;
		438	__IO uint32_t TXCRCR;
		439	__IO uint32_t I2SCFGR;
		440	} SPI_TypeDef;
		441
		442	/**
		443	* @brief TIM Timers
		444	*/
		445	typedef struct
		446	{
		447	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		448	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		449	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		450	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		451	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		452	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		453	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		454	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		455	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		456	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		457	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		458	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		459	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
		460	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		461	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		462	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		463	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		464	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
		465	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		466	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
		467	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		468	}TIM_TypeDef;
		469
		470
		471	/**
		472	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		473	*/
		474
		475	typedef struct
		476	{
		477	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		478	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		479	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		480	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		481	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		482	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		483	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		484	} USART_TypeDef;
		485
		486	/**
		487	* @brief Universal Serial Bus Full Speed Device
		488	*/
		489
		490	typedef struct
		491	{
		492	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
		493	__IO uint16_t RESERVED0; /!< Reserved /
		494	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
		495	__IO uint16_t RESERVED1; /!< Reserved /
		496	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
		497	__IO uint16_t RESERVED2; /!< Reserved /
		498	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
		499	__IO uint16_t RESERVED3; /!< Reserved /
		500	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
		501	__IO uint16_t RESERVED4; /!< Reserved /
		502	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
		503	__IO uint16_t RESERVED5; /!< Reserved /
		504	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
		505	__IO uint16_t RESERVED6; /!< Reserved /
		506	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
		507	__IO uint16_t RESERVED7[17]; /!< Reserved /
		508	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
		509	__IO uint16_t RESERVED8; /!< Reserved /
		510	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
		511	__IO uint16_t RESERVED9; /!< Reserved /
		512	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
		513	__IO uint16_t RESERVEDA; /!< Reserved /
		514	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
		515	__IO uint16_t RESERVEDB; /!< Reserved /
		516	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
		517	__IO uint16_t RESERVEDC; /!< Reserved /
		518	} USB_TypeDef;
		519
		520
		521	/**
		522	* @brief Window WATCHDOG
		523	*/
		524
		525	typedef struct
		526	{
		527	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		528	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		529	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		530	} WWDG_TypeDef;
		531
		532	/**
		533	* @}
		534	*/
		535
		536	/** @addtogroup Peripheral_memory_map
		537	* @{
		538	*/
		539
		540
		541	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
		542	#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /!< FLASH END address of bank1 /
		543	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
		544	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
		545
		546	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
		547	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
		548
		549
		550	/!< Peripheral memory map /
		551	#define APB1PERIPH_BASE PERIPH_BASE
		552	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
		553	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
		554
		555	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
		556	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
		557	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
		558	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
		559	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
		560	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
		561	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
		562	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
		563	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
		564	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
		565	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
		566	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
		567	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
		568	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
		569	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
		570	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
		571	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
		572	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
		573	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
		574	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
		575	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
		576	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
		577
		578	#define SDIO_BASE (PERIPH_BASE + 0x18000)
		579
		580	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
		581	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
		582	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
		583	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
		584	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
		585	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
		586	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
		587	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
		588	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
		589	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
		590
		591	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
		592	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
		593
		594
		595
		596	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
		597
		598	/* USB device FS */
		599	#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
		600	#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
		601
		602
		603	/**
		604	* @}
		605	*/
		606
		607	/** @addtogroup Peripheral_declaration
		608	* @{
		609	*/
		610
		611	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
		612	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
		613	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
		614	#define RTC ((RTC_TypeDef *) RTC_BASE)
		615	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
		616	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
		617	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
		618	#define USART2 ((USART_TypeDef *) USART2_BASE)
		619	#define USART3 ((USART_TypeDef *) USART3_BASE)
		620	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
		621	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
		622	#define USB ((USB_TypeDef *) USB_BASE)
		623	#define BKP ((BKP_TypeDef *) BKP_BASE)
		624	#define PWR ((PWR_TypeDef *) PWR_BASE)
		625	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
		626	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
		627	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
		628	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
		629	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
		630	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
		631	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
		632	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
		633	#define USART1 ((USART_TypeDef *) USART1_BASE)
		634	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
		635	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
		636	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
		637	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
		638	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
		639	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
		640	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
		641	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
		642	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
		643	#define RCC ((RCC_TypeDef *) RCC_BASE)
		644	#define CRC ((CRC_TypeDef *) CRC_BASE)
		645	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
		646	#define OB ((OB_TypeDef *) OB_BASE)
		647	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
		648
		649
		650	/**
		651	* @}
		652	*/
		653
		654	/** @addtogroup Exported_constants
		655	* @{
		656	*/
		657
		658	/** @addtogroup Peripheral_Registers_Bits_Definition
		659	* @{
		660	*/
		661
		662	/******************************************************************************/
		663	/* Peripheral Registers_Bits_Definition */
		664	/******************************************************************************/
		665
		666	/******************************************************************************/
		667	/* */
		668	/* CRC calculation unit (CRC) */
		669	/* */
		670	/******************************************************************************/
		671
		672	/***************** Bit definition for CRC_DR register *******************/
		673	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
		674
		675	/***************** Bit definition for CRC_IDR register ******************/
		676	#define CRC_IDR_IDR ((uint32_t)0xFF) /!< General-purpose 8-bit data register bits /
		677
		678	/****************** Bit definition for CRC_CR register ******************/
		679	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
		680
		681	/******************************************************************************/
		682	/* */
		683	/* Power Control */
		684	/* */
		685	/******************************************************************************/
		686
		687	/****************** Bit definition for PWR_CR register ******************/
		688	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
		689	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
		690	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
		691	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
		692	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
		693
		694	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
		695	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
		696	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
		697	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
		698
		699	/!< PVD level configuration /
		700	#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /!< PVD level 2.2V /
		701	#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /!< PVD level 2.3V /
		702	#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /!< PVD level 2.4V /
		703	#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /!< PVD level 2.5V /
		704	#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /!< PVD level 2.6V /
		705	#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /!< PVD level 2.7V /
		706	#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /!< PVD level 2.8V /
		707	#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /!< PVD level 2.9V /
		708
		709	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
		710
		711
		712	/***************** Bit definition for PWR_CSR register ******************/
		713	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
		714	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
		715	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
		716	#define PWR_CSR_EWUP ((uint32_t)0x00000100) /!< Enable WKUP pin /
		717
		718	/******************************************************************************/
		719	/* */
		720	/* Backup registers */
		721	/* */
		722	/******************************************************************************/
		723
		724	/***************** Bit definition for BKP_DR1 register ******************/
		725	#define BKP_DR1_D ((uint32_t)0x0000FFFF) /!< Backup data /
		726
		727	/***************** Bit definition for BKP_DR2 register ******************/
		728	#define BKP_DR2_D ((uint32_t)0x0000FFFF) /!< Backup data /
		729
		730	/***************** Bit definition for BKP_DR3 register ******************/
		731	#define BKP_DR3_D ((uint32_t)0x0000FFFF) /!< Backup data /
		732
		733	/***************** Bit definition for BKP_DR4 register ******************/
		734	#define BKP_DR4_D ((uint32_t)0x0000FFFF) /!< Backup data /
		735
		736	/***************** Bit definition for BKP_DR5 register ******************/
		737	#define BKP_DR5_D ((uint32_t)0x0000FFFF) /!< Backup data /
		738
		739	/***************** Bit definition for BKP_DR6 register ******************/
		740	#define BKP_DR6_D ((uint32_t)0x0000FFFF) /!< Backup data /
		741
		742	/***************** Bit definition for BKP_DR7 register ******************/
		743	#define BKP_DR7_D ((uint32_t)0x0000FFFF) /!< Backup data /
		744
		745	/***************** Bit definition for BKP_DR8 register ******************/
		746	#define BKP_DR8_D ((uint32_t)0x0000FFFF) /!< Backup data /
		747
		748	/***************** Bit definition for BKP_DR9 register ******************/
		749	#define BKP_DR9_D ((uint32_t)0x0000FFFF) /!< Backup data /
		750
		751	/***************** Bit definition for BKP_DR10 register *****************/
		752	#define BKP_DR10_D ((uint32_t)0x0000FFFF) /!< Backup data /
		753
		754	#define RTC_BKP_NUMBER 10
		755
		756	/**************** Bit definition for BKP_RTCCR register *****************/
		757	#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /!< Calibration value /
		758	#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /!< Calibration Clock Output /
		759	#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /!< Alarm or Second Output Enable /
		760	#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /!< Alarm or Second Output Selection /
		761
		762	/****************** Bit definition for BKP_CR register ******************/
		763	#define BKP_CR_TPE ((uint32_t)0x00000001) /!< TAMPER pin enable /
		764	#define BKP_CR_TPAL ((uint32_t)0x00000002) /!< TAMPER pin active level /
		765
		766	/***************** Bit definition for BKP_CSR register ******************/
		767	#define BKP_CSR_CTE ((uint32_t)0x00000001) /!< Clear Tamper event /
		768	#define BKP_CSR_CTI ((uint32_t)0x00000002) /!< Clear Tamper Interrupt /
		769	#define BKP_CSR_TPIE ((uint32_t)0x00000004) /!< TAMPER Pin interrupt enable /
		770	#define BKP_CSR_TEF ((uint32_t)0x00000100) /!< Tamper Event Flag /
		771	#define BKP_CSR_TIF ((uint32_t)0x00000200) /!< Tamper Interrupt Flag /
		772
		773	/******************************************************************************/
		774	/* */
		775	/* Reset and Clock Control */
		776	/* */
		777	/******************************************************************************/
		778
		779	/****************** Bit definition for RCC_CR register ******************/
		780	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
		781	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
		782	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
		783	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
		784	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
		785	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
		786	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
		787	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
		788	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
		789	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
		790
		791
		792	/***************** Bit definition for RCC_CFGR register *****************/
		793	/!< SW configuration /
		794	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
		795	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
		796	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
		797
		798	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
		799	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
		800	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
		801
		802	/!< SWS configuration /
		803	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
		804	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
		805	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
		806
		807	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
		808	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
		809	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
		810
		811	/!< HPRE configuration /
		812	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
		813	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
		814	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
		815	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
		816	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
		817
		818	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
		819	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
		820	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
		821	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
		822	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
		823	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
		824	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
		825	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
		826	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
		827
		828	/!< PPRE1 configuration /
		829	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
		830	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
		831	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
		832	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
		833
		834	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		835	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
		836	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
		837	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
		838	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
		839
		840	/!< PPRE2 configuration /
		841	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
		842	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
		843	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
		844	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
		845
		846	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		847	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
		848	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
		849	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
		850	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
		851
		852	/!< ADCPPRE configuration /
		853	#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /!< ADCPRE[1:0] bits (ADC prescaler) /
		854	#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /!< Bit 0 /
		855	#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /!< Bit 1 /
		856
		857	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
		858	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
		859	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
		860	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
		861
		862	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
		863
		864	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
		865
		866	/!< PLLMUL configuration /
		867	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
		868	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
		869	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
		870	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
		871	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
		872
		873	#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /!< HSE clock not divided for PLL entry /
		874	#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /!< HSE clock divided by 2 for PLL entry /
		875
		876	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
		877	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
		878	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
		879	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
		880	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
		881	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
		882	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
		883	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
		884	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
		885	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
		886	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
		887	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
		888	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
		889	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
		890	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
		891	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB Device prescaler /
		892
		893	/!< MCO configuration /
		894	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
		895	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
		896	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
		897	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
		898
		899	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		900	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
		901	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
		902	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
		903	#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
		904
		905	/!<*************** Bit definition for RCC_CIR register ******************/
		906	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
		907	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
		908	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
		909	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
		910	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
		911	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
		912	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
		913	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
		914	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
		915	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
		916	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
		917	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
		918	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
		919	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
		920	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
		921	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
		922	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
		923
		924
		925	/*************** Bit definition for RCC_APB2RSTR register ***************/
		926	#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /!< Alternate Function I/O reset /
		927	#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /!< I/O port A reset /
		928	#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /!< I/O port B reset /
		929	#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /!< I/O port C reset /
		930	#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /!< I/O port D reset /
		931	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC 1 interface reset /
		932
		933
		934	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 Timer reset /
		935	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI 1 reset /
		936	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
		937
		938
		939
		940
		941
		942
		943	/*************** Bit definition for RCC_APB1RSTR register ***************/
		944	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
		945	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
		946	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
		947	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
		948	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
		949
		950
		951	#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /!< Backup interface reset /
		952	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
		953
		954	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
		955	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
		956	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
		957	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
		958
		959	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB Device reset /
		960
		961
		962
		963
		964
		965
		966	/**************** Bit definition for RCC_AHBENR register ****************/
		967	#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /!< DMA1 clock enable /
		968	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
		969	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
		970	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
		971
		972
		973
		974
		975	/**************** Bit definition for RCC_APB2ENR register ***************/
		976	#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /!< Alternate Function I/O clock enable /
		977	#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /!< I/O port A clock enable /
		978	#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /!< I/O port B clock enable /
		979	#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /!< I/O port C clock enable /
		980	#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /!< I/O port D clock enable /
		981	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC 1 interface clock enable /
		982
		983
		984	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 Timer clock enable /
		985	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI 1 clock enable /
		986	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
		987
		988
		989
		990
		991
		992
		993	/*************** Bit definition for RCC_APB1ENR register ****************/
		994	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
		995	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
		996	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
		997	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
		998	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
		999
		1000
		1001	#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /!< Backup interface clock enable /
		1002	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
		1003
		1004	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
		1005	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
		1006	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
		1007	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
		1008
		1009	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB Device clock enable /
		1010
		1011
		1012
		1013
		1014
		1015
		1016	/***************** Bit definition for RCC_BDCR register *****************/
		1017	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
		1018	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
		1019	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
		1020
		1021	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
		1022	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1023	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1024
		1025	/!< RTC congiguration /
		1026	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1027	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
		1028	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
		1029	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
		1030
		1031	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
		1032	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
		1033
		1034	/***************** Bit definition for RCC_CSR register ******************/
		1035	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
		1036	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
		1037	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
		1038	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
		1039	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
		1040	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
		1041	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
		1042	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
		1043	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
		1044
		1045
		1046
		1047	/******************************************************************************/
		1048	/* */
		1049	/* General Purpose and Alternate Function I/O */
		1050	/* */
		1051	/******************************************************************************/
		1052
		1053	/***************** Bit definition for GPIO_CRL register *****************/
		1054	#define GPIO_CRL_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
		1055
		1056	#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
		1057	#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1058	#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1059
		1060	#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
		1061	#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1062	#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1063
		1064	#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
		1065	#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1066	#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1067
		1068	#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
		1069	#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /!< Bit 0 /
		1070	#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /!< Bit 1 /
		1071
		1072	#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
		1073	#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /!< Bit 0 /
		1074	#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /!< Bit 1 /
		1075
		1076	#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
		1077	#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /!< Bit 0 /
		1078	#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /!< Bit 1 /
		1079
		1080	#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
		1081	#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1082	#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1083
		1084	#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
		1085	#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /!< Bit 0 /
		1086	#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /!< Bit 1 /
		1087
		1088	#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
		1089
		1090	#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
		1091	#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1092	#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1093
		1094	#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
		1095	#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1096	#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1097
		1098	#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
		1099	#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1100	#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1101
		1102	#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
		1103	#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1104	#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1105
		1106	#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
		1107	#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1108	#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1109
		1110	#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
		1111	#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /!< Bit 0 /
		1112	#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /!< Bit 1 /
		1113
		1114	#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
		1115	#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /!< Bit 0 /
		1116	#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /!< Bit 1 /
		1117
		1118	#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
		1119	#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /!< Bit 0 /
		1120	#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /!< Bit 1 /
		1121
		1122	/***************** Bit definition for GPIO_CRH register *****************/
		1123	#define GPIO_CRH_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
		1124
		1125	#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
		1126	#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1127	#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1128
		1129	#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
		1130	#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1131	#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1132
		1133	#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
		1134	#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1135	#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1136
		1137	#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
		1138	#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /!< Bit 0 /
		1139	#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /!< Bit 1 /
		1140
		1141	#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
		1142	#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /!< Bit 0 /
		1143	#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /!< Bit 1 /
		1144
		1145	#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
		1146	#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /!< Bit 0 /
		1147	#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /!< Bit 1 /
		1148
		1149	#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
		1150	#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1151	#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1152
		1153	#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
		1154	#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /!< Bit 0 /
		1155	#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /!< Bit 1 /
		1156
		1157	#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
		1158
		1159	#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
		1160	#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1161	#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1162
		1163	#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
		1164	#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1165	#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1166
		1167	#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
		1168	#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1169	#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1170
		1171	#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
		1172	#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1173	#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1174
		1175	#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
		1176	#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1177	#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1178
		1179	#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
		1180	#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /!< Bit 0 /
		1181	#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /!< Bit 1 /
		1182
		1183	#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
		1184	#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /!< Bit 0 /
		1185	#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /!< Bit 1 /
		1186
		1187	#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
		1188	#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /!< Bit 0 /
		1189	#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /!< Bit 1 /
		1190
		1191	/!<*************** Bit definition for GPIO_IDR register *****************/
		1192	#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /!< Port input data, bit 0 /
		1193	#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /!< Port input data, bit 1 /
		1194	#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /!< Port input data, bit 2 /
		1195	#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /!< Port input data, bit 3 /
		1196	#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /!< Port input data, bit 4 /
		1197	#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /!< Port input data, bit 5 /
		1198	#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /!< Port input data, bit 6 /
		1199	#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /!< Port input data, bit 7 /
		1200	#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /!< Port input data, bit 8 /
		1201	#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /!< Port input data, bit 9 /
		1202	#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /!< Port input data, bit 10 /
		1203	#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /!< Port input data, bit 11 /
		1204	#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /!< Port input data, bit 12 /
		1205	#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /!< Port input data, bit 13 /
		1206	#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /!< Port input data, bit 14 /
		1207	#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /!< Port input data, bit 15 /
		1208
		1209	/***************** Bit definition for GPIO_ODR register *****************/
		1210	#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /!< Port output data, bit 0 /
		1211	#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /!< Port output data, bit 1 /
		1212	#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /!< Port output data, bit 2 /
		1213	#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /!< Port output data, bit 3 /
		1214	#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /!< Port output data, bit 4 /
		1215	#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /!< Port output data, bit 5 /
		1216	#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /!< Port output data, bit 6 /
		1217	#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /!< Port output data, bit 7 /
		1218	#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /!< Port output data, bit 8 /
		1219	#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /!< Port output data, bit 9 /
		1220	#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /!< Port output data, bit 10 /
		1221	#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /!< Port output data, bit 11 /
		1222	#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /!< Port output data, bit 12 /
		1223	#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /!< Port output data, bit 13 /
		1224	#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /!< Port output data, bit 14 /
		1225	#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /!< Port output data, bit 15 /
		1226
		1227	/**************** Bit definition for GPIO_BSRR register *****************/
		1228	#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /!< Port x Set bit 0 /
		1229	#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /!< Port x Set bit 1 /
		1230	#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /!< Port x Set bit 2 /
		1231	#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /!< Port x Set bit 3 /
		1232	#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /!< Port x Set bit 4 /
		1233	#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /!< Port x Set bit 5 /
		1234	#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /!< Port x Set bit 6 /
		1235	#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /!< Port x Set bit 7 /
		1236	#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /!< Port x Set bit 8 /
		1237	#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /!< Port x Set bit 9 /
		1238	#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /!< Port x Set bit 10 /
		1239	#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /!< Port x Set bit 11 /
		1240	#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /!< Port x Set bit 12 /
		1241	#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /!< Port x Set bit 13 /
		1242	#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /!< Port x Set bit 14 /
		1243	#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /!< Port x Set bit 15 /
		1244
		1245	#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /!< Port x Reset bit 0 /
		1246	#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /!< Port x Reset bit 1 /
		1247	#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /!< Port x Reset bit 2 /
		1248	#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /!< Port x Reset bit 3 /
		1249	#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /!< Port x Reset bit 4 /
		1250	#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /!< Port x Reset bit 5 /
		1251	#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /!< Port x Reset bit 6 /
		1252	#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /!< Port x Reset bit 7 /
		1253	#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /!< Port x Reset bit 8 /
		1254	#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /!< Port x Reset bit 9 /
		1255	#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /!< Port x Reset bit 10 /
		1256	#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /!< Port x Reset bit 11 /
		1257	#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /!< Port x Reset bit 12 /
		1258	#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /!< Port x Reset bit 13 /
		1259	#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /!< Port x Reset bit 14 /
		1260	#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /!< Port x Reset bit 15 /
		1261
		1262	/***************** Bit definition for GPIO_BRR register *****************/
		1263	#define GPIO_BRR_BR0 ((uint32_t)0x0001) /!< Port x Reset bit 0 /
		1264	#define GPIO_BRR_BR1 ((uint32_t)0x0002) /!< Port x Reset bit 1 /
		1265	#define GPIO_BRR_BR2 ((uint32_t)0x0004) /!< Port x Reset bit 2 /
		1266	#define GPIO_BRR_BR3 ((uint32_t)0x0008) /!< Port x Reset bit 3 /
		1267	#define GPIO_BRR_BR4 ((uint32_t)0x0010) /!< Port x Reset bit 4 /
		1268	#define GPIO_BRR_BR5 ((uint32_t)0x0020) /!< Port x Reset bit 5 /
		1269	#define GPIO_BRR_BR6 ((uint32_t)0x0040) /!< Port x Reset bit 6 /
		1270	#define GPIO_BRR_BR7 ((uint32_t)0x0080) /!< Port x Reset bit 7 /
		1271	#define GPIO_BRR_BR8 ((uint32_t)0x0100) /!< Port x Reset bit 8 /
		1272	#define GPIO_BRR_BR9 ((uint32_t)0x0200) /!< Port x Reset bit 9 /
		1273	#define GPIO_BRR_BR10 ((uint32_t)0x0400) /!< Port x Reset bit 10 /
		1274	#define GPIO_BRR_BR11 ((uint32_t)0x0800) /!< Port x Reset bit 11 /
		1275	#define GPIO_BRR_BR12 ((uint32_t)0x1000) /!< Port x Reset bit 12 /
		1276	#define GPIO_BRR_BR13 ((uint32_t)0x2000) /!< Port x Reset bit 13 /
		1277	#define GPIO_BRR_BR14 ((uint32_t)0x4000) /!< Port x Reset bit 14 /
		1278	#define GPIO_BRR_BR15 ((uint32_t)0x8000) /!< Port x Reset bit 15 /
		1279
		1280	/**************** Bit definition for GPIO_LCKR register *****************/
		1281	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /!< Port x Lock bit 0 /
		1282	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /!< Port x Lock bit 1 /
		1283	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /!< Port x Lock bit 2 /
		1284	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /!< Port x Lock bit 3 /
		1285	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /!< Port x Lock bit 4 /
		1286	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /!< Port x Lock bit 5 /
		1287	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /!< Port x Lock bit 6 /
		1288	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /!< Port x Lock bit 7 /
		1289	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /!< Port x Lock bit 8 /
		1290	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /!< Port x Lock bit 9 /
		1291	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /!< Port x Lock bit 10 /
		1292	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /!< Port x Lock bit 11 /
		1293	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /!< Port x Lock bit 12 /
		1294	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /!< Port x Lock bit 13 /
		1295	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /!< Port x Lock bit 14 /
		1296	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /!< Port x Lock bit 15 /
		1297	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /!< Lock key /
		1298
		1299	/----------------------------------------------------------------------------/
		1300
		1301	/**************** Bit definition for AFIO_EVCR register *****************/
		1302	#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /!< PIN[3:0] bits (Pin selection) /
		1303	#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1304	#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1305	#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /!< Bit 2 /
		1306	#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /!< Bit 3 /
		1307
		1308	/!< PIN configuration /
		1309	#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /!< Pin 0 selected /
		1310	#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /!< Pin 1 selected /
		1311	#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /!< Pin 2 selected /
		1312	#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /!< Pin 3 selected /
		1313	#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /!< Pin 4 selected /
		1314	#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /!< Pin 5 selected /
		1315	#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /!< Pin 6 selected /
		1316	#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /!< Pin 7 selected /
		1317	#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /!< Pin 8 selected /
		1318	#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /!< Pin 9 selected /
		1319	#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /!< Pin 10 selected /
		1320	#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /!< Pin 11 selected /
		1321	#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /!< Pin 12 selected /
		1322	#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /!< Pin 13 selected /
		1323	#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /!< Pin 14 selected /
		1324	#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /!< Pin 15 selected /
		1325
		1326	#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /!< PORT[2:0] bits (Port selection) /
		1327	#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1328	#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1329	#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /!< Bit 2 /
		1330
		1331	/!< PORT configuration /
		1332	#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /!< Port A selected /
		1333	#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /!< Port B selected /
		1334	#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /!< Port C selected /
		1335	#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /!< Port D selected /
		1336	#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /!< Port E selected /
		1337
		1338	#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /!< Event Output Enable /
		1339
		1340	/**************** Bit definition for AFIO_MAPR register *****************/
		1341	#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /!< SPI1 remapping /
		1342	#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /!< I2C1 remapping /
		1343	#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /!< USART1 remapping /
		1344	#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /!< USART2 remapping /
		1345
		1346	#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /!< USART3_REMAP[1:0] bits (USART3 remapping) /
		1347	#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1348	#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1349
		1350	/* USART3_REMAP configuration */
		1351	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
		1352	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
		1353	#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
		1354
		1355	#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
		1356	#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1357	#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1358
		1359	/!< TIM1_REMAP configuration /
		1360	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
		1361	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
		1362	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
		1363
		1364	#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
		1365	#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1366	#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1367
		1368	/!< TIM2_REMAP configuration /
		1369	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
		1370	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
		1371	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
		1372	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
		1373
		1374	#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
		1375	#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1376	#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1377
		1378	/!< TIM3_REMAP configuration /
		1379	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
		1380	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
		1381	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
		1382
		1383	#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /!< TIM4_REMAP bit (TIM4 remapping) /
		1384
		1385
		1386	#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
		1387
		1388	/!< SWJ_CFG configuration /
		1389	#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
		1390	#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1391	#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1392	#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /!< Bit 2 /
		1393
		1394	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
		1395	#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
		1396	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /!< JTAG-DP Disabled and SW-DP Enabled /
		1397	#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /!< JTAG-DP Disabled and SW-DP Disabled /
		1398
		1399
		1400	/*************** Bit definition for AFIO_EXTICR1 register ***************/
		1401	#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
		1402	#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
		1403	#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
		1404	#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
		1405
		1406	/!< EXTI0 configuration /
		1407	#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
		1408	#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
		1409	#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
		1410	#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
		1411	#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
		1412	#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
		1413	#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /!< PG[0] pin /
		1414
		1415	/!< EXTI1 configuration /
		1416	#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
		1417	#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
		1418	#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
		1419	#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
		1420	#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
		1421	#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
		1422	#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /!< PG[1] pin /
		1423
		1424	/!< EXTI2 configuration /
		1425	#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
		1426	#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
		1427	#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
		1428	#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
		1429	#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
		1430	#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
		1431	#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /!< PG[2] pin /
		1432
		1433	/!< EXTI3 configuration /
		1434	#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
		1435	#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
		1436	#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
		1437	#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
		1438	#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
		1439	#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
		1440	#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /!< PG[3] pin /
		1441
		1442	/*************** Bit definition for AFIO_EXTICR2 register ***************/
		1443	#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
		1444	#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
		1445	#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
		1446	#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
		1447
		1448	/!< EXTI4 configuration /
		1449	#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
		1450	#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
		1451	#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
		1452	#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
		1453	#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
		1454	#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
		1455	#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /!< PG[4] pin /
		1456
		1457	/* EXTI5 configuration */
		1458	#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
		1459	#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
		1460	#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
		1461	#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
		1462	#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
		1463	#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
		1464	#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /!< PG[5] pin /
		1465
		1466	/!< EXTI6 configuration /
		1467	#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
		1468	#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
		1469	#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
		1470	#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
		1471	#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
		1472	#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
		1473	#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /!< PG[6] pin /
		1474
		1475	/!< EXTI7 configuration /
		1476	#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
		1477	#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
		1478	#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
		1479	#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
		1480	#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
		1481	#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
		1482	#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /!< PG[7] pin /
		1483
		1484	/*************** Bit definition for AFIO_EXTICR3 register ***************/
		1485	#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
		1486	#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
		1487	#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
		1488	#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
		1489
		1490	/!< EXTI8 configuration /
		1491	#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
		1492	#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
		1493	#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
		1494	#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
		1495	#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
		1496	#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!< PF[8] pin /
		1497	#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /!< PG[8] pin /
		1498
		1499	/!< EXTI9 configuration /
		1500	#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
		1501	#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
		1502	#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
		1503	#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
		1504	#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
		1505	#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
		1506	#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /!< PG[9] pin /
		1507
		1508	/!< EXTI10 configuration /
		1509	#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
		1510	#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
		1511	#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
		1512	#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
		1513	#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PE[10] pin /
		1514	#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
		1515	#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /!< PG[10] pin /
		1516
		1517	/!< EXTI11 configuration /
		1518	#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
		1519	#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
		1520	#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
		1521	#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
		1522	#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
		1523	#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!< PF[11] pin /
		1524	#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /!< PG[11] pin /
		1525
		1526	/*************** Bit definition for AFIO_EXTICR4 register ***************/
		1527	#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
		1528	#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
		1529	#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
		1530	#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
		1531
		1532	/* EXTI12 configuration */
		1533	#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
		1534	#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
		1535	#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
		1536	#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
		1537	#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
		1538	#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!< PF[12] pin /
		1539	#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /!< PG[12] pin /
		1540
		1541	/* EXTI13 configuration */
		1542	#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
		1543	#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
		1544	#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
		1545	#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
		1546	#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
		1547	#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!< PF[13] pin /
		1548	#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /!< PG[13] pin /
		1549
		1550	/!< EXTI14 configuration /
		1551	#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
		1552	#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
		1553	#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
		1554	#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
		1555	#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
		1556	#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!< PF[14] pin /
		1557	#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /!< PG[14] pin /
		1558
		1559	/!< EXTI15 configuration /
		1560	#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
		1561	#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
		1562	#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
		1563	#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
		1564	#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
		1565	#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!< PF[15] pin /
		1566	#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /!< PG[15] pin /
		1567
		1568	/**************** Bit definition for AFIO_MAPR2 register ****************/
		1569
		1570
		1571
		1572	/******************************************************************************/
		1573	/* */
		1574	/* SystemTick */
		1575	/* */
		1576	/******************************************************************************/
		1577
		1578	/*************** Bit definition for SysTick_CTRL register ***************/
		1579	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
		1580	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
		1581	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
		1582	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
		1583
		1584	/*************** Bit definition for SysTick_LOAD register ***************/
		1585	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
		1586
		1587	/*************** Bit definition for SysTick_VAL register ****************/
		1588	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
		1589
		1590	/*************** Bit definition for SysTick_CALIB register **************/
		1591	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
		1592	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
		1593	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
		1594
		1595	/******************************************************************************/
		1596	/* */
		1597	/* Nested Vectored Interrupt Controller */
		1598	/* */
		1599	/******************************************************************************/
		1600
		1601	/**************** Bit definition for NVIC_ISER register *****************/
		1602	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
		1603	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
		1604	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
		1605	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
		1606	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
		1607	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
		1608	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
		1609	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
		1610	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
		1611	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
		1612	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
		1613	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
		1614	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
		1615	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
		1616	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
		1617	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
		1618	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
		1619	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
		1620	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
		1621	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
		1622	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
		1623	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
		1624	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
		1625	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
		1626	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
		1627	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
		1628	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
		1629	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
		1630	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
		1631	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
		1632	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
		1633	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
		1634	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
		1635
		1636	/**************** Bit definition for NVIC_ICER register *****************/
		1637	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
		1638	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
		1639	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
		1640	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
		1641	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
		1642	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
		1643	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
		1644	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
		1645	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
		1646	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
		1647	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
		1648	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
		1649	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
		1650	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
		1651	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
		1652	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
		1653	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
		1654	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
		1655	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
		1656	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
		1657	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
		1658	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
		1659	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
		1660	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
		1661	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
		1662	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
		1663	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
		1664	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
		1665	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
		1666	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
		1667	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
		1668	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
		1669	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
		1670
		1671	/**************** Bit definition for NVIC_ISPR register *****************/
		1672	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
		1673	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
		1674	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
		1675	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
		1676	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
		1677	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
		1678	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
		1679	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
		1680	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
		1681	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
		1682	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
		1683	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
		1684	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
		1685	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
		1686	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
		1687	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
		1688	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
		1689	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
		1690	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
		1691	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
		1692	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
		1693	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
		1694	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
		1695	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
		1696	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
		1697	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
		1698	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
		1699	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
		1700	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
		1701	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
		1702	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
		1703	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
		1704	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
		1705
		1706	/**************** Bit definition for NVIC_ICPR register *****************/
		1707	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
		1708	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
		1709	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
		1710	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
		1711	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
		1712	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
		1713	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
		1714	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
		1715	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
		1716	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
		1717	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
		1718	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
		1719	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
		1720	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
		1721	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
		1722	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
		1723	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
		1724	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
		1725	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
		1726	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
		1727	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
		1728	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
		1729	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
		1730	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
		1731	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
		1732	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
		1733	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
		1734	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
		1735	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
		1736	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
		1737	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
		1738	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
		1739	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
		1740
		1741	/**************** Bit definition for NVIC_IABR register *****************/
		1742	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
		1743	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
		1744	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
		1745	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
		1746	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
		1747	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
		1748	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
		1749	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
		1750	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
		1751	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
		1752	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
		1753	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
		1754	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
		1755	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
		1756	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
		1757	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
		1758	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
		1759	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
		1760	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
		1761	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
		1762	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
		1763	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
		1764	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
		1765	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
		1766	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
		1767	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
		1768	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
		1769	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
		1770	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
		1771	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
		1772	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
		1773	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
		1774	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
		1775
		1776	/**************** Bit definition for NVIC_PRI0 register *****************/
		1777	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
		1778	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
		1779	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
		1780	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
		1781
		1782	/**************** Bit definition for NVIC_PRI1 register *****************/
		1783	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
		1784	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
		1785	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
		1786	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
		1787
		1788	/**************** Bit definition for NVIC_PRI2 register *****************/
		1789	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
		1790	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
		1791	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
		1792	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
		1793
		1794	/**************** Bit definition for NVIC_PRI3 register *****************/
		1795	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
		1796	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
		1797	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
		1798	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
		1799
		1800	/**************** Bit definition for NVIC_PRI4 register *****************/
		1801	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
		1802	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
		1803	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
		1804	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
		1805
		1806	/**************** Bit definition for NVIC_PRI5 register *****************/
		1807	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
		1808	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
		1809	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
		1810	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
		1811
		1812	/**************** Bit definition for NVIC_PRI6 register *****************/
		1813	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
		1814	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
		1815	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
		1816	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
		1817
		1818	/**************** Bit definition for NVIC_PRI7 register *****************/
		1819	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
		1820	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
		1821	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
		1822	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
		1823
		1824	/**************** Bit definition for SCB_CPUID register *****************/
		1825	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
		1826	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
		1827	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
		1828	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
		1829	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
		1830
		1831	/***************** Bit definition for SCB_ICSR register *****************/
		1832	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
		1833	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
		1834	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
		1835	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
		1836	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
		1837	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
		1838	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
		1839	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
		1840	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
		1841	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
		1842
		1843	/***************** Bit definition for SCB_VTOR register *****************/
		1844	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
		1845	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
		1846
		1847	/!<************** Bit definition for SCB_AIRCR register *****************/
		1848	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
		1849	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
		1850	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
		1851
		1852	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
		1853	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1854	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1855	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
		1856
		1857	/* prority group configuration */
		1858	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
		1859	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
		1860	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
		1861	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
		1862	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
		1863	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
		1864	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
		1865	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
		1866
		1867	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
		1868	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
		1869
		1870	/***************** Bit definition for SCB_SCR register ******************/
		1871	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
		1872	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
		1873	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
		1874
		1875	/****************** Bit definition for SCB_CCR register *****************/
		1876	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
		1877	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
		1878	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
		1879	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
		1880	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
		1881	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
		1882
		1883	/***************** Bit definition for SCB_SHPR register ******************/
		1884	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
		1885	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
		1886	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
		1887	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
		1888
		1889	/**************** Bit definition for SCB_SHCSR register *****************/
		1890	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
		1891	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
		1892	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
		1893	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
		1894	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
		1895	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
		1896	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
		1897	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
		1898	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
		1899	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
		1900	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
		1901	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
		1902	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
		1903	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
		1904
		1905	/***************** Bit definition for SCB_CFSR register *****************/
		1906	/!< MFSR /
		1907	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
		1908	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
		1909	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
		1910	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
		1911	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
		1912	/!< BFSR /
		1913	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
		1914	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
		1915	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
		1916	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
		1917	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
		1918	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
		1919	/!< UFSR /
		1920	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to execute an undefined instruction /
		1921	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
		1922	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
		1923	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
		1924	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
		1925	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
		1926
		1927	/***************** Bit definition for SCB_HFSR register *****************/
		1928	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
		1929	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
		1930	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
		1931
		1932	/***************** Bit definition for SCB_DFSR register *****************/
		1933	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
		1934	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
		1935	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
		1936	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
		1937	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
		1938
		1939	/***************** Bit definition for SCB_MMFAR register ****************/
		1940	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
		1941
		1942	/***************** Bit definition for SCB_BFAR register *****************/
		1943	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
		1944
		1945	/***************** Bit definition for SCB_afsr register *****************/
		1946	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
		1947
		1948	/******************************************************************************/
		1949	/* */
		1950	/* External Interrupt/Event Controller */
		1951	/* */
		1952	/******************************************************************************/
		1953
		1954	/***************** Bit definition for EXTI_IMR register *****************/
		1955	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
		1956	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
		1957	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
		1958	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
		1959	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
		1960	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
		1961	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
		1962	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
		1963	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
		1964	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
		1965	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
		1966	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
		1967	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
		1968	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
		1969	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
		1970	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
		1971	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
		1972	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
		1973	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
		1974	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
		1975
		1976	/***************** Bit definition for EXTI_EMR register *****************/
		1977	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
		1978	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
		1979	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
		1980	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
		1981	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
		1982	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
		1983	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
		1984	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
		1985	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
		1986	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
		1987	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
		1988	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
		1989	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
		1990	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
		1991	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
		1992	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
		1993	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
		1994	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
		1995	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
		1996	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
		1997
		1998	/**************** Bit definition for EXTI_RTSR register *****************/
		1999	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
		2000	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
		2001	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
		2002	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
		2003	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
		2004	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
		2005	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
		2006	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
		2007	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
		2008	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
		2009	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
		2010	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
		2011	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
		2012	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
		2013	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
		2014	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
		2015	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
		2016	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
		2017	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
		2018	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
		2019
		2020	/**************** Bit definition for EXTI_FTSR register *****************/
		2021	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
		2022	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
		2023	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
		2024	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
		2025	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
		2026	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
		2027	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
		2028	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
		2029	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
		2030	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
		2031	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
		2032	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
		2033	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
		2034	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
		2035	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
		2036	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
		2037	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
		2038	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
		2039	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
		2040	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
		2041
		2042	/**************** Bit definition for EXTI_SWIER register ****************/
		2043	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
		2044	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
		2045	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
		2046	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
		2047	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
		2048	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
		2049	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
		2050	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
		2051	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
		2052	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
		2053	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
		2054	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
		2055	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
		2056	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
		2057	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
		2058	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
		2059	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
		2060	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
		2061	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
		2062	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
		2063
		2064	/***************** Bit definition for EXTI_PR register ******************/
		2065	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
		2066	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
		2067	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
		2068	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
		2069	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
		2070	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
		2071	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
		2072	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
		2073	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
		2074	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
		2075	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
		2076	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
		2077	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
		2078	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
		2079	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
		2080	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
		2081	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
		2082	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
		2083	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
		2084	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
		2085
		2086	/******************************************************************************/
		2087	/* */
		2088	/* DMA Controller */
		2089	/* */
		2090	/******************************************************************************/
		2091
		2092	/***************** Bit definition for DMA_ISR register ******************/
		2093	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
		2094	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
		2095	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
		2096	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
		2097	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
		2098	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
		2099	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
		2100	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
		2101	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
		2102	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
		2103	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
		2104	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
		2105	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
		2106	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
		2107	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
		2108	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
		2109	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
		2110	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
		2111	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
		2112	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
		2113	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
		2114	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
		2115	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
		2116	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
		2117	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
		2118	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
		2119	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
		2120	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
		2121
		2122	/***************** Bit definition for DMA_IFCR register *****************/
		2123	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
		2124	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
		2125	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
		2126	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
		2127	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
		2128	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
		2129	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
		2130	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
		2131	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
		2132	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
		2133	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
		2134	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
		2135	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
		2136	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
		2137	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
		2138	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
		2139	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
		2140	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
		2141	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
		2142	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
		2143	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
		2144	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
		2145	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
		2146	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
		2147	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
		2148	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
		2149	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
		2150	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
		2151
		2152	/***************** Bit definition for DMA_CCR register *****************/
		2153	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
		2154	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
		2155	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
		2156	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
		2157	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
		2158	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
		2159	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
		2160	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
		2161
		2162	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
		2163	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2164	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2165
		2166	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
		2167	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2168	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2169
		2170	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level) /
		2171	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2172	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2173
		2174	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
		2175
		2176	/**************** Bit definition for DMA_CNDTR register ****************/
		2177	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
		2178
		2179	/**************** Bit definition for DMA_CPAR register *****************/
		2180	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
		2181
		2182	/**************** Bit definition for DMA_CMAR register *****************/
		2183	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
		2184
		2185	/******************************************************************************/
		2186	/* */
		2187	/* Analog to Digital Converter */
		2188	/* */
		2189	/******************************************************************************/
		2190
		2191	/****************** Bit definition for ADC_SR register ******************/
		2192	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
		2193	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
		2194	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
		2195	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
		2196	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
		2197
		2198	/***************** Bit definition for ADC_CR1 register ******************/
		2199	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
		2200	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2201	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2202	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2203	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2204	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2205
		2206	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
		2207	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
		2208	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
		2209	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
		2210	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
		2211	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
		2212	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
		2213	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
		2214
		2215	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
		2216	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
		2217	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
		2218	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
		2219
		2220	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
		2221	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
		2222
		2223
		2224	/***************** Bit definition for ADC_CR2 register ******************/
		2225	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
		2226	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
		2227	#define ADC_CR2_CAL ((uint32_t)0x00000004) /!< A/D Calibration /
		2228	#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /!< Reset Calibration /
		2229	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
		2230	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
		2231
		2232	#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /!< JEXTSEL[2:0] bits (External event select for injected group) /
		2233	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2234	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2235	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2236
		2237	#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /!< External Trigger Conversion mode for injected channels /
		2238
		2239	#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
		2240	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /!< Bit 0 /
		2241	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /!< Bit 1 /
		2242	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /!< Bit 2 /
		2243
		2244	#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /!< External Trigger Conversion mode for regular channels /
		2245	#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /!< Start Conversion of injected channels /
		2246	#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /!< Start Conversion of regular channels /
		2247	#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
		2248
		2249	/**************** Bit definition for ADC_SMPR1 register *****************/
		2250	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
		2251	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2252	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2253	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2254
		2255	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
		2256	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2257	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2258	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2259
		2260	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
		2261	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2262	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2263	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
		2264
		2265	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
		2266	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
		2267	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
		2268	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
		2269
		2270	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
		2271	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2272	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2273	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2274
		2275	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 15 Sample time selection) /
		2276	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2277	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2278	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2279
		2280	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
		2281	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
		2282	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
		2283	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
		2284
		2285	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
		2286	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
		2287	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
		2288	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
		2289
		2290	/**************** Bit definition for ADC_SMPR2 register *****************/
		2291	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
		2292	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2293	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2294	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2295
		2296	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
		2297	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2298	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2299	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2300
		2301	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
		2302	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2303	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2304	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
		2305
		2306	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
		2307	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
		2308	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
		2309	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
		2310
		2311	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
		2312	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2313	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2314	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2315
		2316	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
		2317	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2318	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2319	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2320
		2321	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
		2322	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
		2323	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
		2324	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
		2325
		2326	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
		2327	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
		2328	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
		2329	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
		2330
		2331	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
		2332	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
		2333	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
		2334	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
		2335
		2336	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
		2337	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
		2338	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
		2339	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
		2340
		2341	/**************** Bit definition for ADC_JOFR1 register *****************/
		2342	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
		2343
		2344	/**************** Bit definition for ADC_JOFR2 register *****************/
		2345	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
		2346
		2347	/**************** Bit definition for ADC_JOFR3 register *****************/
		2348	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
		2349
		2350	/**************** Bit definition for ADC_JOFR4 register *****************/
		2351	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
		2352
		2353	/***************** Bit definition for ADC_HTR register ******************/
		2354	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
		2355
		2356	/***************** Bit definition for ADC_LTR register ******************/
		2357	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
		2358
		2359	/***************** Bit definition for ADC_SQR1 register *****************/
		2360	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
		2361	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2362	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2363	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2364	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2365	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2366
		2367	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
		2368	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2369	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2370	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2371	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2372	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2373
		2374	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
		2375	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2376	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2377	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2378	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2379	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2380
		2381	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
		2382	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2383	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2384	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2385	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2386	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2387
		2388	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!< L[3:0] bits (Regular channel sequence length) /
		2389	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2390	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2391	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2392	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2393
		2394	/***************** Bit definition for ADC_SQR2 register *****************/
		2395	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
		2396	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2397	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2398	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2399	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2400	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2401
		2402	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
		2403	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2404	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2405	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2406	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2407	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2408
		2409	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
		2410	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2411	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2412	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2413	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2414	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2415
		2416	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
		2417	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2418	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2419	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2420	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2421	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2422
		2423	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
		2424	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2425	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2426	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2427	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2428	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
		2429
		2430	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
		2431	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
		2432	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
		2433	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
		2434	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
		2435	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
		2436
		2437	/***************** Bit definition for ADC_SQR3 register *****************/
		2438	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
		2439	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2440	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2441	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2442	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2443	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2444
		2445	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
		2446	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2447	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2448	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2449	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2450	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2451
		2452	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
		2453	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2454	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2455	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2456	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2457	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2458
		2459	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
		2460	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2461	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2462	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2463	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2464	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2465
		2466	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
		2467	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2468	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2469	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2470	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2471	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
		2472
		2473	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
		2474	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
		2475	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
		2476	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
		2477	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
		2478	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
		2479
		2480	/***************** Bit definition for ADC_JSQR register *****************/
		2481	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
		2482	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2483	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2484	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2485	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2486	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2487
		2488	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
		2489	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2490	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2491	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2492	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2493	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2494
		2495	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
		2496	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2497	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2498	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2499	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2500	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2501
		2502	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
		2503	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2504	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2505	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2506	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2507	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2508
		2509	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
		2510	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2511	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2512
		2513	/***************** Bit definition for ADC_JDR1 register *****************/
		2514	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2515
		2516	/***************** Bit definition for ADC_JDR2 register *****************/
		2517	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2518
		2519	/***************** Bit definition for ADC_JDR3 register *****************/
		2520	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2521
		2522	/***************** Bit definition for ADC_JDR4 register *****************/
		2523	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2524
		2525	/****************** Bit definition for ADC_DR register ******************/
		2526	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
		2527
		2528
		2529	/*****************************************************************************/
		2530	/* */
		2531	/* Timers (TIM) */
		2532	/* */
		2533	/*****************************************************************************/
		2534	/***************** Bit definition for TIM_CR1 register *****************/
		2535	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
		2536	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
		2537	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
		2538	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
		2539	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
		2540
		2541	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
		2542	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
		2543	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
		2544
		2545	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
		2546
		2547	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
		2548	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
		2549	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
		2550
		2551	/***************** Bit definition for TIM_CR2 register *****************/
		2552	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
		2553	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
		2554	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
		2555
		2556	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
		2557	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
		2558	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
		2559	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
		2560
		2561	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
		2562	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
		2563	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
		2564	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
		2565	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
		2566	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
		2567	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
		2568	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
		2569
		2570	/***************** Bit definition for TIM_SMCR register ****************/
		2571	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
		2572	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
		2573	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
		2574	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
		2575
		2576	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
		2577
		2578	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
		2579	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
		2580	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
		2581	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
		2582
		2583	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
		2584
		2585	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
		2586	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
		2587	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
		2588	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
		2589	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
		2590
		2591	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
		2592	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
		2593	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
		2594
		2595	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
		2596	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
		2597
		2598	/***************** Bit definition for TIM_DIER register ****************/
		2599	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
		2600	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
		2601	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
		2602	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
		2603	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
		2604	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
		2605	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
		2606	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
		2607	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
		2608	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
		2609	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
		2610	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
		2611	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
		2612	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
		2613	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
		2614
		2615	/****************** Bit definition for TIM_SR register *****************/
		2616	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
		2617	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
		2618	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
		2619	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
		2620	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
		2621	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
		2622	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
		2623	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
		2624	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
		2625	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
		2626	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
		2627	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
		2628
		2629	/***************** Bit definition for TIM_EGR register *****************/
		2630	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
		2631	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
		2632	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
		2633	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
		2634	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
		2635	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
		2636	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
		2637	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
		2638
		2639	/**************** Bit definition for TIM_CCMR1 register ****************/
		2640	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
		2641	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
		2642	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
		2643
		2644	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
		2645	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
		2646
		2647	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
		2648	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
		2649	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
		2650	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
		2651
		2652	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
		2653
		2654	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
		2655	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
		2656	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
		2657
		2658	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
		2659	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
		2660
		2661	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
		2662	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
		2663	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
		2664	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
		2665
		2666	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
		2667
		2668	/---------------------------------------------------------------------------/
		2669
		2670	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
		2671	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
		2672	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
		2673
		2674	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
		2675	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
		2676	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
		2677	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
		2678	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
		2679
		2680	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
		2681	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
		2682	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
		2683
		2684	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
		2685	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
		2686	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
		2687	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
		2688	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
		2689
		2690	/**************** Bit definition for TIM_CCMR2 register ****************/
		2691	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
		2692	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
		2693	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
		2694
		2695	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
		2696	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
		2697
		2698	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
		2699	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
		2700	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
		2701	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
		2702
		2703	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
		2704
		2705	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
		2706	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
		2707	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
		2708
		2709	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
		2710	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
		2711
		2712	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
		2713	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
		2714	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
		2715	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
		2716
		2717	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
		2718
		2719	/---------------------------------------------------------------------------/
		2720
		2721	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
		2722	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
		2723	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
		2724
		2725	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
		2726	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
		2727	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
		2728	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
		2729	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
		2730
		2731	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
		2732	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
		2733	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
		2734
		2735	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
		2736	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
		2737	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
		2738	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
		2739	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
		2740
		2741	/***************** Bit definition for TIM_CCER register ****************/
		2742	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
		2743	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
		2744	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
		2745	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
		2746	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
		2747	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
		2748	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
		2749	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
		2750	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
		2751	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
		2752	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
		2753	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
		2754	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
		2755	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
		2756	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
		2757
		2758	/***************** Bit definition for TIM_CNT register *****************/
		2759	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
		2760
		2761	/***************** Bit definition for TIM_PSC register *****************/
		2762	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
		2763
		2764	/***************** Bit definition for TIM_ARR register *****************/
		2765	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
		2766
		2767	/***************** Bit definition for TIM_RCR register *****************/
		2768	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
		2769
		2770	/***************** Bit definition for TIM_CCR1 register ****************/
		2771	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
		2772
		2773	/***************** Bit definition for TIM_CCR2 register ****************/
		2774	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
		2775
		2776	/***************** Bit definition for TIM_CCR3 register ****************/
		2777	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
		2778
		2779	/***************** Bit definition for TIM_CCR4 register ****************/
		2780	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
		2781
		2782	/***************** Bit definition for TIM_BDTR register ****************/
		2783	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
		2784	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
		2785	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
		2786	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
		2787	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
		2788	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
		2789	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
		2790	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
		2791	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
		2792
		2793	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
		2794	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
		2795	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
		2796
		2797	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
		2798	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
		2799	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
		2800	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
		2801	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
		2802	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
		2803
		2804	/***************** Bit definition for TIM_DCR register *****************/
		2805	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
		2806	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
		2807	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
		2808	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
		2809	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
		2810	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
		2811
		2812	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
		2813	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
		2814	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
		2815	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
		2816	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
		2817	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
		2818
		2819	/***************** Bit definition for TIM_DMAR register ****************/
		2820	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
		2821
		2822	/***************** Bit definition for TIM_OR register ******************/
		2823
		2824	/******************************************************************************/
		2825	/* */
		2826	/* Real-Time Clock */
		2827	/* */
		2828	/******************************************************************************/
		2829
		2830	/***************** Bit definition for RTC_CRH register ******************/
		2831	#define RTC_CRH_SECIE ((uint32_t)0x00000001) /!< Second Interrupt Enable /
		2832	#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /!< Alarm Interrupt Enable /
		2833	#define RTC_CRH_OWIE ((uint32_t)0x00000004) /!< OverfloW Interrupt Enable /
		2834
		2835	/***************** Bit definition for RTC_CRL register ******************/
		2836	#define RTC_CRL_SECF ((uint32_t)0x00000001) /!< Second Flag /
		2837	#define RTC_CRL_ALRF ((uint32_t)0x00000002) /!< Alarm Flag /
		2838	#define RTC_CRL_OWF ((uint32_t)0x00000004) /!< OverfloW Flag /
		2839	#define RTC_CRL_RSF ((uint32_t)0x00000008) /!< Registers Synchronized Flag /
		2840	#define RTC_CRL_CNF ((uint32_t)0x00000010) /!< Configuration Flag /
		2841	#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /!< RTC operation OFF /
		2842
		2843	/***************** Bit definition for RTC_PRLH register *****************/
		2844	#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /!< RTC Prescaler Reload Value High /
		2845
		2846	/***************** Bit definition for RTC_PRLL register *****************/
		2847	#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /!< RTC Prescaler Reload Value Low /
		2848
		2849	/***************** Bit definition for RTC_DIVH register *****************/
		2850	#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /!< RTC Clock Divider High /
		2851
		2852	/***************** Bit definition for RTC_DIVL register *****************/
		2853	#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /!< RTC Clock Divider Low /
		2854
		2855	/***************** Bit definition for RTC_CNTH register *****************/
		2856	#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter High /
		2857
		2858	/***************** Bit definition for RTC_CNTL register *****************/
		2859	#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter Low /
		2860
		2861	/***************** Bit definition for RTC_ALRH register *****************/
		2862	#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm High /
		2863
		2864	/***************** Bit definition for RTC_ALRL register *****************/
		2865	#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm Low /
		2866
		2867	/******************************************************************************/
		2868	/* */
		2869	/* Independent WATCHDOG (IWDG) */
		2870	/* */
		2871	/******************************************************************************/
		2872
		2873	/***************** Bit definition for IWDG_KR register ******************/
		2874	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!< Key value (write only, read 0000h) /
		2875
		2876	/***************** Bit definition for IWDG_PR register ******************/
		2877	#define IWDG_PR_PR ((uint32_t)0x00000007) /!< PR[2:0] (Prescaler divider) /
		2878	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2879	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2880	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2881
		2882	/***************** Bit definition for IWDG_RLR register *****************/
		2883	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!< Watchdog counter reload value /
		2884
		2885	/***************** Bit definition for IWDG_SR register ******************/
		2886	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
		2887	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
		2888
		2889	/******************************************************************************/
		2890	/* */
		2891	/* Window WATCHDOG */
		2892	/* */
		2893	/******************************************************************************/
		2894
		2895	/***************** Bit definition for WWDG_CR register ******************/
		2896	#define WWDG_CR_T ((uint32_t)0x0000007F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
		2897	#define WWDG_CR_T0 ((uint32_t)0x00000001) /!< Bit 0 /
		2898	#define WWDG_CR_T1 ((uint32_t)0x00000002) /!< Bit 1 /
		2899	#define WWDG_CR_T2 ((uint32_t)0x00000004) /!< Bit 2 /
		2900	#define WWDG_CR_T3 ((uint32_t)0x00000008) /!< Bit 3 /
		2901	#define WWDG_CR_T4 ((uint32_t)0x00000010) /!< Bit 4 /
		2902	#define WWDG_CR_T5 ((uint32_t)0x00000020) /!< Bit 5 /
		2903	#define WWDG_CR_T6 ((uint32_t)0x00000040) /!< Bit 6 /
		2904
		2905	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!< Activation bit /
		2906
		2907	/***************** Bit definition for WWDG_CFR register *****************/
		2908	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!< W[6:0] bits (7-bit window value) /
		2909	#define WWDG_CFR_W0 ((uint32_t)0x00000001) /!< Bit 0 /
		2910	#define WWDG_CFR_W1 ((uint32_t)0x00000002) /!< Bit 1 /
		2911	#define WWDG_CFR_W2 ((uint32_t)0x00000004) /!< Bit 2 /
		2912	#define WWDG_CFR_W3 ((uint32_t)0x00000008) /!< Bit 3 /
		2913	#define WWDG_CFR_W4 ((uint32_t)0x00000010) /!< Bit 4 /
		2914	#define WWDG_CFR_W5 ((uint32_t)0x00000020) /!< Bit 5 /
		2915	#define WWDG_CFR_W6 ((uint32_t)0x00000040) /!< Bit 6 /
		2916
		2917	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!< WDGTB[1:0] bits (Timer Base) /
		2918	#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /!< Bit 0 /
		2919	#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /!< Bit 1 /
		2920
		2921	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!< Early Wakeup Interrupt /
		2922
		2923	/***************** Bit definition for WWDG_SR register ******************/
		2924	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!< Early Wakeup Interrupt Flag /
		2925
		2926
		2927	/******************************************************************************/
		2928	/* */
		2929	/* SD host Interface */
		2930	/* */
		2931	/******************************************************************************/
		2932
		2933	/**************** Bit definition for SDIO_POWER register ****************/
		2934	#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /!< PWRCTRL[1:0] bits (Power supply control bits) /
		2935	#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /!< Bit 0 /
		2936	#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /!< Bit 1 /
		2937
		2938	/**************** Bit definition for SDIO_CLKCR register ****************/
		2939	#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /!< Clock divide factor /
		2940	#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /!< Clock enable bit /
		2941	#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /!< Power saving configuration bit /
		2942	#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /!< Clock divider bypass enable bit /
		2943
		2944	#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
		2945	#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /!< Bit 0 /
		2946	#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /!< Bit 1 /
		2947
		2948	#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /!< SDIO_CK dephasing selection bit /
		2949	#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /!< HW Flow Control enable /
		2950
		2951	/***************** Bit definition for SDIO_ARG register *****************/
		2952	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!< Command argument /
		2953
		2954	/***************** Bit definition for SDIO_CMD register *****************/
		2955	#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /!< Command Index /
		2956
		2957	#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /!< WAITRESP[1:0] bits (Wait for response bits) /
		2958	#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /!< Bit 0 /
		2959	#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /!< Bit 1 /
		2960
		2961	#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /!< CPSM Waits for Interrupt Request /
		2962	#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
		2963	#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /!< Command path state machine (CPSM) Enable bit /
		2964	#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /!< SD I/O suspend command /
		2965	#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /!< Enable CMD completion /
		2966	#define SDIO_CMD_NIEN ((uint32_t)0x2000) /!< Not Interrupt Enable /
		2967	#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /!< CE-ATA command /
		2968
		2969	/*************** Bit definition for SDIO_RESPCMD register ***************/
		2970	#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /!< Response command index /
		2971
		2972	/**************** Bit definition for SDIO_RESP0 register ****************/
		2973	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		2974
		2975	/**************** Bit definition for SDIO_RESP1 register ****************/
		2976	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		2977
		2978	/**************** Bit definition for SDIO_RESP2 register ****************/
		2979	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		2980
		2981	/**************** Bit definition for SDIO_RESP3 register ****************/
		2982	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		2983
		2984	/**************** Bit definition for SDIO_RESP4 register ****************/
		2985	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		2986
		2987	/**************** Bit definition for SDIO_DTIMER register ***************/
		2988	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!< Data timeout period. /
		2989
		2990	/**************** Bit definition for SDIO_DLEN register *****************/
		2991	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!< Data length value /
		2992
		2993	/**************** Bit definition for SDIO_DCTRL register ****************/
		2994	#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /!< Data transfer enabled bit /
		2995	#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /!< Data transfer direction selection /
		2996	#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /!< Data transfer mode selection /
		2997	#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /!< DMA enabled bit /
		2998
		2999	#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /!< DBLOCKSIZE[3:0] bits (Data block size) /
		3000	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /!< Bit 0 /
		3001	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /!< Bit 1 /
		3002	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /!< Bit 2 /
		3003	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /!< Bit 3 /
		3004
		3005	#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /!< Read wait start /
		3006	#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /!< Read wait stop /
		3007	#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /!< Read wait mode /
		3008	#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /!< SD I/O enable functions /
		3009
		3010	/**************** Bit definition for SDIO_DCOUNT register ***************/
		3011	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!< Data count value /
		3012
		3013	/**************** Bit definition for SDIO_STA register ******************/
		3014	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!< Command response received (CRC check failed) /
		3015	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!< Data block sent/received (CRC check failed) /
		3016	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!< Command response timeout /
		3017	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!< Data timeout /
		3018	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!< Transmit FIFO underrun error /
		3019	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!< Received FIFO overrun error /
		3020	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!< Command response received (CRC check passed) /
		3021	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!< Command sent (no response required) /
		3022	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!< Data end (data counter, SDIDCOUNT, is zero) /
		3023	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!< Start bit not detected on all data signals in wide bus mode /
		3024	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!< Data block sent/received (CRC check passed) /
		3025	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!< Command transfer in progress /
		3026	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!< Data transmit in progress /
		3027	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!< Data receive in progress /
		3028	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
		3029	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
		3030	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!< Transmit FIFO full /
		3031	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!< Receive FIFO full /
		3032	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!< Transmit FIFO empty /
		3033	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!< Receive FIFO empty /
		3034	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!< Data available in transmit FIFO /
		3035	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!< Data available in receive FIFO /
		3036	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!< SDIO interrupt received /
		3037	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!< CE-ATA command completion signal received for CMD61 /
		3038
		3039	/***************** Bit definition for SDIO_ICR register *****************/
		3040	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!< CCRCFAIL flag clear bit /
		3041	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!< DCRCFAIL flag clear bit /
		3042	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!< CTIMEOUT flag clear bit /
		3043	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!< DTIMEOUT flag clear bit /
		3044	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!< TXUNDERR flag clear bit /
		3045	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!< RXOVERR flag clear bit /
		3046	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!< CMDREND flag clear bit /
		3047	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!< CMDSENT flag clear bit /
		3048	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!< DATAEND flag clear bit /
		3049	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!< STBITERR flag clear bit /
		3050	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!< DBCKEND flag clear bit /
		3051	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!< SDIOIT flag clear bit /
		3052	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!< CEATAEND flag clear bit /
		3053
		3054	/**************** Bit definition for SDIO_MASK register *****************/
		3055	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!< Command CRC Fail Interrupt Enable /
		3056	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!< Data CRC Fail Interrupt Enable /
		3057	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!< Command TimeOut Interrupt Enable /
		3058	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!< Data TimeOut Interrupt Enable /
		3059	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!< Tx FIFO UnderRun Error Interrupt Enable /
		3060	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!< Rx FIFO OverRun Error Interrupt Enable /
		3061	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!< Command Response Received Interrupt Enable /
		3062	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!< Command Sent Interrupt Enable /
		3063	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!< Data End Interrupt Enable /
		3064	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!< Start Bit Error Interrupt Enable /
		3065	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!< Data Block End Interrupt Enable /
		3066	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!< Command Acting Interrupt Enable /
		3067	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!< Data Transmit Acting Interrupt Enable /
		3068	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!< Data receive acting interrupt enabled /
		3069	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!< Tx FIFO Half Empty interrupt Enable /
		3070	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!< Rx FIFO Half Full interrupt Enable /
		3071	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!< Tx FIFO Full interrupt Enable /
		3072	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!< Rx FIFO Full interrupt Enable /
		3073	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!< Tx FIFO Empty interrupt Enable /
		3074	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!< Rx FIFO Empty interrupt Enable /
		3075	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!< Data available in Tx FIFO interrupt Enable /
		3076	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!< Data available in Rx FIFO interrupt Enable /
		3077	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!< SDIO Mode Interrupt Received interrupt Enable /
		3078	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!< CE-ATA command completion signal received Interrupt Enable /
		3079
		3080	/*************** Bit definition for SDIO_FIFOCNT register ***************/
		3081	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!< Remaining number of words to be written to or read from the FIFO /
		3082
		3083	/**************** Bit definition for SDIO_FIFO register *****************/
		3084	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!< Receive and transmit FIFO data /
		3085
		3086	/******************************************************************************/
		3087	/* */
		3088	/* USB Device FS */
		3089	/* */
		3090	/******************************************************************************/
		3091
		3092	/!< Endpoint-specific registers /
		3093	#define USB_EP0R USB_BASE /!< Endpoint 0 register address /
		3094	#define USB_EP1R (USB_BASE + 0x00000004) /!< Endpoint 1 register address /
		3095	#define USB_EP2R (USB_BASE + 0x00000008) /!< Endpoint 2 register address /
		3096	#define USB_EP3R (USB_BASE + 0x0000000C) /!< Endpoint 3 register address /
		3097	#define USB_EP4R (USB_BASE + 0x00000010) /!< Endpoint 4 register address /
		3098	#define USB_EP5R (USB_BASE + 0x00000014) /!< Endpoint 5 register address /
		3099	#define USB_EP6R (USB_BASE + 0x00000018) /!< Endpoint 6 register address /
		3100	#define USB_EP7R (USB_BASE + 0x0000001C) /!< Endpoint 7 register address /
		3101
		3102	/* bit positions */
		3103	#define USB_EP_CTR_RX ((uint32_t)0x00008000) /!< EndPoint Correct TRansfer RX /
		3104	#define USB_EP_DTOG_RX ((uint32_t)0x00004000) /!< EndPoint Data TOGGLE RX /
		3105	#define USB_EPRX_STAT ((uint32_t)0x00003000) /!< EndPoint RX STATus bit field /
		3106	#define USB_EP_SETUP ((uint32_t)0x00000800) /!< EndPoint SETUP /
		3107	#define USB_EP_T_FIELD ((uint32_t)0x00000600) /!< EndPoint TYPE /
		3108	#define USB_EP_KIND ((uint32_t)0x00000100) /!< EndPoint KIND /
		3109	#define USB_EP_CTR_TX ((uint32_t)0x00000080) /!< EndPoint Correct TRansfer TX /
		3110	#define USB_EP_DTOG_TX ((uint32_t)0x00000040) /!< EndPoint Data TOGGLE TX /
		3111	#define USB_EPTX_STAT ((uint32_t)0x00000030) /!< EndPoint TX STATus bit field /
		3112	#define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /!< EndPoint ADDRess FIELD /
		3113
		3114	/* EndPoint REGister MASK (no toggle fields) */
		3115	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
		3116	/!< EP_TYPE[1:0] EndPoint TYPE /
		3117	#define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /!< EndPoint TYPE Mask /
		3118	#define USB_EP_BULK ((uint32_t)0x00000000) /!< EndPoint BULK /
		3119	#define USB_EP_CONTROL ((uint32_t)0x00000200) /!< EndPoint CONTROL /
		3120	#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /!< EndPoint ISOCHRONOUS /
		3121	#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /!< EndPoint INTERRUPT /
		3122	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
		3123
		3124	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
		3125	/!< STAT_TX[1:0] STATus for TX transfer /
		3126	#define USB_EP_TX_DIS ((uint32_t)0x00000000) /!< EndPoint TX DISabled /
		3127	#define USB_EP_TX_STALL ((uint32_t)0x00000010) /!< EndPoint TX STALLed /
		3128	#define USB_EP_TX_NAK ((uint32_t)0x00000020) /!< EndPoint TX NAKed /
		3129	#define USB_EP_TX_VALID ((uint32_t)0x00000030) /!< EndPoint TX VALID /
		3130	#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /!< EndPoint TX Data TOGgle bit1 /
		3131	#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /!< EndPoint TX Data TOGgle bit2 /
		3132	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
		3133	/!< STAT_RX[1:0] STATus for RX transfer /
		3134	#define USB_EP_RX_DIS ((uint32_t)0x00000000) /!< EndPoint RX DISabled /
		3135	#define USB_EP_RX_STALL ((uint32_t)0x00001000) /!< EndPoint RX STALLed /
		3136	#define USB_EP_RX_NAK ((uint32_t)0x00002000) /!< EndPoint RX NAKed /
		3137	#define USB_EP_RX_VALID ((uint32_t)0x00003000) /!< EndPoint RX VALID /
		3138	#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /!< EndPoint RX Data TOGgle bit1 /
		3139	#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /!< EndPoint RX Data TOGgle bit1 /
		3140	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
		3141
		3142	/***************** Bit definition for USB_EP0R register *****************/
		3143	#define USB_EP0R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3144
		3145	#define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3146	#define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3147	#define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3148
		3149	#define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3150	#define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3151	#define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3152
		3153	#define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3154	#define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3155	#define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3156
		3157	#define USB_EP0R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3158
		3159	#define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3160	#define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3161	#define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3162
		3163	#define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3164	#define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3165
		3166	/***************** Bit definition for USB_EP1R register *****************/
		3167	#define USB_EP1R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3168
		3169	#define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3170	#define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3171	#define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3172
		3173	#define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3174	#define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3175	#define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3176
		3177	#define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3178	#define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3179	#define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3180
		3181	#define USB_EP1R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3182
		3183	#define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3184	#define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3185	#define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3186
		3187	#define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3188	#define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3189
		3190	/***************** Bit definition for USB_EP2R register *****************/
		3191	#define USB_EP2R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3192
		3193	#define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3194	#define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3195	#define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3196
		3197	#define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3198	#define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3199	#define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3200
		3201	#define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3202	#define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3203	#define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3204
		3205	#define USB_EP2R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3206
		3207	#define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3208	#define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3209	#define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3210
		3211	#define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3212	#define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3213
		3214	/***************** Bit definition for USB_EP3R register *****************/
		3215	#define USB_EP3R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3216
		3217	#define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3218	#define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3219	#define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3220
		3221	#define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3222	#define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3223	#define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3224
		3225	#define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3226	#define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3227	#define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3228
		3229	#define USB_EP3R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3230
		3231	#define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3232	#define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3233	#define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3234
		3235	#define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3236	#define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3237
		3238	/***************** Bit definition for USB_EP4R register *****************/
		3239	#define USB_EP4R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3240
		3241	#define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3242	#define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3243	#define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3244
		3245	#define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3246	#define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3247	#define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3248
		3249	#define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3250	#define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3251	#define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3252
		3253	#define USB_EP4R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3254
		3255	#define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3256	#define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3257	#define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3258
		3259	#define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3260	#define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3261
		3262	/***************** Bit definition for USB_EP5R register *****************/
		3263	#define USB_EP5R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3264
		3265	#define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3266	#define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3267	#define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3268
		3269	#define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3270	#define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3271	#define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3272
		3273	#define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3274	#define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3275	#define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3276
		3277	#define USB_EP5R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3278
		3279	#define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3280	#define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3281	#define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3282
		3283	#define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3284	#define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3285
		3286	/***************** Bit definition for USB_EP6R register *****************/
		3287	#define USB_EP6R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3288
		3289	#define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3290	#define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3291	#define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3292
		3293	#define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3294	#define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3295	#define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3296
		3297	#define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3298	#define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3299	#define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3300
		3301	#define USB_EP6R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3302
		3303	#define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3304	#define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3305	#define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3306
		3307	#define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3308	#define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3309
		3310	/***************** Bit definition for USB_EP7R register *****************/
		3311	#define USB_EP7R_EA ((uint32_t)0x0000000F) /!< Endpoint Address /
		3312
		3313	#define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		3314	#define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3315	#define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3316
		3317	#define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /!< Data Toggle, for transmission transfers /
		3318	#define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /!< Correct Transfer for transmission /
		3319	#define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /!< Endpoint Kind /
		3320
		3321	#define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /!< EP_TYPE[1:0] bits (Endpoint type) /
		3322	#define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /!< Bit 0 /
		3323	#define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /!< Bit 1 /
		3324
		3325	#define USB_EP7R_SETUP ((uint32_t)0x00000800) /!< Setup transaction completed /
		3326
		3327	#define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
		3328	#define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3329	#define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3330
		3331	#define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /!< Data Toggle, for reception transfers /
		3332	#define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /!< Correct Transfer for reception /
		3333
		3334	/!< Common registers /
		3335	/***************** Bit definition for USB_CNTR register *****************/
		3336	#define USB_CNTR_FRES ((uint32_t)0x00000001) /!< Force USB Reset /
		3337	#define USB_CNTR_PDWN ((uint32_t)0x00000002) /!< Power down /
		3338	#define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /!< Low-power mode /
		3339	#define USB_CNTR_FSUSP ((uint32_t)0x00000008) /!< Force suspend /
		3340	#define USB_CNTR_RESUME ((uint32_t)0x00000010) /!< Resume request /
		3341	#define USB_CNTR_ESOFM ((uint32_t)0x00000100) /!< Expected Start Of Frame Interrupt Mask /
		3342	#define USB_CNTR_SOFM ((uint32_t)0x00000200) /!< Start Of Frame Interrupt Mask /
		3343	#define USB_CNTR_RESETM ((uint32_t)0x00000400) /!< RESET Interrupt Mask /
		3344	#define USB_CNTR_SUSPM ((uint32_t)0x00000800) /!< Suspend mode Interrupt Mask /
		3345	#define USB_CNTR_WKUPM ((uint32_t)0x00001000) /!< Wakeup Interrupt Mask /
		3346	#define USB_CNTR_ERRM ((uint32_t)0x00002000) /!< Error Interrupt Mask /
		3347	#define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /!< Packet Memory Area Over / Underrun Interrupt Mask /
		3348	#define USB_CNTR_CTRM ((uint32_t)0x00008000) /!< Correct Transfer Interrupt Mask /
		3349
		3350	/***************** Bit definition for USB_ISTR register *****************/
		3351	#define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /!< Endpoint Identifier /
		3352	#define USB_ISTR_DIR ((uint32_t)0x00000010) /!< Direction of transaction /
		3353	#define USB_ISTR_ESOF ((uint32_t)0x00000100) /!< Expected Start Of Frame /
		3354	#define USB_ISTR_SOF ((uint32_t)0x00000200) /!< Start Of Frame /
		3355	#define USB_ISTR_RESET ((uint32_t)0x00000400) /!< USB RESET request /
		3356	#define USB_ISTR_SUSP ((uint32_t)0x00000800) /!< Suspend mode request /
		3357	#define USB_ISTR_WKUP ((uint32_t)0x00001000) /!< Wake up /
		3358	#define USB_ISTR_ERR ((uint32_t)0x00002000) /!< Error /
		3359	#define USB_ISTR_PMAOVR ((uint32_t)0x00004000) /!< Packet Memory Area Over / Underrun /
		3360	#define USB_ISTR_CTR ((uint32_t)0x00008000) /!< Correct Transfer /
		3361
		3362	/***************** Bit definition for USB_FNR register ******************/
		3363	#define USB_FNR_FN ((uint32_t)0x000007FF) /!< Frame Number /
		3364	#define USB_FNR_LSOF ((uint32_t)0x00001800) /!< Lost SOF /
		3365	#define USB_FNR_LCK ((uint32_t)0x00002000) /!< Locked /
		3366	#define USB_FNR_RXDM ((uint32_t)0x00004000) /!< Receive Data - Line Status /
		3367	#define USB_FNR_RXDP ((uint32_t)0x00008000) /!< Receive Data + Line Status /
		3368
		3369	/**************** Bit definition for USB_DADDR register *****************/
		3370	#define USB_DADDR_ADD ((uint32_t)0x0000007F) /!< ADD[6:0] bits (Device Address) /
		3371	#define USB_DADDR_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
		3372	#define USB_DADDR_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
		3373	#define USB_DADDR_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
		3374	#define USB_DADDR_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
		3375	#define USB_DADDR_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
		3376	#define USB_DADDR_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
		3377	#define USB_DADDR_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
		3378
		3379	#define USB_DADDR_EF ((uint32_t)0x00000080) /!< Enable Function /
		3380
		3381	/**************** Bit definition for USB_BTABLE register ****************/
		3382	#define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /!< Buffer Table /
		3383
		3384	/!< Buffer descriptor table /
		3385	/*************** Bit definition for USB_ADDR0_TX register ***************/
		3386	#define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 0 /
		3387
		3388	/*************** Bit definition for USB_ADDR1_TX register ***************/
		3389	#define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 1 /
		3390
		3391	/*************** Bit definition for USB_ADDR2_TX register ***************/
		3392	#define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 2 /
		3393
		3394	/*************** Bit definition for USB_ADDR3_TX register ***************/
		3395	#define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 3 /
		3396
		3397	/*************** Bit definition for USB_ADDR4_TX register ***************/
		3398	#define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 4 /
		3399
		3400	/*************** Bit definition for USB_ADDR5_TX register ***************/
		3401	#define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 5 /
		3402
		3403	/*************** Bit definition for USB_ADDR6_TX register ***************/
		3404	#define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 6 /
		3405
		3406	/*************** Bit definition for USB_ADDR7_TX register ***************/
		3407	#define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /!< Transmission Buffer Address 7 /
		3408
		3409	/----------------------------------------------------------------------------/
		3410
		3411	/*************** Bit definition for USB_COUNT0_TX register **************/
		3412	#define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 /
		3413
		3414	/*************** Bit definition for USB_COUNT1_TX register **************/
		3415	#define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 /
		3416
		3417	/*************** Bit definition for USB_COUNT2_TX register **************/
		3418	#define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 /
		3419
		3420	/*************** Bit definition for USB_COUNT3_TX register **************/
		3421	#define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 /
		3422
		3423	/*************** Bit definition for USB_COUNT4_TX register **************/
		3424	#define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 /
		3425
		3426	/*************** Bit definition for USB_COUNT5_TX register **************/
		3427	#define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 /
		3428
		3429	/*************** Bit definition for USB_COUNT6_TX register **************/
		3430	#define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 /
		3431
		3432	/*************** Bit definition for USB_COUNT7_TX register **************/
		3433	#define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 /
		3434
		3435	/----------------------------------------------------------------------------/
		3436
		3437	/************** Bit definition for USB_COUNT0_TX_0 register *************/
		3438	#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 (low) /
		3439
		3440	/************** Bit definition for USB_COUNT0_TX_1 register *************/
		3441	#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 0 (high) /
		3442
		3443	/************** Bit definition for USB_COUNT1_TX_0 register *************/
		3444	#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 (low) /
		3445
		3446	/************** Bit definition for USB_COUNT1_TX_1 register *************/
		3447	#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 1 (high) /
		3448
		3449	/************** Bit definition for USB_COUNT2_TX_0 register *************/
		3450	#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 (low) /
		3451
		3452	/************** Bit definition for USB_COUNT2_TX_1 register *************/
		3453	#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 2 (high) /
		3454
		3455	/************** Bit definition for USB_COUNT3_TX_0 register *************/
		3456	#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 3 (low) /
		3457
		3458	/************** Bit definition for USB_COUNT3_TX_1 register *************/
		3459	#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 3 (high) /
		3460
		3461	/************** Bit definition for USB_COUNT4_TX_0 register *************/
		3462	#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 (low) /
		3463
		3464	/************** Bit definition for USB_COUNT4_TX_1 register *************/
		3465	#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 4 (high) /
		3466
		3467	/************** Bit definition for USB_COUNT5_TX_0 register *************/
		3468	#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 (low) /
		3469
		3470	/************** Bit definition for USB_COUNT5_TX_1 register *************/
		3471	#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 5 (high) /
		3472
		3473	/************** Bit definition for USB_COUNT6_TX_0 register *************/
		3474	#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 (low) /
		3475
		3476	/************** Bit definition for USB_COUNT6_TX_1 register *************/
		3477	#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 6 (high) /
		3478
		3479	/************** Bit definition for USB_COUNT7_TX_0 register *************/
		3480	#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 (low) /
		3481
		3482	/************** Bit definition for USB_COUNT7_TX_1 register *************/
		3483	#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 7 (high) /
		3484
		3485	/----------------------------------------------------------------------------/
		3486
		3487	/*************** Bit definition for USB_ADDR0_RX register ***************/
		3488	#define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 0 /
		3489
		3490	/*************** Bit definition for USB_ADDR1_RX register ***************/
		3491	#define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 1 /
		3492
		3493	/*************** Bit definition for USB_ADDR2_RX register ***************/
		3494	#define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 2 /
		3495
		3496	/*************** Bit definition for USB_ADDR3_RX register ***************/
		3497	#define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 3 /
		3498
		3499	/*************** Bit definition for USB_ADDR4_RX register ***************/
		3500	#define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 4 /
		3501
		3502	/*************** Bit definition for USB_ADDR5_RX register ***************/
		3503	#define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 5 /
		3504
		3505	/*************** Bit definition for USB_ADDR6_RX register ***************/
		3506	#define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 6 /
		3507
		3508	/*************** Bit definition for USB_ADDR7_RX register ***************/
		3509	#define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /!< Reception Buffer Address 7 /
		3510
		3511	/----------------------------------------------------------------------------/
		3512
		3513	/*************** Bit definition for USB_COUNT0_RX register **************/
		3514	#define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		3515
		3516	#define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		3517	#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3518	#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3519	#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3520	#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3521	#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3522
		3523	#define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		3524
		3525	/*************** Bit definition for USB_COUNT1_RX register **************/
		3526	#define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		3527
		3528	#define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		3529	#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3530	#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3531	#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3532	#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3533	#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3534
		3535	#define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		3536
		3537	/*************** Bit definition for USB_COUNT2_RX register **************/
		3538	#define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		3539
		3540	#define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		3541	#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3542	#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3543	#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3544	#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3545	#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3546
		3547	#define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		3548
		3549	/*************** Bit definition for USB_COUNT3_RX register **************/
		3550	#define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		3551
		3552	#define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		3553	#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3554	#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3555	#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3556	#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3557	#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3558
		3559	#define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		3560
		3561	/*************** Bit definition for USB_COUNT4_RX register **************/
		3562	#define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		3563
		3564	#define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		3565	#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3566	#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3567	#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3568	#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3569	#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3570
		3571	#define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		3572
		3573	/*************** Bit definition for USB_COUNT5_RX register **************/
		3574	#define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		3575
		3576	#define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		3577	#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3578	#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3579	#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3580	#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3581	#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3582
		3583	#define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		3584
		3585	/*************** Bit definition for USB_COUNT6_RX register **************/
		3586	#define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		3587
		3588	#define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		3589	#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3590	#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3591	#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3592	#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3593	#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3594
		3595	#define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		3596
		3597	/*************** Bit definition for USB_COUNT7_RX register **************/
		3598	#define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /!< Reception Byte Count /
		3599
		3600	#define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		3601	#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3602	#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3603	#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3604	#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3605	#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3606
		3607	#define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /!< BLock SIZE /
		3608
		3609	/----------------------------------------------------------------------------/
		3610
		3611	/************** Bit definition for USB_COUNT0_RX_0 register *************/
		3612	#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		3613
		3614	#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		3615	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3616	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3617	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3618	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3619	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3620
		3621	#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		3622
		3623	/************** Bit definition for USB_COUNT0_RX_1 register *************/
		3624	#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		3625
		3626	#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		3627	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 1 /
		3628	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		3629	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		3630	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		3631	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		3632
		3633	#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		3634
		3635	/************** Bit definition for USB_COUNT1_RX_0 register *************/
		3636	#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		3637
		3638	#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		3639	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3640	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3641	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3642	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3643	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3644
		3645	#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		3646
		3647	/************** Bit definition for USB_COUNT1_RX_1 register *************/
		3648	#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		3649
		3650	#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		3651	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		3652	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		3653	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		3654	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		3655	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		3656
		3657	#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		3658
		3659	/************** Bit definition for USB_COUNT2_RX_0 register *************/
		3660	#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		3661
		3662	#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		3663	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3664	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3665	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3666	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3667	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3668
		3669	#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		3670
		3671	/************** Bit definition for USB_COUNT2_RX_1 register *************/
		3672	#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		3673
		3674	#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		3675	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		3676	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		3677	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		3678	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		3679	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		3680
		3681	#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		3682
		3683	/************** Bit definition for USB_COUNT3_RX_0 register *************/
		3684	#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		3685
		3686	#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		3687	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3688	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3689	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3690	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3691	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3692
		3693	#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		3694
		3695	/************** Bit definition for USB_COUNT3_RX_1 register *************/
		3696	#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		3697
		3698	#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		3699	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		3700	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		3701	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		3702	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		3703	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		3704
		3705	#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		3706
		3707	/************** Bit definition for USB_COUNT4_RX_0 register *************/
		3708	#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		3709
		3710	#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		3711	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3712	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3713	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3714	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3715	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3716
		3717	#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		3718
		3719	/************** Bit definition for USB_COUNT4_RX_1 register *************/
		3720	#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		3721
		3722	#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		3723	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		3724	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		3725	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		3726	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		3727	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		3728
		3729	#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		3730
		3731	/************** Bit definition for USB_COUNT5_RX_0 register *************/
		3732	#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		3733
		3734	#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		3735	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3736	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3737	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3738	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3739	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3740
		3741	#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		3742
		3743	/************** Bit definition for USB_COUNT5_RX_1 register *************/
		3744	#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		3745
		3746	#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		3747	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		3748	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		3749	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		3750	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		3751	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		3752
		3753	#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		3754
		3755	/************* Bit definition for USB_COUNT6_RX_0 register *************/
		3756	#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		3757
		3758	#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		3759	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3760	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3761	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3762	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3763	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3764
		3765	#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		3766
		3767	/************** Bit definition for USB_COUNT6_RX_1 register *************/
		3768	#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		3769
		3770	#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		3771	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		3772	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		3773	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		3774	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		3775	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		3776
		3777	#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		3778
		3779	/************* Bit definition for USB_COUNT7_RX_0 register **************/
		3780	#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
		3781
		3782	#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		3783	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
		3784	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
		3785	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
		3786	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
		3787	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
		3788
		3789	#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
		3790
		3791	/************* Bit definition for USB_COUNT7_RX_1 register **************/
		3792	#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
		3793
		3794	#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		3795	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
		3796	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
		3797	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
		3798	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
		3799	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
		3800
		3801	#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
		3802
		3803
		3804	/******************************************************************************/
		3805	/* */
		3806	/* Serial Peripheral Interface */
		3807	/* */
		3808	/******************************************************************************/
		3809
		3810	/***************** Bit definition for SPI_CR1 register ******************/
		3811	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
		3812	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
		3813	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
		3814
		3815	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
		3816	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
		3817	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
		3818	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
		3819
		3820	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
		3821	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
		3822	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
		3823	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
		3824	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
		3825	#define SPI_CR1_DFF ((uint32_t)0x00000800) /!< Data Frame Format /
		3826	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
		3827	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
		3828	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
		3829	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
		3830
		3831	/***************** Bit definition for SPI_CR2 register ******************/
		3832	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
		3833	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
		3834	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
		3835	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
		3836	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
		3837	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
		3838
		3839	/****************** Bit definition for SPI_SR register ******************/
		3840	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
		3841	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
		3842	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
		3843	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
		3844	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
		3845	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
		3846	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
		3847	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
		3848
		3849	/****************** Bit definition for SPI_DR register ******************/
		3850	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!< Data Register /
		3851
		3852	/***************** Bit definition for SPI_CRCPR register ****************/
		3853	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!< CRC polynomial register /
		3854
		3855	/**************** Bit definition for SPI_RXCRCR register ****************/
		3856	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!< Rx CRC Register /
		3857
		3858	/**************** Bit definition for SPI_TXCRCR register ****************/
		3859	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!< Tx CRC Register /
		3860
		3861	/**************** Bit definition for SPI_I2SCFGR register ***************/
		3862	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!< I2S mode selection /
		3863
		3864
		3865	/******************************************************************************/
		3866	/* */
		3867	/* Inter-integrated Circuit Interface */
		3868	/* */
		3869	/******************************************************************************/
		3870
		3871	/***************** Bit definition for I2C_CR1 register ******************/
		3872	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
		3873	#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /!< SMBus Mode /
		3874	#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /!< SMBus Type /
		3875	#define I2C_CR1_ENARP ((uint32_t)0x00000010) /!< ARP Enable /
		3876	#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /!< PEC Enable /
		3877	#define I2C_CR1_ENGC ((uint32_t)0x00000040) /!< General Call Enable /
		3878	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /!< Clock Stretching Disable (Slave mode) /
		3879	#define I2C_CR1_START ((uint32_t)0x00000100) /!< Start Generation /
		3880	#define I2C_CR1_STOP ((uint32_t)0x00000200) /!< Stop Generation /
		3881	#define I2C_CR1_ACK ((uint32_t)0x00000400) /!< Acknowledge Enable /
		3882	#define I2C_CR1_POS ((uint32_t)0x00000800) /!< Acknowledge/PEC Position (for data reception) /
		3883	#define I2C_CR1_PEC ((uint32_t)0x00001000) /!< Packet Error Checking /
		3884	#define I2C_CR1_ALERT ((uint32_t)0x00002000) /!< SMBus Alert /
		3885	#define I2C_CR1_SWRST ((uint32_t)0x00008000) /!< Software Reset /
		3886
		3887	/***************** Bit definition for I2C_CR2 register ******************/
		3888	#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
		3889	#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3890	#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3891	#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3892	#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3893	#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /!< Bit 4 /
		3894	#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /!< Bit 5 /
		3895
		3896	#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /!< Error Interrupt Enable /
		3897	#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /!< Event Interrupt Enable /
		3898	#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /!< Buffer Interrupt Enable /
		3899	#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /!< DMA Requests Enable /
		3900	#define I2C_CR2_LAST ((uint32_t)0x00001000) /!< DMA Last Transfer /
		3901
		3902	/***************** Bit definition for I2C_OAR1 register *****************/
		3903	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
		3904	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
		3905
		3906	#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
		3907	#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
		3908	#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
		3909	#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
		3910	#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
		3911	#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
		3912	#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
		3913	#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /!< Bit 7 /
		3914	#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /!< Bit 8 /
		3915	#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /!< Bit 9 /
		3916
		3917	#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /!< Addressing Mode (Slave mode) /
		3918
		3919	/***************** Bit definition for I2C_OAR2 register *****************/
		3920	#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /!< Dual addressing mode enable /
		3921	#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /!< Interface address /
		3922
		3923	/***************** Bit definition for I2C_SR1 register ******************/
		3924	#define I2C_SR1_SB ((uint32_t)0x00000001) /!< Start Bit (Master mode) /
		3925	#define I2C_SR1_ADDR ((uint32_t)0x00000002) /!< Address sent (master mode)/matched (slave mode) /
		3926	#define I2C_SR1_BTF ((uint32_t)0x00000004) /!< Byte Transfer Finished /
		3927	#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /!< 10-bit header sent (Master mode) /
		3928	#define I2C_SR1_STOPF ((uint32_t)0x00000010) /!< Stop detection (Slave mode) /
		3929	#define I2C_SR1_RXNE ((uint32_t)0x00000040) /!< Data Register not Empty (receivers) /
		3930	#define I2C_SR1_TXE ((uint32_t)0x00000080) /!< Data Register Empty (transmitters) /
		3931	#define I2C_SR1_BERR ((uint32_t)0x00000100) /!< Bus Error /
		3932	#define I2C_SR1_ARLO ((uint32_t)0x00000200) /!< Arbitration Lost (master mode) /
		3933	#define I2C_SR1_AF ((uint32_t)0x00000400) /!< Acknowledge Failure /
		3934	#define I2C_SR1_OVR ((uint32_t)0x00000800) /!< Overrun/Underrun /
		3935	#define I2C_SR1_PECERR ((uint32_t)0x00001000) /!< PEC Error in reception /
		3936	#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /!< Timeout or Tlow Error /
		3937	#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /!< SMBus Alert /
		3938
		3939	/***************** Bit definition for I2C_SR2 register ******************/
		3940	#define I2C_SR2_MSL ((uint32_t)0x00000001) /!< Master/Slave /
		3941	#define I2C_SR2_BUSY ((uint32_t)0x00000002) /!< Bus Busy /
		3942	#define I2C_SR2_TRA ((uint32_t)0x00000004) /!< Transmitter/Receiver /
		3943	#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /!< General Call Address (Slave mode) /
		3944	#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /!< SMBus Device Default Address (Slave mode) /
		3945	#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /!< SMBus Host Header (Slave mode) /
		3946	#define I2C_SR2_DUALF ((uint32_t)0x00000080) /!< Dual Flag (Slave mode) /
		3947	#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /!< Packet Error Checking Register /
		3948
		3949	/***************** Bit definition for I2C_CCR register ******************/
		3950	#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
		3951	#define I2C_CCR_DUTY ((uint32_t)0x00004000) /!< Fast Mode Duty Cycle /
		3952	#define I2C_CCR_FS ((uint32_t)0x00008000) /!< I2C Master Mode Selection /
		3953
		3954	/**************** Bit definition for I2C_TRISE register *****************/
		3955	#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
		3956
		3957	/******************************************************************************/
		3958	/* */
		3959	/* Universal Synchronous Asynchronous Receiver Transmitter */
		3960	/* */
		3961	/******************************************************************************/
		3962
		3963	/***************** Bit definition for USART_SR register *****************/
		3964	#define USART_SR_PE ((uint32_t)0x00000001) /!< Parity Error /
		3965	#define USART_SR_FE ((uint32_t)0x00000002) /!< Framing Error /
		3966	#define USART_SR_NE ((uint32_t)0x00000004) /!< Noise Error Flag /
		3967	#define USART_SR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
		3968	#define USART_SR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
		3969	#define USART_SR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
		3970	#define USART_SR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
		3971	#define USART_SR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
		3972	#define USART_SR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
		3973	#define USART_SR_CTS ((uint32_t)0x00000200) /!< CTS Flag /
		3974
		3975	/***************** Bit definition for USART_DR register *****************/
		3976	#define USART_DR_DR ((uint32_t)0x000001FF) /!< Data value /
		3977
		3978	/**************** Bit definition for USART_BRR register *****************/
		3979	#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
		3980	#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
		3981
		3982	/**************** Bit definition for USART_CR1 register *****************/
		3983	#define USART_CR1_SBK ((uint32_t)0x00000001) /!< Send Break /
		3984	#define USART_CR1_RWU ((uint32_t)0x00000002) /!< Receiver wakeup /
		3985	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
		3986	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
		3987	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
		3988	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
		3989	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
		3990	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< PE Interrupt Enable /
		3991	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
		3992	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
		3993	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
		3994	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Wakeup method /
		3995	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
		3996	#define USART_CR1_UE ((uint32_t)0x00002000) /!< USART Enable /
		3997
		3998	/**************** Bit definition for USART_CR2 register *****************/
		3999	#define USART_CR2_ADD ((uint32_t)0x0000000F) /!< Address of the USART node /
		4000	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
		4001	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
		4002	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
		4003	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
		4004	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
		4005	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
		4006
		4007	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
		4008	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
		4009	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
		4010
		4011	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
		4012
		4013	/**************** Bit definition for USART_CR3 register *****************/
		4014	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
		4015	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
		4016	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
		4017	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
		4018	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< Smartcard NACK enable /
		4019	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Smartcard mode enable /
		4020	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
		4021	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
		4022	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
		4023	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
		4024	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
		4025
		4026	/**************** Bit definition for USART_GTPR register ****************/
		4027	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
		4028	#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /!< Bit 0 /
		4029	#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /!< Bit 1 /
		4030	#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /!< Bit 2 /
		4031	#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /!< Bit 3 /
		4032	#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /!< Bit 4 /
		4033	#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /!< Bit 5 /
		4034	#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /!< Bit 6 /
		4035	#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /!< Bit 7 /
		4036
		4037	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< Guard time value /
		4038
		4039	/******************************************************************************/
		4040	/* */
		4041	/* Debug MCU */
		4042	/* */
		4043	/******************************************************************************/
		4044
		4045	/************** Bit definition for DBGMCU_IDCODE register ***************/
		4046	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
		4047
		4048	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
		4049	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
		4050	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
		4051	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
		4052	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
		4053	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
		4054	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
		4055	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
		4056	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
		4057	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
		4058	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
		4059	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
		4060	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
		4061	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
		4062	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
		4063	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
		4064	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
		4065
		4066	/**************** Bit definition for DBGMCU_CR register *****************/
		4067	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
		4068	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
		4069	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
		4070	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
		4071
		4072	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
		4073	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
		4074	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
		4075
		4076	#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /!< Debug Independent Watchdog stopped when Core is halted /
		4077	#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /!< Debug Window Watchdog stopped when Core is halted /
		4078	#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /!< TIM2 counter stopped when core is halted /
		4079	#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /!< TIM3 counter stopped when core is halted /
		4080	#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /!< TIM4 counter stopped when core is halted /
		4081	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /!< SMBUS timeout mode stopped when Core is halted /
		4082	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /!< SMBUS timeout mode stopped when Core is halted /
		4083
		4084	/******************************************************************************/
		4085	/* */
		4086	/* FLASH and Option Bytes Registers */
		4087	/* */
		4088	/******************************************************************************/
		4089	/***************** Bit definition for FLASH_ACR register ****************/
		4090	#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /!< LATENCY[2:0] bits (Latency) /
		4091	#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /!< Bit 0 /
		4092	#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /!< Bit 1 /
		4093	#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /!< Bit 2 /
		4094
		4095	#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /!< Flash Half Cycle Access Enable /
		4096	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
		4097	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
		4098
		4099	/**************** Bit definition for FLASH_KEYR register ****************/
		4100	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
		4101
		4102	#define RDP_KEY ((uint32_t)0x000000A5) /!< RDP Key /
		4103	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< FPEC Key1 /
		4104	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /!< FPEC Key2 /
		4105
		4106	/*************** Bit definition for FLASH_OPTKEYR register **************/
		4107	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
		4108
		4109	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
		4110	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
		4111
		4112	/**************** Bit definition for FLASH_SR register ******************/
		4113	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
		4114	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
		4115	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
		4116	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
		4117
		4118	/***************** Bit definition for FLASH_CR register *****************/
		4119	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
		4120	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
		4121	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
		4122	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
		4123	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
		4124	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
		4125	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
		4126	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
		4127	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
		4128	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
		4129
		4130	/***************** Bit definition for FLASH_AR register *****************/
		4131	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
		4132
		4133	/**************** Bit definition for FLASH_OBR register *****************/
		4134	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
		4135	#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /!< Read protection /
		4136
		4137	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /!< IWDG SW /
		4138	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /!< nRST_STOP /
		4139	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /!< nRST_STDBY /
		4140	#define FLASH_OBR_USER ((uint32_t)0x0000001C) /!< User Option Bytes /
		4141
		4142	/**************** Bit definition for FLASH_WRPR register ****************/
		4143	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
		4144
		4145	/----------------------------------------------------------------------------/
		4146
		4147	/**************** Bit definition for FLASH_RDP register *****************/
		4148	#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
		4149	#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
		4150
		4151	/**************** Bit definition for FLASH_USER register ****************/
		4152	#define FLASH_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
		4153	#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
		4154
		4155	/**************** Bit definition for FLASH_Data0 register ***************/
		4156	#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /!< User data storage option byte /
		4157	#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /!< User data storage complemented option byte /
		4158
		4159	/**************** Bit definition for FLASH_Data1 register ***************/
		4160	#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /!< User data storage option byte /
		4161	#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /!< User data storage complemented option byte /
		4162
		4163	/**************** Bit definition for FLASH_WRP0 register ****************/
		4164	#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
		4165	#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
		4166
		4167	/**************** Bit definition for FLASH_WRP1 register ****************/
		4168	#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
		4169	#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
		4170
		4171	/**************** Bit definition for FLASH_WRP2 register ****************/
		4172	#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
		4173	#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
		4174
		4175	/**************** Bit definition for FLASH_WRP3 register ****************/
		4176	#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
		4177	#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
		4178
		4179
		4180
		4181	/**
		4182	* @}
		4183	*/
		4184
		4185	/**
		4186	* @}
		4187	*/
		4188
		4189	/** @addtogroup Exported_macro
		4190	* @{
		4191	*/
		4192
		4193	/**************************** ADC Instances *******************************/
		4194	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
		4195
		4196	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		4197
		4198	/**************************** CRC Instances *******************************/
		4199	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		4200
		4201	/**************************** DAC Instances *******************************/
		4202
		4203	/**************************** DMA Instances *******************************/
		4204	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		4205	((INSTANCE) == DMA1_Channel2) \|\| \
		4206	((INSTANCE) == DMA1_Channel3) \|\| \
		4207	((INSTANCE) == DMA1_Channel4) \|\| \
		4208	((INSTANCE) == DMA1_Channel5) \|\| \
		4209	((INSTANCE) == DMA1_Channel6) \|\| \
		4210	((INSTANCE) == DMA1_Channel7))
		4211
		4212	/***************************** GPIO Instances *****************************/
		4213	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		4214	((INSTANCE) == GPIOB) \|\| \
		4215	((INSTANCE) == GPIOC) \|\| \
		4216	((INSTANCE) == GPIOD))
		4217
		4218	/************************** GPIO Alternate Function Instances *************/
		4219	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		4220
		4221	/************************** GPIO Lock Instances ***************************/
		4222	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		4223
		4224	/****************************** I2C Instances *****************************/
		4225	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		4226	((INSTANCE) == I2C2))
		4227
		4228	/**************************** IWDG Instances ******************************/
		4229	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		4230
		4231	/****************************** SPI Instances *****************************/
		4232	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		4233	((INSTANCE) == SPI2))
		4234
		4235	/**************************** START TIM Instances *************************/
		4236	/**************************** TIM Instances *******************************/
		4237	#define IS_TIM_INSTANCE(INSTANCE)\
		4238	(((INSTANCE) == TIM2) \|\| \
		4239	((INSTANCE) == TIM3) \|\| \
		4240	((INSTANCE) == TIM4))
		4241
		4242	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
		4243	(((INSTANCE) == TIM2) \|\| \
		4244	((INSTANCE) == TIM3) \|\| \
		4245	((INSTANCE) == TIM4))
		4246
		4247	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
		4248	(((INSTANCE) == TIM2) \|\| \
		4249	((INSTANCE) == TIM3) \|\| \
		4250	((INSTANCE) == TIM4))
		4251
		4252	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
		4253	(((INSTANCE) == TIM2) \|\| \
		4254	((INSTANCE) == TIM3) \|\| \
		4255	((INSTANCE) == TIM4))
		4256
		4257	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
		4258	(((INSTANCE) == TIM2) \|\| \
		4259	((INSTANCE) == TIM3) \|\| \
		4260	((INSTANCE) == TIM4))
		4261
		4262	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
		4263	(((INSTANCE) == TIM2) \|\| \
		4264	((INSTANCE) == TIM3) \|\| \
		4265	((INSTANCE) == TIM4))
		4266
		4267	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
		4268	(((INSTANCE) == TIM2) \|\| \
		4269	((INSTANCE) == TIM3) \|\| \
		4270	((INSTANCE) == TIM4))
		4271
		4272	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
		4273	(((INSTANCE) == TIM2) \|\| \
		4274	((INSTANCE) == TIM3) \|\| \
		4275	((INSTANCE) == TIM4))
		4276
		4277	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
		4278	(((INSTANCE) == TIM2) \|\| \
		4279	((INSTANCE) == TIM3) \|\| \
		4280	((INSTANCE) == TIM4))
		4281
		4282	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
		4283	(((INSTANCE) == TIM2) \|\| \
		4284	((INSTANCE) == TIM3) \|\| \
		4285	((INSTANCE) == TIM4))
		4286
		4287	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
		4288	(((INSTANCE) == TIM2) \|\| \
		4289	((INSTANCE) == TIM3) \|\| \
		4290	((INSTANCE) == TIM4))
		4291
		4292	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
		4293	(((INSTANCE) == TIM2) \|\| \
		4294	((INSTANCE) == TIM3) \|\| \
		4295	((INSTANCE) == TIM4))
		4296
		4297	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
		4298	(((INSTANCE) == TIM2) \|\| \
		4299	((INSTANCE) == TIM3) \|\| \
		4300	((INSTANCE) == TIM4))
		4301
		4302	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
		4303	(((INSTANCE) == TIM2) \|\| \
		4304	((INSTANCE) == TIM3) \|\| \
		4305	((INSTANCE) == TIM4))
		4306
		4307	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
		4308	(((INSTANCE) == TIM2) \|\| \
		4309	((INSTANCE) == TIM3) \|\| \
		4310	((INSTANCE) == TIM4))
		4311
		4312	#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
		4313
		4314	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		4315	((((INSTANCE) == TIM2) && \
		4316	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4317	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		4318	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		4319	((CHANNEL) == TIM_CHANNEL_4))) \
		4320	\|\| \
		4321	(((INSTANCE) == TIM3) && \
		4322	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4323	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		4324	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		4325	((CHANNEL) == TIM_CHANNEL_4))) \
		4326	\|\| \
		4327	(((INSTANCE) == TIM4) && \
		4328	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4329	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		4330	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		4331	((CHANNEL) == TIM_CHANNEL_4))))
		4332
		4333	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
		4334
		4335	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
		4336	(((INSTANCE) == TIM2) \|\| \
		4337	((INSTANCE) == TIM3) \|\| \
		4338	((INSTANCE) == TIM4))
		4339
		4340	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
		4341
		4342	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
		4343	(((INSTANCE) == TIM2) \|\| \
		4344	((INSTANCE) == TIM3) \|\| \
		4345	((INSTANCE) == TIM4))
		4346
		4347	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
		4348	(((INSTANCE) == TIM2) \|\| \
		4349	((INSTANCE) == TIM3) \|\| \
		4350	((INSTANCE) == TIM4))
		4351
		4352	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
		4353	(((INSTANCE) == TIM2) \|\| \
		4354	((INSTANCE) == TIM3) \|\| \
		4355	((INSTANCE) == TIM4))
		4356
		4357	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
		4358
		4359	/**************************** END TIM Instances ***************************/
		4360
		4361
		4362	/****************** USART Instances : Synchronous mode ********************/
		4363	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4364	((INSTANCE) == USART2) \|\| \
		4365	((INSTANCE) == USART3))
		4366
		4367	/****************** UART Instances : Asynchronous mode ********************/
		4368	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4369	((INSTANCE) == USART2) \|\| \
		4370	((INSTANCE) == USART3))
		4371
		4372	/****************** UART Instances : Half-Duplex mode ********************/
		4373	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4374	((INSTANCE) == USART2) \|\| \
		4375	((INSTANCE) == USART3))
		4376
		4377	/****************** UART Instances : LIN mode ********************/
		4378	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4379	((INSTANCE) == USART2) \|\| \
		4380	((INSTANCE) == USART3))
		4381
		4382	/**************** UART Instances : Hardware Flow control ******************/
		4383	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4384	((INSTANCE) == USART2) \|\| \
		4385	((INSTANCE) == USART3))
		4386
		4387	/******************* UART Instances : Smard card mode *********************/
		4388	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4389	((INSTANCE) == USART2) \|\| \
		4390	((INSTANCE) == USART3))
		4391
		4392	/********************* UART Instances : IRDA mode *************************/
		4393	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4394	((INSTANCE) == USART2) \|\| \
		4395	((INSTANCE) == USART3))
		4396
		4397	/*************** UART Instances : Multi-Processor mode ********************/
		4398	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4399	((INSTANCE) == USART2) \|\| \
		4400	((INSTANCE) == USART3))
		4401
		4402	/*************** UART Instances : DMA mode available ********************/
		4403	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4404	((INSTANCE) == USART2) \|\| \
		4405	((INSTANCE) == USART3))
		4406
		4407	/**************************** RTC Instances *******************************/
		4408	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		4409
		4410	/************************** WWDG Instances ***************************/
		4411	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		4412
		4413	/**************************** USB Instances ******************************/
		4414	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
		4415
		4416
		4417
		4418
		4419	/**
		4420	* @}
		4421	*/
		4422	/******************************************************************************/
		4423	/* For a painless codes migration between the STM32F1xx device product */
		4424	/* lines, the aliases defined below are put in place to overcome the */
		4425	/* differences in the interrupt handlers and IRQn definitions. */
		4426	/* No need to update developed interrupt code when moving across */
		4427	/* product lines within the same STM32F1 Family */
		4428	/******************************************************************************/
		4429
		4430	/* Aliases for __IRQn */
		4431	#define ADC1_2_IRQn ADC1_IRQn
		4432	#define CEC_IRQn USBWakeUp_IRQn
		4433	#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
		4434	#define USB_HP_CAN1_TX_IRQn USB_HP_IRQn
		4435	#define CAN1_TX_IRQn USB_HP_IRQn
		4436	#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn
		4437	#define CAN1_RX0_IRQn USB_LP_IRQn
		4438
		4439
		4440	/* Aliases for __IRQHandler */
		4441	#define ADC1_2_IRQHandler ADC1_IRQHandler
		4442	#define CEC_IRQHandler USBWakeUp_IRQHandler
		4443	#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
		4444	#define USB_HP_CAN1_TX_IRQHandler USB_HP_IRQHandler
		4445	#define CAN1_TX_IRQHandler USB_HP_IRQHandler
		4446	#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler
		4447	#define CAN1_RX0_IRQHandler USB_LP_IRQHandler
		4448
		4449
		4450	/**
		4451	* @}
		4452	*/
		4453
		4454	/**
		4455	* @}
		4456	*/
		4457
		4458
		4459	#ifdef __cplusplus
		4460	}
		4461	#endif /* __cplusplus */
		4462
		4463	#endif /* __STM32F102xB_H */
		4464
		4465
		4466
		4467	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102xb.h – Rev 2