WebSVN – AFRtranscoder – Blame – /trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f101xe.h
		4	* @author MCD Application Team
		5	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		6	* This file contains all the peripheral register's definitions, bits
		7	* definitions and memory mapping for STM32F1xx devices.
		8	*
		9	* This file contains:
		10	* - Data structures and the address mapping for all peripherals
		11	* - Peripheral's registers declarations and bits definition
		12	* - Macros to access peripheral's registers hardware
		13	*
		14	******************************************************************************
		15	* @attention
		16	*
		17	* Copyright (c) 2017-2021 STMicroelectronics.
		18	* All rights reserved.
		19	*
		20	* This software is licensed under terms that can be found in the LICENSE file
		21	* in the root directory of this software component.
		22	* If no LICENSE file comes with this software, it is provided AS-IS.
		23	*
		24	******************************************************************************
		25	*/
		26
		27
		28	/** @addtogroup CMSIS
		29	* @{
		30	*/
		31
		32	/** @addtogroup stm32f101xe
		33	* @{
		34	*/
		35
		36	#ifndef __STM32F101xE_H
		37	#define __STM32F101xE_H
		38
		39	#ifdef __cplusplus
		40	extern "C" {
		41	#endif
		42
		43	/** @addtogroup Configuration_section_for_CMSIS
		44	* @{
		45	*/
		46	/**
		47	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		48	*/
		49	#define __CM3_REV 0x0200U /!< Core Revision r2p0 /
		50	#define __MPU_PRESENT 0U /!< Other STM32 devices does not provide an MPU /
		51	#define __NVIC_PRIO_BITS 4U /!< STM32 uses 4 Bits for the Priority Levels /
		52	#define __Vendor_SysTickConfig 0U /!< Set to 1 if different SysTick Config is used /
		53
		54	/**
		55	* @}
		56	*/
		57
		58	/** @addtogroup Peripheral_interrupt_number_definition
		59	* @{
		60	*/
		61
		62	/**
		63	* @brief STM32F10x Interrupt Number Definition, according to the selected device
		64	* in @ref Library_configuration_section
		65	*/
		66
		67	/!< Interrupt Number Definition /
		68	typedef enum
		69	{
		70	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
		71	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
		72	HardFault_IRQn = -13, /!< 3 Cortex-M3 Hard Fault Interrupt /
		73	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		74	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		75	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		76	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		77	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		78	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		79	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		80
		81	/**** STM32 specific Interrupt Numbers *******************************************************/
		82	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		83	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		84	TAMPER_IRQn = 2, /!< Tamper Interrupt /
		85	RTC_IRQn = 3, /!< RTC global Interrupt /
		86	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		87	RCC_IRQn = 5, /!< RCC global Interrupt /
		88	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		89	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		90	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		91	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		92	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		93	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		94	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		95	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		96	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		97	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		98	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		99	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		100	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
		101	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		102	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		103	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		104	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		105	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		106	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		107	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		108	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		109	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		110	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		111	USART1_IRQn = 37, /!< USART1 global Interrupt /
		112	USART2_IRQn = 38, /!< USART2 global Interrupt /
		113	USART3_IRQn = 39, /!< USART3 global Interrupt /
		114	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		115	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		116	FSMC_IRQn = 48, /!< FSMC global Interrupt /
		117	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
		118	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
		119	UART4_IRQn = 52, /!< UART4 global Interrupt /
		120	UART5_IRQn = 53, /!< UART5 global Interrupt /
		121	TIM6_IRQn = 54, /!< TIM6 global Interrupt /
		122	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
		123	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
		124	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
		125	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
		126	DMA2_Channel4_5_IRQn = 59, /!< DMA2 Channel 4 and Channel 5 global Interrupt /
		127	} IRQn_Type;
		128
		129	/**
		130	* @}
		131	*/
		132
		133	#include "core_cm3.h"
		134	#include "system_stm32f1xx.h"
		135	#include <stdint.h>
		136
		137	/** @addtogroup Peripheral_registers_structures
		138	* @{
		139	*/
		140
		141	/**
		142	* @brief Analog to Digital Converter
		143	*/
		144
		145	typedef struct
		146	{
		147	__IO uint32_t SR;
		148	__IO uint32_t CR1;
		149	__IO uint32_t CR2;
		150	__IO uint32_t SMPR1;
		151	__IO uint32_t SMPR2;
		152	__IO uint32_t JOFR1;
		153	__IO uint32_t JOFR2;
		154	__IO uint32_t JOFR3;
		155	__IO uint32_t JOFR4;
		156	__IO uint32_t HTR;
		157	__IO uint32_t LTR;
		158	__IO uint32_t SQR1;
		159	__IO uint32_t SQR2;
		160	__IO uint32_t SQR3;
		161	__IO uint32_t JSQR;
		162	__IO uint32_t JDR1;
		163	__IO uint32_t JDR2;
		164	__IO uint32_t JDR3;
		165	__IO uint32_t JDR4;
		166	__IO uint32_t DR;
		167	} ADC_TypeDef;
		168
		169	typedef struct
		170	{
		171	__IO uint32_t SR; /!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address /
		172	__IO uint32_t CR1; /!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 /
		173	__IO uint32_t CR2; /!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 /
		174	uint32_t RESERVED[16];
		175	__IO uint32_t DR; /!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C /
		176	} ADC_Common_TypeDef;
		177
		178	/**
		179	* @brief Backup Registers
		180	*/
		181
		182	typedef struct
		183	{
		184	uint32_t RESERVED0;
		185	__IO uint32_t DR1;
		186	__IO uint32_t DR2;
		187	__IO uint32_t DR3;
		188	__IO uint32_t DR4;
		189	__IO uint32_t DR5;
		190	__IO uint32_t DR6;
		191	__IO uint32_t DR7;
		192	__IO uint32_t DR8;
		193	__IO uint32_t DR9;
		194	__IO uint32_t DR10;
		195	__IO uint32_t RTCCR;
		196	__IO uint32_t CR;
		197	__IO uint32_t CSR;
		198	uint32_t RESERVED13[2];
		199	__IO uint32_t DR11;
		200	__IO uint32_t DR12;
		201	__IO uint32_t DR13;
		202	__IO uint32_t DR14;
		203	__IO uint32_t DR15;
		204	__IO uint32_t DR16;
		205	__IO uint32_t DR17;
		206	__IO uint32_t DR18;
		207	__IO uint32_t DR19;
		208	__IO uint32_t DR20;
		209	__IO uint32_t DR21;
		210	__IO uint32_t DR22;
		211	__IO uint32_t DR23;
		212	__IO uint32_t DR24;
		213	__IO uint32_t DR25;
		214	__IO uint32_t DR26;
		215	__IO uint32_t DR27;
		216	__IO uint32_t DR28;
		217	__IO uint32_t DR29;
		218	__IO uint32_t DR30;
		219	__IO uint32_t DR31;
		220	__IO uint32_t DR32;
		221	__IO uint32_t DR33;
		222	__IO uint32_t DR34;
		223	__IO uint32_t DR35;
		224	__IO uint32_t DR36;
		225	__IO uint32_t DR37;
		226	__IO uint32_t DR38;
		227	__IO uint32_t DR39;
		228	__IO uint32_t DR40;
		229	__IO uint32_t DR41;
		230	__IO uint32_t DR42;
		231	} BKP_TypeDef;
		232
		233
		234	/**
		235	* @brief CRC calculation unit
		236	*/
		237
		238	typedef struct
		239	{
		240	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		241	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		242	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		243	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		244	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		245	} CRC_TypeDef;
		246
		247	/**
		248	* @brief Digital to Analog Converter
		249	*/
		250
		251	typedef struct
		252	{
		253	__IO uint32_t CR;
		254	__IO uint32_t SWTRIGR;
		255	__IO uint32_t DHR12R1;
		256	__IO uint32_t DHR12L1;
		257	__IO uint32_t DHR8R1;
		258	__IO uint32_t DHR12R2;
		259	__IO uint32_t DHR12L2;
		260	__IO uint32_t DHR8R2;
		261	__IO uint32_t DHR12RD;
		262	__IO uint32_t DHR12LD;
		263	__IO uint32_t DHR8RD;
		264	__IO uint32_t DOR1;
		265	__IO uint32_t DOR2;
		266	} DAC_TypeDef;
		267
		268	/**
		269	* @brief Debug MCU
		270	*/
		271
		272	typedef struct
		273	{
		274	__IO uint32_t IDCODE;
		275	__IO uint32_t CR;
		276	}DBGMCU_TypeDef;
		277
		278	/**
		279	* @brief DMA Controller
		280	*/
		281
		282	typedef struct
		283	{
		284	__IO uint32_t CCR;
		285	__IO uint32_t CNDTR;
		286	__IO uint32_t CPAR;
		287	__IO uint32_t CMAR;
		288	} DMA_Channel_TypeDef;
		289
		290	typedef struct
		291	{
		292	__IO uint32_t ISR;
		293	__IO uint32_t IFCR;
		294	} DMA_TypeDef;
		295
		296
		297
		298	/**
		299	* @brief External Interrupt/Event Controller
		300	*/
		301
		302	typedef struct
		303	{
		304	__IO uint32_t IMR;
		305	__IO uint32_t EMR;
		306	__IO uint32_t RTSR;
		307	__IO uint32_t FTSR;
		308	__IO uint32_t SWIER;
		309	__IO uint32_t PR;
		310	} EXTI_TypeDef;
		311
		312	/**
		313	* @brief FLASH Registers
		314	*/
		315
		316	typedef struct
		317	{
		318	__IO uint32_t ACR;
		319	__IO uint32_t KEYR;
		320	__IO uint32_t OPTKEYR;
		321	__IO uint32_t SR;
		322	__IO uint32_t CR;
		323	__IO uint32_t AR;
		324	__IO uint32_t RESERVED;
		325	__IO uint32_t OBR;
		326	__IO uint32_t WRPR;
		327	} FLASH_TypeDef;
		328
		329	/**
		330	* @brief Option Bytes Registers
		331	*/
		332
		333	typedef struct
		334	{
		335	__IO uint16_t RDP;
		336	__IO uint16_t USER;
		337	__IO uint16_t Data0;
		338	__IO uint16_t Data1;
		339	__IO uint16_t WRP0;
		340	__IO uint16_t WRP1;
		341	__IO uint16_t WRP2;
		342	__IO uint16_t WRP3;
		343	} OB_TypeDef;
		344
		345	/**
		346	* @brief Flexible Static Memory Controller
		347	*/
		348
		349	typedef struct
		350	{
		351	__IO uint32_t BTCR[8];
		352	} FSMC_Bank1_TypeDef;
		353
		354	/**
		355	* @brief Flexible Static Memory Controller Bank1E
		356	*/
		357
		358	typedef struct
		359	{
		360	__IO uint32_t BWTR[7];
		361	} FSMC_Bank1E_TypeDef;
		362
		363	/**
		364	* @brief Flexible Static Memory Controller Bank2
		365	*/
		366
		367	typedef struct
		368	{
		369	__IO uint32_t PCR2; /!< NAND Flash control register 2, Address offset: 0x60 /
		370	__IO uint32_t SR2; /!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 /
		371	__IO uint32_t PMEM2; /!< NAND Flash Common memory space timing register 2, Address offset: 0x68 /
		372	__IO uint32_t PATT2; /!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C /
		373	uint32_t RESERVED0; /!< Reserved, 0x70 /
		374	__IO uint32_t ECCR2; /!< NAND Flash ECC result registers 2, Address offset: 0x74 /
		375	uint32_t RESERVED1; /!< Reserved, 0x78 /
		376	uint32_t RESERVED2; /!< Reserved, 0x7C /
		377	__IO uint32_t PCR3; /!< NAND Flash control register 3, Address offset: 0x80 /
		378	__IO uint32_t SR3; /!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 /
		379	__IO uint32_t PMEM3; /!< NAND Flash Common memory space timing register 3, Address offset: 0x88 /
		380	__IO uint32_t PATT3; /!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C /
		381	uint32_t RESERVED3; /!< Reserved, 0x90 /
		382	__IO uint32_t ECCR3; /!< NAND Flash ECC result registers 3, Address offset: 0x94 /
		383	} FSMC_Bank2_3_TypeDef;
		384
		385	/**
		386	* @brief Flexible Static Memory Controller Bank4
		387	*/
		388
		389	typedef struct
		390	{
		391	__IO uint32_t PCR4;
		392	__IO uint32_t SR4;
		393	__IO uint32_t PMEM4;
		394	__IO uint32_t PATT4;
		395	__IO uint32_t PIO4;
		396	} FSMC_Bank4_TypeDef;
		397
		398	/**
		399	* @brief General Purpose I/O
		400	*/
		401
		402	typedef struct
		403	{
		404	__IO uint32_t CRL;
		405	__IO uint32_t CRH;
		406	__IO uint32_t IDR;
		407	__IO uint32_t ODR;
		408	__IO uint32_t BSRR;
		409	__IO uint32_t BRR;
		410	__IO uint32_t LCKR;
		411	} GPIO_TypeDef;
		412
		413	/**
		414	* @brief Alternate Function I/O
		415	*/
		416
		417	typedef struct
		418	{
		419	__IO uint32_t EVCR;
		420	__IO uint32_t MAPR;
		421	__IO uint32_t EXTICR[4];
		422	uint32_t RESERVED0;
		423	__IO uint32_t MAPR2;
		424	} AFIO_TypeDef;
		425	/**
		426	* @brief Inter Integrated Circuit Interface
		427	*/
		428
		429	typedef struct
		430	{
		431	__IO uint32_t CR1;
		432	__IO uint32_t CR2;
		433	__IO uint32_t OAR1;
		434	__IO uint32_t OAR2;
		435	__IO uint32_t DR;
		436	__IO uint32_t SR1;
		437	__IO uint32_t SR2;
		438	__IO uint32_t CCR;
		439	__IO uint32_t TRISE;
		440	} I2C_TypeDef;
		441
		442	/**
		443	* @brief Independent WATCHDOG
		444	*/
		445
		446	typedef struct
		447	{
		448	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		449	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		450	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		451	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		452	} IWDG_TypeDef;
		453
		454	/**
		455	* @brief Power Control
		456	*/
		457
		458	typedef struct
		459	{
		460	__IO uint32_t CR;
		461	__IO uint32_t CSR;
		462	} PWR_TypeDef;
		463
		464	/**
		465	* @brief Reset and Clock Control
		466	*/
		467
		468	typedef struct
		469	{
		470	__IO uint32_t CR;
		471	__IO uint32_t CFGR;
		472	__IO uint32_t CIR;
		473	__IO uint32_t APB2RSTR;
		474	__IO uint32_t APB1RSTR;
		475	__IO uint32_t AHBENR;
		476	__IO uint32_t APB2ENR;
		477	__IO uint32_t APB1ENR;
		478	__IO uint32_t BDCR;
		479	__IO uint32_t CSR;
		480
		481
		482	} RCC_TypeDef;
		483
		484	/**
		485	* @brief Real-Time Clock
		486	*/
		487
		488	typedef struct
		489	{
		490	__IO uint32_t CRH;
		491	__IO uint32_t CRL;
		492	__IO uint32_t PRLH;
		493	__IO uint32_t PRLL;
		494	__IO uint32_t DIVH;
		495	__IO uint32_t DIVL;
		496	__IO uint32_t CNTH;
		497	__IO uint32_t CNTL;
		498	__IO uint32_t ALRH;
		499	__IO uint32_t ALRL;
		500	} RTC_TypeDef;
		501
		502	/**
		503	* @brief Serial Peripheral Interface
		504	*/
		505
		506	typedef struct
		507	{
		508	__IO uint32_t CR1;
		509	__IO uint32_t CR2;
		510	__IO uint32_t SR;
		511	__IO uint32_t DR;
		512	__IO uint32_t CRCPR;
		513	__IO uint32_t RXCRCR;
		514	__IO uint32_t TXCRCR;
		515	__IO uint32_t I2SCFGR;
		516	__IO uint32_t I2SPR;
		517	} SPI_TypeDef;
		518
		519	/**
		520	* @brief TIM Timers
		521	*/
		522	typedef struct
		523	{
		524	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		525	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		526	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		527	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		528	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		529	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		530	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		531	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		532	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		533	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		534	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		535	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		536	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
		537	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		538	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		539	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		540	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		541	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
		542	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		543	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
		544	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		545	}TIM_TypeDef;
		546
		547
		548	/**
		549	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		550	*/
		551
		552	typedef struct
		553	{
		554	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		555	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		556	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		557	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		558	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		559	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		560	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		561	} USART_TypeDef;
		562
		563
		564
		565	/**
		566	* @brief Window WATCHDOG
		567	*/
		568
		569	typedef struct
		570	{
		571	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		572	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		573	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		574	} WWDG_TypeDef;
		575
		576	/**
		577	* @}
		578	*/
		579
		580	/** @addtogroup Peripheral_memory_map
		581	* @{
		582	*/
		583
		584
		585	#define FLASH_BASE 0x08000000UL /!< FLASH base address in the alias region /
		586	#define FLASH_BANK1_END 0x0807FFFFUL /!< FLASH END address of bank1 /
		587	#define SRAM_BASE 0x20000000UL /!< SRAM base address in the alias region /
		588	#define PERIPH_BASE 0x40000000UL /!< Peripheral base address in the alias region /
		589
		590	#define SRAM_BB_BASE 0x22000000UL /!< SRAM base address in the bit-band region /
		591	#define PERIPH_BB_BASE 0x42000000UL /!< Peripheral base address in the bit-band region /
		592
		593	#define FSMC_BASE 0x60000000UL /!< FSMC base address /
		594	#define FSMC_R_BASE 0xA0000000UL /!< FSMC registers base address /
		595
		596	/!< Peripheral memory map /
		597	#define APB1PERIPH_BASE PERIPH_BASE
		598	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
		599	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
		600
		601	#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
		602	#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
		603	#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
		604	#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)
		605	#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)
		606	#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)
		607	#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
		608	#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
		609	#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
		610	#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
		611	#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)
		612	#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
		613	#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
		614	#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)
		615	#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)
		616	#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
		617	#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
		618	#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
		619	#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
		620	#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)
		621	#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)
		622	#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
		623	#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)
		624	#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
		625	#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
		626	#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
		627	#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)
		628	#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00UL)
		629	#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000UL)
		630	#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
		631	#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
		632	#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
		633
		634
		635	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
		636	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
		637	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
		638	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)
		639	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)
		640	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)
		641	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)
		642	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)
		643	#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL)
		644	#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL)
		645	#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL)
		646	#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL)
		647	#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL)
		648	#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL)
		649	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
		650	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
		651
		652	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /!< Flash registers base address /
		653	#define FLASHSIZE_BASE 0x1FFFF7E0UL /!< FLASH Size register base address /
		654	#define UID_BASE 0x1FFFF7E8UL /!< Unique device ID register base address /
		655	#define OB_BASE 0x1FFFF800UL /!< Flash Option Bytes base address /
		656
		657
		658	#define FSMC_BANK1 (FSMC_BASE) /!< FSMC Bank1 base address /
		659	#define FSMC_BANK1_1 (FSMC_BANK1) /!< FSMC Bank1_1 base address /
		660	#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL) /!< FSMC Bank1_2 base address /
		661	#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL) /!< FSMC Bank1_3 base address /
		662	#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL) /!< FSMC Bank1_4 base address /
		663
		664	#define FSMC_BANK2 (FSMC_BASE + 0x10000000UL) /!< FSMC Bank2 base address /
		665	#define FSMC_BANK3 (FSMC_BASE + 0x20000000UL) /!< FSMC Bank3 base address /
		666	#define FSMC_BANK4 (FSMC_BASE + 0x30000000UL) /!< FSMC Bank4 base address /
		667
		668	#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000UL) /!< FSMC Bank1 registers base address /
		669	#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104UL) /!< FSMC Bank1E registers base address /
		670	#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060UL) /!< FSMC Bank2/Bank3 registers base address /
		671	#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0UL) /!< FSMC Bank4 registers base address /
		672
		673	#define DBGMCU_BASE 0xE0042000UL /!< Debug MCU registers base address /
		674
		675
		676
		677	/**
		678	* @}
		679	*/
		680
		681	/** @addtogroup Peripheral_declaration
		682	* @{
		683	*/
		684
		685	#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
		686	#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
		687	#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
		688	#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
		689	#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
		690	#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
		691	#define RTC ((RTC_TypeDef *)RTC_BASE)
		692	#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
		693	#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
		694	#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
		695	#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
		696	#define USART2 ((USART_TypeDef *)USART2_BASE)
		697	#define USART3 ((USART_TypeDef *)USART3_BASE)
		698	#define UART4 ((USART_TypeDef *)UART4_BASE)
		699	#define UART5 ((USART_TypeDef *)UART5_BASE)
		700	#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
		701	#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
		702	#define BKP ((BKP_TypeDef *)BKP_BASE)
		703	#define PWR ((PWR_TypeDef *)PWR_BASE)
		704	#define DAC1 ((DAC_TypeDef *)DAC_BASE)
		705	#define DAC ((DAC_TypeDef )DAC_BASE) / Kept for legacy purpose */
		706	#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
		707	#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
		708	#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
		709	#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
		710	#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
		711	#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
		712	#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
		713	#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
		714	#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)
		715	#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
		716	#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
		717	#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
		718	#define USART1 ((USART_TypeDef *)USART1_BASE)
		719	#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
		720	#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
		721	#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
		722	#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
		723	#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
		724	#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
		725	#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
		726	#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
		727	#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
		728	#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
		729	#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
		730	#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
		731	#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
		732	#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
		733	#define RCC ((RCC_TypeDef *)RCC_BASE)
		734	#define CRC ((CRC_TypeDef *)CRC_BASE)
		735	#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
		736	#define OB ((OB_TypeDef *)OB_BASE)
		737	#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)
		738	#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)
		739	#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)
		740	#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)
		741	#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
		742
		743
		744	/**
		745	* @}
		746	*/
		747
		748	/** @addtogroup Exported_constants
		749	* @{
		750	*/
		751
		752	/** @addtogroup Hardware_Constant_Definition
		753	* @{
		754	*/
		755	#define LSI_STARTUP_TIME 85U /!< LSI Maximum startup time in us /
		756	/**
		757	* @}
		758	*/
		759
		760	/** @addtogroup Peripheral_Registers_Bits_Definition
		761	* @{
		762	*/
		763
		764	/******************************************************************************/
		765	/* Peripheral Registers_Bits_Definition */
		766	/******************************************************************************/
		767
		768	/******************************************************************************/
		769	/* */
		770	/* CRC calculation unit (CRC) */
		771	/* */
		772	/******************************************************************************/
		773
		774	/***************** Bit definition for CRC_DR register *******************/
		775	#define CRC_DR_DR_Pos (0U)
		776	#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /!< 0xFFFFFFFF /
		777	#define CRC_DR_DR CRC_DR_DR_Msk /!< Data register bits /
		778
		779	/***************** Bit definition for CRC_IDR register ******************/
		780	#define CRC_IDR_IDR_Pos (0U)
		781	#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /!< 0x000000FF /
		782	#define CRC_IDR_IDR CRC_IDR_IDR_Msk /!< General-purpose 8-bit data register bits /
		783
		784	/****************** Bit definition for CRC_CR register ******************/
		785	#define CRC_CR_RESET_Pos (0U)
		786	#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /!< 0x00000001 /
		787	#define CRC_CR_RESET CRC_CR_RESET_Msk /!< RESET bit /
		788
		789	/******************************************************************************/
		790	/* */
		791	/* Power Control */
		792	/* */
		793	/******************************************************************************/
		794
		795	/****************** Bit definition for PWR_CR register ******************/
		796	#define PWR_CR_LPDS_Pos (0U)
		797	#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /!< 0x00000001 /
		798	#define PWR_CR_LPDS PWR_CR_LPDS_Msk /!< Low-Power Deepsleep /
		799	#define PWR_CR_PDDS_Pos (1U)
		800	#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /!< 0x00000002 /
		801	#define PWR_CR_PDDS PWR_CR_PDDS_Msk /!< Power Down Deepsleep /
		802	#define PWR_CR_CWUF_Pos (2U)
		803	#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /!< 0x00000004 /
		804	#define PWR_CR_CWUF PWR_CR_CWUF_Msk /!< Clear Wakeup Flag /
		805	#define PWR_CR_CSBF_Pos (3U)
		806	#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /!< 0x00000008 /
		807	#define PWR_CR_CSBF PWR_CR_CSBF_Msk /!< Clear Standby Flag /
		808	#define PWR_CR_PVDE_Pos (4U)
		809	#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /!< 0x00000010 /
		810	#define PWR_CR_PVDE PWR_CR_PVDE_Msk /!< Power Voltage Detector Enable /
		811
		812	#define PWR_CR_PLS_Pos (5U)
		813	#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /!< 0x000000E0 /
		814	#define PWR_CR_PLS PWR_CR_PLS_Msk /!< PLS[2:0] bits (PVD Level Selection) /
		815	#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /!< 0x00000020 /
		816	#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /!< 0x00000040 /
		817	#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /!< 0x00000080 /
		818
		819	/!< PVD level configuration /
		820	#define PWR_CR_PLS_LEV0 0x00000000U /!< PVD level 2.2V /
		821	#define PWR_CR_PLS_LEV1 0x00000020U /!< PVD level 2.3V /
		822	#define PWR_CR_PLS_LEV2 0x00000040U /!< PVD level 2.4V /
		823	#define PWR_CR_PLS_LEV3 0x00000060U /!< PVD level 2.5V /
		824	#define PWR_CR_PLS_LEV4 0x00000080U /!< PVD level 2.6V /
		825	#define PWR_CR_PLS_LEV5 0x000000A0U /!< PVD level 2.7V /
		826	#define PWR_CR_PLS_LEV6 0x000000C0U /!< PVD level 2.8V /
		827	#define PWR_CR_PLS_LEV7 0x000000E0U /!< PVD level 2.9V /
		828
		829	/* Legacy defines */
		830	#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
		831	#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
		832	#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
		833	#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
		834	#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
		835	#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
		836	#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
		837	#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
		838
		839	#define PWR_CR_DBP_Pos (8U)
		840	#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /!< 0x00000100 /
		841	#define PWR_CR_DBP PWR_CR_DBP_Msk /!< Disable Backup Domain write protection /
		842
		843
		844	/***************** Bit definition for PWR_CSR register ******************/
		845	#define PWR_CSR_WUF_Pos (0U)
		846	#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /!< 0x00000001 /
		847	#define PWR_CSR_WUF PWR_CSR_WUF_Msk /!< Wakeup Flag /
		848	#define PWR_CSR_SBF_Pos (1U)
		849	#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /!< 0x00000002 /
		850	#define PWR_CSR_SBF PWR_CSR_SBF_Msk /!< Standby Flag /
		851	#define PWR_CSR_PVDO_Pos (2U)
		852	#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /!< 0x00000004 /
		853	#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /!< PVD Output /
		854	#define PWR_CSR_EWUP_Pos (8U)
		855	#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /!< 0x00000100 /
		856	#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /!< Enable WKUP pin /
		857
		858	/******************************************************************************/
		859	/* */
		860	/* Backup registers */
		861	/* */
		862	/******************************************************************************/
		863
		864	/***************** Bit definition for BKP_DR1 register ******************/
		865	#define BKP_DR1_D_Pos (0U)
		866	#define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /!< 0x0000FFFF /
		867	#define BKP_DR1_D BKP_DR1_D_Msk /!< Backup data /
		868
		869	/***************** Bit definition for BKP_DR2 register ******************/
		870	#define BKP_DR2_D_Pos (0U)
		871	#define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /!< 0x0000FFFF /
		872	#define BKP_DR2_D BKP_DR2_D_Msk /!< Backup data /
		873
		874	/***************** Bit definition for BKP_DR3 register ******************/
		875	#define BKP_DR3_D_Pos (0U)
		876	#define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /!< 0x0000FFFF /
		877	#define BKP_DR3_D BKP_DR3_D_Msk /!< Backup data /
		878
		879	/***************** Bit definition for BKP_DR4 register ******************/
		880	#define BKP_DR4_D_Pos (0U)
		881	#define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /!< 0x0000FFFF /
		882	#define BKP_DR4_D BKP_DR4_D_Msk /!< Backup data /
		883
		884	/***************** Bit definition for BKP_DR5 register ******************/
		885	#define BKP_DR5_D_Pos (0U)
		886	#define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /!< 0x0000FFFF /
		887	#define BKP_DR5_D BKP_DR5_D_Msk /!< Backup data /
		888
		889	/***************** Bit definition for BKP_DR6 register ******************/
		890	#define BKP_DR6_D_Pos (0U)
		891	#define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /!< 0x0000FFFF /
		892	#define BKP_DR6_D BKP_DR6_D_Msk /!< Backup data /
		893
		894	/***************** Bit definition for BKP_DR7 register ******************/
		895	#define BKP_DR7_D_Pos (0U)
		896	#define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /!< 0x0000FFFF /
		897	#define BKP_DR7_D BKP_DR7_D_Msk /!< Backup data /
		898
		899	/***************** Bit definition for BKP_DR8 register ******************/
		900	#define BKP_DR8_D_Pos (0U)
		901	#define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /!< 0x0000FFFF /
		902	#define BKP_DR8_D BKP_DR8_D_Msk /!< Backup data /
		903
		904	/***************** Bit definition for BKP_DR9 register ******************/
		905	#define BKP_DR9_D_Pos (0U)
		906	#define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /!< 0x0000FFFF /
		907	#define BKP_DR9_D BKP_DR9_D_Msk /!< Backup data /
		908
		909	/***************** Bit definition for BKP_DR10 register *****************/
		910	#define BKP_DR10_D_Pos (0U)
		911	#define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /!< 0x0000FFFF /
		912	#define BKP_DR10_D BKP_DR10_D_Msk /!< Backup data /
		913
		914	/***************** Bit definition for BKP_DR11 register *****************/
		915	#define BKP_DR11_D_Pos (0U)
		916	#define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos) /!< 0x0000FFFF /
		917	#define BKP_DR11_D BKP_DR11_D_Msk /!< Backup data /
		918
		919	/***************** Bit definition for BKP_DR12 register *****************/
		920	#define BKP_DR12_D_Pos (0U)
		921	#define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos) /!< 0x0000FFFF /
		922	#define BKP_DR12_D BKP_DR12_D_Msk /!< Backup data /
		923
		924	/***************** Bit definition for BKP_DR13 register *****************/
		925	#define BKP_DR13_D_Pos (0U)
		926	#define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos) /!< 0x0000FFFF /
		927	#define BKP_DR13_D BKP_DR13_D_Msk /!< Backup data /
		928
		929	/***************** Bit definition for BKP_DR14 register *****************/
		930	#define BKP_DR14_D_Pos (0U)
		931	#define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos) /!< 0x0000FFFF /
		932	#define BKP_DR14_D BKP_DR14_D_Msk /!< Backup data /
		933
		934	/***************** Bit definition for BKP_DR15 register *****************/
		935	#define BKP_DR15_D_Pos (0U)
		936	#define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos) /!< 0x0000FFFF /
		937	#define BKP_DR15_D BKP_DR15_D_Msk /!< Backup data /
		938
		939	/***************** Bit definition for BKP_DR16 register *****************/
		940	#define BKP_DR16_D_Pos (0U)
		941	#define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos) /!< 0x0000FFFF /
		942	#define BKP_DR16_D BKP_DR16_D_Msk /!< Backup data /
		943
		944	/***************** Bit definition for BKP_DR17 register *****************/
		945	#define BKP_DR17_D_Pos (0U)
		946	#define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos) /!< 0x0000FFFF /
		947	#define BKP_DR17_D BKP_DR17_D_Msk /!< Backup data /
		948
		949	/**************** Bit definition for BKP_DR18 register ******************/
		950	#define BKP_DR18_D_Pos (0U)
		951	#define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos) /!< 0x0000FFFF /
		952	#define BKP_DR18_D BKP_DR18_D_Msk /!< Backup data /
		953
		954	/***************** Bit definition for BKP_DR19 register *****************/
		955	#define BKP_DR19_D_Pos (0U)
		956	#define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos) /!< 0x0000FFFF /
		957	#define BKP_DR19_D BKP_DR19_D_Msk /!< Backup data /
		958
		959	/***************** Bit definition for BKP_DR20 register *****************/
		960	#define BKP_DR20_D_Pos (0U)
		961	#define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos) /!< 0x0000FFFF /
		962	#define BKP_DR20_D BKP_DR20_D_Msk /!< Backup data /
		963
		964	/***************** Bit definition for BKP_DR21 register *****************/
		965	#define BKP_DR21_D_Pos (0U)
		966	#define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos) /!< 0x0000FFFF /
		967	#define BKP_DR21_D BKP_DR21_D_Msk /!< Backup data /
		968
		969	/***************** Bit definition for BKP_DR22 register *****************/
		970	#define BKP_DR22_D_Pos (0U)
		971	#define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos) /!< 0x0000FFFF /
		972	#define BKP_DR22_D BKP_DR22_D_Msk /!< Backup data /
		973
		974	/***************** Bit definition for BKP_DR23 register *****************/
		975	#define BKP_DR23_D_Pos (0U)
		976	#define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos) /!< 0x0000FFFF /
		977	#define BKP_DR23_D BKP_DR23_D_Msk /!< Backup data /
		978
		979	/***************** Bit definition for BKP_DR24 register *****************/
		980	#define BKP_DR24_D_Pos (0U)
		981	#define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos) /!< 0x0000FFFF /
		982	#define BKP_DR24_D BKP_DR24_D_Msk /!< Backup data /
		983
		984	/***************** Bit definition for BKP_DR25 register *****************/
		985	#define BKP_DR25_D_Pos (0U)
		986	#define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos) /!< 0x0000FFFF /
		987	#define BKP_DR25_D BKP_DR25_D_Msk /!< Backup data /
		988
		989	/***************** Bit definition for BKP_DR26 register *****************/
		990	#define BKP_DR26_D_Pos (0U)
		991	#define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos) /!< 0x0000FFFF /
		992	#define BKP_DR26_D BKP_DR26_D_Msk /!< Backup data /
		993
		994	/***************** Bit definition for BKP_DR27 register *****************/
		995	#define BKP_DR27_D_Pos (0U)
		996	#define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos) /!< 0x0000FFFF /
		997	#define BKP_DR27_D BKP_DR27_D_Msk /!< Backup data /
		998
		999	/***************** Bit definition for BKP_DR28 register *****************/
		1000	#define BKP_DR28_D_Pos (0U)
		1001	#define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos) /!< 0x0000FFFF /
		1002	#define BKP_DR28_D BKP_DR28_D_Msk /!< Backup data /
		1003
		1004	/***************** Bit definition for BKP_DR29 register *****************/
		1005	#define BKP_DR29_D_Pos (0U)
		1006	#define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos) /!< 0x0000FFFF /
		1007	#define BKP_DR29_D BKP_DR29_D_Msk /!< Backup data /
		1008
		1009	/***************** Bit definition for BKP_DR30 register *****************/
		1010	#define BKP_DR30_D_Pos (0U)
		1011	#define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos) /!< 0x0000FFFF /
		1012	#define BKP_DR30_D BKP_DR30_D_Msk /!< Backup data /
		1013
		1014	/***************** Bit definition for BKP_DR31 register *****************/
		1015	#define BKP_DR31_D_Pos (0U)
		1016	#define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos) /!< 0x0000FFFF /
		1017	#define BKP_DR31_D BKP_DR31_D_Msk /!< Backup data /
		1018
		1019	/***************** Bit definition for BKP_DR32 register *****************/
		1020	#define BKP_DR32_D_Pos (0U)
		1021	#define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos) /!< 0x0000FFFF /
		1022	#define BKP_DR32_D BKP_DR32_D_Msk /!< Backup data /
		1023
		1024	/***************** Bit definition for BKP_DR33 register *****************/
		1025	#define BKP_DR33_D_Pos (0U)
		1026	#define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos) /!< 0x0000FFFF /
		1027	#define BKP_DR33_D BKP_DR33_D_Msk /!< Backup data /
		1028
		1029	/***************** Bit definition for BKP_DR34 register *****************/
		1030	#define BKP_DR34_D_Pos (0U)
		1031	#define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos) /!< 0x0000FFFF /
		1032	#define BKP_DR34_D BKP_DR34_D_Msk /!< Backup data /
		1033
		1034	/***************** Bit definition for BKP_DR35 register *****************/
		1035	#define BKP_DR35_D_Pos (0U)
		1036	#define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos) /!< 0x0000FFFF /
		1037	#define BKP_DR35_D BKP_DR35_D_Msk /!< Backup data /
		1038
		1039	/***************** Bit definition for BKP_DR36 register *****************/
		1040	#define BKP_DR36_D_Pos (0U)
		1041	#define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos) /!< 0x0000FFFF /
		1042	#define BKP_DR36_D BKP_DR36_D_Msk /!< Backup data /
		1043
		1044	/***************** Bit definition for BKP_DR37 register *****************/
		1045	#define BKP_DR37_D_Pos (0U)
		1046	#define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos) /!< 0x0000FFFF /
		1047	#define BKP_DR37_D BKP_DR37_D_Msk /!< Backup data /
		1048
		1049	/***************** Bit definition for BKP_DR38 register *****************/
		1050	#define BKP_DR38_D_Pos (0U)
		1051	#define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos) /!< 0x0000FFFF /
		1052	#define BKP_DR38_D BKP_DR38_D_Msk /!< Backup data /
		1053
		1054	/***************** Bit definition for BKP_DR39 register *****************/
		1055	#define BKP_DR39_D_Pos (0U)
		1056	#define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos) /!< 0x0000FFFF /
		1057	#define BKP_DR39_D BKP_DR39_D_Msk /!< Backup data /
		1058
		1059	/***************** Bit definition for BKP_DR40 register *****************/
		1060	#define BKP_DR40_D_Pos (0U)
		1061	#define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos) /!< 0x0000FFFF /
		1062	#define BKP_DR40_D BKP_DR40_D_Msk /!< Backup data /
		1063
		1064	/***************** Bit definition for BKP_DR41 register *****************/
		1065	#define BKP_DR41_D_Pos (0U)
		1066	#define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos) /!< 0x0000FFFF /
		1067	#define BKP_DR41_D BKP_DR41_D_Msk /!< Backup data /
		1068
		1069	/***************** Bit definition for BKP_DR42 register *****************/
		1070	#define BKP_DR42_D_Pos (0U)
		1071	#define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos) /!< 0x0000FFFF /
		1072	#define BKP_DR42_D BKP_DR42_D_Msk /!< Backup data /
		1073
		1074	#define RTC_BKP_NUMBER 42
		1075
		1076	/**************** Bit definition for BKP_RTCCR register *****************/
		1077	#define BKP_RTCCR_CAL_Pos (0U)
		1078	#define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /!< 0x0000007F /
		1079	#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /!< Calibration value /
		1080	#define BKP_RTCCR_CCO_Pos (7U)
		1081	#define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /!< 0x00000080 /
		1082	#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /!< Calibration Clock Output /
		1083	#define BKP_RTCCR_ASOE_Pos (8U)
		1084	#define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /!< 0x00000100 /
		1085	#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /!< Alarm or Second Output Enable /
		1086	#define BKP_RTCCR_ASOS_Pos (9U)
		1087	#define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /!< 0x00000200 /
		1088	#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /!< Alarm or Second Output Selection /
		1089
		1090	/****************** Bit definition for BKP_CR register ******************/
		1091	#define BKP_CR_TPE_Pos (0U)
		1092	#define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /!< 0x00000001 /
		1093	#define BKP_CR_TPE BKP_CR_TPE_Msk /!< TAMPER pin enable /
		1094	#define BKP_CR_TPAL_Pos (1U)
		1095	#define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /!< 0x00000002 /
		1096	#define BKP_CR_TPAL BKP_CR_TPAL_Msk /!< TAMPER pin active level /
		1097
		1098	/***************** Bit definition for BKP_CSR register ******************/
		1099	#define BKP_CSR_CTE_Pos (0U)
		1100	#define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /!< 0x00000001 /
		1101	#define BKP_CSR_CTE BKP_CSR_CTE_Msk /!< Clear Tamper event /
		1102	#define BKP_CSR_CTI_Pos (1U)
		1103	#define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /!< 0x00000002 /
		1104	#define BKP_CSR_CTI BKP_CSR_CTI_Msk /!< Clear Tamper Interrupt /
		1105	#define BKP_CSR_TPIE_Pos (2U)
		1106	#define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /!< 0x00000004 /
		1107	#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /!< TAMPER Pin interrupt enable /
		1108	#define BKP_CSR_TEF_Pos (8U)
		1109	#define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /!< 0x00000100 /
		1110	#define BKP_CSR_TEF BKP_CSR_TEF_Msk /!< Tamper Event Flag /
		1111	#define BKP_CSR_TIF_Pos (9U)
		1112	#define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /!< 0x00000200 /
		1113	#define BKP_CSR_TIF BKP_CSR_TIF_Msk /!< Tamper Interrupt Flag /
		1114
		1115	/******************************************************************************/
		1116	/* */
		1117	/* Reset and Clock Control */
		1118	/* */
		1119	/******************************************************************************/
		1120
		1121	/****************** Bit definition for RCC_CR register ******************/
		1122	#define RCC_CR_HSION_Pos (0U)
		1123	#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /!< 0x00000001 /
		1124	#define RCC_CR_HSION RCC_CR_HSION_Msk /!< Internal High Speed clock enable /
		1125	#define RCC_CR_HSIRDY_Pos (1U)
		1126	#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /!< 0x00000002 /
		1127	#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /!< Internal High Speed clock ready flag /
		1128	#define RCC_CR_HSITRIM_Pos (3U)
		1129	#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /!< 0x000000F8 /
		1130	#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /!< Internal High Speed clock trimming /
		1131	#define RCC_CR_HSICAL_Pos (8U)
		1132	#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /!< 0x0000FF00 /
		1133	#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /!< Internal High Speed clock Calibration /
		1134	#define RCC_CR_HSEON_Pos (16U)
		1135	#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /!< 0x00010000 /
		1136	#define RCC_CR_HSEON RCC_CR_HSEON_Msk /!< External High Speed clock enable /
		1137	#define RCC_CR_HSERDY_Pos (17U)
		1138	#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /!< 0x00020000 /
		1139	#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /!< External High Speed clock ready flag /
		1140	#define RCC_CR_HSEBYP_Pos (18U)
		1141	#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /!< 0x00040000 /
		1142	#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /!< External High Speed clock Bypass /
		1143	#define RCC_CR_CSSON_Pos (19U)
		1144	#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /!< 0x00080000 /
		1145	#define RCC_CR_CSSON RCC_CR_CSSON_Msk /!< Clock Security System enable /
		1146	#define RCC_CR_PLLON_Pos (24U)
		1147	#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /!< 0x01000000 /
		1148	#define RCC_CR_PLLON RCC_CR_PLLON_Msk /!< PLL enable /
		1149	#define RCC_CR_PLLRDY_Pos (25U)
		1150	#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /!< 0x02000000 /
		1151	#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /!< PLL clock ready flag /
		1152
		1153
		1154	/***************** Bit definition for RCC_CFGR register *****************/
		1155	/!< SW configuration /
		1156	#define RCC_CFGR_SW_Pos (0U)
		1157	#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /!< 0x00000003 /
		1158	#define RCC_CFGR_SW RCC_CFGR_SW_Msk /!< SW[1:0] bits (System clock Switch) /
		1159	#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /!< 0x00000001 /
		1160	#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /!< 0x00000002 /
		1161
		1162	#define RCC_CFGR_SW_HSI 0x00000000U /!< HSI selected as system clock /
		1163	#define RCC_CFGR_SW_HSE 0x00000001U /!< HSE selected as system clock /
		1164	#define RCC_CFGR_SW_PLL 0x00000002U /!< PLL selected as system clock /
		1165
		1166	/!< SWS configuration /
		1167	#define RCC_CFGR_SWS_Pos (2U)
		1168	#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /!< 0x0000000C /
		1169	#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /!< SWS[1:0] bits (System Clock Switch Status) /
		1170	#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /!< 0x00000004 /
		1171	#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /!< 0x00000008 /
		1172
		1173	#define RCC_CFGR_SWS_HSI 0x00000000U /!< HSI oscillator used as system clock /
		1174	#define RCC_CFGR_SWS_HSE 0x00000004U /!< HSE oscillator used as system clock /
		1175	#define RCC_CFGR_SWS_PLL 0x00000008U /!< PLL used as system clock /
		1176
		1177	/!< HPRE configuration /
		1178	#define RCC_CFGR_HPRE_Pos (4U)
		1179	#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /!< 0x000000F0 /
		1180	#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /!< HPRE[3:0] bits (AHB prescaler) /
		1181	#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /!< 0x00000010 /
		1182	#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /!< 0x00000020 /
		1183	#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /!< 0x00000040 /
		1184	#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /!< 0x00000080 /
		1185
		1186	#define RCC_CFGR_HPRE_DIV1 0x00000000U /!< SYSCLK not divided /
		1187	#define RCC_CFGR_HPRE_DIV2 0x00000080U /!< SYSCLK divided by 2 /
		1188	#define RCC_CFGR_HPRE_DIV4 0x00000090U /!< SYSCLK divided by 4 /
		1189	#define RCC_CFGR_HPRE_DIV8 0x000000A0U /!< SYSCLK divided by 8 /
		1190	#define RCC_CFGR_HPRE_DIV16 0x000000B0U /!< SYSCLK divided by 16 /
		1191	#define RCC_CFGR_HPRE_DIV64 0x000000C0U /!< SYSCLK divided by 64 /
		1192	#define RCC_CFGR_HPRE_DIV128 0x000000D0U /!< SYSCLK divided by 128 /
		1193	#define RCC_CFGR_HPRE_DIV256 0x000000E0U /!< SYSCLK divided by 256 /
		1194	#define RCC_CFGR_HPRE_DIV512 0x000000F0U /!< SYSCLK divided by 512 /
		1195
		1196	/!< PPRE1 configuration /
		1197	#define RCC_CFGR_PPRE1_Pos (8U)
		1198	#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000700 /
		1199	#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /!< PRE1[2:0] bits (APB1 prescaler) /
		1200	#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000100 /
		1201	#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000200 /
		1202	#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000400 /
		1203
		1204	#define RCC_CFGR_PPRE1_DIV1 0x00000000U /!< HCLK not divided /
		1205	#define RCC_CFGR_PPRE1_DIV2 0x00000400U /!< HCLK divided by 2 /
		1206	#define RCC_CFGR_PPRE1_DIV4 0x00000500U /!< HCLK divided by 4 /
		1207	#define RCC_CFGR_PPRE1_DIV8 0x00000600U /!< HCLK divided by 8 /
		1208	#define RCC_CFGR_PPRE1_DIV16 0x00000700U /!< HCLK divided by 16 /
		1209
		1210	/!< PPRE2 configuration /
		1211	#define RCC_CFGR_PPRE2_Pos (11U)
		1212	#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /!< 0x00003800 /
		1213	#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /!< PRE2[2:0] bits (APB2 prescaler) /
		1214	#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /!< 0x00000800 /
		1215	#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /!< 0x00001000 /
		1216	#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /!< 0x00002000 /
		1217
		1218	#define RCC_CFGR_PPRE2_DIV1 0x00000000U /!< HCLK not divided /
		1219	#define RCC_CFGR_PPRE2_DIV2 0x00002000U /!< HCLK divided by 2 /
		1220	#define RCC_CFGR_PPRE2_DIV4 0x00002800U /!< HCLK divided by 4 /
		1221	#define RCC_CFGR_PPRE2_DIV8 0x00003000U /!< HCLK divided by 8 /
		1222	#define RCC_CFGR_PPRE2_DIV16 0x00003800U /!< HCLK divided by 16 /
		1223
		1224	/!< ADCPPRE configuration /
		1225	#define RCC_CFGR_ADCPRE_Pos (14U)
		1226	#define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /!< 0x0000C000 /
		1227	#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /!< ADCPRE[1:0] bits (ADC prescaler) /
		1228	#define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /!< 0x00004000 /
		1229	#define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /!< 0x00008000 /
		1230
		1231	#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /!< PCLK2 divided by 2 /
		1232	#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /!< PCLK2 divided by 4 /
		1233	#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /!< PCLK2 divided by 6 /
		1234	#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /!< PCLK2 divided by 8 /
		1235
		1236	#define RCC_CFGR_PLLSRC_Pos (16U)
		1237	#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /!< 0x00010000 /
		1238	#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /!< PLL entry clock source /
		1239
		1240	#define RCC_CFGR_PLLXTPRE_Pos (17U)
		1241	#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /!< 0x00020000 /
		1242	#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /!< HSE divider for PLL entry /
		1243
		1244	/!< PLLMUL configuration /
		1245	#define RCC_CFGR_PLLMULL_Pos (18U)
		1246	#define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /!< 0x003C0000 /
		1247	#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /!< PLLMUL[3:0] bits (PLL multiplication factor) /
		1248	#define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /!< 0x00040000 /
		1249	#define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /!< 0x00080000 /
		1250	#define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /!< 0x00100000 /
		1251	#define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /!< 0x00200000 /
		1252
		1253	#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /!< HSE clock not divided for PLL entry /
		1254	#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /!< HSE clock divided by 2 for PLL entry /
		1255
		1256	#define RCC_CFGR_PLLMULL2 0x00000000U /!< PLL input clock2 */
		1257	#define RCC_CFGR_PLLMULL3_Pos (18U)
		1258	#define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /!< 0x00040000 /
		1259	#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /!< PLL input clock3 */
		1260	#define RCC_CFGR_PLLMULL4_Pos (19U)
		1261	#define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /!< 0x00080000 /
		1262	#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /!< PLL input clock4 */
		1263	#define RCC_CFGR_PLLMULL5_Pos (18U)
		1264	#define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /!< 0x000C0000 /
		1265	#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /!< PLL input clock5 */
		1266	#define RCC_CFGR_PLLMULL6_Pos (20U)
		1267	#define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /!< 0x00100000 /
		1268	#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /!< PLL input clock6 */
		1269	#define RCC_CFGR_PLLMULL7_Pos (18U)
		1270	#define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /!< 0x00140000 /
		1271	#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /!< PLL input clock7 */
		1272	#define RCC_CFGR_PLLMULL8_Pos (19U)
		1273	#define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /!< 0x00180000 /
		1274	#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /!< PLL input clock8 */
		1275	#define RCC_CFGR_PLLMULL9_Pos (18U)
		1276	#define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /!< 0x001C0000 /
		1277	#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /!< PLL input clock9 */
		1278	#define RCC_CFGR_PLLMULL10_Pos (21U)
		1279	#define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /!< 0x00200000 /
		1280	#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /!< PLL input clock10 /
		1281	#define RCC_CFGR_PLLMULL11_Pos (18U)
		1282	#define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /!< 0x00240000 /
		1283	#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /!< PLL input clock11 */
		1284	#define RCC_CFGR_PLLMULL12_Pos (19U)
		1285	#define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /!< 0x00280000 /
		1286	#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /!< PLL input clock12 */
		1287	#define RCC_CFGR_PLLMULL13_Pos (18U)
		1288	#define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /!< 0x002C0000 /
		1289	#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /!< PLL input clock13 */
		1290	#define RCC_CFGR_PLLMULL14_Pos (20U)
		1291	#define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /!< 0x00300000 /
		1292	#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /!< PLL input clock14 */
		1293	#define RCC_CFGR_PLLMULL15_Pos (18U)
		1294	#define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /!< 0x00340000 /
		1295	#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /!< PLL input clock15 */
		1296	#define RCC_CFGR_PLLMULL16_Pos (19U)
		1297	#define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /!< 0x00380000 /
		1298	#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /!< PLL input clock16 */
		1299
		1300	/!< MCO configuration /
		1301	#define RCC_CFGR_MCO_Pos (24U)
		1302	#define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /!< 0x07000000 /
		1303	#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /!< MCO[2:0] bits (Microcontroller Clock Output) /
		1304	#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /!< 0x01000000 /
		1305	#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /!< 0x02000000 /
		1306	#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /!< 0x04000000 /
		1307
		1308	#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /!< No clock /
		1309	#define RCC_CFGR_MCO_SYSCLK 0x04000000U /!< System clock selected as MCO source /
		1310	#define RCC_CFGR_MCO_HSI 0x05000000U /!< HSI clock selected as MCO source /
		1311	#define RCC_CFGR_MCO_HSE 0x06000000U /!< HSE clock selected as MCO source /
		1312	#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /!< PLL clock divided by 2 selected as MCO source /
		1313
		1314	/* Reference defines */
		1315	#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
		1316	#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
		1317	#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
		1318	#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
		1319	#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
		1320	#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
		1321	#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
		1322	#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
		1323	#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
		1324
		1325	/!<*************** Bit definition for RCC_CIR register ******************/
		1326	#define RCC_CIR_LSIRDYF_Pos (0U)
		1327	#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /!< 0x00000001 /
		1328	#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /!< LSI Ready Interrupt flag /
		1329	#define RCC_CIR_LSERDYF_Pos (1U)
		1330	#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /!< 0x00000002 /
		1331	#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /!< LSE Ready Interrupt flag /
		1332	#define RCC_CIR_HSIRDYF_Pos (2U)
		1333	#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /!< 0x00000004 /
		1334	#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /!< HSI Ready Interrupt flag /
		1335	#define RCC_CIR_HSERDYF_Pos (3U)
		1336	#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /!< 0x00000008 /
		1337	#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /!< HSE Ready Interrupt flag /
		1338	#define RCC_CIR_PLLRDYF_Pos (4U)
		1339	#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /!< 0x00000010 /
		1340	#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /!< PLL Ready Interrupt flag /
		1341	#define RCC_CIR_CSSF_Pos (7U)
		1342	#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /!< 0x00000080 /
		1343	#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /!< Clock Security System Interrupt flag /
		1344	#define RCC_CIR_LSIRDYIE_Pos (8U)
		1345	#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /!< 0x00000100 /
		1346	#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /!< LSI Ready Interrupt Enable /
		1347	#define RCC_CIR_LSERDYIE_Pos (9U)
		1348	#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /!< 0x00000200 /
		1349	#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /!< LSE Ready Interrupt Enable /
		1350	#define RCC_CIR_HSIRDYIE_Pos (10U)
		1351	#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /!< 0x00000400 /
		1352	#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /!< HSI Ready Interrupt Enable /
		1353	#define RCC_CIR_HSERDYIE_Pos (11U)
		1354	#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /!< 0x00000800 /
		1355	#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /!< HSE Ready Interrupt Enable /
		1356	#define RCC_CIR_PLLRDYIE_Pos (12U)
		1357	#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /!< 0x00001000 /
		1358	#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /!< PLL Ready Interrupt Enable /
		1359	#define RCC_CIR_LSIRDYC_Pos (16U)
		1360	#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /!< 0x00010000 /
		1361	#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /!< LSI Ready Interrupt Clear /
		1362	#define RCC_CIR_LSERDYC_Pos (17U)
		1363	#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /!< 0x00020000 /
		1364	#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /!< LSE Ready Interrupt Clear /
		1365	#define RCC_CIR_HSIRDYC_Pos (18U)
		1366	#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /!< 0x00040000 /
		1367	#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /!< HSI Ready Interrupt Clear /
		1368	#define RCC_CIR_HSERDYC_Pos (19U)
		1369	#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /!< 0x00080000 /
		1370	#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /!< HSE Ready Interrupt Clear /
		1371	#define RCC_CIR_PLLRDYC_Pos (20U)
		1372	#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /!< 0x00100000 /
		1373	#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /!< PLL Ready Interrupt Clear /
		1374	#define RCC_CIR_CSSC_Pos (23U)
		1375	#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /!< 0x00800000 /
		1376	#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /!< Clock Security System Interrupt Clear /
		1377
		1378
		1379	/*************** Bit definition for RCC_APB2RSTR register ***************/
		1380	#define RCC_APB2RSTR_AFIORST_Pos (0U)
		1381	#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /!< 0x00000001 /
		1382	#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /!< Alternate Function I/O reset /
		1383	#define RCC_APB2RSTR_IOPARST_Pos (2U)
		1384	#define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /!< 0x00000004 /
		1385	#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /!< I/O port A reset /
		1386	#define RCC_APB2RSTR_IOPBRST_Pos (3U)
		1387	#define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /!< 0x00000008 /
		1388	#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /!< I/O port B reset /
		1389	#define RCC_APB2RSTR_IOPCRST_Pos (4U)
		1390	#define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /!< 0x00000010 /
		1391	#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /!< I/O port C reset /
		1392	#define RCC_APB2RSTR_IOPDRST_Pos (5U)
		1393	#define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /!< 0x00000020 /
		1394	#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /!< I/O port D reset /
		1395	#define RCC_APB2RSTR_ADC1RST_Pos (9U)
		1396	#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /!< 0x00000200 /
		1397	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /!< ADC 1 interface reset /
		1398
		1399
		1400	#define RCC_APB2RSTR_TIM1RST_Pos (11U)
		1401	#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /!< 0x00000800 /
		1402	#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /!< TIM1 Timer reset /
		1403	#define RCC_APB2RSTR_SPI1RST_Pos (12U)
		1404	#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /!< 0x00001000 /
		1405	#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /!< SPI 1 reset /
		1406	#define RCC_APB2RSTR_USART1RST_Pos (14U)
		1407	#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /!< 0x00004000 /
		1408	#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /!< USART1 reset /
		1409
		1410
		1411	#define RCC_APB2RSTR_IOPERST_Pos (6U)
		1412	#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /!< 0x00000040 /
		1413	#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /!< I/O port E reset /
		1414
		1415	#define RCC_APB2RSTR_IOPFRST_Pos (7U)
		1416	#define RCC_APB2RSTR_IOPFRST_Msk (0x1UL << RCC_APB2RSTR_IOPFRST_Pos) /!< 0x00000080 /
		1417	#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /!< I/O port F reset /
		1418	#define RCC_APB2RSTR_IOPGRST_Pos (8U)
		1419	#define RCC_APB2RSTR_IOPGRST_Msk (0x1UL << RCC_APB2RSTR_IOPGRST_Pos) /!< 0x00000100 /
		1420	#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /!< I/O port G reset /
		1421
		1422
		1423
		1424	/*************** Bit definition for RCC_APB1RSTR register ***************/
		1425	#define RCC_APB1RSTR_TIM2RST_Pos (0U)
		1426	#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /!< 0x00000001 /
		1427	#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /!< Timer 2 reset /
		1428	#define RCC_APB1RSTR_TIM3RST_Pos (1U)
		1429	#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /!< 0x00000002 /
		1430	#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /!< Timer 3 reset /
		1431	#define RCC_APB1RSTR_WWDGRST_Pos (11U)
		1432	#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /!< 0x00000800 /
		1433	#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /!< Window Watchdog reset /
		1434	#define RCC_APB1RSTR_USART2RST_Pos (17U)
		1435	#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /!< 0x00020000 /
		1436	#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /!< USART 2 reset /
		1437	#define RCC_APB1RSTR_I2C1RST_Pos (21U)
		1438	#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /!< 0x00200000 /
		1439	#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /!< I2C 1 reset /
		1440
		1441
		1442	#define RCC_APB1RSTR_BKPRST_Pos (27U)
		1443	#define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /!< 0x08000000 /
		1444	#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /!< Backup interface reset /
		1445	#define RCC_APB1RSTR_PWRRST_Pos (28U)
		1446	#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /!< 0x10000000 /
		1447	#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /!< Power interface reset /
		1448
		1449	#define RCC_APB1RSTR_TIM4RST_Pos (2U)
		1450	#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /!< 0x00000004 /
		1451	#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /!< Timer 4 reset /
		1452	#define RCC_APB1RSTR_SPI2RST_Pos (14U)
		1453	#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /!< 0x00004000 /
		1454	#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /!< SPI 2 reset /
		1455	#define RCC_APB1RSTR_USART3RST_Pos (18U)
		1456	#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /!< 0x00040000 /
		1457	#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /!< USART 3 reset /
		1458	#define RCC_APB1RSTR_I2C2RST_Pos (22U)
		1459	#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /!< 0x00400000 /
		1460	#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /!< I2C 2 reset /
		1461
		1462
		1463	#define RCC_APB1RSTR_TIM5RST_Pos (3U)
		1464	#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /!< 0x00000008 /
		1465	#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /!< Timer 5 reset /
		1466	#define RCC_APB1RSTR_TIM6RST_Pos (4U)
		1467	#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /!< 0x00000010 /
		1468	#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /!< Timer 6 reset /
		1469	#define RCC_APB1RSTR_TIM7RST_Pos (5U)
		1470	#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /!< 0x00000020 /
		1471	#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /!< Timer 7 reset /
		1472	#define RCC_APB1RSTR_SPI3RST_Pos (15U)
		1473	#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /!< 0x00008000 /
		1474	#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /!< SPI 3 reset /
		1475	#define RCC_APB1RSTR_UART4RST_Pos (19U)
		1476	#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /!< 0x00080000 /
		1477	#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /!< UART 4 reset /
		1478	#define RCC_APB1RSTR_UART5RST_Pos (20U)
		1479	#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /!< 0x00100000 /
		1480	#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /!< UART 5 reset /
		1481
		1482
		1483
		1484
		1485	#define RCC_APB1RSTR_DACRST_Pos (29U)
		1486	#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /!< 0x20000000 /
		1487	#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /!< DAC interface reset /
		1488
		1489	/**************** Bit definition for RCC_AHBENR register ****************/
		1490	#define RCC_AHBENR_DMA1EN_Pos (0U)
		1491	#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /!< 0x00000001 /
		1492	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /!< DMA1 clock enable /
		1493	#define RCC_AHBENR_SRAMEN_Pos (2U)
		1494	#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /!< 0x00000004 /
		1495	#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /!< SRAM interface clock enable /
		1496	#define RCC_AHBENR_FLITFEN_Pos (4U)
		1497	#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /!< 0x00000010 /
		1498	#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /!< FLITF clock enable /
		1499	#define RCC_AHBENR_CRCEN_Pos (6U)
		1500	#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /!< 0x00000040 /
		1501	#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /!< CRC clock enable /
		1502
		1503	#define RCC_AHBENR_DMA2EN_Pos (1U)
		1504	#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /!< 0x00000002 /
		1505	#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /!< DMA2 clock enable /
		1506
		1507	#define RCC_AHBENR_FSMCEN_Pos (8U)
		1508	#define RCC_AHBENR_FSMCEN_Msk (0x1UL << RCC_AHBENR_FSMCEN_Pos) /!< 0x00000100 /
		1509	#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /!< FSMC clock enable /
		1510
		1511
		1512	/**************** Bit definition for RCC_APB2ENR register ***************/
		1513	#define RCC_APB2ENR_AFIOEN_Pos (0U)
		1514	#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /!< 0x00000001 /
		1515	#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /!< Alternate Function I/O clock enable /
		1516	#define RCC_APB2ENR_IOPAEN_Pos (2U)
		1517	#define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /!< 0x00000004 /
		1518	#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /!< I/O port A clock enable /
		1519	#define RCC_APB2ENR_IOPBEN_Pos (3U)
		1520	#define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /!< 0x00000008 /
		1521	#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /!< I/O port B clock enable /
		1522	#define RCC_APB2ENR_IOPCEN_Pos (4U)
		1523	#define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /!< 0x00000010 /
		1524	#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /!< I/O port C clock enable /
		1525	#define RCC_APB2ENR_IOPDEN_Pos (5U)
		1526	#define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /!< 0x00000020 /
		1527	#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /!< I/O port D clock enable /
		1528	#define RCC_APB2ENR_ADC1EN_Pos (9U)
		1529	#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /!< 0x00000200 /
		1530	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /!< ADC 1 interface clock enable /
		1531
		1532
		1533	#define RCC_APB2ENR_TIM1EN_Pos (11U)
		1534	#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /!< 0x00000800 /
		1535	#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /!< TIM1 Timer clock enable /
		1536	#define RCC_APB2ENR_SPI1EN_Pos (12U)
		1537	#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /!< 0x00001000 /
		1538	#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /!< SPI 1 clock enable /
		1539	#define RCC_APB2ENR_USART1EN_Pos (14U)
		1540	#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /!< 0x00004000 /
		1541	#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /!< USART1 clock enable /
		1542
		1543
		1544	#define RCC_APB2ENR_IOPEEN_Pos (6U)
		1545	#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /!< 0x00000040 /
		1546	#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /!< I/O port E clock enable /
		1547
		1548	#define RCC_APB2ENR_IOPFEN_Pos (7U)
		1549	#define RCC_APB2ENR_IOPFEN_Msk (0x1UL << RCC_APB2ENR_IOPFEN_Pos) /!< 0x00000080 /
		1550	#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /!< I/O port F clock enable /
		1551	#define RCC_APB2ENR_IOPGEN_Pos (8U)
		1552	#define RCC_APB2ENR_IOPGEN_Msk (0x1UL << RCC_APB2ENR_IOPGEN_Pos) /!< 0x00000100 /
		1553	#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /!< I/O port G clock enable /
		1554
		1555
		1556
		1557	/*************** Bit definition for RCC_APB1ENR register ****************/
		1558	#define RCC_APB1ENR_TIM2EN_Pos (0U)
		1559	#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /!< 0x00000001 /
		1560	#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /!< Timer 2 clock enabled/
		1561	#define RCC_APB1ENR_TIM3EN_Pos (1U)
		1562	#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /!< 0x00000002 /
		1563	#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /!< Timer 3 clock enable /
		1564	#define RCC_APB1ENR_WWDGEN_Pos (11U)
		1565	#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /!< 0x00000800 /
		1566	#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /!< Window Watchdog clock enable /
		1567	#define RCC_APB1ENR_USART2EN_Pos (17U)
		1568	#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /!< 0x00020000 /
		1569	#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /!< USART 2 clock enable /
		1570	#define RCC_APB1ENR_I2C1EN_Pos (21U)
		1571	#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /!< 0x00200000 /
		1572	#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /!< I2C 1 clock enable /
		1573
		1574
		1575	#define RCC_APB1ENR_BKPEN_Pos (27U)
		1576	#define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /!< 0x08000000 /
		1577	#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /!< Backup interface clock enable /
		1578	#define RCC_APB1ENR_PWREN_Pos (28U)
		1579	#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /!< 0x10000000 /
		1580	#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /!< Power interface clock enable /
		1581
		1582	#define RCC_APB1ENR_TIM4EN_Pos (2U)
		1583	#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /!< 0x00000004 /
		1584	#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /!< Timer 4 clock enable /
		1585	#define RCC_APB1ENR_SPI2EN_Pos (14U)
		1586	#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /!< 0x00004000 /
		1587	#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /!< SPI 2 clock enable /
		1588	#define RCC_APB1ENR_USART3EN_Pos (18U)
		1589	#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /!< 0x00040000 /
		1590	#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /!< USART 3 clock enable /
		1591	#define RCC_APB1ENR_I2C2EN_Pos (22U)
		1592	#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /!< 0x00400000 /
		1593	#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /!< I2C 2 clock enable /
		1594
		1595
		1596	#define RCC_APB1ENR_TIM5EN_Pos (3U)
		1597	#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /!< 0x00000008 /
		1598	#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /!< Timer 5 clock enable /
		1599	#define RCC_APB1ENR_TIM6EN_Pos (4U)
		1600	#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /!< 0x00000010 /
		1601	#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /!< Timer 6 clock enable /
		1602	#define RCC_APB1ENR_TIM7EN_Pos (5U)
		1603	#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /!< 0x00000020 /
		1604	#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /!< Timer 7 clock enable /
		1605	#define RCC_APB1ENR_SPI3EN_Pos (15U)
		1606	#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /!< 0x00008000 /
		1607	#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /!< SPI 3 clock enable /
		1608	#define RCC_APB1ENR_UART4EN_Pos (19U)
		1609	#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /!< 0x00080000 /
		1610	#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /!< UART 4 clock enable /
		1611	#define RCC_APB1ENR_UART5EN_Pos (20U)
		1612	#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /!< 0x00100000 /
		1613	#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /!< UART 5 clock enable /
		1614
		1615
		1616
		1617
		1618	#define RCC_APB1ENR_DACEN_Pos (29U)
		1619	#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /!< 0x20000000 /
		1620	#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /!< DAC interface clock enable /
		1621
		1622	/***************** Bit definition for RCC_BDCR register *****************/
		1623	#define RCC_BDCR_LSEON_Pos (0U)
		1624	#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /!< 0x00000001 /
		1625	#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /!< External Low Speed oscillator enable /
		1626	#define RCC_BDCR_LSERDY_Pos (1U)
		1627	#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /!< 0x00000002 /
		1628	#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /!< External Low Speed oscillator Ready /
		1629	#define RCC_BDCR_LSEBYP_Pos (2U)
		1630	#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /!< 0x00000004 /
		1631	#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /!< External Low Speed oscillator Bypass /
		1632
		1633	#define RCC_BDCR_RTCSEL_Pos (8U)
		1634	#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /!< 0x00000300 /
		1635	#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /!< RTCSEL[1:0] bits (RTC clock source selection) /
		1636	#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /!< 0x00000100 /
		1637	#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /!< 0x00000200 /
		1638
		1639	/!< RTC configuration /
		1640	#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /!< No clock /
		1641	#define RCC_BDCR_RTCSEL_LSE 0x00000100U /!< LSE oscillator clock used as RTC clock /
		1642	#define RCC_BDCR_RTCSEL_LSI 0x00000200U /!< LSI oscillator clock used as RTC clock /
		1643	#define RCC_BDCR_RTCSEL_HSE 0x00000300U /!< HSE oscillator clock divided by 128 used as RTC clock /
		1644
		1645	#define RCC_BDCR_RTCEN_Pos (15U)
		1646	#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /!< 0x00008000 /
		1647	#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /!< RTC clock enable /
		1648	#define RCC_BDCR_BDRST_Pos (16U)
		1649	#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /!< 0x00010000 /
		1650	#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /!< Backup domain software reset /
		1651
		1652	/***************** Bit definition for RCC_CSR register ******************/
		1653	#define RCC_CSR_LSION_Pos (0U)
		1654	#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /!< 0x00000001 /
		1655	#define RCC_CSR_LSION RCC_CSR_LSION_Msk /!< Internal Low Speed oscillator enable /
		1656	#define RCC_CSR_LSIRDY_Pos (1U)
		1657	#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /!< 0x00000002 /
		1658	#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /!< Internal Low Speed oscillator Ready /
		1659	#define RCC_CSR_RMVF_Pos (24U)
		1660	#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /!< 0x01000000 /
		1661	#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /!< Remove reset flag /
		1662	#define RCC_CSR_PINRSTF_Pos (26U)
		1663	#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /!< 0x04000000 /
		1664	#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /!< PIN reset flag /
		1665	#define RCC_CSR_PORRSTF_Pos (27U)
		1666	#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /!< 0x08000000 /
		1667	#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /!< POR/PDR reset flag /
		1668	#define RCC_CSR_SFTRSTF_Pos (28U)
		1669	#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /!< 0x10000000 /
		1670	#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /!< Software Reset flag /
		1671	#define RCC_CSR_IWDGRSTF_Pos (29U)
		1672	#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /!< 0x20000000 /
		1673	#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /!< Independent Watchdog reset flag /
		1674	#define RCC_CSR_WWDGRSTF_Pos (30U)
		1675	#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /!< 0x40000000 /
		1676	#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /!< Window watchdog reset flag /
		1677	#define RCC_CSR_LPWRRSTF_Pos (31U)
		1678	#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /!< 0x80000000 /
		1679	#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /!< Low-Power reset flag /
		1680
		1681
		1682
		1683	/******************************************************************************/
		1684	/* */
		1685	/* General Purpose and Alternate Function I/O */
		1686	/* */
		1687	/******************************************************************************/
		1688
		1689	/***************** Bit definition for GPIO_CRL register *****************/
		1690	#define GPIO_CRL_MODE_Pos (0U)
		1691	#define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /!< 0x33333333 /
		1692	#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /!< Port x mode bits /
		1693
		1694	#define GPIO_CRL_MODE0_Pos (0U)
		1695	#define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /!< 0x00000003 /
		1696	#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
		1697	#define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /!< 0x00000001 /
		1698	#define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /!< 0x00000002 /
		1699
		1700	#define GPIO_CRL_MODE1_Pos (4U)
		1701	#define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /!< 0x00000030 /
		1702	#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
		1703	#define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /!< 0x00000010 /
		1704	#define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /!< 0x00000020 /
		1705
		1706	#define GPIO_CRL_MODE2_Pos (8U)
		1707	#define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /!< 0x00000300 /
		1708	#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
		1709	#define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /!< 0x00000100 /
		1710	#define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /!< 0x00000200 /
		1711
		1712	#define GPIO_CRL_MODE3_Pos (12U)
		1713	#define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /!< 0x00003000 /
		1714	#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
		1715	#define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /!< 0x00001000 /
		1716	#define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /!< 0x00002000 /
		1717
		1718	#define GPIO_CRL_MODE4_Pos (16U)
		1719	#define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /!< 0x00030000 /
		1720	#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
		1721	#define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /!< 0x00010000 /
		1722	#define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /!< 0x00020000 /
		1723
		1724	#define GPIO_CRL_MODE5_Pos (20U)
		1725	#define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /!< 0x00300000 /
		1726	#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
		1727	#define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /!< 0x00100000 /
		1728	#define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /!< 0x00200000 /
		1729
		1730	#define GPIO_CRL_MODE6_Pos (24U)
		1731	#define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /!< 0x03000000 /
		1732	#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
		1733	#define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /!< 0x01000000 /
		1734	#define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /!< 0x02000000 /
		1735
		1736	#define GPIO_CRL_MODE7_Pos (28U)
		1737	#define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /!< 0x30000000 /
		1738	#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
		1739	#define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /!< 0x10000000 /
		1740	#define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /!< 0x20000000 /
		1741
		1742	#define GPIO_CRL_CNF_Pos (2U)
		1743	#define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /!< 0xCCCCCCCC /
		1744	#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /!< Port x configuration bits /
		1745
		1746	#define GPIO_CRL_CNF0_Pos (2U)
		1747	#define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /!< 0x0000000C /
		1748	#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
		1749	#define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /!< 0x00000004 /
		1750	#define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /!< 0x00000008 /
		1751
		1752	#define GPIO_CRL_CNF1_Pos (6U)
		1753	#define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /!< 0x000000C0 /
		1754	#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
		1755	#define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /!< 0x00000040 /
		1756	#define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /!< 0x00000080 /
		1757
		1758	#define GPIO_CRL_CNF2_Pos (10U)
		1759	#define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /!< 0x00000C00 /
		1760	#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
		1761	#define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /!< 0x00000400 /
		1762	#define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /!< 0x00000800 /
		1763
		1764	#define GPIO_CRL_CNF3_Pos (14U)
		1765	#define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /!< 0x0000C000 /
		1766	#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
		1767	#define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /!< 0x00004000 /
		1768	#define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /!< 0x00008000 /
		1769
		1770	#define GPIO_CRL_CNF4_Pos (18U)
		1771	#define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /!< 0x000C0000 /
		1772	#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
		1773	#define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /!< 0x00040000 /
		1774	#define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /!< 0x00080000 /
		1775
		1776	#define GPIO_CRL_CNF5_Pos (22U)
		1777	#define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /!< 0x00C00000 /
		1778	#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
		1779	#define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /!< 0x00400000 /
		1780	#define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /!< 0x00800000 /
		1781
		1782	#define GPIO_CRL_CNF6_Pos (26U)
		1783	#define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /!< 0x0C000000 /
		1784	#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
		1785	#define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /!< 0x04000000 /
		1786	#define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /!< 0x08000000 /
		1787
		1788	#define GPIO_CRL_CNF7_Pos (30U)
		1789	#define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /!< 0xC0000000 /
		1790	#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
		1791	#define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /!< 0x40000000 /
		1792	#define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /!< 0x80000000 /
		1793
		1794	/***************** Bit definition for GPIO_CRH register *****************/
		1795	#define GPIO_CRH_MODE_Pos (0U)
		1796	#define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /!< 0x33333333 /
		1797	#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /!< Port x mode bits /
		1798
		1799	#define GPIO_CRH_MODE8_Pos (0U)
		1800	#define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /!< 0x00000003 /
		1801	#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
		1802	#define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /!< 0x00000001 /
		1803	#define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /!< 0x00000002 /
		1804
		1805	#define GPIO_CRH_MODE9_Pos (4U)
		1806	#define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /!< 0x00000030 /
		1807	#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
		1808	#define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /!< 0x00000010 /
		1809	#define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /!< 0x00000020 /
		1810
		1811	#define GPIO_CRH_MODE10_Pos (8U)
		1812	#define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /!< 0x00000300 /
		1813	#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
		1814	#define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /!< 0x00000100 /
		1815	#define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /!< 0x00000200 /
		1816
		1817	#define GPIO_CRH_MODE11_Pos (12U)
		1818	#define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /!< 0x00003000 /
		1819	#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
		1820	#define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /!< 0x00001000 /
		1821	#define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /!< 0x00002000 /
		1822
		1823	#define GPIO_CRH_MODE12_Pos (16U)
		1824	#define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /!< 0x00030000 /
		1825	#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
		1826	#define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /!< 0x00010000 /
		1827	#define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /!< 0x00020000 /
		1828
		1829	#define GPIO_CRH_MODE13_Pos (20U)
		1830	#define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /!< 0x00300000 /
		1831	#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
		1832	#define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /!< 0x00100000 /
		1833	#define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /!< 0x00200000 /
		1834
		1835	#define GPIO_CRH_MODE14_Pos (24U)
		1836	#define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /!< 0x03000000 /
		1837	#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
		1838	#define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /!< 0x01000000 /
		1839	#define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /!< 0x02000000 /
		1840
		1841	#define GPIO_CRH_MODE15_Pos (28U)
		1842	#define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /!< 0x30000000 /
		1843	#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
		1844	#define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /!< 0x10000000 /
		1845	#define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /!< 0x20000000 /
		1846
		1847	#define GPIO_CRH_CNF_Pos (2U)
		1848	#define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /!< 0xCCCCCCCC /
		1849	#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /!< Port x configuration bits /
		1850
		1851	#define GPIO_CRH_CNF8_Pos (2U)
		1852	#define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /!< 0x0000000C /
		1853	#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
		1854	#define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /!< 0x00000004 /
		1855	#define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /!< 0x00000008 /
		1856
		1857	#define GPIO_CRH_CNF9_Pos (6U)
		1858	#define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /!< 0x000000C0 /
		1859	#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
		1860	#define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /!< 0x00000040 /
		1861	#define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /!< 0x00000080 /
		1862
		1863	#define GPIO_CRH_CNF10_Pos (10U)
		1864	#define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /!< 0x00000C00 /
		1865	#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
		1866	#define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /!< 0x00000400 /
		1867	#define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /!< 0x00000800 /
		1868
		1869	#define GPIO_CRH_CNF11_Pos (14U)
		1870	#define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /!< 0x0000C000 /
		1871	#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
		1872	#define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /!< 0x00004000 /
		1873	#define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /!< 0x00008000 /
		1874
		1875	#define GPIO_CRH_CNF12_Pos (18U)
		1876	#define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /!< 0x000C0000 /
		1877	#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
		1878	#define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /!< 0x00040000 /
		1879	#define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /!< 0x00080000 /
		1880
		1881	#define GPIO_CRH_CNF13_Pos (22U)
		1882	#define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /!< 0x00C00000 /
		1883	#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
		1884	#define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /!< 0x00400000 /
		1885	#define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /!< 0x00800000 /
		1886
		1887	#define GPIO_CRH_CNF14_Pos (26U)
		1888	#define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /!< 0x0C000000 /
		1889	#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
		1890	#define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /!< 0x04000000 /
		1891	#define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /!< 0x08000000 /
		1892
		1893	#define GPIO_CRH_CNF15_Pos (30U)
		1894	#define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /!< 0xC0000000 /
		1895	#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
		1896	#define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /!< 0x40000000 /
		1897	#define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /!< 0x80000000 /
		1898
		1899	/!<*************** Bit definition for GPIO_IDR register *****************/
		1900	#define GPIO_IDR_IDR0_Pos (0U)
		1901	#define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /!< 0x00000001 /
		1902	#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /!< Port input data, bit 0 /
		1903	#define GPIO_IDR_IDR1_Pos (1U)
		1904	#define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /!< 0x00000002 /
		1905	#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /!< Port input data, bit 1 /
		1906	#define GPIO_IDR_IDR2_Pos (2U)
		1907	#define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /!< 0x00000004 /
		1908	#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /!< Port input data, bit 2 /
		1909	#define GPIO_IDR_IDR3_Pos (3U)
		1910	#define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /!< 0x00000008 /
		1911	#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /!< Port input data, bit 3 /
		1912	#define GPIO_IDR_IDR4_Pos (4U)
		1913	#define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /!< 0x00000010 /
		1914	#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /!< Port input data, bit 4 /
		1915	#define GPIO_IDR_IDR5_Pos (5U)
		1916	#define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /!< 0x00000020 /
		1917	#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /!< Port input data, bit 5 /
		1918	#define GPIO_IDR_IDR6_Pos (6U)
		1919	#define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /!< 0x00000040 /
		1920	#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /!< Port input data, bit 6 /
		1921	#define GPIO_IDR_IDR7_Pos (7U)
		1922	#define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /!< 0x00000080 /
		1923	#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /!< Port input data, bit 7 /
		1924	#define GPIO_IDR_IDR8_Pos (8U)
		1925	#define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /!< 0x00000100 /
		1926	#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /!< Port input data, bit 8 /
		1927	#define GPIO_IDR_IDR9_Pos (9U)
		1928	#define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /!< 0x00000200 /
		1929	#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /!< Port input data, bit 9 /
		1930	#define GPIO_IDR_IDR10_Pos (10U)
		1931	#define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /!< 0x00000400 /
		1932	#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /!< Port input data, bit 10 /
		1933	#define GPIO_IDR_IDR11_Pos (11U)
		1934	#define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /!< 0x00000800 /
		1935	#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /!< Port input data, bit 11 /
		1936	#define GPIO_IDR_IDR12_Pos (12U)
		1937	#define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /!< 0x00001000 /
		1938	#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /!< Port input data, bit 12 /
		1939	#define GPIO_IDR_IDR13_Pos (13U)
		1940	#define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /!< 0x00002000 /
		1941	#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /!< Port input data, bit 13 /
		1942	#define GPIO_IDR_IDR14_Pos (14U)
		1943	#define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /!< 0x00004000 /
		1944	#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /!< Port input data, bit 14 /
		1945	#define GPIO_IDR_IDR15_Pos (15U)
		1946	#define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /!< 0x00008000 /
		1947	#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /!< Port input data, bit 15 /
		1948
		1949	/***************** Bit definition for GPIO_ODR register *****************/
		1950	#define GPIO_ODR_ODR0_Pos (0U)
		1951	#define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /!< 0x00000001 /
		1952	#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /!< Port output data, bit 0 /
		1953	#define GPIO_ODR_ODR1_Pos (1U)
		1954	#define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /!< 0x00000002 /
		1955	#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /!< Port output data, bit 1 /
		1956	#define GPIO_ODR_ODR2_Pos (2U)
		1957	#define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /!< 0x00000004 /
		1958	#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /!< Port output data, bit 2 /
		1959	#define GPIO_ODR_ODR3_Pos (3U)
		1960	#define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /!< 0x00000008 /
		1961	#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /!< Port output data, bit 3 /
		1962	#define GPIO_ODR_ODR4_Pos (4U)
		1963	#define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /!< 0x00000010 /
		1964	#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /!< Port output data, bit 4 /
		1965	#define GPIO_ODR_ODR5_Pos (5U)
		1966	#define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /!< 0x00000020 /
		1967	#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /!< Port output data, bit 5 /
		1968	#define GPIO_ODR_ODR6_Pos (6U)
		1969	#define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /!< 0x00000040 /
		1970	#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /!< Port output data, bit 6 /
		1971	#define GPIO_ODR_ODR7_Pos (7U)
		1972	#define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /!< 0x00000080 /
		1973	#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /!< Port output data, bit 7 /
		1974	#define GPIO_ODR_ODR8_Pos (8U)
		1975	#define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /!< 0x00000100 /
		1976	#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /!< Port output data, bit 8 /
		1977	#define GPIO_ODR_ODR9_Pos (9U)
		1978	#define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /!< 0x00000200 /
		1979	#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /!< Port output data, bit 9 /
		1980	#define GPIO_ODR_ODR10_Pos (10U)
		1981	#define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /!< 0x00000400 /
		1982	#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /!< Port output data, bit 10 /
		1983	#define GPIO_ODR_ODR11_Pos (11U)
		1984	#define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /!< 0x00000800 /
		1985	#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /!< Port output data, bit 11 /
		1986	#define GPIO_ODR_ODR12_Pos (12U)
		1987	#define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /!< 0x00001000 /
		1988	#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /!< Port output data, bit 12 /
		1989	#define GPIO_ODR_ODR13_Pos (13U)
		1990	#define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /!< 0x00002000 /
		1991	#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /!< Port output data, bit 13 /
		1992	#define GPIO_ODR_ODR14_Pos (14U)
		1993	#define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /!< 0x00004000 /
		1994	#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /!< Port output data, bit 14 /
		1995	#define GPIO_ODR_ODR15_Pos (15U)
		1996	#define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /!< 0x00008000 /
		1997	#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /!< Port output data, bit 15 /
		1998
		1999	/**************** Bit definition for GPIO_BSRR register *****************/
		2000	#define GPIO_BSRR_BS0_Pos (0U)
		2001	#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /!< 0x00000001 /
		2002	#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /!< Port x Set bit 0 /
		2003	#define GPIO_BSRR_BS1_Pos (1U)
		2004	#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /!< 0x00000002 /
		2005	#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /!< Port x Set bit 1 /
		2006	#define GPIO_BSRR_BS2_Pos (2U)
		2007	#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /!< 0x00000004 /
		2008	#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /!< Port x Set bit 2 /
		2009	#define GPIO_BSRR_BS3_Pos (3U)
		2010	#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /!< 0x00000008 /
		2011	#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /!< Port x Set bit 3 /
		2012	#define GPIO_BSRR_BS4_Pos (4U)
		2013	#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /!< 0x00000010 /
		2014	#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /!< Port x Set bit 4 /
		2015	#define GPIO_BSRR_BS5_Pos (5U)
		2016	#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /!< 0x00000020 /
		2017	#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /!< Port x Set bit 5 /
		2018	#define GPIO_BSRR_BS6_Pos (6U)
		2019	#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /!< 0x00000040 /
		2020	#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /!< Port x Set bit 6 /
		2021	#define GPIO_BSRR_BS7_Pos (7U)
		2022	#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /!< 0x00000080 /
		2023	#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /!< Port x Set bit 7 /
		2024	#define GPIO_BSRR_BS8_Pos (8U)
		2025	#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /!< 0x00000100 /
		2026	#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /!< Port x Set bit 8 /
		2027	#define GPIO_BSRR_BS9_Pos (9U)
		2028	#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /!< 0x00000200 /
		2029	#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /!< Port x Set bit 9 /
		2030	#define GPIO_BSRR_BS10_Pos (10U)
		2031	#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /!< 0x00000400 /
		2032	#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /!< Port x Set bit 10 /
		2033	#define GPIO_BSRR_BS11_Pos (11U)
		2034	#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /!< 0x00000800 /
		2035	#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /!< Port x Set bit 11 /
		2036	#define GPIO_BSRR_BS12_Pos (12U)
		2037	#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /!< 0x00001000 /
		2038	#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /!< Port x Set bit 12 /
		2039	#define GPIO_BSRR_BS13_Pos (13U)
		2040	#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /!< 0x00002000 /
		2041	#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /!< Port x Set bit 13 /
		2042	#define GPIO_BSRR_BS14_Pos (14U)
		2043	#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /!< 0x00004000 /
		2044	#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /!< Port x Set bit 14 /
		2045	#define GPIO_BSRR_BS15_Pos (15U)
		2046	#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /!< 0x00008000 /
		2047	#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /!< Port x Set bit 15 /
		2048
		2049	#define GPIO_BSRR_BR0_Pos (16U)
		2050	#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /!< 0x00010000 /
		2051	#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /!< Port x Reset bit 0 /
		2052	#define GPIO_BSRR_BR1_Pos (17U)
		2053	#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /!< 0x00020000 /
		2054	#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /!< Port x Reset bit 1 /
		2055	#define GPIO_BSRR_BR2_Pos (18U)
		2056	#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /!< 0x00040000 /
		2057	#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /!< Port x Reset bit 2 /
		2058	#define GPIO_BSRR_BR3_Pos (19U)
		2059	#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /!< 0x00080000 /
		2060	#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /!< Port x Reset bit 3 /
		2061	#define GPIO_BSRR_BR4_Pos (20U)
		2062	#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /!< 0x00100000 /
		2063	#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /!< Port x Reset bit 4 /
		2064	#define GPIO_BSRR_BR5_Pos (21U)
		2065	#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /!< 0x00200000 /
		2066	#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /!< Port x Reset bit 5 /
		2067	#define GPIO_BSRR_BR6_Pos (22U)
		2068	#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /!< 0x00400000 /
		2069	#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /!< Port x Reset bit 6 /
		2070	#define GPIO_BSRR_BR7_Pos (23U)
		2071	#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /!< 0x00800000 /
		2072	#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /!< Port x Reset bit 7 /
		2073	#define GPIO_BSRR_BR8_Pos (24U)
		2074	#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /!< 0x01000000 /
		2075	#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /!< Port x Reset bit 8 /
		2076	#define GPIO_BSRR_BR9_Pos (25U)
		2077	#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /!< 0x02000000 /
		2078	#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /!< Port x Reset bit 9 /
		2079	#define GPIO_BSRR_BR10_Pos (26U)
		2080	#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /!< 0x04000000 /
		2081	#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /!< Port x Reset bit 10 /
		2082	#define GPIO_BSRR_BR11_Pos (27U)
		2083	#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /!< 0x08000000 /
		2084	#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /!< Port x Reset bit 11 /
		2085	#define GPIO_BSRR_BR12_Pos (28U)
		2086	#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /!< 0x10000000 /
		2087	#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /!< Port x Reset bit 12 /
		2088	#define GPIO_BSRR_BR13_Pos (29U)
		2089	#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /!< 0x20000000 /
		2090	#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /!< Port x Reset bit 13 /
		2091	#define GPIO_BSRR_BR14_Pos (30U)
		2092	#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /!< 0x40000000 /
		2093	#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /!< Port x Reset bit 14 /
		2094	#define GPIO_BSRR_BR15_Pos (31U)
		2095	#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /!< 0x80000000 /
		2096	#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /!< Port x Reset bit 15 /
		2097
		2098	/***************** Bit definition for GPIO_BRR register *****************/
		2099	#define GPIO_BRR_BR0_Pos (0U)
		2100	#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /!< 0x00000001 /
		2101	#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /!< Port x Reset bit 0 /
		2102	#define GPIO_BRR_BR1_Pos (1U)
		2103	#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /!< 0x00000002 /
		2104	#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /!< Port x Reset bit 1 /
		2105	#define GPIO_BRR_BR2_Pos (2U)
		2106	#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /!< 0x00000004 /
		2107	#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /!< Port x Reset bit 2 /
		2108	#define GPIO_BRR_BR3_Pos (3U)
		2109	#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /!< 0x00000008 /
		2110	#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /!< Port x Reset bit 3 /
		2111	#define GPIO_BRR_BR4_Pos (4U)
		2112	#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /!< 0x00000010 /
		2113	#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /!< Port x Reset bit 4 /
		2114	#define GPIO_BRR_BR5_Pos (5U)
		2115	#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /!< 0x00000020 /
		2116	#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /!< Port x Reset bit 5 /
		2117	#define GPIO_BRR_BR6_Pos (6U)
		2118	#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /!< 0x00000040 /
		2119	#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /!< Port x Reset bit 6 /
		2120	#define GPIO_BRR_BR7_Pos (7U)
		2121	#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /!< 0x00000080 /
		2122	#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /!< Port x Reset bit 7 /
		2123	#define GPIO_BRR_BR8_Pos (8U)
		2124	#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /!< 0x00000100 /
		2125	#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /!< Port x Reset bit 8 /
		2126	#define GPIO_BRR_BR9_Pos (9U)
		2127	#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /!< 0x00000200 /
		2128	#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /!< Port x Reset bit 9 /
		2129	#define GPIO_BRR_BR10_Pos (10U)
		2130	#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /!< 0x00000400 /
		2131	#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /!< Port x Reset bit 10 /
		2132	#define GPIO_BRR_BR11_Pos (11U)
		2133	#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /!< 0x00000800 /
		2134	#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /!< Port x Reset bit 11 /
		2135	#define GPIO_BRR_BR12_Pos (12U)
		2136	#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /!< 0x00001000 /
		2137	#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /!< Port x Reset bit 12 /
		2138	#define GPIO_BRR_BR13_Pos (13U)
		2139	#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /!< 0x00002000 /
		2140	#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /!< Port x Reset bit 13 /
		2141	#define GPIO_BRR_BR14_Pos (14U)
		2142	#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /!< 0x00004000 /
		2143	#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /!< Port x Reset bit 14 /
		2144	#define GPIO_BRR_BR15_Pos (15U)
		2145	#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /!< 0x00008000 /
		2146	#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /!< Port x Reset bit 15 /
		2147
		2148	/**************** Bit definition for GPIO_LCKR register *****************/
		2149	#define GPIO_LCKR_LCK0_Pos (0U)
		2150	#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /!< 0x00000001 /
		2151	#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /!< Port x Lock bit 0 /
		2152	#define GPIO_LCKR_LCK1_Pos (1U)
		2153	#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /!< 0x00000002 /
		2154	#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /!< Port x Lock bit 1 /
		2155	#define GPIO_LCKR_LCK2_Pos (2U)
		2156	#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /!< 0x00000004 /
		2157	#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /!< Port x Lock bit 2 /
		2158	#define GPIO_LCKR_LCK3_Pos (3U)
		2159	#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /!< 0x00000008 /
		2160	#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /!< Port x Lock bit 3 /
		2161	#define GPIO_LCKR_LCK4_Pos (4U)
		2162	#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /!< 0x00000010 /
		2163	#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /!< Port x Lock bit 4 /
		2164	#define GPIO_LCKR_LCK5_Pos (5U)
		2165	#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /!< 0x00000020 /
		2166	#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /!< Port x Lock bit 5 /
		2167	#define GPIO_LCKR_LCK6_Pos (6U)
		2168	#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /!< 0x00000040 /
		2169	#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /!< Port x Lock bit 6 /
		2170	#define GPIO_LCKR_LCK7_Pos (7U)
		2171	#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /!< 0x00000080 /
		2172	#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /!< Port x Lock bit 7 /
		2173	#define GPIO_LCKR_LCK8_Pos (8U)
		2174	#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /!< 0x00000100 /
		2175	#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /!< Port x Lock bit 8 /
		2176	#define GPIO_LCKR_LCK9_Pos (9U)
		2177	#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /!< 0x00000200 /
		2178	#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /!< Port x Lock bit 9 /
		2179	#define GPIO_LCKR_LCK10_Pos (10U)
		2180	#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /!< 0x00000400 /
		2181	#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /!< Port x Lock bit 10 /
		2182	#define GPIO_LCKR_LCK11_Pos (11U)
		2183	#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /!< 0x00000800 /
		2184	#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /!< Port x Lock bit 11 /
		2185	#define GPIO_LCKR_LCK12_Pos (12U)
		2186	#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /!< 0x00001000 /
		2187	#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /!< Port x Lock bit 12 /
		2188	#define GPIO_LCKR_LCK13_Pos (13U)
		2189	#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /!< 0x00002000 /
		2190	#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /!< Port x Lock bit 13 /
		2191	#define GPIO_LCKR_LCK14_Pos (14U)
		2192	#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /!< 0x00004000 /
		2193	#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /!< Port x Lock bit 14 /
		2194	#define GPIO_LCKR_LCK15_Pos (15U)
		2195	#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /!< 0x00008000 /
		2196	#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /!< Port x Lock bit 15 /
		2197	#define GPIO_LCKR_LCKK_Pos (16U)
		2198	#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /!< 0x00010000 /
		2199	#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /!< Lock key /
		2200
		2201	/----------------------------------------------------------------------------/
		2202
		2203	/**************** Bit definition for AFIO_EVCR register *****************/
		2204	#define AFIO_EVCR_PIN_Pos (0U)
		2205	#define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /!< 0x0000000F /
		2206	#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /!< PIN[3:0] bits (Pin selection) /
		2207	#define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /!< 0x00000001 /
		2208	#define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /!< 0x00000002 /
		2209	#define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /!< 0x00000004 /
		2210	#define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /!< 0x00000008 /
		2211
		2212	/!< PIN configuration /
		2213	#define AFIO_EVCR_PIN_PX0 0x00000000U /!< Pin 0 selected /
		2214	#define AFIO_EVCR_PIN_PX1_Pos (0U)
		2215	#define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /!< 0x00000001 /
		2216	#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /!< Pin 1 selected /
		2217	#define AFIO_EVCR_PIN_PX2_Pos (1U)
		2218	#define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /!< 0x00000002 /
		2219	#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /!< Pin 2 selected /
		2220	#define AFIO_EVCR_PIN_PX3_Pos (0U)
		2221	#define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /!< 0x00000003 /
		2222	#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /!< Pin 3 selected /
		2223	#define AFIO_EVCR_PIN_PX4_Pos (2U)
		2224	#define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /!< 0x00000004 /
		2225	#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /!< Pin 4 selected /
		2226	#define AFIO_EVCR_PIN_PX5_Pos (0U)
		2227	#define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /!< 0x00000005 /
		2228	#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /!< Pin 5 selected /
		2229	#define AFIO_EVCR_PIN_PX6_Pos (1U)
		2230	#define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /!< 0x00000006 /
		2231	#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /!< Pin 6 selected /
		2232	#define AFIO_EVCR_PIN_PX7_Pos (0U)
		2233	#define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /!< 0x00000007 /
		2234	#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /!< Pin 7 selected /
		2235	#define AFIO_EVCR_PIN_PX8_Pos (3U)
		2236	#define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /!< 0x00000008 /
		2237	#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /!< Pin 8 selected /
		2238	#define AFIO_EVCR_PIN_PX9_Pos (0U)
		2239	#define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /!< 0x00000009 /
		2240	#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /!< Pin 9 selected /
		2241	#define AFIO_EVCR_PIN_PX10_Pos (1U)
		2242	#define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /!< 0x0000000A /
		2243	#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /!< Pin 10 selected /
		2244	#define AFIO_EVCR_PIN_PX11_Pos (0U)
		2245	#define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /!< 0x0000000B /
		2246	#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /!< Pin 11 selected /
		2247	#define AFIO_EVCR_PIN_PX12_Pos (2U)
		2248	#define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /!< 0x0000000C /
		2249	#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /!< Pin 12 selected /
		2250	#define AFIO_EVCR_PIN_PX13_Pos (0U)
		2251	#define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /!< 0x0000000D /
		2252	#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /!< Pin 13 selected /
		2253	#define AFIO_EVCR_PIN_PX14_Pos (1U)
		2254	#define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /!< 0x0000000E /
		2255	#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /!< Pin 14 selected /
		2256	#define AFIO_EVCR_PIN_PX15_Pos (0U)
		2257	#define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /!< 0x0000000F /
		2258	#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /!< Pin 15 selected /
		2259
		2260	#define AFIO_EVCR_PORT_Pos (4U)
		2261	#define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /!< 0x00000070 /
		2262	#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /!< PORT[2:0] bits (Port selection) /
		2263	#define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /!< 0x00000010 /
		2264	#define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /!< 0x00000020 /
		2265	#define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /!< 0x00000040 /
		2266
		2267	/!< PORT configuration /
		2268	#define AFIO_EVCR_PORT_PA 0x00000000 /!< Port A selected /
		2269	#define AFIO_EVCR_PORT_PB_Pos (4U)
		2270	#define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /!< 0x00000010 /
		2271	#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /!< Port B selected /
		2272	#define AFIO_EVCR_PORT_PC_Pos (5U)
		2273	#define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /!< 0x00000020 /
		2274	#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /!< Port C selected /
		2275	#define AFIO_EVCR_PORT_PD_Pos (4U)
		2276	#define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /!< 0x00000030 /
		2277	#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /!< Port D selected /
		2278	#define AFIO_EVCR_PORT_PE_Pos (6U)
		2279	#define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /!< 0x00000040 /
		2280	#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /!< Port E selected /
		2281
		2282	#define AFIO_EVCR_EVOE_Pos (7U)
		2283	#define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /!< 0x00000080 /
		2284	#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /!< Event Output Enable /
		2285
		2286	/**************** Bit definition for AFIO_MAPR register *****************/
		2287	#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
		2288	#define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /!< 0x00000001 /
		2289	#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /!< SPI1 remapping /
		2290	#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
		2291	#define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /!< 0x00000002 /
		2292	#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /!< I2C1 remapping /
		2293	#define AFIO_MAPR_USART1_REMAP_Pos (2U)
		2294	#define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /!< 0x00000004 /
		2295	#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /!< USART1 remapping /
		2296	#define AFIO_MAPR_USART2_REMAP_Pos (3U)
		2297	#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /!< 0x00000008 /
		2298	#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /!< USART2 remapping /
		2299
		2300	#define AFIO_MAPR_USART3_REMAP_Pos (4U)
		2301	#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000030 /
		2302	#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /!< USART3_REMAP[1:0] bits (USART3 remapping) /
		2303	#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000010 /
		2304	#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000020 /
		2305
		2306	/* USART3_REMAP configuration */
		2307	#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
		2308	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
		2309	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /!< 0x00000010 /
		2310	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
		2311	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
		2312	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /!< 0x00000030 /
		2313	#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
		2314
		2315	#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
		2316	#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x000000C0 /
		2317	#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
		2318	#define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000040 /
		2319	#define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000080 /
		2320
		2321	/!< TIM1_REMAP configuration /
		2322	#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
		2323	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
		2324	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /!< 0x00000040 /
		2325	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
		2326	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
		2327	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /!< 0x000000C0 /
		2328	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
		2329
		2330	#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
		2331	#define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000300 /
		2332	#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
		2333	#define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000100 /
		2334	#define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000200 /
		2335
		2336	/!< TIM2_REMAP configuration /
		2337	#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
		2338	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
		2339	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /!< 0x00000100 /
		2340	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
		2341	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
		2342	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /!< 0x00000200 /
		2343	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
		2344	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
		2345	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /!< 0x00000300 /
		2346	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
		2347
		2348	#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
		2349	#define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000C00 /
		2350	#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
		2351	#define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000400 /
		2352	#define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000800 /
		2353
		2354	/!< TIM3_REMAP configuration /
		2355	#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
		2356	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
		2357	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /!< 0x00000800 /
		2358	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
		2359	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
		2360	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /!< 0x00000C00 /
		2361	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
		2362
		2363	#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
		2364	#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /!< 0x00001000 /
		2365	#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /!< TIM4_REMAP bit (TIM4 remapping) /
		2366
		2367
		2368	#define AFIO_MAPR_PD01_REMAP_Pos (15U)
		2369	#define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /!< 0x00008000 /
		2370	#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
		2371	#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
		2372	#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /!< 0x00010000 /
		2373	#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /!< TIM5 Channel4 Internal Remap /
		2374
		2375	/!< SWJ_CFG configuration /
		2376	#define AFIO_MAPR_SWJ_CFG_Pos (24U)
		2377	#define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x07000000 /
		2378	#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
		2379	#define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x01000000 /
		2380	#define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x02000000 /
		2381	#define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x04000000 /
		2382
		2383	#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
		2384	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
		2385	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /!< 0x01000000 /
		2386	#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
		2387	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
		2388	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /!< 0x02000000 /
		2389	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /!< JTAG-DP Disabled and SW-DP Enabled /
		2390	#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
		2391	#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /!< 0x04000000 /
		2392	#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /!< JTAG-DP Disabled and SW-DP Disabled /
		2393
		2394
		2395	/*************** Bit definition for AFIO_EXTICR1 register ***************/
		2396	#define AFIO_EXTICR1_EXTI0_Pos (0U)
		2397	#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /!< 0x0000000F /
		2398	#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /!< EXTI 0 configuration /
		2399	#define AFIO_EXTICR1_EXTI1_Pos (4U)
		2400	#define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /!< 0x000000F0 /
		2401	#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /!< EXTI 1 configuration /
		2402	#define AFIO_EXTICR1_EXTI2_Pos (8U)
		2403	#define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /!< 0x00000F00 /
		2404	#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /!< EXTI 2 configuration /
		2405	#define AFIO_EXTICR1_EXTI3_Pos (12U)
		2406	#define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /!< 0x0000F000 /
		2407	#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /!< EXTI 3 configuration /
		2408
		2409	/!< EXTI0 configuration /
		2410	#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /!< PA[0] pin /
		2411	#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
		2412	#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /!< 0x00000001 /
		2413	#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /!< PB[0] pin /
		2414	#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
		2415	#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /!< 0x00000002 /
		2416	#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /!< PC[0] pin /
		2417	#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
		2418	#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /!< 0x00000003 /
		2419	#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /!< PD[0] pin /
		2420	#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
		2421	#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /!< 0x00000004 /
		2422	#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /!< PE[0] pin /
		2423	#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
		2424	#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /!< 0x00000005 /
		2425	#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /!< PF[0] pin /
		2426	#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
		2427	#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /!< 0x00000006 /
		2428	#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /!< PG[0] pin /
		2429
		2430	/!< EXTI1 configuration /
		2431	#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /!< PA[1] pin /
		2432	#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
		2433	#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /!< 0x00000010 /
		2434	#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /!< PB[1] pin /
		2435	#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
		2436	#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /!< 0x00000020 /
		2437	#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /!< PC[1] pin /
		2438	#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
		2439	#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /!< 0x00000030 /
		2440	#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /!< PD[1] pin /
		2441	#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
		2442	#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /!< 0x00000040 /
		2443	#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /!< PE[1] pin /
		2444	#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
		2445	#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /!< 0x00000050 /
		2446	#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /!< PF[1] pin /
		2447	#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
		2448	#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /!< 0x00000060 /
		2449	#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /!< PG[1] pin /
		2450
		2451	/!< EXTI2 configuration /
		2452	#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /!< PA[2] pin /
		2453	#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
		2454	#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /!< 0x00000100 /
		2455	#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /!< PB[2] pin /
		2456	#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
		2457	#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /!< 0x00000200 /
		2458	#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /!< PC[2] pin /
		2459	#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
		2460	#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /!< 0x00000300 /
		2461	#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /!< PD[2] pin /
		2462	#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
		2463	#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /!< 0x00000400 /
		2464	#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /!< PE[2] pin /
		2465	#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
		2466	#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /!< 0x00000500 /
		2467	#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /!< PF[2] pin /
		2468	#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
		2469	#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /!< 0x00000600 /
		2470	#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /!< PG[2] pin /
		2471
		2472	/!< EXTI3 configuration /
		2473	#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /!< PA[3] pin /
		2474	#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
		2475	#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /!< 0x00001000 /
		2476	#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /!< PB[3] pin /
		2477	#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
		2478	#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /!< 0x00002000 /
		2479	#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /!< PC[3] pin /
		2480	#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
		2481	#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /!< 0x00003000 /
		2482	#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /!< PD[3] pin /
		2483	#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
		2484	#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /!< 0x00004000 /
		2485	#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /!< PE[3] pin /
		2486	#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
		2487	#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /!< 0x00005000 /
		2488	#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /!< PF[3] pin /
		2489	#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
		2490	#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /!< 0x00006000 /
		2491	#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /!< PG[3] pin /
		2492
		2493	/*************** Bit definition for AFIO_EXTICR2 register ***************/
		2494	#define AFIO_EXTICR2_EXTI4_Pos (0U)
		2495	#define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /!< 0x0000000F /
		2496	#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /!< EXTI 4 configuration /
		2497	#define AFIO_EXTICR2_EXTI5_Pos (4U)
		2498	#define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /!< 0x000000F0 /
		2499	#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /!< EXTI 5 configuration /
		2500	#define AFIO_EXTICR2_EXTI6_Pos (8U)
		2501	#define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /!< 0x00000F00 /
		2502	#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /!< EXTI 6 configuration /
		2503	#define AFIO_EXTICR2_EXTI7_Pos (12U)
		2504	#define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /!< 0x0000F000 /
		2505	#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /!< EXTI 7 configuration /
		2506
		2507	/!< EXTI4 configuration /
		2508	#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /!< PA[4] pin /
		2509	#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
		2510	#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /!< 0x00000001 /
		2511	#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /!< PB[4] pin /
		2512	#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
		2513	#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /!< 0x00000002 /
		2514	#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /!< PC[4] pin /
		2515	#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
		2516	#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /!< 0x00000003 /
		2517	#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /!< PD[4] pin /
		2518	#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
		2519	#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /!< 0x00000004 /
		2520	#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /!< PE[4] pin /
		2521	#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
		2522	#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /!< 0x00000005 /
		2523	#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /!< PF[4] pin /
		2524	#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
		2525	#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /!< 0x00000006 /
		2526	#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /!< PG[4] pin /
		2527
		2528	/* EXTI5 configuration */
		2529	#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /!< PA[5] pin /
		2530	#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
		2531	#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /!< 0x00000010 /
		2532	#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /!< PB[5] pin /
		2533	#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
		2534	#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /!< 0x00000020 /
		2535	#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /!< PC[5] pin /
		2536	#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
		2537	#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /!< 0x00000030 /
		2538	#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /!< PD[5] pin /
		2539	#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
		2540	#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /!< 0x00000040 /
		2541	#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /!< PE[5] pin /
		2542	#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
		2543	#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /!< 0x00000050 /
		2544	#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /!< PF[5] pin /
		2545	#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
		2546	#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /!< 0x00000060 /
		2547	#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /!< PG[5] pin /
		2548
		2549	/!< EXTI6 configuration /
		2550	#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /!< PA[6] pin /
		2551	#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
		2552	#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /!< 0x00000100 /
		2553	#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /!< PB[6] pin /
		2554	#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
		2555	#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /!< 0x00000200 /
		2556	#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /!< PC[6] pin /
		2557	#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
		2558	#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /!< 0x00000300 /
		2559	#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /!< PD[6] pin /
		2560	#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
		2561	#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /!< 0x00000400 /
		2562	#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /!< PE[6] pin /
		2563	#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
		2564	#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /!< 0x00000500 /
		2565	#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /!< PF[6] pin /
		2566	#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
		2567	#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /!< 0x00000600 /
		2568	#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /!< PG[6] pin /
		2569
		2570	/!< EXTI7 configuration /
		2571	#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /!< PA[7] pin /
		2572	#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
		2573	#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /!< 0x00001000 /
		2574	#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /!< PB[7] pin /
		2575	#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
		2576	#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /!< 0x00002000 /
		2577	#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /!< PC[7] pin /
		2578	#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
		2579	#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /!< 0x00003000 /
		2580	#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /!< PD[7] pin /
		2581	#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
		2582	#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /!< 0x00004000 /
		2583	#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /!< PE[7] pin /
		2584	#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
		2585	#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /!< 0x00005000 /
		2586	#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /!< PF[7] pin /
		2587	#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
		2588	#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /!< 0x00006000 /
		2589	#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /!< PG[7] pin /
		2590
		2591	/*************** Bit definition for AFIO_EXTICR3 register ***************/
		2592	#define AFIO_EXTICR3_EXTI8_Pos (0U)
		2593	#define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /!< 0x0000000F /
		2594	#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /!< EXTI 8 configuration /
		2595	#define AFIO_EXTICR3_EXTI9_Pos (4U)
		2596	#define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /!< 0x000000F0 /
		2597	#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /!< EXTI 9 configuration /
		2598	#define AFIO_EXTICR3_EXTI10_Pos (8U)
		2599	#define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /!< 0x00000F00 /
		2600	#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /!< EXTI 10 configuration /
		2601	#define AFIO_EXTICR3_EXTI11_Pos (12U)
		2602	#define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /!< 0x0000F000 /
		2603	#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /!< EXTI 11 configuration /
		2604
		2605	/!< EXTI8 configuration /
		2606	#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /!< PA[8] pin /
		2607	#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
		2608	#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /!< 0x00000001 /
		2609	#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /!< PB[8] pin /
		2610	#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
		2611	#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /!< 0x00000002 /
		2612	#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /!< PC[8] pin /
		2613	#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
		2614	#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /!< 0x00000003 /
		2615	#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /!< PD[8] pin /
		2616	#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
		2617	#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /!< 0x00000004 /
		2618	#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /!< PE[8] pin /
		2619	#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
		2620	#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /!< 0x00000005 /
		2621	#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /!< PF[8] pin /
		2622	#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
		2623	#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /!< 0x00000006 /
		2624	#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /!< PG[8] pin /
		2625
		2626	/!< EXTI9 configuration /
		2627	#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /!< PA[9] pin /
		2628	#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
		2629	#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /!< 0x00000010 /
		2630	#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /!< PB[9] pin /
		2631	#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
		2632	#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /!< 0x00000020 /
		2633	#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /!< PC[9] pin /
		2634	#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
		2635	#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /!< 0x00000030 /
		2636	#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /!< PD[9] pin /
		2637	#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
		2638	#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /!< 0x00000040 /
		2639	#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /!< PE[9] pin /
		2640	#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
		2641	#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /!< 0x00000050 /
		2642	#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /!< PF[9] pin /
		2643	#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
		2644	#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /!< 0x00000060 /
		2645	#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /!< PG[9] pin /
		2646
		2647	/!< EXTI10 configuration /
		2648	#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /!< PA[10] pin /
		2649	#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
		2650	#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /!< 0x00000100 /
		2651	#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /!< PB[10] pin /
		2652	#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
		2653	#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /!< 0x00000200 /
		2654	#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /!< PC[10] pin /
		2655	#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
		2656	#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /!< 0x00000300 /
		2657	#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /!< PD[10] pin /
		2658	#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
		2659	#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /!< 0x00000400 /
		2660	#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /!< PE[10] pin /
		2661	#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
		2662	#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /!< 0x00000500 /
		2663	#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /!< PF[10] pin /
		2664	#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
		2665	#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /!< 0x00000600 /
		2666	#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /!< PG[10] pin /
		2667
		2668	/!< EXTI11 configuration /
		2669	#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /!< PA[11] pin /
		2670	#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
		2671	#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /!< 0x00001000 /
		2672	#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /!< PB[11] pin /
		2673	#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
		2674	#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /!< 0x00002000 /
		2675	#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /!< PC[11] pin /
		2676	#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
		2677	#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /!< 0x00003000 /
		2678	#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /!< PD[11] pin /
		2679	#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
		2680	#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /!< 0x00004000 /
		2681	#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /!< PE[11] pin /
		2682	#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
		2683	#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /!< 0x00005000 /
		2684	#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /!< PF[11] pin /
		2685	#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
		2686	#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /!< 0x00006000 /
		2687	#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /!< PG[11] pin /
		2688
		2689	/*************** Bit definition for AFIO_EXTICR4 register ***************/
		2690	#define AFIO_EXTICR4_EXTI12_Pos (0U)
		2691	#define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /!< 0x0000000F /
		2692	#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /!< EXTI 12 configuration /
		2693	#define AFIO_EXTICR4_EXTI13_Pos (4U)
		2694	#define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /!< 0x000000F0 /
		2695	#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /!< EXTI 13 configuration /
		2696	#define AFIO_EXTICR4_EXTI14_Pos (8U)
		2697	#define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /!< 0x00000F00 /
		2698	#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /!< EXTI 14 configuration /
		2699	#define AFIO_EXTICR4_EXTI15_Pos (12U)
		2700	#define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /!< 0x0000F000 /
		2701	#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /!< EXTI 15 configuration /
		2702
		2703	/* EXTI12 configuration */
		2704	#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /!< PA[12] pin /
		2705	#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
		2706	#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /!< 0x00000001 /
		2707	#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /!< PB[12] pin /
		2708	#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
		2709	#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /!< 0x00000002 /
		2710	#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /!< PC[12] pin /
		2711	#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
		2712	#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /!< 0x00000003 /
		2713	#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /!< PD[12] pin /
		2714	#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
		2715	#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /!< 0x00000004 /
		2716	#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /!< PE[12] pin /
		2717	#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
		2718	#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /!< 0x00000005 /
		2719	#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /!< PF[12] pin /
		2720	#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
		2721	#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /!< 0x00000006 /
		2722	#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /!< PG[12] pin /
		2723
		2724	/* EXTI13 configuration */
		2725	#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /!< PA[13] pin /
		2726	#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
		2727	#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /!< 0x00000010 /
		2728	#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /!< PB[13] pin /
		2729	#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
		2730	#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /!< 0x00000020 /
		2731	#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /!< PC[13] pin /
		2732	#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
		2733	#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /!< 0x00000030 /
		2734	#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /!< PD[13] pin /
		2735	#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
		2736	#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /!< 0x00000040 /
		2737	#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /!< PE[13] pin /
		2738	#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
		2739	#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /!< 0x00000050 /
		2740	#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /!< PF[13] pin /
		2741	#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
		2742	#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /!< 0x00000060 /
		2743	#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /!< PG[13] pin /
		2744
		2745	/!< EXTI14 configuration /
		2746	#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /!< PA[14] pin /
		2747	#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
		2748	#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /!< 0x00000100 /
		2749	#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /!< PB[14] pin /
		2750	#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
		2751	#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /!< 0x00000200 /
		2752	#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /!< PC[14] pin /
		2753	#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
		2754	#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /!< 0x00000300 /
		2755	#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /!< PD[14] pin /
		2756	#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
		2757	#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /!< 0x00000400 /
		2758	#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /!< PE[14] pin /
		2759	#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
		2760	#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /!< 0x00000500 /
		2761	#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /!< PF[14] pin /
		2762	#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
		2763	#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /!< 0x00000600 /
		2764	#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /!< PG[14] pin /
		2765
		2766	/!< EXTI15 configuration /
		2767	#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /!< PA[15] pin /
		2768	#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
		2769	#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /!< 0x00001000 /
		2770	#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /!< PB[15] pin /
		2771	#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
		2772	#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /!< 0x00002000 /
		2773	#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /!< PC[15] pin /
		2774	#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
		2775	#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /!< 0x00003000 /
		2776	#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /!< PD[15] pin /
		2777	#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
		2778	#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /!< 0x00004000 /
		2779	#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /!< PE[15] pin /
		2780	#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
		2781	#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /!< 0x00005000 /
		2782	#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /!< PF[15] pin /
		2783	#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
		2784	#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /!< 0x00006000 /
		2785	#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /!< PG[15] pin /
		2786
		2787	/**************** Bit definition for AFIO_MAPR2 register ****************/
		2788
		2789
		2790	#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U)
		2791	#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1UL << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /!< 0x00000400 /
		2792	#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /!< FSMC NADV remapping /
		2793
		2794	/******************************************************************************/
		2795	/* */
		2796	/* External Interrupt/Event Controller */
		2797	/* */
		2798	/******************************************************************************/
		2799
		2800	/***************** Bit definition for EXTI_IMR register *****************/
		2801	#define EXTI_IMR_MR0_Pos (0U)
		2802	#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /!< 0x00000001 /
		2803	#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /!< Interrupt Mask on line 0 /
		2804	#define EXTI_IMR_MR1_Pos (1U)
		2805	#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /!< 0x00000002 /
		2806	#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /!< Interrupt Mask on line 1 /
		2807	#define EXTI_IMR_MR2_Pos (2U)
		2808	#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /!< 0x00000004 /
		2809	#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /!< Interrupt Mask on line 2 /
		2810	#define EXTI_IMR_MR3_Pos (3U)
		2811	#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /!< 0x00000008 /
		2812	#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /!< Interrupt Mask on line 3 /
		2813	#define EXTI_IMR_MR4_Pos (4U)
		2814	#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /!< 0x00000010 /
		2815	#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /!< Interrupt Mask on line 4 /
		2816	#define EXTI_IMR_MR5_Pos (5U)
		2817	#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /!< 0x00000020 /
		2818	#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /!< Interrupt Mask on line 5 /
		2819	#define EXTI_IMR_MR6_Pos (6U)
		2820	#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /!< 0x00000040 /
		2821	#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /!< Interrupt Mask on line 6 /
		2822	#define EXTI_IMR_MR7_Pos (7U)
		2823	#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /!< 0x00000080 /
		2824	#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /!< Interrupt Mask on line 7 /
		2825	#define EXTI_IMR_MR8_Pos (8U)
		2826	#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /!< 0x00000100 /
		2827	#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /!< Interrupt Mask on line 8 /
		2828	#define EXTI_IMR_MR9_Pos (9U)
		2829	#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /!< 0x00000200 /
		2830	#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /!< Interrupt Mask on line 9 /
		2831	#define EXTI_IMR_MR10_Pos (10U)
		2832	#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /!< 0x00000400 /
		2833	#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /!< Interrupt Mask on line 10 /
		2834	#define EXTI_IMR_MR11_Pos (11U)
		2835	#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /!< 0x00000800 /
		2836	#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /!< Interrupt Mask on line 11 /
		2837	#define EXTI_IMR_MR12_Pos (12U)
		2838	#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /!< 0x00001000 /
		2839	#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /!< Interrupt Mask on line 12 /
		2840	#define EXTI_IMR_MR13_Pos (13U)
		2841	#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /!< 0x00002000 /
		2842	#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /!< Interrupt Mask on line 13 /
		2843	#define EXTI_IMR_MR14_Pos (14U)
		2844	#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /!< 0x00004000 /
		2845	#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /!< Interrupt Mask on line 14 /
		2846	#define EXTI_IMR_MR15_Pos (15U)
		2847	#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /!< 0x00008000 /
		2848	#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /!< Interrupt Mask on line 15 /
		2849	#define EXTI_IMR_MR16_Pos (16U)
		2850	#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /!< 0x00010000 /
		2851	#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /!< Interrupt Mask on line 16 /
		2852	#define EXTI_IMR_MR17_Pos (17U)
		2853	#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /!< 0x00020000 /
		2854	#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /!< Interrupt Mask on line 17 /
		2855	#define EXTI_IMR_MR18_Pos (18U)
		2856	#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /!< 0x00040000 /
		2857	#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /!< Interrupt Mask on line 18 /
		2858
		2859	/* References Defines */
		2860	#define EXTI_IMR_IM0 EXTI_IMR_MR0
		2861	#define EXTI_IMR_IM1 EXTI_IMR_MR1
		2862	#define EXTI_IMR_IM2 EXTI_IMR_MR2
		2863	#define EXTI_IMR_IM3 EXTI_IMR_MR3
		2864	#define EXTI_IMR_IM4 EXTI_IMR_MR4
		2865	#define EXTI_IMR_IM5 EXTI_IMR_MR5
		2866	#define EXTI_IMR_IM6 EXTI_IMR_MR6
		2867	#define EXTI_IMR_IM7 EXTI_IMR_MR7
		2868	#define EXTI_IMR_IM8 EXTI_IMR_MR8
		2869	#define EXTI_IMR_IM9 EXTI_IMR_MR9
		2870	#define EXTI_IMR_IM10 EXTI_IMR_MR10
		2871	#define EXTI_IMR_IM11 EXTI_IMR_MR11
		2872	#define EXTI_IMR_IM12 EXTI_IMR_MR12
		2873	#define EXTI_IMR_IM13 EXTI_IMR_MR13
		2874	#define EXTI_IMR_IM14 EXTI_IMR_MR14
		2875	#define EXTI_IMR_IM15 EXTI_IMR_MR15
		2876	#define EXTI_IMR_IM16 EXTI_IMR_MR16
		2877	#define EXTI_IMR_IM17 EXTI_IMR_MR17
		2878	#define EXTI_IMR_IM18 EXTI_IMR_MR18
		2879	#define EXTI_IMR_IM 0x0007FFFFU /!< Interrupt Mask All /
		2880
		2881	/***************** Bit definition for EXTI_EMR register *****************/
		2882	#define EXTI_EMR_MR0_Pos (0U)
		2883	#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /!< 0x00000001 /
		2884	#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /!< Event Mask on line 0 /
		2885	#define EXTI_EMR_MR1_Pos (1U)
		2886	#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /!< 0x00000002 /
		2887	#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /!< Event Mask on line 1 /
		2888	#define EXTI_EMR_MR2_Pos (2U)
		2889	#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /!< 0x00000004 /
		2890	#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /!< Event Mask on line 2 /
		2891	#define EXTI_EMR_MR3_Pos (3U)
		2892	#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /!< 0x00000008 /
		2893	#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /!< Event Mask on line 3 /
		2894	#define EXTI_EMR_MR4_Pos (4U)
		2895	#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /!< 0x00000010 /
		2896	#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /!< Event Mask on line 4 /
		2897	#define EXTI_EMR_MR5_Pos (5U)
		2898	#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /!< 0x00000020 /
		2899	#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /!< Event Mask on line 5 /
		2900	#define EXTI_EMR_MR6_Pos (6U)
		2901	#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /!< 0x00000040 /
		2902	#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /!< Event Mask on line 6 /
		2903	#define EXTI_EMR_MR7_Pos (7U)
		2904	#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /!< 0x00000080 /
		2905	#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /!< Event Mask on line 7 /
		2906	#define EXTI_EMR_MR8_Pos (8U)
		2907	#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /!< 0x00000100 /
		2908	#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /!< Event Mask on line 8 /
		2909	#define EXTI_EMR_MR9_Pos (9U)
		2910	#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /!< 0x00000200 /
		2911	#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /!< Event Mask on line 9 /
		2912	#define EXTI_EMR_MR10_Pos (10U)
		2913	#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /!< 0x00000400 /
		2914	#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /!< Event Mask on line 10 /
		2915	#define EXTI_EMR_MR11_Pos (11U)
		2916	#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /!< 0x00000800 /
		2917	#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /!< Event Mask on line 11 /
		2918	#define EXTI_EMR_MR12_Pos (12U)
		2919	#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /!< 0x00001000 /
		2920	#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /!< Event Mask on line 12 /
		2921	#define EXTI_EMR_MR13_Pos (13U)
		2922	#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /!< 0x00002000 /
		2923	#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /!< Event Mask on line 13 /
		2924	#define EXTI_EMR_MR14_Pos (14U)
		2925	#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /!< 0x00004000 /
		2926	#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /!< Event Mask on line 14 /
		2927	#define EXTI_EMR_MR15_Pos (15U)
		2928	#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /!< 0x00008000 /
		2929	#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /!< Event Mask on line 15 /
		2930	#define EXTI_EMR_MR16_Pos (16U)
		2931	#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /!< 0x00010000 /
		2932	#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /!< Event Mask on line 16 /
		2933	#define EXTI_EMR_MR17_Pos (17U)
		2934	#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /!< 0x00020000 /
		2935	#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /!< Event Mask on line 17 /
		2936	#define EXTI_EMR_MR18_Pos (18U)
		2937	#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /!< 0x00040000 /
		2938	#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /!< Event Mask on line 18 /
		2939
		2940	/* References Defines */
		2941	#define EXTI_EMR_EM0 EXTI_EMR_MR0
		2942	#define EXTI_EMR_EM1 EXTI_EMR_MR1
		2943	#define EXTI_EMR_EM2 EXTI_EMR_MR2
		2944	#define EXTI_EMR_EM3 EXTI_EMR_MR3
		2945	#define EXTI_EMR_EM4 EXTI_EMR_MR4
		2946	#define EXTI_EMR_EM5 EXTI_EMR_MR5
		2947	#define EXTI_EMR_EM6 EXTI_EMR_MR6
		2948	#define EXTI_EMR_EM7 EXTI_EMR_MR7
		2949	#define EXTI_EMR_EM8 EXTI_EMR_MR8
		2950	#define EXTI_EMR_EM9 EXTI_EMR_MR9
		2951	#define EXTI_EMR_EM10 EXTI_EMR_MR10
		2952	#define EXTI_EMR_EM11 EXTI_EMR_MR11
		2953	#define EXTI_EMR_EM12 EXTI_EMR_MR12
		2954	#define EXTI_EMR_EM13 EXTI_EMR_MR13
		2955	#define EXTI_EMR_EM14 EXTI_EMR_MR14
		2956	#define EXTI_EMR_EM15 EXTI_EMR_MR15
		2957	#define EXTI_EMR_EM16 EXTI_EMR_MR16
		2958	#define EXTI_EMR_EM17 EXTI_EMR_MR17
		2959	#define EXTI_EMR_EM18 EXTI_EMR_MR18
		2960
		2961	/**************** Bit definition for EXTI_RTSR register *****************/
		2962	#define EXTI_RTSR_TR0_Pos (0U)
		2963	#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /!< 0x00000001 /
		2964	#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /!< Rising trigger event configuration bit of line 0 /
		2965	#define EXTI_RTSR_TR1_Pos (1U)
		2966	#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /!< 0x00000002 /
		2967	#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /!< Rising trigger event configuration bit of line 1 /
		2968	#define EXTI_RTSR_TR2_Pos (2U)
		2969	#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /!< 0x00000004 /
		2970	#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /!< Rising trigger event configuration bit of line 2 /
		2971	#define EXTI_RTSR_TR3_Pos (3U)
		2972	#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /!< 0x00000008 /
		2973	#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /!< Rising trigger event configuration bit of line 3 /
		2974	#define EXTI_RTSR_TR4_Pos (4U)
		2975	#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /!< 0x00000010 /
		2976	#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /!< Rising trigger event configuration bit of line 4 /
		2977	#define EXTI_RTSR_TR5_Pos (5U)
		2978	#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /!< 0x00000020 /
		2979	#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /!< Rising trigger event configuration bit of line 5 /
		2980	#define EXTI_RTSR_TR6_Pos (6U)
		2981	#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /!< 0x00000040 /
		2982	#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /!< Rising trigger event configuration bit of line 6 /
		2983	#define EXTI_RTSR_TR7_Pos (7U)
		2984	#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /!< 0x00000080 /
		2985	#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /!< Rising trigger event configuration bit of line 7 /
		2986	#define EXTI_RTSR_TR8_Pos (8U)
		2987	#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /!< 0x00000100 /
		2988	#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /!< Rising trigger event configuration bit of line 8 /
		2989	#define EXTI_RTSR_TR9_Pos (9U)
		2990	#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /!< 0x00000200 /
		2991	#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /!< Rising trigger event configuration bit of line 9 /
		2992	#define EXTI_RTSR_TR10_Pos (10U)
		2993	#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /!< 0x00000400 /
		2994	#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /!< Rising trigger event configuration bit of line 10 /
		2995	#define EXTI_RTSR_TR11_Pos (11U)
		2996	#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /!< 0x00000800 /
		2997	#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /!< Rising trigger event configuration bit of line 11 /
		2998	#define EXTI_RTSR_TR12_Pos (12U)
		2999	#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /!< 0x00001000 /
		3000	#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /!< Rising trigger event configuration bit of line 12 /
		3001	#define EXTI_RTSR_TR13_Pos (13U)
		3002	#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /!< 0x00002000 /
		3003	#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /!< Rising trigger event configuration bit of line 13 /
		3004	#define EXTI_RTSR_TR14_Pos (14U)
		3005	#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /!< 0x00004000 /
		3006	#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /!< Rising trigger event configuration bit of line 14 /
		3007	#define EXTI_RTSR_TR15_Pos (15U)
		3008	#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /!< 0x00008000 /
		3009	#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /!< Rising trigger event configuration bit of line 15 /
		3010	#define EXTI_RTSR_TR16_Pos (16U)
		3011	#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /!< 0x00010000 /
		3012	#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /!< Rising trigger event configuration bit of line 16 /
		3013	#define EXTI_RTSR_TR17_Pos (17U)
		3014	#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /!< 0x00020000 /
		3015	#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /!< Rising trigger event configuration bit of line 17 /
		3016	#define EXTI_RTSR_TR18_Pos (18U)
		3017	#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /!< 0x00040000 /
		3018	#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /!< Rising trigger event configuration bit of line 18 /
		3019
		3020	/* References Defines */
		3021	#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
		3022	#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
		3023	#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
		3024	#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
		3025	#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
		3026	#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
		3027	#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
		3028	#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
		3029	#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
		3030	#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
		3031	#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
		3032	#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
		3033	#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
		3034	#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
		3035	#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
		3036	#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
		3037	#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
		3038	#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
		3039	#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
		3040
		3041	/**************** Bit definition for EXTI_FTSR register *****************/
		3042	#define EXTI_FTSR_TR0_Pos (0U)
		3043	#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /!< 0x00000001 /
		3044	#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /!< Falling trigger event configuration bit of line 0 /
		3045	#define EXTI_FTSR_TR1_Pos (1U)
		3046	#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /!< 0x00000002 /
		3047	#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /!< Falling trigger event configuration bit of line 1 /
		3048	#define EXTI_FTSR_TR2_Pos (2U)
		3049	#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /!< 0x00000004 /
		3050	#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /!< Falling trigger event configuration bit of line 2 /
		3051	#define EXTI_FTSR_TR3_Pos (3U)
		3052	#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /!< 0x00000008 /
		3053	#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /!< Falling trigger event configuration bit of line 3 /
		3054	#define EXTI_FTSR_TR4_Pos (4U)
		3055	#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /!< 0x00000010 /
		3056	#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /!< Falling trigger event configuration bit of line 4 /
		3057	#define EXTI_FTSR_TR5_Pos (5U)
		3058	#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /!< 0x00000020 /
		3059	#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /!< Falling trigger event configuration bit of line 5 /
		3060	#define EXTI_FTSR_TR6_Pos (6U)
		3061	#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /!< 0x00000040 /
		3062	#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /!< Falling trigger event configuration bit of line 6 /
		3063	#define EXTI_FTSR_TR7_Pos (7U)
		3064	#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /!< 0x00000080 /
		3065	#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /!< Falling trigger event configuration bit of line 7 /
		3066	#define EXTI_FTSR_TR8_Pos (8U)
		3067	#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /!< 0x00000100 /
		3068	#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /!< Falling trigger event configuration bit of line 8 /
		3069	#define EXTI_FTSR_TR9_Pos (9U)
		3070	#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /!< 0x00000200 /
		3071	#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /!< Falling trigger event configuration bit of line 9 /
		3072	#define EXTI_FTSR_TR10_Pos (10U)
		3073	#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /!< 0x00000400 /
		3074	#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /!< Falling trigger event configuration bit of line 10 /
		3075	#define EXTI_FTSR_TR11_Pos (11U)
		3076	#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /!< 0x00000800 /
		3077	#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /!< Falling trigger event configuration bit of line 11 /
		3078	#define EXTI_FTSR_TR12_Pos (12U)
		3079	#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /!< 0x00001000 /
		3080	#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /!< Falling trigger event configuration bit of line 12 /
		3081	#define EXTI_FTSR_TR13_Pos (13U)
		3082	#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /!< 0x00002000 /
		3083	#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /!< Falling trigger event configuration bit of line 13 /
		3084	#define EXTI_FTSR_TR14_Pos (14U)
		3085	#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /!< 0x00004000 /
		3086	#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /!< Falling trigger event configuration bit of line 14 /
		3087	#define EXTI_FTSR_TR15_Pos (15U)
		3088	#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /!< 0x00008000 /
		3089	#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /!< Falling trigger event configuration bit of line 15 /
		3090	#define EXTI_FTSR_TR16_Pos (16U)
		3091	#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /!< 0x00010000 /
		3092	#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /!< Falling trigger event configuration bit of line 16 /
		3093	#define EXTI_FTSR_TR17_Pos (17U)
		3094	#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /!< 0x00020000 /
		3095	#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /!< Falling trigger event configuration bit of line 17 /
		3096	#define EXTI_FTSR_TR18_Pos (18U)
		3097	#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /!< 0x00040000 /
		3098	#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /!< Falling trigger event configuration bit of line 18 /
		3099
		3100	/* References Defines */
		3101	#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
		3102	#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
		3103	#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
		3104	#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
		3105	#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
		3106	#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
		3107	#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
		3108	#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
		3109	#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
		3110	#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
		3111	#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
		3112	#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
		3113	#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
		3114	#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
		3115	#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
		3116	#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
		3117	#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
		3118	#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
		3119	#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
		3120
		3121	/**************** Bit definition for EXTI_SWIER register ****************/
		3122	#define EXTI_SWIER_SWIER0_Pos (0U)
		3123	#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /!< 0x00000001 /
		3124	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /!< Software Interrupt on line 0 /
		3125	#define EXTI_SWIER_SWIER1_Pos (1U)
		3126	#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /!< 0x00000002 /
		3127	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /!< Software Interrupt on line 1 /
		3128	#define EXTI_SWIER_SWIER2_Pos (2U)
		3129	#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /!< 0x00000004 /
		3130	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /!< Software Interrupt on line 2 /
		3131	#define EXTI_SWIER_SWIER3_Pos (3U)
		3132	#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /!< 0x00000008 /
		3133	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /!< Software Interrupt on line 3 /
		3134	#define EXTI_SWIER_SWIER4_Pos (4U)
		3135	#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /!< 0x00000010 /
		3136	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /!< Software Interrupt on line 4 /
		3137	#define EXTI_SWIER_SWIER5_Pos (5U)
		3138	#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /!< 0x00000020 /
		3139	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /!< Software Interrupt on line 5 /
		3140	#define EXTI_SWIER_SWIER6_Pos (6U)
		3141	#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /!< 0x00000040 /
		3142	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /!< Software Interrupt on line 6 /
		3143	#define EXTI_SWIER_SWIER7_Pos (7U)
		3144	#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /!< 0x00000080 /
		3145	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /!< Software Interrupt on line 7 /
		3146	#define EXTI_SWIER_SWIER8_Pos (8U)
		3147	#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /!< 0x00000100 /
		3148	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /!< Software Interrupt on line 8 /
		3149	#define EXTI_SWIER_SWIER9_Pos (9U)
		3150	#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /!< 0x00000200 /
		3151	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /!< Software Interrupt on line 9 /
		3152	#define EXTI_SWIER_SWIER10_Pos (10U)
		3153	#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /!< 0x00000400 /
		3154	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /!< Software Interrupt on line 10 /
		3155	#define EXTI_SWIER_SWIER11_Pos (11U)
		3156	#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /!< 0x00000800 /
		3157	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /!< Software Interrupt on line 11 /
		3158	#define EXTI_SWIER_SWIER12_Pos (12U)
		3159	#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /!< 0x00001000 /
		3160	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /!< Software Interrupt on line 12 /
		3161	#define EXTI_SWIER_SWIER13_Pos (13U)
		3162	#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /!< 0x00002000 /
		3163	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /!< Software Interrupt on line 13 /
		3164	#define EXTI_SWIER_SWIER14_Pos (14U)
		3165	#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /!< 0x00004000 /
		3166	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /!< Software Interrupt on line 14 /
		3167	#define EXTI_SWIER_SWIER15_Pos (15U)
		3168	#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /!< 0x00008000 /
		3169	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /!< Software Interrupt on line 15 /
		3170	#define EXTI_SWIER_SWIER16_Pos (16U)
		3171	#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /!< 0x00010000 /
		3172	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /!< Software Interrupt on line 16 /
		3173	#define EXTI_SWIER_SWIER17_Pos (17U)
		3174	#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /!< 0x00020000 /
		3175	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /!< Software Interrupt on line 17 /
		3176	#define EXTI_SWIER_SWIER18_Pos (18U)
		3177	#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /!< 0x00040000 /
		3178	#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /!< Software Interrupt on line 18 /
		3179
		3180	/* References Defines */
		3181	#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
		3182	#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
		3183	#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
		3184	#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
		3185	#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
		3186	#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
		3187	#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
		3188	#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
		3189	#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
		3190	#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
		3191	#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
		3192	#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
		3193	#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
		3194	#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
		3195	#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
		3196	#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
		3197	#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
		3198	#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
		3199	#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
		3200
		3201	/***************** Bit definition for EXTI_PR register ******************/
		3202	#define EXTI_PR_PR0_Pos (0U)
		3203	#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /!< 0x00000001 /
		3204	#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /!< Pending bit for line 0 /
		3205	#define EXTI_PR_PR1_Pos (1U)
		3206	#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /!< 0x00000002 /
		3207	#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /!< Pending bit for line 1 /
		3208	#define EXTI_PR_PR2_Pos (2U)
		3209	#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /!< 0x00000004 /
		3210	#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /!< Pending bit for line 2 /
		3211	#define EXTI_PR_PR3_Pos (3U)
		3212	#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /!< 0x00000008 /
		3213	#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /!< Pending bit for line 3 /
		3214	#define EXTI_PR_PR4_Pos (4U)
		3215	#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /!< 0x00000010 /
		3216	#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /!< Pending bit for line 4 /
		3217	#define EXTI_PR_PR5_Pos (5U)
		3218	#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /!< 0x00000020 /
		3219	#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /!< Pending bit for line 5 /
		3220	#define EXTI_PR_PR6_Pos (6U)
		3221	#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /!< 0x00000040 /
		3222	#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /!< Pending bit for line 6 /
		3223	#define EXTI_PR_PR7_Pos (7U)
		3224	#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /!< 0x00000080 /
		3225	#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /!< Pending bit for line 7 /
		3226	#define EXTI_PR_PR8_Pos (8U)
		3227	#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /!< 0x00000100 /
		3228	#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /!< Pending bit for line 8 /
		3229	#define EXTI_PR_PR9_Pos (9U)
		3230	#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /!< 0x00000200 /
		3231	#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /!< Pending bit for line 9 /
		3232	#define EXTI_PR_PR10_Pos (10U)
		3233	#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /!< 0x00000400 /
		3234	#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /!< Pending bit for line 10 /
		3235	#define EXTI_PR_PR11_Pos (11U)
		3236	#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /!< 0x00000800 /
		3237	#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /!< Pending bit for line 11 /
		3238	#define EXTI_PR_PR12_Pos (12U)
		3239	#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /!< 0x00001000 /
		3240	#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /!< Pending bit for line 12 /
		3241	#define EXTI_PR_PR13_Pos (13U)
		3242	#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /!< 0x00002000 /
		3243	#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /!< Pending bit for line 13 /
		3244	#define EXTI_PR_PR14_Pos (14U)
		3245	#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /!< 0x00004000 /
		3246	#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /!< Pending bit for line 14 /
		3247	#define EXTI_PR_PR15_Pos (15U)
		3248	#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /!< 0x00008000 /
		3249	#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /!< Pending bit for line 15 /
		3250	#define EXTI_PR_PR16_Pos (16U)
		3251	#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /!< 0x00010000 /
		3252	#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /!< Pending bit for line 16 /
		3253	#define EXTI_PR_PR17_Pos (17U)
		3254	#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /!< 0x00020000 /
		3255	#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /!< Pending bit for line 17 /
		3256	#define EXTI_PR_PR18_Pos (18U)
		3257	#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /!< 0x00040000 /
		3258	#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /!< Pending bit for line 18 /
		3259
		3260	/* References Defines */
		3261	#define EXTI_PR_PIF0 EXTI_PR_PR0
		3262	#define EXTI_PR_PIF1 EXTI_PR_PR1
		3263	#define EXTI_PR_PIF2 EXTI_PR_PR2
		3264	#define EXTI_PR_PIF3 EXTI_PR_PR3
		3265	#define EXTI_PR_PIF4 EXTI_PR_PR4
		3266	#define EXTI_PR_PIF5 EXTI_PR_PR5
		3267	#define EXTI_PR_PIF6 EXTI_PR_PR6
		3268	#define EXTI_PR_PIF7 EXTI_PR_PR7
		3269	#define EXTI_PR_PIF8 EXTI_PR_PR8
		3270	#define EXTI_PR_PIF9 EXTI_PR_PR9
		3271	#define EXTI_PR_PIF10 EXTI_PR_PR10
		3272	#define EXTI_PR_PIF11 EXTI_PR_PR11
		3273	#define EXTI_PR_PIF12 EXTI_PR_PR12
		3274	#define EXTI_PR_PIF13 EXTI_PR_PR13
		3275	#define EXTI_PR_PIF14 EXTI_PR_PR14
		3276	#define EXTI_PR_PIF15 EXTI_PR_PR15
		3277	#define EXTI_PR_PIF16 EXTI_PR_PR16
		3278	#define EXTI_PR_PIF17 EXTI_PR_PR17
		3279	#define EXTI_PR_PIF18 EXTI_PR_PR18
		3280
		3281	/******************************************************************************/
		3282	/* */
		3283	/* DMA Controller */
		3284	/* */
		3285	/******************************************************************************/
		3286
		3287	/***************** Bit definition for DMA_ISR register ******************/
		3288	#define DMA_ISR_GIF1_Pos (0U)
		3289	#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /!< 0x00000001 /
		3290	#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /!< Channel 1 Global interrupt flag /
		3291	#define DMA_ISR_TCIF1_Pos (1U)
		3292	#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /!< 0x00000002 /
		3293	#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /!< Channel 1 Transfer Complete flag /
		3294	#define DMA_ISR_HTIF1_Pos (2U)
		3295	#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /!< 0x00000004 /
		3296	#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /!< Channel 1 Half Transfer flag /
		3297	#define DMA_ISR_TEIF1_Pos (3U)
		3298	#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /!< 0x00000008 /
		3299	#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /!< Channel 1 Transfer Error flag /
		3300	#define DMA_ISR_GIF2_Pos (4U)
		3301	#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /!< 0x00000010 /
		3302	#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /!< Channel 2 Global interrupt flag /
		3303	#define DMA_ISR_TCIF2_Pos (5U)
		3304	#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /!< 0x00000020 /
		3305	#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /!< Channel 2 Transfer Complete flag /
		3306	#define DMA_ISR_HTIF2_Pos (6U)
		3307	#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /!< 0x00000040 /
		3308	#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /!< Channel 2 Half Transfer flag /
		3309	#define DMA_ISR_TEIF2_Pos (7U)
		3310	#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /!< 0x00000080 /
		3311	#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /!< Channel 2 Transfer Error flag /
		3312	#define DMA_ISR_GIF3_Pos (8U)
		3313	#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /!< 0x00000100 /
		3314	#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /!< Channel 3 Global interrupt flag /
		3315	#define DMA_ISR_TCIF3_Pos (9U)
		3316	#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /!< 0x00000200 /
		3317	#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /!< Channel 3 Transfer Complete flag /
		3318	#define DMA_ISR_HTIF3_Pos (10U)
		3319	#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /!< 0x00000400 /
		3320	#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /!< Channel 3 Half Transfer flag /
		3321	#define DMA_ISR_TEIF3_Pos (11U)
		3322	#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /!< 0x00000800 /
		3323	#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /!< Channel 3 Transfer Error flag /
		3324	#define DMA_ISR_GIF4_Pos (12U)
		3325	#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /!< 0x00001000 /
		3326	#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /!< Channel 4 Global interrupt flag /
		3327	#define DMA_ISR_TCIF4_Pos (13U)
		3328	#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /!< 0x00002000 /
		3329	#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /!< Channel 4 Transfer Complete flag /
		3330	#define DMA_ISR_HTIF4_Pos (14U)
		3331	#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /!< 0x00004000 /
		3332	#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /!< Channel 4 Half Transfer flag /
		3333	#define DMA_ISR_TEIF4_Pos (15U)
		3334	#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /!< 0x00008000 /
		3335	#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /!< Channel 4 Transfer Error flag /
		3336	#define DMA_ISR_GIF5_Pos (16U)
		3337	#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /!< 0x00010000 /
		3338	#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /!< Channel 5 Global interrupt flag /
		3339	#define DMA_ISR_TCIF5_Pos (17U)
		3340	#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /!< 0x00020000 /
		3341	#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /!< Channel 5 Transfer Complete flag /
		3342	#define DMA_ISR_HTIF5_Pos (18U)
		3343	#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /!< 0x00040000 /
		3344	#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /!< Channel 5 Half Transfer flag /
		3345	#define DMA_ISR_TEIF5_Pos (19U)
		3346	#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /!< 0x00080000 /
		3347	#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /!< Channel 5 Transfer Error flag /
		3348	#define DMA_ISR_GIF6_Pos (20U)
		3349	#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /!< 0x00100000 /
		3350	#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /!< Channel 6 Global interrupt flag /
		3351	#define DMA_ISR_TCIF6_Pos (21U)
		3352	#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /!< 0x00200000 /
		3353	#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /!< Channel 6 Transfer Complete flag /
		3354	#define DMA_ISR_HTIF6_Pos (22U)
		3355	#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /!< 0x00400000 /
		3356	#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /!< Channel 6 Half Transfer flag /
		3357	#define DMA_ISR_TEIF6_Pos (23U)
		3358	#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /!< 0x00800000 /
		3359	#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /!< Channel 6 Transfer Error flag /
		3360	#define DMA_ISR_GIF7_Pos (24U)
		3361	#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /!< 0x01000000 /
		3362	#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /!< Channel 7 Global interrupt flag /
		3363	#define DMA_ISR_TCIF7_Pos (25U)
		3364	#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /!< 0x02000000 /
		3365	#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /!< Channel 7 Transfer Complete flag /
		3366	#define DMA_ISR_HTIF7_Pos (26U)
		3367	#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /!< 0x04000000 /
		3368	#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /!< Channel 7 Half Transfer flag /
		3369	#define DMA_ISR_TEIF7_Pos (27U)
		3370	#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /!< 0x08000000 /
		3371	#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /!< Channel 7 Transfer Error flag /
		3372
		3373	/***************** Bit definition for DMA_IFCR register *****************/
		3374	#define DMA_IFCR_CGIF1_Pos (0U)
		3375	#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /!< 0x00000001 /
		3376	#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /!< Channel 1 Global interrupt clear /
		3377	#define DMA_IFCR_CTCIF1_Pos (1U)
		3378	#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /!< 0x00000002 /
		3379	#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /!< Channel 1 Transfer Complete clear /
		3380	#define DMA_IFCR_CHTIF1_Pos (2U)
		3381	#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /!< 0x00000004 /
		3382	#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /!< Channel 1 Half Transfer clear /
		3383	#define DMA_IFCR_CTEIF1_Pos (3U)
		3384	#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /!< 0x00000008 /
		3385	#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /!< Channel 1 Transfer Error clear /
		3386	#define DMA_IFCR_CGIF2_Pos (4U)
		3387	#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /!< 0x00000010 /
		3388	#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /!< Channel 2 Global interrupt clear /
		3389	#define DMA_IFCR_CTCIF2_Pos (5U)
		3390	#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /!< 0x00000020 /
		3391	#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /!< Channel 2 Transfer Complete clear /
		3392	#define DMA_IFCR_CHTIF2_Pos (6U)
		3393	#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /!< 0x00000040 /
		3394	#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /!< Channel 2 Half Transfer clear /
		3395	#define DMA_IFCR_CTEIF2_Pos (7U)
		3396	#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /!< 0x00000080 /
		3397	#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /!< Channel 2 Transfer Error clear /
		3398	#define DMA_IFCR_CGIF3_Pos (8U)
		3399	#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /!< 0x00000100 /
		3400	#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /!< Channel 3 Global interrupt clear /
		3401	#define DMA_IFCR_CTCIF3_Pos (9U)
		3402	#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /!< 0x00000200 /
		3403	#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /!< Channel 3 Transfer Complete clear /
		3404	#define DMA_IFCR_CHTIF3_Pos (10U)
		3405	#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /!< 0x00000400 /
		3406	#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /!< Channel 3 Half Transfer clear /
		3407	#define DMA_IFCR_CTEIF3_Pos (11U)
		3408	#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /!< 0x00000800 /
		3409	#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /!< Channel 3 Transfer Error clear /
		3410	#define DMA_IFCR_CGIF4_Pos (12U)
		3411	#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /!< 0x00001000 /
		3412	#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /!< Channel 4 Global interrupt clear /
		3413	#define DMA_IFCR_CTCIF4_Pos (13U)
		3414	#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /!< 0x00002000 /
		3415	#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /!< Channel 4 Transfer Complete clear /
		3416	#define DMA_IFCR_CHTIF4_Pos (14U)
		3417	#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /!< 0x00004000 /
		3418	#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /!< Channel 4 Half Transfer clear /
		3419	#define DMA_IFCR_CTEIF4_Pos (15U)
		3420	#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /!< 0x00008000 /
		3421	#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /!< Channel 4 Transfer Error clear /
		3422	#define DMA_IFCR_CGIF5_Pos (16U)
		3423	#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /!< 0x00010000 /
		3424	#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /!< Channel 5 Global interrupt clear /
		3425	#define DMA_IFCR_CTCIF5_Pos (17U)
		3426	#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /!< 0x00020000 /
		3427	#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /!< Channel 5 Transfer Complete clear /
		3428	#define DMA_IFCR_CHTIF5_Pos (18U)
		3429	#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /!< 0x00040000 /
		3430	#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /!< Channel 5 Half Transfer clear /
		3431	#define DMA_IFCR_CTEIF5_Pos (19U)
		3432	#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /!< 0x00080000 /
		3433	#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /!< Channel 5 Transfer Error clear /
		3434	#define DMA_IFCR_CGIF6_Pos (20U)
		3435	#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /!< 0x00100000 /
		3436	#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /!< Channel 6 Global interrupt clear /
		3437	#define DMA_IFCR_CTCIF6_Pos (21U)
		3438	#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /!< 0x00200000 /
		3439	#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /!< Channel 6 Transfer Complete clear /
		3440	#define DMA_IFCR_CHTIF6_Pos (22U)
		3441	#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /!< 0x00400000 /
		3442	#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /!< Channel 6 Half Transfer clear /
		3443	#define DMA_IFCR_CTEIF6_Pos (23U)
		3444	#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /!< 0x00800000 /
		3445	#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /!< Channel 6 Transfer Error clear /
		3446	#define DMA_IFCR_CGIF7_Pos (24U)
		3447	#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /!< 0x01000000 /
		3448	#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /!< Channel 7 Global interrupt clear /
		3449	#define DMA_IFCR_CTCIF7_Pos (25U)
		3450	#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /!< 0x02000000 /
		3451	#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /!< Channel 7 Transfer Complete clear /
		3452	#define DMA_IFCR_CHTIF7_Pos (26U)
		3453	#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /!< 0x04000000 /
		3454	#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /!< Channel 7 Half Transfer clear /
		3455	#define DMA_IFCR_CTEIF7_Pos (27U)
		3456	#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /!< 0x08000000 /
		3457	#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /!< Channel 7 Transfer Error clear /
		3458
		3459	/***************** Bit definition for DMA_CCR register *****************/
		3460	#define DMA_CCR_EN_Pos (0U)
		3461	#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /!< 0x00000001 /
		3462	#define DMA_CCR_EN DMA_CCR_EN_Msk /!< Channel enable /
		3463	#define DMA_CCR_TCIE_Pos (1U)
		3464	#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /!< 0x00000002 /
		3465	#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /!< Transfer complete interrupt enable /
		3466	#define DMA_CCR_HTIE_Pos (2U)
		3467	#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /!< 0x00000004 /
		3468	#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /!< Half Transfer interrupt enable /
		3469	#define DMA_CCR_TEIE_Pos (3U)
		3470	#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /!< 0x00000008 /
		3471	#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /!< Transfer error interrupt enable /
		3472	#define DMA_CCR_DIR_Pos (4U)
		3473	#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /!< 0x00000010 /
		3474	#define DMA_CCR_DIR DMA_CCR_DIR_Msk /!< Data transfer direction /
		3475	#define DMA_CCR_CIRC_Pos (5U)
		3476	#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /!< 0x00000020 /
		3477	#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /!< Circular mode /
		3478	#define DMA_CCR_PINC_Pos (6U)
		3479	#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /!< 0x00000040 /
		3480	#define DMA_CCR_PINC DMA_CCR_PINC_Msk /!< Peripheral increment mode /
		3481	#define DMA_CCR_MINC_Pos (7U)
		3482	#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /!< 0x00000080 /
		3483	#define DMA_CCR_MINC DMA_CCR_MINC_Msk /!< Memory increment mode /
		3484
		3485	#define DMA_CCR_PSIZE_Pos (8U)
		3486	#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /!< 0x00000300 /
		3487	#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /!< PSIZE[1:0] bits (Peripheral size) /
		3488	#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /!< 0x00000100 /
		3489	#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /!< 0x00000200 /
		3490
		3491	#define DMA_CCR_MSIZE_Pos (10U)
		3492	#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /!< 0x00000C00 /
		3493	#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /!< MSIZE[1:0] bits (Memory size) /
		3494	#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /!< 0x00000400 /
		3495	#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /!< 0x00000800 /
		3496
		3497	#define DMA_CCR_PL_Pos (12U)
		3498	#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /!< 0x00003000 /
		3499	#define DMA_CCR_PL DMA_CCR_PL_Msk /!< PL[1:0] bits(Channel Priority level) /
		3500	#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /!< 0x00001000 /
		3501	#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /!< 0x00002000 /
		3502
		3503	#define DMA_CCR_MEM2MEM_Pos (14U)
		3504	#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /!< 0x00004000 /
		3505	#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /!< Memory to memory mode /
		3506
		3507	/**************** Bit definition for DMA_CNDTR register ****************/
		3508	#define DMA_CNDTR_NDT_Pos (0U)
		3509	#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /!< 0x0000FFFF /
		3510	#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /!< Number of data to Transfer /
		3511
		3512	/**************** Bit definition for DMA_CPAR register *****************/
		3513	#define DMA_CPAR_PA_Pos (0U)
		3514	#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /!< 0xFFFFFFFF /
		3515	#define DMA_CPAR_PA DMA_CPAR_PA_Msk /!< Peripheral Address /
		3516
		3517	/**************** Bit definition for DMA_CMAR register *****************/
		3518	#define DMA_CMAR_MA_Pos (0U)
		3519	#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /!< 0xFFFFFFFF /
		3520	#define DMA_CMAR_MA DMA_CMAR_MA_Msk /!< Memory Address /
		3521
		3522	/******************************************************************************/
		3523	/* */
		3524	/* Analog to Digital Converter (ADC) */
		3525	/* */
		3526	/******************************************************************************/
		3527
		3528	/*
		3529	* @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
		3530	*/
		3531	/* Note: No specific macro feature on this device */
		3532
		3533	/****************** Bit definition for ADC_SR register ******************/
		3534	#define ADC_SR_AWD_Pos (0U)
		3535	#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /!< 0x00000001 /
		3536	#define ADC_SR_AWD ADC_SR_AWD_Msk /!< ADC analog watchdog 1 flag /
		3537	#define ADC_SR_EOS_Pos (1U)
		3538	#define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /!< 0x00000002 /
		3539	#define ADC_SR_EOS ADC_SR_EOS_Msk /!< ADC group regular end of sequence conversions flag /
		3540	#define ADC_SR_JEOS_Pos (2U)
		3541	#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /!< 0x00000004 /
		3542	#define ADC_SR_JEOS ADC_SR_JEOS_Msk /!< ADC group injected end of sequence conversions flag /
		3543	#define ADC_SR_JSTRT_Pos (3U)
		3544	#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /!< 0x00000008 /
		3545	#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /!< ADC group injected conversion start flag /
		3546	#define ADC_SR_STRT_Pos (4U)
		3547	#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /!< 0x00000010 /
		3548	#define ADC_SR_STRT ADC_SR_STRT_Msk /!< ADC group regular conversion start flag /
		3549
		3550	/* Legacy defines */
		3551	#define ADC_SR_EOC (ADC_SR_EOS)
		3552	#define ADC_SR_JEOC (ADC_SR_JEOS)
		3553
		3554	/***************** Bit definition for ADC_CR1 register ******************/
		3555	#define ADC_CR1_AWDCH_Pos (0U)
		3556	#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /!< 0x0000001F /
		3557	#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /!< ADC analog watchdog 1 monitored channel selection /
		3558	#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /!< 0x00000001 /
		3559	#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /!< 0x00000002 /
		3560	#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /!< 0x00000004 /
		3561	#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /!< 0x00000008 /
		3562	#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /!< 0x00000010 /
		3563
		3564	#define ADC_CR1_EOSIE_Pos (5U)
		3565	#define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /!< 0x00000020 /
		3566	#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /!< ADC group regular end of sequence conversions interrupt /
		3567	#define ADC_CR1_AWDIE_Pos (6U)
		3568	#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /!< 0x00000040 /
		3569	#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /!< ADC analog watchdog 1 interrupt /
		3570	#define ADC_CR1_JEOSIE_Pos (7U)
		3571	#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /!< 0x00000080 /
		3572	#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /!< ADC group injected end of sequence conversions interrupt /
		3573	#define ADC_CR1_SCAN_Pos (8U)
		3574	#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /!< 0x00000100 /
		3575	#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /!< ADC scan mode /
		3576	#define ADC_CR1_AWDSGL_Pos (9U)
		3577	#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /!< 0x00000200 /
		3578	#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /!< ADC analog watchdog 1 monitoring a single channel or all channels /
		3579	#define ADC_CR1_JAUTO_Pos (10U)
		3580	#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /!< 0x00000400 /
		3581	#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /!< ADC group injected automatic trigger mode /
		3582	#define ADC_CR1_DISCEN_Pos (11U)
		3583	#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /!< 0x00000800 /
		3584	#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /
		3585	#define ADC_CR1_JDISCEN_Pos (12U)
		3586	#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /!< 0x00001000 /
		3587	#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /!< ADC group injected sequencer discontinuous mode /
		3588
		3589	#define ADC_CR1_DISCNUM_Pos (13U)
		3590	#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /!< 0x0000E000 /
		3591	#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /!< ADC group regular sequencer discontinuous number of ranks /
		3592	#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /!< 0x00002000 /
		3593	#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /!< 0x00004000 /
		3594	#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /!< 0x00008000 /
		3595
		3596	#define ADC_CR1_JAWDEN_Pos (22U)
		3597	#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /!< 0x00400000 /
		3598	#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group injected /
		3599	#define ADC_CR1_AWDEN_Pos (23U)
		3600	#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /!< 0x00800000 /
		3601	#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group regular /
		3602
		3603	/* Legacy defines */
		3604	#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
		3605	#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
		3606
		3607	/***************** Bit definition for ADC_CR2 register ******************/
		3608	#define ADC_CR2_ADON_Pos (0U)
		3609	#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /!< 0x00000001 /
		3610	#define ADC_CR2_ADON ADC_CR2_ADON_Msk /!< ADC enable /
		3611	#define ADC_CR2_CONT_Pos (1U)
		3612	#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /!< 0x00000002 /
		3613	#define ADC_CR2_CONT ADC_CR2_CONT_Msk /!< ADC group regular continuous conversion mode /
		3614	#define ADC_CR2_CAL_Pos (2U)
		3615	#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /!< 0x00000004 /
		3616	#define ADC_CR2_CAL ADC_CR2_CAL_Msk /!< ADC calibration start /
		3617	#define ADC_CR2_RSTCAL_Pos (3U)
		3618	#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /!< 0x00000008 /
		3619	#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /!< ADC calibration reset /
		3620	#define ADC_CR2_DMA_Pos (8U)
		3621	#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /!< 0x00000100 /
		3622	#define ADC_CR2_DMA ADC_CR2_DMA_Msk /!< ADC DMA transfer enable /
		3623	#define ADC_CR2_ALIGN_Pos (11U)
		3624	#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /!< 0x00000800 /
		3625	#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /!< ADC data alignment /
		3626
		3627	#define ADC_CR2_JEXTSEL_Pos (12U)
		3628	#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00007000 /
		3629	#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /!< ADC group injected external trigger source /
		3630	#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00001000 /
		3631	#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00002000 /
		3632	#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00004000 /
		3633
		3634	#define ADC_CR2_JEXTTRIG_Pos (15U)
		3635	#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /!< 0x00008000 /
		3636	#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /!< ADC group injected external trigger enable /
		3637
		3638	#define ADC_CR2_EXTSEL_Pos (17U)
		3639	#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /!< 0x000E0000 /
		3640	#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /!< ADC group regular external trigger source /
		3641	#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /!< 0x00020000 /
		3642	#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /!< 0x00040000 /
		3643	#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /!< 0x00080000 /
		3644
		3645	#define ADC_CR2_EXTTRIG_Pos (20U)
		3646	#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /!< 0x00100000 /
		3647	#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /!< ADC group regular external trigger enable /
		3648	#define ADC_CR2_JSWSTART_Pos (21U)
		3649	#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /!< 0x00200000 /
		3650	#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /!< ADC group injected conversion start /
		3651	#define ADC_CR2_SWSTART_Pos (22U)
		3652	#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /!< 0x00400000 /
		3653	#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /!< ADC group regular conversion start /
		3654	#define ADC_CR2_TSVREFE_Pos (23U)
		3655	#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /!< 0x00800000 /
		3656	#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /!< ADC internal path to VrefInt and temperature sensor enable /
		3657
		3658	/**************** Bit definition for ADC_SMPR1 register *****************/
		3659	#define ADC_SMPR1_SMP10_Pos (0U)
		3660	#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /!< 0x00000007 /
		3661	#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /!< ADC channel 10 sampling time selection /
		3662	#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /!< 0x00000001 /
		3663	#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /!< 0x00000002 /
		3664	#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /!< 0x00000004 /
		3665
		3666	#define ADC_SMPR1_SMP11_Pos (3U)
		3667	#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /!< 0x00000038 /
		3668	#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /!< ADC channel 11 sampling time selection /
		3669	#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /!< 0x00000008 /
		3670	#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /!< 0x00000010 /
		3671	#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /!< 0x00000020 /
		3672
		3673	#define ADC_SMPR1_SMP12_Pos (6U)
		3674	#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /!< 0x000001C0 /
		3675	#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /!< ADC channel 12 sampling time selection /
		3676	#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /!< 0x00000040 /
		3677	#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /!< 0x00000080 /
		3678	#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /!< 0x00000100 /
		3679
		3680	#define ADC_SMPR1_SMP13_Pos (9U)
		3681	#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /!< 0x00000E00 /
		3682	#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /!< ADC channel 13 sampling time selection /
		3683	#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /!< 0x00000200 /
		3684	#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /!< 0x00000400 /
		3685	#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /!< 0x00000800 /
		3686
		3687	#define ADC_SMPR1_SMP14_Pos (12U)
		3688	#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /!< 0x00007000 /
		3689	#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /!< ADC channel 14 sampling time selection /
		3690	#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /!< 0x00001000 /
		3691	#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /!< 0x00002000 /
		3692	#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /!< 0x00004000 /
		3693
		3694	#define ADC_SMPR1_SMP15_Pos (15U)
		3695	#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /!< 0x00038000 /
		3696	#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /!< ADC channel 15 sampling time selection /
		3697	#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /!< 0x00008000 /
		3698	#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /!< 0x00010000 /
		3699	#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /!< 0x00020000 /
		3700
		3701	#define ADC_SMPR1_SMP16_Pos (18U)
		3702	#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /!< 0x001C0000 /
		3703	#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /!< ADC channel 16 sampling time selection /
		3704	#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /!< 0x00040000 /
		3705	#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /!< 0x00080000 /
		3706	#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /!< 0x00100000 /
		3707
		3708	#define ADC_SMPR1_SMP17_Pos (21U)
		3709	#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /!< 0x00E00000 /
		3710	#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /!< ADC channel 17 sampling time selection /
		3711	#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /!< 0x00200000 /
		3712	#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /!< 0x00400000 /
		3713	#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /!< 0x00800000 /
		3714
		3715	/**************** Bit definition for ADC_SMPR2 register *****************/
		3716	#define ADC_SMPR2_SMP0_Pos (0U)
		3717	#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /!< 0x00000007 /
		3718	#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /!< ADC channel 0 sampling time selection /
		3719	#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /!< 0x00000001 /
		3720	#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /!< 0x00000002 /
		3721	#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /!< 0x00000004 /
		3722
		3723	#define ADC_SMPR2_SMP1_Pos (3U)
		3724	#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /!< 0x00000038 /
		3725	#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /!< ADC channel 1 sampling time selection /
		3726	#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /!< 0x00000008 /
		3727	#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /!< 0x00000010 /
		3728	#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /!< 0x00000020 /
		3729
		3730	#define ADC_SMPR2_SMP2_Pos (6U)
		3731	#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /!< 0x000001C0 /
		3732	#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /!< ADC channel 2 sampling time selection /
		3733	#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /!< 0x00000040 /
		3734	#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /!< 0x00000080 /
		3735	#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /!< 0x00000100 /
		3736
		3737	#define ADC_SMPR2_SMP3_Pos (9U)
		3738	#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /!< 0x00000E00 /
		3739	#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /!< ADC channel 3 sampling time selection /
		3740	#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /!< 0x00000200 /
		3741	#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /!< 0x00000400 /
		3742	#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /!< 0x00000800 /
		3743
		3744	#define ADC_SMPR2_SMP4_Pos (12U)
		3745	#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /!< 0x00007000 /
		3746	#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /!< ADC channel 4 sampling time selection /
		3747	#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /!< 0x00001000 /
		3748	#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /!< 0x00002000 /
		3749	#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /!< 0x00004000 /
		3750
		3751	#define ADC_SMPR2_SMP5_Pos (15U)
		3752	#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /!< 0x00038000 /
		3753	#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /!< ADC channel 5 sampling time selection /
		3754	#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /!< 0x00008000 /
		3755	#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /!< 0x00010000 /
		3756	#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /!< 0x00020000 /
		3757
		3758	#define ADC_SMPR2_SMP6_Pos (18U)
		3759	#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /!< 0x001C0000 /
		3760	#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /!< ADC channel 6 sampling time selection /
		3761	#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /!< 0x00040000 /
		3762	#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /!< 0x00080000 /
		3763	#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /!< 0x00100000 /
		3764
		3765	#define ADC_SMPR2_SMP7_Pos (21U)
		3766	#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /!< 0x00E00000 /
		3767	#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /!< ADC channel 7 sampling time selection /
		3768	#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /!< 0x00200000 /
		3769	#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /!< 0x00400000 /
		3770	#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /!< 0x00800000 /
		3771
		3772	#define ADC_SMPR2_SMP8_Pos (24U)
		3773	#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /!< 0x07000000 /
		3774	#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /!< ADC channel 8 sampling time selection /
		3775	#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /!< 0x01000000 /
		3776	#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /!< 0x02000000 /
		3777	#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /!< 0x04000000 /
		3778
		3779	#define ADC_SMPR2_SMP9_Pos (27U)
		3780	#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /!< 0x38000000 /
		3781	#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /!< ADC channel 9 sampling time selection /
		3782	#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /!< 0x08000000 /
		3783	#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /!< 0x10000000 /
		3784	#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /!< 0x20000000 /
		3785
		3786	/**************** Bit definition for ADC_JOFR1 register *****************/
		3787	#define ADC_JOFR1_JOFFSET1_Pos (0U)
		3788	#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /!< 0x00000FFF /
		3789	#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /!< ADC group injected sequencer rank 1 offset value /
		3790
		3791	/**************** Bit definition for ADC_JOFR2 register *****************/
		3792	#define ADC_JOFR2_JOFFSET2_Pos (0U)
		3793	#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /!< 0x00000FFF /
		3794	#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /!< ADC group injected sequencer rank 2 offset value /
		3795
		3796	/**************** Bit definition for ADC_JOFR3 register *****************/
		3797	#define ADC_JOFR3_JOFFSET3_Pos (0U)
		3798	#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /!< 0x00000FFF /
		3799	#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /!< ADC group injected sequencer rank 3 offset value /
		3800
		3801	/**************** Bit definition for ADC_JOFR4 register *****************/
		3802	#define ADC_JOFR4_JOFFSET4_Pos (0U)
		3803	#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /!< 0x00000FFF /
		3804	#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /!< ADC group injected sequencer rank 4 offset value /
		3805
		3806	/***************** Bit definition for ADC_HTR register ******************/
		3807	#define ADC_HTR_HT_Pos (0U)
		3808	#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /!< 0x00000FFF /
		3809	#define ADC_HTR_HT ADC_HTR_HT_Msk /!< ADC analog watchdog 1 threshold high /
		3810
		3811	/***************** Bit definition for ADC_LTR register ******************/
		3812	#define ADC_LTR_LT_Pos (0U)
		3813	#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /!< 0x00000FFF /
		3814	#define ADC_LTR_LT ADC_LTR_LT_Msk /!< ADC analog watchdog 1 threshold low /
		3815
		3816	/***************** Bit definition for ADC_SQR1 register *****************/
		3817	#define ADC_SQR1_SQ13_Pos (0U)
		3818	#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /!< 0x0000001F /
		3819	#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /!< ADC group regular sequencer rank 13 /
		3820	#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /!< 0x00000001 /
		3821	#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /!< 0x00000002 /
		3822	#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /!< 0x00000004 /
		3823	#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /!< 0x00000008 /
		3824	#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /!< 0x00000010 /
		3825
		3826	#define ADC_SQR1_SQ14_Pos (5U)
		3827	#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /!< 0x000003E0 /
		3828	#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /!< ADC group regular sequencer rank 14 /
		3829	#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /!< 0x00000020 /
		3830	#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /!< 0x00000040 /
		3831	#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /!< 0x00000080 /
		3832	#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /!< 0x00000100 /
		3833	#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /!< 0x00000200 /
		3834
		3835	#define ADC_SQR1_SQ15_Pos (10U)
		3836	#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /!< 0x00007C00 /
		3837	#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /!< ADC group regular sequencer rank 15 /
		3838	#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /!< 0x00000400 /
		3839	#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /!< 0x00000800 /
		3840	#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /!< 0x00001000 /
		3841	#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /!< 0x00002000 /
		3842	#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /!< 0x00004000 /
		3843
		3844	#define ADC_SQR1_SQ16_Pos (15U)
		3845	#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /!< 0x000F8000 /
		3846	#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /!< ADC group regular sequencer rank 16 /
		3847	#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /!< 0x00008000 /
		3848	#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /!< 0x00010000 /
		3849	#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /!< 0x00020000 /
		3850	#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /!< 0x00040000 /
		3851	#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /!< 0x00080000 /
		3852
		3853	#define ADC_SQR1_L_Pos (20U)
		3854	#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /!< 0x00F00000 /
		3855	#define ADC_SQR1_L ADC_SQR1_L_Msk /!< ADC group regular sequencer scan length /
		3856	#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /!< 0x00100000 /
		3857	#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /!< 0x00200000 /
		3858	#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /!< 0x00400000 /
		3859	#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /!< 0x00800000 /
		3860
		3861	/***************** Bit definition for ADC_SQR2 register *****************/
		3862	#define ADC_SQR2_SQ7_Pos (0U)
		3863	#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /!< 0x0000001F /
		3864	#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /!< ADC group regular sequencer rank 7 /
		3865	#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /!< 0x00000001 /
		3866	#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /!< 0x00000002 /
		3867	#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /!< 0x00000004 /
		3868	#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /!< 0x00000008 /
		3869	#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /!< 0x00000010 /
		3870
		3871	#define ADC_SQR2_SQ8_Pos (5U)
		3872	#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /!< 0x000003E0 /
		3873	#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /!< ADC group regular sequencer rank 8 /
		3874	#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /!< 0x00000020 /
		3875	#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /!< 0x00000040 /
		3876	#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /!< 0x00000080 /
		3877	#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /!< 0x00000100 /
		3878	#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /!< 0x00000200 /
		3879
		3880	#define ADC_SQR2_SQ9_Pos (10U)
		3881	#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /!< 0x00007C00 /
		3882	#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /!< ADC group regular sequencer rank 9 /
		3883	#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /!< 0x00000400 /
		3884	#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /!< 0x00000800 /
		3885	#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /!< 0x00001000 /
		3886	#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /!< 0x00002000 /
		3887	#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /!< 0x00004000 /
		3888
		3889	#define ADC_SQR2_SQ10_Pos (15U)
		3890	#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /!< 0x000F8000 /
		3891	#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /!< ADC group regular sequencer rank 10 /
		3892	#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /!< 0x00008000 /
		3893	#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /!< 0x00010000 /
		3894	#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /!< 0x00020000 /
		3895	#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /!< 0x00040000 /
		3896	#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /!< 0x00080000 /
		3897
		3898	#define ADC_SQR2_SQ11_Pos (20U)
		3899	#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /!< 0x01F00000 /
		3900	#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /!< ADC group regular sequencer rank 1 /
		3901	#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /!< 0x00100000 /
		3902	#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /!< 0x00200000 /
		3903	#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /!< 0x00400000 /
		3904	#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /!< 0x00800000 /
		3905	#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /!< 0x01000000 /
		3906
		3907	#define ADC_SQR2_SQ12_Pos (25U)
		3908	#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /!< 0x3E000000 /
		3909	#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /!< ADC group regular sequencer rank 12 /
		3910	#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /!< 0x02000000 /
		3911	#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /!< 0x04000000 /
		3912	#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /!< 0x08000000 /
		3913	#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /!< 0x10000000 /
		3914	#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /!< 0x20000000 /
		3915
		3916	/***************** Bit definition for ADC_SQR3 register *****************/
		3917	#define ADC_SQR3_SQ1_Pos (0U)
		3918	#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /!< 0x0000001F /
		3919	#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /!< ADC group regular sequencer rank 1 /
		3920	#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /!< 0x00000001 /
		3921	#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /!< 0x00000002 /
		3922	#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /!< 0x00000004 /
		3923	#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /!< 0x00000008 /
		3924	#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /!< 0x00000010 /
		3925
		3926	#define ADC_SQR3_SQ2_Pos (5U)
		3927	#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /!< 0x000003E0 /
		3928	#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /!< ADC group regular sequencer rank 2 /
		3929	#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /!< 0x00000020 /
		3930	#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /!< 0x00000040 /
		3931	#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /!< 0x00000080 /
		3932	#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /!< 0x00000100 /
		3933	#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /!< 0x00000200 /
		3934
		3935	#define ADC_SQR3_SQ3_Pos (10U)
		3936	#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /!< 0x00007C00 /
		3937	#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /!< ADC group regular sequencer rank 3 /
		3938	#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /!< 0x00000400 /
		3939	#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /!< 0x00000800 /
		3940	#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /!< 0x00001000 /
		3941	#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /!< 0x00002000 /
		3942	#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /!< 0x00004000 /
		3943
		3944	#define ADC_SQR3_SQ4_Pos (15U)
		3945	#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /!< 0x000F8000 /
		3946	#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /!< ADC group regular sequencer rank 4 /
		3947	#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /!< 0x00008000 /
		3948	#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /!< 0x00010000 /
		3949	#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /!< 0x00020000 /
		3950	#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /!< 0x00040000 /
		3951	#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /!< 0x00080000 /
		3952
		3953	#define ADC_SQR3_SQ5_Pos (20U)
		3954	#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /!< 0x01F00000 /
		3955	#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /!< ADC group regular sequencer rank 5 /
		3956	#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /!< 0x00100000 /
		3957	#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /!< 0x00200000 /
		3958	#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /!< 0x00400000 /
		3959	#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /!< 0x00800000 /
		3960	#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /!< 0x01000000 /
		3961
		3962	#define ADC_SQR3_SQ6_Pos (25U)
		3963	#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /!< 0x3E000000 /
		3964	#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /!< ADC group regular sequencer rank 6 /
		3965	#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /!< 0x02000000 /
		3966	#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /!< 0x04000000 /
		3967	#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /!< 0x08000000 /
		3968	#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /!< 0x10000000 /
		3969	#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /!< 0x20000000 /
		3970
		3971	/***************** Bit definition for ADC_JSQR register *****************/
		3972	#define ADC_JSQR_JSQ1_Pos (0U)
		3973	#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /!< 0x0000001F /
		3974	#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /!< ADC group injected sequencer rank 1 /
		3975	#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000001 /
		3976	#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000002 /
		3977	#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000004 /
		3978	#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000008 /
		3979	#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000010 /
		3980
		3981	#define ADC_JSQR_JSQ2_Pos (5U)
		3982	#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /!< 0x000003E0 /
		3983	#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /!< ADC group injected sequencer rank 2 /
		3984	#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000020 /
		3985	#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000040 /
		3986	#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000080 /
		3987	#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000100 /
		3988	#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000200 /
		3989
		3990	#define ADC_JSQR_JSQ3_Pos (10U)
		3991	#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /!< 0x00007C00 /
		3992	#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /!< ADC group injected sequencer rank 3 /
		3993	#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /!< 0x00000400 /
		3994	#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /!< 0x00000800 /
		3995	#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /!< 0x00001000 /
		3996	#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /!< 0x00002000 /
		3997	#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /!< 0x00004000 /
		3998
		3999	#define ADC_JSQR_JSQ4_Pos (15U)
		4000	#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /!< 0x000F8000 /
		4001	#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /!< ADC group injected sequencer rank 4 /
		4002	#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /!< 0x00008000 /
		4003	#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /!< 0x00010000 /
		4004	#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /!< 0x00020000 /
		4005	#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /!< 0x00040000 /
		4006	#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /!< 0x00080000 /
		4007
		4008	#define ADC_JSQR_JL_Pos (20U)
		4009	#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /!< 0x00300000 /
		4010	#define ADC_JSQR_JL ADC_JSQR_JL_Msk /!< ADC group injected sequencer scan length /
		4011	#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /!< 0x00100000 /
		4012	#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /!< 0x00200000 /
		4013
		4014	/***************** Bit definition for ADC_JDR1 register *****************/
		4015	#define ADC_JDR1_JDATA_Pos (0U)
		4016	#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /!< 0x0000FFFF /
		4017	#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /!< ADC group injected sequencer rank 1 conversion data /
		4018
		4019	/***************** Bit definition for ADC_JDR2 register *****************/
		4020	#define ADC_JDR2_JDATA_Pos (0U)
		4021	#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /!< 0x0000FFFF /
		4022	#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /!< ADC group injected sequencer rank 2 conversion data /
		4023
		4024	/***************** Bit definition for ADC_JDR3 register *****************/
		4025	#define ADC_JDR3_JDATA_Pos (0U)
		4026	#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /!< 0x0000FFFF /
		4027	#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /!< ADC group injected sequencer rank 3 conversion data /
		4028
		4029	/***************** Bit definition for ADC_JDR4 register *****************/
		4030	#define ADC_JDR4_JDATA_Pos (0U)
		4031	#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /!< 0x0000FFFF /
		4032	#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /!< ADC group injected sequencer rank 4 conversion data /
		4033
		4034	/****************** Bit definition for ADC_DR register ******************/
		4035	#define ADC_DR_DATA_Pos (0U)
		4036	#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /!< 0x0000FFFF /
		4037	#define ADC_DR_DATA ADC_DR_DATA_Msk /!< ADC group regular conversion data /
		4038	/******************************************************************************/
		4039	/* */
		4040	/* Digital to Analog Converter */
		4041	/* */
		4042	/******************************************************************************/
		4043
		4044	/****************** Bit definition for DAC_CR register ******************/
		4045	#define DAC_CR_EN1_Pos (0U)
		4046	#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /!< 0x00000001 /
		4047	#define DAC_CR_EN1 DAC_CR_EN1_Msk /!< DAC channel1 enable /
		4048	#define DAC_CR_BOFF1_Pos (1U)
		4049	#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /!< 0x00000002 /
		4050	#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /!< DAC channel1 output buffer disable /
		4051	#define DAC_CR_TEN1_Pos (2U)
		4052	#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /!< 0x00000004 /
		4053	#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /!< DAC channel1 Trigger enable /
		4054
		4055	#define DAC_CR_TSEL1_Pos (3U)
		4056	#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /!< 0x00000038 /
		4057	#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
		4058	#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /!< 0x00000008 /
		4059	#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /!< 0x00000010 /
		4060	#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /!< 0x00000020 /
		4061
		4062	#define DAC_CR_WAVE1_Pos (6U)
		4063	#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /!< 0x000000C0 /
		4064	#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
		4065	#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /!< 0x00000040 /
		4066	#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /!< 0x00000080 /
		4067
		4068	#define DAC_CR_MAMP1_Pos (8U)
		4069	#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /!< 0x00000F00 /
		4070	#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
		4071	#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /!< 0x00000100 /
		4072	#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /!< 0x00000200 /
		4073	#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /!< 0x00000400 /
		4074	#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /!< 0x00000800 /
		4075
		4076	#define DAC_CR_DMAEN1_Pos (12U)
		4077	#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /!< 0x00001000 /
		4078	#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /!< DAC channel1 DMA enable /
		4079	#define DAC_CR_EN2_Pos (16U)
		4080	#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /!< 0x00010000 /
		4081	#define DAC_CR_EN2 DAC_CR_EN2_Msk /!< DAC channel2 enable /
		4082	#define DAC_CR_BOFF2_Pos (17U)
		4083	#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /!< 0x00020000 /
		4084	#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /!< DAC channel2 output buffer disable /
		4085	#define DAC_CR_TEN2_Pos (18U)
		4086	#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /!< 0x00040000 /
		4087	#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /!< DAC channel2 Trigger enable /
		4088
		4089	#define DAC_CR_TSEL2_Pos (19U)
		4090	#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /!< 0x00380000 /
		4091	#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
		4092	#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /!< 0x00080000 /
		4093	#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /!< 0x00100000 /
		4094	#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /!< 0x00200000 /
		4095
		4096	#define DAC_CR_WAVE2_Pos (22U)
		4097	#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /!< 0x00C00000 /
		4098	#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
		4099	#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /!< 0x00400000 /
		4100	#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /!< 0x00800000 /
		4101
		4102	#define DAC_CR_MAMP2_Pos (24U)
		4103	#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /!< 0x0F000000 /
		4104	#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
		4105	#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /!< 0x01000000 /
		4106	#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /!< 0x02000000 /
		4107	#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /!< 0x04000000 /
		4108	#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /!< 0x08000000 /
		4109
		4110	#define DAC_CR_DMAEN2_Pos (28U)
		4111	#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /!< 0x10000000 /
		4112	#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /!< DAC channel2 DMA enabled /
		4113
		4114
		4115	/*************** Bit definition for DAC_SWTRIGR register ****************/
		4116	#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
		4117	#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /!< 0x00000001 /
		4118	#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /!< DAC channel1 software trigger /
		4119	#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
		4120	#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /!< 0x00000002 /
		4121	#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /!< DAC channel2 software trigger /
		4122
		4123	/*************** Bit definition for DAC_DHR12R1 register ****************/
		4124	#define DAC_DHR12R1_DACC1DHR_Pos (0U)
		4125	#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /!< 0x00000FFF /
		4126	#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /!< DAC channel1 12-bit Right aligned data /
		4127
		4128	/*************** Bit definition for DAC_DHR12L1 register ****************/
		4129	#define DAC_DHR12L1_DACC1DHR_Pos (4U)
		4130	#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /!< 0x0000FFF0 /
		4131	#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /!< DAC channel1 12-bit Left aligned data /
		4132
		4133	/**************** Bit definition for DAC_DHR8R1 register ****************/
		4134	#define DAC_DHR8R1_DACC1DHR_Pos (0U)
		4135	#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /!< 0x000000FF /
		4136	#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /!< DAC channel1 8-bit Right aligned data /
		4137
		4138	/*************** Bit definition for DAC_DHR12R2 register ****************/
		4139	#define DAC_DHR12R2_DACC2DHR_Pos (0U)
		4140	#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /!< 0x00000FFF /
		4141	#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /!< DAC channel2 12-bit Right aligned data /
		4142
		4143	/*************** Bit definition for DAC_DHR12L2 register ****************/
		4144	#define DAC_DHR12L2_DACC2DHR_Pos (4U)
		4145	#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /!< 0x0000FFF0 /
		4146	#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /!< DAC channel2 12-bit Left aligned data /
		4147
		4148	/**************** Bit definition for DAC_DHR8R2 register ****************/
		4149	#define DAC_DHR8R2_DACC2DHR_Pos (0U)
		4150	#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /!< 0x000000FF /
		4151	#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /!< DAC channel2 8-bit Right aligned data /
		4152
		4153	/*************** Bit definition for DAC_DHR12RD register ****************/
		4154	#define DAC_DHR12RD_DACC1DHR_Pos (0U)
		4155	#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /!< 0x00000FFF /
		4156	#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /!< DAC channel1 12-bit Right aligned data /
		4157	#define DAC_DHR12RD_DACC2DHR_Pos (16U)
		4158	#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /!< 0x0FFF0000 /
		4159	#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /!< DAC channel2 12-bit Right aligned data /
		4160
		4161	/*************** Bit definition for DAC_DHR12LD register ****************/
		4162	#define DAC_DHR12LD_DACC1DHR_Pos (4U)
		4163	#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /!< 0x0000FFF0 /
		4164	#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /!< DAC channel1 12-bit Left aligned data /
		4165	#define DAC_DHR12LD_DACC2DHR_Pos (20U)
		4166	#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /!< 0xFFF00000 /
		4167	#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /!< DAC channel2 12-bit Left aligned data /
		4168
		4169	/**************** Bit definition for DAC_DHR8RD register ****************/
		4170	#define DAC_DHR8RD_DACC1DHR_Pos (0U)
		4171	#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /!< 0x000000FF /
		4172	#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /!< DAC channel1 8-bit Right aligned data /
		4173	#define DAC_DHR8RD_DACC2DHR_Pos (8U)
		4174	#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /!< 0x0000FF00 /
		4175	#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /!< DAC channel2 8-bit Right aligned data /
		4176
		4177	/***************** Bit definition for DAC_DOR1 register *****************/
		4178	#define DAC_DOR1_DACC1DOR_Pos (0U)
		4179	#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /!< 0x00000FFF /
		4180	#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /!< DAC channel1 data output /
		4181
		4182	/***************** Bit definition for DAC_DOR2 register *****************/
		4183	#define DAC_DOR2_DACC2DOR_Pos (0U)
		4184	#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /!< 0x00000FFF /
		4185	#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /!< DAC channel2 data output /
		4186
		4187
		4188
		4189	/*****************************************************************************/
		4190	/* */
		4191	/* Timers (TIM) */
		4192	/* */
		4193	/*****************************************************************************/
		4194	/***************** Bit definition for TIM_CR1 register *****************/
		4195	#define TIM_CR1_CEN_Pos (0U)
		4196	#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /!< 0x00000001 /
		4197	#define TIM_CR1_CEN TIM_CR1_CEN_Msk /!<Counter enable /
		4198	#define TIM_CR1_UDIS_Pos (1U)
		4199	#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /!< 0x00000002 /
		4200	#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /!<Update disable /
		4201	#define TIM_CR1_URS_Pos (2U)
		4202	#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /!< 0x00000004 /
		4203	#define TIM_CR1_URS TIM_CR1_URS_Msk /!<Update request source /
		4204	#define TIM_CR1_OPM_Pos (3U)
		4205	#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /!< 0x00000008 /
		4206	#define TIM_CR1_OPM TIM_CR1_OPM_Msk /!<One pulse mode /
		4207	#define TIM_CR1_DIR_Pos (4U)
		4208	#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /!< 0x00000010 /
		4209	#define TIM_CR1_DIR TIM_CR1_DIR_Msk /!<Direction /
		4210
		4211	#define TIM_CR1_CMS_Pos (5U)
		4212	#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /!< 0x00000060 /
		4213	#define TIM_CR1_CMS TIM_CR1_CMS_Msk /!<CMS[1:0] bits (Center-aligned mode selection) /
		4214	#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /!< 0x00000020 /
		4215	#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /!< 0x00000040 /
		4216
		4217	#define TIM_CR1_ARPE_Pos (7U)
		4218	#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /!< 0x00000080 /
		4219	#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /!<Auto-reload preload enable /
		4220
		4221	#define TIM_CR1_CKD_Pos (8U)
		4222	#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /!< 0x00000300 /
		4223	#define TIM_CR1_CKD TIM_CR1_CKD_Msk /!<CKD[1:0] bits (clock division) /
		4224	#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /!< 0x00000100 /
		4225	#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /!< 0x00000200 /
		4226
		4227	/***************** Bit definition for TIM_CR2 register *****************/
		4228	#define TIM_CR2_CCPC_Pos (0U)
		4229	#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /!< 0x00000001 /
		4230	#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /!<Capture/Compare Preloaded Control /
		4231	#define TIM_CR2_CCUS_Pos (2U)
		4232	#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /!< 0x00000004 /
		4233	#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /!<Capture/Compare Control Update Selection /
		4234	#define TIM_CR2_CCDS_Pos (3U)
		4235	#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /!< 0x00000008 /
		4236	#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /!<Capture/Compare DMA Selection /
		4237
		4238	#define TIM_CR2_MMS_Pos (4U)
		4239	#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /!< 0x00000070 /
		4240	#define TIM_CR2_MMS TIM_CR2_MMS_Msk /!<MMS[2:0] bits (Master Mode Selection) /
		4241	#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /!< 0x00000010 /
		4242	#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /!< 0x00000020 /
		4243	#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /!< 0x00000040 /
		4244
		4245	#define TIM_CR2_TI1S_Pos (7U)
		4246	#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /!< 0x00000080 /
		4247	#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /!<TI1 Selection /
		4248	#define TIM_CR2_OIS1_Pos (8U)
		4249	#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /!< 0x00000100 /
		4250	#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /!<Output Idle state 1 (OC1 output) /
		4251	#define TIM_CR2_OIS1N_Pos (9U)
		4252	#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /!< 0x00000200 /
		4253	#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /!<Output Idle state 1 (OC1N output) /
		4254	#define TIM_CR2_OIS2_Pos (10U)
		4255	#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /!< 0x00000400 /
		4256	#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /!<Output Idle state 2 (OC2 output) /
		4257	#define TIM_CR2_OIS2N_Pos (11U)
		4258	#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /!< 0x00000800 /
		4259	#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /!<Output Idle state 2 (OC2N output) /
		4260	#define TIM_CR2_OIS3_Pos (12U)
		4261	#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /!< 0x00001000 /
		4262	#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /!<Output Idle state 3 (OC3 output) /
		4263	#define TIM_CR2_OIS3N_Pos (13U)
		4264	#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /!< 0x00002000 /
		4265	#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /!<Output Idle state 3 (OC3N output) /
		4266	#define TIM_CR2_OIS4_Pos (14U)
		4267	#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /!< 0x00004000 /
		4268	#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /!<Output Idle state 4 (OC4 output) /
		4269
		4270	/***************** Bit definition for TIM_SMCR register ****************/
		4271	#define TIM_SMCR_SMS_Pos (0U)
		4272	#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /!< 0x00000007 /
		4273	#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /!<SMS[2:0] bits (Slave mode selection) /
		4274	#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /!< 0x00000001 /
		4275	#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /!< 0x00000002 /
		4276	#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /!< 0x00000004 /
		4277
		4278	#define TIM_SMCR_TS_Pos (4U)
		4279	#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /!< 0x00000070 /
		4280	#define TIM_SMCR_TS TIM_SMCR_TS_Msk /!<TS[2:0] bits (Trigger selection) /
		4281	#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /!< 0x00000010 /
		4282	#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /!< 0x00000020 /
		4283	#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /!< 0x00000040 /
		4284
		4285	#define TIM_SMCR_MSM_Pos (7U)
		4286	#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /!< 0x00000080 /
		4287	#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /!<Master/slave mode /
		4288
		4289	#define TIM_SMCR_ETF_Pos (8U)
		4290	#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /!< 0x00000F00 /
		4291	#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /!<ETF[3:0] bits (External trigger filter) /
		4292	#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /!< 0x00000100 /
		4293	#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /!< 0x00000200 /
		4294	#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /!< 0x00000400 /
		4295	#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /!< 0x00000800 /
		4296
		4297	#define TIM_SMCR_ETPS_Pos (12U)
		4298	#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /!< 0x00003000 /
		4299	#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /!<ETPS[1:0] bits (External trigger prescaler) /
		4300	#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /!< 0x00001000 /
		4301	#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /!< 0x00002000 /
		4302
		4303	#define TIM_SMCR_ECE_Pos (14U)
		4304	#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /!< 0x00004000 /
		4305	#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /!<External clock enable /
		4306	#define TIM_SMCR_ETP_Pos (15U)
		4307	#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /!< 0x00008000 /
		4308	#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /!<External trigger polarity /
		4309
		4310	/***************** Bit definition for TIM_DIER register ****************/
		4311	#define TIM_DIER_UIE_Pos (0U)
		4312	#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /!< 0x00000001 /
		4313	#define TIM_DIER_UIE TIM_DIER_UIE_Msk /!<Update interrupt enable /
		4314	#define TIM_DIER_CC1IE_Pos (1U)
		4315	#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /!< 0x00000002 /
		4316	#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /!<Capture/Compare 1 interrupt enable /
		4317	#define TIM_DIER_CC2IE_Pos (2U)
		4318	#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /!< 0x00000004 /
		4319	#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /!<Capture/Compare 2 interrupt enable /
		4320	#define TIM_DIER_CC3IE_Pos (3U)
		4321	#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /!< 0x00000008 /
		4322	#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /!<Capture/Compare 3 interrupt enable /
		4323	#define TIM_DIER_CC4IE_Pos (4U)
		4324	#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /!< 0x00000010 /
		4325	#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /!<Capture/Compare 4 interrupt enable /
		4326	#define TIM_DIER_COMIE_Pos (5U)
		4327	#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /!< 0x00000020 /
		4328	#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /!<COM interrupt enable /
		4329	#define TIM_DIER_TIE_Pos (6U)
		4330	#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /!< 0x00000040 /
		4331	#define TIM_DIER_TIE TIM_DIER_TIE_Msk /!<Trigger interrupt enable /
		4332	#define TIM_DIER_BIE_Pos (7U)
		4333	#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /!< 0x00000080 /
		4334	#define TIM_DIER_BIE TIM_DIER_BIE_Msk /!<Break interrupt enable /
		4335	#define TIM_DIER_UDE_Pos (8U)
		4336	#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /!< 0x00000100 /
		4337	#define TIM_DIER_UDE TIM_DIER_UDE_Msk /!<Update DMA request enable /
		4338	#define TIM_DIER_CC1DE_Pos (9U)
		4339	#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /!< 0x00000200 /
		4340	#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /!<Capture/Compare 1 DMA request enable /
		4341	#define TIM_DIER_CC2DE_Pos (10U)
		4342	#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /!< 0x00000400 /
		4343	#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /!<Capture/Compare 2 DMA request enable /
		4344	#define TIM_DIER_CC3DE_Pos (11U)
		4345	#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /!< 0x00000800 /
		4346	#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /!<Capture/Compare 3 DMA request enable /
		4347	#define TIM_DIER_CC4DE_Pos (12U)
		4348	#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /!< 0x00001000 /
		4349	#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /!<Capture/Compare 4 DMA request enable /
		4350	#define TIM_DIER_COMDE_Pos (13U)
		4351	#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /!< 0x00002000 /
		4352	#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /!<COM DMA request enable /
		4353	#define TIM_DIER_TDE_Pos (14U)
		4354	#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /!< 0x00004000 /
		4355	#define TIM_DIER_TDE TIM_DIER_TDE_Msk /!<Trigger DMA request enable /
		4356
		4357	/****************** Bit definition for TIM_SR register *****************/
		4358	#define TIM_SR_UIF_Pos (0U)
		4359	#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /!< 0x00000001 /
		4360	#define TIM_SR_UIF TIM_SR_UIF_Msk /!<Update interrupt Flag /
		4361	#define TIM_SR_CC1IF_Pos (1U)
		4362	#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /!< 0x00000002 /
		4363	#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /!<Capture/Compare 1 interrupt Flag /
		4364	#define TIM_SR_CC2IF_Pos (2U)
		4365	#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /!< 0x00000004 /
		4366	#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /!<Capture/Compare 2 interrupt Flag /
		4367	#define TIM_SR_CC3IF_Pos (3U)
		4368	#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /!< 0x00000008 /
		4369	#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /!<Capture/Compare 3 interrupt Flag /
		4370	#define TIM_SR_CC4IF_Pos (4U)
		4371	#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /!< 0x00000010 /
		4372	#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /!<Capture/Compare 4 interrupt Flag /
		4373	#define TIM_SR_COMIF_Pos (5U)
		4374	#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /!< 0x00000020 /
		4375	#define TIM_SR_COMIF TIM_SR_COMIF_Msk /!<COM interrupt Flag /
		4376	#define TIM_SR_TIF_Pos (6U)
		4377	#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /!< 0x00000040 /
		4378	#define TIM_SR_TIF TIM_SR_TIF_Msk /!<Trigger interrupt Flag /
		4379	#define TIM_SR_BIF_Pos (7U)
		4380	#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /!< 0x00000080 /
		4381	#define TIM_SR_BIF TIM_SR_BIF_Msk /!<Break interrupt Flag /
		4382	#define TIM_SR_CC1OF_Pos (9U)
		4383	#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /!< 0x00000200 /
		4384	#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /!<Capture/Compare 1 Overcapture Flag /
		4385	#define TIM_SR_CC2OF_Pos (10U)
		4386	#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /!< 0x00000400 /
		4387	#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /!<Capture/Compare 2 Overcapture Flag /
		4388	#define TIM_SR_CC3OF_Pos (11U)
		4389	#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /!< 0x00000800 /
		4390	#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /!<Capture/Compare 3 Overcapture Flag /
		4391	#define TIM_SR_CC4OF_Pos (12U)
		4392	#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /!< 0x00001000 /
		4393	#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /!<Capture/Compare 4 Overcapture Flag /
		4394
		4395	/***************** Bit definition for TIM_EGR register *****************/
		4396	#define TIM_EGR_UG_Pos (0U)
		4397	#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /!< 0x00000001 /
		4398	#define TIM_EGR_UG TIM_EGR_UG_Msk /!<Update Generation /
		4399	#define TIM_EGR_CC1G_Pos (1U)
		4400	#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /!< 0x00000002 /
		4401	#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /!<Capture/Compare 1 Generation /
		4402	#define TIM_EGR_CC2G_Pos (2U)
		4403	#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /!< 0x00000004 /
		4404	#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /!<Capture/Compare 2 Generation /
		4405	#define TIM_EGR_CC3G_Pos (3U)
		4406	#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /!< 0x00000008 /
		4407	#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /!<Capture/Compare 3 Generation /
		4408	#define TIM_EGR_CC4G_Pos (4U)
		4409	#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /!< 0x00000010 /
		4410	#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /!<Capture/Compare 4 Generation /
		4411	#define TIM_EGR_COMG_Pos (5U)
		4412	#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /!< 0x00000020 /
		4413	#define TIM_EGR_COMG TIM_EGR_COMG_Msk /!<Capture/Compare Control Update Generation /
		4414	#define TIM_EGR_TG_Pos (6U)
		4415	#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /!< 0x00000040 /
		4416	#define TIM_EGR_TG TIM_EGR_TG_Msk /!<Trigger Generation /
		4417	#define TIM_EGR_BG_Pos (7U)
		4418	#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /!< 0x00000080 /
		4419	#define TIM_EGR_BG TIM_EGR_BG_Msk /!<Break Generation /
		4420
		4421	/**************** Bit definition for TIM_CCMR1 register ****************/
		4422	#define TIM_CCMR1_CC1S_Pos (0U)
		4423	#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /!< 0x00000003 /
		4424	#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
		4425	#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /!< 0x00000001 /
		4426	#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /!< 0x00000002 /
		4427
		4428	#define TIM_CCMR1_OC1FE_Pos (2U)
		4429	#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /!< 0x00000004 /
		4430	#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /!<Output Compare 1 Fast enable /
		4431	#define TIM_CCMR1_OC1PE_Pos (3U)
		4432	#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /!< 0x00000008 /
		4433	#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /!<Output Compare 1 Preload enable /
		4434
		4435	#define TIM_CCMR1_OC1M_Pos (4U)
		4436	#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000070 /
		4437	#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /!<OC1M[2:0] bits (Output Compare 1 Mode) /
		4438	#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000010 /
		4439	#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000020 /
		4440	#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000040 /
		4441
		4442	#define TIM_CCMR1_OC1CE_Pos (7U)
		4443	#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /!< 0x00000080 /
		4444	#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /!<Output Compare 1Clear Enable /
		4445
		4446	#define TIM_CCMR1_CC2S_Pos (8U)
		4447	#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /!< 0x00000300 /
		4448	#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
		4449	#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /!< 0x00000100 /
		4450	#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /!< 0x00000200 /
		4451
		4452	#define TIM_CCMR1_OC2FE_Pos (10U)
		4453	#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /!< 0x00000400 /
		4454	#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /!<Output Compare 2 Fast enable /
		4455	#define TIM_CCMR1_OC2PE_Pos (11U)
		4456	#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /!< 0x00000800 /
		4457	#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /!<Output Compare 2 Preload enable /
		4458
		4459	#define TIM_CCMR1_OC2M_Pos (12U)
		4460	#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /!< 0x00007000 /
		4461	#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /!<OC2M[2:0] bits (Output Compare 2 Mode) /
		4462	#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /!< 0x00001000 /
		4463	#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /!< 0x00002000 /
		4464	#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /!< 0x00004000 /
		4465
		4466	#define TIM_CCMR1_OC2CE_Pos (15U)
		4467	#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /!< 0x00008000 /
		4468	#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /!<Output Compare 2 Clear Enable /
		4469
		4470	/---------------------------------------------------------------------------/
		4471
		4472	#define TIM_CCMR1_IC1PSC_Pos (2U)
		4473	#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /!< 0x0000000C /
		4474	#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
		4475	#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000004 /
		4476	#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000008 /
		4477
		4478	#define TIM_CCMR1_IC1F_Pos (4U)
		4479	#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /!< 0x000000F0 /
		4480	#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /!<IC1F[3:0] bits (Input Capture 1 Filter) /
		4481	#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000010 /
		4482	#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000020 /
		4483	#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000040 /
		4484	#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000080 /
		4485
		4486	#define TIM_CCMR1_IC2PSC_Pos (10U)
		4487	#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000C00 /
		4488	#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
		4489	#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000400 /
		4490	#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000800 /
		4491
		4492	#define TIM_CCMR1_IC2F_Pos (12U)
		4493	#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /!< 0x0000F000 /
		4494	#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /!<IC2F[3:0] bits (Input Capture 2 Filter) /
		4495	#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /!< 0x00001000 /
		4496	#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /!< 0x00002000 /
		4497	#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /!< 0x00004000 /
		4498	#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /!< 0x00008000 /
		4499
		4500	/**************** Bit definition for TIM_CCMR2 register ****************/
		4501	#define TIM_CCMR2_CC3S_Pos (0U)
		4502	#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /!< 0x00000003 /
		4503	#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
		4504	#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /!< 0x00000001 /
		4505	#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /!< 0x00000002 /
		4506
		4507	#define TIM_CCMR2_OC3FE_Pos (2U)
		4508	#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /!< 0x00000004 /
		4509	#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /!<Output Compare 3 Fast enable /
		4510	#define TIM_CCMR2_OC3PE_Pos (3U)
		4511	#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /!< 0x00000008 /
		4512	#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /!<Output Compare 3 Preload enable /
		4513
		4514	#define TIM_CCMR2_OC3M_Pos (4U)
		4515	#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000070 /
		4516	#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /!<OC3M[2:0] bits (Output Compare 3 Mode) /
		4517	#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000010 /
		4518	#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000020 /
		4519	#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000040 /
		4520
		4521	#define TIM_CCMR2_OC3CE_Pos (7U)
		4522	#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /!< 0x00000080 /
		4523	#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /!<Output Compare 3 Clear Enable /
		4524
		4525	#define TIM_CCMR2_CC4S_Pos (8U)
		4526	#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /!< 0x00000300 /
		4527	#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
		4528	#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /!< 0x00000100 /
		4529	#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /!< 0x00000200 /
		4530
		4531	#define TIM_CCMR2_OC4FE_Pos (10U)
		4532	#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /!< 0x00000400 /
		4533	#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /!<Output Compare 4 Fast enable /
		4534	#define TIM_CCMR2_OC4PE_Pos (11U)
		4535	#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /!< 0x00000800 /
		4536	#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /!<Output Compare 4 Preload enable /
		4537
		4538	#define TIM_CCMR2_OC4M_Pos (12U)
		4539	#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /!< 0x00007000 /
		4540	#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /!<OC4M[2:0] bits (Output Compare 4 Mode) /
		4541	#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /!< 0x00001000 /
		4542	#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /!< 0x00002000 /
		4543	#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /!< 0x00004000 /
		4544
		4545	#define TIM_CCMR2_OC4CE_Pos (15U)
		4546	#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /!< 0x00008000 /
		4547	#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /!<Output Compare 4 Clear Enable /
		4548
		4549	/---------------------------------------------------------------------------/
		4550
		4551	#define TIM_CCMR2_IC3PSC_Pos (2U)
		4552	#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /!< 0x0000000C /
		4553	#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
		4554	#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000004 /
		4555	#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000008 /
		4556
		4557	#define TIM_CCMR2_IC3F_Pos (4U)
		4558	#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /!< 0x000000F0 /
		4559	#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /!<IC3F[3:0] bits (Input Capture 3 Filter) /
		4560	#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000010 /
		4561	#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000020 /
		4562	#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000040 /
		4563	#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000080 /
		4564
		4565	#define TIM_CCMR2_IC4PSC_Pos (10U)
		4566	#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000C00 /
		4567	#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
		4568	#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000400 /
		4569	#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000800 /
		4570
		4571	#define TIM_CCMR2_IC4F_Pos (12U)
		4572	#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /!< 0x0000F000 /
		4573	#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /!<IC4F[3:0] bits (Input Capture 4 Filter) /
		4574	#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /!< 0x00001000 /
		4575	#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /!< 0x00002000 /
		4576	#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /!< 0x00004000 /
		4577	#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /!< 0x00008000 /
		4578
		4579	/***************** Bit definition for TIM_CCER register ****************/
		4580	#define TIM_CCER_CC1E_Pos (0U)
		4581	#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /!< 0x00000001 /
		4582	#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /!<Capture/Compare 1 output enable /
		4583	#define TIM_CCER_CC1P_Pos (1U)
		4584	#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /!< 0x00000002 /
		4585	#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /!<Capture/Compare 1 output Polarity /
		4586	#define TIM_CCER_CC1NE_Pos (2U)
		4587	#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /!< 0x00000004 /
		4588	#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /!<Capture/Compare 1 Complementary output enable /
		4589	#define TIM_CCER_CC1NP_Pos (3U)
		4590	#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /!< 0x00000008 /
		4591	#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /!<Capture/Compare 1 Complementary output Polarity /
		4592	#define TIM_CCER_CC2E_Pos (4U)
		4593	#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /!< 0x00000010 /
		4594	#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /!<Capture/Compare 2 output enable /
		4595	#define TIM_CCER_CC2P_Pos (5U)
		4596	#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /!< 0x00000020 /
		4597	#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /!<Capture/Compare 2 output Polarity /
		4598	#define TIM_CCER_CC2NE_Pos (6U)
		4599	#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /!< 0x00000040 /
		4600	#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /!<Capture/Compare 2 Complementary output enable /
		4601	#define TIM_CCER_CC2NP_Pos (7U)
		4602	#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /!< 0x00000080 /
		4603	#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /!<Capture/Compare 2 Complementary output Polarity /
		4604	#define TIM_CCER_CC3E_Pos (8U)
		4605	#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /!< 0x00000100 /
		4606	#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /!<Capture/Compare 3 output enable /
		4607	#define TIM_CCER_CC3P_Pos (9U)
		4608	#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /!< 0x00000200 /
		4609	#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /!<Capture/Compare 3 output Polarity /
		4610	#define TIM_CCER_CC3NE_Pos (10U)
		4611	#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /!< 0x00000400 /
		4612	#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /!<Capture/Compare 3 Complementary output enable /
		4613	#define TIM_CCER_CC3NP_Pos (11U)
		4614	#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /!< 0x00000800 /
		4615	#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /!<Capture/Compare 3 Complementary output Polarity /
		4616	#define TIM_CCER_CC4E_Pos (12U)
		4617	#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /!< 0x00001000 /
		4618	#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /!<Capture/Compare 4 output enable /
		4619	#define TIM_CCER_CC4P_Pos (13U)
		4620	#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /!< 0x00002000 /
		4621	#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /!<Capture/Compare 4 output Polarity /
		4622
		4623	/***************** Bit definition for TIM_CNT register *****************/
		4624	#define TIM_CNT_CNT_Pos (0U)
		4625	#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /!< 0xFFFFFFFF /
		4626	#define TIM_CNT_CNT TIM_CNT_CNT_Msk /!<Counter Value /
		4627
		4628	/***************** Bit definition for TIM_PSC register *****************/
		4629	#define TIM_PSC_PSC_Pos (0U)
		4630	#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /!< 0x0000FFFF /
		4631	#define TIM_PSC_PSC TIM_PSC_PSC_Msk /!<Prescaler Value /
		4632
		4633	/***************** Bit definition for TIM_ARR register *****************/
		4634	#define TIM_ARR_ARR_Pos (0U)
		4635	#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /!< 0xFFFFFFFF /
		4636	#define TIM_ARR_ARR TIM_ARR_ARR_Msk /!<actual auto-reload Value /
		4637
		4638	/***************** Bit definition for TIM_RCR register *****************/
		4639	#define TIM_RCR_REP_Pos (0U)
		4640	#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /!< 0x000000FF /
		4641	#define TIM_RCR_REP TIM_RCR_REP_Msk /!<Repetition Counter Value /
		4642
		4643	/***************** Bit definition for TIM_CCR1 register ****************/
		4644	#define TIM_CCR1_CCR1_Pos (0U)
		4645	#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /!< 0x0000FFFF /
		4646	#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /!<Capture/Compare 1 Value /
		4647
		4648	/***************** Bit definition for TIM_CCR2 register ****************/
		4649	#define TIM_CCR2_CCR2_Pos (0U)
		4650	#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /!< 0x0000FFFF /
		4651	#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /!<Capture/Compare 2 Value /
		4652
		4653	/***************** Bit definition for TIM_CCR3 register ****************/
		4654	#define TIM_CCR3_CCR3_Pos (0U)
		4655	#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /!< 0x0000FFFF /
		4656	#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /!<Capture/Compare 3 Value /
		4657
		4658	/***************** Bit definition for TIM_CCR4 register ****************/
		4659	#define TIM_CCR4_CCR4_Pos (0U)
		4660	#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /!< 0x0000FFFF /
		4661	#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /!<Capture/Compare 4 Value /
		4662
		4663	/***************** Bit definition for TIM_BDTR register ****************/
		4664	#define TIM_BDTR_DTG_Pos (0U)
		4665	#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /!< 0x000000FF /
		4666	#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /!<DTG[0:7] bits (Dead-Time Generator set-up) /
		4667	#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /!< 0x00000001 /
		4668	#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /!< 0x00000002 /
		4669	#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /!< 0x00000004 /
		4670	#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /!< 0x00000008 /
		4671	#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /!< 0x00000010 /
		4672	#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /!< 0x00000020 /
		4673	#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /!< 0x00000040 /
		4674	#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /!< 0x00000080 /
		4675
		4676	#define TIM_BDTR_LOCK_Pos (8U)
		4677	#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /!< 0x00000300 /
		4678	#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /!<LOCK[1:0] bits (Lock Configuration) /
		4679	#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /!< 0x00000100 /
		4680	#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /!< 0x00000200 /
		4681
		4682	#define TIM_BDTR_OSSI_Pos (10U)
		4683	#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /!< 0x00000400 /
		4684	#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /!<Off-State Selection for Idle mode /
		4685	#define TIM_BDTR_OSSR_Pos (11U)
		4686	#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /!< 0x00000800 /
		4687	#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /!<Off-State Selection for Run mode /
		4688	#define TIM_BDTR_BKE_Pos (12U)
		4689	#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /!< 0x00001000 /
		4690	#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /!<Break enable /
		4691	#define TIM_BDTR_BKP_Pos (13U)
		4692	#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /!< 0x00002000 /
		4693	#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /!<Break Polarity /
		4694	#define TIM_BDTR_AOE_Pos (14U)
		4695	#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /!< 0x00004000 /
		4696	#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /!<Automatic Output enable /
		4697	#define TIM_BDTR_MOE_Pos (15U)
		4698	#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /!< 0x00008000 /
		4699	#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /!<Main Output enable /
		4700
		4701	/***************** Bit definition for TIM_DCR register *****************/
		4702	#define TIM_DCR_DBA_Pos (0U)
		4703	#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /!< 0x0000001F /
		4704	#define TIM_DCR_DBA TIM_DCR_DBA_Msk /!<DBA[4:0] bits (DMA Base Address) /
		4705	#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /!< 0x00000001 /
		4706	#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /!< 0x00000002 /
		4707	#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /!< 0x00000004 /
		4708	#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /!< 0x00000008 /
		4709	#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /!< 0x00000010 /
		4710
		4711	#define TIM_DCR_DBL_Pos (8U)
		4712	#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /!< 0x00001F00 /
		4713	#define TIM_DCR_DBL TIM_DCR_DBL_Msk /!<DBL[4:0] bits (DMA Burst Length) /
		4714	#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /!< 0x00000100 /
		4715	#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /!< 0x00000200 /
		4716	#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /!< 0x00000400 /
		4717	#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /!< 0x00000800 /
		4718	#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /!< 0x00001000 /
		4719
		4720	/***************** Bit definition for TIM_DMAR register ****************/
		4721	#define TIM_DMAR_DMAB_Pos (0U)
		4722	#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /!< 0x0000FFFF /
		4723	#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /!<DMA register for burst accesses /
		4724
		4725	/******************************************************************************/
		4726	/* */
		4727	/* Real-Time Clock */
		4728	/* */
		4729	/******************************************************************************/
		4730
		4731	/***************** Bit definition for RTC_CRH register ******************/
		4732	#define RTC_CRH_SECIE_Pos (0U)
		4733	#define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /!< 0x00000001 /
		4734	#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /!< Second Interrupt Enable /
		4735	#define RTC_CRH_ALRIE_Pos (1U)
		4736	#define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /!< 0x00000002 /
		4737	#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /!< Alarm Interrupt Enable /
		4738	#define RTC_CRH_OWIE_Pos (2U)
		4739	#define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /!< 0x00000004 /
		4740	#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /!< OverfloW Interrupt Enable /
		4741
		4742	/***************** Bit definition for RTC_CRL register ******************/
		4743	#define RTC_CRL_SECF_Pos (0U)
		4744	#define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /!< 0x00000001 /
		4745	#define RTC_CRL_SECF RTC_CRL_SECF_Msk /!< Second Flag /
		4746	#define RTC_CRL_ALRF_Pos (1U)
		4747	#define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /!< 0x00000002 /
		4748	#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /!< Alarm Flag /
		4749	#define RTC_CRL_OWF_Pos (2U)
		4750	#define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /!< 0x00000004 /
		4751	#define RTC_CRL_OWF RTC_CRL_OWF_Msk /!< OverfloW Flag /
		4752	#define RTC_CRL_RSF_Pos (3U)
		4753	#define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /!< 0x00000008 /
		4754	#define RTC_CRL_RSF RTC_CRL_RSF_Msk /!< Registers Synchronized Flag /
		4755	#define RTC_CRL_CNF_Pos (4U)
		4756	#define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /!< 0x00000010 /
		4757	#define RTC_CRL_CNF RTC_CRL_CNF_Msk /!< Configuration Flag /
		4758	#define RTC_CRL_RTOFF_Pos (5U)
		4759	#define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /!< 0x00000020 /
		4760	#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /!< RTC operation OFF /
		4761
		4762	/***************** Bit definition for RTC_PRLH register *****************/
		4763	#define RTC_PRLH_PRL_Pos (0U)
		4764	#define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /!< 0x0000000F /
		4765	#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /!< RTC Prescaler Reload Value High /
		4766
		4767	/***************** Bit definition for RTC_PRLL register *****************/
		4768	#define RTC_PRLL_PRL_Pos (0U)
		4769	#define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /!< 0x0000FFFF /
		4770	#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /!< RTC Prescaler Reload Value Low /
		4771
		4772	/***************** Bit definition for RTC_DIVH register *****************/
		4773	#define RTC_DIVH_RTC_DIV_Pos (0U)
		4774	#define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /!< 0x0000000F /
		4775	#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /!< RTC Clock Divider High /
		4776
		4777	/***************** Bit definition for RTC_DIVL register *****************/
		4778	#define RTC_DIVL_RTC_DIV_Pos (0U)
		4779	#define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /!< 0x0000FFFF /
		4780	#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /!< RTC Clock Divider Low /
		4781
		4782	/***************** Bit definition for RTC_CNTH register *****************/
		4783	#define RTC_CNTH_RTC_CNT_Pos (0U)
		4784	#define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /!< 0x0000FFFF /
		4785	#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /!< RTC Counter High /
		4786
		4787	/***************** Bit definition for RTC_CNTL register *****************/
		4788	#define RTC_CNTL_RTC_CNT_Pos (0U)
		4789	#define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /!< 0x0000FFFF /
		4790	#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /!< RTC Counter Low /
		4791
		4792	/***************** Bit definition for RTC_ALRH register *****************/
		4793	#define RTC_ALRH_RTC_ALR_Pos (0U)
		4794	#define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /!< 0x0000FFFF /
		4795	#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /!< RTC Alarm High /
		4796
		4797	/***************** Bit definition for RTC_ALRL register *****************/
		4798	#define RTC_ALRL_RTC_ALR_Pos (0U)
		4799	#define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /!< 0x0000FFFF /
		4800	#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /!< RTC Alarm Low /
		4801
		4802	/******************************************************************************/
		4803	/* */
		4804	/* Independent WATCHDOG (IWDG) */
		4805	/* */
		4806	/******************************************************************************/
		4807
		4808	/***************** Bit definition for IWDG_KR register ******************/
		4809	#define IWDG_KR_KEY_Pos (0U)
		4810	#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /!< 0x0000FFFF /
		4811	#define IWDG_KR_KEY IWDG_KR_KEY_Msk /!< Key value (write only, read 0000h) /
		4812
		4813	/***************** Bit definition for IWDG_PR register ******************/
		4814	#define IWDG_PR_PR_Pos (0U)
		4815	#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /!< 0x00000007 /
		4816	#define IWDG_PR_PR IWDG_PR_PR_Msk /!< PR[2:0] (Prescaler divider) /
		4817	#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /!< 0x00000001 /
		4818	#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /!< 0x00000002 /
		4819	#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /!< 0x00000004 /
		4820
		4821	/***************** Bit definition for IWDG_RLR register *****************/
		4822	#define IWDG_RLR_RL_Pos (0U)
		4823	#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /!< 0x00000FFF /
		4824	#define IWDG_RLR_RL IWDG_RLR_RL_Msk /!< Watchdog counter reload value /
		4825
		4826	/***************** Bit definition for IWDG_SR register ******************/
		4827	#define IWDG_SR_PVU_Pos (0U)
		4828	#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /!< 0x00000001 /
		4829	#define IWDG_SR_PVU IWDG_SR_PVU_Msk /!< Watchdog prescaler value update /
		4830	#define IWDG_SR_RVU_Pos (1U)
		4831	#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /!< 0x00000002 /
		4832	#define IWDG_SR_RVU IWDG_SR_RVU_Msk /!< Watchdog counter reload value update /
		4833
		4834	/******************************************************************************/
		4835	/* */
		4836	/* Window WATCHDOG (WWDG) */
		4837	/* */
		4838	/******************************************************************************/
		4839
		4840	/***************** Bit definition for WWDG_CR register ******************/
		4841	#define WWDG_CR_T_Pos (0U)
		4842	#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /!< 0x0000007F /
		4843	#define WWDG_CR_T WWDG_CR_T_Msk /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
		4844	#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /!< 0x00000001 /
		4845	#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /!< 0x00000002 /
		4846	#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /!< 0x00000004 /
		4847	#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /!< 0x00000008 /
		4848	#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /!< 0x00000010 /
		4849	#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /!< 0x00000020 /
		4850	#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /!< 0x00000040 /
		4851
		4852	/* Legacy defines */
		4853	#define WWDG_CR_T0 WWDG_CR_T_0
		4854	#define WWDG_CR_T1 WWDG_CR_T_1
		4855	#define WWDG_CR_T2 WWDG_CR_T_2
		4856	#define WWDG_CR_T3 WWDG_CR_T_3
		4857	#define WWDG_CR_T4 WWDG_CR_T_4
		4858	#define WWDG_CR_T5 WWDG_CR_T_5
		4859	#define WWDG_CR_T6 WWDG_CR_T_6
		4860
		4861	#define WWDG_CR_WDGA_Pos (7U)
		4862	#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /!< 0x00000080 /
		4863	#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /!< Activation bit /
		4864
		4865	/***************** Bit definition for WWDG_CFR register *****************/
		4866	#define WWDG_CFR_W_Pos (0U)
		4867	#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /!< 0x0000007F /
		4868	#define WWDG_CFR_W WWDG_CFR_W_Msk /!< W[6:0] bits (7-bit window value) /
		4869	#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /!< 0x00000001 /
		4870	#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /!< 0x00000002 /
		4871	#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /!< 0x00000004 /
		4872	#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /!< 0x00000008 /
		4873	#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /!< 0x00000010 /
		4874	#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /!< 0x00000020 /
		4875	#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /!< 0x00000040 /
		4876
		4877	/* Legacy defines */
		4878	#define WWDG_CFR_W0 WWDG_CFR_W_0
		4879	#define WWDG_CFR_W1 WWDG_CFR_W_1
		4880	#define WWDG_CFR_W2 WWDG_CFR_W_2
		4881	#define WWDG_CFR_W3 WWDG_CFR_W_3
		4882	#define WWDG_CFR_W4 WWDG_CFR_W_4
		4883	#define WWDG_CFR_W5 WWDG_CFR_W_5
		4884	#define WWDG_CFR_W6 WWDG_CFR_W_6
		4885
		4886	#define WWDG_CFR_WDGTB_Pos (7U)
		4887	#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /!< 0x00000180 /
		4888	#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /!< WDGTB[1:0] bits (Timer Base) /
		4889	#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /!< 0x00000080 /
		4890	#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /!< 0x00000100 /
		4891
		4892	/* Legacy defines */
		4893	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
		4894	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
		4895
		4896	#define WWDG_CFR_EWI_Pos (9U)
		4897	#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /!< 0x00000200 /
		4898	#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /!< Early Wakeup Interrupt /
		4899
		4900	/***************** Bit definition for WWDG_SR register ******************/
		4901	#define WWDG_SR_EWIF_Pos (0U)
		4902	#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /!< 0x00000001 /
		4903	#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /!< Early Wakeup Interrupt Flag /
		4904
		4905	/******************************************************************************/
		4906	/* */
		4907	/* Flexible Static Memory Controller */
		4908	/* */
		4909	/******************************************************************************/
		4910
		4911	/**************** Bit definition for FSMC_BCRx (x=1..4) register ********/
		4912	#define FSMC_BCRx_MBKEN_Pos (0U)
		4913	#define FSMC_BCRx_MBKEN_Msk (0x1UL << FSMC_BCRx_MBKEN_Pos) /!< 0x00000001 /
		4914	#define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /!< Memory bank enable bit /
		4915	#define FSMC_BCRx_MUXEN_Pos (1U)
		4916	#define FSMC_BCRx_MUXEN_Msk (0x1UL << FSMC_BCRx_MUXEN_Pos) /!< 0x00000002 /
		4917	#define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /!< Address/data multiplexing enable bit /
		4918
		4919	#define FSMC_BCRx_MTYP_Pos (2U)
		4920	#define FSMC_BCRx_MTYP_Msk (0x3UL << FSMC_BCRx_MTYP_Pos) /!< 0x0000000C /
		4921	#define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /!< MTYP[1:0] bits (Memory type) /
		4922	#define FSMC_BCRx_MTYP_0 (0x1UL << FSMC_BCRx_MTYP_Pos) /!< 0x00000004 /
		4923	#define FSMC_BCRx_MTYP_1 (0x2UL << FSMC_BCRx_MTYP_Pos) /!< 0x00000008 /
		4924
		4925	#define FSMC_BCRx_MWID_Pos (4U)
		4926	#define FSMC_BCRx_MWID_Msk (0x3UL << FSMC_BCRx_MWID_Pos) /!< 0x00000030 /
		4927	#define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /!< MWID[1:0] bits (Memory data bus width) /
		4928	#define FSMC_BCRx_MWID_0 (0x1UL << FSMC_BCRx_MWID_Pos) /!< 0x00000010 /
		4929	#define FSMC_BCRx_MWID_1 (0x2UL << FSMC_BCRx_MWID_Pos) /!< 0x00000020 /
		4930
		4931	#define FSMC_BCRx_FACCEN_Pos (6U)
		4932	#define FSMC_BCRx_FACCEN_Msk (0x1UL << FSMC_BCRx_FACCEN_Pos) /!< 0x00000040 /
		4933	#define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /!< Flash access enable /
		4934	#define FSMC_BCRx_BURSTEN_Pos (8U)
		4935	#define FSMC_BCRx_BURSTEN_Msk (0x1UL << FSMC_BCRx_BURSTEN_Pos) /!< 0x00000100 /
		4936	#define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /!< Burst enable bit /
		4937	#define FSMC_BCRx_WAITPOL_Pos (9U)
		4938	#define FSMC_BCRx_WAITPOL_Msk (0x1UL << FSMC_BCRx_WAITPOL_Pos) /!< 0x00000200 /
		4939	#define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /!< Wait signal polarity bit /
		4940	#define FSMC_BCRx_WRAPMOD_Pos (10U)
		4941	#define FSMC_BCRx_WRAPMOD_Msk (0x1UL << FSMC_BCRx_WRAPMOD_Pos) /!< 0x00000400 /
		4942	#define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /!< Wrapped burst mode support /
		4943	#define FSMC_BCRx_WAITCFG_Pos (11U)
		4944	#define FSMC_BCRx_WAITCFG_Msk (0x1UL << FSMC_BCRx_WAITCFG_Pos) /!< 0x00000800 /
		4945	#define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /!< Wait timing configuration /
		4946	#define FSMC_BCRx_WREN_Pos (12U)
		4947	#define FSMC_BCRx_WREN_Msk (0x1UL << FSMC_BCRx_WREN_Pos) /!< 0x00001000 /
		4948	#define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /!< Write enable bit /
		4949	#define FSMC_BCRx_WAITEN_Pos (13U)
		4950	#define FSMC_BCRx_WAITEN_Msk (0x1UL << FSMC_BCRx_WAITEN_Pos) /!< 0x00002000 /
		4951	#define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /!< Wait enable bit /
		4952	#define FSMC_BCRx_EXTMOD_Pos (14U)
		4953	#define FSMC_BCRx_EXTMOD_Msk (0x1UL << FSMC_BCRx_EXTMOD_Pos) /!< 0x00004000 /
		4954	#define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /!< Extended mode enable /
		4955	#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
		4956	#define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /!< 0x00008000 /
		4957	#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /!< Asynchronous wait /
		4958	#define FSMC_BCRx_CBURSTRW_Pos (19U)
		4959	#define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /!< 0x00080000 /
		4960	#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /!< Write burst enable /
		4961
		4962	/**************** Bit definition for FSMC_BTRx (x=1..4) register ****/
		4963	#define FSMC_BTRx_ADDSET_Pos (0U)
		4964	#define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /!< 0x0000000F /
		4965	#define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /!< ADDSET[3:0] bits (Address setup phase duration) /
		4966	#define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /!< 0x00000001 /
		4967	#define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /!< 0x00000002 /
		4968	#define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /!< 0x00000004 /
		4969	#define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /!< 0x00000008 /
		4970
		4971	#define FSMC_BTRx_ADDHLD_Pos (4U)
		4972	#define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /!< 0x000000F0 /
		4973	#define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		4974	#define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000010 /
		4975	#define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000020 /
		4976	#define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000040 /
		4977	#define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000080 /
		4978
		4979	#define FSMC_BTRx_DATAST_Pos (8U)
		4980	#define FSMC_BTRx_DATAST_Msk (0xFFUL << FSMC_BTRx_DATAST_Pos) /!< 0x0000FF00 /
		4981	#define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /!< DATAST [3:0] bits (Data-phase duration) /
		4982	#define FSMC_BTRx_DATAST_0 (0x01UL << FSMC_BTRx_DATAST_Pos) /!< 0x00000100 /
		4983	#define FSMC_BTRx_DATAST_1 (0x02UL << FSMC_BTRx_DATAST_Pos) /!< 0x00000200 /
		4984	#define FSMC_BTRx_DATAST_2 (0x04UL << FSMC_BTRx_DATAST_Pos) /!< 0x00000400 /
		4985	#define FSMC_BTRx_DATAST_3 (0x08UL << FSMC_BTRx_DATAST_Pos) /!< 0x00000800 /
		4986	#define FSMC_BTRx_DATAST_4 (0x10UL << FSMC_BTRx_DATAST_Pos) /!< 0x00001000 /
		4987	#define FSMC_BTRx_DATAST_5 (0x20UL << FSMC_BTRx_DATAST_Pos) /!< 0x00002000 /
		4988	#define FSMC_BTRx_DATAST_6 (0x40UL << FSMC_BTRx_DATAST_Pos) /!< 0x00004000 /
		4989	#define FSMC_BTRx_DATAST_7 (0x80UL << FSMC_BTRx_DATAST_Pos) /!< 0x00008000 /
		4990
		4991	#define FSMC_BTRx_BUSTURN_Pos (16U)
		4992	#define FSMC_BTRx_BUSTURN_Msk (0xFUL << FSMC_BTRx_BUSTURN_Pos) /!< 0x000F0000 /
		4993	#define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
		4994	#define FSMC_BTRx_BUSTURN_0 (0x1UL << FSMC_BTRx_BUSTURN_Pos) /!< 0x00010000 /
		4995	#define FSMC_BTRx_BUSTURN_1 (0x2UL << FSMC_BTRx_BUSTURN_Pos) /!< 0x00020000 /
		4996	#define FSMC_BTRx_BUSTURN_2 (0x4UL << FSMC_BTRx_BUSTURN_Pos) /!< 0x00040000 /
		4997	#define FSMC_BTRx_BUSTURN_3 (0x8UL << FSMC_BTRx_BUSTURN_Pos) /!< 0x00080000 /
		4998
		4999	#define FSMC_BTRx_CLKDIV_Pos (20U)
		5000	#define FSMC_BTRx_CLKDIV_Msk (0xFUL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00F00000 /
		5001	#define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /!< CLKDIV[3:0] bits (Clock divide ratio) /
		5002	#define FSMC_BTRx_CLKDIV_0 (0x1UL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00100000 /
		5003	#define FSMC_BTRx_CLKDIV_1 (0x2UL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00200000 /
		5004	#define FSMC_BTRx_CLKDIV_2 (0x4UL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00400000 /
		5005	#define FSMC_BTRx_CLKDIV_3 (0x8UL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00800000 /
		5006
		5007	#define FSMC_BTRx_DATLAT_Pos (24U)
		5008	#define FSMC_BTRx_DATLAT_Msk (0xFUL << FSMC_BTRx_DATLAT_Pos) /!< 0x0F000000 /
		5009	#define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /!< DATLA[3:0] bits (Data latency) /
		5010	#define FSMC_BTRx_DATLAT_0 (0x1UL << FSMC_BTRx_DATLAT_Pos) /!< 0x01000000 /
		5011	#define FSMC_BTRx_DATLAT_1 (0x2UL << FSMC_BTRx_DATLAT_Pos) /!< 0x02000000 /
		5012	#define FSMC_BTRx_DATLAT_2 (0x4UL << FSMC_BTRx_DATLAT_Pos) /!< 0x04000000 /
		5013	#define FSMC_BTRx_DATLAT_3 (0x8UL << FSMC_BTRx_DATLAT_Pos) /!< 0x08000000 /
		5014
		5015	#define FSMC_BTRx_ACCMOD_Pos (28U)
		5016	#define FSMC_BTRx_ACCMOD_Msk (0x3UL << FSMC_BTRx_ACCMOD_Pos) /!< 0x30000000 /
		5017	#define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /!< ACCMOD[1:0] bits (Access mode) /
		5018	#define FSMC_BTRx_ACCMOD_0 (0x1UL << FSMC_BTRx_ACCMOD_Pos) /!< 0x10000000 /
		5019	#define FSMC_BTRx_ACCMOD_1 (0x2UL << FSMC_BTRx_ACCMOD_Pos) /!< 0x20000000 /
		5020
		5021	/**************** Bit definition for FSMC_BWTRx (x=1..4) register ****/
		5022	#define FSMC_BWTRx_ADDSET_Pos (0U)
		5023	#define FSMC_BWTRx_ADDSET_Msk (0xFUL << FSMC_BWTRx_ADDSET_Pos) /!< 0x0000000F /
		5024	#define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /!< ADDSET[3:0] bits (Address setup phase duration) /
		5025	#define FSMC_BWTRx_ADDSET_0 (0x1UL << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000001 /
		5026	#define FSMC_BWTRx_ADDSET_1 (0x2UL << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000002 /
		5027	#define FSMC_BWTRx_ADDSET_2 (0x4UL << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000004 /
		5028	#define FSMC_BWTRx_ADDSET_3 (0x8UL << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000008 /
		5029
		5030	#define FSMC_BWTRx_ADDHLD_Pos (4U)
		5031	#define FSMC_BWTRx_ADDHLD_Msk (0xFUL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x000000F0 /
		5032	#define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		5033	#define FSMC_BWTRx_ADDHLD_0 (0x1UL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000010 /
		5034	#define FSMC_BWTRx_ADDHLD_1 (0x2UL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000020 /
		5035	#define FSMC_BWTRx_ADDHLD_2 (0x4UL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000040 /
		5036	#define FSMC_BWTRx_ADDHLD_3 (0x8UL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000080 /
		5037
		5038	#define FSMC_BWTRx_DATAST_Pos (8U)
		5039	#define FSMC_BWTRx_DATAST_Msk (0xFFUL << FSMC_BWTRx_DATAST_Pos) /!< 0x0000FF00 /
		5040	#define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /!< DATAST [3:0] bits (Data-phase duration) /
		5041	#define FSMC_BWTRx_DATAST_0 (0x01UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00000100 /
		5042	#define FSMC_BWTRx_DATAST_1 (0x02UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00000200 /
		5043	#define FSMC_BWTRx_DATAST_2 (0x04UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00000400 /
		5044	#define FSMC_BWTRx_DATAST_3 (0x08UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00000800 /
		5045	#define FSMC_BWTRx_DATAST_4 (0x10UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00001000 /
		5046	#define FSMC_BWTRx_DATAST_5 (0x20UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00002000 /
		5047	#define FSMC_BWTRx_DATAST_6 (0x40UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00004000 /
		5048	#define FSMC_BWTRx_DATAST_7 (0x80UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00008000 /
		5049
		5050	#define FSMC_BWTRx_BUSTURN_Pos (16U)
		5051	#define FSMC_BWTRx_BUSTURN_Msk (0xFUL << FSMC_BWTRx_BUSTURN_Pos) /!< 0x000F0000 /
		5052	#define FSMC_BWTRx_BUSTURN FSMC_BWTRx_BUSTURN_Msk /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
		5053	#define FSMC_BWTRx_BUSTURN_0 (0x1UL << FSMC_BWTRx_BUSTURN_Pos) /!< 0x00010000 /
		5054	#define FSMC_BWTRx_BUSTURN_1 (0x2UL << FSMC_BWTRx_BUSTURN_Pos) /!< 0x00020000 /
		5055	#define FSMC_BWTRx_BUSTURN_2 (0x4UL << FSMC_BWTRx_BUSTURN_Pos) /!< 0x00040000 /
		5056	#define FSMC_BWTRx_BUSTURN_3 (0x8UL << FSMC_BWTRx_BUSTURN_Pos) /!< 0x00080000 /
		5057
		5058	#define FSMC_BWTRx_ACCMOD_Pos (28U)
		5059	#define FSMC_BWTRx_ACCMOD_Msk (0x3UL << FSMC_BWTRx_ACCMOD_Pos) /!< 0x30000000 /
		5060	#define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /!< ACCMOD[1:0] bits (Access mode) /
		5061	#define FSMC_BWTRx_ACCMOD_0 (0x1UL << FSMC_BWTRx_ACCMOD_Pos) /!< 0x10000000 /
		5062	#define FSMC_BWTRx_ACCMOD_1 (0x2UL << FSMC_BWTRx_ACCMOD_Pos) /!< 0x20000000 /
		5063
		5064	/**************** Bit definition for FSMC_PCRx (x = 2 to 4) register *****************/
		5065	#define FSMC_PCRx_PWAITEN_Pos (1U)
		5066	#define FSMC_PCRx_PWAITEN_Msk (0x1UL << FSMC_PCRx_PWAITEN_Pos) /!< 0x00000002 /
		5067	#define FSMC_PCRx_PWAITEN FSMC_PCRx_PWAITEN_Msk /!< Wait feature enable bit /
		5068	#define FSMC_PCRx_PBKEN_Pos (2U)
		5069	#define FSMC_PCRx_PBKEN_Msk (0x1UL << FSMC_PCRx_PBKEN_Pos) /!< 0x00000004 /
		5070	#define FSMC_PCRx_PBKEN FSMC_PCRx_PBKEN_Msk /!< PC Card/NAND Flash memory bank enable bit /
		5071	#define FSMC_PCRx_PTYP_Pos (3U)
		5072	#define FSMC_PCRx_PTYP_Msk (0x1UL << FSMC_PCRx_PTYP_Pos) /!< 0x00000008 /
		5073	#define FSMC_PCRx_PTYP FSMC_PCRx_PTYP_Msk /!< Memory type /
		5074
		5075	#define FSMC_PCRx_PWID_Pos (4U)
		5076	#define FSMC_PCRx_PWID_Msk (0x3UL << FSMC_PCRx_PWID_Pos) /!< 0x00000030 /
		5077	#define FSMC_PCRx_PWID FSMC_PCRx_PWID_Msk /!< PWID[1:0] bits (NAND Flash databus width) /
		5078	#define FSMC_PCRx_PWID_0 (0x1UL << FSMC_PCRx_PWID_Pos) /!< 0x00000010 /
		5079	#define FSMC_PCRx_PWID_1 (0x2UL << FSMC_PCRx_PWID_Pos) /!< 0x00000020 /
		5080
		5081	#define FSMC_PCRx_ECCEN_Pos (6U)
		5082	#define FSMC_PCRx_ECCEN_Msk (0x1UL << FSMC_PCRx_ECCEN_Pos) /!< 0x00000040 /
		5083	#define FSMC_PCRx_ECCEN FSMC_PCRx_ECCEN_Msk /!< ECC computation logic enable bit /
		5084
		5085	#define FSMC_PCRx_TCLR_Pos (9U)
		5086	#define FSMC_PCRx_TCLR_Msk (0xFUL << FSMC_PCRx_TCLR_Pos) /!< 0x00001E00 /
		5087	#define FSMC_PCRx_TCLR FSMC_PCRx_TCLR_Msk /!< TCLR[3:0] bits (CLE to RE delay) /
		5088	#define FSMC_PCRx_TCLR_0 (0x1UL << FSMC_PCRx_TCLR_Pos) /!< 0x00000200 /
		5089	#define FSMC_PCRx_TCLR_1 (0x2UL << FSMC_PCRx_TCLR_Pos) /!< 0x00000400 /
		5090	#define FSMC_PCRx_TCLR_2 (0x4UL << FSMC_PCRx_TCLR_Pos) /!< 0x00000800 /
		5091	#define FSMC_PCRx_TCLR_3 (0x8UL << FSMC_PCRx_TCLR_Pos) /!< 0x00001000 /
		5092
		5093	#define FSMC_PCRx_TAR_Pos (13U)
		5094	#define FSMC_PCRx_TAR_Msk (0xFUL << FSMC_PCRx_TAR_Pos) /!< 0x0001E000 /
		5095	#define FSMC_PCRx_TAR FSMC_PCRx_TAR_Msk /!< TAR[3:0] bits (ALE to RE delay) /
		5096	#define FSMC_PCRx_TAR_0 (0x1UL << FSMC_PCRx_TAR_Pos) /!< 0x00002000 /
		5097	#define FSMC_PCRx_TAR_1 (0x2UL << FSMC_PCRx_TAR_Pos) /!< 0x00004000 /
		5098	#define FSMC_PCRx_TAR_2 (0x4UL << FSMC_PCRx_TAR_Pos) /!< 0x00008000 /
		5099	#define FSMC_PCRx_TAR_3 (0x8UL << FSMC_PCRx_TAR_Pos) /!< 0x00010000 /
		5100
		5101	#define FSMC_PCRx_ECCPS_Pos (17U)
		5102	#define FSMC_PCRx_ECCPS_Msk (0x7UL << FSMC_PCRx_ECCPS_Pos) /!< 0x000E0000 /
		5103	#define FSMC_PCRx_ECCPS FSMC_PCRx_ECCPS_Msk /!< ECCPS[1:0] bits (ECC page size) /
		5104	#define FSMC_PCRx_ECCPS_0 (0x1UL << FSMC_PCRx_ECCPS_Pos) /!< 0x00020000 /
		5105	#define FSMC_PCRx_ECCPS_1 (0x2UL << FSMC_PCRx_ECCPS_Pos) /!< 0x00040000 /
		5106	#define FSMC_PCRx_ECCPS_2 (0x4UL << FSMC_PCRx_ECCPS_Pos) /!< 0x00080000 /
		5107
		5108	/***************** Bit definition for FSMC_SRx (x = 2 to 4) register *****************/
		5109	#define FSMC_SRx_IRS_Pos (0U)
		5110	#define FSMC_SRx_IRS_Msk (0x1UL << FSMC_SRx_IRS_Pos) /!< 0x00000001 /
		5111	#define FSMC_SRx_IRS FSMC_SRx_IRS_Msk /!< Interrupt Rising Edge status /
		5112	#define FSMC_SRx_ILS_Pos (1U)
		5113	#define FSMC_SRx_ILS_Msk (0x1UL << FSMC_SRx_ILS_Pos) /!< 0x00000002 /
		5114	#define FSMC_SRx_ILS FSMC_SRx_ILS_Msk /!< Interrupt Level status /
		5115	#define FSMC_SRx_IFS_Pos (2U)
		5116	#define FSMC_SRx_IFS_Msk (0x1UL << FSMC_SRx_IFS_Pos) /!< 0x00000004 /
		5117	#define FSMC_SRx_IFS FSMC_SRx_IFS_Msk /!< Interrupt Falling Edge status /
		5118	#define FSMC_SRx_IREN_Pos (3U)
		5119	#define FSMC_SRx_IREN_Msk (0x1UL << FSMC_SRx_IREN_Pos) /!< 0x00000008 /
		5120	#define FSMC_SRx_IREN FSMC_SRx_IREN_Msk /!< Interrupt Rising Edge detection Enable bit /
		5121	#define FSMC_SRx_ILEN_Pos (4U)
		5122	#define FSMC_SRx_ILEN_Msk (0x1UL << FSMC_SRx_ILEN_Pos) /!< 0x00000010 /
		5123	#define FSMC_SRx_ILEN FSMC_SRx_ILEN_Msk /!< Interrupt Level detection Enable bit /
		5124	#define FSMC_SRx_IFEN_Pos (5U)
		5125	#define FSMC_SRx_IFEN_Msk (0x1UL << FSMC_SRx_IFEN_Pos) /!< 0x00000020 /
		5126	#define FSMC_SRx_IFEN FSMC_SRx_IFEN_Msk /!< Interrupt Falling Edge detection Enable bit /
		5127	#define FSMC_SRx_FEMPT_Pos (6U)
		5128	#define FSMC_SRx_FEMPT_Msk (0x1UL << FSMC_SRx_FEMPT_Pos) /!< 0x00000040 /
		5129	#define FSMC_SRx_FEMPT FSMC_SRx_FEMPT_Msk /!< FIFO empty /
		5130
		5131	/**************** Bit definition for FSMC_PMEMx (x = 2 to 4) register ****************/
		5132	#define FSMC_PMEMx_MEMSETx_Pos (0U)
		5133	#define FSMC_PMEMx_MEMSETx_Msk (0xFFUL << FSMC_PMEMx_MEMSETx_Pos) /!< 0x000000FF /
		5134	#define FSMC_PMEMx_MEMSETx FSMC_PMEMx_MEMSETx_Msk /!< MEMSETx[7:0] bits (Common memory x setup time) /
		5135	#define FSMC_PMEMx_MEMSETx_0 (0x01UL << FSMC_PMEMx_MEMSETx_Pos) /!< 0x00000001 /
		5136	#define FSMC_PMEMx_MEMSETx_1 (0x02UL << FSMC_PMEMx_MEMSETx_Pos) /!< 0x00000002 /
		5137	#define FSMC_PMEMx_MEMSETx_2 (0x04UL << FSMC_PMEMx_MEMSETx_Pos) /!< 0x00000004 /
		5138	#define FSMC_PMEMx_MEMSETx_3 (0x08UL << FSMC_PMEMx_MEMSETx_Pos) /!< 0x00000008 /
		5139	#define FSMC_PMEMx_MEMSETx_4 (0x10UL << FSMC_PMEMx_MEMSETx_Pos) /!< 0x00000010 /
		5140	#define FSMC_PMEMx_MEMSETx_5 (0x20UL << FSMC_PMEMx_MEMSETx_Pos) /!< 0x00000020 /
		5141	#define FSMC_PMEMx_MEMSETx_6 (0x40UL << FSMC_PMEMx_MEMSETx_Pos) /!< 0x00000040 /
		5142	#define FSMC_PMEMx_MEMSETx_7 (0x80UL << FSMC_PMEMx_MEMSETx_Pos) /!< 0x00000080 /
		5143
		5144	#define FSMC_PMEMx_MEMWAITx_Pos (8U)
		5145	#define FSMC_PMEMx_MEMWAITx_Msk (0xFFUL << FSMC_PMEMx_MEMWAITx_Pos) /!< 0x0000FF00 /
		5146	#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /!< MEMWAITx[7:0] bits (Common memory x wait time) /
		5147	#define FSMC_PMEMx_MEMWAIT2_0 0x00000100U /!< Bit 0 /
		5148	#define FSMC_PMEMx_MEMWAITx_1 0x00000200U /!< Bit 1 /
		5149	#define FSMC_PMEMx_MEMWAITx_2 0x00000400U /!< Bit 2 /
		5150	#define FSMC_PMEMx_MEMWAITx_3 0x00000800U /!< Bit 3 /
		5151	#define FSMC_PMEMx_MEMWAITx_4 0x00001000U /!< Bit 4 /
		5152	#define FSMC_PMEMx_MEMWAITx_5 0x00002000U /!< Bit 5 /
		5153	#define FSMC_PMEMx_MEMWAITx_6 0x00004000U /!< Bit 6 /
		5154	#define FSMC_PMEMx_MEMWAITx_7 0x00008000U /!< Bit 7 /
		5155
		5156	#define FSMC_PMEMx_MEMHOLDx_Pos (16U)
		5157	#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFUL << FSMC_PMEMx_MEMHOLDx_Pos) /!< 0x00FF0000 /
		5158	#define FSMC_PMEMx_MEMHOLDx FSMC_PMEMx_MEMHOLDx_Msk /!< MEMHOLDx[7:0] bits (Common memory x hold time) /
		5159	#define FSMC_PMEMx_MEMHOLDx_0 (0x01UL << FSMC_PMEMx_MEMHOLDx_Pos) /!< 0x00010000 /
		5160	#define FSMC_PMEMx_MEMHOLDx_1 (0x02UL << FSMC_PMEMx_MEMHOLDx_Pos) /!< 0x00020000 /
		5161	#define FSMC_PMEMx_MEMHOLDx_2 (0x04UL << FSMC_PMEMx_MEMHOLDx_Pos) /!< 0x00040000 /
		5162	#define FSMC_PMEMx_MEMHOLDx_3 (0x08UL << FSMC_PMEMx_MEMHOLDx_Pos) /!< 0x00080000 /
		5163	#define FSMC_PMEMx_MEMHOLDx_4 (0x10UL << FSMC_PMEMx_MEMHOLDx_Pos) /!< 0x00100000 /
		5164	#define FSMC_PMEMx_MEMHOLDx_5 (0x20UL << FSMC_PMEMx_MEMHOLDx_Pos) /!< 0x00200000 /
		5165	#define FSMC_PMEMx_MEMHOLDx_6 (0x40UL << FSMC_PMEMx_MEMHOLDx_Pos) /!< 0x00400000 /
		5166	#define FSMC_PMEMx_MEMHOLDx_7 (0x80UL << FSMC_PMEMx_MEMHOLDx_Pos) /!< 0x00800000 /
		5167
		5168	#define FSMC_PMEMx_MEMHIZx_Pos (24U)
		5169	#define FSMC_PMEMx_MEMHIZx_Msk (0xFFUL << FSMC_PMEMx_MEMHIZx_Pos) /!< 0xFF000000 /
		5170	#define FSMC_PMEMx_MEMHIZx FSMC_PMEMx_MEMHIZx_Msk /!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) /
		5171	#define FSMC_PMEMx_MEMHIZx_0 (0x01UL << FSMC_PMEMx_MEMHIZx_Pos) /!< 0x01000000 /
		5172	#define FSMC_PMEMx_MEMHIZx_1 (0x02UL << FSMC_PMEMx_MEMHIZx_Pos) /!< 0x02000000 /
		5173	#define FSMC_PMEMx_MEMHIZx_2 (0x04UL << FSMC_PMEMx_MEMHIZx_Pos) /!< 0x04000000 /
		5174	#define FSMC_PMEMx_MEMHIZx_3 (0x08UL << FSMC_PMEMx_MEMHIZx_Pos) /!< 0x08000000 /
		5175	#define FSMC_PMEMx_MEMHIZx_4 (0x10UL << FSMC_PMEMx_MEMHIZx_Pos) /!< 0x10000000 /
		5176	#define FSMC_PMEMx_MEMHIZx_5 (0x20UL << FSMC_PMEMx_MEMHIZx_Pos) /!< 0x20000000 /
		5177	#define FSMC_PMEMx_MEMHIZx_6 (0x40UL << FSMC_PMEMx_MEMHIZx_Pos) /!< 0x40000000 /
		5178	#define FSMC_PMEMx_MEMHIZx_7 (0x80UL << FSMC_PMEMx_MEMHIZx_Pos) /!< 0x80000000 /
		5179
		5180	/**************** Bit definition for FSMC_PATTx (x = 2 to 4) register ****************/
		5181	#define FSMC_PATTx_ATTSETx_Pos (0U)
		5182	#define FSMC_PATTx_ATTSETx_Msk (0xFFUL << FSMC_PATTx_ATTSETx_Pos) /!< 0x000000FF /
		5183	#define FSMC_PATTx_ATTSETx FSMC_PATTx_ATTSETx_Msk /!< ATTSETx[7:0] bits (Attribute memory x setup time) /
		5184	#define FSMC_PATTx_ATTSETx_0 (0x01UL << FSMC_PATTx_ATTSETx_Pos) /!< 0x00000001 /
		5185	#define FSMC_PATTx_ATTSETx_1 (0x02UL << FSMC_PATTx_ATTSETx_Pos) /!< 0x00000002 /
		5186	#define FSMC_PATTx_ATTSETx_2 (0x04UL << FSMC_PATTx_ATTSETx_Pos) /!< 0x00000004 /
		5187	#define FSMC_PATTx_ATTSETx_3 (0x08UL << FSMC_PATTx_ATTSETx_Pos) /!< 0x00000008 /
		5188	#define FSMC_PATTx_ATTSETx_4 (0x10UL << FSMC_PATTx_ATTSETx_Pos) /!< 0x00000010 /
		5189	#define FSMC_PATTx_ATTSETx_5 (0x20UL << FSMC_PATTx_ATTSETx_Pos) /!< 0x00000020 /
		5190	#define FSMC_PATTx_ATTSETx_6 (0x40UL << FSMC_PATTx_ATTSETx_Pos) /!< 0x00000040 /
		5191	#define FSMC_PATTx_ATTSETx_7 (0x80UL << FSMC_PATTx_ATTSETx_Pos) /!< 0x00000080 /
		5192
		5193	#define FSMC_PATTx_ATTWAITx_Pos (8U)
		5194	#define FSMC_PATTx_ATTWAITx_Msk (0xFFUL << FSMC_PATTx_ATTWAITx_Pos) /!< 0x0000FF00 /
		5195	#define FSMC_PATTx_ATTWAITx FSMC_PATTx_ATTWAITx_Msk /!< ATTWAITx[7:0] bits (Attribute memory x wait time) /
		5196	#define FSMC_PATTx_ATTWAITx_0 (0x01UL << FSMC_PATTx_ATTWAITx_Pos) /!< 0x00000100 /
		5197	#define FSMC_PATTx_ATTWAITx_1 (0x02UL << FSMC_PATTx_ATTWAITx_Pos) /!< 0x00000200 /
		5198	#define FSMC_PATTx_ATTWAITx_2 (0x04UL << FSMC_PATTx_ATTWAITx_Pos) /!< 0x00000400 /
		5199	#define FSMC_PATTx_ATTWAITx_3 (0x08UL << FSMC_PATTx_ATTWAITx_Pos) /!< 0x00000800 /
		5200	#define FSMC_PATTx_ATTWAITx_4 (0x10UL << FSMC_PATTx_ATTWAITx_Pos) /!< 0x00001000 /
		5201	#define FSMC_PATTx_ATTWAITx_5 (0x20UL << FSMC_PATTx_ATTWAITx_Pos) /!< 0x00002000 /
		5202	#define FSMC_PATTx_ATTWAITx_6 (0x40UL << FSMC_PATTx_ATTWAITx_Pos) /!< 0x00004000 /
		5203	#define FSMC_PATTx_ATTWAITx_7 (0x80UL << FSMC_PATTx_ATTWAITx_Pos) /!< 0x00008000 /
		5204
		5205	#define FSMC_PATTx_ATTHOLDx_Pos (16U)
		5206	#define FSMC_PATTx_ATTHOLDx_Msk (0xFFUL << FSMC_PATTx_ATTHOLDx_Pos) /!< 0x00FF0000 /
		5207	#define FSMC_PATTx_ATTHOLDx FSMC_PATTx_ATTHOLDx_Msk /!< ATTHOLDx[7:0] bits (Attribute memory x hold time) /
		5208	#define FSMC_PATTx_ATTHOLDx_0 (0x01UL << FSMC_PATTx_ATTHOLDx_Pos) /!< 0x00010000 /
		5209	#define FSMC_PATTx_ATTHOLDx_1 (0x02UL << FSMC_PATTx_ATTHOLDx_Pos) /!< 0x00020000 /
		5210	#define FSMC_PATTx_ATTHOLDx_2 (0x04UL << FSMC_PATTx_ATTHOLDx_Pos) /!< 0x00040000 /
		5211	#define FSMC_PATTx_ATTHOLDx_3 (0x08UL << FSMC_PATTx_ATTHOLDx_Pos) /!< 0x00080000 /
		5212	#define FSMC_PATTx_ATTHOLDx_4 (0x10UL << FSMC_PATTx_ATTHOLDx_Pos) /!< 0x00100000 /
		5213	#define FSMC_PATTx_ATTHOLDx_5 (0x20UL << FSMC_PATTx_ATTHOLDx_Pos) /!< 0x00200000 /
		5214	#define FSMC_PATTx_ATTHOLDx_6 (0x40UL << FSMC_PATTx_ATTHOLDx_Pos) /!< 0x00400000 /
		5215	#define FSMC_PATTx_ATTHOLDx_7 (0x80UL << FSMC_PATTx_ATTHOLDx_Pos) /!< 0x00800000 /
		5216
		5217	#define FSMC_PATTx_ATTHIZx_Pos (24U)
		5218	#define FSMC_PATTx_ATTHIZx_Msk (0xFFUL << FSMC_PATTx_ATTHIZx_Pos) /!< 0xFF000000 /
		5219	#define FSMC_PATTx_ATTHIZx FSMC_PATTx_ATTHIZx_Msk /!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) /
		5220	#define FSMC_PATTx_ATTHIZx_0 (0x01UL << FSMC_PATTx_ATTHIZx_Pos) /!< 0x01000000 /
		5221	#define FSMC_PATTx_ATTHIZx_1 (0x02UL << FSMC_PATTx_ATTHIZx_Pos) /!< 0x02000000 /
		5222	#define FSMC_PATTx_ATTHIZx_2 (0x04UL << FSMC_PATTx_ATTHIZx_Pos) /!< 0x04000000 /
		5223	#define FSMC_PATTx_ATTHIZx_3 (0x08UL << FSMC_PATTx_ATTHIZx_Pos) /!< 0x08000000 /
		5224	#define FSMC_PATTx_ATTHIZx_4 (0x10UL << FSMC_PATTx_ATTHIZx_Pos) /!< 0x10000000 /
		5225	#define FSMC_PATTx_ATTHIZx_5 (0x20UL << FSMC_PATTx_ATTHIZx_Pos) /!< 0x20000000 /
		5226	#define FSMC_PATTx_ATTHIZx_6 (0x40UL << FSMC_PATTx_ATTHIZx_Pos) /!< 0x40000000 /
		5227	#define FSMC_PATTx_ATTHIZx_7 (0x80UL << FSMC_PATTx_ATTHIZx_Pos) /!< 0x80000000 /
		5228
		5229	/**************** Bit definition for FSMC_PIO4 register *****************/
		5230	#define FSMC_PIO4_IOSET4_Pos (0U)
		5231	#define FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos) /!< 0x000000FF /
		5232	#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /!< IOSET4[7:0] bits (I/O 4 setup time) /
		5233	#define FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos) /!< 0x00000001 /
		5234	#define FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos) /!< 0x00000002 /
		5235	#define FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos) /!< 0x00000004 /
		5236	#define FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos) /!< 0x00000008 /
		5237	#define FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos) /!< 0x00000010 /
		5238	#define FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos) /!< 0x00000020 /
		5239	#define FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos) /!< 0x00000040 /
		5240	#define FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos) /!< 0x00000080 /
		5241
		5242	#define FSMC_PIO4_IOWAIT4_Pos (8U)
		5243	#define FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos) /!< 0x0000FF00 /
		5244	#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /!< IOWAIT4[7:0] bits (I/O 4 wait time) /
		5245	#define FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos) /!< 0x00000100 /
		5246	#define FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos) /!< 0x00000200 /
		5247	#define FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos) /!< 0x00000400 /
		5248	#define FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos) /!< 0x00000800 /
		5249	#define FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos) /!< 0x00001000 /
		5250	#define FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos) /!< 0x00002000 /
		5251	#define FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos) /!< 0x00004000 /
		5252	#define FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos) /!< 0x00008000 /
		5253
		5254	#define FSMC_PIO4_IOHOLD4_Pos (16U)
		5255	#define FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos) /!< 0x00FF0000 /
		5256	#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /!< IOHOLD4[7:0] bits (I/O 4 hold time) /
		5257	#define FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos) /!< 0x00010000 /
		5258	#define FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos) /!< 0x00020000 /
		5259	#define FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos) /!< 0x00040000 /
		5260	#define FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos) /!< 0x00080000 /
		5261	#define FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos) /!< 0x00100000 /
		5262	#define FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos) /!< 0x00200000 /
		5263	#define FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos) /!< 0x00400000 /
		5264	#define FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos) /!< 0x00800000 /
		5265
		5266	#define FSMC_PIO4_IOHIZ4_Pos (24U)
		5267	#define FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos) /!< 0xFF000000 /
		5268	#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) /
		5269	#define FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos) /!< 0x01000000 /
		5270	#define FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos) /!< 0x02000000 /
		5271	#define FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos) /!< 0x04000000 /
		5272	#define FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos) /!< 0x08000000 /
		5273	#define FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos) /!< 0x10000000 /
		5274	#define FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos) /!< 0x20000000 /
		5275	#define FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos) /!< 0x40000000 /
		5276	#define FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos) /!< 0x80000000 /
		5277
		5278	/**************** Bit definition for FSMC_ECCR2 register ****************/
		5279	#define FSMC_ECCR2_ECC2_Pos (0U)
		5280	#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos) /!< 0xFFFFFFFF /
		5281	#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /!< ECC result /
		5282
		5283	/**************** Bit definition for FSMC_ECCR3 register ****************/
		5284	#define FSMC_ECCR3_ECC3_Pos (0U)
		5285	#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos) /!< 0xFFFFFFFF /
		5286	#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /!< ECC result /
		5287
		5288
		5289	/******************************************************************************/
		5290	/* */
		5291	/* Serial Peripheral Interface */
		5292	/* */
		5293	/******************************************************************************/
		5294	/*
		5295	* @brief Specific device feature definitions (not present on all devices in the STM32F1 series)
		5296	*/
		5297	#define SPI_I2S_SUPPORT /!< I2S support /
		5298	#define SPI_CRC_ERROR_WORKAROUND_FEATURE
		5299
		5300	/***************** Bit definition for SPI_CR1 register ******************/
		5301	#define SPI_CR1_CPHA_Pos (0U)
		5302	#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /!< 0x00000001 /
		5303	#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /!< Clock Phase /
		5304	#define SPI_CR1_CPOL_Pos (1U)
		5305	#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /!< 0x00000002 /
		5306	#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /!< Clock Polarity /
		5307	#define SPI_CR1_MSTR_Pos (2U)
		5308	#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /!< 0x00000004 /
		5309	#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /!< Master Selection /
		5310
		5311	#define SPI_CR1_BR_Pos (3U)
		5312	#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /!< 0x00000038 /
		5313	#define SPI_CR1_BR SPI_CR1_BR_Msk /!< BR[2:0] bits (Baud Rate Control) /
		5314	#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /!< 0x00000008 /
		5315	#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /!< 0x00000010 /
		5316	#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /!< 0x00000020 /
		5317
		5318	#define SPI_CR1_SPE_Pos (6U)
		5319	#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /!< 0x00000040 /
		5320	#define SPI_CR1_SPE SPI_CR1_SPE_Msk /!< SPI Enable /
		5321	#define SPI_CR1_LSBFIRST_Pos (7U)
		5322	#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /!< 0x00000080 /
		5323	#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /!< Frame Format /
		5324	#define SPI_CR1_SSI_Pos (8U)
		5325	#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /!< 0x00000100 /
		5326	#define SPI_CR1_SSI SPI_CR1_SSI_Msk /!< Internal slave select /
		5327	#define SPI_CR1_SSM_Pos (9U)
		5328	#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /!< 0x00000200 /
		5329	#define SPI_CR1_SSM SPI_CR1_SSM_Msk /!< Software slave management /
		5330	#define SPI_CR1_RXONLY_Pos (10U)
		5331	#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /!< 0x00000400 /
		5332	#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /!< Receive only /
		5333	#define SPI_CR1_DFF_Pos (11U)
		5334	#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /!< 0x00000800 /
		5335	#define SPI_CR1_DFF SPI_CR1_DFF_Msk /!< Data Frame Format /
		5336	#define SPI_CR1_CRCNEXT_Pos (12U)
		5337	#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /!< 0x00001000 /
		5338	#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /!< Transmit CRC next /
		5339	#define SPI_CR1_CRCEN_Pos (13U)
		5340	#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /!< 0x00002000 /
		5341	#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /!< Hardware CRC calculation enable /
		5342	#define SPI_CR1_BIDIOE_Pos (14U)
		5343	#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /!< 0x00004000 /
		5344	#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /!< Output enable in bidirectional mode /
		5345	#define SPI_CR1_BIDIMODE_Pos (15U)
		5346	#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /!< 0x00008000 /
		5347	#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /!< Bidirectional data mode enable /
		5348
		5349	/***************** Bit definition for SPI_CR2 register ******************/
		5350	#define SPI_CR2_RXDMAEN_Pos (0U)
		5351	#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /!< 0x00000001 /
		5352	#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /!< Rx Buffer DMA Enable /
		5353	#define SPI_CR2_TXDMAEN_Pos (1U)
		5354	#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /!< 0x00000002 /
		5355	#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /!< Tx Buffer DMA Enable /
		5356	#define SPI_CR2_SSOE_Pos (2U)
		5357	#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /!< 0x00000004 /
		5358	#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /!< SS Output Enable /
		5359	#define SPI_CR2_ERRIE_Pos (5U)
		5360	#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /!< 0x00000020 /
		5361	#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /!< Error Interrupt Enable /
		5362	#define SPI_CR2_RXNEIE_Pos (6U)
		5363	#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /!< 0x00000040 /
		5364	#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /!< RX buffer Not Empty Interrupt Enable /
		5365	#define SPI_CR2_TXEIE_Pos (7U)
		5366	#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /!< 0x00000080 /
		5367	#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /!< Tx buffer Empty Interrupt Enable /
		5368
		5369	/****************** Bit definition for SPI_SR register ******************/
		5370	#define SPI_SR_RXNE_Pos (0U)
		5371	#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /!< 0x00000001 /
		5372	#define SPI_SR_RXNE SPI_SR_RXNE_Msk /!< Receive buffer Not Empty /
		5373	#define SPI_SR_TXE_Pos (1U)
		5374	#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /!< 0x00000002 /
		5375	#define SPI_SR_TXE SPI_SR_TXE_Msk /!< Transmit buffer Empty /
		5376	#define SPI_SR_CHSIDE_Pos (2U)
		5377	#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /!< 0x00000004 /
		5378	#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /!< Channel side /
		5379	#define SPI_SR_UDR_Pos (3U)
		5380	#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /!< 0x00000008 /
		5381	#define SPI_SR_UDR SPI_SR_UDR_Msk /!< Underrun flag /
		5382	#define SPI_SR_CRCERR_Pos (4U)
		5383	#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /!< 0x00000010 /
		5384	#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /!< CRC Error flag /
		5385	#define SPI_SR_MODF_Pos (5U)
		5386	#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /!< 0x00000020 /
		5387	#define SPI_SR_MODF SPI_SR_MODF_Msk /!< Mode fault /
		5388	#define SPI_SR_OVR_Pos (6U)
		5389	#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /!< 0x00000040 /
		5390	#define SPI_SR_OVR SPI_SR_OVR_Msk /!< Overrun flag /
		5391	#define SPI_SR_BSY_Pos (7U)
		5392	#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /!< 0x00000080 /
		5393	#define SPI_SR_BSY SPI_SR_BSY_Msk /!< Busy flag /
		5394
		5395	/****************** Bit definition for SPI_DR register ******************/
		5396	#define SPI_DR_DR_Pos (0U)
		5397	#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /!< 0x0000FFFF /
		5398	#define SPI_DR_DR SPI_DR_DR_Msk /!< Data Register /
		5399
		5400	/***************** Bit definition for SPI_CRCPR register ****************/
		5401	#define SPI_CRCPR_CRCPOLY_Pos (0U)
		5402	#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /!< 0x0000FFFF /
		5403	#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /!< CRC polynomial register /
		5404
		5405	/**************** Bit definition for SPI_RXCRCR register ****************/
		5406	#define SPI_RXCRCR_RXCRC_Pos (0U)
		5407	#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /!< 0x0000FFFF /
		5408	#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /!< Rx CRC Register /
		5409
		5410	/**************** Bit definition for SPI_TXCRCR register ****************/
		5411	#define SPI_TXCRCR_TXCRC_Pos (0U)
		5412	#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /!< 0x0000FFFF /
		5413	#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /!< Tx CRC Register /
		5414
		5415	/**************** Bit definition for SPI_I2SCFGR register ***************/
		5416	#define SPI_I2SCFGR_CHLEN_Pos (0U)
		5417	#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /!< 0x00000001 /
		5418	#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /!< Channel length (number of bits per audio channel) /
		5419
		5420	#define SPI_I2SCFGR_DATLEN_Pos (1U)
		5421	#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /!< 0x00000006 /
		5422	#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /!< DATLEN[1:0] bits (Data length to be transferred) /
		5423	#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /!< 0x00000002 /
		5424	#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /!< 0x00000004 /
		5425
		5426	#define SPI_I2SCFGR_CKPOL_Pos (3U)
		5427	#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /!< 0x00000008 /
		5428	#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /!< steady state clock polarity /
		5429
		5430	#define SPI_I2SCFGR_I2SSTD_Pos (4U)
		5431	#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /!< 0x00000030 /
		5432	#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /!< I2SSTD[1:0] bits (I2S standard selection) /
		5433	#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /!< 0x00000010 /
		5434	#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /!< 0x00000020 /
		5435
		5436	#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
		5437	#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /!< 0x00000080 /
		5438	#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /!< PCM frame synchronization /
		5439
		5440	#define SPI_I2SCFGR_I2SCFG_Pos (8U)
		5441	#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /!< 0x00000300 /
		5442	#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /!< I2SCFG[1:0] bits (I2S configuration mode) /
		5443	#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /!< 0x00000100 /
		5444	#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /!< 0x00000200 /
		5445
		5446	#define SPI_I2SCFGR_I2SE_Pos (10U)
		5447	#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /!< 0x00000400 /
		5448	#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /!< I2S Enable /
		5449	#define SPI_I2SCFGR_I2SMOD_Pos (11U)
		5450	#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /!< 0x00000800 /
		5451	#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /!< I2S mode selection /
		5452	/**************** Bit definition for SPI_I2SPR register *****************/
		5453	#define SPI_I2SPR_I2SDIV_Pos (0U)
		5454	#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /!< 0x000000FF /
		5455	#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /!< I2S Linear prescaler /
		5456	#define SPI_I2SPR_ODD_Pos (8U)
		5457	#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /!< 0x00000100 /
		5458	#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /!< Odd factor for the prescaler /
		5459	#define SPI_I2SPR_MCKOE_Pos (9U)
		5460	#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /!< 0x00000200 /
		5461	#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /!< Master Clock Output Enable /
		5462
		5463	/******************************************************************************/
		5464	/* */
		5465	/* Inter-integrated Circuit Interface */
		5466	/* */
		5467	/******************************************************************************/
		5468
		5469	/***************** Bit definition for I2C_CR1 register ******************/
		5470	#define I2C_CR1_PE_Pos (0U)
		5471	#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /!< 0x00000001 /
		5472	#define I2C_CR1_PE I2C_CR1_PE_Msk /!< Peripheral Enable /
		5473	#define I2C_CR1_SMBUS_Pos (1U)
		5474	#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /!< 0x00000002 /
		5475	#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /!< SMBus Mode /
		5476	#define I2C_CR1_SMBTYPE_Pos (3U)
		5477	#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /!< 0x00000008 /
		5478	#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /!< SMBus Type /
		5479	#define I2C_CR1_ENARP_Pos (4U)
		5480	#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /!< 0x00000010 /
		5481	#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /!< ARP Enable /
		5482	#define I2C_CR1_ENPEC_Pos (5U)
		5483	#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /!< 0x00000020 /
		5484	#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /!< PEC Enable /
		5485	#define I2C_CR1_ENGC_Pos (6U)
		5486	#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /!< 0x00000040 /
		5487	#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /!< General Call Enable /
		5488	#define I2C_CR1_NOSTRETCH_Pos (7U)
		5489	#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /!< 0x00000080 /
		5490	#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /!< Clock Stretching Disable (Slave mode) /
		5491	#define I2C_CR1_START_Pos (8U)
		5492	#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /!< 0x00000100 /
		5493	#define I2C_CR1_START I2C_CR1_START_Msk /!< Start Generation /
		5494	#define I2C_CR1_STOP_Pos (9U)
		5495	#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /!< 0x00000200 /
		5496	#define I2C_CR1_STOP I2C_CR1_STOP_Msk /!< Stop Generation /
		5497	#define I2C_CR1_ACK_Pos (10U)
		5498	#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /!< 0x00000400 /
		5499	#define I2C_CR1_ACK I2C_CR1_ACK_Msk /!< Acknowledge Enable /
		5500	#define I2C_CR1_POS_Pos (11U)
		5501	#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /!< 0x00000800 /
		5502	#define I2C_CR1_POS I2C_CR1_POS_Msk /!< Acknowledge/PEC Position (for data reception) /
		5503	#define I2C_CR1_PEC_Pos (12U)
		5504	#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /!< 0x00001000 /
		5505	#define I2C_CR1_PEC I2C_CR1_PEC_Msk /!< Packet Error Checking /
		5506	#define I2C_CR1_ALERT_Pos (13U)
		5507	#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /!< 0x00002000 /
		5508	#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /!< SMBus Alert /
		5509	#define I2C_CR1_SWRST_Pos (15U)
		5510	#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /!< 0x00008000 /
		5511	#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /!< Software Reset /
		5512
		5513	/***************** Bit definition for I2C_CR2 register ******************/
		5514	#define I2C_CR2_FREQ_Pos (0U)
		5515	#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /!< 0x0000003F /
		5516	#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
		5517	#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /!< 0x00000001 /
		5518	#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /!< 0x00000002 /
		5519	#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /!< 0x00000004 /
		5520	#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /!< 0x00000008 /
		5521	#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /!< 0x00000010 /
		5522	#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /!< 0x00000020 /
		5523
		5524	#define I2C_CR2_ITERREN_Pos (8U)
		5525	#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /!< 0x00000100 /
		5526	#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /!< Error Interrupt Enable /
		5527	#define I2C_CR2_ITEVTEN_Pos (9U)
		5528	#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /!< 0x00000200 /
		5529	#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /!< Event Interrupt Enable /
		5530	#define I2C_CR2_ITBUFEN_Pos (10U)
		5531	#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /!< 0x00000400 /
		5532	#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /!< Buffer Interrupt Enable /
		5533	#define I2C_CR2_DMAEN_Pos (11U)
		5534	#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /!< 0x00000800 /
		5535	#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /!< DMA Requests Enable /
		5536	#define I2C_CR2_LAST_Pos (12U)
		5537	#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /!< 0x00001000 /
		5538	#define I2C_CR2_LAST I2C_CR2_LAST_Msk /!< DMA Last Transfer /
		5539
		5540	/***************** Bit definition for I2C_OAR1 register *****************/
		5541	#define I2C_OAR1_ADD1_7 0x000000FEU /!< Interface Address /
		5542	#define I2C_OAR1_ADD8_9 0x00000300U /!< Interface Address /
		5543
		5544	#define I2C_OAR1_ADD0_Pos (0U)
		5545	#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /!< 0x00000001 /
		5546	#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /!< Bit 0 /
		5547	#define I2C_OAR1_ADD1_Pos (1U)
		5548	#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /!< 0x00000002 /
		5549	#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /!< Bit 1 /
		5550	#define I2C_OAR1_ADD2_Pos (2U)
		5551	#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /!< 0x00000004 /
		5552	#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /!< Bit 2 /
		5553	#define I2C_OAR1_ADD3_Pos (3U)
		5554	#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /!< 0x00000008 /
		5555	#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /!< Bit 3 /
		5556	#define I2C_OAR1_ADD4_Pos (4U)
		5557	#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /!< 0x00000010 /
		5558	#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /!< Bit 4 /
		5559	#define I2C_OAR1_ADD5_Pos (5U)
		5560	#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /!< 0x00000020 /
		5561	#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /!< Bit 5 /
		5562	#define I2C_OAR1_ADD6_Pos (6U)
		5563	#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /!< 0x00000040 /
		5564	#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /!< Bit 6 /
		5565	#define I2C_OAR1_ADD7_Pos (7U)
		5566	#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /!< 0x00000080 /
		5567	#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /!< Bit 7 /
		5568	#define I2C_OAR1_ADD8_Pos (8U)
		5569	#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /!< 0x00000100 /
		5570	#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /!< Bit 8 /
		5571	#define I2C_OAR1_ADD9_Pos (9U)
		5572	#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /!< 0x00000200 /
		5573	#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /!< Bit 9 /
		5574
		5575	#define I2C_OAR1_ADDMODE_Pos (15U)
		5576	#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /!< 0x00008000 /
		5577	#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /!< Addressing Mode (Slave mode) /
		5578
		5579	/***************** Bit definition for I2C_OAR2 register *****************/
		5580	#define I2C_OAR2_ENDUAL_Pos (0U)
		5581	#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /!< 0x00000001 /
		5582	#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /!< Dual addressing mode enable /
		5583	#define I2C_OAR2_ADD2_Pos (1U)
		5584	#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /!< 0x000000FE /
		5585	#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /!< Interface address /
		5586
		5587	/****************** Bit definition for I2C_DR register ******************/
		5588	#define I2C_DR_DR_Pos (0U)
		5589	#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /!< 0x000000FF /
		5590	#define I2C_DR_DR I2C_DR_DR_Msk /!< 8-bit Data Register /
		5591
		5592	/***************** Bit definition for I2C_SR1 register ******************/
		5593	#define I2C_SR1_SB_Pos (0U)
		5594	#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /!< 0x00000001 /
		5595	#define I2C_SR1_SB I2C_SR1_SB_Msk /!< Start Bit (Master mode) /
		5596	#define I2C_SR1_ADDR_Pos (1U)
		5597	#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /!< 0x00000002 /
		5598	#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /!< Address sent (master mode)/matched (slave mode) /
		5599	#define I2C_SR1_BTF_Pos (2U)
		5600	#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /!< 0x00000004 /
		5601	#define I2C_SR1_BTF I2C_SR1_BTF_Msk /!< Byte Transfer Finished /
		5602	#define I2C_SR1_ADD10_Pos (3U)
		5603	#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /!< 0x00000008 /
		5604	#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /!< 10-bit header sent (Master mode) /
		5605	#define I2C_SR1_STOPF_Pos (4U)
		5606	#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /!< 0x00000010 /
		5607	#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /!< Stop detection (Slave mode) /
		5608	#define I2C_SR1_RXNE_Pos (6U)
		5609	#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /!< 0x00000040 /
		5610	#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /!< Data Register not Empty (receivers) /
		5611	#define I2C_SR1_TXE_Pos (7U)
		5612	#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /!< 0x00000080 /
		5613	#define I2C_SR1_TXE I2C_SR1_TXE_Msk /!< Data Register Empty (transmitters) /
		5614	#define I2C_SR1_BERR_Pos (8U)
		5615	#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /!< 0x00000100 /
		5616	#define I2C_SR1_BERR I2C_SR1_BERR_Msk /!< Bus Error /
		5617	#define I2C_SR1_ARLO_Pos (9U)
		5618	#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /!< 0x00000200 /
		5619	#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /!< Arbitration Lost (master mode) /
		5620	#define I2C_SR1_AF_Pos (10U)
		5621	#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /!< 0x00000400 /
		5622	#define I2C_SR1_AF I2C_SR1_AF_Msk /!< Acknowledge Failure /
		5623	#define I2C_SR1_OVR_Pos (11U)
		5624	#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /!< 0x00000800 /
		5625	#define I2C_SR1_OVR I2C_SR1_OVR_Msk /!< Overrun/Underrun /
		5626	#define I2C_SR1_PECERR_Pos (12U)
		5627	#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /!< 0x00001000 /
		5628	#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /!< PEC Error in reception /
		5629	#define I2C_SR1_TIMEOUT_Pos (14U)
		5630	#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /!< 0x00004000 /
		5631	#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /!< Timeout or Tlow Error /
		5632	#define I2C_SR1_SMBALERT_Pos (15U)
		5633	#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /!< 0x00008000 /
		5634	#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /!< SMBus Alert /
		5635
		5636	/***************** Bit definition for I2C_SR2 register ******************/
		5637	#define I2C_SR2_MSL_Pos (0U)
		5638	#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /!< 0x00000001 /
		5639	#define I2C_SR2_MSL I2C_SR2_MSL_Msk /!< Master/Slave /
		5640	#define I2C_SR2_BUSY_Pos (1U)
		5641	#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /!< 0x00000002 /
		5642	#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /!< Bus Busy /
		5643	#define I2C_SR2_TRA_Pos (2U)
		5644	#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /!< 0x00000004 /
		5645	#define I2C_SR2_TRA I2C_SR2_TRA_Msk /!< Transmitter/Receiver /
		5646	#define I2C_SR2_GENCALL_Pos (4U)
		5647	#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /!< 0x00000010 /
		5648	#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /!< General Call Address (Slave mode) /
		5649	#define I2C_SR2_SMBDEFAULT_Pos (5U)
		5650	#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /!< 0x00000020 /
		5651	#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /!< SMBus Device Default Address (Slave mode) /
		5652	#define I2C_SR2_SMBHOST_Pos (6U)
		5653	#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /!< 0x00000040 /
		5654	#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /!< SMBus Host Header (Slave mode) /
		5655	#define I2C_SR2_DUALF_Pos (7U)
		5656	#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /!< 0x00000080 /
		5657	#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /!< Dual Flag (Slave mode) /
		5658	#define I2C_SR2_PEC_Pos (8U)
		5659	#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /!< 0x0000FF00 /
		5660	#define I2C_SR2_PEC I2C_SR2_PEC_Msk /!< Packet Error Checking Register /
		5661
		5662	/***************** Bit definition for I2C_CCR register ******************/
		5663	#define I2C_CCR_CCR_Pos (0U)
		5664	#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /!< 0x00000FFF /
		5665	#define I2C_CCR_CCR I2C_CCR_CCR_Msk /!< Clock Control Register in Fast/Standard mode (Master mode) /
		5666	#define I2C_CCR_DUTY_Pos (14U)
		5667	#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /!< 0x00004000 /
		5668	#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /!< Fast Mode Duty Cycle /
		5669	#define I2C_CCR_FS_Pos (15U)
		5670	#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /!< 0x00008000 /
		5671	#define I2C_CCR_FS I2C_CCR_FS_Msk /!< I2C Master Mode Selection /
		5672
		5673	/**************** Bit definition for I2C_TRISE register *****************/
		5674	#define I2C_TRISE_TRISE_Pos (0U)
		5675	#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /!< 0x0000003F /
		5676	#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
		5677
		5678	/******************************************************************************/
		5679	/* */
		5680	/* Universal Synchronous Asynchronous Receiver Transmitter */
		5681	/* */
		5682	/******************************************************************************/
		5683
		5684	/***************** Bit definition for USART_SR register *****************/
		5685	#define USART_SR_PE_Pos (0U)
		5686	#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /!< 0x00000001 /
		5687	#define USART_SR_PE USART_SR_PE_Msk /!< Parity Error /
		5688	#define USART_SR_FE_Pos (1U)
		5689	#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /!< 0x00000002 /
		5690	#define USART_SR_FE USART_SR_FE_Msk /!< Framing Error /
		5691	#define USART_SR_NE_Pos (2U)
		5692	#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /!< 0x00000004 /
		5693	#define USART_SR_NE USART_SR_NE_Msk /!< Noise Error Flag /
		5694	#define USART_SR_ORE_Pos (3U)
		5695	#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /!< 0x00000008 /
		5696	#define USART_SR_ORE USART_SR_ORE_Msk /!< OverRun Error /
		5697	#define USART_SR_IDLE_Pos (4U)
		5698	#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /!< 0x00000010 /
		5699	#define USART_SR_IDLE USART_SR_IDLE_Msk /!< IDLE line detected /
		5700	#define USART_SR_RXNE_Pos (5U)
		5701	#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /!< 0x00000020 /
		5702	#define USART_SR_RXNE USART_SR_RXNE_Msk /!< Read Data Register Not Empty /
		5703	#define USART_SR_TC_Pos (6U)
		5704	#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /!< 0x00000040 /
		5705	#define USART_SR_TC USART_SR_TC_Msk /!< Transmission Complete /
		5706	#define USART_SR_TXE_Pos (7U)
		5707	#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /!< 0x00000080 /
		5708	#define USART_SR_TXE USART_SR_TXE_Msk /!< Transmit Data Register Empty /
		5709	#define USART_SR_LBD_Pos (8U)
		5710	#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /!< 0x00000100 /
		5711	#define USART_SR_LBD USART_SR_LBD_Msk /!< LIN Break Detection Flag /
		5712	#define USART_SR_CTS_Pos (9U)
		5713	#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /!< 0x00000200 /
		5714	#define USART_SR_CTS USART_SR_CTS_Msk /!< CTS Flag /
		5715
		5716	/***************** Bit definition for USART_DR register *****************/
		5717	#define USART_DR_DR_Pos (0U)
		5718	#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /!< 0x000001FF /
		5719	#define USART_DR_DR USART_DR_DR_Msk /!< Data value /
		5720
		5721	/**************** Bit definition for USART_BRR register *****************/
		5722	#define USART_BRR_DIV_Fraction_Pos (0U)
		5723	#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /!< 0x0000000F /
		5724	#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /!< Fraction of USARTDIV /
		5725	#define USART_BRR_DIV_Mantissa_Pos (4U)
		5726	#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /!< 0x0000FFF0 /
		5727	#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /!< Mantissa of USARTDIV /
		5728
		5729	/**************** Bit definition for USART_CR1 register *****************/
		5730	#define USART_CR1_SBK_Pos (0U)
		5731	#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /!< 0x00000001 /
		5732	#define USART_CR1_SBK USART_CR1_SBK_Msk /!< Send Break /
		5733	#define USART_CR1_RWU_Pos (1U)
		5734	#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /!< 0x00000002 /
		5735	#define USART_CR1_RWU USART_CR1_RWU_Msk /!< Receiver wakeup /
		5736	#define USART_CR1_RE_Pos (2U)
		5737	#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /!< 0x00000004 /
		5738	#define USART_CR1_RE USART_CR1_RE_Msk /!< Receiver Enable /
		5739	#define USART_CR1_TE_Pos (3U)
		5740	#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /!< 0x00000008 /
		5741	#define USART_CR1_TE USART_CR1_TE_Msk /!< Transmitter Enable /
		5742	#define USART_CR1_IDLEIE_Pos (4U)
		5743	#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /!< 0x00000010 /
		5744	#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /!< IDLE Interrupt Enable /
		5745	#define USART_CR1_RXNEIE_Pos (5U)
		5746	#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /!< 0x00000020 /
		5747	#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /!< RXNE Interrupt Enable /
		5748	#define USART_CR1_TCIE_Pos (6U)
		5749	#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /!< 0x00000040 /
		5750	#define USART_CR1_TCIE USART_CR1_TCIE_Msk /!< Transmission Complete Interrupt Enable /
		5751	#define USART_CR1_TXEIE_Pos (7U)
		5752	#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /!< 0x00000080 /
		5753	#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /!< PE Interrupt Enable /
		5754	#define USART_CR1_PEIE_Pos (8U)
		5755	#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /!< 0x00000100 /
		5756	#define USART_CR1_PEIE USART_CR1_PEIE_Msk /!< PE Interrupt Enable /
		5757	#define USART_CR1_PS_Pos (9U)
		5758	#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /!< 0x00000200 /
		5759	#define USART_CR1_PS USART_CR1_PS_Msk /!< Parity Selection /
		5760	#define USART_CR1_PCE_Pos (10U)
		5761	#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /!< 0x00000400 /
		5762	#define USART_CR1_PCE USART_CR1_PCE_Msk /!< Parity Control Enable /
		5763	#define USART_CR1_WAKE_Pos (11U)
		5764	#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /!< 0x00000800 /
		5765	#define USART_CR1_WAKE USART_CR1_WAKE_Msk /!< Wakeup method /
		5766	#define USART_CR1_M_Pos (12U)
		5767	#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /!< 0x00001000 /
		5768	#define USART_CR1_M USART_CR1_M_Msk /!< Word length /
		5769	#define USART_CR1_UE_Pos (13U)
		5770	#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /!< 0x00002000 /
		5771	#define USART_CR1_UE USART_CR1_UE_Msk /!< USART Enable /
		5772
		5773	/**************** Bit definition for USART_CR2 register *****************/
		5774	#define USART_CR2_ADD_Pos (0U)
		5775	#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /!< 0x0000000F /
		5776	#define USART_CR2_ADD USART_CR2_ADD_Msk /!< Address of the USART node /
		5777	#define USART_CR2_LBDL_Pos (5U)
		5778	#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /!< 0x00000020 /
		5779	#define USART_CR2_LBDL USART_CR2_LBDL_Msk /!< LIN Break Detection Length /
		5780	#define USART_CR2_LBDIE_Pos (6U)
		5781	#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /!< 0x00000040 /
		5782	#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /!< LIN Break Detection Interrupt Enable /
		5783	#define USART_CR2_LBCL_Pos (8U)
		5784	#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /!< 0x00000100 /
		5785	#define USART_CR2_LBCL USART_CR2_LBCL_Msk /!< Last Bit Clock pulse /
		5786	#define USART_CR2_CPHA_Pos (9U)
		5787	#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /!< 0x00000200 /
		5788	#define USART_CR2_CPHA USART_CR2_CPHA_Msk /!< Clock Phase /
		5789	#define USART_CR2_CPOL_Pos (10U)
		5790	#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /!< 0x00000400 /
		5791	#define USART_CR2_CPOL USART_CR2_CPOL_Msk /!< Clock Polarity /
		5792	#define USART_CR2_CLKEN_Pos (11U)
		5793	#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /!< 0x00000800 /
		5794	#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /!< Clock Enable /
		5795
		5796	#define USART_CR2_STOP_Pos (12U)
		5797	#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /!< 0x00003000 /
		5798	#define USART_CR2_STOP USART_CR2_STOP_Msk /!< STOP[1:0] bits (STOP bits) /
		5799	#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /!< 0x00001000 /
		5800	#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /!< 0x00002000 /
		5801
		5802	#define USART_CR2_LINEN_Pos (14U)
		5803	#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /!< 0x00004000 /
		5804	#define USART_CR2_LINEN USART_CR2_LINEN_Msk /!< LIN mode enable /
		5805
		5806	/**************** Bit definition for USART_CR3 register *****************/
		5807	#define USART_CR3_EIE_Pos (0U)
		5808	#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /!< 0x00000001 /
		5809	#define USART_CR3_EIE USART_CR3_EIE_Msk /!< Error Interrupt Enable /
		5810	#define USART_CR3_IREN_Pos (1U)
		5811	#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /!< 0x00000002 /
		5812	#define USART_CR3_IREN USART_CR3_IREN_Msk /!< IrDA mode Enable /
		5813	#define USART_CR3_IRLP_Pos (2U)
		5814	#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /!< 0x00000004 /
		5815	#define USART_CR3_IRLP USART_CR3_IRLP_Msk /!< IrDA Low-Power /
		5816	#define USART_CR3_HDSEL_Pos (3U)
		5817	#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /!< 0x00000008 /
		5818	#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /!< Half-Duplex Selection /
		5819	#define USART_CR3_NACK_Pos (4U)
		5820	#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /!< 0x00000010 /
		5821	#define USART_CR3_NACK USART_CR3_NACK_Msk /!< Smartcard NACK enable /
		5822	#define USART_CR3_SCEN_Pos (5U)
		5823	#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /!< 0x00000020 /
		5824	#define USART_CR3_SCEN USART_CR3_SCEN_Msk /!< Smartcard mode enable /
		5825	#define USART_CR3_DMAR_Pos (6U)
		5826	#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /!< 0x00000040 /
		5827	#define USART_CR3_DMAR USART_CR3_DMAR_Msk /!< DMA Enable Receiver /
		5828	#define USART_CR3_DMAT_Pos (7U)
		5829	#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /!< 0x00000080 /
		5830	#define USART_CR3_DMAT USART_CR3_DMAT_Msk /!< DMA Enable Transmitter /
		5831	#define USART_CR3_RTSE_Pos (8U)
		5832	#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /!< 0x00000100 /
		5833	#define USART_CR3_RTSE USART_CR3_RTSE_Msk /!< RTS Enable /
		5834	#define USART_CR3_CTSE_Pos (9U)
		5835	#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /!< 0x00000200 /
		5836	#define USART_CR3_CTSE USART_CR3_CTSE_Msk /!< CTS Enable /
		5837	#define USART_CR3_CTSIE_Pos (10U)
		5838	#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /!< 0x00000400 /
		5839	#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /!< CTS Interrupt Enable /
		5840
		5841	/**************** Bit definition for USART_GTPR register ****************/
		5842	#define USART_GTPR_PSC_Pos (0U)
		5843	#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /!< 0x000000FF /
		5844	#define USART_GTPR_PSC USART_GTPR_PSC_Msk /!< PSC[7:0] bits (Prescaler value) /
		5845	#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /!< 0x00000001 /
		5846	#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /!< 0x00000002 /
		5847	#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /!< 0x00000004 /
		5848	#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /!< 0x00000008 /
		5849	#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /!< 0x00000010 /
		5850	#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /!< 0x00000020 /
		5851	#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /!< 0x00000040 /
		5852	#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /!< 0x00000080 /
		5853
		5854	#define USART_GTPR_GT_Pos (8U)
		5855	#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /!< 0x0000FF00 /
		5856	#define USART_GTPR_GT USART_GTPR_GT_Msk /!< Guard time value /
		5857
		5858	/******************************************************************************/
		5859	/* */
		5860	/* Debug MCU */
		5861	/* */
		5862	/******************************************************************************/
		5863
		5864	/************** Bit definition for DBGMCU_IDCODE register ***************/
		5865	#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
		5866	#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /!< 0x00000FFF /
		5867	#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /!< Device Identifier /
		5868
		5869	#define DBGMCU_IDCODE_REV_ID_Pos (16U)
		5870	#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0xFFFF0000 /
		5871	#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /!< REV_ID[15:0] bits (Revision Identifier) /
		5872	#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00010000 /
		5873	#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00020000 /
		5874	#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00040000 /
		5875	#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00080000 /
		5876	#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00100000 /
		5877	#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00200000 /
		5878	#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00400000 /
		5879	#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00800000 /
		5880	#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x01000000 /
		5881	#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x02000000 /
		5882	#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x04000000 /
		5883	#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x08000000 /
		5884	#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x10000000 /
		5885	#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x20000000 /
		5886	#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x40000000 /
		5887	#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x80000000 /
		5888
		5889	/**************** Bit definition for DBGMCU_CR register *****************/
		5890	#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
		5891	#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /!< 0x00000001 /
		5892	#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /!< Debug Sleep Mode /
		5893	#define DBGMCU_CR_DBG_STOP_Pos (1U)
		5894	#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /!< 0x00000002 /
		5895	#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /!< Debug Stop Mode /
		5896	#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
		5897	#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /!< 0x00000004 /
		5898	#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /!< Debug Standby mode /
		5899	#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
		5900	#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /!< 0x00000020 /
		5901	#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /!< Trace Pin Assignment Control /
		5902
		5903	#define DBGMCU_CR_TRACE_MODE_Pos (6U)
		5904	#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x000000C0 /
		5905	#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
		5906	#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000040 /
		5907	#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000080 /
		5908
		5909	#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
		5910	#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /!< 0x00000100 /
		5911	#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /!< Debug Independent Watchdog stopped when Core is halted /
		5912	#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
		5913	#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /!< 0x00000200 /
		5914	#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /!< Debug Window Watchdog stopped when Core is halted /
		5915	#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
		5916	#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /!< 0x00000400 /
		5917	#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /!< TIM1 counter stopped when core is halted /
		5918	#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
		5919	#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /!< 0x00000800 /
		5920	#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /!< TIM2 counter stopped when core is halted /
		5921	#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
		5922	#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /!< 0x00001000 /
		5923	#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /!< TIM3 counter stopped when core is halted /
		5924	#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
		5925	#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /!< 0x00002000 /
		5926	#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /!< TIM4 counter stopped when core is halted /
		5927	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
		5928	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /!< 0x00008000 /
		5929	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		5930	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
		5931	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /!< 0x00010000 /
		5932	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		5933	#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
		5934	#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos) /!< 0x00040000 /
		5935	#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /!< TIM5 counter stopped when core is halted /
		5936	#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
		5937	#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos) /!< 0x00080000 /
		5938	#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /!< TIM6 counter stopped when core is halted /
		5939	#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
		5940	#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos) /!< 0x00100000 /
		5941	#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /!< TIM7 counter stopped when core is halted /
		5942	#define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U)
		5943	#define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM9_STOP_Pos) /!< 0x10000000 /
		5944	#define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk /!< Debug TIM9 stopped when Core is halted /
		5945	#define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U)
		5946	#define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM10_STOP_Pos) /!< 0x20000000 /
		5947	#define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk /!< Debug TIM10 stopped when Core is halted /
		5948	#define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U)
		5949	#define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM11_STOP_Pos) /!< 0x40000000 /
		5950	#define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk /!< Debug TIM11 stopped when Core is halted /
		5951
		5952	/******************************************************************************/
		5953	/* */
		5954	/* FLASH and Option Bytes Registers */
		5955	/* */
		5956	/******************************************************************************/
		5957	/***************** Bit definition for FLASH_ACR register ****************/
		5958	#define FLASH_ACR_LATENCY_Pos (0U)
		5959	#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /!< 0x00000007 /
		5960	#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /!< LATENCY[2:0] bits (Latency) /
		5961	#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /!< 0x00000001 /
		5962	#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /!< 0x00000002 /
		5963	#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /!< 0x00000004 /
		5964
		5965	#define FLASH_ACR_HLFCYA_Pos (3U)
		5966	#define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /!< 0x00000008 /
		5967	#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /!< Flash Half Cycle Access Enable /
		5968	#define FLASH_ACR_PRFTBE_Pos (4U)
		5969	#define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /!< 0x00000010 /
		5970	#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /!< Prefetch Buffer Enable /
		5971	#define FLASH_ACR_PRFTBS_Pos (5U)
		5972	#define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /!< 0x00000020 /
		5973	#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /!< Prefetch Buffer Status /
		5974
		5975	/**************** Bit definition for FLASH_KEYR register ****************/
		5976	#define FLASH_KEYR_FKEYR_Pos (0U)
		5977	#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /!< 0xFFFFFFFF /
		5978	#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /!< FPEC Key /
		5979
		5980	#define RDP_KEY_Pos (0U)
		5981	#define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /!< 0x000000A5 /
		5982	#define RDP_KEY RDP_KEY_Msk /!< RDP Key /
		5983	#define FLASH_KEY1_Pos (0U)
		5984	#define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /!< 0x45670123 /
		5985	#define FLASH_KEY1 FLASH_KEY1_Msk /!< FPEC Key1 /
		5986	#define FLASH_KEY2_Pos (0U)
		5987	#define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /!< 0xCDEF89AB /
		5988	#define FLASH_KEY2 FLASH_KEY2_Msk /!< FPEC Key2 /
		5989
		5990	/*************** Bit definition for FLASH_OPTKEYR register **************/
		5991	#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
		5992	#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /!< 0xFFFFFFFF /
		5993	#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /!< Option Byte Key /
		5994
		5995	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
		5996	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
		5997
		5998	/**************** Bit definition for FLASH_SR register ******************/
		5999	#define FLASH_SR_BSY_Pos (0U)
		6000	#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /!< 0x00000001 /
		6001	#define FLASH_SR_BSY FLASH_SR_BSY_Msk /!< Busy /
		6002	#define FLASH_SR_PGERR_Pos (2U)
		6003	#define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /!< 0x00000004 /
		6004	#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /!< Programming Error /
		6005	#define FLASH_SR_WRPRTERR_Pos (4U)
		6006	#define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /!< 0x00000010 /
		6007	#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /!< Write Protection Error /
		6008	#define FLASH_SR_EOP_Pos (5U)
		6009	#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /!< 0x00000020 /
		6010	#define FLASH_SR_EOP FLASH_SR_EOP_Msk /!< End of operation /
		6011
		6012	/***************** Bit definition for FLASH_CR register *****************/
		6013	#define FLASH_CR_PG_Pos (0U)
		6014	#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /!< 0x00000001 /
		6015	#define FLASH_CR_PG FLASH_CR_PG_Msk /!< Programming /
		6016	#define FLASH_CR_PER_Pos (1U)
		6017	#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /!< 0x00000002 /
		6018	#define FLASH_CR_PER FLASH_CR_PER_Msk /!< Page Erase /
		6019	#define FLASH_CR_MER_Pos (2U)
		6020	#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /!< 0x00000004 /
		6021	#define FLASH_CR_MER FLASH_CR_MER_Msk /!< Mass Erase /
		6022	#define FLASH_CR_OPTPG_Pos (4U)
		6023	#define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /!< 0x00000010 /
		6024	#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /!< Option Byte Programming /
		6025	#define FLASH_CR_OPTER_Pos (5U)
		6026	#define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /!< 0x00000020 /
		6027	#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /!< Option Byte Erase /
		6028	#define FLASH_CR_STRT_Pos (6U)
		6029	#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /!< 0x00000040 /
		6030	#define FLASH_CR_STRT FLASH_CR_STRT_Msk /!< Start /
		6031	#define FLASH_CR_LOCK_Pos (7U)
		6032	#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /!< 0x00000080 /
		6033	#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /!< Lock /
		6034	#define FLASH_CR_OPTWRE_Pos (9U)
		6035	#define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /!< 0x00000200 /
		6036	#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /!< Option Bytes Write Enable /
		6037	#define FLASH_CR_ERRIE_Pos (10U)
		6038	#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /!< 0x00000400 /
		6039	#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /!< Error Interrupt Enable /
		6040	#define FLASH_CR_EOPIE_Pos (12U)
		6041	#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /!< 0x00001000 /
		6042	#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /!< End of operation interrupt enable /
		6043
		6044	/***************** Bit definition for FLASH_AR register *****************/
		6045	#define FLASH_AR_FAR_Pos (0U)
		6046	#define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /!< 0xFFFFFFFF /
		6047	#define FLASH_AR_FAR FLASH_AR_FAR_Msk /!< Flash Address /
		6048
		6049	/**************** Bit definition for FLASH_OBR register *****************/
		6050	#define FLASH_OBR_OPTERR_Pos (0U)
		6051	#define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /!< 0x00000001 /
		6052	#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /!< Option Byte Error /
		6053	#define FLASH_OBR_RDPRT_Pos (1U)
		6054	#define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos) /!< 0x00000002 /
		6055	#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /!< Read protection /
		6056
		6057	#define FLASH_OBR_IWDG_SW_Pos (2U)
		6058	#define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /!< 0x00000004 /
		6059	#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /!< IWDG SW /
		6060	#define FLASH_OBR_nRST_STOP_Pos (3U)
		6061	#define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /!< 0x00000008 /
		6062	#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /!< nRST_STOP /
		6063	#define FLASH_OBR_nRST_STDBY_Pos (4U)
		6064	#define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /!< 0x00000010 /
		6065	#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /!< nRST_STDBY /
		6066	#define FLASH_OBR_USER_Pos (2U)
		6067	#define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /!< 0x0000001C /
		6068	#define FLASH_OBR_USER FLASH_OBR_USER_Msk /!< User Option Bytes /
		6069	#define FLASH_OBR_DATA0_Pos (10U)
		6070	#define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /!< 0x0003FC00 /
		6071	#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /!< Data0 /
		6072	#define FLASH_OBR_DATA1_Pos (18U)
		6073	#define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /!< 0x03FC0000 /
		6074	#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /!< Data1 /
		6075
		6076	/**************** Bit definition for FLASH_WRPR register ****************/
		6077	#define FLASH_WRPR_WRP_Pos (0U)
		6078	#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /!< 0xFFFFFFFF /
		6079	#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /!< Write Protect /
		6080
		6081	/----------------------------------------------------------------------------/
		6082
		6083	/**************** Bit definition for FLASH_RDP register *****************/
		6084	#define FLASH_RDP_RDP_Pos (0U)
		6085	#define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos) /!< 0x000000FF /
		6086	#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /!< Read protection option byte /
		6087	#define FLASH_RDP_nRDP_Pos (8U)
		6088	#define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos) /!< 0x0000FF00 /
		6089	#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /!< Read protection complemented option byte /
		6090
		6091	/**************** Bit definition for FLASH_USER register ****************/
		6092	#define FLASH_USER_USER_Pos (16U)
		6093	#define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos) /!< 0x00FF0000 /
		6094	#define FLASH_USER_USER FLASH_USER_USER_Msk /!< User option byte /
		6095	#define FLASH_USER_nUSER_Pos (24U)
		6096	#define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos) /!< 0xFF000000 /
		6097	#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /!< User complemented option byte /
		6098
		6099	/**************** Bit definition for FLASH_Data0 register ***************/
		6100	#define FLASH_DATA0_DATA0_Pos (0U)
		6101	#define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos) /!< 0x000000FF /
		6102	#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /!< User data storage option byte /
		6103	#define FLASH_DATA0_nDATA0_Pos (8U)
		6104	#define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos) /!< 0x0000FF00 /
		6105	#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /!< User data storage complemented option byte /
		6106
		6107	/**************** Bit definition for FLASH_Data1 register ***************/
		6108	#define FLASH_DATA1_DATA1_Pos (16U)
		6109	#define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos) /!< 0x00FF0000 /
		6110	#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /!< User data storage option byte /
		6111	#define FLASH_DATA1_nDATA1_Pos (24U)
		6112	#define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos) /!< 0xFF000000 /
		6113	#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /!< User data storage complemented option byte /
		6114
		6115	/**************** Bit definition for FLASH_WRP0 register ****************/
		6116	#define FLASH_WRP0_WRP0_Pos (0U)
		6117	#define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos) /!< 0x000000FF /
		6118	#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /!< Flash memory write protection option bytes /
		6119	#define FLASH_WRP0_nWRP0_Pos (8U)
		6120	#define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /!< 0x0000FF00 /
		6121	#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /!< Flash memory write protection complemented option bytes /
		6122
		6123	/**************** Bit definition for FLASH_WRP1 register ****************/
		6124	#define FLASH_WRP1_WRP1_Pos (16U)
		6125	#define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos) /!< 0x00FF0000 /
		6126	#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /!< Flash memory write protection option bytes /
		6127	#define FLASH_WRP1_nWRP1_Pos (24U)
		6128	#define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos) /!< 0xFF000000 /
		6129	#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /!< Flash memory write protection complemented option bytes /
		6130
		6131	/**************** Bit definition for FLASH_WRP2 register ****************/
		6132	#define FLASH_WRP2_WRP2_Pos (0U)
		6133	#define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos) /!< 0x000000FF /
		6134	#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /!< Flash memory write protection option bytes /
		6135	#define FLASH_WRP2_nWRP2_Pos (8U)
		6136	#define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos) /!< 0x0000FF00 /
		6137	#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /!< Flash memory write protection complemented option bytes /
		6138
		6139	/**************** Bit definition for FLASH_WRP3 register ****************/
		6140	#define FLASH_WRP3_WRP3_Pos (16U)
		6141	#define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos) /!< 0x00FF0000 /
		6142	#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /!< Flash memory write protection option bytes /
		6143	#define FLASH_WRP3_nWRP3_Pos (24U)
		6144	#define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /!< 0xFF000000 /
		6145	#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /!< Flash memory write protection complemented option bytes /
		6146
		6147
		6148
		6149	/**
		6150	* @}
		6151	*/
		6152
		6153	/**
		6154	* @}
		6155	*/
		6156
		6157	/** @addtogroup Exported_macro
		6158	* @{
		6159	*/
		6160
		6161	/**************************** ADC Instances *******************************/
		6162	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
		6163
		6164	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
		6165
		6166	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		6167
		6168	/**************************** CRC Instances *******************************/
		6169	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		6170
		6171	/**************************** DAC Instances *******************************/
		6172	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
		6173
		6174	/**************************** DMA Instances *******************************/
		6175	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		6176	((INSTANCE) == DMA1_Channel2) \|\| \
		6177	((INSTANCE) == DMA1_Channel3) \|\| \
		6178	((INSTANCE) == DMA1_Channel4) \|\| \
		6179	((INSTANCE) == DMA1_Channel5) \|\| \
		6180	((INSTANCE) == DMA1_Channel6) \|\| \
		6181	((INSTANCE) == DMA1_Channel7) \|\| \
		6182	((INSTANCE) == DMA2_Channel1) \|\| \
		6183	((INSTANCE) == DMA2_Channel2) \|\| \
		6184	((INSTANCE) == DMA2_Channel3) \|\| \
		6185	((INSTANCE) == DMA2_Channel4) \|\| \
		6186	((INSTANCE) == DMA2_Channel5))
		6187
		6188	/***************************** GPIO Instances *****************************/
		6189	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		6190	((INSTANCE) == GPIOB) \|\| \
		6191	((INSTANCE) == GPIOC) \|\| \
		6192	((INSTANCE) == GPIOD) \|\| \
		6193	((INSTANCE) == GPIOE) \|\| \
		6194	((INSTANCE) == GPIOF) \|\| \
		6195	((INSTANCE) == GPIOG))
		6196
		6197	/************************** GPIO Alternate Function Instances *************/
		6198	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		6199
		6200	/************************** GPIO Lock Instances ***************************/
		6201	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		6202
		6203	/****************************** I2C Instances *****************************/
		6204	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		6205	((INSTANCE) == I2C2))
		6206
		6207	/***************************** SMBUS Instances ****************************/
		6208	#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
		6209
		6210	/****************************** I2S Instances *****************************/
		6211	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) \|\| \
		6212	((INSTANCE) == SPI3))
		6213
		6214	/**************************** IWDG Instances ******************************/
		6215	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		6216
		6217	/****************************** SPI Instances *****************************/
		6218	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		6219	((INSTANCE) == SPI2) \|\| \
		6220	((INSTANCE) == SPI3))
		6221
		6222	/**************************** START TIM Instances *************************/
		6223	/**************************** TIM Instances *******************************/
		6224	#define IS_TIM_INSTANCE(INSTANCE)\
		6225	(((INSTANCE) == TIM2) \|\| \
		6226	((INSTANCE) == TIM3) \|\| \
		6227	((INSTANCE) == TIM4) \|\| \
		6228	((INSTANCE) == TIM5) \|\| \
		6229	((INSTANCE) == TIM6) \|\| \
		6230	((INSTANCE) == TIM7))
		6231
		6232	#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U
		6233
		6234	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
		6235	(((INSTANCE) == TIM2) \|\| \
		6236	((INSTANCE) == TIM3) \|\| \
		6237	((INSTANCE) == TIM4) \|\| \
		6238	((INSTANCE) == TIM5))
		6239
		6240	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
		6241	(((INSTANCE) == TIM2) \|\| \
		6242	((INSTANCE) == TIM3) \|\| \
		6243	((INSTANCE) == TIM4) \|\| \
		6244	((INSTANCE) == TIM5))
		6245
		6246	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
		6247	(((INSTANCE) == TIM2) \|\| \
		6248	((INSTANCE) == TIM3) \|\| \
		6249	((INSTANCE) == TIM4) \|\| \
		6250	((INSTANCE) == TIM5))
		6251
		6252	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
		6253	(((INSTANCE) == TIM2) \|\| \
		6254	((INSTANCE) == TIM3) \|\| \
		6255	((INSTANCE) == TIM4) \|\| \
		6256	((INSTANCE) == TIM5))
		6257
		6258	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
		6259	(((INSTANCE) == TIM2) \|\| \
		6260	((INSTANCE) == TIM3) \|\| \
		6261	((INSTANCE) == TIM4) \|\| \
		6262	((INSTANCE) == TIM5))
		6263
		6264	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
		6265	(((INSTANCE) == TIM2) \|\| \
		6266	((INSTANCE) == TIM3) \|\| \
		6267	((INSTANCE) == TIM4) \|\| \
		6268	((INSTANCE) == TIM5))
		6269
		6270	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
		6271	(((INSTANCE) == TIM2) \|\| \
		6272	((INSTANCE) == TIM3) \|\| \
		6273	((INSTANCE) == TIM4) \|\| \
		6274	((INSTANCE) == TIM5))
		6275
		6276	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
		6277	(((INSTANCE) == TIM2) \|\| \
		6278	((INSTANCE) == TIM3) \|\| \
		6279	((INSTANCE) == TIM4) \|\| \
		6280	((INSTANCE) == TIM5))
		6281
		6282	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
		6283	(((INSTANCE) == TIM2) \|\| \
		6284	((INSTANCE) == TIM3) \|\| \
		6285	((INSTANCE) == TIM4) \|\| \
		6286	((INSTANCE) == TIM5))
		6287
		6288	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
		6289	(((INSTANCE) == TIM2) \|\| \
		6290	((INSTANCE) == TIM3) \|\| \
		6291	((INSTANCE) == TIM4) \|\| \
		6292	((INSTANCE) == TIM5))
		6293
		6294	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
		6295	(((INSTANCE) == TIM2) \|\| \
		6296	((INSTANCE) == TIM3) \|\| \
		6297	((INSTANCE) == TIM4) \|\| \
		6298	((INSTANCE) == TIM5))
		6299
		6300	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
		6301	(((INSTANCE) == TIM2) \|\| \
		6302	((INSTANCE) == TIM3) \|\| \
		6303	((INSTANCE) == TIM4) \|\| \
		6304	((INSTANCE) == TIM5) \|\| \
		6305	((INSTANCE) == TIM6) \|\| \
		6306	((INSTANCE) == TIM7))
		6307
		6308	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
		6309	(((INSTANCE) == TIM2) \|\| \
		6310	((INSTANCE) == TIM3) \|\| \
		6311	((INSTANCE) == TIM4) \|\| \
		6312	((INSTANCE) == TIM5))
		6313
		6314	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
		6315	(((INSTANCE) == TIM2) \|\| \
		6316	((INSTANCE) == TIM3) \|\| \
		6317	((INSTANCE) == TIM4) \|\| \
		6318	((INSTANCE) == TIM5))
		6319
		6320	#define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U
		6321
		6322	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		6323	((((INSTANCE) == TIM2) && \
		6324	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6325	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6326	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6327	((CHANNEL) == TIM_CHANNEL_4))) \
		6328	\|\| \
		6329	(((INSTANCE) == TIM3) && \
		6330	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6331	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6332	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6333	((CHANNEL) == TIM_CHANNEL_4))) \
		6334	\|\| \
		6335	(((INSTANCE) == TIM4) && \
		6336	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6337	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6338	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6339	((CHANNEL) == TIM_CHANNEL_4))) \
		6340	\|\| \
		6341	(((INSTANCE) == TIM5) && \
		6342	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6343	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6344	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6345	((CHANNEL) == TIM_CHANNEL_4))))
		6346
		6347	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U
		6348
		6349	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
		6350	(((INSTANCE) == TIM2) \|\| \
		6351	((INSTANCE) == TIM3) \|\| \
		6352	((INSTANCE) == TIM4) \|\| \
		6353	((INSTANCE) == TIM5))
		6354
		6355	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U
		6356
		6357	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
		6358	(((INSTANCE) == TIM2) \|\| \
		6359	((INSTANCE) == TIM3) \|\| \
		6360	((INSTANCE) == TIM4) \|\| \
		6361	((INSTANCE) == TIM5))
		6362
		6363	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
		6364	(((INSTANCE) == TIM2) \|\| \
		6365	((INSTANCE) == TIM3) \|\| \
		6366	((INSTANCE) == TIM4) \|\| \
		6367	((INSTANCE) == TIM5) \|\| \
		6368	((INSTANCE) == TIM6) \|\| \
		6369	((INSTANCE) == TIM7))
		6370
		6371	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
		6372	(((INSTANCE) == TIM2) \|\| \
		6373	((INSTANCE) == TIM3) \|\| \
		6374	((INSTANCE) == TIM4) \|\| \
		6375	((INSTANCE) == TIM5))
		6376
		6377	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U
		6378
		6379	#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		6380	((INSTANCE) == TIM3) \|\| \
		6381	((INSTANCE) == TIM4) \|\| \
		6382	((INSTANCE) == TIM5))
		6383
		6384	#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		6385	((INSTANCE) == TIM3) \|\| \
		6386	((INSTANCE) == TIM4) \|\| \
		6387	((INSTANCE) == TIM5))
		6388
		6389	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
		6390
		6391	/**************************** END TIM Instances ***************************/
		6392
		6393
		6394	/****************** USART Instances : Synchronous mode ********************/
		6395	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6396	((INSTANCE) == USART2) \|\| \
		6397	((INSTANCE) == USART3))
		6398
		6399	/****************** UART Instances : Asynchronous mode ********************/
		6400	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6401	((INSTANCE) == USART2) \|\| \
		6402	((INSTANCE) == USART3) \|\| \
		6403	((INSTANCE) == UART4) \|\| \
		6404	((INSTANCE) == UART5))
		6405
		6406	/****************** UART Instances : Half-Duplex mode ********************/
		6407	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6408	((INSTANCE) == USART2) \|\| \
		6409	((INSTANCE) == USART3) \|\| \
		6410	((INSTANCE) == UART4) \|\| \
		6411	((INSTANCE) == UART5))
		6412
		6413	/****************** UART Instances : LIN mode ********************/
		6414	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6415	((INSTANCE) == USART2) \|\| \
		6416	((INSTANCE) == USART3) \|\| \
		6417	((INSTANCE) == UART4) \|\| \
		6418	((INSTANCE) == UART5))
		6419
		6420	/**************** UART Instances : Hardware Flow control ******************/
		6421	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6422	((INSTANCE) == USART2) \|\| \
		6423	((INSTANCE) == USART3))
		6424
		6425	/******************* UART Instances : Smard card mode *********************/
		6426	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6427	((INSTANCE) == USART2) \|\| \
		6428	((INSTANCE) == USART3))
		6429
		6430	/********************* UART Instances : IRDA mode *************************/
		6431	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6432	((INSTANCE) == USART2) \|\| \
		6433	((INSTANCE) == USART3) \|\| \
		6434	((INSTANCE) == UART4) \|\| \
		6435	((INSTANCE) == UART5))
		6436
		6437	/*************** UART Instances : Multi-Processor mode ********************/
		6438	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6439	((INSTANCE) == USART2) \|\| \
		6440	((INSTANCE) == USART3) \|\| \
		6441	((INSTANCE) == UART4) \|\| \
		6442	((INSTANCE) == UART5))
		6443
		6444	/*************** UART Instances : DMA mode available ********************/
		6445	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6446	((INSTANCE) == USART2) \|\| \
		6447	((INSTANCE) == USART3) \|\| \
		6448	((INSTANCE) == UART4))
		6449
		6450	/**************************** RTC Instances *******************************/
		6451	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		6452
		6453	/************************** WWDG Instances ***************************/
		6454	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		6455
		6456
		6457
		6458
		6459	#define RCC_HSE_MIN 4000000U
		6460	#define RCC_HSE_MAX 16000000U
		6461
		6462	#define RCC_MAX_FREQUENCY 72000000U
		6463
		6464	/**
		6465	* @}
		6466	*/
		6467	/******************************************************************************/
		6468	/* For a painless codes migration between the STM32F1xx device product */
		6469	/* lines, the aliases defined below are put in place to overcome the */
		6470	/* differences in the interrupt handlers and IRQn definitions. */
		6471	/* No need to update developed interrupt code when moving across */
		6472	/* product lines within the same STM32F1 Family */
		6473	/******************************************************************************/
		6474
		6475	/* Aliases for __IRQn */
		6476	#define ADC1_2_IRQn ADC1_IRQn
		6477	#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
		6478	#define TIM6_DAC_IRQn TIM6_IRQn
		6479
		6480
		6481	/* Aliases for __IRQHandler */
		6482	#define ADC1_2_IRQHandler ADC1_IRQHandler
		6483	#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
		6484	#define TIM6_DAC_IRQHandler TIM6_IRQHandler
		6485
		6486
		6487	/**
		6488	* @}
		6489	*/
		6490
		6491	/**
		6492	* @}
		6493	*/
		6494
		6495
		6496	#ifdef __cplusplus
		6497	}
		6498	#endif /* __cplusplus */
		6499
		6500	#endif /* __STM32F101xE_H */
		6501
		6502
		6503

Subversion Repositories AFRtranscoder

(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h – Rev 2