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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f101xb.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V4.0.1 |
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| 6 | * @date 31-July-2015 |
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| 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
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| 8 | * This file contains all the peripheral register's definitions, bits |
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| 9 | * definitions and memory mapping for STM32F1xx devices. |
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| 10 | * |
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| 11 | * This file contains: |
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| 12 | * - Data structures and the address mapping for all peripherals |
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| 13 | * - Peripheral's registers declarations and bits definition |
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| 14 | * - Macros to access peripheral’s registers hardware |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | * @attention |
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| 18 | * |
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| 19 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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| 20 | * |
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| 21 | * Redistribution and use in source and binary forms, with or without modification, |
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| 22 | * are permitted provided that the following conditions are met: |
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| 23 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 24 | * this list of conditions and the following disclaimer. |
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| 25 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 26 | * this list of conditions and the following disclaimer in the documentation |
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| 27 | * and/or other materials provided with the distribution. |
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| 28 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 29 | * may be used to endorse or promote products derived from this software |
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| 30 | * without specific prior written permission. |
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| 31 | * |
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| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 33 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 34 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 35 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 36 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 37 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 38 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 39 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 40 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 41 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 42 | * |
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| 43 | ****************************************************************************** |
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| 44 | */ |
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| 45 | |||
| 46 | |||
| 47 | /** @addtogroup CMSIS |
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| 48 | * @{ |
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| 49 | */ |
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| 50 | |||
| 51 | /** @addtogroup stm32f101xb |
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| 52 | * @{ |
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| 53 | */ |
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| 54 | |||
| 55 | #ifndef __STM32F101xB_H |
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| 56 | #define __STM32F101xB_H |
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| 57 | |||
| 58 | #ifdef __cplusplus |
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| 59 | extern "C" { |
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| 60 | #endif |
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| 61 | |||
| 62 | /** @addtogroup Configuration_section_for_CMSIS |
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| 63 | * @{ |
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| 64 | */ |
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| 65 | /** |
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| 66 | * @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
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| 67 | */ |
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| 68 | #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ |
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| 69 | #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ |
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| 70 | #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ |
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| 71 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
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| 72 | |||
| 73 | /** |
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| 74 | * @} |
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| 75 | */ |
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| 76 | |||
| 77 | /** @addtogroup Peripheral_interrupt_number_definition |
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| 78 | * @{ |
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| 79 | */ |
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| 80 | |||
| 81 | /** |
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| 82 | * @brief STM32F10x Interrupt Number Definition, according to the selected device |
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| 83 | * in @ref Library_configuration_section |
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| 84 | */ |
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| 85 | |||
| 86 | /*!< Interrupt Number Definition */ |
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| 87 | typedef enum |
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| 88 | { |
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| 89 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
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| 90 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
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| 91 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
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| 92 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
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| 93 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
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| 94 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
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| 95 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
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| 96 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
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| 97 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
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| 98 | |||
| 99 | /****** STM32 specific Interrupt Numbers *********************************************************/ |
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| 100 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
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| 101 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
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| 102 | TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
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| 103 | RTC_IRQn = 3, /*!< RTC global Interrupt */ |
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| 104 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
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| 105 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
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| 106 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
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| 107 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
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| 108 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
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| 109 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
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| 110 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
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| 111 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
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| 112 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
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| 113 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
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| 114 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
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| 115 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
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| 116 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
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| 117 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
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| 118 | ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
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| 119 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
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| 120 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
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| 121 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
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| 122 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
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| 123 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
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| 124 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
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| 125 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
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| 126 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
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| 127 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
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| 128 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
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| 129 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
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| 130 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
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| 131 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
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| 132 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
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| 133 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
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| 134 | } IRQn_Type; |
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| 135 | |||
| 136 | |||
| 137 | /** |
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| 138 | * @} |
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| 139 | */ |
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| 140 | |||
| 141 | #include "core_cm3.h" |
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| 142 | #include "system_stm32f1xx.h" |
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| 143 | #include <stdint.h> |
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| 144 | |||
| 145 | /** @addtogroup Peripheral_registers_structures |
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| 146 | * @{ |
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| 147 | */ |
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| 148 | |||
| 149 | /** |
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| 150 | * @brief Analog to Digital Converter |
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| 151 | */ |
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| 152 | |||
| 153 | typedef struct |
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| 154 | { |
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| 155 | __IO uint32_t SR; |
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| 156 | __IO uint32_t CR1; |
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| 157 | __IO uint32_t CR2; |
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| 158 | __IO uint32_t SMPR1; |
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| 159 | __IO uint32_t SMPR2; |
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| 160 | __IO uint32_t JOFR1; |
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| 161 | __IO uint32_t JOFR2; |
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| 162 | __IO uint32_t JOFR3; |
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| 163 | __IO uint32_t JOFR4; |
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| 164 | __IO uint32_t HTR; |
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| 165 | __IO uint32_t LTR; |
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| 166 | __IO uint32_t SQR1; |
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| 167 | __IO uint32_t SQR2; |
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| 168 | __IO uint32_t SQR3; |
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| 169 | __IO uint32_t JSQR; |
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| 170 | __IO uint32_t JDR1; |
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| 171 | __IO uint32_t JDR2; |
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| 172 | __IO uint32_t JDR3; |
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| 173 | __IO uint32_t JDR4; |
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| 174 | __IO uint32_t DR; |
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| 175 | } ADC_TypeDef; |
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| 176 | |||
| 177 | /** |
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| 178 | * @brief Backup Registers |
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| 179 | */ |
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| 180 | |||
| 181 | typedef struct |
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| 182 | { |
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| 183 | uint32_t RESERVED0; |
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| 184 | __IO uint32_t DR1; |
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| 185 | __IO uint32_t DR2; |
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| 186 | __IO uint32_t DR3; |
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| 187 | __IO uint32_t DR4; |
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| 188 | __IO uint32_t DR5; |
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| 189 | __IO uint32_t DR6; |
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| 190 | __IO uint32_t DR7; |
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| 191 | __IO uint32_t DR8; |
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| 192 | __IO uint32_t DR9; |
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| 193 | __IO uint32_t DR10; |
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| 194 | __IO uint32_t RTCCR; |
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| 195 | __IO uint32_t CR; |
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| 196 | __IO uint32_t CSR; |
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| 197 | } BKP_TypeDef; |
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| 198 | |||
| 199 | |||
| 200 | /** |
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| 201 | * @brief CRC calculation unit |
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| 202 | */ |
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| 203 | |||
| 204 | typedef struct |
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| 205 | { |
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| 206 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
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| 207 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
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| 208 | uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ |
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| 209 | uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ |
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| 210 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
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| 211 | } CRC_TypeDef; |
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| 212 | |||
| 213 | |||
| 214 | /** |
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| 215 | * @brief Debug MCU |
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| 216 | */ |
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| 217 | |||
| 218 | typedef struct |
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| 219 | { |
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| 220 | __IO uint32_t IDCODE; |
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| 221 | __IO uint32_t CR; |
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| 222 | }DBGMCU_TypeDef; |
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| 223 | |||
| 224 | /** |
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| 225 | * @brief DMA Controller |
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| 226 | */ |
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| 227 | |||
| 228 | typedef struct |
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| 229 | { |
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| 230 | __IO uint32_t CCR; |
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| 231 | __IO uint32_t CNDTR; |
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| 232 | __IO uint32_t CPAR; |
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| 233 | __IO uint32_t CMAR; |
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| 234 | } DMA_Channel_TypeDef; |
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| 235 | |||
| 236 | typedef struct |
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| 237 | { |
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| 238 | __IO uint32_t ISR; |
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| 239 | __IO uint32_t IFCR; |
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| 240 | } DMA_TypeDef; |
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| 241 | |||
| 242 | |||
| 243 | |||
| 244 | /** |
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| 245 | * @brief External Interrupt/Event Controller |
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| 246 | */ |
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| 247 | |||
| 248 | typedef struct |
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| 249 | { |
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| 250 | __IO uint32_t IMR; |
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| 251 | __IO uint32_t EMR; |
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| 252 | __IO uint32_t RTSR; |
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| 253 | __IO uint32_t FTSR; |
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| 254 | __IO uint32_t SWIER; |
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| 255 | __IO uint32_t PR; |
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| 256 | } EXTI_TypeDef; |
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| 257 | |||
| 258 | /** |
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| 259 | * @brief FLASH Registers |
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| 260 | */ |
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| 261 | |||
| 262 | typedef struct |
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| 263 | { |
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| 264 | __IO uint32_t ACR; |
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| 265 | __IO uint32_t KEYR; |
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| 266 | __IO uint32_t OPTKEYR; |
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| 267 | __IO uint32_t SR; |
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| 268 | __IO uint32_t CR; |
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| 269 | __IO uint32_t AR; |
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| 270 | __IO uint32_t RESERVED; |
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| 271 | __IO uint32_t OBR; |
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| 272 | __IO uint32_t WRPR; |
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| 273 | } FLASH_TypeDef; |
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| 274 | |||
| 275 | /** |
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| 276 | * @brief Option Bytes Registers |
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| 277 | */ |
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| 278 | |||
| 279 | typedef struct |
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| 280 | { |
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| 281 | __IO uint16_t RDP; |
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| 282 | __IO uint16_t USER; |
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| 283 | __IO uint16_t Data0; |
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| 284 | __IO uint16_t Data1; |
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| 285 | __IO uint16_t WRP0; |
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| 286 | __IO uint16_t WRP1; |
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| 287 | __IO uint16_t WRP2; |
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| 288 | __IO uint16_t WRP3; |
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| 289 | } OB_TypeDef; |
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| 290 | |||
| 291 | /** |
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| 292 | * @brief General Purpose I/O |
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| 293 | */ |
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| 294 | |||
| 295 | typedef struct |
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| 296 | { |
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| 297 | __IO uint32_t CRL; |
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| 298 | __IO uint32_t CRH; |
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| 299 | __IO uint32_t IDR; |
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| 300 | __IO uint32_t ODR; |
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| 301 | __IO uint32_t BSRR; |
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| 302 | __IO uint32_t BRR; |
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| 303 | __IO uint32_t LCKR; |
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| 304 | } GPIO_TypeDef; |
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| 305 | |||
| 306 | /** |
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| 307 | * @brief Alternate Function I/O |
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| 308 | */ |
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| 309 | |||
| 310 | typedef struct |
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| 311 | { |
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| 312 | __IO uint32_t EVCR; |
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| 313 | __IO uint32_t MAPR; |
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| 314 | __IO uint32_t EXTICR[4]; |
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| 315 | uint32_t RESERVED0; |
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| 316 | __IO uint32_t MAPR2; |
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| 317 | } AFIO_TypeDef; |
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| 318 | /** |
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| 319 | * @brief Inter Integrated Circuit Interface |
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| 320 | */ |
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| 321 | |||
| 322 | typedef struct |
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| 323 | { |
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| 324 | __IO uint32_t CR1; |
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| 325 | __IO uint32_t CR2; |
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| 326 | __IO uint32_t OAR1; |
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| 327 | __IO uint32_t OAR2; |
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| 328 | __IO uint32_t DR; |
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| 329 | __IO uint32_t SR1; |
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| 330 | __IO uint32_t SR2; |
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| 331 | __IO uint32_t CCR; |
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| 332 | __IO uint32_t TRISE; |
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| 333 | } I2C_TypeDef; |
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| 334 | |||
| 335 | /** |
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| 336 | * @brief Independent WATCHDOG |
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| 337 | */ |
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| 338 | |||
| 339 | typedef struct |
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| 340 | { |
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| 341 | __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ |
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| 342 | __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ |
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| 343 | __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ |
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| 344 | __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ |
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| 345 | } IWDG_TypeDef; |
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| 346 | |||
| 347 | /** |
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| 348 | * @brief Power Control |
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| 349 | */ |
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| 350 | |||
| 351 | typedef struct |
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| 352 | { |
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| 353 | __IO uint32_t CR; |
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| 354 | __IO uint32_t CSR; |
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| 355 | } PWR_TypeDef; |
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| 356 | |||
| 357 | /** |
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| 358 | * @brief Reset and Clock Control |
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| 359 | */ |
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| 360 | |||
| 361 | typedef struct |
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| 362 | { |
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| 363 | __IO uint32_t CR; |
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| 364 | __IO uint32_t CFGR; |
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| 365 | __IO uint32_t CIR; |
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| 366 | __IO uint32_t APB2RSTR; |
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| 367 | __IO uint32_t APB1RSTR; |
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| 368 | __IO uint32_t AHBENR; |
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| 369 | __IO uint32_t APB2ENR; |
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| 370 | __IO uint32_t APB1ENR; |
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| 371 | __IO uint32_t BDCR; |
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| 372 | __IO uint32_t CSR; |
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| 373 | |||
| 374 | |||
| 375 | } RCC_TypeDef; |
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| 376 | |||
| 377 | /** |
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| 378 | * @brief Real-Time Clock |
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| 379 | */ |
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| 380 | |||
| 381 | typedef struct |
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| 382 | { |
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| 383 | __IO uint32_t CRH; |
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| 384 | __IO uint32_t CRL; |
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| 385 | __IO uint32_t PRLH; |
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| 386 | __IO uint32_t PRLL; |
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| 387 | __IO uint32_t DIVH; |
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| 388 | __IO uint32_t DIVL; |
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| 389 | __IO uint32_t CNTH; |
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| 390 | __IO uint32_t CNTL; |
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| 391 | __IO uint32_t ALRH; |
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| 392 | __IO uint32_t ALRL; |
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| 393 | } RTC_TypeDef; |
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| 394 | |||
| 395 | /** |
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| 396 | * @brief SD host Interface |
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| 397 | */ |
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| 398 | |||
| 399 | typedef struct |
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| 400 | { |
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| 401 | __IO uint32_t POWER; |
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| 402 | __IO uint32_t CLKCR; |
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| 403 | __IO uint32_t ARG; |
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| 404 | __IO uint32_t CMD; |
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| 405 | __I uint32_t RESPCMD; |
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| 406 | __I uint32_t RESP1; |
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| 407 | __I uint32_t RESP2; |
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| 408 | __I uint32_t RESP3; |
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| 409 | __I uint32_t RESP4; |
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| 410 | __IO uint32_t DTIMER; |
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| 411 | __IO uint32_t DLEN; |
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| 412 | __IO uint32_t DCTRL; |
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| 413 | __I uint32_t DCOUNT; |
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| 414 | __I uint32_t STA; |
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| 415 | __IO uint32_t ICR; |
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| 416 | __IO uint32_t MASK; |
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| 417 | uint32_t RESERVED0[2]; |
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| 418 | __I uint32_t FIFOCNT; |
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| 419 | uint32_t RESERVED1[13]; |
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| 420 | __IO uint32_t FIFO; |
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| 421 | } SDIO_TypeDef; |
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| 422 | |||
| 423 | /** |
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| 424 | * @brief Serial Peripheral Interface |
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| 425 | */ |
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| 426 | |||
| 427 | typedef struct |
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| 428 | { |
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| 429 | __IO uint32_t CR1; |
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| 430 | __IO uint32_t CR2; |
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| 431 | __IO uint32_t SR; |
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| 432 | __IO uint32_t DR; |
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| 433 | __IO uint32_t CRCPR; |
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| 434 | __IO uint32_t RXCRCR; |
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| 435 | __IO uint32_t TXCRCR; |
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| 436 | __IO uint32_t I2SCFGR; |
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| 437 | } SPI_TypeDef; |
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| 438 | |||
| 439 | /** |
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| 440 | * @brief TIM Timers |
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| 441 | */ |
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| 442 | typedef struct |
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| 443 | { |
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| 444 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
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| 445 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
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| 446 | __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
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| 447 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
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| 448 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
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| 449 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
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| 450 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
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| 451 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
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| 452 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
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| 453 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
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| 454 | __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
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| 455 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
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| 456 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
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| 457 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
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| 458 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
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| 459 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
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| 460 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
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| 461 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
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| 462 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
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| 463 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ |
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| 464 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
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| 465 | }TIM_TypeDef; |
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| 466 | |||
| 467 | |||
| 468 | /** |
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| 469 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
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| 470 | */ |
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| 471 | |||
| 472 | typedef struct |
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| 473 | { |
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| 474 | __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
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| 475 | __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
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| 476 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
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| 477 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
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| 478 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
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| 479 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
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| 480 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
||
| 481 | } USART_TypeDef; |
||
| 482 | |||
| 483 | |||
| 484 | |||
| 485 | /** |
||
| 486 | * @brief Window WATCHDOG |
||
| 487 | */ |
||
| 488 | |||
| 489 | typedef struct |
||
| 490 | { |
||
| 491 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
||
| 492 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
||
| 493 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
||
| 494 | } WWDG_TypeDef; |
||
| 495 | |||
| 496 | /** |
||
| 497 | * @} |
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| 498 | */ |
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| 499 | |||
| 500 | /** @addtogroup Peripheral_memory_map |
||
| 501 | * @{ |
||
| 502 | */ |
||
| 503 | |||
| 504 | |||
| 505 | #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ |
||
| 506 | #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ |
||
| 507 | #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ |
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| 508 | #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
||
| 509 | |||
| 510 | #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ |
||
| 511 | #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
||
| 512 | |||
| 513 | |||
| 514 | /*!< Peripheral memory map */ |
||
| 515 | #define APB1PERIPH_BASE PERIPH_BASE |
||
| 516 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
||
| 517 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
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| 518 | |||
| 519 | #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
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| 520 | #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
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| 521 | #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
||
| 522 | #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
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| 523 | #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
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| 524 | #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
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| 525 | #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
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| 526 | #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
||
| 527 | #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
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| 528 | #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
||
| 529 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
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| 530 | #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
||
| 531 | #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
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| 532 | #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
||
| 533 | #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
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| 534 | #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
||
| 535 | #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
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| 536 | #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
||
| 537 | #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
||
| 538 | #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
||
| 539 | #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
||
| 540 | #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
||
| 541 | #define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
||
| 542 | |||
| 543 | #define SDIO_BASE (PERIPH_BASE + 0x18000) |
||
| 544 | |||
| 545 | #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
||
| 546 | #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
||
| 547 | #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
||
| 548 | #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
||
| 549 | #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
||
| 550 | #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
||
| 551 | #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
||
| 552 | #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
||
| 553 | #define RCC_BASE (AHBPERIPH_BASE + 0x1000) |
||
| 554 | #define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
||
| 555 | |||
| 556 | #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ |
||
| 557 | #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ |
||
| 558 | |||
| 559 | |||
| 560 | |||
| 561 | #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ |
||
| 562 | |||
| 563 | |||
| 564 | |||
| 565 | /** |
||
| 566 | * @} |
||
| 567 | */ |
||
| 568 | |||
| 569 | /** @addtogroup Peripheral_declaration |
||
| 570 | * @{ |
||
| 571 | */ |
||
| 572 | |||
| 573 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
||
| 574 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
||
| 575 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
||
| 576 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
||
| 577 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
||
| 578 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
||
| 579 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
||
| 580 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
||
| 581 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
||
| 582 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
||
| 583 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
||
| 584 | #define BKP ((BKP_TypeDef *) BKP_BASE) |
||
| 585 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
||
| 586 | #define AFIO ((AFIO_TypeDef *) AFIO_BASE) |
||
| 587 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
||
| 588 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
||
| 589 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
||
| 590 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
||
| 591 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
||
| 592 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
||
| 593 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
||
| 594 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
||
| 595 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
||
| 596 | #define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
||
| 597 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
||
| 598 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
||
| 599 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
||
| 600 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
||
| 601 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
||
| 602 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
||
| 603 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
||
| 604 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
||
| 605 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
||
| 606 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
||
| 607 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
||
| 608 | #define OB ((OB_TypeDef *) OB_BASE) |
||
| 609 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
||
| 610 | |||
| 611 | |||
| 612 | /** |
||
| 613 | * @} |
||
| 614 | */ |
||
| 615 | |||
| 616 | /** @addtogroup Exported_constants |
||
| 617 | * @{ |
||
| 618 | */ |
||
| 619 | |||
| 620 | /** @addtogroup Peripheral_Registers_Bits_Definition |
||
| 621 | * @{ |
||
| 622 | */ |
||
| 623 | |||
| 624 | /******************************************************************************/ |
||
| 625 | /* Peripheral Registers_Bits_Definition */ |
||
| 626 | /******************************************************************************/ |
||
| 627 | |||
| 628 | /******************************************************************************/ |
||
| 629 | /* */ |
||
| 630 | /* CRC calculation unit (CRC) */ |
||
| 631 | /* */ |
||
| 632 | /******************************************************************************/ |
||
| 633 | |||
| 634 | /******************* Bit definition for CRC_DR register *********************/ |
||
| 635 | #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
||
| 636 | |||
| 637 | /******************* Bit definition for CRC_IDR register ********************/ |
||
| 638 | #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
||
| 639 | |||
| 640 | /******************** Bit definition for CRC_CR register ********************/ |
||
| 641 | #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ |
||
| 642 | |||
| 643 | /******************************************************************************/ |
||
| 644 | /* */ |
||
| 645 | /* Power Control */ |
||
| 646 | /* */ |
||
| 647 | /******************************************************************************/ |
||
| 648 | |||
| 649 | /******************** Bit definition for PWR_CR register ********************/ |
||
| 650 | #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */ |
||
| 651 | #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */ |
||
| 652 | #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */ |
||
| 653 | #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */ |
||
| 654 | #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */ |
||
| 655 | |||
| 656 | #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */ |
||
| 657 | #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 658 | #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 659 | #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 660 | |||
| 661 | /*!< PVD level configuration */ |
||
| 662 | #define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */ |
||
| 663 | #define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */ |
||
| 664 | #define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */ |
||
| 665 | #define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */ |
||
| 666 | #define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */ |
||
| 667 | #define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */ |
||
| 668 | #define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */ |
||
| 669 | #define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */ |
||
| 670 | |||
| 671 | #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ |
||
| 672 | |||
| 673 | |||
| 674 | /******************* Bit definition for PWR_CSR register ********************/ |
||
| 675 | #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */ |
||
| 676 | #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */ |
||
| 677 | #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */ |
||
| 678 | #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */ |
||
| 679 | |||
| 680 | /******************************************************************************/ |
||
| 681 | /* */ |
||
| 682 | /* Backup registers */ |
||
| 683 | /* */ |
||
| 684 | /******************************************************************************/ |
||
| 685 | |||
| 686 | /******************* Bit definition for BKP_DR1 register ********************/ |
||
| 687 | #define BKP_DR1_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 688 | |||
| 689 | /******************* Bit definition for BKP_DR2 register ********************/ |
||
| 690 | #define BKP_DR2_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 691 | |||
| 692 | /******************* Bit definition for BKP_DR3 register ********************/ |
||
| 693 | #define BKP_DR3_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 694 | |||
| 695 | /******************* Bit definition for BKP_DR4 register ********************/ |
||
| 696 | #define BKP_DR4_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 697 | |||
| 698 | /******************* Bit definition for BKP_DR5 register ********************/ |
||
| 699 | #define BKP_DR5_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 700 | |||
| 701 | /******************* Bit definition for BKP_DR6 register ********************/ |
||
| 702 | #define BKP_DR6_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 703 | |||
| 704 | /******************* Bit definition for BKP_DR7 register ********************/ |
||
| 705 | #define BKP_DR7_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 706 | |||
| 707 | /******************* Bit definition for BKP_DR8 register ********************/ |
||
| 708 | #define BKP_DR8_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 709 | |||
| 710 | /******************* Bit definition for BKP_DR9 register ********************/ |
||
| 711 | #define BKP_DR9_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 712 | |||
| 713 | /******************* Bit definition for BKP_DR10 register *******************/ |
||
| 714 | #define BKP_DR10_D ((uint32_t)0x0000FFFF) /*!< Backup data */ |
||
| 715 | |||
| 716 | #define RTC_BKP_NUMBER 10 |
||
| 717 | |||
| 718 | /****************** Bit definition for BKP_RTCCR register *******************/ |
||
| 719 | #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /*!< Calibration value */ |
||
| 720 | #define BKP_RTCCR_CCO ((uint32_t)0x00000080) /*!< Calibration Clock Output */ |
||
| 721 | #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /*!< Alarm or Second Output Enable */ |
||
| 722 | #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /*!< Alarm or Second Output Selection */ |
||
| 723 | |||
| 724 | /******************** Bit definition for BKP_CR register ********************/ |
||
| 725 | #define BKP_CR_TPE ((uint32_t)0x00000001) /*!< TAMPER pin enable */ |
||
| 726 | #define BKP_CR_TPAL ((uint32_t)0x00000002) /*!< TAMPER pin active level */ |
||
| 727 | |||
| 728 | /******************* Bit definition for BKP_CSR register ********************/ |
||
| 729 | #define BKP_CSR_CTE ((uint32_t)0x00000001) /*!< Clear Tamper event */ |
||
| 730 | #define BKP_CSR_CTI ((uint32_t)0x00000002) /*!< Clear Tamper Interrupt */ |
||
| 731 | #define BKP_CSR_TPIE ((uint32_t)0x00000004) /*!< TAMPER Pin interrupt enable */ |
||
| 732 | #define BKP_CSR_TEF ((uint32_t)0x00000100) /*!< Tamper Event Flag */ |
||
| 733 | #define BKP_CSR_TIF ((uint32_t)0x00000200) /*!< Tamper Interrupt Flag */ |
||
| 734 | |||
| 735 | /******************************************************************************/ |
||
| 736 | /* */ |
||
| 737 | /* Reset and Clock Control */ |
||
| 738 | /* */ |
||
| 739 | /******************************************************************************/ |
||
| 740 | |||
| 741 | /******************** Bit definition for RCC_CR register ********************/ |
||
| 742 | #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ |
||
| 743 | #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ |
||
| 744 | #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ |
||
| 745 | #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ |
||
| 746 | #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ |
||
| 747 | #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ |
||
| 748 | #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ |
||
| 749 | #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ |
||
| 750 | #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ |
||
| 751 | #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ |
||
| 752 | |||
| 753 | |||
| 754 | /******************* Bit definition for RCC_CFGR register *******************/ |
||
| 755 | /*!< SW configuration */ |
||
| 756 | #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
||
| 757 | #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 758 | #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 759 | |||
| 760 | #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
||
| 761 | #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
||
| 762 | #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ |
||
| 763 | |||
| 764 | /*!< SWS configuration */ |
||
| 765 | #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
||
| 766 | #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
||
| 767 | #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
||
| 768 | |||
| 769 | #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
||
| 770 | #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
||
| 771 | #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ |
||
| 772 | |||
| 773 | /*!< HPRE configuration */ |
||
| 774 | #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
||
| 775 | #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 776 | #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 777 | #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
||
| 778 | #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
||
| 779 | |||
| 780 | #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
||
| 781 | #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
||
| 782 | #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
||
| 783 | #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
||
| 784 | #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
||
| 785 | #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
||
| 786 | #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
||
| 787 | #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
||
| 788 | #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
||
| 789 | |||
| 790 | /*!< PPRE1 configuration */ |
||
| 791 | #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ |
||
| 792 | #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 793 | #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 794 | #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 795 | |||
| 796 | #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
||
| 797 | #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ |
||
| 798 | #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ |
||
| 799 | #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ |
||
| 800 | #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ |
||
| 801 | |||
| 802 | /*!< PPRE2 configuration */ |
||
| 803 | #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
||
| 804 | #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ |
||
| 805 | #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ |
||
| 806 | #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ |
||
| 807 | |||
| 808 | #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
||
| 809 | #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ |
||
| 810 | #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ |
||
| 811 | #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ |
||
| 812 | #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ |
||
| 813 | |||
| 814 | /*!< ADCPPRE configuration */ |
||
| 815 | #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
||
| 816 | #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
||
| 817 | #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
||
| 818 | |||
| 819 | #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ |
||
| 820 | #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ |
||
| 821 | #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ |
||
| 822 | #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ |
||
| 823 | |||
| 824 | #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ |
||
| 825 | |||
| 826 | #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ |
||
| 827 | |||
| 828 | /*!< PLLMUL configuration */ |
||
| 829 | #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
||
| 830 | #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 831 | #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 832 | #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
||
| 833 | #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ |
||
| 834 | |||
| 835 | #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ |
||
| 836 | #define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ |
||
| 837 | |||
| 838 | #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
||
| 839 | #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
||
| 840 | #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
||
| 841 | #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
||
| 842 | #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
||
| 843 | #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
||
| 844 | #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
||
| 845 | #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
||
| 846 | #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
||
| 847 | #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
||
| 848 | #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
||
| 849 | #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
||
| 850 | #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
||
| 851 | #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
||
| 852 | #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
||
| 853 | |||
| 854 | /*!< MCO configuration */ |
||
| 855 | #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
||
| 856 | #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 857 | #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 858 | #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 859 | |||
| 860 | #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
||
| 861 | #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
||
| 862 | #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
||
| 863 | #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
||
| 864 | #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
||
| 865 | |||
| 866 | /*!<****************** Bit definition for RCC_CIR register ********************/ |
||
| 867 | #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ |
||
| 868 | #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ |
||
| 869 | #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ |
||
| 870 | #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ |
||
| 871 | #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ |
||
| 872 | #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ |
||
| 873 | #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ |
||
| 874 | #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ |
||
| 875 | #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ |
||
| 876 | #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ |
||
| 877 | #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ |
||
| 878 | #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ |
||
| 879 | #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ |
||
| 880 | #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ |
||
| 881 | #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ |
||
| 882 | #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ |
||
| 883 | #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ |
||
| 884 | |||
| 885 | |||
| 886 | /***************** Bit definition for RCC_APB2RSTR register *****************/ |
||
| 887 | #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ |
||
| 888 | #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ |
||
| 889 | #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ |
||
| 890 | #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ |
||
| 891 | #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ |
||
| 892 | #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ |
||
| 893 | |||
| 894 | |||
| 895 | #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ |
||
| 896 | #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ |
||
| 897 | #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ |
||
| 898 | |||
| 899 | |||
| 900 | #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ |
||
| 901 | |||
| 902 | |||
| 903 | |||
| 904 | |||
| 905 | /***************** Bit definition for RCC_APB1RSTR register *****************/ |
||
| 906 | #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ |
||
| 907 | #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ |
||
| 908 | #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ |
||
| 909 | #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ |
||
| 910 | #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ |
||
| 911 | |||
| 912 | |||
| 913 | #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ |
||
| 914 | #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ |
||
| 915 | |||
| 916 | #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ |
||
| 917 | #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ |
||
| 918 | #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ |
||
| 919 | #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ |
||
| 920 | |||
| 921 | |||
| 922 | |||
| 923 | |||
| 924 | |||
| 925 | |||
| 926 | |||
| 927 | /****************** Bit definition for RCC_AHBENR register ******************/ |
||
| 928 | #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ |
||
| 929 | #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ |
||
| 930 | #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ |
||
| 931 | #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ |
||
| 932 | |||
| 933 | |||
| 934 | |||
| 935 | |||
| 936 | /****************** Bit definition for RCC_APB2ENR register *****************/ |
||
| 937 | #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ |
||
| 938 | #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ |
||
| 939 | #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ |
||
| 940 | #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ |
||
| 941 | #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ |
||
| 942 | #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ |
||
| 943 | |||
| 944 | |||
| 945 | #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ |
||
| 946 | #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ |
||
| 947 | #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ |
||
| 948 | |||
| 949 | |||
| 950 | #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ |
||
| 951 | |||
| 952 | |||
| 953 | |||
| 954 | |||
| 955 | /***************** Bit definition for RCC_APB1ENR register ******************/ |
||
| 956 | #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ |
||
| 957 | #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ |
||
| 958 | #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ |
||
| 959 | #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ |
||
| 960 | #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ |
||
| 961 | |||
| 962 | |||
| 963 | #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ |
||
| 964 | #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ |
||
| 965 | |||
| 966 | #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ |
||
| 967 | #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ |
||
| 968 | #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ |
||
| 969 | #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ |
||
| 970 | |||
| 971 | |||
| 972 | |||
| 973 | |||
| 974 | |||
| 975 | |||
| 976 | |||
| 977 | /******************* Bit definition for RCC_BDCR register *******************/ |
||
| 978 | #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ |
||
| 979 | #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ |
||
| 980 | #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ |
||
| 981 | |||
| 982 | #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
||
| 983 | #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 984 | #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 985 | |||
| 986 | /*!< RTC congiguration */ |
||
| 987 | #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
||
| 988 | #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ |
||
| 989 | #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ |
||
| 990 | #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
||
| 991 | |||
| 992 | #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ |
||
| 993 | #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ |
||
| 994 | |||
| 995 | /******************* Bit definition for RCC_CSR register ********************/ |
||
| 996 | #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ |
||
| 997 | #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ |
||
| 998 | #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ |
||
| 999 | #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ |
||
| 1000 | #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ |
||
| 1001 | #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ |
||
| 1002 | #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ |
||
| 1003 | #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ |
||
| 1004 | #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ |
||
| 1005 | |||
| 1006 | |||
| 1007 | |||
| 1008 | /******************************************************************************/ |
||
| 1009 | /* */ |
||
| 1010 | /* General Purpose and Alternate Function I/O */ |
||
| 1011 | /* */ |
||
| 1012 | /******************************************************************************/ |
||
| 1013 | |||
| 1014 | /******************* Bit definition for GPIO_CRL register *******************/ |
||
| 1015 | #define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
||
| 1016 | |||
| 1017 | #define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
||
| 1018 | #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 1019 | #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 1020 | |||
| 1021 | #define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
||
| 1022 | #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 1023 | #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 1024 | |||
| 1025 | #define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
||
| 1026 | #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 1027 | #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 1028 | |||
| 1029 | #define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
||
| 1030 | #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 1031 | #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 1032 | |||
| 1033 | #define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
||
| 1034 | #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 1035 | #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 1036 | |||
| 1037 | #define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
||
| 1038 | #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 1039 | #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 1040 | |||
| 1041 | #define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
||
| 1042 | #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 1043 | #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 1044 | |||
| 1045 | #define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
||
| 1046 | #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
||
| 1047 | #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
||
| 1048 | |||
| 1049 | #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
||
| 1050 | |||
| 1051 | #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
||
| 1052 | #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
||
| 1053 | #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
||
| 1054 | |||
| 1055 | #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
||
| 1056 | #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 1057 | #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 1058 | |||
| 1059 | #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
||
| 1060 | #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 1061 | #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 1062 | |||
| 1063 | #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
||
| 1064 | #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
||
| 1065 | #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
||
| 1066 | |||
| 1067 | #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
||
| 1068 | #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 1069 | #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 1070 | |||
| 1071 | #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
||
| 1072 | #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
||
| 1073 | #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
||
| 1074 | |||
| 1075 | #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
||
| 1076 | #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 1077 | #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 1078 | |||
| 1079 | #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
||
| 1080 | #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
||
| 1081 | #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
||
| 1082 | |||
| 1083 | /******************* Bit definition for GPIO_CRH register *******************/ |
||
| 1084 | #define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ |
||
| 1085 | |||
| 1086 | #define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
||
| 1087 | #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 1088 | #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 1089 | |||
| 1090 | #define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
||
| 1091 | #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 1092 | #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 1093 | |||
| 1094 | #define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
||
| 1095 | #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 1096 | #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 1097 | |||
| 1098 | #define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
||
| 1099 | #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 1100 | #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 1101 | |||
| 1102 | #define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
||
| 1103 | #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 1104 | #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 1105 | |||
| 1106 | #define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
||
| 1107 | #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 1108 | #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 1109 | |||
| 1110 | #define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
||
| 1111 | #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 1112 | #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 1113 | |||
| 1114 | #define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
||
| 1115 | #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ |
||
| 1116 | #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ |
||
| 1117 | |||
| 1118 | #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ |
||
| 1119 | |||
| 1120 | #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
||
| 1121 | #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
||
| 1122 | #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
||
| 1123 | |||
| 1124 | #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
||
| 1125 | #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 1126 | #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 1127 | |||
| 1128 | #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
||
| 1129 | #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 1130 | #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 1131 | |||
| 1132 | #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
||
| 1133 | #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
||
| 1134 | #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
||
| 1135 | |||
| 1136 | #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
||
| 1137 | #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 1138 | #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 1139 | |||
| 1140 | #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
||
| 1141 | #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
||
| 1142 | #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
||
| 1143 | |||
| 1144 | #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
||
| 1145 | #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
||
| 1146 | #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
||
| 1147 | |||
| 1148 | #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
||
| 1149 | #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ |
||
| 1150 | #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ |
||
| 1151 | |||
| 1152 | /*!<****************** Bit definition for GPIO_IDR register *******************/ |
||
| 1153 | #define GPIO_IDR_IDR0 ((uint32_t)0x0001) /*!< Port input data, bit 0 */ |
||
| 1154 | #define GPIO_IDR_IDR1 ((uint32_t)0x0002) /*!< Port input data, bit 1 */ |
||
| 1155 | #define GPIO_IDR_IDR2 ((uint32_t)0x0004) /*!< Port input data, bit 2 */ |
||
| 1156 | #define GPIO_IDR_IDR3 ((uint32_t)0x0008) /*!< Port input data, bit 3 */ |
||
| 1157 | #define GPIO_IDR_IDR4 ((uint32_t)0x0010) /*!< Port input data, bit 4 */ |
||
| 1158 | #define GPIO_IDR_IDR5 ((uint32_t)0x0020) /*!< Port input data, bit 5 */ |
||
| 1159 | #define GPIO_IDR_IDR6 ((uint32_t)0x0040) /*!< Port input data, bit 6 */ |
||
| 1160 | #define GPIO_IDR_IDR7 ((uint32_t)0x0080) /*!< Port input data, bit 7 */ |
||
| 1161 | #define GPIO_IDR_IDR8 ((uint32_t)0x0100) /*!< Port input data, bit 8 */ |
||
| 1162 | #define GPIO_IDR_IDR9 ((uint32_t)0x0200) /*!< Port input data, bit 9 */ |
||
| 1163 | #define GPIO_IDR_IDR10 ((uint32_t)0x0400) /*!< Port input data, bit 10 */ |
||
| 1164 | #define GPIO_IDR_IDR11 ((uint32_t)0x0800) /*!< Port input data, bit 11 */ |
||
| 1165 | #define GPIO_IDR_IDR12 ((uint32_t)0x1000) /*!< Port input data, bit 12 */ |
||
| 1166 | #define GPIO_IDR_IDR13 ((uint32_t)0x2000) /*!< Port input data, bit 13 */ |
||
| 1167 | #define GPIO_IDR_IDR14 ((uint32_t)0x4000) /*!< Port input data, bit 14 */ |
||
| 1168 | #define GPIO_IDR_IDR15 ((uint32_t)0x8000) /*!< Port input data, bit 15 */ |
||
| 1169 | |||
| 1170 | /******************* Bit definition for GPIO_ODR register *******************/ |
||
| 1171 | #define GPIO_ODR_ODR0 ((uint32_t)0x0001) /*!< Port output data, bit 0 */ |
||
| 1172 | #define GPIO_ODR_ODR1 ((uint32_t)0x0002) /*!< Port output data, bit 1 */ |
||
| 1173 | #define GPIO_ODR_ODR2 ((uint32_t)0x0004) /*!< Port output data, bit 2 */ |
||
| 1174 | #define GPIO_ODR_ODR3 ((uint32_t)0x0008) /*!< Port output data, bit 3 */ |
||
| 1175 | #define GPIO_ODR_ODR4 ((uint32_t)0x0010) /*!< Port output data, bit 4 */ |
||
| 1176 | #define GPIO_ODR_ODR5 ((uint32_t)0x0020) /*!< Port output data, bit 5 */ |
||
| 1177 | #define GPIO_ODR_ODR6 ((uint32_t)0x0040) /*!< Port output data, bit 6 */ |
||
| 1178 | #define GPIO_ODR_ODR7 ((uint32_t)0x0080) /*!< Port output data, bit 7 */ |
||
| 1179 | #define GPIO_ODR_ODR8 ((uint32_t)0x0100) /*!< Port output data, bit 8 */ |
||
| 1180 | #define GPIO_ODR_ODR9 ((uint32_t)0x0200) /*!< Port output data, bit 9 */ |
||
| 1181 | #define GPIO_ODR_ODR10 ((uint32_t)0x0400) /*!< Port output data, bit 10 */ |
||
| 1182 | #define GPIO_ODR_ODR11 ((uint32_t)0x0800) /*!< Port output data, bit 11 */ |
||
| 1183 | #define GPIO_ODR_ODR12 ((uint32_t)0x1000) /*!< Port output data, bit 12 */ |
||
| 1184 | #define GPIO_ODR_ODR13 ((uint32_t)0x2000) /*!< Port output data, bit 13 */ |
||
| 1185 | #define GPIO_ODR_ODR14 ((uint32_t)0x4000) /*!< Port output data, bit 14 */ |
||
| 1186 | #define GPIO_ODR_ODR15 ((uint32_t)0x8000) /*!< Port output data, bit 15 */ |
||
| 1187 | |||
| 1188 | /****************** Bit definition for GPIO_BSRR register *******************/ |
||
| 1189 | #define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ |
||
| 1190 | #define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ |
||
| 1191 | #define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ |
||
| 1192 | #define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ |
||
| 1193 | #define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ |
||
| 1194 | #define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ |
||
| 1195 | #define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ |
||
| 1196 | #define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ |
||
| 1197 | #define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ |
||
| 1198 | #define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ |
||
| 1199 | #define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ |
||
| 1200 | #define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ |
||
| 1201 | #define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ |
||
| 1202 | #define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ |
||
| 1203 | #define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ |
||
| 1204 | #define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ |
||
| 1205 | |||
| 1206 | #define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ |
||
| 1207 | #define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ |
||
| 1208 | #define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ |
||
| 1209 | #define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ |
||
| 1210 | #define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ |
||
| 1211 | #define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ |
||
| 1212 | #define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ |
||
| 1213 | #define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ |
||
| 1214 | #define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ |
||
| 1215 | #define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ |
||
| 1216 | #define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ |
||
| 1217 | #define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ |
||
| 1218 | #define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ |
||
| 1219 | #define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ |
||
| 1220 | #define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ |
||
| 1221 | #define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ |
||
| 1222 | |||
| 1223 | /******************* Bit definition for GPIO_BRR register *******************/ |
||
| 1224 | #define GPIO_BRR_BR0 ((uint32_t)0x0001) /*!< Port x Reset bit 0 */ |
||
| 1225 | #define GPIO_BRR_BR1 ((uint32_t)0x0002) /*!< Port x Reset bit 1 */ |
||
| 1226 | #define GPIO_BRR_BR2 ((uint32_t)0x0004) /*!< Port x Reset bit 2 */ |
||
| 1227 | #define GPIO_BRR_BR3 ((uint32_t)0x0008) /*!< Port x Reset bit 3 */ |
||
| 1228 | #define GPIO_BRR_BR4 ((uint32_t)0x0010) /*!< Port x Reset bit 4 */ |
||
| 1229 | #define GPIO_BRR_BR5 ((uint32_t)0x0020) /*!< Port x Reset bit 5 */ |
||
| 1230 | #define GPIO_BRR_BR6 ((uint32_t)0x0040) /*!< Port x Reset bit 6 */ |
||
| 1231 | #define GPIO_BRR_BR7 ((uint32_t)0x0080) /*!< Port x Reset bit 7 */ |
||
| 1232 | #define GPIO_BRR_BR8 ((uint32_t)0x0100) /*!< Port x Reset bit 8 */ |
||
| 1233 | #define GPIO_BRR_BR9 ((uint32_t)0x0200) /*!< Port x Reset bit 9 */ |
||
| 1234 | #define GPIO_BRR_BR10 ((uint32_t)0x0400) /*!< Port x Reset bit 10 */ |
||
| 1235 | #define GPIO_BRR_BR11 ((uint32_t)0x0800) /*!< Port x Reset bit 11 */ |
||
| 1236 | #define GPIO_BRR_BR12 ((uint32_t)0x1000) /*!< Port x Reset bit 12 */ |
||
| 1237 | #define GPIO_BRR_BR13 ((uint32_t)0x2000) /*!< Port x Reset bit 13 */ |
||
| 1238 | #define GPIO_BRR_BR14 ((uint32_t)0x4000) /*!< Port x Reset bit 14 */ |
||
| 1239 | #define GPIO_BRR_BR15 ((uint32_t)0x8000) /*!< Port x Reset bit 15 */ |
||
| 1240 | |||
| 1241 | /****************** Bit definition for GPIO_LCKR register *******************/ |
||
| 1242 | #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ |
||
| 1243 | #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ |
||
| 1244 | #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ |
||
| 1245 | #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ |
||
| 1246 | #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ |
||
| 1247 | #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ |
||
| 1248 | #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ |
||
| 1249 | #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ |
||
| 1250 | #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ |
||
| 1251 | #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ |
||
| 1252 | #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ |
||
| 1253 | #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ |
||
| 1254 | #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ |
||
| 1255 | #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ |
||
| 1256 | #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ |
||
| 1257 | #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ |
||
| 1258 | #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ |
||
| 1259 | |||
| 1260 | /*----------------------------------------------------------------------------*/ |
||
| 1261 | |||
| 1262 | /****************** Bit definition for AFIO_EVCR register *******************/ |
||
| 1263 | #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /*!< PIN[3:0] bits (Pin selection) */ |
||
| 1264 | #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 1265 | #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 1266 | #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 1267 | #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 1268 | |||
| 1269 | /*!< PIN configuration */ |
||
| 1270 | #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */ |
||
| 1271 | #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /*!< Pin 1 selected */ |
||
| 1272 | #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /*!< Pin 2 selected */ |
||
| 1273 | #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /*!< Pin 3 selected */ |
||
| 1274 | #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /*!< Pin 4 selected */ |
||
| 1275 | #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /*!< Pin 5 selected */ |
||
| 1276 | #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /*!< Pin 6 selected */ |
||
| 1277 | #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /*!< Pin 7 selected */ |
||
| 1278 | #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /*!< Pin 8 selected */ |
||
| 1279 | #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /*!< Pin 9 selected */ |
||
| 1280 | #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /*!< Pin 10 selected */ |
||
| 1281 | #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /*!< Pin 11 selected */ |
||
| 1282 | #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /*!< Pin 12 selected */ |
||
| 1283 | #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /*!< Pin 13 selected */ |
||
| 1284 | #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /*!< Pin 14 selected */ |
||
| 1285 | #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /*!< Pin 15 selected */ |
||
| 1286 | |||
| 1287 | #define AFIO_EVCR_PORT ((uint32_t)0x00000070) /*!< PORT[2:0] bits (Port selection) */ |
||
| 1288 | #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 1289 | #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 1290 | #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
||
| 1291 | |||
| 1292 | /*!< PORT configuration */ |
||
| 1293 | #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */ |
||
| 1294 | #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /*!< Port B selected */ |
||
| 1295 | #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /*!< Port C selected */ |
||
| 1296 | #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /*!< Port D selected */ |
||
| 1297 | #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /*!< Port E selected */ |
||
| 1298 | |||
| 1299 | #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /*!< Event Output Enable */ |
||
| 1300 | |||
| 1301 | /****************** Bit definition for AFIO_MAPR register *******************/ |
||
| 1302 | #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ |
||
| 1303 | #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ |
||
| 1304 | #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ |
||
| 1305 | #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ |
||
| 1306 | |||
| 1307 | #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
||
| 1308 | #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
||
| 1309 | #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
||
| 1310 | |||
| 1311 | /* USART3_REMAP configuration */ |
||
| 1312 | #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
||
| 1313 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
||
| 1314 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
||
| 1315 | |||
| 1316 | #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
||
| 1317 | #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 1318 | #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 1319 | |||
| 1320 | /*!< TIM1_REMAP configuration */ |
||
| 1321 | #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
||
| 1322 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
||
| 1323 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
||
| 1324 | |||
| 1325 | #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
||
| 1326 | #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 1327 | #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 1328 | |||
| 1329 | /*!< TIM2_REMAP configuration */ |
||
| 1330 | #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
||
| 1331 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
||
| 1332 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
||
| 1333 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
||
| 1334 | |||
| 1335 | #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
||
| 1336 | #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 1337 | #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 1338 | |||
| 1339 | /*!< TIM3_REMAP configuration */ |
||
| 1340 | #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
||
| 1341 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
||
| 1342 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
||
| 1343 | |||
| 1344 | #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ |
||
| 1345 | |||
| 1346 | |||
| 1347 | #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
||
| 1348 | |||
| 1349 | /*!< SWJ_CFG configuration */ |
||
| 1350 | #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
||
| 1351 | #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 1352 | #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 1353 | #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 1354 | |||
| 1355 | #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
||
| 1356 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
||
| 1357 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ |
||
| 1358 | #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ |
||
| 1359 | |||
| 1360 | |||
| 1361 | /***************** Bit definition for AFIO_EXTICR1 register *****************/ |
||
| 1362 | #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */ |
||
| 1363 | #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */ |
||
| 1364 | #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */ |
||
| 1365 | #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */ |
||
| 1366 | |||
| 1367 | /*!< EXTI0 configuration */ |
||
| 1368 | #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ |
||
| 1369 | #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */ |
||
| 1370 | #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */ |
||
| 1371 | #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */ |
||
| 1372 | #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */ |
||
| 1373 | #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */ |
||
| 1374 | #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */ |
||
| 1375 | |||
| 1376 | /*!< EXTI1 configuration */ |
||
| 1377 | #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ |
||
| 1378 | #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */ |
||
| 1379 | #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */ |
||
| 1380 | #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */ |
||
| 1381 | #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */ |
||
| 1382 | #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */ |
||
| 1383 | #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */ |
||
| 1384 | |||
| 1385 | /*!< EXTI2 configuration */ |
||
| 1386 | #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ |
||
| 1387 | #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */ |
||
| 1388 | #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */ |
||
| 1389 | #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */ |
||
| 1390 | #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */ |
||
| 1391 | #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */ |
||
| 1392 | #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */ |
||
| 1393 | |||
| 1394 | /*!< EXTI3 configuration */ |
||
| 1395 | #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ |
||
| 1396 | #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */ |
||
| 1397 | #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */ |
||
| 1398 | #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */ |
||
| 1399 | #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */ |
||
| 1400 | #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */ |
||
| 1401 | #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */ |
||
| 1402 | |||
| 1403 | /***************** Bit definition for AFIO_EXTICR2 register *****************/ |
||
| 1404 | #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */ |
||
| 1405 | #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */ |
||
| 1406 | #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */ |
||
| 1407 | #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */ |
||
| 1408 | |||
| 1409 | /*!< EXTI4 configuration */ |
||
| 1410 | #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ |
||
| 1411 | #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */ |
||
| 1412 | #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */ |
||
| 1413 | #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */ |
||
| 1414 | #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */ |
||
| 1415 | #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */ |
||
| 1416 | #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */ |
||
| 1417 | |||
| 1418 | /* EXTI5 configuration */ |
||
| 1419 | #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ |
||
| 1420 | #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */ |
||
| 1421 | #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */ |
||
| 1422 | #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */ |
||
| 1423 | #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */ |
||
| 1424 | #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */ |
||
| 1425 | #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */ |
||
| 1426 | |||
| 1427 | /*!< EXTI6 configuration */ |
||
| 1428 | #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ |
||
| 1429 | #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */ |
||
| 1430 | #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */ |
||
| 1431 | #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */ |
||
| 1432 | #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */ |
||
| 1433 | #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */ |
||
| 1434 | #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */ |
||
| 1435 | |||
| 1436 | /*!< EXTI7 configuration */ |
||
| 1437 | #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ |
||
| 1438 | #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */ |
||
| 1439 | #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */ |
||
| 1440 | #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */ |
||
| 1441 | #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */ |
||
| 1442 | #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */ |
||
| 1443 | #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */ |
||
| 1444 | |||
| 1445 | /***************** Bit definition for AFIO_EXTICR3 register *****************/ |
||
| 1446 | #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */ |
||
| 1447 | #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */ |
||
| 1448 | #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */ |
||
| 1449 | #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */ |
||
| 1450 | |||
| 1451 | /*!< EXTI8 configuration */ |
||
| 1452 | #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ |
||
| 1453 | #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */ |
||
| 1454 | #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */ |
||
| 1455 | #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */ |
||
| 1456 | #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */ |
||
| 1457 | #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */ |
||
| 1458 | #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */ |
||
| 1459 | |||
| 1460 | /*!< EXTI9 configuration */ |
||
| 1461 | #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ |
||
| 1462 | #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */ |
||
| 1463 | #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */ |
||
| 1464 | #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */ |
||
| 1465 | #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */ |
||
| 1466 | #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */ |
||
| 1467 | #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */ |
||
| 1468 | |||
| 1469 | /*!< EXTI10 configuration */ |
||
| 1470 | #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ |
||
| 1471 | #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */ |
||
| 1472 | #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */ |
||
| 1473 | #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */ |
||
| 1474 | #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */ |
||
| 1475 | #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */ |
||
| 1476 | #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */ |
||
| 1477 | |||
| 1478 | /*!< EXTI11 configuration */ |
||
| 1479 | #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ |
||
| 1480 | #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */ |
||
| 1481 | #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */ |
||
| 1482 | #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */ |
||
| 1483 | #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */ |
||
| 1484 | #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */ |
||
| 1485 | #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */ |
||
| 1486 | |||
| 1487 | /***************** Bit definition for AFIO_EXTICR4 register *****************/ |
||
| 1488 | #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */ |
||
| 1489 | #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */ |
||
| 1490 | #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */ |
||
| 1491 | #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */ |
||
| 1492 | |||
| 1493 | /* EXTI12 configuration */ |
||
| 1494 | #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ |
||
| 1495 | #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */ |
||
| 1496 | #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */ |
||
| 1497 | #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */ |
||
| 1498 | #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */ |
||
| 1499 | #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */ |
||
| 1500 | #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */ |
||
| 1501 | |||
| 1502 | /* EXTI13 configuration */ |
||
| 1503 | #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ |
||
| 1504 | #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */ |
||
| 1505 | #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */ |
||
| 1506 | #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */ |
||
| 1507 | #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */ |
||
| 1508 | #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */ |
||
| 1509 | #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */ |
||
| 1510 | |||
| 1511 | /*!< EXTI14 configuration */ |
||
| 1512 | #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ |
||
| 1513 | #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */ |
||
| 1514 | #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */ |
||
| 1515 | #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */ |
||
| 1516 | #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */ |
||
| 1517 | #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */ |
||
| 1518 | #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */ |
||
| 1519 | |||
| 1520 | /*!< EXTI15 configuration */ |
||
| 1521 | #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ |
||
| 1522 | #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */ |
||
| 1523 | #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */ |
||
| 1524 | #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */ |
||
| 1525 | #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */ |
||
| 1526 | #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */ |
||
| 1527 | #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */ |
||
| 1528 | |||
| 1529 | /****************** Bit definition for AFIO_MAPR2 register ******************/ |
||
| 1530 | |||
| 1531 | |||
| 1532 | |||
| 1533 | /******************************************************************************/ |
||
| 1534 | /* */ |
||
| 1535 | /* SystemTick */ |
||
| 1536 | /* */ |
||
| 1537 | /******************************************************************************/ |
||
| 1538 | |||
| 1539 | /***************** Bit definition for SysTick_CTRL register *****************/ |
||
| 1540 | #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ |
||
| 1541 | #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ |
||
| 1542 | #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ |
||
| 1543 | #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ |
||
| 1544 | |||
| 1545 | /***************** Bit definition for SysTick_LOAD register *****************/ |
||
| 1546 | #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ |
||
| 1547 | |||
| 1548 | /***************** Bit definition for SysTick_VAL register ******************/ |
||
| 1549 | #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ |
||
| 1550 | |||
| 1551 | /***************** Bit definition for SysTick_CALIB register ****************/ |
||
| 1552 | #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ |
||
| 1553 | #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ |
||
| 1554 | #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ |
||
| 1555 | |||
| 1556 | /******************************************************************************/ |
||
| 1557 | /* */ |
||
| 1558 | /* Nested Vectored Interrupt Controller */ |
||
| 1559 | /* */ |
||
| 1560 | /******************************************************************************/ |
||
| 1561 | |||
| 1562 | /****************** Bit definition for NVIC_ISER register *******************/ |
||
| 1563 | #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ |
||
| 1564 | #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 1565 | #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 1566 | #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 1567 | #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 1568 | #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 1569 | #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 1570 | #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 1571 | #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 1572 | #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 1573 | #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 1574 | #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 1575 | #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 1576 | #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 1577 | #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 1578 | #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 1579 | #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 1580 | #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 1581 | #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 1582 | #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 1583 | #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 1584 | #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 1585 | #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 1586 | #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 1587 | #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 1588 | #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 1589 | #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 1590 | #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 1591 | #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 1592 | #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 1593 | #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 1594 | #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 1595 | #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 1596 | |||
| 1597 | /****************** Bit definition for NVIC_ICER register *******************/ |
||
| 1598 | #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ |
||
| 1599 | #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 1600 | #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 1601 | #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 1602 | #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 1603 | #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 1604 | #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 1605 | #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 1606 | #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 1607 | #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 1608 | #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 1609 | #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 1610 | #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 1611 | #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 1612 | #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 1613 | #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 1614 | #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 1615 | #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 1616 | #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 1617 | #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 1618 | #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 1619 | #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 1620 | #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 1621 | #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 1622 | #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 1623 | #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 1624 | #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 1625 | #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 1626 | #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 1627 | #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 1628 | #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 1629 | #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 1630 | #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 1631 | |||
| 1632 | /****************** Bit definition for NVIC_ISPR register *******************/ |
||
| 1633 | #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ |
||
| 1634 | #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 1635 | #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 1636 | #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 1637 | #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 1638 | #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 1639 | #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 1640 | #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 1641 | #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 1642 | #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 1643 | #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 1644 | #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 1645 | #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 1646 | #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 1647 | #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 1648 | #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 1649 | #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 1650 | #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 1651 | #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 1652 | #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 1653 | #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 1654 | #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 1655 | #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 1656 | #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 1657 | #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 1658 | #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 1659 | #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 1660 | #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 1661 | #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 1662 | #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 1663 | #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 1664 | #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 1665 | #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 1666 | |||
| 1667 | /****************** Bit definition for NVIC_ICPR register *******************/ |
||
| 1668 | #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ |
||
| 1669 | #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 1670 | #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 1671 | #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 1672 | #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 1673 | #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 1674 | #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 1675 | #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 1676 | #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 1677 | #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 1678 | #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 1679 | #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 1680 | #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 1681 | #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 1682 | #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 1683 | #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 1684 | #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 1685 | #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 1686 | #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 1687 | #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 1688 | #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 1689 | #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 1690 | #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 1691 | #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 1692 | #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 1693 | #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 1694 | #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 1695 | #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 1696 | #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 1697 | #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 1698 | #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 1699 | #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 1700 | #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 1701 | |||
| 1702 | /****************** Bit definition for NVIC_IABR register *******************/ |
||
| 1703 | #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ |
||
| 1704 | #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ |
||
| 1705 | #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ |
||
| 1706 | #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ |
||
| 1707 | #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ |
||
| 1708 | #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ |
||
| 1709 | #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ |
||
| 1710 | #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ |
||
| 1711 | #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ |
||
| 1712 | #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ |
||
| 1713 | #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ |
||
| 1714 | #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ |
||
| 1715 | #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ |
||
| 1716 | #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ |
||
| 1717 | #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ |
||
| 1718 | #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ |
||
| 1719 | #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ |
||
| 1720 | #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ |
||
| 1721 | #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ |
||
| 1722 | #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ |
||
| 1723 | #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ |
||
| 1724 | #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ |
||
| 1725 | #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ |
||
| 1726 | #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ |
||
| 1727 | #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ |
||
| 1728 | #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ |
||
| 1729 | #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ |
||
| 1730 | #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ |
||
| 1731 | #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ |
||
| 1732 | #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ |
||
| 1733 | #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ |
||
| 1734 | #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ |
||
| 1735 | #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ |
||
| 1736 | |||
| 1737 | /****************** Bit definition for NVIC_PRI0 register *******************/ |
||
| 1738 | #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ |
||
| 1739 | #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ |
||
| 1740 | #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ |
||
| 1741 | #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ |
||
| 1742 | |||
| 1743 | /****************** Bit definition for NVIC_PRI1 register *******************/ |
||
| 1744 | #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ |
||
| 1745 | #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ |
||
| 1746 | #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ |
||
| 1747 | #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ |
||
| 1748 | |||
| 1749 | /****************** Bit definition for NVIC_PRI2 register *******************/ |
||
| 1750 | #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ |
||
| 1751 | #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ |
||
| 1752 | #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ |
||
| 1753 | #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ |
||
| 1754 | |||
| 1755 | /****************** Bit definition for NVIC_PRI3 register *******************/ |
||
| 1756 | #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ |
||
| 1757 | #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ |
||
| 1758 | #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ |
||
| 1759 | #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ |
||
| 1760 | |||
| 1761 | /****************** Bit definition for NVIC_PRI4 register *******************/ |
||
| 1762 | #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ |
||
| 1763 | #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ |
||
| 1764 | #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ |
||
| 1765 | #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ |
||
| 1766 | |||
| 1767 | /****************** Bit definition for NVIC_PRI5 register *******************/ |
||
| 1768 | #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ |
||
| 1769 | #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ |
||
| 1770 | #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ |
||
| 1771 | #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ |
||
| 1772 | |||
| 1773 | /****************** Bit definition for NVIC_PRI6 register *******************/ |
||
| 1774 | #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ |
||
| 1775 | #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ |
||
| 1776 | #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ |
||
| 1777 | #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ |
||
| 1778 | |||
| 1779 | /****************** Bit definition for NVIC_PRI7 register *******************/ |
||
| 1780 | #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ |
||
| 1781 | #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ |
||
| 1782 | #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ |
||
| 1783 | #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ |
||
| 1784 | |||
| 1785 | /****************** Bit definition for SCB_CPUID register *******************/ |
||
| 1786 | #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ |
||
| 1787 | #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ |
||
| 1788 | #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ |
||
| 1789 | #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ |
||
| 1790 | #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ |
||
| 1791 | |||
| 1792 | /******************* Bit definition for SCB_ICSR register *******************/ |
||
| 1793 | #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ |
||
| 1794 | #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ |
||
| 1795 | #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ |
||
| 1796 | #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ |
||
| 1797 | #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ |
||
| 1798 | #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ |
||
| 1799 | #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ |
||
| 1800 | #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ |
||
| 1801 | #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ |
||
| 1802 | #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ |
||
| 1803 | |||
| 1804 | /******************* Bit definition for SCB_VTOR register *******************/ |
||
| 1805 | #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ |
||
| 1806 | #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ |
||
| 1807 | |||
| 1808 | /*!<***************** Bit definition for SCB_AIRCR register *******************/ |
||
| 1809 | #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ |
||
| 1810 | #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ |
||
| 1811 | #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ |
||
| 1812 | |||
| 1813 | #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ |
||
| 1814 | #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 1815 | #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 1816 | #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
||
| 1817 | |||
| 1818 | /* prority group configuration */ |
||
| 1819 | #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ |
||
| 1820 | #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ |
||
| 1821 | #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ |
||
| 1822 | #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ |
||
| 1823 | #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ |
||
| 1824 | #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ |
||
| 1825 | #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ |
||
| 1826 | #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ |
||
| 1827 | |||
| 1828 | #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ |
||
| 1829 | #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ |
||
| 1830 | |||
| 1831 | /******************* Bit definition for SCB_SCR register ********************/ |
||
| 1832 | #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */ |
||
| 1833 | #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */ |
||
| 1834 | #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */ |
||
| 1835 | |||
| 1836 | /******************** Bit definition for SCB_CCR register *******************/ |
||
| 1837 | #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ |
||
| 1838 | #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ |
||
| 1839 | #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */ |
||
| 1840 | #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */ |
||
| 1841 | #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */ |
||
| 1842 | #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ |
||
| 1843 | |||
| 1844 | /******************* Bit definition for SCB_SHPR register ********************/ |
||
| 1845 | #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ |
||
| 1846 | #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ |
||
| 1847 | #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ |
||
| 1848 | #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ |
||
| 1849 | |||
| 1850 | /****************** Bit definition for SCB_SHCSR register *******************/ |
||
| 1851 | #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ |
||
| 1852 | #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ |
||
| 1853 | #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ |
||
| 1854 | #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ |
||
| 1855 | #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ |
||
| 1856 | #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ |
||
| 1857 | #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ |
||
| 1858 | #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ |
||
| 1859 | #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ |
||
| 1860 | #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ |
||
| 1861 | #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ |
||
| 1862 | #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ |
||
| 1863 | #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ |
||
| 1864 | #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ |
||
| 1865 | |||
| 1866 | /******************* Bit definition for SCB_CFSR register *******************/ |
||
| 1867 | /*!< MFSR */ |
||
| 1868 | #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ |
||
| 1869 | #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ |
||
| 1870 | #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ |
||
| 1871 | #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ |
||
| 1872 | #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ |
||
| 1873 | /*!< BFSR */ |
||
| 1874 | #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ |
||
| 1875 | #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ |
||
| 1876 | #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ |
||
| 1877 | #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ |
||
| 1878 | #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ |
||
| 1879 | #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ |
||
| 1880 | /*!< UFSR */ |
||
| 1881 | #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ |
||
| 1882 | #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ |
||
| 1883 | #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ |
||
| 1884 | #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ |
||
| 1885 | #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ |
||
| 1886 | #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ |
||
| 1887 | |||
| 1888 | /******************* Bit definition for SCB_HFSR register *******************/ |
||
| 1889 | #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ |
||
| 1890 | #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ |
||
| 1891 | #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ |
||
| 1892 | |||
| 1893 | /******************* Bit definition for SCB_DFSR register *******************/ |
||
| 1894 | #define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */ |
||
| 1895 | #define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */ |
||
| 1896 | #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */ |
||
| 1897 | #define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */ |
||
| 1898 | #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */ |
||
| 1899 | |||
| 1900 | /******************* Bit definition for SCB_MMFAR register ******************/ |
||
| 1901 | #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ |
||
| 1902 | |||
| 1903 | /******************* Bit definition for SCB_BFAR register *******************/ |
||
| 1904 | #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ |
||
| 1905 | |||
| 1906 | /******************* Bit definition for SCB_afsr register *******************/ |
||
| 1907 | #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ |
||
| 1908 | |||
| 1909 | /******************************************************************************/ |
||
| 1910 | /* */ |
||
| 1911 | /* External Interrupt/Event Controller */ |
||
| 1912 | /* */ |
||
| 1913 | /******************************************************************************/ |
||
| 1914 | |||
| 1915 | /******************* Bit definition for EXTI_IMR register *******************/ |
||
| 1916 | #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
||
| 1917 | #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
||
| 1918 | #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
||
| 1919 | #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
||
| 1920 | #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
||
| 1921 | #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
||
| 1922 | #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
||
| 1923 | #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
||
| 1924 | #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
||
| 1925 | #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
||
| 1926 | #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
||
| 1927 | #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
||
| 1928 | #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
||
| 1929 | #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
||
| 1930 | #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
||
| 1931 | #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
||
| 1932 | #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
||
| 1933 | #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
||
| 1934 | #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
||
| 1935 | #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
||
| 1936 | |||
| 1937 | /******************* Bit definition for EXTI_EMR register *******************/ |
||
| 1938 | #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
||
| 1939 | #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
||
| 1940 | #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
||
| 1941 | #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
||
| 1942 | #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
||
| 1943 | #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
||
| 1944 | #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
||
| 1945 | #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
||
| 1946 | #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
||
| 1947 | #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
||
| 1948 | #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
||
| 1949 | #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
||
| 1950 | #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
||
| 1951 | #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
||
| 1952 | #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
||
| 1953 | #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
||
| 1954 | #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
||
| 1955 | #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
||
| 1956 | #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
||
| 1957 | #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
||
| 1958 | |||
| 1959 | /****************** Bit definition for EXTI_RTSR register *******************/ |
||
| 1960 | #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
||
| 1961 | #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
||
| 1962 | #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
||
| 1963 | #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
||
| 1964 | #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
||
| 1965 | #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
||
| 1966 | #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
||
| 1967 | #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
||
| 1968 | #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
||
| 1969 | #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
||
| 1970 | #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
||
| 1971 | #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
||
| 1972 | #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
||
| 1973 | #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
||
| 1974 | #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
||
| 1975 | #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
||
| 1976 | #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
||
| 1977 | #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ |
||
| 1978 | #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
||
| 1979 | #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
||
| 1980 | |||
| 1981 | /****************** Bit definition for EXTI_FTSR register *******************/ |
||
| 1982 | #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
||
| 1983 | #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
||
| 1984 | #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
||
| 1985 | #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
||
| 1986 | #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
||
| 1987 | #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
||
| 1988 | #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
||
| 1989 | #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
||
| 1990 | #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
||
| 1991 | #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
||
| 1992 | #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
||
| 1993 | #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
||
| 1994 | #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
||
| 1995 | #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
||
| 1996 | #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
||
| 1997 | #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
||
| 1998 | #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
||
| 1999 | #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ |
||
| 2000 | #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
||
| 2001 | #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
||
| 2002 | |||
| 2003 | /****************** Bit definition for EXTI_SWIER register ******************/ |
||
| 2004 | #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
||
| 2005 | #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
||
| 2006 | #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
||
| 2007 | #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
||
| 2008 | #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
||
| 2009 | #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
||
| 2010 | #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
||
| 2011 | #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
||
| 2012 | #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
||
| 2013 | #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
||
| 2014 | #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
||
| 2015 | #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
||
| 2016 | #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
||
| 2017 | #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
||
| 2018 | #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
||
| 2019 | #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
||
| 2020 | #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
||
| 2021 | #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ |
||
| 2022 | #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
||
| 2023 | #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
||
| 2024 | |||
| 2025 | /******************* Bit definition for EXTI_PR register ********************/ |
||
| 2026 | #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
||
| 2027 | #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
||
| 2028 | #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
||
| 2029 | #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
||
| 2030 | #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
||
| 2031 | #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
||
| 2032 | #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
||
| 2033 | #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
||
| 2034 | #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
||
| 2035 | #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
||
| 2036 | #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
||
| 2037 | #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
||
| 2038 | #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
||
| 2039 | #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
||
| 2040 | #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
||
| 2041 | #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
||
| 2042 | #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
||
| 2043 | #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ |
||
| 2044 | #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
||
| 2045 | #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
||
| 2046 | |||
| 2047 | /******************************************************************************/ |
||
| 2048 | /* */ |
||
| 2049 | /* DMA Controller */ |
||
| 2050 | /* */ |
||
| 2051 | /******************************************************************************/ |
||
| 2052 | |||
| 2053 | /******************* Bit definition for DMA_ISR register ********************/ |
||
| 2054 | #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ |
||
| 2055 | #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ |
||
| 2056 | #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ |
||
| 2057 | #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ |
||
| 2058 | #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ |
||
| 2059 | #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ |
||
| 2060 | #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ |
||
| 2061 | #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ |
||
| 2062 | #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ |
||
| 2063 | #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ |
||
| 2064 | #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ |
||
| 2065 | #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ |
||
| 2066 | #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ |
||
| 2067 | #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ |
||
| 2068 | #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ |
||
| 2069 | #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ |
||
| 2070 | #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ |
||
| 2071 | #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ |
||
| 2072 | #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ |
||
| 2073 | #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ |
||
| 2074 | #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ |
||
| 2075 | #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ |
||
| 2076 | #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ |
||
| 2077 | #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ |
||
| 2078 | #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ |
||
| 2079 | #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ |
||
| 2080 | #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ |
||
| 2081 | #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ |
||
| 2082 | |||
| 2083 | /******************* Bit definition for DMA_IFCR register *******************/ |
||
| 2084 | #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ |
||
| 2085 | #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ |
||
| 2086 | #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ |
||
| 2087 | #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ |
||
| 2088 | #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ |
||
| 2089 | #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ |
||
| 2090 | #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ |
||
| 2091 | #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ |
||
| 2092 | #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ |
||
| 2093 | #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ |
||
| 2094 | #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ |
||
| 2095 | #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ |
||
| 2096 | #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ |
||
| 2097 | #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ |
||
| 2098 | #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ |
||
| 2099 | #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ |
||
| 2100 | #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ |
||
| 2101 | #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ |
||
| 2102 | #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ |
||
| 2103 | #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ |
||
| 2104 | #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ |
||
| 2105 | #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ |
||
| 2106 | #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ |
||
| 2107 | #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ |
||
| 2108 | #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ |
||
| 2109 | #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ |
||
| 2110 | #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ |
||
| 2111 | #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ |
||
| 2112 | |||
| 2113 | /******************* Bit definition for DMA_CCR register *******************/ |
||
| 2114 | #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ |
||
| 2115 | #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ |
||
| 2116 | #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ |
||
| 2117 | #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ |
||
| 2118 | #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ |
||
| 2119 | #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ |
||
| 2120 | #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ |
||
| 2121 | #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ |
||
| 2122 | |||
| 2123 | #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
||
| 2124 | #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
||
| 2125 | #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
||
| 2126 | |||
| 2127 | #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ |
||
| 2128 | #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2129 | #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2130 | |||
| 2131 | #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */ |
||
| 2132 | #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 2133 | #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 2134 | |||
| 2135 | #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ |
||
| 2136 | |||
| 2137 | /****************** Bit definition for DMA_CNDTR register ******************/ |
||
| 2138 | #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ |
||
| 2139 | |||
| 2140 | /****************** Bit definition for DMA_CPAR register *******************/ |
||
| 2141 | #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
||
| 2142 | |||
| 2143 | /****************** Bit definition for DMA_CMAR register *******************/ |
||
| 2144 | #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
||
| 2145 | |||
| 2146 | /******************************************************************************/ |
||
| 2147 | /* */ |
||
| 2148 | /* Analog to Digital Converter */ |
||
| 2149 | /* */ |
||
| 2150 | /******************************************************************************/ |
||
| 2151 | |||
| 2152 | /******************** Bit definition for ADC_SR register ********************/ |
||
| 2153 | #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ |
||
| 2154 | #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ |
||
| 2155 | #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ |
||
| 2156 | #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ |
||
| 2157 | #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ |
||
| 2158 | |||
| 2159 | /******************* Bit definition for ADC_CR1 register ********************/ |
||
| 2160 | #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
||
| 2161 | #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2162 | #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2163 | #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2164 | #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2165 | #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2166 | |||
| 2167 | #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ |
||
| 2168 | #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ |
||
| 2169 | #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ |
||
| 2170 | #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ |
||
| 2171 | #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ |
||
| 2172 | #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ |
||
| 2173 | #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ |
||
| 2174 | #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ |
||
| 2175 | |||
| 2176 | #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
||
| 2177 | #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
||
| 2178 | #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
||
| 2179 | #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
||
| 2180 | |||
| 2181 | #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ |
||
| 2182 | #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ |
||
| 2183 | |||
| 2184 | |||
| 2185 | /******************* Bit definition for ADC_CR2 register ********************/ |
||
| 2186 | #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ |
||
| 2187 | #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ |
||
| 2188 | #define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ |
||
| 2189 | #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ |
||
| 2190 | #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ |
||
| 2191 | #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ |
||
| 2192 | |||
| 2193 | #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ |
||
| 2194 | #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 2195 | #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 2196 | #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
||
| 2197 | |||
| 2198 | #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ |
||
| 2199 | |||
| 2200 | #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ |
||
| 2201 | #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
||
| 2202 | #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
||
| 2203 | #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
||
| 2204 | |||
| 2205 | #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ |
||
| 2206 | #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ |
||
| 2207 | #define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ |
||
| 2208 | #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ |
||
| 2209 | |||
| 2210 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
||
| 2211 | #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ |
||
| 2212 | #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2213 | #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2214 | #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2215 | |||
| 2216 | #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ |
||
| 2217 | #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
||
| 2218 | #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
||
| 2219 | #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
||
| 2220 | |||
| 2221 | #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ |
||
| 2222 | #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 2223 | #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 2224 | #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ |
||
| 2225 | |||
| 2226 | #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ |
||
| 2227 | #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 2228 | #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 2229 | #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
||
| 2230 | |||
| 2231 | #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ |
||
| 2232 | #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 2233 | #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 2234 | #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
||
| 2235 | |||
| 2236 | #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ |
||
| 2237 | #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2238 | #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2239 | #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2240 | |||
| 2241 | #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ |
||
| 2242 | #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 2243 | #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 2244 | #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
||
| 2245 | |||
| 2246 | #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ |
||
| 2247 | #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
||
| 2248 | #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
||
| 2249 | #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ |
||
| 2250 | |||
| 2251 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
||
| 2252 | #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ |
||
| 2253 | #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2254 | #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2255 | #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2256 | |||
| 2257 | #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ |
||
| 2258 | #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
||
| 2259 | #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
||
| 2260 | #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
||
| 2261 | |||
| 2262 | #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ |
||
| 2263 | #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 2264 | #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 2265 | #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ |
||
| 2266 | |||
| 2267 | #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ |
||
| 2268 | #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
||
| 2269 | #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
||
| 2270 | #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
||
| 2271 | |||
| 2272 | #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ |
||
| 2273 | #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 2274 | #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 2275 | #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ |
||
| 2276 | |||
| 2277 | #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ |
||
| 2278 | #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2279 | #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2280 | #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2281 | |||
| 2282 | #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ |
||
| 2283 | #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
||
| 2284 | #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
||
| 2285 | #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
||
| 2286 | |||
| 2287 | #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ |
||
| 2288 | #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
||
| 2289 | #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
||
| 2290 | #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ |
||
| 2291 | |||
| 2292 | #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ |
||
| 2293 | #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
||
| 2294 | #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
||
| 2295 | #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
||
| 2296 | |||
| 2297 | #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ |
||
| 2298 | #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ |
||
| 2299 | #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ |
||
| 2300 | #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ |
||
| 2301 | |||
| 2302 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
||
| 2303 | #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ |
||
| 2304 | |||
| 2305 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
||
| 2306 | #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ |
||
| 2307 | |||
| 2308 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
||
| 2309 | #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ |
||
| 2310 | |||
| 2311 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
||
| 2312 | #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ |
||
| 2313 | |||
| 2314 | /******************* Bit definition for ADC_HTR register ********************/ |
||
| 2315 | #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ |
||
| 2316 | |||
| 2317 | /******************* Bit definition for ADC_LTR register ********************/ |
||
| 2318 | #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ |
||
| 2319 | |||
| 2320 | /******************* Bit definition for ADC_SQR1 register *******************/ |
||
| 2321 | #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ |
||
| 2322 | #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2323 | #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2324 | #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2325 | #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2326 | #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2327 | |||
| 2328 | #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ |
||
| 2329 | #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 2330 | #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 2331 | #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 2332 | #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
||
| 2333 | #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
||
| 2334 | |||
| 2335 | #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ |
||
| 2336 | #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2337 | #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2338 | #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 2339 | #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 2340 | #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 2341 | |||
| 2342 | #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ |
||
| 2343 | #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2344 | #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2345 | #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2346 | #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
||
| 2347 | #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
||
| 2348 | |||
| 2349 | #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ |
||
| 2350 | #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 2351 | #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 2352 | #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
||
| 2353 | #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
||
| 2354 | |||
| 2355 | /******************* Bit definition for ADC_SQR2 register *******************/ |
||
| 2356 | #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ |
||
| 2357 | #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2358 | #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2359 | #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2360 | #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2361 | #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2362 | |||
| 2363 | #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ |
||
| 2364 | #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 2365 | #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 2366 | #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 2367 | #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
||
| 2368 | #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
||
| 2369 | |||
| 2370 | #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ |
||
| 2371 | #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2372 | #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2373 | #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 2374 | #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 2375 | #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 2376 | |||
| 2377 | #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ |
||
| 2378 | #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2379 | #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2380 | #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2381 | #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
||
| 2382 | #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
||
| 2383 | |||
| 2384 | #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ |
||
| 2385 | #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 2386 | #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 2387 | #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
||
| 2388 | #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
||
| 2389 | #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ |
||
| 2390 | |||
| 2391 | #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ |
||
| 2392 | #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ |
||
| 2393 | #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ |
||
| 2394 | #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ |
||
| 2395 | #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ |
||
| 2396 | #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ |
||
| 2397 | |||
| 2398 | /******************* Bit definition for ADC_SQR3 register *******************/ |
||
| 2399 | #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ |
||
| 2400 | #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2401 | #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2402 | #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2403 | #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2404 | #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2405 | |||
| 2406 | #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ |
||
| 2407 | #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 2408 | #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 2409 | #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 2410 | #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
||
| 2411 | #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
||
| 2412 | |||
| 2413 | #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ |
||
| 2414 | #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2415 | #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2416 | #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 2417 | #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 2418 | #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 2419 | |||
| 2420 | #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ |
||
| 2421 | #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2422 | #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2423 | #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2424 | #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
||
| 2425 | #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
||
| 2426 | |||
| 2427 | #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ |
||
| 2428 | #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 2429 | #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 2430 | #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ |
||
| 2431 | #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ |
||
| 2432 | #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ |
||
| 2433 | |||
| 2434 | #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ |
||
| 2435 | #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ |
||
| 2436 | #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ |
||
| 2437 | #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ |
||
| 2438 | #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ |
||
| 2439 | #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ |
||
| 2440 | |||
| 2441 | /******************* Bit definition for ADC_JSQR register *******************/ |
||
| 2442 | #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ |
||
| 2443 | #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2444 | #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2445 | #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2446 | #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2447 | #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2448 | |||
| 2449 | #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
||
| 2450 | #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
||
| 2451 | #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
||
| 2452 | #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
||
| 2453 | #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ |
||
| 2454 | #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ |
||
| 2455 | |||
| 2456 | #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
||
| 2457 | #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
||
| 2458 | #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
||
| 2459 | #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
||
| 2460 | #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ |
||
| 2461 | #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ |
||
| 2462 | |||
| 2463 | #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ |
||
| 2464 | #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ |
||
| 2465 | #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ |
||
| 2466 | #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ |
||
| 2467 | #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ |
||
| 2468 | #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ |
||
| 2469 | |||
| 2470 | #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ |
||
| 2471 | #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
||
| 2472 | #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
||
| 2473 | |||
| 2474 | /******************* Bit definition for ADC_JDR1 register *******************/ |
||
| 2475 | #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ |
||
| 2476 | |||
| 2477 | /******************* Bit definition for ADC_JDR2 register *******************/ |
||
| 2478 | #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ |
||
| 2479 | |||
| 2480 | /******************* Bit definition for ADC_JDR3 register *******************/ |
||
| 2481 | #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ |
||
| 2482 | |||
| 2483 | /******************* Bit definition for ADC_JDR4 register *******************/ |
||
| 2484 | #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ |
||
| 2485 | |||
| 2486 | /******************** Bit definition for ADC_DR register ********************/ |
||
| 2487 | #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ |
||
| 2488 | |||
| 2489 | |||
| 2490 | /*****************************************************************************/ |
||
| 2491 | /* */ |
||
| 2492 | /* Timers (TIM) */ |
||
| 2493 | /* */ |
||
| 2494 | /*****************************************************************************/ |
||
| 2495 | /******************* Bit definition for TIM_CR1 register *******************/ |
||
| 2496 | #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */ |
||
| 2497 | #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */ |
||
| 2498 | #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */ |
||
| 2499 | #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */ |
||
| 2500 | #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */ |
||
| 2501 | |||
| 2502 | #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
||
| 2503 | #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
||
| 2504 | #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
||
| 2505 | |||
| 2506 | #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */ |
||
| 2507 | |||
| 2508 | #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */ |
||
| 2509 | #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 2510 | #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 2511 | |||
| 2512 | /******************* Bit definition for TIM_CR2 register *******************/ |
||
| 2513 | #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */ |
||
| 2514 | #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */ |
||
| 2515 | #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */ |
||
| 2516 | |||
| 2517 | #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */ |
||
| 2518 | #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 2519 | #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 2520 | #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 2521 | |||
| 2522 | #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */ |
||
| 2523 | #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */ |
||
| 2524 | #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */ |
||
| 2525 | #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */ |
||
| 2526 | #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */ |
||
| 2527 | #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */ |
||
| 2528 | #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */ |
||
| 2529 | #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */ |
||
| 2530 | |||
| 2531 | /******************* Bit definition for TIM_SMCR register ******************/ |
||
| 2532 | #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */ |
||
| 2533 | #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 2534 | #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 2535 | #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
||
| 2536 | |||
| 2537 | #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */ |
||
| 2538 | |||
| 2539 | #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */ |
||
| 2540 | #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 2541 | #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 2542 | #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 2543 | |||
| 2544 | #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */ |
||
| 2545 | |||
| 2546 | #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */ |
||
| 2547 | #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 2548 | #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 2549 | #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
||
| 2550 | #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
||
| 2551 | |||
| 2552 | #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */ |
||
| 2553 | #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 2554 | #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 2555 | |||
| 2556 | #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */ |
||
| 2557 | #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */ |
||
| 2558 | |||
| 2559 | /******************* Bit definition for TIM_DIER register ******************/ |
||
| 2560 | #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */ |
||
| 2561 | #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */ |
||
| 2562 | #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */ |
||
| 2563 | #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */ |
||
| 2564 | #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */ |
||
| 2565 | #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */ |
||
| 2566 | #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */ |
||
| 2567 | #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */ |
||
| 2568 | #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */ |
||
| 2569 | #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */ |
||
| 2570 | #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */ |
||
| 2571 | #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */ |
||
| 2572 | #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */ |
||
| 2573 | #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */ |
||
| 2574 | #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */ |
||
| 2575 | |||
| 2576 | /******************** Bit definition for TIM_SR register *******************/ |
||
| 2577 | #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */ |
||
| 2578 | #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */ |
||
| 2579 | #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */ |
||
| 2580 | #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */ |
||
| 2581 | #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */ |
||
| 2582 | #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */ |
||
| 2583 | #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */ |
||
| 2584 | #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */ |
||
| 2585 | #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */ |
||
| 2586 | #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */ |
||
| 2587 | #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */ |
||
| 2588 | #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */ |
||
| 2589 | |||
| 2590 | /******************* Bit definition for TIM_EGR register *******************/ |
||
| 2591 | #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */ |
||
| 2592 | #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */ |
||
| 2593 | #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */ |
||
| 2594 | #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */ |
||
| 2595 | #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */ |
||
| 2596 | #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */ |
||
| 2597 | #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */ |
||
| 2598 | #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */ |
||
| 2599 | |||
| 2600 | /****************** Bit definition for TIM_CCMR1 register ******************/ |
||
| 2601 | #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
||
| 2602 | #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 2603 | #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 2604 | |||
| 2605 | #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */ |
||
| 2606 | #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */ |
||
| 2607 | |||
| 2608 | #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
||
| 2609 | #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 2610 | #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 2611 | #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 2612 | |||
| 2613 | #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */ |
||
| 2614 | |||
| 2615 | #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
||
| 2616 | #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 2617 | #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 2618 | |||
| 2619 | #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */ |
||
| 2620 | #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */ |
||
| 2621 | |||
| 2622 | #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
||
| 2623 | #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 2624 | #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 2625 | #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
||
| 2626 | |||
| 2627 | #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */ |
||
| 2628 | |||
| 2629 | /*---------------------------------------------------------------------------*/ |
||
| 2630 | |||
| 2631 | #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
||
| 2632 | #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
||
| 2633 | #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
||
| 2634 | |||
| 2635 | #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
||
| 2636 | #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 2637 | #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 2638 | #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 2639 | #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
||
| 2640 | |||
| 2641 | #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
||
| 2642 | #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
||
| 2643 | #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
||
| 2644 | |||
| 2645 | #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
||
| 2646 | #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 2647 | #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 2648 | #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
||
| 2649 | #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ |
||
| 2650 | |||
| 2651 | /****************** Bit definition for TIM_CCMR2 register ******************/ |
||
| 2652 | #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
||
| 2653 | #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 2654 | #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 2655 | |||
| 2656 | #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */ |
||
| 2657 | #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */ |
||
| 2658 | |||
| 2659 | #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
||
| 2660 | #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 2661 | #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 2662 | #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 2663 | |||
| 2664 | #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */ |
||
| 2665 | |||
| 2666 | #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
||
| 2667 | #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 2668 | #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 2669 | |||
| 2670 | #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ |
||
| 2671 | #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ |
||
| 2672 | |||
| 2673 | #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
||
| 2674 | #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 2675 | #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 2676 | #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
||
| 2677 | |||
| 2678 | #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ |
||
| 2679 | |||
| 2680 | /*---------------------------------------------------------------------------*/ |
||
| 2681 | |||
| 2682 | #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
||
| 2683 | #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
||
| 2684 | #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
||
| 2685 | |||
| 2686 | #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
||
| 2687 | #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
||
| 2688 | #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
||
| 2689 | #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
||
| 2690 | #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
||
| 2691 | |||
| 2692 | #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
||
| 2693 | #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
||
| 2694 | #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
||
| 2695 | |||
| 2696 | #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
||
| 2697 | #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
||
| 2698 | #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
||
| 2699 | #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
||
| 2700 | #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ |
||
| 2701 | |||
| 2702 | /******************* Bit definition for TIM_CCER register ******************/ |
||
| 2703 | #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */ |
||
| 2704 | #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */ |
||
| 2705 | #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */ |
||
| 2706 | #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */ |
||
| 2707 | #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */ |
||
| 2708 | #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */ |
||
| 2709 | #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */ |
||
| 2710 | #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */ |
||
| 2711 | #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */ |
||
| 2712 | #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */ |
||
| 2713 | #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */ |
||
| 2714 | #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */ |
||
| 2715 | #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */ |
||
| 2716 | #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */ |
||
| 2717 | #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */ |
||
| 2718 | |||
| 2719 | /******************* Bit definition for TIM_CNT register *******************/ |
||
| 2720 | #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ |
||
| 2721 | |||
| 2722 | /******************* Bit definition for TIM_PSC register *******************/ |
||
| 2723 | #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */ |
||
| 2724 | |||
| 2725 | /******************* Bit definition for TIM_ARR register *******************/ |
||
| 2726 | #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */ |
||
| 2727 | |||
| 2728 | /******************* Bit definition for TIM_RCR register *******************/ |
||
| 2729 | #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */ |
||
| 2730 | |||
| 2731 | /******************* Bit definition for TIM_CCR1 register ******************/ |
||
| 2732 | #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */ |
||
| 2733 | |||
| 2734 | /******************* Bit definition for TIM_CCR2 register ******************/ |
||
| 2735 | #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */ |
||
| 2736 | |||
| 2737 | /******************* Bit definition for TIM_CCR3 register ******************/ |
||
| 2738 | #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */ |
||
| 2739 | |||
| 2740 | /******************* Bit definition for TIM_CCR4 register ******************/ |
||
| 2741 | #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */ |
||
| 2742 | |||
| 2743 | /******************* Bit definition for TIM_BDTR register ******************/ |
||
| 2744 | #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
||
| 2745 | #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 2746 | #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 2747 | #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
||
| 2748 | #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
||
| 2749 | #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
||
| 2750 | #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
||
| 2751 | #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
||
| 2752 | #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
||
| 2753 | |||
| 2754 | #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */ |
||
| 2755 | #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 2756 | #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 2757 | |||
| 2758 | #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */ |
||
| 2759 | #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */ |
||
| 2760 | #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */ |
||
| 2761 | #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */ |
||
| 2762 | #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */ |
||
| 2763 | #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */ |
||
| 2764 | |||
| 2765 | /******************* Bit definition for TIM_DCR register *******************/ |
||
| 2766 | #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */ |
||
| 2767 | #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
||
| 2768 | #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
||
| 2769 | #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
||
| 2770 | #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
||
| 2771 | #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
||
| 2772 | |||
| 2773 | #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */ |
||
| 2774 | #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
||
| 2775 | #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
||
| 2776 | #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
||
| 2777 | #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
||
| 2778 | #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
||
| 2779 | |||
| 2780 | /******************* Bit definition for TIM_DMAR register ******************/ |
||
| 2781 | #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */ |
||
| 2782 | |||
| 2783 | /******************* Bit definition for TIM_OR register ********************/ |
||
| 2784 | |||
| 2785 | /******************************************************************************/ |
||
| 2786 | /* */ |
||
| 2787 | /* Real-Time Clock */ |
||
| 2788 | /* */ |
||
| 2789 | /******************************************************************************/ |
||
| 2790 | |||
| 2791 | /******************* Bit definition for RTC_CRH register ********************/ |
||
| 2792 | #define RTC_CRH_SECIE ((uint32_t)0x00000001) /*!< Second Interrupt Enable */ |
||
| 2793 | #define RTC_CRH_ALRIE ((uint32_t)0x00000002) /*!< Alarm Interrupt Enable */ |
||
| 2794 | #define RTC_CRH_OWIE ((uint32_t)0x00000004) /*!< OverfloW Interrupt Enable */ |
||
| 2795 | |||
| 2796 | /******************* Bit definition for RTC_CRL register ********************/ |
||
| 2797 | #define RTC_CRL_SECF ((uint32_t)0x00000001) /*!< Second Flag */ |
||
| 2798 | #define RTC_CRL_ALRF ((uint32_t)0x00000002) /*!< Alarm Flag */ |
||
| 2799 | #define RTC_CRL_OWF ((uint32_t)0x00000004) /*!< OverfloW Flag */ |
||
| 2800 | #define RTC_CRL_RSF ((uint32_t)0x00000008) /*!< Registers Synchronized Flag */ |
||
| 2801 | #define RTC_CRL_CNF ((uint32_t)0x00000010) /*!< Configuration Flag */ |
||
| 2802 | #define RTC_CRL_RTOFF ((uint32_t)0x00000020) /*!< RTC operation OFF */ |
||
| 2803 | |||
| 2804 | /******************* Bit definition for RTC_PRLH register *******************/ |
||
| 2805 | #define RTC_PRLH_PRL ((uint32_t)0x0000000F) /*!< RTC Prescaler Reload Value High */ |
||
| 2806 | |||
| 2807 | /******************* Bit definition for RTC_PRLL register *******************/ |
||
| 2808 | #define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /*!< RTC Prescaler Reload Value Low */ |
||
| 2809 | |||
| 2810 | /******************* Bit definition for RTC_DIVH register *******************/ |
||
| 2811 | #define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /*!< RTC Clock Divider High */ |
||
| 2812 | |||
| 2813 | /******************* Bit definition for RTC_DIVL register *******************/ |
||
| 2814 | #define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /*!< RTC Clock Divider Low */ |
||
| 2815 | |||
| 2816 | /******************* Bit definition for RTC_CNTH register *******************/ |
||
| 2817 | #define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter High */ |
||
| 2818 | |||
| 2819 | /******************* Bit definition for RTC_CNTL register *******************/ |
||
| 2820 | #define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter Low */ |
||
| 2821 | |||
| 2822 | /******************* Bit definition for RTC_ALRH register *******************/ |
||
| 2823 | #define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm High */ |
||
| 2824 | |||
| 2825 | /******************* Bit definition for RTC_ALRL register *******************/ |
||
| 2826 | #define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm Low */ |
||
| 2827 | |||
| 2828 | /******************************************************************************/ |
||
| 2829 | /* */ |
||
| 2830 | /* Independent WATCHDOG (IWDG) */ |
||
| 2831 | /* */ |
||
| 2832 | /******************************************************************************/ |
||
| 2833 | |||
| 2834 | /******************* Bit definition for IWDG_KR register ********************/ |
||
| 2835 | #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */ |
||
| 2836 | |||
| 2837 | /******************* Bit definition for IWDG_PR register ********************/ |
||
| 2838 | #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */ |
||
| 2839 | #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2840 | #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2841 | #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2842 | |||
| 2843 | /******************* Bit definition for IWDG_RLR register *******************/ |
||
| 2844 | #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */ |
||
| 2845 | |||
| 2846 | /******************* Bit definition for IWDG_SR register ********************/ |
||
| 2847 | #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */ |
||
| 2848 | #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */ |
||
| 2849 | |||
| 2850 | /******************************************************************************/ |
||
| 2851 | /* */ |
||
| 2852 | /* Window WATCHDOG */ |
||
| 2853 | /* */ |
||
| 2854 | /******************************************************************************/ |
||
| 2855 | |||
| 2856 | /******************* Bit definition for WWDG_CR register ********************/ |
||
| 2857 | #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
||
| 2858 | #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2859 | #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2860 | #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2861 | #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2862 | #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2863 | #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 2864 | #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 2865 | |||
| 2866 | #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */ |
||
| 2867 | |||
| 2868 | /******************* Bit definition for WWDG_CFR register *******************/ |
||
| 2869 | #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */ |
||
| 2870 | #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 2871 | #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 2872 | #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 2873 | #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 2874 | #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 2875 | #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 2876 | #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 2877 | |||
| 2878 | #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */ |
||
| 2879 | #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */ |
||
| 2880 | #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */ |
||
| 2881 | |||
| 2882 | #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */ |
||
| 2883 | |||
| 2884 | /******************* Bit definition for WWDG_SR register ********************/ |
||
| 2885 | #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */ |
||
| 2886 | |||
| 2887 | |||
| 2888 | /******************************************************************************/ |
||
| 2889 | /* */ |
||
| 2890 | /* SD host Interface */ |
||
| 2891 | /* */ |
||
| 2892 | /******************************************************************************/ |
||
| 2893 | |||
| 2894 | /****************** Bit definition for SDIO_POWER register ******************/ |
||
| 2895 | #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ |
||
| 2896 | #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!< Bit 0 */ |
||
| 2897 | #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!< Bit 1 */ |
||
| 2898 | |||
| 2899 | /****************** Bit definition for SDIO_CLKCR register ******************/ |
||
| 2900 | #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!< Clock divide factor */ |
||
| 2901 | #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!< Clock enable bit */ |
||
| 2902 | #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!< Power saving configuration bit */ |
||
| 2903 | #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!< Clock divider bypass enable bit */ |
||
| 2904 | |||
| 2905 | #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
||
| 2906 | #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!< Bit 0 */ |
||
| 2907 | #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!< Bit 1 */ |
||
| 2908 | |||
| 2909 | #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!< SDIO_CK dephasing selection bit */ |
||
| 2910 | #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!< HW Flow Control enable */ |
||
| 2911 | |||
| 2912 | /******************* Bit definition for SDIO_ARG register *******************/ |
||
| 2913 | #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ |
||
| 2914 | |||
| 2915 | /******************* Bit definition for SDIO_CMD register *******************/ |
||
| 2916 | #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!< Command Index */ |
||
| 2917 | |||
| 2918 | #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ |
||
| 2919 | #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */ |
||
| 2920 | #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */ |
||
| 2921 | |||
| 2922 | #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!< CPSM Waits for Interrupt Request */ |
||
| 2923 | #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
||
| 2924 | #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ |
||
| 2925 | #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!< SD I/O suspend command */ |
||
| 2926 | #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!< Enable CMD completion */ |
||
| 2927 | #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!< Not Interrupt Enable */ |
||
| 2928 | #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!< CE-ATA command */ |
||
| 2929 | |||
| 2930 | /***************** Bit definition for SDIO_RESPCMD register *****************/ |
||
| 2931 | #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!< Response command index */ |
||
| 2932 | |||
| 2933 | /****************** Bit definition for SDIO_RESP0 register ******************/ |
||
| 2934 | #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 2935 | |||
| 2936 | /****************** Bit definition for SDIO_RESP1 register ******************/ |
||
| 2937 | #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 2938 | |||
| 2939 | /****************** Bit definition for SDIO_RESP2 register ******************/ |
||
| 2940 | #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 2941 | |||
| 2942 | /****************** Bit definition for SDIO_RESP3 register ******************/ |
||
| 2943 | #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 2944 | |||
| 2945 | /****************** Bit definition for SDIO_RESP4 register ******************/ |
||
| 2946 | #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ |
||
| 2947 | |||
| 2948 | /****************** Bit definition for SDIO_DTIMER register *****************/ |
||
| 2949 | #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ |
||
| 2950 | |||
| 2951 | /****************** Bit definition for SDIO_DLEN register *******************/ |
||
| 2952 | #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ |
||
| 2953 | |||
| 2954 | /****************** Bit definition for SDIO_DCTRL register ******************/ |
||
| 2955 | #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!< Data transfer enabled bit */ |
||
| 2956 | #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!< Data transfer direction selection */ |
||
| 2957 | #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!< Data transfer mode selection */ |
||
| 2958 | #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!< DMA enabled bit */ |
||
| 2959 | |||
| 2960 | #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ |
||
| 2961 | #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!< Bit 0 */ |
||
| 2962 | #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!< Bit 1 */ |
||
| 2963 | #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!< Bit 2 */ |
||
| 2964 | #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!< Bit 3 */ |
||
| 2965 | |||
| 2966 | #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!< Read wait start */ |
||
| 2967 | #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!< Read wait stop */ |
||
| 2968 | #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!< Read wait mode */ |
||
| 2969 | #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!< SD I/O enable functions */ |
||
| 2970 | |||
| 2971 | /****************** Bit definition for SDIO_DCOUNT register *****************/ |
||
| 2972 | #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ |
||
| 2973 | |||
| 2974 | /****************** Bit definition for SDIO_STA register ********************/ |
||
| 2975 | #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ |
||
| 2976 | #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ |
||
| 2977 | #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ |
||
| 2978 | #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ |
||
| 2979 | #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ |
||
| 2980 | #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ |
||
| 2981 | #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ |
||
| 2982 | #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ |
||
| 2983 | #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ |
||
| 2984 | #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ |
||
| 2985 | #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ |
||
| 2986 | #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ |
||
| 2987 | #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ |
||
| 2988 | #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ |
||
| 2989 | #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
||
| 2990 | #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
||
| 2991 | #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ |
||
| 2992 | #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ |
||
| 2993 | #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ |
||
| 2994 | #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ |
||
| 2995 | #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ |
||
| 2996 | #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ |
||
| 2997 | #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ |
||
| 2998 | #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ |
||
| 2999 | |||
| 3000 | /******************* Bit definition for SDIO_ICR register *******************/ |
||
| 3001 | #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ |
||
| 3002 | #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ |
||
| 3003 | #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ |
||
| 3004 | #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ |
||
| 3005 | #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ |
||
| 3006 | #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ |
||
| 3007 | #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ |
||
| 3008 | #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ |
||
| 3009 | #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ |
||
| 3010 | #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ |
||
| 3011 | #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ |
||
| 3012 | #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ |
||
| 3013 | #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ |
||
| 3014 | |||
| 3015 | /****************** Bit definition for SDIO_MASK register *******************/ |
||
| 3016 | #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ |
||
| 3017 | #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ |
||
| 3018 | #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ |
||
| 3019 | #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ |
||
| 3020 | #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ |
||
| 3021 | #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ |
||
| 3022 | #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ |
||
| 3023 | #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ |
||
| 3024 | #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ |
||
| 3025 | #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ |
||
| 3026 | #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ |
||
| 3027 | #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ |
||
| 3028 | #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ |
||
| 3029 | #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ |
||
| 3030 | #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ |
||
| 3031 | #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ |
||
| 3032 | #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ |
||
| 3033 | #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ |
||
| 3034 | #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ |
||
| 3035 | #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ |
||
| 3036 | #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ |
||
| 3037 | #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ |
||
| 3038 | #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ |
||
| 3039 | #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ |
||
| 3040 | |||
| 3041 | /***************** Bit definition for SDIO_FIFOCNT register *****************/ |
||
| 3042 | #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ |
||
| 3043 | |||
| 3044 | /****************** Bit definition for SDIO_FIFO register *******************/ |
||
| 3045 | #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ |
||
| 3046 | |||
| 3047 | |||
| 3048 | |||
| 3049 | /******************************************************************************/ |
||
| 3050 | /* */ |
||
| 3051 | /* Serial Peripheral Interface */ |
||
| 3052 | /* */ |
||
| 3053 | /******************************************************************************/ |
||
| 3054 | |||
| 3055 | /******************* Bit definition for SPI_CR1 register ********************/ |
||
| 3056 | #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */ |
||
| 3057 | #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */ |
||
| 3058 | #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */ |
||
| 3059 | |||
| 3060 | #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */ |
||
| 3061 | #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
||
| 3062 | #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
||
| 3063 | #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
||
| 3064 | |||
| 3065 | #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */ |
||
| 3066 | #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */ |
||
| 3067 | #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */ |
||
| 3068 | #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */ |
||
| 3069 | #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */ |
||
| 3070 | #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */ |
||
| 3071 | #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */ |
||
| 3072 | #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */ |
||
| 3073 | #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */ |
||
| 3074 | #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */ |
||
| 3075 | |||
| 3076 | /******************* Bit definition for SPI_CR2 register ********************/ |
||
| 3077 | #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */ |
||
| 3078 | #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */ |
||
| 3079 | #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */ |
||
| 3080 | #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */ |
||
| 3081 | #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */ |
||
| 3082 | #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */ |
||
| 3083 | |||
| 3084 | /******************** Bit definition for SPI_SR register ********************/ |
||
| 3085 | #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */ |
||
| 3086 | #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */ |
||
| 3087 | #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */ |
||
| 3088 | #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */ |
||
| 3089 | #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */ |
||
| 3090 | #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */ |
||
| 3091 | #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */ |
||
| 3092 | #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */ |
||
| 3093 | |||
| 3094 | /******************** Bit definition for SPI_DR register ********************/ |
||
| 3095 | #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */ |
||
| 3096 | |||
| 3097 | /******************* Bit definition for SPI_CRCPR register ******************/ |
||
| 3098 | #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */ |
||
| 3099 | |||
| 3100 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
||
| 3101 | #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */ |
||
| 3102 | |||
| 3103 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
||
| 3104 | #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */ |
||
| 3105 | |||
| 3106 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
||
| 3107 | #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!< I2S mode selection */ |
||
| 3108 | |||
| 3109 | |||
| 3110 | /******************************************************************************/ |
||
| 3111 | /* */ |
||
| 3112 | /* Inter-integrated Circuit Interface */ |
||
| 3113 | /* */ |
||
| 3114 | /******************************************************************************/ |
||
| 3115 | |||
| 3116 | /******************* Bit definition for I2C_CR1 register ********************/ |
||
| 3117 | #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */ |
||
| 3118 | #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */ |
||
| 3119 | #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */ |
||
| 3120 | #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */ |
||
| 3121 | #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */ |
||
| 3122 | #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */ |
||
| 3123 | #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */ |
||
| 3124 | #define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */ |
||
| 3125 | #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */ |
||
| 3126 | #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */ |
||
| 3127 | #define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */ |
||
| 3128 | #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */ |
||
| 3129 | #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */ |
||
| 3130 | #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */ |
||
| 3131 | |||
| 3132 | /******************* Bit definition for I2C_CR2 register ********************/ |
||
| 3133 | #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ |
||
| 3134 | #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3135 | #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3136 | #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3137 | #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3138 | #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 3139 | #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 3140 | |||
| 3141 | #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */ |
||
| 3142 | #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */ |
||
| 3143 | #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */ |
||
| 3144 | #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */ |
||
| 3145 | #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */ |
||
| 3146 | |||
| 3147 | /******************* Bit definition for I2C_OAR1 register *******************/ |
||
| 3148 | #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */ |
||
| 3149 | #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */ |
||
| 3150 | |||
| 3151 | #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3152 | #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3153 | #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3154 | #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3155 | #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 3156 | #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 3157 | #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 3158 | #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
||
| 3159 | #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */ |
||
| 3160 | #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */ |
||
| 3161 | |||
| 3162 | #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */ |
||
| 3163 | |||
| 3164 | /******************* Bit definition for I2C_OAR2 register *******************/ |
||
| 3165 | #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */ |
||
| 3166 | #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */ |
||
| 3167 | |||
| 3168 | /******************* Bit definition for I2C_SR1 register ********************/ |
||
| 3169 | #define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */ |
||
| 3170 | #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */ |
||
| 3171 | #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */ |
||
| 3172 | #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */ |
||
| 3173 | #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */ |
||
| 3174 | #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */ |
||
| 3175 | #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */ |
||
| 3176 | #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */ |
||
| 3177 | #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */ |
||
| 3178 | #define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */ |
||
| 3179 | #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */ |
||
| 3180 | #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */ |
||
| 3181 | #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */ |
||
| 3182 | #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */ |
||
| 3183 | |||
| 3184 | /******************* Bit definition for I2C_SR2 register ********************/ |
||
| 3185 | #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */ |
||
| 3186 | #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */ |
||
| 3187 | #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */ |
||
| 3188 | #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */ |
||
| 3189 | #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */ |
||
| 3190 | #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */ |
||
| 3191 | #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */ |
||
| 3192 | #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */ |
||
| 3193 | |||
| 3194 | /******************* Bit definition for I2C_CCR register ********************/ |
||
| 3195 | #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ |
||
| 3196 | #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */ |
||
| 3197 | #define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */ |
||
| 3198 | |||
| 3199 | /****************** Bit definition for I2C_TRISE register *******************/ |
||
| 3200 | #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ |
||
| 3201 | |||
| 3202 | /******************************************************************************/ |
||
| 3203 | /* */ |
||
| 3204 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
||
| 3205 | /* */ |
||
| 3206 | /******************************************************************************/ |
||
| 3207 | |||
| 3208 | /******************* Bit definition for USART_SR register *******************/ |
||
| 3209 | #define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */ |
||
| 3210 | #define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */ |
||
| 3211 | #define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */ |
||
| 3212 | #define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */ |
||
| 3213 | #define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */ |
||
| 3214 | #define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */ |
||
| 3215 | #define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */ |
||
| 3216 | #define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */ |
||
| 3217 | #define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */ |
||
| 3218 | #define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */ |
||
| 3219 | |||
| 3220 | /******************* Bit definition for USART_DR register *******************/ |
||
| 3221 | #define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */ |
||
| 3222 | |||
| 3223 | /****************** Bit definition for USART_BRR register *******************/ |
||
| 3224 | #define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */ |
||
| 3225 | #define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */ |
||
| 3226 | |||
| 3227 | /****************** Bit definition for USART_CR1 register *******************/ |
||
| 3228 | #define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */ |
||
| 3229 | #define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */ |
||
| 3230 | #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */ |
||
| 3231 | #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */ |
||
| 3232 | #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */ |
||
| 3233 | #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */ |
||
| 3234 | #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */ |
||
| 3235 | #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */ |
||
| 3236 | #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */ |
||
| 3237 | #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */ |
||
| 3238 | #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */ |
||
| 3239 | #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */ |
||
| 3240 | #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */ |
||
| 3241 | #define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */ |
||
| 3242 | |||
| 3243 | /****************** Bit definition for USART_CR2 register *******************/ |
||
| 3244 | #define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */ |
||
| 3245 | #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */ |
||
| 3246 | #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */ |
||
| 3247 | #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */ |
||
| 3248 | #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */ |
||
| 3249 | #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */ |
||
| 3250 | #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */ |
||
| 3251 | |||
| 3252 | #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */ |
||
| 3253 | #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
||
| 3254 | #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
||
| 3255 | |||
| 3256 | #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */ |
||
| 3257 | |||
| 3258 | /****************** Bit definition for USART_CR3 register *******************/ |
||
| 3259 | #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */ |
||
| 3260 | #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */ |
||
| 3261 | #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */ |
||
| 3262 | #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */ |
||
| 3263 | #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */ |
||
| 3264 | #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */ |
||
| 3265 | #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */ |
||
| 3266 | #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */ |
||
| 3267 | #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */ |
||
| 3268 | #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */ |
||
| 3269 | #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */ |
||
| 3270 | |||
| 3271 | /****************** Bit definition for USART_GTPR register ******************/ |
||
| 3272 | #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */ |
||
| 3273 | #define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3274 | #define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3275 | #define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3276 | #define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
||
| 3277 | #define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
||
| 3278 | #define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
||
| 3279 | #define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
||
| 3280 | #define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
||
| 3281 | |||
| 3282 | #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */ |
||
| 3283 | |||
| 3284 | /******************************************************************************/ |
||
| 3285 | /* */ |
||
| 3286 | /* Debug MCU */ |
||
| 3287 | /* */ |
||
| 3288 | /******************************************************************************/ |
||
| 3289 | |||
| 3290 | /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
||
| 3291 | #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ |
||
| 3292 | |||
| 3293 | #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ |
||
| 3294 | #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
||
| 3295 | #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
||
| 3296 | #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
||
| 3297 | #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
||
| 3298 | #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
||
| 3299 | #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ |
||
| 3300 | #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ |
||
| 3301 | #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ |
||
| 3302 | #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ |
||
| 3303 | #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ |
||
| 3304 | #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ |
||
| 3305 | #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ |
||
| 3306 | #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ |
||
| 3307 | #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ |
||
| 3308 | #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ |
||
| 3309 | #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ |
||
| 3310 | |||
| 3311 | /****************** Bit definition for DBGMCU_CR register *******************/ |
||
| 3312 | #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ |
||
| 3313 | #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ |
||
| 3314 | #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ |
||
| 3315 | #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ |
||
| 3316 | |||
| 3317 | #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
||
| 3318 | #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
||
| 3319 | #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
||
| 3320 | |||
| 3321 | #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ |
||
| 3322 | #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ |
||
| 3323 | #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ |
||
| 3324 | #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ |
||
| 3325 | #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ |
||
| 3326 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ |
||
| 3327 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ |
||
| 3328 | |||
| 3329 | /******************************************************************************/ |
||
| 3330 | /* */ |
||
| 3331 | /* FLASH and Option Bytes Registers */ |
||
| 3332 | /* */ |
||
| 3333 | /******************************************************************************/ |
||
| 3334 | /******************* Bit definition for FLASH_ACR register ******************/ |
||
| 3335 | #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */ |
||
| 3336 | #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
||
| 3337 | #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
||
| 3338 | #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
||
| 3339 | |||
| 3340 | #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */ |
||
| 3341 | #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */ |
||
| 3342 | #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */ |
||
| 3343 | |||
| 3344 | /****************** Bit definition for FLASH_KEYR register ******************/ |
||
| 3345 | #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ |
||
| 3346 | |||
| 3347 | #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */ |
||
| 3348 | #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */ |
||
| 3349 | #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */ |
||
| 3350 | |||
| 3351 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
||
| 3352 | #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ |
||
| 3353 | |||
| 3354 | #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ |
||
| 3355 | #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ |
||
| 3356 | |||
| 3357 | /****************** Bit definition for FLASH_SR register ********************/ |
||
| 3358 | #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ |
||
| 3359 | #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ |
||
| 3360 | #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */ |
||
| 3361 | #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */ |
||
| 3362 | |||
| 3363 | /******************* Bit definition for FLASH_CR register *******************/ |
||
| 3364 | #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */ |
||
| 3365 | #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */ |
||
| 3366 | #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */ |
||
| 3367 | #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ |
||
| 3368 | #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */ |
||
| 3369 | #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */ |
||
| 3370 | #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */ |
||
| 3371 | #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ |
||
| 3372 | #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ |
||
| 3373 | #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ |
||
| 3374 | |||
| 3375 | /******************* Bit definition for FLASH_AR register *******************/ |
||
| 3376 | #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ |
||
| 3377 | |||
| 3378 | /****************** Bit definition for FLASH_OBR register *******************/ |
||
| 3379 | #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */ |
||
| 3380 | #define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /*!< Read protection */ |
||
| 3381 | |||
| 3382 | #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /*!< IWDG SW */ |
||
| 3383 | #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /*!< nRST_STOP */ |
||
| 3384 | #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /*!< nRST_STDBY */ |
||
| 3385 | #define FLASH_OBR_USER ((uint32_t)0x0000001C) /*!< User Option Bytes */ |
||
| 3386 | |||
| 3387 | /****************** Bit definition for FLASH_WRPR register ******************/ |
||
| 3388 | #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ |
||
| 3389 | |||
| 3390 | /*----------------------------------------------------------------------------*/ |
||
| 3391 | |||
| 3392 | /****************** Bit definition for FLASH_RDP register *******************/ |
||
| 3393 | #define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ |
||
| 3394 | #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ |
||
| 3395 | |||
| 3396 | /****************** Bit definition for FLASH_USER register ******************/ |
||
| 3397 | #define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ |
||
| 3398 | #define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ |
||
| 3399 | |||
| 3400 | /****************** Bit definition for FLASH_Data0 register *****************/ |
||
| 3401 | #define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ |
||
| 3402 | #define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ |
||
| 3403 | |||
| 3404 | /****************** Bit definition for FLASH_Data1 register *****************/ |
||
| 3405 | #define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ |
||
| 3406 | #define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ |
||
| 3407 | |||
| 3408 | /****************** Bit definition for FLASH_WRP0 register ******************/ |
||
| 3409 | #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ |
||
| 3410 | #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ |
||
| 3411 | |||
| 3412 | /****************** Bit definition for FLASH_WRP1 register ******************/ |
||
| 3413 | #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ |
||
| 3414 | #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ |
||
| 3415 | |||
| 3416 | /****************** Bit definition for FLASH_WRP2 register ******************/ |
||
| 3417 | #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ |
||
| 3418 | #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ |
||
| 3419 | |||
| 3420 | /****************** Bit definition for FLASH_WRP3 register ******************/ |
||
| 3421 | #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ |
||
| 3422 | #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ |
||
| 3423 | |||
| 3424 | |||
| 3425 | |||
| 3426 | /** |
||
| 3427 | * @} |
||
| 3428 | */ |
||
| 3429 | |||
| 3430 | /** |
||
| 3431 | * @} |
||
| 3432 | */ |
||
| 3433 | |||
| 3434 | /** @addtogroup Exported_macro |
||
| 3435 | * @{ |
||
| 3436 | */ |
||
| 3437 | |||
| 3438 | /****************************** ADC Instances *********************************/ |
||
| 3439 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1)) |
||
| 3440 | |||
| 3441 | #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
||
| 3442 | |||
| 3443 | /****************************** CRC Instances *********************************/ |
||
| 3444 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
||
| 3445 | |||
| 3446 | /****************************** DAC Instances *********************************/ |
||
| 3447 | |||
| 3448 | /****************************** DMA Instances *********************************/ |
||
| 3449 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
||
| 3450 | ((INSTANCE) == DMA1_Channel2) || \ |
||
| 3451 | ((INSTANCE) == DMA1_Channel3) || \ |
||
| 3452 | ((INSTANCE) == DMA1_Channel4) || \ |
||
| 3453 | ((INSTANCE) == DMA1_Channel5) || \ |
||
| 3454 | ((INSTANCE) == DMA1_Channel6) || \ |
||
| 3455 | ((INSTANCE) == DMA1_Channel7)) |
||
| 3456 | |||
| 3457 | /******************************* GPIO Instances *******************************/ |
||
| 3458 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
||
| 3459 | ((INSTANCE) == GPIOB) || \ |
||
| 3460 | ((INSTANCE) == GPIOC) || \ |
||
| 3461 | ((INSTANCE) == GPIOD) || \ |
||
| 3462 | ((INSTANCE) == GPIOE)) |
||
| 3463 | |||
| 3464 | /**************************** GPIO Alternate Function Instances ***************/ |
||
| 3465 | #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
||
| 3466 | |||
| 3467 | /**************************** GPIO Lock Instances *****************************/ |
||
| 3468 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
||
| 3469 | |||
| 3470 | /******************************** I2C Instances *******************************/ |
||
| 3471 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
||
| 3472 | ((INSTANCE) == I2C2)) |
||
| 3473 | |||
| 3474 | /****************************** IWDG Instances ********************************/ |
||
| 3475 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
||
| 3476 | |||
| 3477 | /******************************** SPI Instances *******************************/ |
||
| 3478 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
||
| 3479 | ((INSTANCE) == SPI2)) |
||
| 3480 | |||
| 3481 | /****************************** START TIM Instances ***************************/ |
||
| 3482 | /****************************** TIM Instances *********************************/ |
||
| 3483 | #define IS_TIM_INSTANCE(INSTANCE)\ |
||
| 3484 | (((INSTANCE) == TIM2) || \ |
||
| 3485 | ((INSTANCE) == TIM3) || \ |
||
| 3486 | ((INSTANCE) == TIM4)) |
||
| 3487 | |||
| 3488 | #define IS_TIM_CC1_INSTANCE(INSTANCE)\ |
||
| 3489 | (((INSTANCE) == TIM2) || \ |
||
| 3490 | ((INSTANCE) == TIM3) || \ |
||
| 3491 | ((INSTANCE) == TIM4)) |
||
| 3492 | |||
| 3493 | #define IS_TIM_CC2_INSTANCE(INSTANCE)\ |
||
| 3494 | (((INSTANCE) == TIM2) || \ |
||
| 3495 | ((INSTANCE) == TIM3) || \ |
||
| 3496 | ((INSTANCE) == TIM4)) |
||
| 3497 | |||
| 3498 | #define IS_TIM_CC3_INSTANCE(INSTANCE)\ |
||
| 3499 | (((INSTANCE) == TIM2) || \ |
||
| 3500 | ((INSTANCE) == TIM3) || \ |
||
| 3501 | ((INSTANCE) == TIM4)) |
||
| 3502 | |||
| 3503 | #define IS_TIM_CC4_INSTANCE(INSTANCE)\ |
||
| 3504 | (((INSTANCE) == TIM2) || \ |
||
| 3505 | ((INSTANCE) == TIM3) || \ |
||
| 3506 | ((INSTANCE) == TIM4)) |
||
| 3507 | |||
| 3508 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ |
||
| 3509 | (((INSTANCE) == TIM2) || \ |
||
| 3510 | ((INSTANCE) == TIM3) || \ |
||
| 3511 | ((INSTANCE) == TIM4)) |
||
| 3512 | |||
| 3513 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ |
||
| 3514 | (((INSTANCE) == TIM2) || \ |
||
| 3515 | ((INSTANCE) == TIM3) || \ |
||
| 3516 | ((INSTANCE) == TIM4)) |
||
| 3517 | |||
| 3518 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ |
||
| 3519 | (((INSTANCE) == TIM2) || \ |
||
| 3520 | ((INSTANCE) == TIM3) || \ |
||
| 3521 | ((INSTANCE) == TIM4)) |
||
| 3522 | |||
| 3523 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ |
||
| 3524 | (((INSTANCE) == TIM2) || \ |
||
| 3525 | ((INSTANCE) == TIM3) || \ |
||
| 3526 | ((INSTANCE) == TIM4)) |
||
| 3527 | |||
| 3528 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ |
||
| 3529 | (((INSTANCE) == TIM2) || \ |
||
| 3530 | ((INSTANCE) == TIM3) || \ |
||
| 3531 | ((INSTANCE) == TIM4)) |
||
| 3532 | |||
| 3533 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ |
||
| 3534 | (((INSTANCE) == TIM2) || \ |
||
| 3535 | ((INSTANCE) == TIM3) || \ |
||
| 3536 | ((INSTANCE) == TIM4)) |
||
| 3537 | |||
| 3538 | #define IS_TIM_XOR_INSTANCE(INSTANCE)\ |
||
| 3539 | (((INSTANCE) == TIM2) || \ |
||
| 3540 | ((INSTANCE) == TIM3) || \ |
||
| 3541 | ((INSTANCE) == TIM4)) |
||
| 3542 | |||
| 3543 | #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ |
||
| 3544 | (((INSTANCE) == TIM2) || \ |
||
| 3545 | ((INSTANCE) == TIM3) || \ |
||
| 3546 | ((INSTANCE) == TIM4)) |
||
| 3547 | |||
| 3548 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ |
||
| 3549 | (((INSTANCE) == TIM2) || \ |
||
| 3550 | ((INSTANCE) == TIM3) || \ |
||
| 3551 | ((INSTANCE) == TIM4)) |
||
| 3552 | |||
| 3553 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ |
||
| 3554 | (((INSTANCE) == TIM2) || \ |
||
| 3555 | ((INSTANCE) == TIM3) || \ |
||
| 3556 | ((INSTANCE) == TIM4)) |
||
| 3557 | |||
| 3558 | #define IS_TIM_BREAK_INSTANCE(INSTANCE) (0) |
||
| 3559 | |||
| 3560 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
||
| 3561 | ((((INSTANCE) == TIM2) && \ |
||
| 3562 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 3563 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 3564 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 3565 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 3566 | || \ |
||
| 3567 | (((INSTANCE) == TIM3) && \ |
||
| 3568 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 3569 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 3570 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 3571 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 3572 | || \ |
||
| 3573 | (((INSTANCE) == TIM4) && \ |
||
| 3574 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 3575 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 3576 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 3577 | ((CHANNEL) == TIM_CHANNEL_4)))) |
||
| 3578 | |||
| 3579 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0) |
||
| 3580 | |||
| 3581 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ |
||
| 3582 | (((INSTANCE) == TIM2) || \ |
||
| 3583 | ((INSTANCE) == TIM3) || \ |
||
| 3584 | ((INSTANCE) == TIM4)) |
||
| 3585 | |||
| 3586 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0) |
||
| 3587 | |||
| 3588 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ |
||
| 3589 | (((INSTANCE) == TIM2) || \ |
||
| 3590 | ((INSTANCE) == TIM3) || \ |
||
| 3591 | ((INSTANCE) == TIM4)) |
||
| 3592 | |||
| 3593 | #define IS_TIM_DMA_INSTANCE(INSTANCE)\ |
||
| 3594 | (((INSTANCE) == TIM2) || \ |
||
| 3595 | ((INSTANCE) == TIM3) || \ |
||
| 3596 | ((INSTANCE) == TIM4)) |
||
| 3597 | |||
| 3598 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ |
||
| 3599 | (((INSTANCE) == TIM2) || \ |
||
| 3600 | ((INSTANCE) == TIM3) || \ |
||
| 3601 | ((INSTANCE) == TIM4)) |
||
| 3602 | |||
| 3603 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0) |
||
| 3604 | |||
| 3605 | /****************************** END TIM Instances *****************************/ |
||
| 3606 | |||
| 3607 | |||
| 3608 | /******************** USART Instances : Synchronous mode **********************/ |
||
| 3609 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 3610 | ((INSTANCE) == USART2) || \ |
||
| 3611 | ((INSTANCE) == USART3)) |
||
| 3612 | |||
| 3613 | /******************** UART Instances : Asynchronous mode **********************/ |
||
| 3614 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 3615 | ((INSTANCE) == USART2) || \ |
||
| 3616 | ((INSTANCE) == USART3)) |
||
| 3617 | |||
| 3618 | /******************** UART Instances : Half-Duplex mode **********************/ |
||
| 3619 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 3620 | ((INSTANCE) == USART2) || \ |
||
| 3621 | ((INSTANCE) == USART3)) |
||
| 3622 | |||
| 3623 | /******************** UART Instances : LIN mode **********************/ |
||
| 3624 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 3625 | ((INSTANCE) == USART2) || \ |
||
| 3626 | ((INSTANCE) == USART3)) |
||
| 3627 | |||
| 3628 | /****************** UART Instances : Hardware Flow control ********************/ |
||
| 3629 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 3630 | ((INSTANCE) == USART2) || \ |
||
| 3631 | ((INSTANCE) == USART3)) |
||
| 3632 | |||
| 3633 | /********************* UART Instances : Smard card mode ***********************/ |
||
| 3634 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 3635 | ((INSTANCE) == USART2) || \ |
||
| 3636 | ((INSTANCE) == USART3)) |
||
| 3637 | |||
| 3638 | /*********************** UART Instances : IRDA mode ***************************/ |
||
| 3639 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 3640 | ((INSTANCE) == USART2) || \ |
||
| 3641 | ((INSTANCE) == USART3)) |
||
| 3642 | |||
| 3643 | /***************** UART Instances : Multi-Processor mode **********************/ |
||
| 3644 | #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 3645 | ((INSTANCE) == USART2) || \ |
||
| 3646 | ((INSTANCE) == USART3)) |
||
| 3647 | |||
| 3648 | /***************** UART Instances : DMA mode available **********************/ |
||
| 3649 | #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 3650 | ((INSTANCE) == USART2) || \ |
||
| 3651 | ((INSTANCE) == USART3)) |
||
| 3652 | |||
| 3653 | /****************************** RTC Instances *********************************/ |
||
| 3654 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
||
| 3655 | |||
| 3656 | /**************************** WWDG Instances *****************************/ |
||
| 3657 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
||
| 3658 | |||
| 3659 | |||
| 3660 | |||
| 3661 | |||
| 3662 | |||
| 3663 | /** |
||
| 3664 | * @} |
||
| 3665 | */ |
||
| 3666 | /******************************************************************************/ |
||
| 3667 | /* For a painless codes migration between the STM32F1xx device product */ |
||
| 3668 | /* lines, the aliases defined below are put in place to overcome the */ |
||
| 3669 | /* differences in the interrupt handlers and IRQn definitions. */ |
||
| 3670 | /* No need to update developed interrupt code when moving across */ |
||
| 3671 | /* product lines within the same STM32F1 Family */ |
||
| 3672 | /******************************************************************************/ |
||
| 3673 | |||
| 3674 | /* Aliases for __IRQn */ |
||
| 3675 | #define ADC1_2_IRQn ADC1_IRQn |
||
| 3676 | |||
| 3677 | |||
| 3678 | /* Aliases for __IRQHandler */ |
||
| 3679 | #define ADC1_2_IRQHandler ADC1_IRQHandler |
||
| 3680 | |||
| 3681 | |||
| 3682 | /** |
||
| 3683 | * @} |
||
| 3684 | */ |
||
| 3685 | |||
| 3686 | /** |
||
| 3687 | * @} |
||
| 3688 | */ |
||
| 3689 | |||
| 3690 | |||
| 3691 | #ifdef __cplusplus |
||
| 3692 | } |
||
| 3693 | #endif /* __cplusplus */ |
||
| 3694 | |||
| 3695 | #endif /* __STM32F101xB_H */ |
||
| 3696 | |||
| 3697 | |||
| 3698 | |||
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