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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f100xe.h
		4	* @author MCD Application Team
		5	* @version V4.0.1
		6	* @date 31-July-2015
		7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		8	* This file contains all the peripheral register's definitions, bits
		9	* definitions and memory mapping for STM32F1xx devices.
		10	*
		11	* This file contains:
		12	* - Data structures and the address mapping for all peripherals
		13	* - Peripheral's registers declarations and bits definition
		14	* - Macros to access peripheral�s registers hardware
		15	*
		16	******************************************************************************
		17	* @attention
		18	*
		19	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
		20	*
		21	* Redistribution and use in source and binary forms, with or without modification,
		22	* are permitted provided that the following conditions are met:
		23	* 1. Redistributions of source code must retain the above copyright notice,
		24	* this list of conditions and the following disclaimer.
		25	* 2. Redistributions in binary form must reproduce the above copyright notice,
		26	* this list of conditions and the following disclaimer in the documentation
		27	* and/or other materials provided with the distribution.
		28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		29	* may be used to endorse or promote products derived from this software
		30	* without specific prior written permission.
		31	*
		32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		42	*
		43	******************************************************************************
		44	*/
		45
		46
		47	/** @addtogroup CMSIS
		48	* @{
		49	*/
		50
		51	/** @addtogroup stm32f100xe
		52	* @{
		53	*/
		54
		55	#ifndef __STM32F100xE_H
		56	#define __STM32F100xE_H
		57
		58	#ifdef __cplusplus
		59	extern "C" {
		60	#endif
		61
		62	/** @addtogroup Configuration_section_for_CMSIS
		63	* @{
		64	*/
		65	/**
		66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		67	*/
		68	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
		69	#define __CM3_REV 0x0200 /!< Core Revision r2p0 /
		70	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
		71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
		72
		73	/**
		74	* @}
		75	*/
		76
		77	/** @addtogroup Peripheral_interrupt_number_definition
		78	* @{
		79	*/
		80
		81	/**
		82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
		83	* in @ref Library_configuration_section
		84	*/
		85
		86	/!< Interrupt Number Definition /
		87	typedef enum
		88	{
		89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
		90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
		91	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		92	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		93	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		94	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		95	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		96	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		97	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		98
		99	/**** STM32 specific Interrupt Numbers *******************************************************/
		100	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		101	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		102	TAMPER_IRQn = 2, /!< Tamper Interrupt /
		103	RTC_IRQn = 3, /!< RTC global Interrupt /
		104	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		105	RCC_IRQn = 5, /!< RCC global Interrupt /
		106	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		107	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		108	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		109	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		110	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		111	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		112	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		113	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		114	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		115	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		116	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		117	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		118	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
		119	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		120	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
		121	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
		122	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
		123	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
		124	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		125	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		126	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		127	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		128	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		129	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		130	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		131	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		132	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		133	USART1_IRQn = 37, /!< USART1 global Interrupt /
		134	USART2_IRQn = 38, /!< USART2 global Interrupt /
		135	USART3_IRQn = 39, /!< USART3 global Interrupt /
		136	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		137	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		138	CEC_IRQn = 42, /!< HDMI-CEC Interrupt /
		139	TIM12_IRQn = 43, /!< TIM12 global Interrupt /
		140	TIM13_IRQn = 44, /!< TIM13 global Interrupt /
		141	TIM14_IRQn = 45, /!< TIM14 global Interrupt /
		142	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
		143	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
		144	UART4_IRQn = 52, /!< UART4 global Interrupt /
		145	UART5_IRQn = 53, /!< UART5 global Interrupt /
		146	TIM6_DAC_IRQn = 54, /!< TIM6 and DAC underrun Interrupt /
		147	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
		148	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
		149	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
		150	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
		151	DMA2_Channel4_5_IRQn = 59, /!< DMA2 Channel 4 and Channel 5 global Interrupt /
		152	DMA2_Channel4_IRQn = 59, /!< DMA2 Channel 4 global Interrupt /
		153	DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
		154	mapped at position 60 only if the MISC_REMAP bit in
		155	the AFIO_MAPR2 register is set) */
		156	} IRQn_Type;
		157
		158
		159	/**
		160	* @}
		161	*/
		162
		163	#include "core_cm3.h"
		164	#include "system_stm32f1xx.h"
		165	#include <stdint.h>
		166
		167	/** @addtogroup Peripheral_registers_structures
		168	* @{
		169	*/
		170
		171	/**
		172	* @brief Analog to Digital Converter
		173	*/
		174
		175	typedef struct
		176	{
		177	__IO uint32_t SR;
		178	__IO uint32_t CR1;
		179	__IO uint32_t CR2;
		180	__IO uint32_t SMPR1;
		181	__IO uint32_t SMPR2;
		182	__IO uint32_t JOFR1;
		183	__IO uint32_t JOFR2;
		184	__IO uint32_t JOFR3;
		185	__IO uint32_t JOFR4;
		186	__IO uint32_t HTR;
		187	__IO uint32_t LTR;
		188	__IO uint32_t SQR1;
		189	__IO uint32_t SQR2;
		190	__IO uint32_t SQR3;
		191	__IO uint32_t JSQR;
		192	__IO uint32_t JDR1;
		193	__IO uint32_t JDR2;
		194	__IO uint32_t JDR3;
		195	__IO uint32_t JDR4;
		196	__IO uint32_t DR;
		197	} ADC_TypeDef;
		198
		199	/**
		200	* @brief Backup Registers
		201	*/
		202
		203	typedef struct
		204	{
		205	uint32_t RESERVED0;
		206	__IO uint32_t DR1;
		207	__IO uint32_t DR2;
		208	__IO uint32_t DR3;
		209	__IO uint32_t DR4;
		210	__IO uint32_t DR5;
		211	__IO uint32_t DR6;
		212	__IO uint32_t DR7;
		213	__IO uint32_t DR8;
		214	__IO uint32_t DR9;
		215	__IO uint32_t DR10;
		216	__IO uint32_t RTCCR;
		217	__IO uint32_t CR;
		218	__IO uint32_t CSR;
		219	uint32_t RESERVED13[2];
		220	__IO uint32_t DR11;
		221	__IO uint32_t DR12;
		222	__IO uint32_t DR13;
		223	__IO uint32_t DR14;
		224	__IO uint32_t DR15;
		225	__IO uint32_t DR16;
		226	__IO uint32_t DR17;
		227	__IO uint32_t DR18;
		228	__IO uint32_t DR19;
		229	__IO uint32_t DR20;
		230	__IO uint32_t DR21;
		231	__IO uint32_t DR22;
		232	__IO uint32_t DR23;
		233	__IO uint32_t DR24;
		234	__IO uint32_t DR25;
		235	__IO uint32_t DR26;
		236	__IO uint32_t DR27;
		237	__IO uint32_t DR28;
		238	__IO uint32_t DR29;
		239	__IO uint32_t DR30;
		240	__IO uint32_t DR31;
		241	__IO uint32_t DR32;
		242	__IO uint32_t DR33;
		243	__IO uint32_t DR34;
		244	__IO uint32_t DR35;
		245	__IO uint32_t DR36;
		246	__IO uint32_t DR37;
		247	__IO uint32_t DR38;
		248	__IO uint32_t DR39;
		249	__IO uint32_t DR40;
		250	__IO uint32_t DR41;
		251	__IO uint32_t DR42;
		252	} BKP_TypeDef;
		253
		254
		255	/**
		256	* @brief Consumer Electronics Control (CEC)
		257	*/
		258	typedef struct
		259	{
		260	__IO uint32_t CFGR;
		261	__IO uint32_t OAR;
		262	__IO uint32_t PRES;
		263	__IO uint32_t ESR;
		264	__IO uint32_t CSR;
		265	__IO uint32_t TXD;
		266	__IO uint32_t RXD;
		267	} CEC_TypeDef;
		268
		269	/**
		270	* @brief CRC calculation unit
		271	*/
		272
		273	typedef struct
		274	{
		275	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		276	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		277	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		278	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		279	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		280	} CRC_TypeDef;
		281
		282	/**
		283	* @brief Digital to Analog Converter
		284	*/
		285
		286	typedef struct
		287	{
		288	__IO uint32_t CR;
		289	__IO uint32_t SWTRIGR;
		290	__IO uint32_t DHR12R1;
		291	__IO uint32_t DHR12L1;
		292	__IO uint32_t DHR8R1;
		293	__IO uint32_t DHR12R2;
		294	__IO uint32_t DHR12L2;
		295	__IO uint32_t DHR8R2;
		296	__IO uint32_t DHR12RD;
		297	__IO uint32_t DHR12LD;
		298	__IO uint32_t DHR8RD;
		299	__IO uint32_t DOR1;
		300	__IO uint32_t DOR2;
		301	__IO uint32_t SR;
		302	} DAC_TypeDef;
		303
		304	/**
		305	* @brief Debug MCU
		306	*/
		307
		308	typedef struct
		309	{
		310	__IO uint32_t IDCODE;
		311	__IO uint32_t CR;
		312	}DBGMCU_TypeDef;
		313
		314	/**
		315	* @brief DMA Controller
		316	*/
		317
		318	typedef struct
		319	{
		320	__IO uint32_t CCR;
		321	__IO uint32_t CNDTR;
		322	__IO uint32_t CPAR;
		323	__IO uint32_t CMAR;
		324	} DMA_Channel_TypeDef;
		325
		326	typedef struct
		327	{
		328	__IO uint32_t ISR;
		329	__IO uint32_t IFCR;
		330	} DMA_TypeDef;
		331
		332
		333
		334	/**
		335	* @brief External Interrupt/Event Controller
		336	*/
		337
		338	typedef struct
		339	{
		340	__IO uint32_t IMR;
		341	__IO uint32_t EMR;
		342	__IO uint32_t RTSR;
		343	__IO uint32_t FTSR;
		344	__IO uint32_t SWIER;
		345	__IO uint32_t PR;
		346	} EXTI_TypeDef;
		347
		348	/**
		349	* @brief FLASH Registers
		350	*/
		351
		352	typedef struct
		353	{
		354	__IO uint32_t ACR;
		355	__IO uint32_t KEYR;
		356	__IO uint32_t OPTKEYR;
		357	__IO uint32_t SR;
		358	__IO uint32_t CR;
		359	__IO uint32_t AR;
		360	__IO uint32_t RESERVED;
		361	__IO uint32_t OBR;
		362	__IO uint32_t WRPR;
		363	} FLASH_TypeDef;
		364
		365	/**
		366	* @brief Option Bytes Registers
		367	*/
		368
		369	typedef struct
		370	{
		371	__IO uint16_t RDP;
		372	__IO uint16_t USER;
		373	__IO uint16_t Data0;
		374	__IO uint16_t Data1;
		375	__IO uint16_t WRP0;
		376	__IO uint16_t WRP1;
		377	__IO uint16_t WRP2;
		378	__IO uint16_t WRP3;
		379	} OB_TypeDef;
		380
		381	/**
		382	* @brief Flexible Static Memory Controller
		383	*/
		384
		385	typedef struct
		386	{
		387	__IO uint32_t BTCR[8];
		388	} FSMC_Bank1_TypeDef;
		389
		390	/**
		391	* @brief Flexible Static Memory Controller Bank1E
		392	*/
		393
		394	typedef struct
		395	{
		396	__IO uint32_t BWTR[7];
		397	} FSMC_Bank1E_TypeDef;
		398
		399	/**
		400	* @brief General Purpose I/O
		401	*/
		402
		403	typedef struct
		404	{
		405	__IO uint32_t CRL;
		406	__IO uint32_t CRH;
		407	__IO uint32_t IDR;
		408	__IO uint32_t ODR;
		409	__IO uint32_t BSRR;
		410	__IO uint32_t BRR;
		411	__IO uint32_t LCKR;
		412	} GPIO_TypeDef;
		413
		414	/**
		415	* @brief Alternate Function I/O
		416	*/
		417
		418	typedef struct
		419	{
		420	__IO uint32_t EVCR;
		421	__IO uint32_t MAPR;
		422	__IO uint32_t EXTICR[4];
		423	uint32_t RESERVED0;
		424	__IO uint32_t MAPR2;
		425	} AFIO_TypeDef;
		426	/**
		427	* @brief Inter Integrated Circuit Interface
		428	*/
		429
		430	typedef struct
		431	{
		432	__IO uint32_t CR1;
		433	__IO uint32_t CR2;
		434	__IO uint32_t OAR1;
		435	__IO uint32_t OAR2;
		436	__IO uint32_t DR;
		437	__IO uint32_t SR1;
		438	__IO uint32_t SR2;
		439	__IO uint32_t CCR;
		440	__IO uint32_t TRISE;
		441	} I2C_TypeDef;
		442
		443	/**
		444	* @brief Independent WATCHDOG
		445	*/
		446
		447	typedef struct
		448	{
		449	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		450	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		451	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		452	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		453	} IWDG_TypeDef;
		454
		455	/**
		456	* @brief Power Control
		457	*/
		458
		459	typedef struct
		460	{
		461	__IO uint32_t CR;
		462	__IO uint32_t CSR;
		463	} PWR_TypeDef;
		464
		465	/**
		466	* @brief Reset and Clock Control
		467	*/
		468
		469	typedef struct
		470	{
		471	__IO uint32_t CR;
		472	__IO uint32_t CFGR;
		473	__IO uint32_t CIR;
		474	__IO uint32_t APB2RSTR;
		475	__IO uint32_t APB1RSTR;
		476	__IO uint32_t AHBENR;
		477	__IO uint32_t APB2ENR;
		478	__IO uint32_t APB1ENR;
		479	__IO uint32_t BDCR;
		480	__IO uint32_t CSR;
		481
		482
		483	uint32_t RESERVED0;
		484	__IO uint32_t CFGR2;
		485	} RCC_TypeDef;
		486
		487	/**
		488	* @brief Real-Time Clock
		489	*/
		490
		491	typedef struct
		492	{
		493	__IO uint32_t CRH;
		494	__IO uint32_t CRL;
		495	__IO uint32_t PRLH;
		496	__IO uint32_t PRLL;
		497	__IO uint32_t DIVH;
		498	__IO uint32_t DIVL;
		499	__IO uint32_t CNTH;
		500	__IO uint32_t CNTL;
		501	__IO uint32_t ALRH;
		502	__IO uint32_t ALRL;
		503	} RTC_TypeDef;
		504
		505	/**
		506	* @brief SD host Interface
		507	*/
		508
		509	typedef struct
		510	{
		511	__IO uint32_t POWER;
		512	__IO uint32_t CLKCR;
		513	__IO uint32_t ARG;
		514	__IO uint32_t CMD;
		515	__I uint32_t RESPCMD;
		516	__I uint32_t RESP1;
		517	__I uint32_t RESP2;
		518	__I uint32_t RESP3;
		519	__I uint32_t RESP4;
		520	__IO uint32_t DTIMER;
		521	__IO uint32_t DLEN;
		522	__IO uint32_t DCTRL;
		523	__I uint32_t DCOUNT;
		524	__I uint32_t STA;
		525	__IO uint32_t ICR;
		526	__IO uint32_t MASK;
		527	uint32_t RESERVED0[2];
		528	__I uint32_t FIFOCNT;
		529	uint32_t RESERVED1[13];
		530	__IO uint32_t FIFO;
		531	} SDIO_TypeDef;
		532
		533	/**
		534	* @brief Serial Peripheral Interface
		535	*/
		536
		537	typedef struct
		538	{
		539	__IO uint32_t CR1;
		540	__IO uint32_t CR2;
		541	__IO uint32_t SR;
		542	__IO uint32_t DR;
		543	__IO uint32_t CRCPR;
		544	__IO uint32_t RXCRCR;
		545	__IO uint32_t TXCRCR;
		546	} SPI_TypeDef;
		547
		548	/**
		549	* @brief TIM Timers
		550	*/
		551	typedef struct
		552	{
		553	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		554	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		555	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		556	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		557	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		558	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		559	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		560	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		561	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		562	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		563	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		564	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		565	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
		566	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		567	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		568	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		569	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		570	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
		571	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		572	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
		573	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		574	}TIM_TypeDef;
		575
		576
		577	/**
		578	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		579	*/
		580
		581	typedef struct
		582	{
		583	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		584	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		585	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		586	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		587	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		588	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		589	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		590	} USART_TypeDef;
		591
		592
		593
		594	/**
		595	* @brief Window WATCHDOG
		596	*/
		597
		598	typedef struct
		599	{
		600	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		601	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		602	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		603	} WWDG_TypeDef;
		604
		605	/**
		606	* @}
		607	*/
		608
		609	/** @addtogroup Peripheral_memory_map
		610	* @{
		611	*/
		612
		613
		614	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
		615	#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /!< FLASH END address of bank1 /
		616	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
		617	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
		618
		619	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
		620	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
		621
		622	#define FSMC_BASE ((uint32_t)0x60000000) /!< FSMC base address /
		623	#define FSMC_R_BASE ((uint32_t)0xA0000000) /!< FSMC registers base address /
		624
		625	/!< Peripheral memory map /
		626	#define APB1PERIPH_BASE PERIPH_BASE
		627	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
		628	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
		629
		630	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
		631	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
		632	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
		633	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
		634	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
		635	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
		636	#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
		637	#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
		638	#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
		639	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
		640	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
		641	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
		642	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
		643	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
		644	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
		645	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
		646	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
		647	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
		648	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
		649	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
		650	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
		651	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
		652	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
		653	#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
		654	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
		655	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
		656	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
		657	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
		658	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
		659	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
		660	#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
		661	#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
		662	#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
		663	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
		664	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
		665	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
		666	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
		667	#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
		668	#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
		669	#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
		670
		671	#define SDIO_BASE (PERIPH_BASE + 0x18000)
		672
		673	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
		674	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
		675	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
		676	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
		677	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
		678	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
		679	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
		680	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
		681	#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
		682	#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
		683	#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
		684	#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
		685	#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
		686	#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
		687	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
		688	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
		689
		690	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
		691	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
		692
		693
		694	#define FSMC_BANK1 (FSMC_BASE) /!< FSMC Bank1 base address /
		695	#define FSMC_BANK1_1 (FSMC_BANK1) /!< FSMC Bank1_1 base address /
		696	#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /!< FSMC Bank1_2 base address /
		697	#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /!< FSMC Bank1_3 base address /
		698	#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /!< FSMC Bank1_4 base address /
		699
		700
		701	#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /!< FSMC Bank1 registers base address /
		702	#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /!< FSMC Bank1E registers base address /
		703
		704	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
		705
		706
		707
		708	/**
		709	* @}
		710	*/
		711
		712	/** @addtogroup Peripheral_declaration
		713	* @{
		714	*/
		715
		716	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
		717	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
		718	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
		719	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
		720	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
		721	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
		722	#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
		723	#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
		724	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
		725	#define RTC ((RTC_TypeDef *) RTC_BASE)
		726	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
		727	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
		728	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
		729	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
		730	#define USART2 ((USART_TypeDef *) USART2_BASE)
		731	#define USART3 ((USART_TypeDef *) USART3_BASE)
		732	#define UART4 ((USART_TypeDef *) UART4_BASE)
		733	#define UART5 ((USART_TypeDef *) UART5_BASE)
		734	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
		735	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
		736	#define BKP ((BKP_TypeDef *) BKP_BASE)
		737	#define PWR ((PWR_TypeDef *) PWR_BASE)
		738	#define DAC ((DAC_TypeDef *) DAC_BASE)
		739	#define CEC ((CEC_TypeDef *) CEC_BASE)
		740	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
		741	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
		742	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
		743	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
		744	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
		745	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
		746	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
		747	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
		748	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
		749	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
		750	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
		751	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
		752	#define USART1 ((USART_TypeDef *) USART1_BASE)
		753	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
		754	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
		755	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
		756	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
		757	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
		758	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
		759	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
		760	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
		761	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
		762	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
		763	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
		764	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
		765	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
		766	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
		767	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
		768	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
		769	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
		770	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
		771	#define RCC ((RCC_TypeDef *) RCC_BASE)
		772	#define CRC ((CRC_TypeDef *) CRC_BASE)
		773	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
		774	#define OB ((OB_TypeDef *) OB_BASE)
		775	#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
		776	#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
		777	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
		778
		779
		780	/**
		781	* @}
		782	*/
		783
		784	/** @addtogroup Exported_constants
		785	* @{
		786	*/
		787
		788	/** @addtogroup Peripheral_Registers_Bits_Definition
		789	* @{
		790	*/
		791
		792	/******************************************************************************/
		793	/* Peripheral Registers_Bits_Definition */
		794	/******************************************************************************/
		795
		796	/******************************************************************************/
		797	/* */
		798	/* CRC calculation unit (CRC) */
		799	/* */
		800	/******************************************************************************/
		801
		802	/***************** Bit definition for CRC_DR register *******************/
		803	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
		804
		805	/***************** Bit definition for CRC_IDR register ******************/
		806	#define CRC_IDR_IDR ((uint32_t)0xFF) /!< General-purpose 8-bit data register bits /
		807
		808	/****************** Bit definition for CRC_CR register ******************/
		809	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET bit /
		810
		811	/******************************************************************************/
		812	/* */
		813	/* Power Control */
		814	/* */
		815	/******************************************************************************/
		816
		817	/****************** Bit definition for PWR_CR register ******************/
		818	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-Power Deepsleep /
		819	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
		820	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
		821	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
		822	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
		823
		824	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
		825	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
		826	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
		827	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
		828
		829	/!< PVD level configuration /
		830	#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /!< PVD level 2.2V /
		831	#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /!< PVD level 2.3V /
		832	#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /!< PVD level 2.4V /
		833	#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /!< PVD level 2.5V /
		834	#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /!< PVD level 2.6V /
		835	#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /!< PVD level 2.7V /
		836	#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /!< PVD level 2.8V /
		837	#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /!< PVD level 2.9V /
		838
		839	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
		840
		841
		842	/***************** Bit definition for PWR_CSR register ******************/
		843	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
		844	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
		845	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
		846	#define PWR_CSR_EWUP ((uint32_t)0x00000100) /!< Enable WKUP pin /
		847
		848	/******************************************************************************/
		849	/* */
		850	/* Backup registers */
		851	/* */
		852	/******************************************************************************/
		853
		854	/***************** Bit definition for BKP_DR1 register ******************/
		855	#define BKP_DR1_D ((uint32_t)0x0000FFFF) /!< Backup data /
		856
		857	/***************** Bit definition for BKP_DR2 register ******************/
		858	#define BKP_DR2_D ((uint32_t)0x0000FFFF) /!< Backup data /
		859
		860	/***************** Bit definition for BKP_DR3 register ******************/
		861	#define BKP_DR3_D ((uint32_t)0x0000FFFF) /!< Backup data /
		862
		863	/***************** Bit definition for BKP_DR4 register ******************/
		864	#define BKP_DR4_D ((uint32_t)0x0000FFFF) /!< Backup data /
		865
		866	/***************** Bit definition for BKP_DR5 register ******************/
		867	#define BKP_DR5_D ((uint32_t)0x0000FFFF) /!< Backup data /
		868
		869	/***************** Bit definition for BKP_DR6 register ******************/
		870	#define BKP_DR6_D ((uint32_t)0x0000FFFF) /!< Backup data /
		871
		872	/***************** Bit definition for BKP_DR7 register ******************/
		873	#define BKP_DR7_D ((uint32_t)0x0000FFFF) /!< Backup data /
		874
		875	/***************** Bit definition for BKP_DR8 register ******************/
		876	#define BKP_DR8_D ((uint32_t)0x0000FFFF) /!< Backup data /
		877
		878	/***************** Bit definition for BKP_DR9 register ******************/
		879	#define BKP_DR9_D ((uint32_t)0x0000FFFF) /!< Backup data /
		880
		881	/***************** Bit definition for BKP_DR10 register *****************/
		882	#define BKP_DR10_D ((uint32_t)0x0000FFFF) /!< Backup data /
		883
		884	/***************** Bit definition for BKP_DR11 register *****************/
		885	#define BKP_DR11_D ((uint32_t)0x0000FFFF) /!< Backup data /
		886
		887	/***************** Bit definition for BKP_DR12 register *****************/
		888	#define BKP_DR12_D ((uint32_t)0x0000FFFF) /!< Backup data /
		889
		890	/***************** Bit definition for BKP_DR13 register *****************/
		891	#define BKP_DR13_D ((uint32_t)0x0000FFFF) /!< Backup data /
		892
		893	/***************** Bit definition for BKP_DR14 register *****************/
		894	#define BKP_DR14_D ((uint32_t)0x0000FFFF) /!< Backup data /
		895
		896	/***************** Bit definition for BKP_DR15 register *****************/
		897	#define BKP_DR15_D ((uint32_t)0x0000FFFF) /!< Backup data /
		898
		899	/***************** Bit definition for BKP_DR16 register *****************/
		900	#define BKP_DR16_D ((uint32_t)0x0000FFFF) /!< Backup data /
		901
		902	/***************** Bit definition for BKP_DR17 register *****************/
		903	#define BKP_DR17_D ((uint32_t)0x0000FFFF) /!< Backup data /
		904
		905	/**************** Bit definition for BKP_DR18 register ******************/
		906	#define BKP_DR18_D ((uint32_t)0x0000FFFF) /!< Backup data /
		907
		908	/***************** Bit definition for BKP_DR19 register *****************/
		909	#define BKP_DR19_D ((uint32_t)0x0000FFFF) /!< Backup data /
		910
		911	/***************** Bit definition for BKP_DR20 register *****************/
		912	#define BKP_DR20_D ((uint32_t)0x0000FFFF) /!< Backup data /
		913
		914	/***************** Bit definition for BKP_DR21 register *****************/
		915	#define BKP_DR21_D ((uint32_t)0x0000FFFF) /!< Backup data /
		916
		917	/***************** Bit definition for BKP_DR22 register *****************/
		918	#define BKP_DR22_D ((uint32_t)0x0000FFFF) /!< Backup data /
		919
		920	/***************** Bit definition for BKP_DR23 register *****************/
		921	#define BKP_DR23_D ((uint32_t)0x0000FFFF) /!< Backup data /
		922
		923	/***************** Bit definition for BKP_DR24 register *****************/
		924	#define BKP_DR24_D ((uint32_t)0x0000FFFF) /!< Backup data /
		925
		926	/***************** Bit definition for BKP_DR25 register *****************/
		927	#define BKP_DR25_D ((uint32_t)0x0000FFFF) /!< Backup data /
		928
		929	/***************** Bit definition for BKP_DR26 register *****************/
		930	#define BKP_DR26_D ((uint32_t)0x0000FFFF) /!< Backup data /
		931
		932	/***************** Bit definition for BKP_DR27 register *****************/
		933	#define BKP_DR27_D ((uint32_t)0x0000FFFF) /!< Backup data /
		934
		935	/***************** Bit definition for BKP_DR28 register *****************/
		936	#define BKP_DR28_D ((uint32_t)0x0000FFFF) /!< Backup data /
		937
		938	/***************** Bit definition for BKP_DR29 register *****************/
		939	#define BKP_DR29_D ((uint32_t)0x0000FFFF) /!< Backup data /
		940
		941	/***************** Bit definition for BKP_DR30 register *****************/
		942	#define BKP_DR30_D ((uint32_t)0x0000FFFF) /!< Backup data /
		943
		944	/***************** Bit definition for BKP_DR31 register *****************/
		945	#define BKP_DR31_D ((uint32_t)0x0000FFFF) /!< Backup data /
		946
		947	/***************** Bit definition for BKP_DR32 register *****************/
		948	#define BKP_DR32_D ((uint32_t)0x0000FFFF) /!< Backup data /
		949
		950	/***************** Bit definition for BKP_DR33 register *****************/
		951	#define BKP_DR33_D ((uint32_t)0x0000FFFF) /!< Backup data /
		952
		953	/***************** Bit definition for BKP_DR34 register *****************/
		954	#define BKP_DR34_D ((uint32_t)0x0000FFFF) /!< Backup data /
		955
		956	/***************** Bit definition for BKP_DR35 register *****************/
		957	#define BKP_DR35_D ((uint32_t)0x0000FFFF) /!< Backup data /
		958
		959	/***************** Bit definition for BKP_DR36 register *****************/
		960	#define BKP_DR36_D ((uint32_t)0x0000FFFF) /!< Backup data /
		961
		962	/***************** Bit definition for BKP_DR37 register *****************/
		963	#define BKP_DR37_D ((uint32_t)0x0000FFFF) /!< Backup data /
		964
		965	/***************** Bit definition for BKP_DR38 register *****************/
		966	#define BKP_DR38_D ((uint32_t)0x0000FFFF) /!< Backup data /
		967
		968	/***************** Bit definition for BKP_DR39 register *****************/
		969	#define BKP_DR39_D ((uint32_t)0x0000FFFF) /!< Backup data /
		970
		971	/***************** Bit definition for BKP_DR40 register *****************/
		972	#define BKP_DR40_D ((uint32_t)0x0000FFFF) /!< Backup data /
		973
		974	/***************** Bit definition for BKP_DR41 register *****************/
		975	#define BKP_DR41_D ((uint32_t)0x0000FFFF) /!< Backup data /
		976
		977	/***************** Bit definition for BKP_DR42 register *****************/
		978	#define BKP_DR42_D ((uint32_t)0x0000FFFF) /!< Backup data /
		979
		980	#define RTC_BKP_NUMBER 42
		981
		982	/**************** Bit definition for BKP_RTCCR register *****************/
		983	#define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /!< Calibration value /
		984	#define BKP_RTCCR_CCO ((uint32_t)0x00000080) /!< Calibration Clock Output /
		985	#define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /!< Alarm or Second Output Enable /
		986	#define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /!< Alarm or Second Output Selection /
		987
		988	/****************** Bit definition for BKP_CR register ******************/
		989	#define BKP_CR_TPE ((uint32_t)0x00000001) /!< TAMPER pin enable /
		990	#define BKP_CR_TPAL ((uint32_t)0x00000002) /!< TAMPER pin active level /
		991
		992	/***************** Bit definition for BKP_CSR register ******************/
		993	#define BKP_CSR_CTE ((uint32_t)0x00000001) /!< Clear Tamper event /
		994	#define BKP_CSR_CTI ((uint32_t)0x00000002) /!< Clear Tamper Interrupt /
		995	#define BKP_CSR_TPIE ((uint32_t)0x00000004) /!< TAMPER Pin interrupt enable /
		996	#define BKP_CSR_TEF ((uint32_t)0x00000100) /!< Tamper Event Flag /
		997	#define BKP_CSR_TIF ((uint32_t)0x00000200) /!< Tamper Interrupt Flag /
		998
		999	/******************************************************************************/
		1000	/* */
		1001	/* Reset and Clock Control */
		1002	/* */
		1003	/******************************************************************************/
		1004
		1005	/****************** Bit definition for RCC_CR register ******************/
		1006	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
		1007	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
		1008	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
		1009	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
		1010	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
		1011	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
		1012	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
		1013	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
		1014	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
		1015	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
		1016
		1017
		1018	/***************** Bit definition for RCC_CFGR register *****************/
		1019	/!< SW configuration /
		1020	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
		1021	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1022	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1023
		1024	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
		1025	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
		1026	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
		1027
		1028	/!< SWS configuration /
		1029	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
		1030	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1031	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1032
		1033	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
		1034	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
		1035	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
		1036
		1037	/!< HPRE configuration /
		1038	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
		1039	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1040	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1041	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
		1042	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
		1043
		1044	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
		1045	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
		1046	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
		1047	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
		1048	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
		1049	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
		1050	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
		1051	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
		1052	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
		1053
		1054	/!< PPRE1 configuration /
		1055	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
		1056	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1057	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1058	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
		1059
		1060	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		1061	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
		1062	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
		1063	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
		1064	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
		1065
		1066	/!< PPRE2 configuration /
		1067	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
		1068	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
		1069	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
		1070	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
		1071
		1072	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		1073	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
		1074	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
		1075	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
		1076	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
		1077
		1078	/!< ADCPPRE configuration /
		1079	#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /!< ADCPRE[1:0] bits (ADC prescaler) /
		1080	#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1081	#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1082
		1083	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
		1084	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
		1085	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
		1086	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
		1087
		1088	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
		1089
		1090	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
		1091
		1092	/!< PLLMUL configuration /
		1093	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
		1094	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1095	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1096	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
		1097	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
		1098
		1099	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
		1100	#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
		1101
		1102	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
		1103	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
		1104	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
		1105	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
		1106	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
		1107	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
		1108	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
		1109	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
		1110	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
		1111	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
		1112	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
		1113	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
		1114	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
		1115	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
		1116	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
		1117
		1118	/!< MCO configuration /
		1119	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
		1120	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1121	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1122	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
		1123
		1124	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1125	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
		1126	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
		1127	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
		1128	#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
		1129
		1130	/!<*************** Bit definition for RCC_CIR register ******************/
		1131	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
		1132	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
		1133	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
		1134	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
		1135	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
		1136	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
		1137	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
		1138	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
		1139	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
		1140	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
		1141	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
		1142	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
		1143	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
		1144	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
		1145	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
		1146	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
		1147	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
		1148
		1149
		1150	/*************** Bit definition for RCC_APB2RSTR register ***************/
		1151	#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /!< Alternate Function I/O reset /
		1152	#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /!< I/O port A reset /
		1153	#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /!< I/O port B reset /
		1154	#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /!< I/O port C reset /
		1155	#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /!< I/O port D reset /
		1156	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC 1 interface reset /
		1157
		1158
		1159	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 Timer reset /
		1160	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI 1 reset /
		1161	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
		1162
		1163	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 Timer reset /
		1164	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 Timer reset /
		1165	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 Timer reset /
		1166
		1167	#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /!< I/O port E reset /
		1168
		1169
		1170	#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /!< I/O port F reset /
		1171	#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /!< I/O port G reset /
		1172
		1173
		1174	/*************** Bit definition for RCC_APB1RSTR register ***************/
		1175	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
		1176	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
		1177	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
		1178	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
		1179	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
		1180
		1181
		1182	#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /!< Backup interface reset /
		1183	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
		1184
		1185	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
		1186	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
		1187	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
		1188	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
		1189
		1190
		1191
		1192	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
		1193	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
		1194	#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /!< CEC interface reset /
		1195
		1196	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /!< Timer 5 reset /
		1197	#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /!< TIM12 Timer reset /
		1198	#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /!< TIM13 Timer reset /
		1199	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< TIM14 Timer reset /
		1200	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI 3 reset /
		1201	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /!< UART 4 reset /
		1202	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /!< UART 5 reset /
		1203
		1204
		1205	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC interface reset /
		1206
		1207	/**************** Bit definition for RCC_AHBENR register ****************/
		1208	#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /!< DMA1 clock enable /
		1209	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
		1210	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
		1211	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
		1212
		1213	#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /!< DMA2 clock enable /
		1214
		1215	#define RCC_AHBENR_FSMCEN ((uint32_t)0x00000100) /!< FSMC clock enable /
		1216
		1217
		1218	/**************** Bit definition for RCC_APB2ENR register ***************/
		1219	#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /!< Alternate Function I/O clock enable /
		1220	#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /!< I/O port A clock enable /
		1221	#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /!< I/O port B clock enable /
		1222	#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /!< I/O port C clock enable /
		1223	#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /!< I/O port D clock enable /
		1224	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC 1 interface clock enable /
		1225
		1226
		1227	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 Timer clock enable /
		1228	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI 1 clock enable /
		1229	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
		1230
		1231	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 Timer clock enable /
		1232	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 Timer clock enable /
		1233	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 Timer clock enable /
		1234
		1235	#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /!< I/O port E clock enable /
		1236
		1237
		1238	#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /!< I/O port F clock enable /
		1239	#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /!< I/O port G clock enable /
		1240
		1241
		1242	/*************** Bit definition for RCC_APB1ENR register ****************/
		1243	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
		1244	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
		1245	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
		1246	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
		1247	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
		1248
		1249
		1250	#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /!< Backup interface clock enable /
		1251	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
		1252
		1253	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
		1254	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
		1255	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
		1256	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
		1257
		1258
		1259
		1260	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
		1261	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
		1262	#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /!< CEC interface clock enable /
		1263
		1264	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /!< Timer 5 clock enable /
		1265	#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /!< TIM12 Timer clock enable /
		1266	#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /!< TIM13 Timer clock enable /
		1267	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< TIM14 Timer clock enable /
		1268	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI 3 clock enable /
		1269	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /!< UART 4 clock enable /
		1270	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /!< UART 5 clock enable /
		1271
		1272
		1273	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC interface clock enable /
		1274
		1275	/***************** Bit definition for RCC_BDCR register *****************/
		1276	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
		1277	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
		1278	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
		1279
		1280	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
		1281	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1282	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1283
		1284	/!< RTC congiguration /
		1285	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1286	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
		1287	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
		1288	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
		1289
		1290	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
		1291	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
		1292
		1293	/***************** Bit definition for RCC_CSR register ******************/
		1294	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
		1295	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
		1296	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
		1297	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
		1298	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
		1299	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
		1300	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
		1301	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
		1302	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
		1303
		1304
		1305	/***************** Bit definition for RCC_CFGR2 register ****************/
		1306	/!< PREDIV1 configuration /
		1307	#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /!< PREDIV1[3:0] bits /
		1308	#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1309	#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1310	#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		1311	#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		1312
		1313	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
		1314	#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /!< PREDIV1 input clock divided by 2 /
		1315	#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /!< PREDIV1 input clock divided by 3 /
		1316	#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /!< PREDIV1 input clock divided by 4 /
		1317	#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /!< PREDIV1 input clock divided by 5 /
		1318	#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /!< PREDIV1 input clock divided by 6 /
		1319	#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /!< PREDIV1 input clock divided by 7 /
		1320	#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /!< PREDIV1 input clock divided by 8 /
		1321	#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /!< PREDIV1 input clock divided by 9 /
		1322	#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /!< PREDIV1 input clock divided by 10 /
		1323	#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /!< PREDIV1 input clock divided by 11 /
		1324	#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /!< PREDIV1 input clock divided by 12 /
		1325	#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /!< PREDIV1 input clock divided by 13 /
		1326	#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /!< PREDIV1 input clock divided by 14 /
		1327	#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /!< PREDIV1 input clock divided by 15 /
		1328	#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /!< PREDIV1 input clock divided by 16 /
		1329
		1330	/******************************************************************************/
		1331	/* */
		1332	/* General Purpose and Alternate Function I/O */
		1333	/* */
		1334	/******************************************************************************/
		1335
		1336	/***************** Bit definition for GPIO_CRL register *****************/
		1337	#define GPIO_CRL_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
		1338
		1339	#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
		1340	#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1341	#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1342
		1343	#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
		1344	#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1345	#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1346
		1347	#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
		1348	#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1349	#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1350
		1351	#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
		1352	#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /!< Bit 0 /
		1353	#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /!< Bit 1 /
		1354
		1355	#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
		1356	#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /!< Bit 0 /
		1357	#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /!< Bit 1 /
		1358
		1359	#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
		1360	#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /!< Bit 0 /
		1361	#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /!< Bit 1 /
		1362
		1363	#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
		1364	#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1365	#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1366
		1367	#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
		1368	#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /!< Bit 0 /
		1369	#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /!< Bit 1 /
		1370
		1371	#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
		1372
		1373	#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
		1374	#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1375	#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1376
		1377	#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
		1378	#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1379	#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1380
		1381	#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
		1382	#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1383	#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1384
		1385	#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
		1386	#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1387	#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1388
		1389	#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
		1390	#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1391	#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1392
		1393	#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
		1394	#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /!< Bit 0 /
		1395	#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /!< Bit 1 /
		1396
		1397	#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
		1398	#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /!< Bit 0 /
		1399	#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /!< Bit 1 /
		1400
		1401	#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
		1402	#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /!< Bit 0 /
		1403	#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /!< Bit 1 /
		1404
		1405	/***************** Bit definition for GPIO_CRH register *****************/
		1406	#define GPIO_CRH_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
		1407
		1408	#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
		1409	#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1410	#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1411
		1412	#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
		1413	#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1414	#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1415
		1416	#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
		1417	#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1418	#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1419
		1420	#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
		1421	#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /!< Bit 0 /
		1422	#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /!< Bit 1 /
		1423
		1424	#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
		1425	#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /!< Bit 0 /
		1426	#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /!< Bit 1 /
		1427
		1428	#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
		1429	#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /!< Bit 0 /
		1430	#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /!< Bit 1 /
		1431
		1432	#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
		1433	#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1434	#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1435
		1436	#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
		1437	#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /!< Bit 0 /
		1438	#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /!< Bit 1 /
		1439
		1440	#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
		1441
		1442	#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
		1443	#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /!< Bit 0 /
		1444	#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /!< Bit 1 /
		1445
		1446	#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
		1447	#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1448	#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1449
		1450	#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
		1451	#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1452	#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1453
		1454	#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
		1455	#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /!< Bit 0 /
		1456	#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /!< Bit 1 /
		1457
		1458	#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
		1459	#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /!< Bit 0 /
		1460	#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /!< Bit 1 /
		1461
		1462	#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
		1463	#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /!< Bit 0 /
		1464	#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /!< Bit 1 /
		1465
		1466	#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
		1467	#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /!< Bit 0 /
		1468	#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /!< Bit 1 /
		1469
		1470	#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
		1471	#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /!< Bit 0 /
		1472	#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /!< Bit 1 /
		1473
		1474	/!<*************** Bit definition for GPIO_IDR register *****************/
		1475	#define GPIO_IDR_IDR0 ((uint32_t)0x0001) /!< Port input data, bit 0 /
		1476	#define GPIO_IDR_IDR1 ((uint32_t)0x0002) /!< Port input data, bit 1 /
		1477	#define GPIO_IDR_IDR2 ((uint32_t)0x0004) /!< Port input data, bit 2 /
		1478	#define GPIO_IDR_IDR3 ((uint32_t)0x0008) /!< Port input data, bit 3 /
		1479	#define GPIO_IDR_IDR4 ((uint32_t)0x0010) /!< Port input data, bit 4 /
		1480	#define GPIO_IDR_IDR5 ((uint32_t)0x0020) /!< Port input data, bit 5 /
		1481	#define GPIO_IDR_IDR6 ((uint32_t)0x0040) /!< Port input data, bit 6 /
		1482	#define GPIO_IDR_IDR7 ((uint32_t)0x0080) /!< Port input data, bit 7 /
		1483	#define GPIO_IDR_IDR8 ((uint32_t)0x0100) /!< Port input data, bit 8 /
		1484	#define GPIO_IDR_IDR9 ((uint32_t)0x0200) /!< Port input data, bit 9 /
		1485	#define GPIO_IDR_IDR10 ((uint32_t)0x0400) /!< Port input data, bit 10 /
		1486	#define GPIO_IDR_IDR11 ((uint32_t)0x0800) /!< Port input data, bit 11 /
		1487	#define GPIO_IDR_IDR12 ((uint32_t)0x1000) /!< Port input data, bit 12 /
		1488	#define GPIO_IDR_IDR13 ((uint32_t)0x2000) /!< Port input data, bit 13 /
		1489	#define GPIO_IDR_IDR14 ((uint32_t)0x4000) /!< Port input data, bit 14 /
		1490	#define GPIO_IDR_IDR15 ((uint32_t)0x8000) /!< Port input data, bit 15 /
		1491
		1492	/***************** Bit definition for GPIO_ODR register *****************/
		1493	#define GPIO_ODR_ODR0 ((uint32_t)0x0001) /!< Port output data, bit 0 /
		1494	#define GPIO_ODR_ODR1 ((uint32_t)0x0002) /!< Port output data, bit 1 /
		1495	#define GPIO_ODR_ODR2 ((uint32_t)0x0004) /!< Port output data, bit 2 /
		1496	#define GPIO_ODR_ODR3 ((uint32_t)0x0008) /!< Port output data, bit 3 /
		1497	#define GPIO_ODR_ODR4 ((uint32_t)0x0010) /!< Port output data, bit 4 /
		1498	#define GPIO_ODR_ODR5 ((uint32_t)0x0020) /!< Port output data, bit 5 /
		1499	#define GPIO_ODR_ODR6 ((uint32_t)0x0040) /!< Port output data, bit 6 /
		1500	#define GPIO_ODR_ODR7 ((uint32_t)0x0080) /!< Port output data, bit 7 /
		1501	#define GPIO_ODR_ODR8 ((uint32_t)0x0100) /!< Port output data, bit 8 /
		1502	#define GPIO_ODR_ODR9 ((uint32_t)0x0200) /!< Port output data, bit 9 /
		1503	#define GPIO_ODR_ODR10 ((uint32_t)0x0400) /!< Port output data, bit 10 /
		1504	#define GPIO_ODR_ODR11 ((uint32_t)0x0800) /!< Port output data, bit 11 /
		1505	#define GPIO_ODR_ODR12 ((uint32_t)0x1000) /!< Port output data, bit 12 /
		1506	#define GPIO_ODR_ODR13 ((uint32_t)0x2000) /!< Port output data, bit 13 /
		1507	#define GPIO_ODR_ODR14 ((uint32_t)0x4000) /!< Port output data, bit 14 /
		1508	#define GPIO_ODR_ODR15 ((uint32_t)0x8000) /!< Port output data, bit 15 /
		1509
		1510	/**************** Bit definition for GPIO_BSRR register *****************/
		1511	#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /!< Port x Set bit 0 /
		1512	#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /!< Port x Set bit 1 /
		1513	#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /!< Port x Set bit 2 /
		1514	#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /!< Port x Set bit 3 /
		1515	#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /!< Port x Set bit 4 /
		1516	#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /!< Port x Set bit 5 /
		1517	#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /!< Port x Set bit 6 /
		1518	#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /!< Port x Set bit 7 /
		1519	#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /!< Port x Set bit 8 /
		1520	#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /!< Port x Set bit 9 /
		1521	#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /!< Port x Set bit 10 /
		1522	#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /!< Port x Set bit 11 /
		1523	#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /!< Port x Set bit 12 /
		1524	#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /!< Port x Set bit 13 /
		1525	#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /!< Port x Set bit 14 /
		1526	#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /!< Port x Set bit 15 /
		1527
		1528	#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /!< Port x Reset bit 0 /
		1529	#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /!< Port x Reset bit 1 /
		1530	#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /!< Port x Reset bit 2 /
		1531	#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /!< Port x Reset bit 3 /
		1532	#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /!< Port x Reset bit 4 /
		1533	#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /!< Port x Reset bit 5 /
		1534	#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /!< Port x Reset bit 6 /
		1535	#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /!< Port x Reset bit 7 /
		1536	#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /!< Port x Reset bit 8 /
		1537	#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /!< Port x Reset bit 9 /
		1538	#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /!< Port x Reset bit 10 /
		1539	#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /!< Port x Reset bit 11 /
		1540	#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /!< Port x Reset bit 12 /
		1541	#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /!< Port x Reset bit 13 /
		1542	#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /!< Port x Reset bit 14 /
		1543	#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /!< Port x Reset bit 15 /
		1544
		1545	/***************** Bit definition for GPIO_BRR register *****************/
		1546	#define GPIO_BRR_BR0 ((uint32_t)0x0001) /!< Port x Reset bit 0 /
		1547	#define GPIO_BRR_BR1 ((uint32_t)0x0002) /!< Port x Reset bit 1 /
		1548	#define GPIO_BRR_BR2 ((uint32_t)0x0004) /!< Port x Reset bit 2 /
		1549	#define GPIO_BRR_BR3 ((uint32_t)0x0008) /!< Port x Reset bit 3 /
		1550	#define GPIO_BRR_BR4 ((uint32_t)0x0010) /!< Port x Reset bit 4 /
		1551	#define GPIO_BRR_BR5 ((uint32_t)0x0020) /!< Port x Reset bit 5 /
		1552	#define GPIO_BRR_BR6 ((uint32_t)0x0040) /!< Port x Reset bit 6 /
		1553	#define GPIO_BRR_BR7 ((uint32_t)0x0080) /!< Port x Reset bit 7 /
		1554	#define GPIO_BRR_BR8 ((uint32_t)0x0100) /!< Port x Reset bit 8 /
		1555	#define GPIO_BRR_BR9 ((uint32_t)0x0200) /!< Port x Reset bit 9 /
		1556	#define GPIO_BRR_BR10 ((uint32_t)0x0400) /!< Port x Reset bit 10 /
		1557	#define GPIO_BRR_BR11 ((uint32_t)0x0800) /!< Port x Reset bit 11 /
		1558	#define GPIO_BRR_BR12 ((uint32_t)0x1000) /!< Port x Reset bit 12 /
		1559	#define GPIO_BRR_BR13 ((uint32_t)0x2000) /!< Port x Reset bit 13 /
		1560	#define GPIO_BRR_BR14 ((uint32_t)0x4000) /!< Port x Reset bit 14 /
		1561	#define GPIO_BRR_BR15 ((uint32_t)0x8000) /!< Port x Reset bit 15 /
		1562
		1563	/**************** Bit definition for GPIO_LCKR register *****************/
		1564	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /!< Port x Lock bit 0 /
		1565	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /!< Port x Lock bit 1 /
		1566	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /!< Port x Lock bit 2 /
		1567	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /!< Port x Lock bit 3 /
		1568	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /!< Port x Lock bit 4 /
		1569	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /!< Port x Lock bit 5 /
		1570	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /!< Port x Lock bit 6 /
		1571	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /!< Port x Lock bit 7 /
		1572	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /!< Port x Lock bit 8 /
		1573	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /!< Port x Lock bit 9 /
		1574	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /!< Port x Lock bit 10 /
		1575	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /!< Port x Lock bit 11 /
		1576	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /!< Port x Lock bit 12 /
		1577	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /!< Port x Lock bit 13 /
		1578	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /!< Port x Lock bit 14 /
		1579	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /!< Port x Lock bit 15 /
		1580	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /!< Lock key /
		1581
		1582	/----------------------------------------------------------------------------/
		1583
		1584	/**************** Bit definition for AFIO_EVCR register *****************/
		1585	#define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /!< PIN[3:0] bits (Pin selection) /
		1586	#define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /!< Bit 0 /
		1587	#define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /!< Bit 1 /
		1588	#define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /!< Bit 2 /
		1589	#define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /!< Bit 3 /
		1590
		1591	/!< PIN configuration /
		1592	#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /!< Pin 0 selected /
		1593	#define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /!< Pin 1 selected /
		1594	#define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /!< Pin 2 selected /
		1595	#define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /!< Pin 3 selected /
		1596	#define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /!< Pin 4 selected /
		1597	#define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /!< Pin 5 selected /
		1598	#define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /!< Pin 6 selected /
		1599	#define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /!< Pin 7 selected /
		1600	#define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /!< Pin 8 selected /
		1601	#define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /!< Pin 9 selected /
		1602	#define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /!< Pin 10 selected /
		1603	#define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /!< Pin 11 selected /
		1604	#define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /!< Pin 12 selected /
		1605	#define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /!< Pin 13 selected /
		1606	#define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /!< Pin 14 selected /
		1607	#define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /!< Pin 15 selected /
		1608
		1609	#define AFIO_EVCR_PORT ((uint32_t)0x00000070) /!< PORT[2:0] bits (Port selection) /
		1610	#define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1611	#define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1612	#define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /!< Bit 2 /
		1613
		1614	/!< PORT configuration /
		1615	#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /!< Port A selected /
		1616	#define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /!< Port B selected /
		1617	#define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /!< Port C selected /
		1618	#define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /!< Port D selected /
		1619	#define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /!< Port E selected /
		1620
		1621	#define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /!< Event Output Enable /
		1622
		1623	/**************** Bit definition for AFIO_MAPR register *****************/
		1624	#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /!< SPI1 remapping /
		1625	#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /!< I2C1 remapping /
		1626	#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /!< USART1 remapping /
		1627	#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /!< USART2 remapping /
		1628
		1629	#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /!< USART3_REMAP[1:0] bits (USART3 remapping) /
		1630	#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /!< Bit 0 /
		1631	#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /!< Bit 1 /
		1632
		1633	/* USART3_REMAP configuration */
		1634	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
		1635	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
		1636	#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
		1637
		1638	#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
		1639	#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /!< Bit 0 /
		1640	#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /!< Bit 1 /
		1641
		1642	/!< TIM1_REMAP configuration /
		1643	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
		1644	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
		1645	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
		1646
		1647	#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
		1648	#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		1649	#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		1650
		1651	/!< TIM2_REMAP configuration /
		1652	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
		1653	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
		1654	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
		1655	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
		1656
		1657	#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
		1658	#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /!< Bit 0 /
		1659	#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /!< Bit 1 /
		1660
		1661	/!< TIM3_REMAP configuration /
		1662	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
		1663	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
		1664	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
		1665
		1666	#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /!< TIM4_REMAP bit (TIM4 remapping) /
		1667
		1668
		1669	#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
		1670	#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /!< TIM5 Channel4 Internal Remap /
		1671
		1672	/!< SWJ_CFG configuration /
		1673	#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
		1674	#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /!< Bit 0 /
		1675	#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /!< Bit 1 /
		1676	#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /!< Bit 2 /
		1677
		1678	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
		1679	#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
		1680	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /!< JTAG-DP Disabled and SW-DP Enabled /
		1681	#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /!< JTAG-DP Disabled and SW-DP Disabled /
		1682
		1683
		1684	/*************** Bit definition for AFIO_EXTICR1 register ***************/
		1685	#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /!< EXTI 0 configuration /
		1686	#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /!< EXTI 1 configuration /
		1687	#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /!< EXTI 2 configuration /
		1688	#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /!< EXTI 3 configuration /
		1689
		1690	/!< EXTI0 configuration /
		1691	#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
		1692	#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!< PB[0] pin /
		1693	#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!< PC[0] pin /
		1694	#define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!< PD[0] pin /
		1695	#define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!< PE[0] pin /
		1696	#define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!< PF[0] pin /
		1697	#define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /!< PG[0] pin /
		1698
		1699	/!< EXTI1 configuration /
		1700	#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
		1701	#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!< PB[1] pin /
		1702	#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!< PC[1] pin /
		1703	#define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!< PD[1] pin /
		1704	#define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!< PE[1] pin /
		1705	#define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!< PF[1] pin /
		1706	#define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /!< PG[1] pin /
		1707
		1708	/!< EXTI2 configuration /
		1709	#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
		1710	#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!< PB[2] pin /
		1711	#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!< PC[2] pin /
		1712	#define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!< PD[2] pin /
		1713	#define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!< PE[2] pin /
		1714	#define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!< PF[2] pin /
		1715	#define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /!< PG[2] pin /
		1716
		1717	/!< EXTI3 configuration /
		1718	#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
		1719	#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!< PB[3] pin /
		1720	#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!< PC[3] pin /
		1721	#define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!< PD[3] pin /
		1722	#define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!< PE[3] pin /
		1723	#define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!< PF[3] pin /
		1724	#define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /!< PG[3] pin /
		1725
		1726	/*************** Bit definition for AFIO_EXTICR2 register ***************/
		1727	#define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /!< EXTI 4 configuration /
		1728	#define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /!< EXTI 5 configuration /
		1729	#define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /!< EXTI 6 configuration /
		1730	#define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /!< EXTI 7 configuration /
		1731
		1732	/!< EXTI4 configuration /
		1733	#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
		1734	#define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!< PB[4] pin /
		1735	#define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!< PC[4] pin /
		1736	#define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!< PD[4] pin /
		1737	#define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!< PE[4] pin /
		1738	#define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!< PF[4] pin /
		1739	#define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /!< PG[4] pin /
		1740
		1741	/* EXTI5 configuration */
		1742	#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
		1743	#define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!< PB[5] pin /
		1744	#define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!< PC[5] pin /
		1745	#define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!< PD[5] pin /
		1746	#define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!< PE[5] pin /
		1747	#define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!< PF[5] pin /
		1748	#define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /!< PG[5] pin /
		1749
		1750	/!< EXTI6 configuration /
		1751	#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
		1752	#define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!< PB[6] pin /
		1753	#define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!< PC[6] pin /
		1754	#define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!< PD[6] pin /
		1755	#define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!< PE[6] pin /
		1756	#define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!< PF[6] pin /
		1757	#define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /!< PG[6] pin /
		1758
		1759	/!< EXTI7 configuration /
		1760	#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
		1761	#define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!< PB[7] pin /
		1762	#define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!< PC[7] pin /
		1763	#define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!< PD[7] pin /
		1764	#define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!< PE[7] pin /
		1765	#define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!< PF[7] pin /
		1766	#define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /!< PG[7] pin /
		1767
		1768	/*************** Bit definition for AFIO_EXTICR3 register ***************/
		1769	#define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /!< EXTI 8 configuration /
		1770	#define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /!< EXTI 9 configuration /
		1771	#define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /!< EXTI 10 configuration /
		1772	#define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /!< EXTI 11 configuration /
		1773
		1774	/!< EXTI8 configuration /
		1775	#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
		1776	#define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!< PB[8] pin /
		1777	#define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!< PC[8] pin /
		1778	#define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!< PD[8] pin /
		1779	#define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!< PE[8] pin /
		1780	#define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!< PF[8] pin /
		1781	#define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /!< PG[8] pin /
		1782
		1783	/!< EXTI9 configuration /
		1784	#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
		1785	#define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!< PB[9] pin /
		1786	#define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!< PC[9] pin /
		1787	#define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!< PD[9] pin /
		1788	#define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!< PE[9] pin /
		1789	#define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!< PF[9] pin /
		1790	#define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /!< PG[9] pin /
		1791
		1792	/!< EXTI10 configuration /
		1793	#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
		1794	#define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!< PB[10] pin /
		1795	#define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!< PC[10] pin /
		1796	#define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!< PD[10] pin /
		1797	#define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!< PE[10] pin /
		1798	#define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!< PF[10] pin /
		1799	#define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /!< PG[10] pin /
		1800
		1801	/!< EXTI11 configuration /
		1802	#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
		1803	#define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!< PB[11] pin /
		1804	#define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!< PC[11] pin /
		1805	#define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!< PD[11] pin /
		1806	#define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!< PE[11] pin /
		1807	#define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!< PF[11] pin /
		1808	#define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /!< PG[11] pin /
		1809
		1810	/*************** Bit definition for AFIO_EXTICR4 register ***************/
		1811	#define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /!< EXTI 12 configuration /
		1812	#define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /!< EXTI 13 configuration /
		1813	#define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /!< EXTI 14 configuration /
		1814	#define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /!< EXTI 15 configuration /
		1815
		1816	/* EXTI12 configuration */
		1817	#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
		1818	#define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!< PB[12] pin /
		1819	#define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!< PC[12] pin /
		1820	#define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!< PD[12] pin /
		1821	#define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!< PE[12] pin /
		1822	#define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!< PF[12] pin /
		1823	#define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /!< PG[12] pin /
		1824
		1825	/* EXTI13 configuration */
		1826	#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
		1827	#define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!< PB[13] pin /
		1828	#define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!< PC[13] pin /
		1829	#define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!< PD[13] pin /
		1830	#define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!< PE[13] pin /
		1831	#define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!< PF[13] pin /
		1832	#define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /!< PG[13] pin /
		1833
		1834	/!< EXTI14 configuration /
		1835	#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
		1836	#define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!< PB[14] pin /
		1837	#define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!< PC[14] pin /
		1838	#define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!< PD[14] pin /
		1839	#define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!< PE[14] pin /
		1840	#define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!< PF[14] pin /
		1841	#define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /!< PG[14] pin /
		1842
		1843	/!< EXTI15 configuration /
		1844	#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
		1845	#define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!< PB[15] pin /
		1846	#define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!< PC[15] pin /
		1847	#define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!< PD[15] pin /
		1848	#define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!< PE[15] pin /
		1849	#define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!< PF[15] pin /
		1850	#define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /!< PG[15] pin /
		1851
		1852	/**************** Bit definition for AFIO_MAPR2 register ****************/
		1853	#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /!< TIM15 remapping /
		1854	#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /!< TIM16 remapping /
		1855	#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /!< TIM17 remapping /
		1856	#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /!< CEC remapping /
		1857	#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /!< TIM1_DMA remapping /
		1858
		1859	#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /!< TIM13 remapping /
		1860	#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /!< TIM14 remapping /
		1861	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /!< TIM6/TIM7 and DAC DMA remapping /
		1862	#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /!< TIM12 remapping /
		1863	#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /!< Miscellaneous remapping /
		1864
		1865	#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /!< FSMC NADV remapping /
		1866
		1867	/******************************************************************************/
		1868	/* */
		1869	/* SystemTick */
		1870	/* */
		1871	/******************************************************************************/
		1872
		1873	/*************** Bit definition for SysTick_CTRL register ***************/
		1874	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
		1875	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
		1876	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
		1877	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
		1878
		1879	/*************** Bit definition for SysTick_LOAD register ***************/
		1880	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
		1881
		1882	/*************** Bit definition for SysTick_VAL register ****************/
		1883	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
		1884
		1885	/*************** Bit definition for SysTick_CALIB register **************/
		1886	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
		1887	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
		1888	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
		1889
		1890	/******************************************************************************/
		1891	/* */
		1892	/* Nested Vectored Interrupt Controller */
		1893	/* */
		1894	/******************************************************************************/
		1895
		1896	/**************** Bit definition for NVIC_ISER register *****************/
		1897	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
		1898	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
		1899	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
		1900	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
		1901	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
		1902	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
		1903	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
		1904	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
		1905	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
		1906	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
		1907	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
		1908	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
		1909	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
		1910	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
		1911	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
		1912	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
		1913	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
		1914	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
		1915	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
		1916	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
		1917	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
		1918	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
		1919	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
		1920	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
		1921	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
		1922	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
		1923	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
		1924	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
		1925	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
		1926	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
		1927	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
		1928	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
		1929	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
		1930
		1931	/**************** Bit definition for NVIC_ICER register *****************/
		1932	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
		1933	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
		1934	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
		1935	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
		1936	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
		1937	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
		1938	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
		1939	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
		1940	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
		1941	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
		1942	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
		1943	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
		1944	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
		1945	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
		1946	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
		1947	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
		1948	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
		1949	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
		1950	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
		1951	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
		1952	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
		1953	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
		1954	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
		1955	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
		1956	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
		1957	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
		1958	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
		1959	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
		1960	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
		1961	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
		1962	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
		1963	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
		1964	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
		1965
		1966	/**************** Bit definition for NVIC_ISPR register *****************/
		1967	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
		1968	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
		1969	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
		1970	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
		1971	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
		1972	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
		1973	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
		1974	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
		1975	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
		1976	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
		1977	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
		1978	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
		1979	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
		1980	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
		1981	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
		1982	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
		1983	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
		1984	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
		1985	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
		1986	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
		1987	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
		1988	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
		1989	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
		1990	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
		1991	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
		1992	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
		1993	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
		1994	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
		1995	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
		1996	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
		1997	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
		1998	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
		1999	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
		2000
		2001	/**************** Bit definition for NVIC_ICPR register *****************/
		2002	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
		2003	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
		2004	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
		2005	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
		2006	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
		2007	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
		2008	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
		2009	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
		2010	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
		2011	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
		2012	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
		2013	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
		2014	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
		2015	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
		2016	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
		2017	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
		2018	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
		2019	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
		2020	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
		2021	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
		2022	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
		2023	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
		2024	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
		2025	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
		2026	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
		2027	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
		2028	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
		2029	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
		2030	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
		2031	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
		2032	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
		2033	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
		2034	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
		2035
		2036	/**************** Bit definition for NVIC_IABR register *****************/
		2037	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
		2038	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
		2039	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
		2040	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
		2041	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
		2042	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
		2043	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
		2044	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
		2045	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
		2046	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
		2047	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
		2048	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
		2049	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
		2050	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
		2051	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
		2052	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
		2053	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
		2054	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
		2055	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
		2056	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
		2057	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
		2058	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
		2059	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
		2060	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
		2061	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
		2062	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
		2063	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
		2064	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
		2065	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
		2066	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
		2067	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
		2068	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
		2069	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
		2070
		2071	/**************** Bit definition for NVIC_PRI0 register *****************/
		2072	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
		2073	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
		2074	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
		2075	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
		2076
		2077	/**************** Bit definition for NVIC_PRI1 register *****************/
		2078	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
		2079	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
		2080	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
		2081	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
		2082
		2083	/**************** Bit definition for NVIC_PRI2 register *****************/
		2084	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
		2085	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
		2086	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
		2087	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
		2088
		2089	/**************** Bit definition for NVIC_PRI3 register *****************/
		2090	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
		2091	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
		2092	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
		2093	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
		2094
		2095	/**************** Bit definition for NVIC_PRI4 register *****************/
		2096	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
		2097	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
		2098	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
		2099	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
		2100
		2101	/**************** Bit definition for NVIC_PRI5 register *****************/
		2102	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
		2103	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
		2104	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
		2105	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
		2106
		2107	/**************** Bit definition for NVIC_PRI6 register *****************/
		2108	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
		2109	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
		2110	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
		2111	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
		2112
		2113	/**************** Bit definition for NVIC_PRI7 register *****************/
		2114	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
		2115	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
		2116	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
		2117	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
		2118
		2119	/**************** Bit definition for SCB_CPUID register *****************/
		2120	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
		2121	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
		2122	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
		2123	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
		2124	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
		2125
		2126	/***************** Bit definition for SCB_ICSR register *****************/
		2127	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
		2128	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
		2129	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
		2130	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
		2131	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
		2132	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
		2133	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
		2134	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
		2135	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
		2136	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
		2137
		2138	/***************** Bit definition for SCB_VTOR register *****************/
		2139	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
		2140	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
		2141
		2142	/!<************** Bit definition for SCB_AIRCR register *****************/
		2143	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
		2144	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
		2145	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
		2146
		2147	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
		2148	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2149	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2150	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
		2151
		2152	/* prority group configuration */
		2153	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
		2154	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
		2155	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
		2156	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
		2157	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
		2158	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
		2159	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
		2160	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
		2161
		2162	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
		2163	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
		2164
		2165	/***************** Bit definition for SCB_SCR register ******************/
		2166	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
		2167	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
		2168	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
		2169
		2170	/****************** Bit definition for SCB_CCR register *****************/
		2171	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
		2172	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
		2173	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
		2174	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
		2175	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
		2176	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
		2177
		2178	/***************** Bit definition for SCB_SHPR register ******************/
		2179	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
		2180	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
		2181	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
		2182	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
		2183
		2184	/**************** Bit definition for SCB_SHCSR register *****************/
		2185	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
		2186	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
		2187	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
		2188	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
		2189	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
		2190	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
		2191	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
		2192	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
		2193	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
		2194	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
		2195	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
		2196	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
		2197	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
		2198	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
		2199
		2200	/***************** Bit definition for SCB_CFSR register *****************/
		2201	/!< MFSR /
		2202	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
		2203	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
		2204	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
		2205	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
		2206	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
		2207	/!< BFSR /
		2208	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
		2209	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
		2210	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
		2211	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
		2212	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
		2213	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
		2214	/!< UFSR /
		2215	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to execute an undefined instruction /
		2216	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
		2217	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
		2218	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
		2219	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
		2220	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
		2221
		2222	/***************** Bit definition for SCB_HFSR register *****************/
		2223	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
		2224	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
		2225	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
		2226
		2227	/***************** Bit definition for SCB_DFSR register *****************/
		2228	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
		2229	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
		2230	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
		2231	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
		2232	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
		2233
		2234	/***************** Bit definition for SCB_MMFAR register ****************/
		2235	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
		2236
		2237	/***************** Bit definition for SCB_BFAR register *****************/
		2238	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
		2239
		2240	/***************** Bit definition for SCB_afsr register *****************/
		2241	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
		2242
		2243	/******************************************************************************/
		2244	/* */
		2245	/* External Interrupt/Event Controller */
		2246	/* */
		2247	/******************************************************************************/
		2248
		2249	/***************** Bit definition for EXTI_IMR register *****************/
		2250	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
		2251	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
		2252	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
		2253	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
		2254	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
		2255	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
		2256	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
		2257	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
		2258	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
		2259	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
		2260	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
		2261	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
		2262	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
		2263	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
		2264	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
		2265	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
		2266	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
		2267	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
		2268	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
		2269	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
		2270
		2271	/***************** Bit definition for EXTI_EMR register *****************/
		2272	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
		2273	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
		2274	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
		2275	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
		2276	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
		2277	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
		2278	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
		2279	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
		2280	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
		2281	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
		2282	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
		2283	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
		2284	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
		2285	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
		2286	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
		2287	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
		2288	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
		2289	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
		2290	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
		2291	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
		2292
		2293	/**************** Bit definition for EXTI_RTSR register *****************/
		2294	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
		2295	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
		2296	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
		2297	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
		2298	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
		2299	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
		2300	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
		2301	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
		2302	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
		2303	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
		2304	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
		2305	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
		2306	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
		2307	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
		2308	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
		2309	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
		2310	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
		2311	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
		2312	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
		2313	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
		2314
		2315	/**************** Bit definition for EXTI_FTSR register *****************/
		2316	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
		2317	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
		2318	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
		2319	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
		2320	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
		2321	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
		2322	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
		2323	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
		2324	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
		2325	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
		2326	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
		2327	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
		2328	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
		2329	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
		2330	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
		2331	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
		2332	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
		2333	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
		2334	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
		2335	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
		2336
		2337	/**************** Bit definition for EXTI_SWIER register ****************/
		2338	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
		2339	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
		2340	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
		2341	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
		2342	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
		2343	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
		2344	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
		2345	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
		2346	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
		2347	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
		2348	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
		2349	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
		2350	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
		2351	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
		2352	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
		2353	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
		2354	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
		2355	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
		2356	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
		2357	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
		2358
		2359	/***************** Bit definition for EXTI_PR register ******************/
		2360	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
		2361	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
		2362	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
		2363	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
		2364	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
		2365	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
		2366	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
		2367	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
		2368	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
		2369	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
		2370	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
		2371	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
		2372	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
		2373	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
		2374	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
		2375	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
		2376	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
		2377	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
		2378	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
		2379	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
		2380
		2381	/******************************************************************************/
		2382	/* */
		2383	/* DMA Controller */
		2384	/* */
		2385	/******************************************************************************/
		2386
		2387	/***************** Bit definition for DMA_ISR register ******************/
		2388	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
		2389	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
		2390	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
		2391	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
		2392	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
		2393	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
		2394	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
		2395	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
		2396	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
		2397	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
		2398	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
		2399	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
		2400	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
		2401	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
		2402	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
		2403	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
		2404	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
		2405	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
		2406	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
		2407	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
		2408	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
		2409	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
		2410	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
		2411	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
		2412	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
		2413	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
		2414	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
		2415	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
		2416
		2417	/***************** Bit definition for DMA_IFCR register *****************/
		2418	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
		2419	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
		2420	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
		2421	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
		2422	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
		2423	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
		2424	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
		2425	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
		2426	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
		2427	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
		2428	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
		2429	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
		2430	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
		2431	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
		2432	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
		2433	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
		2434	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
		2435	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
		2436	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
		2437	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
		2438	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
		2439	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
		2440	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
		2441	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
		2442	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
		2443	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
		2444	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
		2445	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
		2446
		2447	/***************** Bit definition for DMA_CCR register *****************/
		2448	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
		2449	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
		2450	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
		2451	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
		2452	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
		2453	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
		2454	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
		2455	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
		2456
		2457	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
		2458	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2459	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2460
		2461	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
		2462	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2463	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2464
		2465	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level) /
		2466	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2467	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2468
		2469	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
		2470
		2471	/**************** Bit definition for DMA_CNDTR register ****************/
		2472	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
		2473
		2474	/**************** Bit definition for DMA_CPAR register *****************/
		2475	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
		2476
		2477	/**************** Bit definition for DMA_CMAR register *****************/
		2478	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
		2479
		2480	/******************************************************************************/
		2481	/* */
		2482	/* Analog to Digital Converter */
		2483	/* */
		2484	/******************************************************************************/
		2485
		2486	/****************** Bit definition for ADC_SR register ******************/
		2487	#define ADC_SR_AWD ((uint32_t)0x00000001) /!< Analog watchdog flag /
		2488	#define ADC_SR_EOC ((uint32_t)0x00000002) /!< End of conversion /
		2489	#define ADC_SR_JEOC ((uint32_t)0x00000004) /!< Injected channel end of conversion /
		2490	#define ADC_SR_JSTRT ((uint32_t)0x00000008) /!< Injected channel Start flag /
		2491	#define ADC_SR_STRT ((uint32_t)0x00000010) /!< Regular channel Start flag /
		2492
		2493	/***************** Bit definition for ADC_CR1 register ******************/
		2494	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
		2495	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2496	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2497	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2498	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2499	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2500
		2501	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
		2502	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
		2503	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
		2504	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
		2505	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
		2506	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
		2507	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
		2508	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
		2509
		2510	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
		2511	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
		2512	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
		2513	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
		2514
		2515	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
		2516	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
		2517
		2518
		2519	/***************** Bit definition for ADC_CR2 register ******************/
		2520	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
		2521	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
		2522	#define ADC_CR2_CAL ((uint32_t)0x00000004) /!< A/D Calibration /
		2523	#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /!< Reset Calibration /
		2524	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
		2525	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
		2526
		2527	#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /!< JEXTSEL[2:0] bits (External event select for injected group) /
		2528	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2529	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2530	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2531
		2532	#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /!< External Trigger Conversion mode for injected channels /
		2533
		2534	#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
		2535	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /!< Bit 0 /
		2536	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /!< Bit 1 /
		2537	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /!< Bit 2 /
		2538
		2539	#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /!< External Trigger Conversion mode for regular channels /
		2540	#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /!< Start Conversion of injected channels /
		2541	#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /!< Start Conversion of regular channels /
		2542	#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
		2543
		2544	/**************** Bit definition for ADC_SMPR1 register *****************/
		2545	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
		2546	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2547	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2548	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2549
		2550	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
		2551	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2552	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2553	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2554
		2555	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
		2556	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2557	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2558	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
		2559
		2560	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
		2561	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
		2562	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
		2563	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
		2564
		2565	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
		2566	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2567	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2568	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2569
		2570	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 15 Sample time selection) /
		2571	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2572	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2573	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2574
		2575	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
		2576	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
		2577	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
		2578	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
		2579
		2580	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
		2581	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
		2582	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
		2583	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
		2584
		2585	/**************** Bit definition for ADC_SMPR2 register *****************/
		2586	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
		2587	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2588	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2589	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2590
		2591	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
		2592	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2593	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2594	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2595
		2596	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
		2597	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2598	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2599	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
		2600
		2601	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
		2602	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
		2603	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
		2604	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
		2605
		2606	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
		2607	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
		2608	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
		2609	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
		2610
		2611	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
		2612	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2613	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2614	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2615
		2616	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
		2617	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
		2618	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
		2619	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
		2620
		2621	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
		2622	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
		2623	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
		2624	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
		2625
		2626	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
		2627	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
		2628	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
		2629	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
		2630
		2631	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
		2632	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
		2633	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
		2634	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
		2635
		2636	/**************** Bit definition for ADC_JOFR1 register *****************/
		2637	#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 1 /
		2638
		2639	/**************** Bit definition for ADC_JOFR2 register *****************/
		2640	#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 2 /
		2641
		2642	/**************** Bit definition for ADC_JOFR3 register *****************/
		2643	#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 3 /
		2644
		2645	/**************** Bit definition for ADC_JOFR4 register *****************/
		2646	#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /!< Data offset for injected channel 4 /
		2647
		2648	/***************** Bit definition for ADC_HTR register ******************/
		2649	#define ADC_HTR_HT ((uint32_t)0x00000FFF) /!< Analog watchdog high threshold /
		2650
		2651	/***************** Bit definition for ADC_LTR register ******************/
		2652	#define ADC_LTR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
		2653
		2654	/***************** Bit definition for ADC_SQR1 register *****************/
		2655	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
		2656	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2657	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2658	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2659	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2660	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2661
		2662	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
		2663	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2664	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2665	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2666	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2667	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2668
		2669	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
		2670	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2671	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2672	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2673	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2674	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2675
		2676	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
		2677	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2678	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2679	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2680	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2681	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2682
		2683	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!< L[3:0] bits (Regular channel sequence length) /
		2684	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2685	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2686	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2687	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2688
		2689	/***************** Bit definition for ADC_SQR2 register *****************/
		2690	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
		2691	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2692	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2693	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2694	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2695	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2696
		2697	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
		2698	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2699	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2700	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2701	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2702	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2703
		2704	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
		2705	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2706	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2707	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2708	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2709	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2710
		2711	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
		2712	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2713	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2714	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2715	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2716	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2717
		2718	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
		2719	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2720	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2721	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2722	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2723	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
		2724
		2725	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
		2726	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
		2727	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
		2728	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
		2729	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
		2730	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
		2731
		2732	/***************** Bit definition for ADC_SQR3 register *****************/
		2733	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
		2734	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2735	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2736	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2737	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2738	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2739
		2740	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
		2741	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2742	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2743	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2744	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2745	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2746
		2747	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
		2748	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2749	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2750	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2751	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2752	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2753
		2754	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
		2755	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2756	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2757	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2758	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2759	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2760
		2761	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
		2762	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2763	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2764	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
		2765	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
		2766	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
		2767
		2768	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
		2769	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
		2770	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
		2771	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
		2772	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
		2773	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
		2774
		2775	/***************** Bit definition for ADC_JSQR register *****************/
		2776	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
		2777	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2778	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2779	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2780	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2781	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
		2782
		2783	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
		2784	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
		2785	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
		2786	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
		2787	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
		2788	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
		2789
		2790	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
		2791	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
		2792	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
		2793	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
		2794	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
		2795	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
		2796
		2797	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
		2798	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
		2799	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
		2800	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
		2801	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
		2802	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
		2803
		2804	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
		2805	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
		2806	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
		2807
		2808	/***************** Bit definition for ADC_JDR1 register *****************/
		2809	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2810
		2811	/***************** Bit definition for ADC_JDR2 register *****************/
		2812	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2813
		2814	/***************** Bit definition for ADC_JDR3 register *****************/
		2815	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2816
		2817	/***************** Bit definition for ADC_JDR4 register *****************/
		2818	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< Injected data /
		2819
		2820	/****************** Bit definition for ADC_DR register ******************/
		2821	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
		2822	/******************************************************************************/
		2823	/* */
		2824	/* Digital to Analog Converter */
		2825	/* */
		2826	/******************************************************************************/
		2827
		2828	/****************** Bit definition for DAC_CR register ******************/
		2829	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
		2830	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
		2831	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
		2832
		2833	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
		2834	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
		2835	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
		2836	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
		2837
		2838	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
		2839	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
		2840	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
		2841
		2842	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
		2843	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2844	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2845	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
		2846	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
		2847
		2848	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
		2849	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
		2850	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
		2851	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
		2852
		2853	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
		2854	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
		2855	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
		2856	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
		2857
		2858	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
		2859	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
		2860	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
		2861
		2862	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
		2863	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
		2864	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
		2865	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
		2866	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
		2867
		2868	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
		2869
		2870	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun interrupt enable /
		2871	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun interrupt enable /
		2872
		2873	/*************** Bit definition for DAC_SWTRIGR register ****************/
		2874	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!< DAC channel1 software trigger /
		2875	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!< DAC channel2 software trigger /
		2876
		2877	/*************** Bit definition for DAC_DHR12R1 register ****************/
		2878	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
		2879
		2880	/*************** Bit definition for DAC_DHR12L1 register ****************/
		2881	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
		2882
		2883	/**************** Bit definition for DAC_DHR8R1 register ****************/
		2884	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
		2885
		2886	/*************** Bit definition for DAC_DHR12R2 register ****************/
		2887	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!< DAC channel2 12-bit Right aligned data /
		2888
		2889	/*************** Bit definition for DAC_DHR12L2 register ****************/
		2890	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!< DAC channel2 12-bit Left aligned data /
		2891
		2892	/**************** Bit definition for DAC_DHR8R2 register ****************/
		2893	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!< DAC channel2 8-bit Right aligned data /
		2894
		2895	/*************** Bit definition for DAC_DHR12RD register ****************/
		2896	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
		2897	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!< DAC channel2 12-bit Right aligned data /
		2898
		2899	/*************** Bit definition for DAC_DHR12LD register ****************/
		2900	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
		2901	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!< DAC channel2 12-bit Left aligned data /
		2902
		2903	/**************** Bit definition for DAC_DHR8RD register ****************/
		2904	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
		2905	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!< DAC channel2 8-bit Right aligned data /
		2906
		2907	/***************** Bit definition for DAC_DOR1 register *****************/
		2908	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!< DAC channel1 data output /
		2909
		2910	/***************** Bit definition for DAC_DOR2 register *****************/
		2911	#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /!< DAC channel2 data output /
		2912
		2913	/****************** Bit definition for DAC_SR register ******************/
		2914	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun flag /
		2915	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun flag /
		2916
		2917	/******************************************************************************/
		2918	/* */
		2919	/* CEC */
		2920	/* */
		2921	/******************************************************************************/
		2922	/****************** Bit definition for CEC_CFGR register ****************/
		2923	#define CEC_CFGR_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
		2924	#define CEC_CFGR_IE ((uint32_t)0x00000002) /!< Interrupt Enable /
		2925	#define CEC_CFGR_BTEM ((uint32_t)0x00000004) /!< Bit Timing Error Mode /
		2926	#define CEC_CFGR_BPEM ((uint32_t)0x00000008) /!< Bit Period Error Mode /
		2927
		2928	/****************** Bit definition for CEC_OAR register ****************/
		2929	#define CEC_OAR_OA ((uint32_t)0x0000000F) /!< OA[3:0]: Own Address /
		2930	#define CEC_OAR_OA_0 ((uint32_t)0x00000001) /!< Bit 0 /
		2931	#define CEC_OAR_OA_1 ((uint32_t)0x00000002) /!< Bit 1 /
		2932	#define CEC_OAR_OA_2 ((uint32_t)0x00000004) /!< Bit 2 /
		2933	#define CEC_OAR_OA_3 ((uint32_t)0x00000008) /!< Bit 3 /
		2934
		2935	/****************** Bit definition for CEC_PRES register ****************/
		2936	#define CEC_PRES_PRES ((uint32_t)0x00003FFF) /!< Prescaler Counter Value /
		2937
		2938	/****************** Bit definition for CEC_ESR register ****************/
		2939	#define CEC_ESR_BTE ((uint32_t)0x00000001) /!< Bit Timing Error /
		2940	#define CEC_ESR_BPE ((uint32_t)0x00000002) /!< Bit Period Error /
		2941	#define CEC_ESR_RBTFE ((uint32_t)0x00000004) /!< Rx Block Transfer Finished Error /
		2942	#define CEC_ESR_SBE ((uint32_t)0x00000008) /!< Start Bit Error /
		2943	#define CEC_ESR_ACKE ((uint32_t)0x00000010) /!< Block Acknowledge Error /
		2944	#define CEC_ESR_LINE ((uint32_t)0x00000020) /!< Line Error /
		2945	#define CEC_ESR_TBTFE ((uint32_t)0x00000040) /!< Tx Block Transfer Finished Error /
		2946
		2947	/****************** Bit definition for CEC_CSR register ****************/
		2948	#define CEC_CSR_TSOM ((uint32_t)0x00000001) /!< Tx Start Of Message /
		2949	#define CEC_CSR_TEOM ((uint32_t)0x00000002) /!< Tx End Of Message /
		2950	#define CEC_CSR_TERR ((uint32_t)0x00000004) /!< Tx Error /
		2951	#define CEC_CSR_TBTRF ((uint32_t)0x00000008) /!< Tx Byte Transfer Request or Block Transfer Finished /
		2952	#define CEC_CSR_RSOM ((uint32_t)0x00000010) /!< Rx Start Of Message /
		2953	#define CEC_CSR_REOM ((uint32_t)0x00000020) /!< Rx End Of Message /
		2954	#define CEC_CSR_RERR ((uint32_t)0x00000040) /!< Rx Error /
		2955	#define CEC_CSR_RBTF ((uint32_t)0x00000080) /!< Rx Block Transfer Finished /
		2956
		2957	/****************** Bit definition for CEC_TXD register ****************/
		2958	#define CEC_TXD_TXD ((uint32_t)0x000000FF) /!< Tx Data register /
		2959
		2960	/****************** Bit definition for CEC_RXD register ****************/
		2961	#define CEC_RXD_RXD ((uint32_t)0x000000FF) /!< Rx Data register /
		2962
		2963	/*****************************************************************************/
		2964	/* */
		2965	/* Timers (TIM) */
		2966	/* */
		2967	/*****************************************************************************/
		2968	/***************** Bit definition for TIM_CR1 register *****************/
		2969	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
		2970	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
		2971	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
		2972	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
		2973	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
		2974
		2975	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
		2976	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
		2977	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
		2978
		2979	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
		2980
		2981	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
		2982	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
		2983	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
		2984
		2985	/***************** Bit definition for TIM_CR2 register *****************/
		2986	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
		2987	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
		2988	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
		2989
		2990	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
		2991	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
		2992	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
		2993	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
		2994
		2995	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
		2996	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
		2997	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
		2998	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
		2999	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
		3000	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
		3001	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
		3002	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
		3003
		3004	/***************** Bit definition for TIM_SMCR register ****************/
		3005	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
		3006	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3007	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3008	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
		3009
		3010	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
		3011
		3012	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
		3013	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3014	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3015	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3016
		3017	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
		3018
		3019	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
		3020	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3021	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3022	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
		3023	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
		3024
		3025	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
		3026	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3027	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3028
		3029	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
		3030	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
		3031
		3032	/***************** Bit definition for TIM_DIER register ****************/
		3033	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
		3034	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
		3035	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
		3036	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
		3037	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
		3038	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
		3039	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
		3040	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
		3041	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
		3042	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
		3043	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
		3044	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
		3045	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
		3046	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
		3047	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
		3048
		3049	/****************** Bit definition for TIM_SR register *****************/
		3050	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
		3051	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
		3052	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
		3053	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
		3054	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
		3055	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
		3056	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
		3057	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
		3058	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
		3059	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
		3060	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
		3061	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
		3062
		3063	/***************** Bit definition for TIM_EGR register *****************/
		3064	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
		3065	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
		3066	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
		3067	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
		3068	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
		3069	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
		3070	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
		3071	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
		3072
		3073	/**************** Bit definition for TIM_CCMR1 register ****************/
		3074	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
		3075	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3076	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3077
		3078	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
		3079	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
		3080
		3081	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
		3082	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3083	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3084	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3085
		3086	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
		3087
		3088	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
		3089	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3090	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3091
		3092	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
		3093	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
		3094
		3095	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
		3096	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3097	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3098	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3099
		3100	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
		3101
		3102	/---------------------------------------------------------------------------/
		3103
		3104	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
		3105	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
		3106	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
		3107
		3108	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
		3109	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3110	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3111	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3112	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
		3113
		3114	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
		3115	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
		3116	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
		3117
		3118	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
		3119	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3120	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3121	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3122	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
		3123
		3124	/**************** Bit definition for TIM_CCMR2 register ****************/
		3125	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
		3126	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3127	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3128
		3129	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
		3130	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
		3131
		3132	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
		3133	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3134	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3135	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3136
		3137	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
		3138
		3139	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
		3140	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3141	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3142
		3143	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
		3144	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
		3145
		3146	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
		3147	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3148	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3149	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3150
		3151	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
		3152
		3153	/---------------------------------------------------------------------------/
		3154
		3155	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
		3156	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
		3157	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
		3158
		3159	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
		3160	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
		3161	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
		3162	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
		3163	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
		3164
		3165	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
		3166	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
		3167	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
		3168
		3169	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
		3170	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
		3171	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
		3172	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
		3173	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
		3174
		3175	/***************** Bit definition for TIM_CCER register ****************/
		3176	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
		3177	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
		3178	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
		3179	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
		3180	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
		3181	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
		3182	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
		3183	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
		3184	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
		3185	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
		3186	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
		3187	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
		3188	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
		3189	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
		3190	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
		3191
		3192	/***************** Bit definition for TIM_CNT register *****************/
		3193	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
		3194
		3195	/***************** Bit definition for TIM_PSC register *****************/
		3196	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
		3197
		3198	/***************** Bit definition for TIM_ARR register *****************/
		3199	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
		3200
		3201	/***************** Bit definition for TIM_RCR register *****************/
		3202	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
		3203
		3204	/***************** Bit definition for TIM_CCR1 register ****************/
		3205	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
		3206
		3207	/***************** Bit definition for TIM_CCR2 register ****************/
		3208	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
		3209
		3210	/***************** Bit definition for TIM_CCR3 register ****************/
		3211	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
		3212
		3213	/***************** Bit definition for TIM_CCR4 register ****************/
		3214	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
		3215
		3216	/***************** Bit definition for TIM_BDTR register ****************/
		3217	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
		3218	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3219	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3220	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
		3221	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
		3222	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
		3223	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
		3224	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
		3225	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
		3226
		3227	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
		3228	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3229	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3230
		3231	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
		3232	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
		3233	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
		3234	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
		3235	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
		3236	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
		3237
		3238	/***************** Bit definition for TIM_DCR register *****************/
		3239	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
		3240	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
		3241	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
		3242	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
		3243	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
		3244	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
		3245
		3246	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
		3247	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
		3248	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
		3249	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
		3250	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
		3251	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
		3252
		3253	/***************** Bit definition for TIM_DMAR register ****************/
		3254	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
		3255
		3256	/***************** Bit definition for TIM_OR register ******************/
		3257
		3258	/******************************************************************************/
		3259	/* */
		3260	/* Real-Time Clock */
		3261	/* */
		3262	/******************************************************************************/
		3263
		3264	/***************** Bit definition for RTC_CRH register ******************/
		3265	#define RTC_CRH_SECIE ((uint32_t)0x00000001) /!< Second Interrupt Enable /
		3266	#define RTC_CRH_ALRIE ((uint32_t)0x00000002) /!< Alarm Interrupt Enable /
		3267	#define RTC_CRH_OWIE ((uint32_t)0x00000004) /!< OverfloW Interrupt Enable /
		3268
		3269	/***************** Bit definition for RTC_CRL register ******************/
		3270	#define RTC_CRL_SECF ((uint32_t)0x00000001) /!< Second Flag /
		3271	#define RTC_CRL_ALRF ((uint32_t)0x00000002) /!< Alarm Flag /
		3272	#define RTC_CRL_OWF ((uint32_t)0x00000004) /!< OverfloW Flag /
		3273	#define RTC_CRL_RSF ((uint32_t)0x00000008) /!< Registers Synchronized Flag /
		3274	#define RTC_CRL_CNF ((uint32_t)0x00000010) /!< Configuration Flag /
		3275	#define RTC_CRL_RTOFF ((uint32_t)0x00000020) /!< RTC operation OFF /
		3276
		3277	/***************** Bit definition for RTC_PRLH register *****************/
		3278	#define RTC_PRLH_PRL ((uint32_t)0x0000000F) /!< RTC Prescaler Reload Value High /
		3279
		3280	/***************** Bit definition for RTC_PRLL register *****************/
		3281	#define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /!< RTC Prescaler Reload Value Low /
		3282
		3283	/***************** Bit definition for RTC_DIVH register *****************/
		3284	#define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /!< RTC Clock Divider High /
		3285
		3286	/***************** Bit definition for RTC_DIVL register *****************/
		3287	#define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /!< RTC Clock Divider Low /
		3288
		3289	/***************** Bit definition for RTC_CNTH register *****************/
		3290	#define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter High /
		3291
		3292	/***************** Bit definition for RTC_CNTL register *****************/
		3293	#define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /!< RTC Counter Low /
		3294
		3295	/***************** Bit definition for RTC_ALRH register *****************/
		3296	#define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm High /
		3297
		3298	/***************** Bit definition for RTC_ALRL register *****************/
		3299	#define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /!< RTC Alarm Low /
		3300
		3301	/******************************************************************************/
		3302	/* */
		3303	/* Independent WATCHDOG (IWDG) */
		3304	/* */
		3305	/******************************************************************************/
		3306
		3307	/***************** Bit definition for IWDG_KR register ******************/
		3308	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!< Key value (write only, read 0000h) /
		3309
		3310	/***************** Bit definition for IWDG_PR register ******************/
		3311	#define IWDG_PR_PR ((uint32_t)0x00000007) /!< PR[2:0] (Prescaler divider) /
		3312	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3313	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3314	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3315
		3316	/***************** Bit definition for IWDG_RLR register *****************/
		3317	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!< Watchdog counter reload value /
		3318
		3319	/***************** Bit definition for IWDG_SR register ******************/
		3320	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
		3321	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
		3322
		3323	/******************************************************************************/
		3324	/* */
		3325	/* Window WATCHDOG */
		3326	/* */
		3327	/******************************************************************************/
		3328
		3329	/***************** Bit definition for WWDG_CR register ******************/
		3330	#define WWDG_CR_T ((uint32_t)0x0000007F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
		3331	#define WWDG_CR_T0 ((uint32_t)0x00000001) /!< Bit 0 /
		3332	#define WWDG_CR_T1 ((uint32_t)0x00000002) /!< Bit 1 /
		3333	#define WWDG_CR_T2 ((uint32_t)0x00000004) /!< Bit 2 /
		3334	#define WWDG_CR_T3 ((uint32_t)0x00000008) /!< Bit 3 /
		3335	#define WWDG_CR_T4 ((uint32_t)0x00000010) /!< Bit 4 /
		3336	#define WWDG_CR_T5 ((uint32_t)0x00000020) /!< Bit 5 /
		3337	#define WWDG_CR_T6 ((uint32_t)0x00000040) /!< Bit 6 /
		3338
		3339	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!< Activation bit /
		3340
		3341	/***************** Bit definition for WWDG_CFR register *****************/
		3342	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!< W[6:0] bits (7-bit window value) /
		3343	#define WWDG_CFR_W0 ((uint32_t)0x00000001) /!< Bit 0 /
		3344	#define WWDG_CFR_W1 ((uint32_t)0x00000002) /!< Bit 1 /
		3345	#define WWDG_CFR_W2 ((uint32_t)0x00000004) /!< Bit 2 /
		3346	#define WWDG_CFR_W3 ((uint32_t)0x00000008) /!< Bit 3 /
		3347	#define WWDG_CFR_W4 ((uint32_t)0x00000010) /!< Bit 4 /
		3348	#define WWDG_CFR_W5 ((uint32_t)0x00000020) /!< Bit 5 /
		3349	#define WWDG_CFR_W6 ((uint32_t)0x00000040) /!< Bit 6 /
		3350
		3351	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!< WDGTB[1:0] bits (Timer Base) /
		3352	#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /!< Bit 0 /
		3353	#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /!< Bit 1 /
		3354
		3355	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!< Early Wakeup Interrupt /
		3356
		3357	/***************** Bit definition for WWDG_SR register ******************/
		3358	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!< Early Wakeup Interrupt Flag /
		3359
		3360	/******************************************************************************/
		3361	/* */
		3362	/* Flexible Static Memory Controller */
		3363	/* */
		3364	/******************************************************************************/
		3365
		3366	/**************** Bit definition for FSMC_BCRx (x=1..4) register ********/
		3367	#define FSMC_BCRx_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
		3368	#define FSMC_BCRx_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
		3369
		3370	#define FSMC_BCRx_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
		3371	#define FSMC_BCRx_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
		3372	#define FSMC_BCRx_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
		3373
		3374	#define FSMC_BCRx_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
		3375	#define FSMC_BCRx_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3376	#define FSMC_BCRx_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3377
		3378	#define FSMC_BCRx_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
		3379	#define FSMC_BCRx_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
		3380	#define FSMC_BCRx_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit /
		3381	#define FSMC_BCRx_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
		3382	#define FSMC_BCRx_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
		3383	#define FSMC_BCRx_WREN ((uint32_t)0x00001000) /!< Write enable bit /
		3384	#define FSMC_BCRx_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
		3385	#define FSMC_BCRx_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
		3386	#define FSMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
		3387	#define FSMC_BCRx_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
		3388
		3389	/**************** Bit definition for FSMC_BTRx (x=1..4) register ****/
		3390	#define FSMC_BTRx_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
		3391	#define FSMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3392	#define FSMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3393	#define FSMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3394	#define FSMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3395
		3396	#define FSMC_BTRx_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		3397	#define FSMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3398	#define FSMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3399	#define FSMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
		3400	#define FSMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
		3401
		3402	#define FSMC_BTRx_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
		3403	#define FSMC_BTRx_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
		3404	#define FSMC_BTRx_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
		3405	#define FSMC_BTRx_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
		3406	#define FSMC_BTRx_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
		3407	#define FSMC_BTRx_DATAST_4 ((uint32_t)0x00001000) /!< Bit 4 /
		3408	#define FSMC_BTRx_DATAST_5 ((uint32_t)0x00002000) /!< Bit 5 /
		3409	#define FSMC_BTRx_DATAST_6 ((uint32_t)0x00004000) /!< Bit 6 /
		3410	#define FSMC_BTRx_DATAST_7 ((uint32_t)0x00008000) /!< Bit 7 /
		3411
		3412	#define FSMC_BTRx_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
		3413	#define FSMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
		3414	#define FSMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
		3415	#define FSMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
		3416	#define FSMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
		3417
		3418	#define FSMC_BTRx_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
		3419	#define FSMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
		3420	#define FSMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
		3421	#define FSMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
		3422	#define FSMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
		3423
		3424	#define FSMC_BTRx_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
		3425	#define FSMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
		3426	#define FSMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
		3427	#define FSMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
		3428	#define FSMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
		3429
		3430	#define FSMC_BTRx_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
		3431	#define FSMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
		3432	#define FSMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
		3433
		3434	/**************** Bit definition for FSMC_BWTRx (x=1..4) register ****/
		3435	#define FSMC_BWTRx_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
		3436	#define FSMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3437	#define FSMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3438	#define FSMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3439	#define FSMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3440
		3441	#define FSMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		3442	#define FSMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
		3443	#define FSMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
		3444	#define FSMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
		3445	#define FSMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
		3446
		3447	#define FSMC_BWTRx_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
		3448	#define FSMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
		3449	#define FSMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
		3450	#define FSMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
		3451	#define FSMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
		3452	#define FSMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) /!< Bit 4 /
		3453	#define FSMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) /!< Bit 5 /
		3454	#define FSMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) /!< Bit 6 /
		3455	#define FSMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) /!< Bit 7 /
		3456
		3457	#define FSMC_BWTRx_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
		3458	#define FSMC_BWTRx_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
		3459	#define FSMC_BWTRx_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
		3460	#define FSMC_BWTRx_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
		3461	#define FSMC_BWTRx_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
		3462
		3463	#define FSMC_BWTRx_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
		3464	#define FSMC_BWTRx_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
		3465	#define FSMC_BWTRx_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
		3466	#define FSMC_BWTRx_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
		3467	#define FSMC_BWTRx_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
		3468
		3469	#define FSMC_BWTRx_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
		3470	#define FSMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
		3471	#define FSMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
		3472
		3473
		3474	/******************************************************************************/
		3475	/* */
		3476	/* SD host Interface */
		3477	/* */
		3478	/******************************************************************************/
		3479
		3480	/**************** Bit definition for SDIO_POWER register ****************/
		3481	#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /!< PWRCTRL[1:0] bits (Power supply control bits) /
		3482	#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /!< Bit 0 /
		3483	#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /!< Bit 1 /
		3484
		3485	/**************** Bit definition for SDIO_CLKCR register ****************/
		3486	#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /!< Clock divide factor /
		3487	#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /!< Clock enable bit /
		3488	#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /!< Power saving configuration bit /
		3489	#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /!< Clock divider bypass enable bit /
		3490
		3491	#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
		3492	#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /!< Bit 0 /
		3493	#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /!< Bit 1 /
		3494
		3495	#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /!< SDIO_CK dephasing selection bit /
		3496	#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /!< HW Flow Control enable /
		3497
		3498	/***************** Bit definition for SDIO_ARG register *****************/
		3499	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!< Command argument /
		3500
		3501	/***************** Bit definition for SDIO_CMD register *****************/
		3502	#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /!< Command Index /
		3503
		3504	#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /!< WAITRESP[1:0] bits (Wait for response bits) /
		3505	#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /!< Bit 0 /
		3506	#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /!< Bit 1 /
		3507
		3508	#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /!< CPSM Waits for Interrupt Request /
		3509	#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
		3510	#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /!< Command path state machine (CPSM) Enable bit /
		3511	#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /!< SD I/O suspend command /
		3512	#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /!< Enable CMD completion /
		3513	#define SDIO_CMD_NIEN ((uint32_t)0x2000) /!< Not Interrupt Enable /
		3514	#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /!< CE-ATA command /
		3515
		3516	/*************** Bit definition for SDIO_RESPCMD register ***************/
		3517	#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /!< Response command index /
		3518
		3519	/**************** Bit definition for SDIO_RESP0 register ****************/
		3520	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3521
		3522	/**************** Bit definition for SDIO_RESP1 register ****************/
		3523	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3524
		3525	/**************** Bit definition for SDIO_RESP2 register ****************/
		3526	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3527
		3528	/**************** Bit definition for SDIO_RESP3 register ****************/
		3529	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3530
		3531	/**************** Bit definition for SDIO_RESP4 register ****************/
		3532	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!< Card Status /
		3533
		3534	/**************** Bit definition for SDIO_DTIMER register ***************/
		3535	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!< Data timeout period. /
		3536
		3537	/**************** Bit definition for SDIO_DLEN register *****************/
		3538	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!< Data length value /
		3539
		3540	/**************** Bit definition for SDIO_DCTRL register ****************/
		3541	#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /!< Data transfer enabled bit /
		3542	#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /!< Data transfer direction selection /
		3543	#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /!< Data transfer mode selection /
		3544	#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /!< DMA enabled bit /
		3545
		3546	#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /!< DBLOCKSIZE[3:0] bits (Data block size) /
		3547	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /!< Bit 0 /
		3548	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /!< Bit 1 /
		3549	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /!< Bit 2 /
		3550	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /!< Bit 3 /
		3551
		3552	#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /!< Read wait start /
		3553	#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /!< Read wait stop /
		3554	#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /!< Read wait mode /
		3555	#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /!< SD I/O enable functions /
		3556
		3557	/**************** Bit definition for SDIO_DCOUNT register ***************/
		3558	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!< Data count value /
		3559
		3560	/**************** Bit definition for SDIO_STA register ******************/
		3561	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!< Command response received (CRC check failed) /
		3562	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!< Data block sent/received (CRC check failed) /
		3563	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!< Command response timeout /
		3564	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!< Data timeout /
		3565	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!< Transmit FIFO underrun error /
		3566	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!< Received FIFO overrun error /
		3567	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!< Command response received (CRC check passed) /
		3568	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!< Command sent (no response required) /
		3569	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!< Data end (data counter, SDIDCOUNT, is zero) /
		3570	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!< Start bit not detected on all data signals in wide bus mode /
		3571	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!< Data block sent/received (CRC check passed) /
		3572	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!< Command transfer in progress /
		3573	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!< Data transmit in progress /
		3574	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!< Data receive in progress /
		3575	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
		3576	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
		3577	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!< Transmit FIFO full /
		3578	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!< Receive FIFO full /
		3579	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!< Transmit FIFO empty /
		3580	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!< Receive FIFO empty /
		3581	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!< Data available in transmit FIFO /
		3582	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!< Data available in receive FIFO /
		3583	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!< SDIO interrupt received /
		3584	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!< CE-ATA command completion signal received for CMD61 /
		3585
		3586	/***************** Bit definition for SDIO_ICR register *****************/
		3587	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!< CCRCFAIL flag clear bit /
		3588	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!< DCRCFAIL flag clear bit /
		3589	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!< CTIMEOUT flag clear bit /
		3590	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!< DTIMEOUT flag clear bit /
		3591	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!< TXUNDERR flag clear bit /
		3592	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!< RXOVERR flag clear bit /
		3593	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!< CMDREND flag clear bit /
		3594	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!< CMDSENT flag clear bit /
		3595	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!< DATAEND flag clear bit /
		3596	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!< STBITERR flag clear bit /
		3597	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!< DBCKEND flag clear bit /
		3598	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!< SDIOIT flag clear bit /
		3599	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!< CEATAEND flag clear bit /
		3600
		3601	/**************** Bit definition for SDIO_MASK register *****************/
		3602	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!< Command CRC Fail Interrupt Enable /
		3603	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!< Data CRC Fail Interrupt Enable /
		3604	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!< Command TimeOut Interrupt Enable /
		3605	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!< Data TimeOut Interrupt Enable /
		3606	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!< Tx FIFO UnderRun Error Interrupt Enable /
		3607	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!< Rx FIFO OverRun Error Interrupt Enable /
		3608	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!< Command Response Received Interrupt Enable /
		3609	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!< Command Sent Interrupt Enable /
		3610	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!< Data End Interrupt Enable /
		3611	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!< Start Bit Error Interrupt Enable /
		3612	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!< Data Block End Interrupt Enable /
		3613	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!< Command Acting Interrupt Enable /
		3614	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!< Data Transmit Acting Interrupt Enable /
		3615	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!< Data receive acting interrupt enabled /
		3616	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!< Tx FIFO Half Empty interrupt Enable /
		3617	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!< Rx FIFO Half Full interrupt Enable /
		3618	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!< Tx FIFO Full interrupt Enable /
		3619	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!< Rx FIFO Full interrupt Enable /
		3620	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!< Tx FIFO Empty interrupt Enable /
		3621	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!< Rx FIFO Empty interrupt Enable /
		3622	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!< Data available in Tx FIFO interrupt Enable /
		3623	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!< Data available in Rx FIFO interrupt Enable /
		3624	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!< SDIO Mode Interrupt Received interrupt Enable /
		3625	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!< CE-ATA command completion signal received Interrupt Enable /
		3626
		3627	/*************** Bit definition for SDIO_FIFOCNT register ***************/
		3628	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!< Remaining number of words to be written to or read from the FIFO /
		3629
		3630	/**************** Bit definition for SDIO_FIFO register *****************/
		3631	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!< Receive and transmit FIFO data /
		3632
		3633
		3634
		3635	/******************************************************************************/
		3636	/* */
		3637	/* Serial Peripheral Interface */
		3638	/* */
		3639	/******************************************************************************/
		3640
		3641	/***************** Bit definition for SPI_CR1 register ******************/
		3642	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
		3643	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
		3644	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
		3645
		3646	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
		3647	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
		3648	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
		3649	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
		3650
		3651	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
		3652	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
		3653	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
		3654	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
		3655	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
		3656	#define SPI_CR1_DFF ((uint32_t)0x00000800) /!< Data Frame Format /
		3657	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
		3658	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
		3659	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
		3660	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
		3661
		3662	/***************** Bit definition for SPI_CR2 register ******************/
		3663	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
		3664	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
		3665	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
		3666	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
		3667	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
		3668	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
		3669
		3670	/****************** Bit definition for SPI_SR register ******************/
		3671	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
		3672	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
		3673	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
		3674	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
		3675	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
		3676	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
		3677	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
		3678	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
		3679
		3680	/****************** Bit definition for SPI_DR register ******************/
		3681	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!< Data Register /
		3682
		3683	/***************** Bit definition for SPI_CRCPR register ****************/
		3684	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!< CRC polynomial register /
		3685
		3686	/**************** Bit definition for SPI_RXCRCR register ****************/
		3687	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!< Rx CRC Register /
		3688
		3689	/**************** Bit definition for SPI_TXCRCR register ****************/
		3690	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!< Tx CRC Register /
		3691
		3692
		3693
		3694	/******************************************************************************/
		3695	/* */
		3696	/* Inter-integrated Circuit Interface */
		3697	/* */
		3698	/******************************************************************************/
		3699
		3700	/***************** Bit definition for I2C_CR1 register ******************/
		3701	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral Enable /
		3702	#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /!< SMBus Mode /
		3703	#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /!< SMBus Type /
		3704	#define I2C_CR1_ENARP ((uint32_t)0x00000010) /!< ARP Enable /
		3705	#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /!< PEC Enable /
		3706	#define I2C_CR1_ENGC ((uint32_t)0x00000040) /!< General Call Enable /
		3707	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /!< Clock Stretching Disable (Slave mode) /
		3708	#define I2C_CR1_START ((uint32_t)0x00000100) /!< Start Generation /
		3709	#define I2C_CR1_STOP ((uint32_t)0x00000200) /!< Stop Generation /
		3710	#define I2C_CR1_ACK ((uint32_t)0x00000400) /!< Acknowledge Enable /
		3711	#define I2C_CR1_POS ((uint32_t)0x00000800) /!< Acknowledge/PEC Position (for data reception) /
		3712	#define I2C_CR1_PEC ((uint32_t)0x00001000) /!< Packet Error Checking /
		3713	#define I2C_CR1_ALERT ((uint32_t)0x00002000) /!< SMBus Alert /
		3714	#define I2C_CR1_SWRST ((uint32_t)0x00008000) /!< Software Reset /
		3715
		3716	/***************** Bit definition for I2C_CR2 register ******************/
		3717	#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
		3718	#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3719	#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3720	#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3721	#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3722	#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /!< Bit 4 /
		3723	#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /!< Bit 5 /
		3724
		3725	#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /!< Error Interrupt Enable /
		3726	#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /!< Event Interrupt Enable /
		3727	#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /!< Buffer Interrupt Enable /
		3728	#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /!< DMA Requests Enable /
		3729	#define I2C_CR2_LAST ((uint32_t)0x00001000) /!< DMA Last Transfer /
		3730
		3731	/***************** Bit definition for I2C_OAR1 register *****************/
		3732	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
		3733	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
		3734
		3735	#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /!< Bit 0 /
		3736	#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /!< Bit 1 /
		3737	#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /!< Bit 2 /
		3738	#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /!< Bit 3 /
		3739	#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /!< Bit 4 /
		3740	#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /!< Bit 5 /
		3741	#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /!< Bit 6 /
		3742	#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /!< Bit 7 /
		3743	#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /!< Bit 8 /
		3744	#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /!< Bit 9 /
		3745
		3746	#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /!< Addressing Mode (Slave mode) /
		3747
		3748	/***************** Bit definition for I2C_OAR2 register *****************/
		3749	#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /!< Dual addressing mode enable /
		3750	#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /!< Interface address /
		3751
		3752	/***************** Bit definition for I2C_SR1 register ******************/
		3753	#define I2C_SR1_SB ((uint32_t)0x00000001) /!< Start Bit (Master mode) /
		3754	#define I2C_SR1_ADDR ((uint32_t)0x00000002) /!< Address sent (master mode)/matched (slave mode) /
		3755	#define I2C_SR1_BTF ((uint32_t)0x00000004) /!< Byte Transfer Finished /
		3756	#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /!< 10-bit header sent (Master mode) /
		3757	#define I2C_SR1_STOPF ((uint32_t)0x00000010) /!< Stop detection (Slave mode) /
		3758	#define I2C_SR1_RXNE ((uint32_t)0x00000040) /!< Data Register not Empty (receivers) /
		3759	#define I2C_SR1_TXE ((uint32_t)0x00000080) /!< Data Register Empty (transmitters) /
		3760	#define I2C_SR1_BERR ((uint32_t)0x00000100) /!< Bus Error /
		3761	#define I2C_SR1_ARLO ((uint32_t)0x00000200) /!< Arbitration Lost (master mode) /
		3762	#define I2C_SR1_AF ((uint32_t)0x00000400) /!< Acknowledge Failure /
		3763	#define I2C_SR1_OVR ((uint32_t)0x00000800) /!< Overrun/Underrun /
		3764	#define I2C_SR1_PECERR ((uint32_t)0x00001000) /!< PEC Error in reception /
		3765	#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /!< Timeout or Tlow Error /
		3766	#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /!< SMBus Alert /
		3767
		3768	/***************** Bit definition for I2C_SR2 register ******************/
		3769	#define I2C_SR2_MSL ((uint32_t)0x00000001) /!< Master/Slave /
		3770	#define I2C_SR2_BUSY ((uint32_t)0x00000002) /!< Bus Busy /
		3771	#define I2C_SR2_TRA ((uint32_t)0x00000004) /!< Transmitter/Receiver /
		3772	#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /!< General Call Address (Slave mode) /
		3773	#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /!< SMBus Device Default Address (Slave mode) /
		3774	#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /!< SMBus Host Header (Slave mode) /
		3775	#define I2C_SR2_DUALF ((uint32_t)0x00000080) /!< Dual Flag (Slave mode) /
		3776	#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /!< Packet Error Checking Register /
		3777
		3778	/***************** Bit definition for I2C_CCR register ******************/
		3779	#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
		3780	#define I2C_CCR_DUTY ((uint32_t)0x00004000) /!< Fast Mode Duty Cycle /
		3781	#define I2C_CCR_FS ((uint32_t)0x00008000) /!< I2C Master Mode Selection /
		3782
		3783	/**************** Bit definition for I2C_TRISE register *****************/
		3784	#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
		3785
		3786	/******************************************************************************/
		3787	/* */
		3788	/* Universal Synchronous Asynchronous Receiver Transmitter */
		3789	/* */
		3790	/******************************************************************************/
		3791
		3792	/***************** Bit definition for USART_SR register *****************/
		3793	#define USART_SR_PE ((uint32_t)0x00000001) /!< Parity Error /
		3794	#define USART_SR_FE ((uint32_t)0x00000002) /!< Framing Error /
		3795	#define USART_SR_NE ((uint32_t)0x00000004) /!< Noise Error Flag /
		3796	#define USART_SR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
		3797	#define USART_SR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
		3798	#define USART_SR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
		3799	#define USART_SR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
		3800	#define USART_SR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
		3801	#define USART_SR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
		3802	#define USART_SR_CTS ((uint32_t)0x00000200) /!< CTS Flag /
		3803
		3804	/***************** Bit definition for USART_DR register *****************/
		3805	#define USART_DR_DR ((uint32_t)0x000001FF) /!< Data value /
		3806
		3807	/**************** Bit definition for USART_BRR register *****************/
		3808	#define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
		3809	#define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
		3810
		3811	/**************** Bit definition for USART_CR1 register *****************/
		3812	#define USART_CR1_SBK ((uint32_t)0x00000001) /!< Send Break /
		3813	#define USART_CR1_RWU ((uint32_t)0x00000002) /!< Receiver wakeup /
		3814	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
		3815	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
		3816	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
		3817	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
		3818	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
		3819	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< PE Interrupt Enable /
		3820	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
		3821	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
		3822	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
		3823	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Wakeup method /
		3824	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
		3825	#define USART_CR1_UE ((uint32_t)0x00002000) /!< USART Enable /
		3826
		3827	/**************** Bit definition for USART_CR2 register *****************/
		3828	#define USART_CR2_ADD ((uint32_t)0x0000000F) /!< Address of the USART node /
		3829	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
		3830	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
		3831	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
		3832	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
		3833	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
		3834	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
		3835
		3836	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
		3837	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
		3838	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
		3839
		3840	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
		3841
		3842	/**************** Bit definition for USART_CR3 register *****************/
		3843	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
		3844	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
		3845	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
		3846	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
		3847	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< Smartcard NACK enable /
		3848	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< Smartcard mode enable /
		3849	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
		3850	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
		3851	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
		3852	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
		3853	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
		3854
		3855	/**************** Bit definition for USART_GTPR register ****************/
		3856	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
		3857	#define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /!< Bit 0 /
		3858	#define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /!< Bit 1 /
		3859	#define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /!< Bit 2 /
		3860	#define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /!< Bit 3 /
		3861	#define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /!< Bit 4 /
		3862	#define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /!< Bit 5 /
		3863	#define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /!< Bit 6 /
		3864	#define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /!< Bit 7 /
		3865
		3866	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< Guard time value /
		3867
		3868	/******************************************************************************/
		3869	/* */
		3870	/* Debug MCU */
		3871	/* */
		3872	/******************************************************************************/
		3873
		3874	/************** Bit definition for DBGMCU_IDCODE register ***************/
		3875	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
		3876
		3877	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
		3878	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
		3879	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
		3880	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
		3881	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
		3882	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
		3883	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
		3884	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
		3885	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
		3886	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
		3887	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
		3888	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
		3889	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
		3890	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
		3891	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
		3892	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
		3893	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
		3894
		3895	/**************** Bit definition for DBGMCU_CR register *****************/
		3896	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
		3897	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
		3898	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
		3899	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
		3900
		3901	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
		3902	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
		3903	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
		3904
		3905	#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /!< Debug Independent Watchdog stopped when Core is halted /
		3906	#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /!< Debug Window Watchdog stopped when Core is halted /
		3907	#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /!< TIM1 counter stopped when core is halted /
		3908	#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /!< TIM2 counter stopped when core is halted /
		3909	#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /!< TIM3 counter stopped when core is halted /
		3910	#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /!< TIM4 counter stopped when core is halted /
		3911	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /!< SMBUS timeout mode stopped when Core is halted /
		3912	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /!< SMBUS timeout mode stopped when Core is halted /
		3913	#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /!< TIM5 counter stopped when core is halted /
		3914	#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /!< TIM6 counter stopped when core is halted /
		3915	#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /!< TIM7 counter stopped when core is halted /
		3916	#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /!< Debug TIM15 stopped when Core is halted /
		3917	#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /!< Debug TIM16 stopped when Core is halted /
		3918	#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /!< Debug TIM17 stopped when Core is halted /
		3919	#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /!< Debug TIM12 stopped when Core is halted /
		3920	#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /!< Debug TIM13 stopped when Core is halted /
		3921	#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /!< Debug TIM14 stopped when Core is halted /
		3922
		3923	/******************************************************************************/
		3924	/* */
		3925	/* FLASH and Option Bytes Registers */
		3926	/* */
		3927	/******************************************************************************/
		3928	/***************** Bit definition for FLASH_ACR register ****************/
		3929	#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /!< Flash Half Cycle Access Enable /
		3930
		3931	/**************** Bit definition for FLASH_KEYR register ****************/
		3932	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
		3933
		3934	#define RDP_KEY ((uint32_t)0x000000A5) /!< RDP Key /
		3935	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< FPEC Key1 /
		3936	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /!< FPEC Key2 /
		3937
		3938	/*************** Bit definition for FLASH_OPTKEYR register **************/
		3939	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
		3940
		3941	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
		3942	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
		3943
		3944	/**************** Bit definition for FLASH_SR register ******************/
		3945	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
		3946	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
		3947	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
		3948	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
		3949
		3950	/***************** Bit definition for FLASH_CR register *****************/
		3951	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
		3952	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
		3953	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
		3954	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
		3955	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
		3956	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
		3957	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
		3958	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
		3959	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
		3960	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
		3961
		3962	/***************** Bit definition for FLASH_AR register *****************/
		3963	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
		3964
		3965	/**************** Bit definition for FLASH_OBR register *****************/
		3966	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
		3967	#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /!< Read protection /
		3968
		3969	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /!< IWDG SW /
		3970	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /!< nRST_STOP /
		3971	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /!< nRST_STDBY /
		3972	#define FLASH_OBR_USER ((uint32_t)0x0000001C) /!< User Option Bytes /
		3973
		3974	/**************** Bit definition for FLASH_WRPR register ****************/
		3975	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
		3976
		3977	/----------------------------------------------------------------------------/
		3978
		3979	/**************** Bit definition for FLASH_RDP register *****************/
		3980	#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
		3981	#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
		3982
		3983	/**************** Bit definition for FLASH_USER register ****************/
		3984	#define FLASH_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
		3985	#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
		3986
		3987	/**************** Bit definition for FLASH_Data0 register ***************/
		3988	#define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /!< User data storage option byte /
		3989	#define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /!< User data storage complemented option byte /
		3990
		3991	/**************** Bit definition for FLASH_Data1 register ***************/
		3992	#define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /!< User data storage option byte /
		3993	#define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /!< User data storage complemented option byte /
		3994
		3995	/**************** Bit definition for FLASH_WRP0 register ****************/
		3996	#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
		3997	#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
		3998
		3999	/**************** Bit definition for FLASH_WRP1 register ****************/
		4000	#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
		4001	#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
		4002
		4003	/**************** Bit definition for FLASH_WRP2 register ****************/
		4004	#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
		4005	#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
		4006
		4007	/**************** Bit definition for FLASH_WRP3 register ****************/
		4008	#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
		4009	#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
		4010
		4011
		4012
		4013	/**
		4014	* @}
		4015	*/
		4016
		4017	/**
		4018	* @}
		4019	*/
		4020
		4021	/** @addtogroup Exported_macro
		4022	* @{
		4023	*/
		4024
		4025	/**************************** ADC Instances *******************************/
		4026	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
		4027
		4028	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		4029
		4030	/**************************** CEC Instances *******************************/
		4031	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
		4032
		4033	/**************************** CRC Instances *******************************/
		4034	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		4035
		4036	/**************************** DAC Instances *******************************/
		4037	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
		4038
		4039	/**************************** DMA Instances *******************************/
		4040	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		4041	((INSTANCE) == DMA1_Channel2) \|\| \
		4042	((INSTANCE) == DMA1_Channel3) \|\| \
		4043	((INSTANCE) == DMA1_Channel4) \|\| \
		4044	((INSTANCE) == DMA1_Channel5) \|\| \
		4045	((INSTANCE) == DMA1_Channel6) \|\| \
		4046	((INSTANCE) == DMA1_Channel7) \|\| \
		4047	((INSTANCE) == DMA2_Channel1) \|\| \
		4048	((INSTANCE) == DMA2_Channel2) \|\| \
		4049	((INSTANCE) == DMA2_Channel3) \|\| \
		4050	((INSTANCE) == DMA2_Channel4) \|\| \
		4051	((INSTANCE) == DMA2_Channel5))
		4052
		4053	/***************************** GPIO Instances *****************************/
		4054	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		4055	((INSTANCE) == GPIOB) \|\| \
		4056	((INSTANCE) == GPIOC) \|\| \
		4057	((INSTANCE) == GPIOD) \|\| \
		4058	((INSTANCE) == GPIOE) \|\| \
		4059	((INSTANCE) == GPIOF) \|\| \
		4060	((INSTANCE) == GPIOG))
		4061
		4062	/************************** GPIO Alternate Function Instances *************/
		4063	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		4064
		4065	/************************** GPIO Lock Instances ***************************/
		4066	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		4067
		4068	/****************************** I2C Instances *****************************/
		4069	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		4070	((INSTANCE) == I2C2))
		4071
		4072	/**************************** IWDG Instances ******************************/
		4073	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		4074
		4075	/****************************** SPI Instances *****************************/
		4076	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		4077	((INSTANCE) == SPI2) \|\| \
		4078	((INSTANCE) == SPI3))
		4079
		4080	/**************************** START TIM Instances *************************/
		4081	/**************************** TIM Instances *******************************/
		4082	#define IS_TIM_INSTANCE(INSTANCE)\
		4083	(((INSTANCE) == TIM1) \|\| \
		4084	((INSTANCE) == TIM2) \|\| \
		4085	((INSTANCE) == TIM3) \|\| \
		4086	((INSTANCE) == TIM4) \|\| \
		4087	((INSTANCE) == TIM5) \|\| \
		4088	((INSTANCE) == TIM6) \|\| \
		4089	((INSTANCE) == TIM7) \|\| \
		4090	((INSTANCE) == TIM12) \|\| \
		4091	((INSTANCE) == TIM13) \|\| \
		4092	((INSTANCE) == TIM14) \|\| \
		4093	((INSTANCE) == TIM15) \|\| \
		4094	((INSTANCE) == TIM16) \|\| \
		4095	((INSTANCE) == TIM17))
		4096
		4097	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
		4098	(((INSTANCE) == TIM1) \|\| \
		4099	((INSTANCE) == TIM2) \|\| \
		4100	((INSTANCE) == TIM3) \|\| \
		4101	((INSTANCE) == TIM4) \|\| \
		4102	((INSTANCE) == TIM5) \|\| \
		4103	((INSTANCE) == TIM12) \|\| \
		4104	((INSTANCE) == TIM13) \|\| \
		4105	((INSTANCE) == TIM14) \|\| \
		4106	((INSTANCE) == TIM15) \|\| \
		4107	((INSTANCE) == TIM16) \|\| \
		4108	((INSTANCE) == TIM17))
		4109
		4110	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
		4111	(((INSTANCE) == TIM1) \|\| \
		4112	((INSTANCE) == TIM2) \|\| \
		4113	((INSTANCE) == TIM3) \|\| \
		4114	((INSTANCE) == TIM4) \|\| \
		4115	((INSTANCE) == TIM5) \|\| \
		4116	((INSTANCE) == TIM12) \|\| \
		4117	((INSTANCE) == TIM15))
		4118
		4119	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
		4120	(((INSTANCE) == TIM1) \|\| \
		4121	((INSTANCE) == TIM2) \|\| \
		4122	((INSTANCE) == TIM3) \|\| \
		4123	((INSTANCE) == TIM4) \|\| \
		4124	((INSTANCE) == TIM5))
		4125
		4126	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
		4127	(((INSTANCE) == TIM1) \|\| \
		4128	((INSTANCE) == TIM2) \|\| \
		4129	((INSTANCE) == TIM3) \|\| \
		4130	((INSTANCE) == TIM4) \|\| \
		4131	((INSTANCE) == TIM5))
		4132
		4133	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
		4134	(((INSTANCE) == TIM1) \|\| \
		4135	((INSTANCE) == TIM2) \|\| \
		4136	((INSTANCE) == TIM3) \|\| \
		4137	((INSTANCE) == TIM4) \|\| \
		4138	((INSTANCE) == TIM5))
		4139
		4140	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
		4141	(((INSTANCE) == TIM1) \|\| \
		4142	((INSTANCE) == TIM2) \|\| \
		4143	((INSTANCE) == TIM3) \|\| \
		4144	((INSTANCE) == TIM4) \|\| \
		4145	((INSTANCE) == TIM5))
		4146
		4147	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
		4148	(((INSTANCE) == TIM1) \|\| \
		4149	((INSTANCE) == TIM2) \|\| \
		4150	((INSTANCE) == TIM3) \|\| \
		4151	((INSTANCE) == TIM4) \|\| \
		4152	((INSTANCE) == TIM5) \|\| \
		4153	((INSTANCE) == TIM12) \|\| \
		4154	((INSTANCE) == TIM15))
		4155
		4156	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
		4157	(((INSTANCE) == TIM1) \|\| \
		4158	((INSTANCE) == TIM2) \|\| \
		4159	((INSTANCE) == TIM3) \|\| \
		4160	((INSTANCE) == TIM4) \|\| \
		4161	((INSTANCE) == TIM5) \|\| \
		4162	((INSTANCE) == TIM12) \|\| \
		4163	((INSTANCE) == TIM15))
		4164
		4165	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
		4166	(((INSTANCE) == TIM1) \|\| \
		4167	((INSTANCE) == TIM2) \|\| \
		4168	((INSTANCE) == TIM3) \|\| \
		4169	((INSTANCE) == TIM4) \|\| \
		4170	((INSTANCE) == TIM5))
		4171
		4172	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
		4173	(((INSTANCE) == TIM1) \|\| \
		4174	((INSTANCE) == TIM2) \|\| \
		4175	((INSTANCE) == TIM3) \|\| \
		4176	((INSTANCE) == TIM4) \|\| \
		4177	((INSTANCE) == TIM5))
		4178
		4179	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
		4180	(((INSTANCE) == TIM1) \|\| \
		4181	((INSTANCE) == TIM2) \|\| \
		4182	((INSTANCE) == TIM3) \|\| \
		4183	((INSTANCE) == TIM4) \|\| \
		4184	((INSTANCE) == TIM5))
		4185
		4186	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
		4187	(((INSTANCE) == TIM1) \|\| \
		4188	((INSTANCE) == TIM2) \|\| \
		4189	((INSTANCE) == TIM3) \|\| \
		4190	((INSTANCE) == TIM4) \|\| \
		4191	((INSTANCE) == TIM5) \|\| \
		4192	((INSTANCE) == TIM6) \|\| \
		4193	((INSTANCE) == TIM7) \|\| \
		4194	((INSTANCE) == TIM12) \|\| \
		4195	((INSTANCE) == TIM15))
		4196
		4197	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
		4198	(((INSTANCE) == TIM1) \|\| \
		4199	((INSTANCE) == TIM2) \|\| \
		4200	((INSTANCE) == TIM3) \|\| \
		4201	((INSTANCE) == TIM4) \|\| \
		4202	((INSTANCE) == TIM5) \|\| \
		4203	((INSTANCE) == TIM12) \|\| \
		4204	((INSTANCE) == TIM15))
		4205
		4206	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
		4207	(((INSTANCE) == TIM1) \|\| \
		4208	((INSTANCE) == TIM2) \|\| \
		4209	((INSTANCE) == TIM3) \|\| \
		4210	((INSTANCE) == TIM4) \|\| \
		4211	((INSTANCE) == TIM5) \|\| \
		4212	((INSTANCE) == TIM15) \|\| \
		4213	((INSTANCE) == TIM16) \|\| \
		4214	((INSTANCE) == TIM17))
		4215
		4216	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
		4217	(((INSTANCE) == TIM1) \|\| \
		4218	((INSTANCE) == TIM15) \|\| \
		4219	((INSTANCE) == TIM16) \|\| \
		4220	((INSTANCE) == TIM17))
		4221
		4222	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		4223	((((INSTANCE) == TIM1) && \
		4224	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4225	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		4226	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		4227	((CHANNEL) == TIM_CHANNEL_4))) \
		4228	\|\| \
		4229	(((INSTANCE) == TIM2) && \
		4230	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4231	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		4232	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		4233	((CHANNEL) == TIM_CHANNEL_4))) \
		4234	\|\| \
		4235	(((INSTANCE) == TIM3) && \
		4236	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4237	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		4238	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		4239	((CHANNEL) == TIM_CHANNEL_4))) \
		4240	\|\| \
		4241	(((INSTANCE) == TIM4) && \
		4242	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4243	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		4244	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		4245	((CHANNEL) == TIM_CHANNEL_4))) \
		4246	\|\| \
		4247	(((INSTANCE) == TIM5) && \
		4248	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4249	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		4250	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		4251	((CHANNEL) == TIM_CHANNEL_4))) \
		4252	\|\| \
		4253	(((INSTANCE) == TIM12) && \
		4254	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4255	((CHANNEL) == TIM_CHANNEL_2))) \
		4256	\|\| \
		4257	(((INSTANCE) == TIM13) && \
		4258	(((CHANNEL) == TIM_CHANNEL_1))) \
		4259	\|\| \
		4260	(((INSTANCE) == TIM14) && \
		4261	(((CHANNEL) == TIM_CHANNEL_1))) \
		4262	\|\| \
		4263	(((INSTANCE) == TIM15) && \
		4264	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4265	((CHANNEL) == TIM_CHANNEL_2))) \
		4266	\|\| \
		4267	(((INSTANCE) == TIM16) && \
		4268	(((CHANNEL) == TIM_CHANNEL_1))) \
		4269	\|\| \
		4270	(((INSTANCE) == TIM17) && \
		4271	(((CHANNEL) == TIM_CHANNEL_1))))
		4272
		4273	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
		4274	((((INSTANCE) == TIM1) && \
		4275	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		4276	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		4277	((CHANNEL) == TIM_CHANNEL_3))) \
		4278	\|\| \
		4279	(((INSTANCE) == TIM15) && \
		4280	((CHANNEL) == TIM_CHANNEL_1)) \
		4281	\|\| \
		4282	(((INSTANCE) == TIM16) && \
		4283	((CHANNEL) == TIM_CHANNEL_1)) \
		4284	\|\| \
		4285	(((INSTANCE) == TIM17) && \
		4286	((CHANNEL) == TIM_CHANNEL_1)))
		4287
		4288	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
		4289	(((INSTANCE) == TIM1) \|\| \
		4290	((INSTANCE) == TIM2) \|\| \
		4291	((INSTANCE) == TIM3) \|\| \
		4292	((INSTANCE) == TIM4) \|\| \
		4293	((INSTANCE) == TIM5))
		4294
		4295	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
		4296	(((INSTANCE) == TIM1) \|\| \
		4297	((INSTANCE) == TIM15) \|\| \
		4298	((INSTANCE) == TIM16) \|\| \
		4299	((INSTANCE) == TIM17))
		4300
		4301	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
		4302	(((INSTANCE) == TIM1) \|\| \
		4303	((INSTANCE) == TIM2) \|\| \
		4304	((INSTANCE) == TIM3) \|\| \
		4305	((INSTANCE) == TIM4) \|\| \
		4306	((INSTANCE) == TIM5) \|\| \
		4307	((INSTANCE) == TIM12) \|\| \
		4308	((INSTANCE) == TIM13) \|\| \
		4309	((INSTANCE) == TIM14) \|\| \
		4310	((INSTANCE) == TIM15) \|\| \
		4311	((INSTANCE) == TIM16) \|\| \
		4312	((INSTANCE) == TIM17))
		4313
		4314	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
		4315	(((INSTANCE) == TIM1) \|\| \
		4316	((INSTANCE) == TIM2) \|\| \
		4317	((INSTANCE) == TIM3) \|\| \
		4318	((INSTANCE) == TIM4) \|\| \
		4319	((INSTANCE) == TIM5) \|\| \
		4320	((INSTANCE) == TIM6) \|\| \
		4321	((INSTANCE) == TIM7) \|\| \
		4322	((INSTANCE) == TIM15) \|\| \
		4323	((INSTANCE) == TIM16) \|\| \
		4324	((INSTANCE) == TIM17))
		4325
		4326	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
		4327	(((INSTANCE) == TIM1) \|\| \
		4328	((INSTANCE) == TIM2) \|\| \
		4329	((INSTANCE) == TIM3) \|\| \
		4330	((INSTANCE) == TIM4) \|\| \
		4331	((INSTANCE) == TIM5) \|\| \
		4332	((INSTANCE) == TIM15) \|\| \
		4333	((INSTANCE) == TIM16) \|\| \
		4334	((INSTANCE) == TIM17))
		4335
		4336	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
		4337	(((INSTANCE) == TIM1) \|\| \
		4338	((INSTANCE) == TIM15) \|\| \
		4339	((INSTANCE) == TIM16) \|\| \
		4340	((INSTANCE) == TIM17))
		4341
		4342	/**************************** END TIM Instances ***************************/
		4343
		4344
		4345	/****************** USART Instances : Synchronous mode ********************/
		4346	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4347	((INSTANCE) == USART2) \|\| \
		4348	((INSTANCE) == USART3))
		4349
		4350	/****************** UART Instances : Asynchronous mode ********************/
		4351	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4352	((INSTANCE) == USART2) \|\| \
		4353	((INSTANCE) == USART3) \|\| \
		4354	((INSTANCE) == UART4) \|\| \
		4355	((INSTANCE) == UART5))
		4356
		4357	/****************** UART Instances : Half-Duplex mode ********************/
		4358	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4359	((INSTANCE) == USART2) \|\| \
		4360	((INSTANCE) == USART3) \|\| \
		4361	((INSTANCE) == UART4) \|\| \
		4362	((INSTANCE) == UART5))
		4363
		4364	/****************** UART Instances : LIN mode ********************/
		4365	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4366	((INSTANCE) == USART2) \|\| \
		4367	((INSTANCE) == USART3) \|\| \
		4368	((INSTANCE) == UART4) \|\| \
		4369	((INSTANCE) == UART5))
		4370
		4371	/**************** UART Instances : Hardware Flow control ******************/
		4372	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4373	((INSTANCE) == USART2) \|\| \
		4374	((INSTANCE) == USART3))
		4375
		4376	/******************* UART Instances : Smard card mode *********************/
		4377	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4378	((INSTANCE) == USART2) \|\| \
		4379	((INSTANCE) == USART3))
		4380
		4381	/********************* UART Instances : IRDA mode *************************/
		4382	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4383	((INSTANCE) == USART2) \|\| \
		4384	((INSTANCE) == USART3) \|\| \
		4385	((INSTANCE) == UART4) \|\| \
		4386	((INSTANCE) == UART5))
		4387
		4388	/*************** UART Instances : Multi-Processor mode ********************/
		4389	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4390	((INSTANCE) == USART2) \|\| \
		4391	((INSTANCE) == USART3) \|\| \
		4392	((INSTANCE) == UART4) \|\| \
		4393	((INSTANCE) == UART5))
		4394
		4395	/*************** UART Instances : DMA mode available ********************/
		4396	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		4397	((INSTANCE) == USART2) \|\| \
		4398	((INSTANCE) == USART3) \|\| \
		4399	((INSTANCE) == UART4) \|\| \
		4400	((INSTANCE) == UART5))
		4401
		4402	/**************************** RTC Instances *******************************/
		4403	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		4404
		4405	/************************** WWDG Instances ***************************/
		4406	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		4407
		4408
		4409
		4410
		4411
		4412	/**
		4413	* @}
		4414	*/
		4415	/******************************************************************************/
		4416	/* For a painless codes migration between the STM32F1xx device product */
		4417	/* lines, the aliases defined below are put in place to overcome the */
		4418	/* differences in the interrupt handlers and IRQn definitions. */
		4419	/* No need to update developed interrupt code when moving across */
		4420	/* product lines within the same STM32F1 Family */
		4421	/******************************************************************************/
		4422
		4423	/* Aliases for __IRQn */
		4424	#define ADC1_2_IRQn ADC1_IRQn
		4425	#define USBWakeUp_IRQn CEC_IRQn
		4426	#define OTG_FS_WKUP_IRQn CEC_IRQn
		4427	#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
		4428	#define TIM8_BRK_IRQn TIM12_IRQn
		4429	#define TIM8_UP_IRQn TIM13_IRQn
		4430	#define TIM8_UP_TIM13_IRQn TIM13_IRQn
		4431	#define TIM8_TRG_COM_IRQn TIM14_IRQn
		4432	#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
		4433	#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
		4434	#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
		4435	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
		4436	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
		4437	#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
		4438	#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
		4439	#define TIM10_IRQn TIM1_UP_TIM16_IRQn
		4440	#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
		4441	#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
		4442	#define TIM6_IRQn TIM6_DAC_IRQn
		4443
		4444
		4445	/* Aliases for __IRQHandler */
		4446	#define ADC1_2_IRQHandler ADC1_IRQHandler
		4447	#define USBWakeUp_IRQHandler CEC_IRQHandler
		4448	#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
		4449	#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
		4450	#define TIM8_BRK_IRQHandler TIM12_IRQHandler
		4451	#define TIM8_UP_IRQHandler TIM13_IRQHandler
		4452	#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
		4453	#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
		4454	#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
		4455	#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
		4456	#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
		4457	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
		4458	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		4459	#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		4460	#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		4461	#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
		4462	#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
		4463	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
		4464	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
		4465
		4466
		4467	/**
		4468	* @}
		4469	*/
		4470
		4471	/**
		4472	* @}
		4473	*/
		4474
		4475
		4476	#ifdef __cplusplus
		4477	}
		4478	#endif /* __cplusplus */
		4479
		4480	#endif /* __STM32F100xE_H */
		4481
		4482
		4483
		4484	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h – Rev 2