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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f100xe.h
		4	* @author MCD Application Team
5	mjames	5	* @version V4.1.0
		6	* @date 29-April-2016
2	mjames	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		8	* This file contains all the peripheral register's definitions, bits
		9	* definitions and memory mapping for STM32F1xx devices.
		10	*
		11	* This file contains:
		12	* - Data structures and the address mapping for all peripherals
		13	* - Peripheral's registers declarations and bits definition
		14	* - Macros to access peripheral�s registers hardware
		15	*
		16	******************************************************************************
		17	* @attention
		18	*
5	mjames	19	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2	mjames	20	*
		21	* Redistribution and use in source and binary forms, with or without modification,
		22	* are permitted provided that the following conditions are met:
		23	* 1. Redistributions of source code must retain the above copyright notice,
		24	* this list of conditions and the following disclaimer.
		25	* 2. Redistributions in binary form must reproduce the above copyright notice,
		26	* this list of conditions and the following disclaimer in the documentation
		27	* and/or other materials provided with the distribution.
		28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		29	* may be used to endorse or promote products derived from this software
		30	* without specific prior written permission.
		31	*
		32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		42	*
		43	******************************************************************************
		44	*/
		45
		46
		47	/** @addtogroup CMSIS
		48	* @{
		49	*/
		50
		51	/** @addtogroup stm32f100xe
		52	* @{
		53	*/
		54
		55	#ifndef __STM32F100xE_H
		56	#define __STM32F100xE_H
		57
		58	#ifdef __cplusplus
		59	extern "C" {
		60	#endif
		61
		62	/** @addtogroup Configuration_section_for_CMSIS
		63	* @{
		64	*/
		65	/**
		66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		67	*/
		68	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
		69	#define __CM3_REV 0x0200 /!< Core Revision r2p0 /
		70	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
		71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
		72
		73	/**
		74	* @}
		75	*/
		76
		77	/** @addtogroup Peripheral_interrupt_number_definition
		78	* @{
		79	*/
		80
		81	/**
		82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
		83	* in @ref Library_configuration_section
		84	*/
		85
		86	/!< Interrupt Number Definition /
		87	typedef enum
		88	{
		89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
		90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
5	mjames	91	HardFault_IRQn = -13, /!< 3 Cortex-M3 Hard Fault Interrupt /
2	mjames	92	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		93	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		94	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		95	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		96	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		97	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		98	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		99
		100	/**** STM32 specific Interrupt Numbers *******************************************************/
		101	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		102	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		103	TAMPER_IRQn = 2, /!< Tamper Interrupt /
		104	RTC_IRQn = 3, /!< RTC global Interrupt /
		105	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		106	RCC_IRQn = 5, /!< RCC global Interrupt /
		107	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		108	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		109	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		110	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		111	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		112	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		113	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		114	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		115	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		116	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		117	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		118	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		119	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
		120	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		121	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
		122	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
		123	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
		124	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
		125	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		126	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		127	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		128	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		129	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		130	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		131	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		132	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		133	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		134	USART1_IRQn = 37, /!< USART1 global Interrupt /
		135	USART2_IRQn = 38, /!< USART2 global Interrupt /
		136	USART3_IRQn = 39, /!< USART3 global Interrupt /
		137	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		138	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		139	CEC_IRQn = 42, /!< HDMI-CEC Interrupt /
		140	TIM12_IRQn = 43, /!< TIM12 global Interrupt /
		141	TIM13_IRQn = 44, /!< TIM13 global Interrupt /
		142	TIM14_IRQn = 45, /!< TIM14 global Interrupt /
		143	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
		144	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
		145	UART4_IRQn = 52, /!< UART4 global Interrupt /
		146	UART5_IRQn = 53, /!< UART5 global Interrupt /
		147	TIM6_DAC_IRQn = 54, /!< TIM6 and DAC underrun Interrupt /
		148	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
		149	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
		150	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
		151	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
		152	DMA2_Channel4_5_IRQn = 59, /!< DMA2 Channel 4 and Channel 5 global Interrupt /
		153	DMA2_Channel4_IRQn = 59, /!< DMA2 Channel 4 global Interrupt /
		154	DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
		155	mapped at position 60 only if the MISC_REMAP bit in
		156	the AFIO_MAPR2 register is set) */
		157	} IRQn_Type;
		158
		159
		160	/**
		161	* @}
		162	*/
		163
		164	#include "core_cm3.h"
		165	#include "system_stm32f1xx.h"
		166	#include <stdint.h>
		167
		168	/** @addtogroup Peripheral_registers_structures
		169	* @{
		170	*/
		171
		172	/**
		173	* @brief Analog to Digital Converter
		174	*/
		175
		176	typedef struct
		177	{
		178	__IO uint32_t SR;
		179	__IO uint32_t CR1;
		180	__IO uint32_t CR2;
		181	__IO uint32_t SMPR1;
		182	__IO uint32_t SMPR2;
		183	__IO uint32_t JOFR1;
		184	__IO uint32_t JOFR2;
		185	__IO uint32_t JOFR3;
		186	__IO uint32_t JOFR4;
		187	__IO uint32_t HTR;
		188	__IO uint32_t LTR;
		189	__IO uint32_t SQR1;
		190	__IO uint32_t SQR2;
		191	__IO uint32_t SQR3;
		192	__IO uint32_t JSQR;
		193	__IO uint32_t JDR1;
		194	__IO uint32_t JDR2;
		195	__IO uint32_t JDR3;
		196	__IO uint32_t JDR4;
		197	__IO uint32_t DR;
		198	} ADC_TypeDef;
		199
5	mjames	200	typedef struct
		201	{
		202	__IO uint32_t SR; /!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address /
		203	__IO uint32_t CR1; /!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 /
		204	__IO uint32_t CR2; /!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 /
		205	uint32_t RESERVED[16];
		206	__IO uint32_t DR; /!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C /
		207	} ADC_Common_TypeDef;
		208
2	mjames	209	/**
		210	* @brief Backup Registers
		211	*/
		212
		213	typedef struct
		214	{
		215	uint32_t RESERVED0;
		216	__IO uint32_t DR1;
		217	__IO uint32_t DR2;
		218	__IO uint32_t DR3;
		219	__IO uint32_t DR4;
		220	__IO uint32_t DR5;
		221	__IO uint32_t DR6;
		222	__IO uint32_t DR7;
		223	__IO uint32_t DR8;
		224	__IO uint32_t DR9;
		225	__IO uint32_t DR10;
		226	__IO uint32_t RTCCR;
		227	__IO uint32_t CR;
		228	__IO uint32_t CSR;
		229	uint32_t RESERVED13[2];
		230	__IO uint32_t DR11;
		231	__IO uint32_t DR12;
		232	__IO uint32_t DR13;
		233	__IO uint32_t DR14;
		234	__IO uint32_t DR15;
		235	__IO uint32_t DR16;
		236	__IO uint32_t DR17;
		237	__IO uint32_t DR18;
		238	__IO uint32_t DR19;
		239	__IO uint32_t DR20;
		240	__IO uint32_t DR21;
		241	__IO uint32_t DR22;
		242	__IO uint32_t DR23;
		243	__IO uint32_t DR24;
		244	__IO uint32_t DR25;
		245	__IO uint32_t DR26;
		246	__IO uint32_t DR27;
		247	__IO uint32_t DR28;
		248	__IO uint32_t DR29;
		249	__IO uint32_t DR30;
		250	__IO uint32_t DR31;
		251	__IO uint32_t DR32;
		252	__IO uint32_t DR33;
		253	__IO uint32_t DR34;
		254	__IO uint32_t DR35;
		255	__IO uint32_t DR36;
		256	__IO uint32_t DR37;
		257	__IO uint32_t DR38;
		258	__IO uint32_t DR39;
		259	__IO uint32_t DR40;
		260	__IO uint32_t DR41;
		261	__IO uint32_t DR42;
		262	} BKP_TypeDef;
		263
		264
		265	/**
		266	* @brief Consumer Electronics Control (CEC)
		267	*/
		268	typedef struct
		269	{
		270	__IO uint32_t CFGR;
		271	__IO uint32_t OAR;
		272	__IO uint32_t PRES;
		273	__IO uint32_t ESR;
		274	__IO uint32_t CSR;
		275	__IO uint32_t TXD;
		276	__IO uint32_t RXD;
		277	} CEC_TypeDef;
		278
		279	/**
		280	* @brief CRC calculation unit
		281	*/
		282
		283	typedef struct
		284	{
		285	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		286	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		287	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		288	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		289	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		290	} CRC_TypeDef;
		291
		292	/**
		293	* @brief Digital to Analog Converter
		294	*/
		295
		296	typedef struct
		297	{
		298	__IO uint32_t CR;
		299	__IO uint32_t SWTRIGR;
		300	__IO uint32_t DHR12R1;
		301	__IO uint32_t DHR12L1;
		302	__IO uint32_t DHR8R1;
		303	__IO uint32_t DHR12R2;
		304	__IO uint32_t DHR12L2;
		305	__IO uint32_t DHR8R2;
		306	__IO uint32_t DHR12RD;
		307	__IO uint32_t DHR12LD;
		308	__IO uint32_t DHR8RD;
		309	__IO uint32_t DOR1;
		310	__IO uint32_t DOR2;
		311	__IO uint32_t SR;
		312	} DAC_TypeDef;
		313
		314	/**
		315	* @brief Debug MCU
		316	*/
		317
		318	typedef struct
		319	{
		320	__IO uint32_t IDCODE;
		321	__IO uint32_t CR;
		322	}DBGMCU_TypeDef;
		323
		324	/**
		325	* @brief DMA Controller
		326	*/
		327
		328	typedef struct
		329	{
		330	__IO uint32_t CCR;
		331	__IO uint32_t CNDTR;
		332	__IO uint32_t CPAR;
		333	__IO uint32_t CMAR;
		334	} DMA_Channel_TypeDef;
		335
		336	typedef struct
		337	{
		338	__IO uint32_t ISR;
		339	__IO uint32_t IFCR;
		340	} DMA_TypeDef;
		341
		342
		343
		344	/**
		345	* @brief External Interrupt/Event Controller
		346	*/
		347
		348	typedef struct
		349	{
		350	__IO uint32_t IMR;
		351	__IO uint32_t EMR;
		352	__IO uint32_t RTSR;
		353	__IO uint32_t FTSR;
		354	__IO uint32_t SWIER;
		355	__IO uint32_t PR;
		356	} EXTI_TypeDef;
		357
		358	/**
		359	* @brief FLASH Registers
		360	*/
		361
		362	typedef struct
		363	{
		364	__IO uint32_t ACR;
		365	__IO uint32_t KEYR;
		366	__IO uint32_t OPTKEYR;
		367	__IO uint32_t SR;
		368	__IO uint32_t CR;
		369	__IO uint32_t AR;
		370	__IO uint32_t RESERVED;
		371	__IO uint32_t OBR;
		372	__IO uint32_t WRPR;
		373	} FLASH_TypeDef;
		374
		375	/**
		376	* @brief Option Bytes Registers
		377	*/
		378
		379	typedef struct
		380	{
		381	__IO uint16_t RDP;
		382	__IO uint16_t USER;
		383	__IO uint16_t Data0;
		384	__IO uint16_t Data1;
		385	__IO uint16_t WRP0;
		386	__IO uint16_t WRP1;
		387	__IO uint16_t WRP2;
		388	__IO uint16_t WRP3;
		389	} OB_TypeDef;
		390
		391	/**
		392	* @brief Flexible Static Memory Controller
		393	*/
		394
		395	typedef struct
		396	{
		397	__IO uint32_t BTCR[8];
		398	} FSMC_Bank1_TypeDef;
		399
		400	/**
		401	* @brief Flexible Static Memory Controller Bank1E
		402	*/
		403
		404	typedef struct
		405	{
		406	__IO uint32_t BWTR[7];
		407	} FSMC_Bank1E_TypeDef;
		408
		409	/**
		410	* @brief General Purpose I/O
		411	*/
		412
		413	typedef struct
		414	{
		415	__IO uint32_t CRL;
		416	__IO uint32_t CRH;
		417	__IO uint32_t IDR;
		418	__IO uint32_t ODR;
		419	__IO uint32_t BSRR;
		420	__IO uint32_t BRR;
		421	__IO uint32_t LCKR;
		422	} GPIO_TypeDef;
		423
		424	/**
		425	* @brief Alternate Function I/O
		426	*/
		427
		428	typedef struct
		429	{
		430	__IO uint32_t EVCR;
		431	__IO uint32_t MAPR;
		432	__IO uint32_t EXTICR[4];
		433	uint32_t RESERVED0;
		434	__IO uint32_t MAPR2;
		435	} AFIO_TypeDef;
		436	/**
		437	* @brief Inter Integrated Circuit Interface
		438	*/
		439
		440	typedef struct
		441	{
		442	__IO uint32_t CR1;
		443	__IO uint32_t CR2;
		444	__IO uint32_t OAR1;
		445	__IO uint32_t OAR2;
		446	__IO uint32_t DR;
		447	__IO uint32_t SR1;
		448	__IO uint32_t SR2;
		449	__IO uint32_t CCR;
		450	__IO uint32_t TRISE;
		451	} I2C_TypeDef;
		452
		453	/**
		454	* @brief Independent WATCHDOG
		455	*/
		456
		457	typedef struct
		458	{
		459	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		460	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		461	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		462	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		463	} IWDG_TypeDef;
		464
		465	/**
		466	* @brief Power Control
		467	*/
		468
		469	typedef struct
		470	{
		471	__IO uint32_t CR;
		472	__IO uint32_t CSR;
		473	} PWR_TypeDef;
		474
		475	/**
		476	* @brief Reset and Clock Control
		477	*/
		478
		479	typedef struct
		480	{
		481	__IO uint32_t CR;
		482	__IO uint32_t CFGR;
		483	__IO uint32_t CIR;
		484	__IO uint32_t APB2RSTR;
		485	__IO uint32_t APB1RSTR;
		486	__IO uint32_t AHBENR;
		487	__IO uint32_t APB2ENR;
		488	__IO uint32_t APB1ENR;
		489	__IO uint32_t BDCR;
		490	__IO uint32_t CSR;
		491
		492
		493	uint32_t RESERVED0;
		494	__IO uint32_t CFGR2;
		495	} RCC_TypeDef;
		496
		497	/**
		498	* @brief Real-Time Clock
		499	*/
		500
		501	typedef struct
		502	{
		503	__IO uint32_t CRH;
		504	__IO uint32_t CRL;
		505	__IO uint32_t PRLH;
		506	__IO uint32_t PRLL;
		507	__IO uint32_t DIVH;
		508	__IO uint32_t DIVL;
		509	__IO uint32_t CNTH;
		510	__IO uint32_t CNTL;
		511	__IO uint32_t ALRH;
		512	__IO uint32_t ALRL;
		513	} RTC_TypeDef;
		514
		515	/**
		516	* @brief SD host Interface
		517	*/
		518
		519	typedef struct
		520	{
		521	__IO uint32_t POWER;
		522	__IO uint32_t CLKCR;
		523	__IO uint32_t ARG;
		524	__IO uint32_t CMD;
		525	__I uint32_t RESPCMD;
		526	__I uint32_t RESP1;
		527	__I uint32_t RESP2;
		528	__I uint32_t RESP3;
		529	__I uint32_t RESP4;
		530	__IO uint32_t DTIMER;
		531	__IO uint32_t DLEN;
		532	__IO uint32_t DCTRL;
		533	__I uint32_t DCOUNT;
		534	__I uint32_t STA;
		535	__IO uint32_t ICR;
		536	__IO uint32_t MASK;
		537	uint32_t RESERVED0[2];
		538	__I uint32_t FIFOCNT;
		539	uint32_t RESERVED1[13];
		540	__IO uint32_t FIFO;
		541	} SDIO_TypeDef;
		542
		543	/**
		544	* @brief Serial Peripheral Interface
		545	*/
		546
		547	typedef struct
		548	{
		549	__IO uint32_t CR1;
		550	__IO uint32_t CR2;
		551	__IO uint32_t SR;
		552	__IO uint32_t DR;
		553	__IO uint32_t CRCPR;
		554	__IO uint32_t RXCRCR;
		555	__IO uint32_t TXCRCR;
		556	} SPI_TypeDef;
		557
		558	/**
		559	* @brief TIM Timers
		560	*/
		561	typedef struct
		562	{
		563	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		564	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		565	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		566	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		567	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		568	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		569	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		570	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		571	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		572	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		573	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		574	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		575	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
		576	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		577	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		578	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		579	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		580	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
		581	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		582	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
		583	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		584	}TIM_TypeDef;
		585
		586
		587	/**
		588	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		589	*/
		590
		591	typedef struct
		592	{
		593	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		594	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		595	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		596	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		597	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		598	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		599	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		600	} USART_TypeDef;
		601
		602
		603
		604	/**
		605	* @brief Window WATCHDOG
		606	*/
		607
		608	typedef struct
		609	{
		610	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		611	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		612	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		613	} WWDG_TypeDef;
		614
		615	/**
		616	* @}
		617	*/
		618
		619	/** @addtogroup Peripheral_memory_map
		620	* @{
		621	*/
		622
		623
		624	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
		625	#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /!< FLASH END address of bank1 /
		626	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
		627	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
		628
		629	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
		630	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
		631
		632	#define FSMC_BASE ((uint32_t)0x60000000) /!< FSMC base address /
		633	#define FSMC_R_BASE ((uint32_t)0xA0000000) /!< FSMC registers base address /
		634
		635	/!< Peripheral memory map /
		636	#define APB1PERIPH_BASE PERIPH_BASE
		637	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
		638	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
		639
		640	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
		641	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
		642	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
		643	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
		644	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
		645	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
		646	#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
		647	#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
		648	#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
		649	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
		650	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
		651	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
		652	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
		653	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
		654	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
		655	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
		656	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
		657	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
		658	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
		659	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
		660	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
		661	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
		662	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
		663	#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
		664	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
		665	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
		666	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
		667	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
		668	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
		669	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
		670	#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
		671	#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
		672	#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
		673	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
		674	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
		675	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
		676	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
		677	#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
		678	#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
		679	#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
		680
		681	#define SDIO_BASE (PERIPH_BASE + 0x18000)
		682
		683	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
		684	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
		685	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
		686	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
		687	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
		688	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
		689	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
		690	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
		691	#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
		692	#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
		693	#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
		694	#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
		695	#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
		696	#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
		697	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
		698	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
		699
		700	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
5	mjames	701	#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /!< FLASH Size register base address /
		702	#define UID_BASE ((uint32_t)0x1FFFF7E8) /!< Unique device ID register base address /
2	mjames	703	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
		704
		705
		706	#define FSMC_BANK1 (FSMC_BASE) /!< FSMC Bank1 base address /
		707	#define FSMC_BANK1_1 (FSMC_BANK1) /!< FSMC Bank1_1 base address /
		708	#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /!< FSMC Bank1_2 base address /
		709	#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /!< FSMC Bank1_3 base address /
		710	#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /!< FSMC Bank1_4 base address /
		711
		712
		713	#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /!< FSMC Bank1 registers base address /
		714	#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /!< FSMC Bank1E registers base address /
		715
		716	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
		717
		718
		719
		720	/**
		721	* @}
		722	*/
		723
		724	/** @addtogroup Peripheral_declaration
		725	* @{
		726	*/
		727
		728	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
		729	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
		730	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
		731	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
		732	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
		733	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
		734	#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
		735	#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
		736	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
		737	#define RTC ((RTC_TypeDef *) RTC_BASE)
		738	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
		739	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
		740	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
		741	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
		742	#define USART2 ((USART_TypeDef *) USART2_BASE)
		743	#define USART3 ((USART_TypeDef *) USART3_BASE)
		744	#define UART4 ((USART_TypeDef *) UART4_BASE)
		745	#define UART5 ((USART_TypeDef *) UART5_BASE)
		746	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
		747	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
		748	#define BKP ((BKP_TypeDef *) BKP_BASE)
		749	#define PWR ((PWR_TypeDef *) PWR_BASE)
		750	#define DAC ((DAC_TypeDef *) DAC_BASE)
		751	#define CEC ((CEC_TypeDef *) CEC_BASE)
		752	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
		753	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
		754	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
		755	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
		756	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
		757	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
		758	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
		759	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
		760	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
		761	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
5	mjames	762	#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
2	mjames	763	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
		764	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
		765	#define USART1 ((USART_TypeDef *) USART1_BASE)
		766	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
		767	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
		768	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
		769	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
		770	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
		771	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
		772	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
		773	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
		774	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
		775	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
		776	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
		777	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
		778	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
		779	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
		780	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
		781	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
		782	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
		783	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
		784	#define RCC ((RCC_TypeDef *) RCC_BASE)
		785	#define CRC ((CRC_TypeDef *) CRC_BASE)
		786	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
		787	#define OB ((OB_TypeDef *) OB_BASE)
		788	#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
		789	#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
		790	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
		791
		792
		793	/**
		794	* @}
		795	*/
		796
		797	/** @addtogroup Exported_constants
		798	* @{
		799	*/
		800
		801	/** @addtogroup Peripheral_Registers_Bits_Definition
		802	* @{
		803	*/
		804
		805	/******************************************************************************/
		806	/* Peripheral Registers_Bits_Definition */
		807	/******************************************************************************/
		808
		809	/******************************************************************************/
		810	/* */
		811	/* CRC calculation unit (CRC) */
		812	/* */
		813	/******************************************************************************/
		814
		815	/***************** Bit definition for CRC_DR register *******************/
5	mjames	816	#define CRC_DR_DR_Pos (0U)
		817	#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /!< 0xFFFFFFFF /
		818	#define CRC_DR_DR CRC_DR_DR_Msk /!< Data register bits /
2	mjames	819
		820	/***************** Bit definition for CRC_IDR register ******************/
5	mjames	821	#define CRC_IDR_IDR_Pos (0U)
		822	#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /!< 0x000000FF /
		823	#define CRC_IDR_IDR CRC_IDR_IDR_Msk /!< General-purpose 8-bit data register bits /
2	mjames	824
		825	/****************** Bit definition for CRC_CR register ******************/
5	mjames	826	#define CRC_CR_RESET_Pos (0U)
		827	#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /!< 0x00000001 /
		828	#define CRC_CR_RESET CRC_CR_RESET_Msk /!< RESET bit /
2	mjames	829
		830	/******************************************************************************/
		831	/* */
		832	/* Power Control */
		833	/* */
		834	/******************************************************************************/
		835
		836	/****************** Bit definition for PWR_CR register ******************/
5	mjames	837	#define PWR_CR_LPDS_Pos (0U)
		838	#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /!< 0x00000001 /
		839	#define PWR_CR_LPDS PWR_CR_LPDS_Msk /!< Low-Power Deepsleep /
		840	#define PWR_CR_PDDS_Pos (1U)
		841	#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /!< 0x00000002 /
		842	#define PWR_CR_PDDS PWR_CR_PDDS_Msk /!< Power Down Deepsleep /
		843	#define PWR_CR_CWUF_Pos (2U)
		844	#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /!< 0x00000004 /
		845	#define PWR_CR_CWUF PWR_CR_CWUF_Msk /!< Clear Wakeup Flag /
		846	#define PWR_CR_CSBF_Pos (3U)
		847	#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /!< 0x00000008 /
		848	#define PWR_CR_CSBF PWR_CR_CSBF_Msk /!< Clear Standby Flag /
		849	#define PWR_CR_PVDE_Pos (4U)
		850	#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /!< 0x00000010 /
		851	#define PWR_CR_PVDE PWR_CR_PVDE_Msk /!< Power Voltage Detector Enable /
2	mjames	852
5	mjames	853	#define PWR_CR_PLS_Pos (5U)
		854	#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /!< 0x000000E0 /
		855	#define PWR_CR_PLS PWR_CR_PLS_Msk /!< PLS[2:0] bits (PVD Level Selection) /
		856	#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /!< 0x00000020 /
		857	#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /!< 0x00000040 /
		858	#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /!< 0x00000080 /
2	mjames	859
		860	/!< PVD level configuration /
5	mjames	861	#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /!< PVD level 2.2V /
		862	#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /!< PVD level 2.3V /
		863	#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /!< PVD level 2.4V /
		864	#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /!< PVD level 2.5V /
		865	#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /!< PVD level 2.6V /
		866	#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /!< PVD level 2.7V /
		867	#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /!< PVD level 2.8V /
		868	#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /!< PVD level 2.9V /
2	mjames	869
5	mjames	870	#define PWR_CR_DBP_Pos (8U)
		871	#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /!< 0x00000100 /
		872	#define PWR_CR_DBP PWR_CR_DBP_Msk /!< Disable Backup Domain write protection /
2	mjames	873
		874
		875	/***************** Bit definition for PWR_CSR register ******************/
5	mjames	876	#define PWR_CSR_WUF_Pos (0U)
		877	#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /!< 0x00000001 /
		878	#define PWR_CSR_WUF PWR_CSR_WUF_Msk /!< Wakeup Flag /
		879	#define PWR_CSR_SBF_Pos (1U)
		880	#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /!< 0x00000002 /
		881	#define PWR_CSR_SBF PWR_CSR_SBF_Msk /!< Standby Flag /
		882	#define PWR_CSR_PVDO_Pos (2U)
		883	#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /!< 0x00000004 /
		884	#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /!< PVD Output /
		885	#define PWR_CSR_EWUP_Pos (8U)
		886	#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /!< 0x00000100 /
		887	#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /!< Enable WKUP pin /
2	mjames	888
		889	/******************************************************************************/
		890	/* */
		891	/* Backup registers */
		892	/* */
		893	/******************************************************************************/
		894
		895	/***************** Bit definition for BKP_DR1 register ******************/
5	mjames	896	#define BKP_DR1_D_Pos (0U)
		897	#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /!< 0x0000FFFF /
		898	#define BKP_DR1_D BKP_DR1_D_Msk /!< Backup data /
2	mjames	899
		900	/***************** Bit definition for BKP_DR2 register ******************/
5	mjames	901	#define BKP_DR2_D_Pos (0U)
		902	#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /!< 0x0000FFFF /
		903	#define BKP_DR2_D BKP_DR2_D_Msk /!< Backup data /
2	mjames	904
		905	/***************** Bit definition for BKP_DR3 register ******************/
5	mjames	906	#define BKP_DR3_D_Pos (0U)
		907	#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /!< 0x0000FFFF /
		908	#define BKP_DR3_D BKP_DR3_D_Msk /!< Backup data /
2	mjames	909
		910	/***************** Bit definition for BKP_DR4 register ******************/
5	mjames	911	#define BKP_DR4_D_Pos (0U)
		912	#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /!< 0x0000FFFF /
		913	#define BKP_DR4_D BKP_DR4_D_Msk /!< Backup data /
2	mjames	914
		915	/***************** Bit definition for BKP_DR5 register ******************/
5	mjames	916	#define BKP_DR5_D_Pos (0U)
		917	#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /!< 0x0000FFFF /
		918	#define BKP_DR5_D BKP_DR5_D_Msk /!< Backup data /
2	mjames	919
		920	/***************** Bit definition for BKP_DR6 register ******************/
5	mjames	921	#define BKP_DR6_D_Pos (0U)
		922	#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /!< 0x0000FFFF /
		923	#define BKP_DR6_D BKP_DR6_D_Msk /!< Backup data /
2	mjames	924
		925	/***************** Bit definition for BKP_DR7 register ******************/
5	mjames	926	#define BKP_DR7_D_Pos (0U)
		927	#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /!< 0x0000FFFF /
		928	#define BKP_DR7_D BKP_DR7_D_Msk /!< Backup data /
2	mjames	929
		930	/***************** Bit definition for BKP_DR8 register ******************/
5	mjames	931	#define BKP_DR8_D_Pos (0U)
		932	#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /!< 0x0000FFFF /
		933	#define BKP_DR8_D BKP_DR8_D_Msk /!< Backup data /
2	mjames	934
		935	/***************** Bit definition for BKP_DR9 register ******************/
5	mjames	936	#define BKP_DR9_D_Pos (0U)
		937	#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /!< 0x0000FFFF /
		938	#define BKP_DR9_D BKP_DR9_D_Msk /!< Backup data /
2	mjames	939
		940	/***************** Bit definition for BKP_DR10 register *****************/
5	mjames	941	#define BKP_DR10_D_Pos (0U)
		942	#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /!< 0x0000FFFF /
		943	#define BKP_DR10_D BKP_DR10_D_Msk /!< Backup data /
2	mjames	944
		945	/***************** Bit definition for BKP_DR11 register *****************/
5	mjames	946	#define BKP_DR11_D_Pos (0U)
		947	#define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /!< 0x0000FFFF /
		948	#define BKP_DR11_D BKP_DR11_D_Msk /!< Backup data /
2	mjames	949
		950	/***************** Bit definition for BKP_DR12 register *****************/
5	mjames	951	#define BKP_DR12_D_Pos (0U)
		952	#define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /!< 0x0000FFFF /
		953	#define BKP_DR12_D BKP_DR12_D_Msk /!< Backup data /
2	mjames	954
		955	/***************** Bit definition for BKP_DR13 register *****************/
5	mjames	956	#define BKP_DR13_D_Pos (0U)
		957	#define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /!< 0x0000FFFF /
		958	#define BKP_DR13_D BKP_DR13_D_Msk /!< Backup data /
2	mjames	959
		960	/***************** Bit definition for BKP_DR14 register *****************/
5	mjames	961	#define BKP_DR14_D_Pos (0U)
		962	#define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /!< 0x0000FFFF /
		963	#define BKP_DR14_D BKP_DR14_D_Msk /!< Backup data /
2	mjames	964
		965	/***************** Bit definition for BKP_DR15 register *****************/
5	mjames	966	#define BKP_DR15_D_Pos (0U)
		967	#define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /!< 0x0000FFFF /
		968	#define BKP_DR15_D BKP_DR15_D_Msk /!< Backup data /
2	mjames	969
		970	/***************** Bit definition for BKP_DR16 register *****************/
5	mjames	971	#define BKP_DR16_D_Pos (0U)
		972	#define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /!< 0x0000FFFF /
		973	#define BKP_DR16_D BKP_DR16_D_Msk /!< Backup data /
2	mjames	974
		975	/***************** Bit definition for BKP_DR17 register *****************/
5	mjames	976	#define BKP_DR17_D_Pos (0U)
		977	#define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /!< 0x0000FFFF /
		978	#define BKP_DR17_D BKP_DR17_D_Msk /!< Backup data /
2	mjames	979
		980	/**************** Bit definition for BKP_DR18 register ******************/
5	mjames	981	#define BKP_DR18_D_Pos (0U)
		982	#define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /!< 0x0000FFFF /
		983	#define BKP_DR18_D BKP_DR18_D_Msk /!< Backup data /
2	mjames	984
		985	/***************** Bit definition for BKP_DR19 register *****************/
5	mjames	986	#define BKP_DR19_D_Pos (0U)
		987	#define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /!< 0x0000FFFF /
		988	#define BKP_DR19_D BKP_DR19_D_Msk /!< Backup data /
2	mjames	989
		990	/***************** Bit definition for BKP_DR20 register *****************/
5	mjames	991	#define BKP_DR20_D_Pos (0U)
		992	#define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /!< 0x0000FFFF /
		993	#define BKP_DR20_D BKP_DR20_D_Msk /!< Backup data /
2	mjames	994
		995	/***************** Bit definition for BKP_DR21 register *****************/
5	mjames	996	#define BKP_DR21_D_Pos (0U)
		997	#define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /!< 0x0000FFFF /
		998	#define BKP_DR21_D BKP_DR21_D_Msk /!< Backup data /
2	mjames	999
		1000	/***************** Bit definition for BKP_DR22 register *****************/
5	mjames	1001	#define BKP_DR22_D_Pos (0U)
		1002	#define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /!< 0x0000FFFF /
		1003	#define BKP_DR22_D BKP_DR22_D_Msk /!< Backup data /
2	mjames	1004
		1005	/***************** Bit definition for BKP_DR23 register *****************/
5	mjames	1006	#define BKP_DR23_D_Pos (0U)
		1007	#define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /!< 0x0000FFFF /
		1008	#define BKP_DR23_D BKP_DR23_D_Msk /!< Backup data /
2	mjames	1009
		1010	/***************** Bit definition for BKP_DR24 register *****************/
5	mjames	1011	#define BKP_DR24_D_Pos (0U)
		1012	#define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /!< 0x0000FFFF /
		1013	#define BKP_DR24_D BKP_DR24_D_Msk /!< Backup data /
2	mjames	1014
		1015	/***************** Bit definition for BKP_DR25 register *****************/
5	mjames	1016	#define BKP_DR25_D_Pos (0U)
		1017	#define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /!< 0x0000FFFF /
		1018	#define BKP_DR25_D BKP_DR25_D_Msk /!< Backup data /
2	mjames	1019
		1020	/***************** Bit definition for BKP_DR26 register *****************/
5	mjames	1021	#define BKP_DR26_D_Pos (0U)
		1022	#define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /!< 0x0000FFFF /
		1023	#define BKP_DR26_D BKP_DR26_D_Msk /!< Backup data /
2	mjames	1024
		1025	/***************** Bit definition for BKP_DR27 register *****************/
5	mjames	1026	#define BKP_DR27_D_Pos (0U)
		1027	#define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /!< 0x0000FFFF /
		1028	#define BKP_DR27_D BKP_DR27_D_Msk /!< Backup data /
2	mjames	1029
		1030	/***************** Bit definition for BKP_DR28 register *****************/
5	mjames	1031	#define BKP_DR28_D_Pos (0U)
		1032	#define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /!< 0x0000FFFF /
		1033	#define BKP_DR28_D BKP_DR28_D_Msk /!< Backup data /
2	mjames	1034
		1035	/***************** Bit definition for BKP_DR29 register *****************/
5	mjames	1036	#define BKP_DR29_D_Pos (0U)
		1037	#define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /!< 0x0000FFFF /
		1038	#define BKP_DR29_D BKP_DR29_D_Msk /!< Backup data /
2	mjames	1039
		1040	/***************** Bit definition for BKP_DR30 register *****************/
5	mjames	1041	#define BKP_DR30_D_Pos (0U)
		1042	#define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /!< 0x0000FFFF /
		1043	#define BKP_DR30_D BKP_DR30_D_Msk /!< Backup data /
2	mjames	1044
		1045	/***************** Bit definition for BKP_DR31 register *****************/
5	mjames	1046	#define BKP_DR31_D_Pos (0U)
		1047	#define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /!< 0x0000FFFF /
		1048	#define BKP_DR31_D BKP_DR31_D_Msk /!< Backup data /
2	mjames	1049
		1050	/***************** Bit definition for BKP_DR32 register *****************/
5	mjames	1051	#define BKP_DR32_D_Pos (0U)
		1052	#define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /!< 0x0000FFFF /
		1053	#define BKP_DR32_D BKP_DR32_D_Msk /!< Backup data /
2	mjames	1054
		1055	/***************** Bit definition for BKP_DR33 register *****************/
5	mjames	1056	#define BKP_DR33_D_Pos (0U)
		1057	#define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /!< 0x0000FFFF /
		1058	#define BKP_DR33_D BKP_DR33_D_Msk /!< Backup data /
2	mjames	1059
		1060	/***************** Bit definition for BKP_DR34 register *****************/
5	mjames	1061	#define BKP_DR34_D_Pos (0U)
		1062	#define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /!< 0x0000FFFF /
		1063	#define BKP_DR34_D BKP_DR34_D_Msk /!< Backup data /
2	mjames	1064
		1065	/***************** Bit definition for BKP_DR35 register *****************/
5	mjames	1066	#define BKP_DR35_D_Pos (0U)
		1067	#define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /!< 0x0000FFFF /
		1068	#define BKP_DR35_D BKP_DR35_D_Msk /!< Backup data /
2	mjames	1069
		1070	/***************** Bit definition for BKP_DR36 register *****************/
5	mjames	1071	#define BKP_DR36_D_Pos (0U)
		1072	#define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /!< 0x0000FFFF /
		1073	#define BKP_DR36_D BKP_DR36_D_Msk /!< Backup data /
2	mjames	1074
		1075	/***************** Bit definition for BKP_DR37 register *****************/
5	mjames	1076	#define BKP_DR37_D_Pos (0U)
		1077	#define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /!< 0x0000FFFF /
		1078	#define BKP_DR37_D BKP_DR37_D_Msk /!< Backup data /
2	mjames	1079
		1080	/***************** Bit definition for BKP_DR38 register *****************/
5	mjames	1081	#define BKP_DR38_D_Pos (0U)
		1082	#define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /!< 0x0000FFFF /
		1083	#define BKP_DR38_D BKP_DR38_D_Msk /!< Backup data /
2	mjames	1084
		1085	/***************** Bit definition for BKP_DR39 register *****************/
5	mjames	1086	#define BKP_DR39_D_Pos (0U)
		1087	#define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /!< 0x0000FFFF /
		1088	#define BKP_DR39_D BKP_DR39_D_Msk /!< Backup data /
2	mjames	1089
		1090	/***************** Bit definition for BKP_DR40 register *****************/
5	mjames	1091	#define BKP_DR40_D_Pos (0U)
		1092	#define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /!< 0x0000FFFF /
		1093	#define BKP_DR40_D BKP_DR40_D_Msk /!< Backup data /
2	mjames	1094
		1095	/***************** Bit definition for BKP_DR41 register *****************/
5	mjames	1096	#define BKP_DR41_D_Pos (0U)
		1097	#define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /!< 0x0000FFFF /
		1098	#define BKP_DR41_D BKP_DR41_D_Msk /!< Backup data /
2	mjames	1099
		1100	/***************** Bit definition for BKP_DR42 register *****************/
5	mjames	1101	#define BKP_DR42_D_Pos (0U)
		1102	#define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /!< 0x0000FFFF /
		1103	#define BKP_DR42_D BKP_DR42_D_Msk /!< Backup data /
2	mjames	1104
		1105	#define RTC_BKP_NUMBER 42
		1106
		1107	/**************** Bit definition for BKP_RTCCR register *****************/
5	mjames	1108	#define BKP_RTCCR_CAL_Pos (0U)
		1109	#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /!< 0x0000007F /
		1110	#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /!< Calibration value /
		1111	#define BKP_RTCCR_CCO_Pos (7U)
		1112	#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /!< 0x00000080 /
		1113	#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /!< Calibration Clock Output /
		1114	#define BKP_RTCCR_ASOE_Pos (8U)
		1115	#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /!< 0x00000100 /
		1116	#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /!< Alarm or Second Output Enable /
		1117	#define BKP_RTCCR_ASOS_Pos (9U)
		1118	#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /!< 0x00000200 /
		1119	#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /!< Alarm or Second Output Selection /
2	mjames	1120
		1121	/****************** Bit definition for BKP_CR register ******************/
5	mjames	1122	#define BKP_CR_TPE_Pos (0U)
		1123	#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /!< 0x00000001 /
		1124	#define BKP_CR_TPE BKP_CR_TPE_Msk /!< TAMPER pin enable /
		1125	#define BKP_CR_TPAL_Pos (1U)
		1126	#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /!< 0x00000002 /
		1127	#define BKP_CR_TPAL BKP_CR_TPAL_Msk /!< TAMPER pin active level /
2	mjames	1128
		1129	/***************** Bit definition for BKP_CSR register ******************/
5	mjames	1130	#define BKP_CSR_CTE_Pos (0U)
		1131	#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /!< 0x00000001 /
		1132	#define BKP_CSR_CTE BKP_CSR_CTE_Msk /!< Clear Tamper event /
		1133	#define BKP_CSR_CTI_Pos (1U)
		1134	#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /!< 0x00000002 /
		1135	#define BKP_CSR_CTI BKP_CSR_CTI_Msk /!< Clear Tamper Interrupt /
		1136	#define BKP_CSR_TPIE_Pos (2U)
		1137	#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /!< 0x00000004 /
		1138	#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /!< TAMPER Pin interrupt enable /
		1139	#define BKP_CSR_TEF_Pos (8U)
		1140	#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /!< 0x00000100 /
		1141	#define BKP_CSR_TEF BKP_CSR_TEF_Msk /!< Tamper Event Flag /
		1142	#define BKP_CSR_TIF_Pos (9U)
		1143	#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /!< 0x00000200 /
		1144	#define BKP_CSR_TIF BKP_CSR_TIF_Msk /!< Tamper Interrupt Flag /
2	mjames	1145
		1146	/******************************************************************************/
		1147	/* */
		1148	/* Reset and Clock Control */
		1149	/* */
		1150	/******************************************************************************/
		1151
		1152	/****************** Bit definition for RCC_CR register ******************/
5	mjames	1153	#define RCC_CR_HSION_Pos (0U)
		1154	#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /!< 0x00000001 /
		1155	#define RCC_CR_HSION RCC_CR_HSION_Msk /!< Internal High Speed clock enable /
		1156	#define RCC_CR_HSIRDY_Pos (1U)
		1157	#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /!< 0x00000002 /
		1158	#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /!< Internal High Speed clock ready flag /
		1159	#define RCC_CR_HSITRIM_Pos (3U)
		1160	#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /!< 0x000000F8 /
		1161	#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /!< Internal High Speed clock trimming /
		1162	#define RCC_CR_HSICAL_Pos (8U)
		1163	#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /!< 0x0000FF00 /
		1164	#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /!< Internal High Speed clock Calibration /
		1165	#define RCC_CR_HSEON_Pos (16U)
		1166	#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /!< 0x00010000 /
		1167	#define RCC_CR_HSEON RCC_CR_HSEON_Msk /!< External High Speed clock enable /
		1168	#define RCC_CR_HSERDY_Pos (17U)
		1169	#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /!< 0x00020000 /
		1170	#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /!< External High Speed clock ready flag /
		1171	#define RCC_CR_HSEBYP_Pos (18U)
		1172	#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /!< 0x00040000 /
		1173	#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /!< External High Speed clock Bypass /
		1174	#define RCC_CR_CSSON_Pos (19U)
		1175	#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /!< 0x00080000 /
		1176	#define RCC_CR_CSSON RCC_CR_CSSON_Msk /!< Clock Security System enable /
		1177	#define RCC_CR_PLLON_Pos (24U)
		1178	#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /!< 0x01000000 /
		1179	#define RCC_CR_PLLON RCC_CR_PLLON_Msk /!< PLL enable /
		1180	#define RCC_CR_PLLRDY_Pos (25U)
		1181	#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /!< 0x02000000 /
		1182	#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /!< PLL clock ready flag /
2	mjames	1183
		1184
		1185	/***************** Bit definition for RCC_CFGR register *****************/
		1186	/!< SW configuration /
5	mjames	1187	#define RCC_CFGR_SW_Pos (0U)
		1188	#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /!< 0x00000003 /
		1189	#define RCC_CFGR_SW RCC_CFGR_SW_Msk /!< SW[1:0] bits (System clock Switch) /
		1190	#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /!< 0x00000001 /
		1191	#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /!< 0x00000002 /
2	mjames	1192
5	mjames	1193	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
		1194	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
		1195	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
2	mjames	1196
		1197	/!< SWS configuration /
5	mjames	1198	#define RCC_CFGR_SWS_Pos (2U)
		1199	#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /!< 0x0000000C /
		1200	#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /!< SWS[1:0] bits (System Clock Switch Status) /
		1201	#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /!< 0x00000004 /
		1202	#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /!< 0x00000008 /
2	mjames	1203
5	mjames	1204	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
		1205	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
		1206	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
2	mjames	1207
		1208	/!< HPRE configuration /
5	mjames	1209	#define RCC_CFGR_HPRE_Pos (4U)
		1210	#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /!< 0x000000F0 /
		1211	#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /!< HPRE[3:0] bits (AHB prescaler) /
		1212	#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /!< 0x00000010 /
		1213	#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /!< 0x00000020 /
		1214	#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /!< 0x00000040 /
		1215	#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /!< 0x00000080 /
2	mjames	1216
5	mjames	1217	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
		1218	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
		1219	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
		1220	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
		1221	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
		1222	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
		1223	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
		1224	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
		1225	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
2	mjames	1226
		1227	/!< PPRE1 configuration /
5	mjames	1228	#define RCC_CFGR_PPRE1_Pos (8U)
		1229	#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /!< 0x00000700 /
		1230	#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /!< PRE1[2:0] bits (APB1 prescaler) /
		1231	#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /!< 0x00000100 /
		1232	#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /!< 0x00000200 /
		1233	#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /!< 0x00000400 /
2	mjames	1234
5	mjames	1235	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		1236	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
		1237	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
		1238	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
		1239	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
2	mjames	1240
		1241	/!< PPRE2 configuration /
5	mjames	1242	#define RCC_CFGR_PPRE2_Pos (11U)
		1243	#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /!< 0x00003800 /
		1244	#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /!< PRE2[2:0] bits (APB2 prescaler) /
		1245	#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /!< 0x00000800 /
		1246	#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /!< 0x00001000 /
		1247	#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /!< 0x00002000 /
2	mjames	1248
5	mjames	1249	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		1250	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
		1251	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
		1252	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
		1253	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
2	mjames	1254
		1255	/!< ADCPPRE configuration /
5	mjames	1256	#define RCC_CFGR_ADCPRE_Pos (14U)
		1257	#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /!< 0x0000C000 /
		1258	#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /!< ADCPRE[1:0] bits (ADC prescaler) /
		1259	#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /!< 0x00004000 /
		1260	#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /!< 0x00008000 /
2	mjames	1261
5	mjames	1262	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
		1263	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
		1264	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
		1265	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
2	mjames	1266
5	mjames	1267	#define RCC_CFGR_PLLSRC_Pos (16U)
		1268	#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /!< 0x00010000 /
		1269	#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /!< PLL entry clock source /
2	mjames	1270
5	mjames	1271	#define RCC_CFGR_PLLXTPRE_Pos (17U)
		1272	#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /!< 0x00020000 /
		1273	#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /!< HSE divider for PLL entry /
2	mjames	1274
		1275	/!< PLLMUL configuration /
5	mjames	1276	#define RCC_CFGR_PLLMULL_Pos (18U)
		1277	#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /!< 0x003C0000 /
		1278	#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /!< PLLMUL[3:0] bits (PLL multiplication factor) /
		1279	#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /!< 0x00040000 /
		1280	#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /!< 0x00080000 /
		1281	#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /!< 0x00100000 /
		1282	#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /!< 0x00200000 /
2	mjames	1283
5	mjames	1284	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
		1285	#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
2	mjames	1286
5	mjames	1287	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
		1288	#define RCC_CFGR_PLLMULL3_Pos (18U)
		1289	#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /!< 0x00040000 /
		1290	#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /!< PLL input clock3 */
		1291	#define RCC_CFGR_PLLMULL4_Pos (19U)
		1292	#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /!< 0x00080000 /
		1293	#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /!< PLL input clock4 */
		1294	#define RCC_CFGR_PLLMULL5_Pos (18U)
		1295	#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /!< 0x000C0000 /
		1296	#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /!< PLL input clock5 */
		1297	#define RCC_CFGR_PLLMULL6_Pos (20U)
		1298	#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /!< 0x00100000 /
		1299	#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /!< PLL input clock6 */
		1300	#define RCC_CFGR_PLLMULL7_Pos (18U)
		1301	#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /!< 0x00140000 /
		1302	#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /!< PLL input clock7 */
		1303	#define RCC_CFGR_PLLMULL8_Pos (19U)
		1304	#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /!< 0x00180000 /
		1305	#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /!< PLL input clock8 */
		1306	#define RCC_CFGR_PLLMULL9_Pos (18U)
		1307	#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /!< 0x001C0000 /
		1308	#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /!< PLL input clock9 */
		1309	#define RCC_CFGR_PLLMULL10_Pos (21U)
		1310	#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /!< 0x00200000 /
		1311	#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /!< PLL input clock10 /
		1312	#define RCC_CFGR_PLLMULL11_Pos (18U)
		1313	#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /!< 0x00240000 /
		1314	#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /!< PLL input clock11 */
		1315	#define RCC_CFGR_PLLMULL12_Pos (19U)
		1316	#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /!< 0x00280000 /
		1317	#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /!< PLL input clock12 */
		1318	#define RCC_CFGR_PLLMULL13_Pos (18U)
		1319	#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /!< 0x002C0000 /
		1320	#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /!< PLL input clock13 */
		1321	#define RCC_CFGR_PLLMULL14_Pos (20U)
		1322	#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /!< 0x00300000 /
		1323	#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /!< PLL input clock14 */
		1324	#define RCC_CFGR_PLLMULL15_Pos (18U)
		1325	#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /!< 0x00340000 /
		1326	#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /!< PLL input clock15 */
		1327	#define RCC_CFGR_PLLMULL16_Pos (19U)
		1328	#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /!< 0x00380000 /
		1329	#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /!< PLL input clock16 */
2	mjames	1330
		1331	/!< MCO configuration /
5	mjames	1332	#define RCC_CFGR_MCO_Pos (24U)
		1333	#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /!< 0x07000000 /
		1334	#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /!< MCO[2:0] bits (Microcontroller Clock Output) /
		1335	#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /!< 0x01000000 /
		1336	#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /!< 0x02000000 /
		1337	#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /!< 0x04000000 /
2	mjames	1338
5	mjames	1339	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1340	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
		1341	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
		1342	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
		1343	#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
2	mjames	1344
5	mjames	1345	/* Reference defines */
		1346	#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
		1347	#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
		1348	#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
		1349	#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
		1350	#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
		1351	#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
		1352	#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
		1353	#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
		1354	#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
		1355
2	mjames	1356	/!<*************** Bit definition for RCC_CIR register ******************/
5	mjames	1357	#define RCC_CIR_LSIRDYF_Pos (0U)
		1358	#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /!< 0x00000001 /
		1359	#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /!< LSI Ready Interrupt flag /
		1360	#define RCC_CIR_LSERDYF_Pos (1U)
		1361	#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /!< 0x00000002 /
		1362	#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /!< LSE Ready Interrupt flag /
		1363	#define RCC_CIR_HSIRDYF_Pos (2U)
		1364	#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /!< 0x00000004 /
		1365	#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /!< HSI Ready Interrupt flag /
		1366	#define RCC_CIR_HSERDYF_Pos (3U)
		1367	#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /!< 0x00000008 /
		1368	#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /!< HSE Ready Interrupt flag /
		1369	#define RCC_CIR_PLLRDYF_Pos (4U)
		1370	#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /!< 0x00000010 /
		1371	#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /!< PLL Ready Interrupt flag /
		1372	#define RCC_CIR_CSSF_Pos (7U)
		1373	#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /!< 0x00000080 /
		1374	#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /!< Clock Security System Interrupt flag /
		1375	#define RCC_CIR_LSIRDYIE_Pos (8U)
		1376	#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /!< 0x00000100 /
		1377	#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /!< LSI Ready Interrupt Enable /
		1378	#define RCC_CIR_LSERDYIE_Pos (9U)
		1379	#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /!< 0x00000200 /
		1380	#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /!< LSE Ready Interrupt Enable /
		1381	#define RCC_CIR_HSIRDYIE_Pos (10U)
		1382	#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /!< 0x00000400 /
		1383	#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /!< HSI Ready Interrupt Enable /
		1384	#define RCC_CIR_HSERDYIE_Pos (11U)
		1385	#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /!< 0x00000800 /
		1386	#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /!< HSE Ready Interrupt Enable /
		1387	#define RCC_CIR_PLLRDYIE_Pos (12U)
		1388	#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /!< 0x00001000 /
		1389	#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /!< PLL Ready Interrupt Enable /
		1390	#define RCC_CIR_LSIRDYC_Pos (16U)
		1391	#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /!< 0x00010000 /
		1392	#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /!< LSI Ready Interrupt Clear /
		1393	#define RCC_CIR_LSERDYC_Pos (17U)
		1394	#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /!< 0x00020000 /
		1395	#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /!< LSE Ready Interrupt Clear /
		1396	#define RCC_CIR_HSIRDYC_Pos (18U)
		1397	#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /!< 0x00040000 /
		1398	#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /!< HSI Ready Interrupt Clear /
		1399	#define RCC_CIR_HSERDYC_Pos (19U)
		1400	#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /!< 0x00080000 /
		1401	#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /!< HSE Ready Interrupt Clear /
		1402	#define RCC_CIR_PLLRDYC_Pos (20U)
		1403	#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /!< 0x00100000 /
		1404	#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /!< PLL Ready Interrupt Clear /
		1405	#define RCC_CIR_CSSC_Pos (23U)
		1406	#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /!< 0x00800000 /
		1407	#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /!< Clock Security System Interrupt Clear /
2	mjames	1408
		1409
		1410	/*************** Bit definition for RCC_APB2RSTR register ***************/
5	mjames	1411	#define RCC_APB2RSTR_AFIORST_Pos (0U)
		1412	#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /!< 0x00000001 /
		1413	#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /!< Alternate Function I/O reset /
		1414	#define RCC_APB2RSTR_IOPARST_Pos (2U)
		1415	#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /!< 0x00000004 /
		1416	#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /!< I/O port A reset /
		1417	#define RCC_APB2RSTR_IOPBRST_Pos (3U)
		1418	#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /!< 0x00000008 /
		1419	#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /!< I/O port B reset /
		1420	#define RCC_APB2RSTR_IOPCRST_Pos (4U)
		1421	#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /!< 0x00000010 /
		1422	#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /!< I/O port C reset /
		1423	#define RCC_APB2RSTR_IOPDRST_Pos (5U)
		1424	#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /!< 0x00000020 /
		1425	#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /!< I/O port D reset /
		1426	#define RCC_APB2RSTR_ADC1RST_Pos (9U)
		1427	#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /!< 0x00000200 /
		1428	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /!< ADC 1 interface reset /
2	mjames	1429
		1430
5	mjames	1431	#define RCC_APB2RSTR_TIM1RST_Pos (11U)
		1432	#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /!< 0x00000800 /
		1433	#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /!< TIM1 Timer reset /
		1434	#define RCC_APB2RSTR_SPI1RST_Pos (12U)
		1435	#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /!< 0x00001000 /
		1436	#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /!< SPI 1 reset /
		1437	#define RCC_APB2RSTR_USART1RST_Pos (14U)
		1438	#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /!< 0x00004000 /
		1439	#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /!< USART1 reset /
2	mjames	1440
5	mjames	1441	#define RCC_APB2RSTR_TIM15RST_Pos (16U)
		1442	#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /!< 0x00010000 /
		1443	#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /!< TIM15 Timer reset /
		1444	#define RCC_APB2RSTR_TIM16RST_Pos (17U)
		1445	#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /!< 0x00020000 /
		1446	#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /!< TIM16 Timer reset /
		1447	#define RCC_APB2RSTR_TIM17RST_Pos (18U)
		1448	#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /!< 0x00040000 /
		1449	#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /!< TIM17 Timer reset /
2	mjames	1450
5	mjames	1451	#define RCC_APB2RSTR_IOPERST_Pos (6U)
		1452	#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /!< 0x00000040 /
		1453	#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /!< I/O port E reset /
2	mjames	1454
		1455
5	mjames	1456	#define RCC_APB2RSTR_IOPFRST_Pos (7U)
		1457	#define RCC_APB2RSTR_IOPFRST_Msk (0x1U << RCC_APB2RSTR_IOPFRST_Pos) /!< 0x00000080 /
		1458	#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /!< I/O port F reset /
		1459	#define RCC_APB2RSTR_IOPGRST_Pos (8U)
		1460	#define RCC_APB2RSTR_IOPGRST_Msk (0x1U << RCC_APB2RSTR_IOPGRST_Pos) /!< 0x00000100 /
		1461	#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /!< I/O port G reset /
2	mjames	1462
		1463
		1464	/*************** Bit definition for RCC_APB1RSTR register ***************/
5	mjames	1465	#define RCC_APB1RSTR_TIM2RST_Pos (0U)
		1466	#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /!< 0x00000001 /
		1467	#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /!< Timer 2 reset /
		1468	#define RCC_APB1RSTR_TIM3RST_Pos (1U)
		1469	#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /!< 0x00000002 /
		1470	#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /!< Timer 3 reset /
		1471	#define RCC_APB1RSTR_WWDGRST_Pos (11U)
		1472	#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /!< 0x00000800 /
		1473	#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /!< Window Watchdog reset /
		1474	#define RCC_APB1RSTR_USART2RST_Pos (17U)
		1475	#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /!< 0x00020000 /
		1476	#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /!< USART 2 reset /
		1477	#define RCC_APB1RSTR_I2C1RST_Pos (21U)
		1478	#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /!< 0x00200000 /
		1479	#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /!< I2C 1 reset /
2	mjames	1480
		1481
5	mjames	1482	#define RCC_APB1RSTR_BKPRST_Pos (27U)
		1483	#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /!< 0x08000000 /
		1484	#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /!< Backup interface reset /
		1485	#define RCC_APB1RSTR_PWRRST_Pos (28U)
		1486	#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /!< 0x10000000 /
		1487	#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /!< Power interface reset /
2	mjames	1488
5	mjames	1489	#define RCC_APB1RSTR_TIM4RST_Pos (2U)
		1490	#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /!< 0x00000004 /
		1491	#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /!< Timer 4 reset /
		1492	#define RCC_APB1RSTR_SPI2RST_Pos (14U)
		1493	#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /!< 0x00004000 /
		1494	#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /!< SPI 2 reset /
		1495	#define RCC_APB1RSTR_USART3RST_Pos (18U)
		1496	#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /!< 0x00040000 /
		1497	#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /!< USART 3 reset /
		1498	#define RCC_APB1RSTR_I2C2RST_Pos (22U)
		1499	#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /!< 0x00400000 /
		1500	#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /!< I2C 2 reset /
2	mjames	1501
		1502
		1503
5	mjames	1504	#define RCC_APB1RSTR_TIM6RST_Pos (4U)
		1505	#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /!< 0x00000010 /
		1506	#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /!< Timer 6 reset /
		1507	#define RCC_APB1RSTR_TIM7RST_Pos (5U)
		1508	#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /!< 0x00000020 /
		1509	#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /!< Timer 7 reset /
		1510	#define RCC_APB1RSTR_CECRST_Pos (30U)
		1511	#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /!< 0x40000000 /
		1512	#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /!< CEC interface reset /
2	mjames	1513
5	mjames	1514	#define RCC_APB1RSTR_TIM5RST_Pos (3U)
		1515	#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /!< 0x00000008 /
		1516	#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /!< Timer 5 reset /
		1517	#define RCC_APB1RSTR_TIM12RST_Pos (6U)
		1518	#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /!< 0x00000040 /
		1519	#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk /!< TIM12 Timer reset /
		1520	#define RCC_APB1RSTR_TIM13RST_Pos (7U)
		1521	#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /!< 0x00000080 /
		1522	#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk /!< TIM13 Timer reset /
		1523	#define RCC_APB1RSTR_TIM14RST_Pos (8U)
		1524	#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /!< 0x00000100 /
		1525	#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /!< TIM14 Timer reset /
		1526	#define RCC_APB1RSTR_SPI3RST_Pos (15U)
		1527	#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /!< 0x00008000 /
		1528	#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /!< SPI 3 reset /
		1529	#define RCC_APB1RSTR_UART4RST_Pos (19U)
		1530	#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /!< 0x00080000 /
		1531	#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /!< UART 4 reset /
		1532	#define RCC_APB1RSTR_UART5RST_Pos (20U)
		1533	#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /!< 0x00100000 /
		1534	#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /!< UART 5 reset /
2	mjames	1535
		1536
5	mjames	1537	#define RCC_APB1RSTR_DACRST_Pos (29U)
		1538	#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /!< 0x20000000 /
		1539	#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /!< DAC interface reset /
2	mjames	1540
		1541	/**************** Bit definition for RCC_AHBENR register ****************/
5	mjames	1542	#define RCC_AHBENR_DMA1EN_Pos (0U)
		1543	#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /!< 0x00000001 /
		1544	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /!< DMA1 clock enable /
		1545	#define RCC_AHBENR_SRAMEN_Pos (2U)
		1546	#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /!< 0x00000004 /
		1547	#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /!< SRAM interface clock enable /
		1548	#define RCC_AHBENR_FLITFEN_Pos (4U)
		1549	#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /!< 0x00000010 /
		1550	#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /!< FLITF clock enable /
		1551	#define RCC_AHBENR_CRCEN_Pos (6U)
		1552	#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /!< 0x00000040 /
		1553	#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /!< CRC clock enable /
2	mjames	1554
5	mjames	1555	#define RCC_AHBENR_DMA2EN_Pos (1U)
		1556	#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /!< 0x00000002 /
		1557	#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /!< DMA2 clock enable /
2	mjames	1558
5	mjames	1559	#define RCC_AHBENR_FSMCEN_Pos (8U)
		1560	#define RCC_AHBENR_FSMCEN_Msk (0x1U << RCC_AHBENR_FSMCEN_Pos) /!< 0x00000100 /
		1561	#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /!< FSMC clock enable /
2	mjames	1562
		1563
		1564	/**************** Bit definition for RCC_APB2ENR register ***************/
5	mjames	1565	#define RCC_APB2ENR_AFIOEN_Pos (0U)
		1566	#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /!< 0x00000001 /
		1567	#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /!< Alternate Function I/O clock enable /
		1568	#define RCC_APB2ENR_IOPAEN_Pos (2U)
		1569	#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /!< 0x00000004 /
		1570	#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /!< I/O port A clock enable /
		1571	#define RCC_APB2ENR_IOPBEN_Pos (3U)
		1572	#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /!< 0x00000008 /
		1573	#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /!< I/O port B clock enable /
		1574	#define RCC_APB2ENR_IOPCEN_Pos (4U)
		1575	#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /!< 0x00000010 /
		1576	#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /!< I/O port C clock enable /
		1577	#define RCC_APB2ENR_IOPDEN_Pos (5U)
		1578	#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /!< 0x00000020 /
		1579	#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /!< I/O port D clock enable /
		1580	#define RCC_APB2ENR_ADC1EN_Pos (9U)
		1581	#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /!< 0x00000200 /
		1582	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /!< ADC 1 interface clock enable /
2	mjames	1583
		1584
5	mjames	1585	#define RCC_APB2ENR_TIM1EN_Pos (11U)
		1586	#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /!< 0x00000800 /
		1587	#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /!< TIM1 Timer clock enable /
		1588	#define RCC_APB2ENR_SPI1EN_Pos (12U)
		1589	#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /!< 0x00001000 /
		1590	#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /!< SPI 1 clock enable /
		1591	#define RCC_APB2ENR_USART1EN_Pos (14U)
		1592	#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /!< 0x00004000 /
		1593	#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /!< USART1 clock enable /
2	mjames	1594
5	mjames	1595	#define RCC_APB2ENR_TIM15EN_Pos (16U)
		1596	#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /!< 0x00010000 /
		1597	#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /!< TIM15 Timer clock enable /
		1598	#define RCC_APB2ENR_TIM16EN_Pos (17U)
		1599	#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /!< 0x00020000 /
		1600	#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /!< TIM16 Timer clock enable /
		1601	#define RCC_APB2ENR_TIM17EN_Pos (18U)
		1602	#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /!< 0x00040000 /
		1603	#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /!< TIM17 Timer clock enable /
2	mjames	1604
5	mjames	1605	#define RCC_APB2ENR_IOPEEN_Pos (6U)
		1606	#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /!< 0x00000040 /
		1607	#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /!< I/O port E clock enable /
2	mjames	1608
		1609
5	mjames	1610	#define RCC_APB2ENR_IOPFEN_Pos (7U)
		1611	#define RCC_APB2ENR_IOPFEN_Msk (0x1U << RCC_APB2ENR_IOPFEN_Pos) /!< 0x00000080 /
		1612	#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /!< I/O port F clock enable /
		1613	#define RCC_APB2ENR_IOPGEN_Pos (8U)
		1614	#define RCC_APB2ENR_IOPGEN_Msk (0x1U << RCC_APB2ENR_IOPGEN_Pos) /!< 0x00000100 /
		1615	#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /!< I/O port G clock enable /
2	mjames	1616
		1617
		1618	/*************** Bit definition for RCC_APB1ENR register ****************/
5	mjames	1619	#define RCC_APB1ENR_TIM2EN_Pos (0U)
		1620	#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /!< 0x00000001 /
		1621	#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /!< Timer 2 clock enabled/
		1622	#define RCC_APB1ENR_TIM3EN_Pos (1U)
		1623	#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /!< 0x00000002 /
		1624	#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /!< Timer 3 clock enable /
		1625	#define RCC_APB1ENR_WWDGEN_Pos (11U)
		1626	#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /!< 0x00000800 /
		1627	#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /!< Window Watchdog clock enable /
		1628	#define RCC_APB1ENR_USART2EN_Pos (17U)
		1629	#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /!< 0x00020000 /
		1630	#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /!< USART 2 clock enable /
		1631	#define RCC_APB1ENR_I2C1EN_Pos (21U)
		1632	#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /!< 0x00200000 /
		1633	#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /!< I2C 1 clock enable /
2	mjames	1634
		1635
5	mjames	1636	#define RCC_APB1ENR_BKPEN_Pos (27U)
		1637	#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /!< 0x08000000 /
		1638	#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /!< Backup interface clock enable /
		1639	#define RCC_APB1ENR_PWREN_Pos (28U)
		1640	#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /!< 0x10000000 /
		1641	#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /!< Power interface clock enable /
2	mjames	1642
5	mjames	1643	#define RCC_APB1ENR_TIM4EN_Pos (2U)
		1644	#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /!< 0x00000004 /
		1645	#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /!< Timer 4 clock enable /
		1646	#define RCC_APB1ENR_SPI2EN_Pos (14U)
		1647	#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /!< 0x00004000 /
		1648	#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /!< SPI 2 clock enable /
		1649	#define RCC_APB1ENR_USART3EN_Pos (18U)
		1650	#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /!< 0x00040000 /
		1651	#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /!< USART 3 clock enable /
		1652	#define RCC_APB1ENR_I2C2EN_Pos (22U)
		1653	#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /!< 0x00400000 /
		1654	#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /!< I2C 2 clock enable /
2	mjames	1655
		1656
		1657
5	mjames	1658	#define RCC_APB1ENR_TIM6EN_Pos (4U)
		1659	#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /!< 0x00000010 /
		1660	#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /!< Timer 6 clock enable /
		1661	#define RCC_APB1ENR_TIM7EN_Pos (5U)
		1662	#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /!< 0x00000020 /
		1663	#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /!< Timer 7 clock enable /
		1664	#define RCC_APB1ENR_CECEN_Pos (30U)
		1665	#define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /!< 0x40000000 /
		1666	#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /!< CEC interface clock enable /
2	mjames	1667
5	mjames	1668	#define RCC_APB1ENR_TIM5EN_Pos (3U)
		1669	#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /!< 0x00000008 /
		1670	#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /!< Timer 5 clock enable /
		1671	#define RCC_APB1ENR_TIM12EN_Pos (6U)
		1672	#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /!< 0x00000040 /
		1673	#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk /!< TIM12 Timer clock enable /
		1674	#define RCC_APB1ENR_TIM13EN_Pos (7U)
		1675	#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /!< 0x00000080 /
		1676	#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk /!< TIM13 Timer clock enable /
		1677	#define RCC_APB1ENR_TIM14EN_Pos (8U)
		1678	#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /!< 0x00000100 /
		1679	#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /!< TIM14 Timer clock enable /
		1680	#define RCC_APB1ENR_SPI3EN_Pos (15U)
		1681	#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /!< 0x00008000 /
		1682	#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /!< SPI 3 clock enable /
		1683	#define RCC_APB1ENR_UART4EN_Pos (19U)
		1684	#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /!< 0x00080000 /
		1685	#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /!< UART 4 clock enable /
		1686	#define RCC_APB1ENR_UART5EN_Pos (20U)
		1687	#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /!< 0x00100000 /
		1688	#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /!< UART 5 clock enable /
2	mjames	1689
		1690
5	mjames	1691	#define RCC_APB1ENR_DACEN_Pos (29U)
		1692	#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /!< 0x20000000 /
		1693	#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /!< DAC interface clock enable /
2	mjames	1694
		1695	/***************** Bit definition for RCC_BDCR register *****************/
5	mjames	1696	#define RCC_BDCR_LSEON_Pos (0U)
		1697	#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /!< 0x00000001 /
		1698	#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /!< External Low Speed oscillator enable /
		1699	#define RCC_BDCR_LSERDY_Pos (1U)
		1700	#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /!< 0x00000002 /
		1701	#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /!< External Low Speed oscillator Ready /
		1702	#define RCC_BDCR_LSEBYP_Pos (2U)
		1703	#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /!< 0x00000004 /
		1704	#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /!< External Low Speed oscillator Bypass /
2	mjames	1705
5	mjames	1706	#define RCC_BDCR_RTCSEL_Pos (8U)
		1707	#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000300 /
		1708	#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /!< RTCSEL[1:0] bits (RTC clock source selection) /
		1709	#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000100 /
		1710	#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000200 /
2	mjames	1711
		1712	/!< RTC congiguration /
5	mjames	1713	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1714	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
		1715	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
		1716	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
2	mjames	1717
5	mjames	1718	#define RCC_BDCR_RTCEN_Pos (15U)
		1719	#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /!< 0x00008000 /
		1720	#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /!< RTC clock enable /
		1721	#define RCC_BDCR_BDRST_Pos (16U)
		1722	#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /!< 0x00010000 /
		1723	#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /!< Backup domain software reset /
2	mjames	1724
		1725	/***************** Bit definition for RCC_CSR register ******************/
5	mjames	1726	#define RCC_CSR_LSION_Pos (0U)
		1727	#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /!< 0x00000001 /
		1728	#define RCC_CSR_LSION RCC_CSR_LSION_Msk /!< Internal Low Speed oscillator enable /
		1729	#define RCC_CSR_LSIRDY_Pos (1U)
		1730	#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /!< 0x00000002 /
		1731	#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /!< Internal Low Speed oscillator Ready /
		1732	#define RCC_CSR_RMVF_Pos (24U)
		1733	#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /!< 0x01000000 /
		1734	#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /!< Remove reset flag /
		1735	#define RCC_CSR_PINRSTF_Pos (26U)
		1736	#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /!< 0x04000000 /
		1737	#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /!< PIN reset flag /
		1738	#define RCC_CSR_PORRSTF_Pos (27U)
		1739	#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /!< 0x08000000 /
		1740	#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /!< POR/PDR reset flag /
		1741	#define RCC_CSR_SFTRSTF_Pos (28U)
		1742	#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /!< 0x10000000 /
		1743	#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /!< Software Reset flag /
		1744	#define RCC_CSR_IWDGRSTF_Pos (29U)
		1745	#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /!< 0x20000000 /
		1746	#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /!< Independent Watchdog reset flag /
		1747	#define RCC_CSR_WWDGRSTF_Pos (30U)
		1748	#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /!< 0x40000000 /
		1749	#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /!< Window watchdog reset flag /
		1750	#define RCC_CSR_LPWRRSTF_Pos (31U)
		1751	#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /!< 0x80000000 /
		1752	#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /!< Low-Power reset flag /
2	mjames	1753
		1754
		1755	/***************** Bit definition for RCC_CFGR2 register ****************/
		1756	/!< PREDIV1 configuration /
5	mjames	1757	#define RCC_CFGR2_PREDIV1_Pos (0U)
		1758	#define RCC_CFGR2_PREDIV1_Msk (0xFU << RCC_CFGR2_PREDIV1_Pos) /!< 0x0000000F /
		1759	#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /!< PREDIV1[3:0] bits /
		1760	#define RCC_CFGR2_PREDIV1_0 (0x1U << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000001 /
		1761	#define RCC_CFGR2_PREDIV1_1 (0x2U << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000002 /
		1762	#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000004 /
		1763	#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000008 /
2	mjames	1764
5	mjames	1765	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
		1766	#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
		1767	#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /!< 0x00000001 /
		1768	#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /!< PREDIV1 input clock divided by 2 /
		1769	#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U)
		1770	#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV3_Pos) /!< 0x00000002 /
		1771	#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /!< PREDIV1 input clock divided by 3 /
		1772	#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U)
		1773	#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV4_Pos) /!< 0x00000003 /
		1774	#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /!< PREDIV1 input clock divided by 4 /
		1775	#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U)
		1776	#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV5_Pos) /!< 0x00000004 /
		1777	#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /!< PREDIV1 input clock divided by 5 /
		1778	#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U)
		1779	#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV6_Pos) /!< 0x00000005 /
		1780	#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /!< PREDIV1 input clock divided by 6 /
		1781	#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U)
		1782	#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV7_Pos) /!< 0x00000006 /
		1783	#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /!< PREDIV1 input clock divided by 7 /
		1784	#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U)
		1785	#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV8_Pos) /!< 0x00000007 /
		1786	#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /!< PREDIV1 input clock divided by 8 /
		1787	#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U)
		1788	#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV9_Pos) /!< 0x00000008 /
		1789	#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /!< PREDIV1 input clock divided by 9 /
		1790	#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U)
		1791	#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV1_DIV10_Pos) /!< 0x00000009 /
		1792	#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /!< PREDIV1 input clock divided by 10 /
		1793	#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U)
		1794	#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV11_Pos) /!< 0x0000000A /
		1795	#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /!< PREDIV1 input clock divided by 11 /
		1796	#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U)
		1797	#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV1_DIV12_Pos) /!< 0x0000000B /
		1798	#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /!< PREDIV1 input clock divided by 12 /
		1799	#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U)
		1800	#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV13_Pos) /!< 0x0000000C /
		1801	#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /!< PREDIV1 input clock divided by 13 /
		1802	#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U)
		1803	#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV1_DIV14_Pos) /!< 0x0000000D /
		1804	#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /!< PREDIV1 input clock divided by 14 /
		1805	#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U)
		1806	#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV15_Pos) /!< 0x0000000E /
		1807	#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /!< PREDIV1 input clock divided by 15 /
		1808	#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U)
		1809	#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV1_DIV16_Pos) /!< 0x0000000F /
		1810	#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /!< PREDIV1 input clock divided by 16 /
2	mjames	1811
		1812	/******************************************************************************/
		1813	/* */
		1814	/* General Purpose and Alternate Function I/O */
		1815	/* */
		1816	/******************************************************************************/
		1817
		1818	/***************** Bit definition for GPIO_CRL register *****************/
5	mjames	1819	#define GPIO_CRL_MODE_Pos (0U)
		1820	#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /!< 0x33333333 /
		1821	#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /!< Port x mode bits /
2	mjames	1822
5	mjames	1823	#define GPIO_CRL_MODE0_Pos (0U)
		1824	#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /!< 0x00000003 /
		1825	#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
		1826	#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /!< 0x00000001 /
		1827	#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /!< 0x00000002 /
2	mjames	1828
5	mjames	1829	#define GPIO_CRL_MODE1_Pos (4U)
		1830	#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /!< 0x00000030 /
		1831	#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
		1832	#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /!< 0x00000010 /
		1833	#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /!< 0x00000020 /
2	mjames	1834
5	mjames	1835	#define GPIO_CRL_MODE2_Pos (8U)
		1836	#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /!< 0x00000300 /
		1837	#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
		1838	#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /!< 0x00000100 /
		1839	#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /!< 0x00000200 /
2	mjames	1840
5	mjames	1841	#define GPIO_CRL_MODE3_Pos (12U)
		1842	#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /!< 0x00003000 /
		1843	#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
		1844	#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /!< 0x00001000 /
		1845	#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /!< 0x00002000 /
2	mjames	1846
5	mjames	1847	#define GPIO_CRL_MODE4_Pos (16U)
		1848	#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /!< 0x00030000 /
		1849	#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
		1850	#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /!< 0x00010000 /
		1851	#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /!< 0x00020000 /
2	mjames	1852
5	mjames	1853	#define GPIO_CRL_MODE5_Pos (20U)
		1854	#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /!< 0x00300000 /
		1855	#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
		1856	#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /!< 0x00100000 /
		1857	#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /!< 0x00200000 /
2	mjames	1858
5	mjames	1859	#define GPIO_CRL_MODE6_Pos (24U)
		1860	#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /!< 0x03000000 /
		1861	#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
		1862	#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /!< 0x01000000 /
		1863	#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /!< 0x02000000 /
2	mjames	1864
5	mjames	1865	#define GPIO_CRL_MODE7_Pos (28U)
		1866	#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /!< 0x30000000 /
		1867	#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
		1868	#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /!< 0x10000000 /
		1869	#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /!< 0x20000000 /
2	mjames	1870
5	mjames	1871	#define GPIO_CRL_CNF_Pos (2U)
		1872	#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /!< 0xCCCCCCCC /
		1873	#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /!< Port x configuration bits /
2	mjames	1874
5	mjames	1875	#define GPIO_CRL_CNF0_Pos (2U)
		1876	#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /!< 0x0000000C /
		1877	#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
		1878	#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /!< 0x00000004 /
		1879	#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /!< 0x00000008 /
2	mjames	1880
5	mjames	1881	#define GPIO_CRL_CNF1_Pos (6U)
		1882	#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /!< 0x000000C0 /
		1883	#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
		1884	#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /!< 0x00000040 /
		1885	#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /!< 0x00000080 /
2	mjames	1886
5	mjames	1887	#define GPIO_CRL_CNF2_Pos (10U)
		1888	#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /!< 0x00000C00 /
		1889	#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
		1890	#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /!< 0x00000400 /
		1891	#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /!< 0x00000800 /
2	mjames	1892
5	mjames	1893	#define GPIO_CRL_CNF3_Pos (14U)
		1894	#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /!< 0x0000C000 /
		1895	#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
		1896	#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /!< 0x00004000 /
		1897	#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /!< 0x00008000 /
2	mjames	1898
5	mjames	1899	#define GPIO_CRL_CNF4_Pos (18U)
		1900	#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /!< 0x000C0000 /
		1901	#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
		1902	#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /!< 0x00040000 /
		1903	#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /!< 0x00080000 /
2	mjames	1904
5	mjames	1905	#define GPIO_CRL_CNF5_Pos (22U)
		1906	#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /!< 0x00C00000 /
		1907	#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
		1908	#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /!< 0x00400000 /
		1909	#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /!< 0x00800000 /
2	mjames	1910
5	mjames	1911	#define GPIO_CRL_CNF6_Pos (26U)
		1912	#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /!< 0x0C000000 /
		1913	#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
		1914	#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /!< 0x04000000 /
		1915	#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /!< 0x08000000 /
2	mjames	1916
5	mjames	1917	#define GPIO_CRL_CNF7_Pos (30U)
		1918	#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /!< 0xC0000000 /
		1919	#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
		1920	#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /!< 0x40000000 /
		1921	#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /!< 0x80000000 /
2	mjames	1922
		1923	/***************** Bit definition for GPIO_CRH register *****************/
5	mjames	1924	#define GPIO_CRH_MODE_Pos (0U)
		1925	#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /!< 0x33333333 /
		1926	#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /!< Port x mode bits /
2	mjames	1927
5	mjames	1928	#define GPIO_CRH_MODE8_Pos (0U)
		1929	#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /!< 0x00000003 /
		1930	#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
		1931	#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /!< 0x00000001 /
		1932	#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /!< 0x00000002 /
2	mjames	1933
5	mjames	1934	#define GPIO_CRH_MODE9_Pos (4U)
		1935	#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /!< 0x00000030 /
		1936	#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
		1937	#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /!< 0x00000010 /
		1938	#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /!< 0x00000020 /
2	mjames	1939
5	mjames	1940	#define GPIO_CRH_MODE10_Pos (8U)
		1941	#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /!< 0x00000300 /
		1942	#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
		1943	#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /!< 0x00000100 /
		1944	#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /!< 0x00000200 /
2	mjames	1945
5	mjames	1946	#define GPIO_CRH_MODE11_Pos (12U)
		1947	#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /!< 0x00003000 /
		1948	#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
		1949	#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /!< 0x00001000 /
		1950	#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /!< 0x00002000 /
2	mjames	1951
5	mjames	1952	#define GPIO_CRH_MODE12_Pos (16U)
		1953	#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /!< 0x00030000 /
		1954	#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
		1955	#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /!< 0x00010000 /
		1956	#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /!< 0x00020000 /
2	mjames	1957
5	mjames	1958	#define GPIO_CRH_MODE13_Pos (20U)
		1959	#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /!< 0x00300000 /
		1960	#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
		1961	#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /!< 0x00100000 /
		1962	#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /!< 0x00200000 /
2	mjames	1963
5	mjames	1964	#define GPIO_CRH_MODE14_Pos (24U)
		1965	#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /!< 0x03000000 /
		1966	#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
		1967	#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /!< 0x01000000 /
		1968	#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /!< 0x02000000 /
2	mjames	1969
5	mjames	1970	#define GPIO_CRH_MODE15_Pos (28U)
		1971	#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /!< 0x30000000 /
		1972	#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
		1973	#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /!< 0x10000000 /
		1974	#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /!< 0x20000000 /
2	mjames	1975
5	mjames	1976	#define GPIO_CRH_CNF_Pos (2U)
		1977	#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /!< 0xCCCCCCCC /
		1978	#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /!< Port x configuration bits /
2	mjames	1979
5	mjames	1980	#define GPIO_CRH_CNF8_Pos (2U)
		1981	#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /!< 0x0000000C /
		1982	#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
		1983	#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /!< 0x00000004 /
		1984	#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /!< 0x00000008 /
2	mjames	1985
5	mjames	1986	#define GPIO_CRH_CNF9_Pos (6U)
		1987	#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /!< 0x000000C0 /
		1988	#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
		1989	#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /!< 0x00000040 /
		1990	#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /!< 0x00000080 /
2	mjames	1991
5	mjames	1992	#define GPIO_CRH_CNF10_Pos (10U)
		1993	#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /!< 0x00000C00 /
		1994	#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
		1995	#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /!< 0x00000400 /
		1996	#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /!< 0x00000800 /
2	mjames	1997
5	mjames	1998	#define GPIO_CRH_CNF11_Pos (14U)
		1999	#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /!< 0x0000C000 /
		2000	#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
		2001	#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /!< 0x00004000 /
		2002	#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /!< 0x00008000 /
2	mjames	2003
5	mjames	2004	#define GPIO_CRH_CNF12_Pos (18U)
		2005	#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /!< 0x000C0000 /
		2006	#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
		2007	#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /!< 0x00040000 /
		2008	#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /!< 0x00080000 /
2	mjames	2009
5	mjames	2010	#define GPIO_CRH_CNF13_Pos (22U)
		2011	#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /!< 0x00C00000 /
		2012	#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
		2013	#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /!< 0x00400000 /
		2014	#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /!< 0x00800000 /
2	mjames	2015
5	mjames	2016	#define GPIO_CRH_CNF14_Pos (26U)
		2017	#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /!< 0x0C000000 /
		2018	#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
		2019	#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /!< 0x04000000 /
		2020	#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /!< 0x08000000 /
2	mjames	2021
5	mjames	2022	#define GPIO_CRH_CNF15_Pos (30U)
		2023	#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /!< 0xC0000000 /
		2024	#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
		2025	#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /!< 0x40000000 /
		2026	#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /!< 0x80000000 /
2	mjames	2027
		2028	/!<*************** Bit definition for GPIO_IDR register *****************/
5	mjames	2029	#define GPIO_IDR_IDR0_Pos (0U)
		2030	#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /!< 0x00000001 /
		2031	#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /!< Port input data, bit 0 /
		2032	#define GPIO_IDR_IDR1_Pos (1U)
		2033	#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /!< 0x00000002 /
		2034	#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /!< Port input data, bit 1 /
		2035	#define GPIO_IDR_IDR2_Pos (2U)
		2036	#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /!< 0x00000004 /
		2037	#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /!< Port input data, bit 2 /
		2038	#define GPIO_IDR_IDR3_Pos (3U)
		2039	#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /!< 0x00000008 /
		2040	#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /!< Port input data, bit 3 /
		2041	#define GPIO_IDR_IDR4_Pos (4U)
		2042	#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /!< 0x00000010 /
		2043	#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /!< Port input data, bit 4 /
		2044	#define GPIO_IDR_IDR5_Pos (5U)
		2045	#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /!< 0x00000020 /
		2046	#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /!< Port input data, bit 5 /
		2047	#define GPIO_IDR_IDR6_Pos (6U)
		2048	#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /!< 0x00000040 /
		2049	#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /!< Port input data, bit 6 /
		2050	#define GPIO_IDR_IDR7_Pos (7U)
		2051	#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /!< 0x00000080 /
		2052	#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /!< Port input data, bit 7 /
		2053	#define GPIO_IDR_IDR8_Pos (8U)
		2054	#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /!< 0x00000100 /
		2055	#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /!< Port input data, bit 8 /
		2056	#define GPIO_IDR_IDR9_Pos (9U)
		2057	#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /!< 0x00000200 /
		2058	#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /!< Port input data, bit 9 /
		2059	#define GPIO_IDR_IDR10_Pos (10U)
		2060	#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /!< 0x00000400 /
		2061	#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /!< Port input data, bit 10 /
		2062	#define GPIO_IDR_IDR11_Pos (11U)
		2063	#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /!< 0x00000800 /
		2064	#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /!< Port input data, bit 11 /
		2065	#define GPIO_IDR_IDR12_Pos (12U)
		2066	#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /!< 0x00001000 /
		2067	#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /!< Port input data, bit 12 /
		2068	#define GPIO_IDR_IDR13_Pos (13U)
		2069	#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /!< 0x00002000 /
		2070	#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /!< Port input data, bit 13 /
		2071	#define GPIO_IDR_IDR14_Pos (14U)
		2072	#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /!< 0x00004000 /
		2073	#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /!< Port input data, bit 14 /
		2074	#define GPIO_IDR_IDR15_Pos (15U)
		2075	#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /!< 0x00008000 /
		2076	#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /!< Port input data, bit 15 /
2	mjames	2077
		2078	/***************** Bit definition for GPIO_ODR register *****************/
5	mjames	2079	#define GPIO_ODR_ODR0_Pos (0U)
		2080	#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /!< 0x00000001 /
		2081	#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /!< Port output data, bit 0 /
		2082	#define GPIO_ODR_ODR1_Pos (1U)
		2083	#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /!< 0x00000002 /
		2084	#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /!< Port output data, bit 1 /
		2085	#define GPIO_ODR_ODR2_Pos (2U)
		2086	#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /!< 0x00000004 /
		2087	#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /!< Port output data, bit 2 /
		2088	#define GPIO_ODR_ODR3_Pos (3U)
		2089	#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /!< 0x00000008 /
		2090	#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /!< Port output data, bit 3 /
		2091	#define GPIO_ODR_ODR4_Pos (4U)
		2092	#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /!< 0x00000010 /
		2093	#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /!< Port output data, bit 4 /
		2094	#define GPIO_ODR_ODR5_Pos (5U)
		2095	#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /!< 0x00000020 /
		2096	#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /!< Port output data, bit 5 /
		2097	#define GPIO_ODR_ODR6_Pos (6U)
		2098	#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /!< 0x00000040 /
		2099	#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /!< Port output data, bit 6 /
		2100	#define GPIO_ODR_ODR7_Pos (7U)
		2101	#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /!< 0x00000080 /
		2102	#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /!< Port output data, bit 7 /
		2103	#define GPIO_ODR_ODR8_Pos (8U)
		2104	#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /!< 0x00000100 /
		2105	#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /!< Port output data, bit 8 /
		2106	#define GPIO_ODR_ODR9_Pos (9U)
		2107	#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /!< 0x00000200 /
		2108	#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /!< Port output data, bit 9 /
		2109	#define GPIO_ODR_ODR10_Pos (10U)
		2110	#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /!< 0x00000400 /
		2111	#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /!< Port output data, bit 10 /
		2112	#define GPIO_ODR_ODR11_Pos (11U)
		2113	#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /!< 0x00000800 /
		2114	#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /!< Port output data, bit 11 /
		2115	#define GPIO_ODR_ODR12_Pos (12U)
		2116	#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /!< 0x00001000 /
		2117	#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /!< Port output data, bit 12 /
		2118	#define GPIO_ODR_ODR13_Pos (13U)
		2119	#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /!< 0x00002000 /
		2120	#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /!< Port output data, bit 13 /
		2121	#define GPIO_ODR_ODR14_Pos (14U)
		2122	#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /!< 0x00004000 /
		2123	#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /!< Port output data, bit 14 /
		2124	#define GPIO_ODR_ODR15_Pos (15U)
		2125	#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /!< 0x00008000 /
		2126	#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /!< Port output data, bit 15 /
2	mjames	2127
		2128	/**************** Bit definition for GPIO_BSRR register *****************/
5	mjames	2129	#define GPIO_BSRR_BS0_Pos (0U)
		2130	#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /!< 0x00000001 /
		2131	#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /!< Port x Set bit 0 /
		2132	#define GPIO_BSRR_BS1_Pos (1U)
		2133	#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /!< 0x00000002 /
		2134	#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /!< Port x Set bit 1 /
		2135	#define GPIO_BSRR_BS2_Pos (2U)
		2136	#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /!< 0x00000004 /
		2137	#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /!< Port x Set bit 2 /
		2138	#define GPIO_BSRR_BS3_Pos (3U)
		2139	#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /!< 0x00000008 /
		2140	#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /!< Port x Set bit 3 /
		2141	#define GPIO_BSRR_BS4_Pos (4U)
		2142	#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /!< 0x00000010 /
		2143	#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /!< Port x Set bit 4 /
		2144	#define GPIO_BSRR_BS5_Pos (5U)
		2145	#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /!< 0x00000020 /
		2146	#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /!< Port x Set bit 5 /
		2147	#define GPIO_BSRR_BS6_Pos (6U)
		2148	#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /!< 0x00000040 /
		2149	#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /!< Port x Set bit 6 /
		2150	#define GPIO_BSRR_BS7_Pos (7U)
		2151	#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /!< 0x00000080 /
		2152	#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /!< Port x Set bit 7 /
		2153	#define GPIO_BSRR_BS8_Pos (8U)
		2154	#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /!< 0x00000100 /
		2155	#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /!< Port x Set bit 8 /
		2156	#define GPIO_BSRR_BS9_Pos (9U)
		2157	#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /!< 0x00000200 /
		2158	#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /!< Port x Set bit 9 /
		2159	#define GPIO_BSRR_BS10_Pos (10U)
		2160	#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /!< 0x00000400 /
		2161	#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /!< Port x Set bit 10 /
		2162	#define GPIO_BSRR_BS11_Pos (11U)
		2163	#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /!< 0x00000800 /
		2164	#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /!< Port x Set bit 11 /
		2165	#define GPIO_BSRR_BS12_Pos (12U)
		2166	#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /!< 0x00001000 /
		2167	#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /!< Port x Set bit 12 /
		2168	#define GPIO_BSRR_BS13_Pos (13U)
		2169	#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /!< 0x00002000 /
		2170	#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /!< Port x Set bit 13 /
		2171	#define GPIO_BSRR_BS14_Pos (14U)
		2172	#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /!< 0x00004000 /
		2173	#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /!< Port x Set bit 14 /
		2174	#define GPIO_BSRR_BS15_Pos (15U)
		2175	#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /!< 0x00008000 /
		2176	#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /!< Port x Set bit 15 /
2	mjames	2177
5	mjames	2178	#define GPIO_BSRR_BR0_Pos (16U)
		2179	#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /!< 0x00010000 /
		2180	#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /!< Port x Reset bit 0 /
		2181	#define GPIO_BSRR_BR1_Pos (17U)
		2182	#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /!< 0x00020000 /
		2183	#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /!< Port x Reset bit 1 /
		2184	#define GPIO_BSRR_BR2_Pos (18U)
		2185	#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /!< 0x00040000 /
		2186	#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /!< Port x Reset bit 2 /
		2187	#define GPIO_BSRR_BR3_Pos (19U)
		2188	#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /!< 0x00080000 /
		2189	#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /!< Port x Reset bit 3 /
		2190	#define GPIO_BSRR_BR4_Pos (20U)
		2191	#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /!< 0x00100000 /
		2192	#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /!< Port x Reset bit 4 /
		2193	#define GPIO_BSRR_BR5_Pos (21U)
		2194	#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /!< 0x00200000 /
		2195	#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /!< Port x Reset bit 5 /
		2196	#define GPIO_BSRR_BR6_Pos (22U)
		2197	#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /!< 0x00400000 /
		2198	#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /!< Port x Reset bit 6 /
		2199	#define GPIO_BSRR_BR7_Pos (23U)
		2200	#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /!< 0x00800000 /
		2201	#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /!< Port x Reset bit 7 /
		2202	#define GPIO_BSRR_BR8_Pos (24U)
		2203	#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /!< 0x01000000 /
		2204	#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /!< Port x Reset bit 8 /
		2205	#define GPIO_BSRR_BR9_Pos (25U)
		2206	#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /!< 0x02000000 /
		2207	#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /!< Port x Reset bit 9 /
		2208	#define GPIO_BSRR_BR10_Pos (26U)
		2209	#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /!< 0x04000000 /
		2210	#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /!< Port x Reset bit 10 /
		2211	#define GPIO_BSRR_BR11_Pos (27U)
		2212	#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /!< 0x08000000 /
		2213	#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /!< Port x Reset bit 11 /
		2214	#define GPIO_BSRR_BR12_Pos (28U)
		2215	#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /!< 0x10000000 /
		2216	#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /!< Port x Reset bit 12 /
		2217	#define GPIO_BSRR_BR13_Pos (29U)
		2218	#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /!< 0x20000000 /
		2219	#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /!< Port x Reset bit 13 /
		2220	#define GPIO_BSRR_BR14_Pos (30U)
		2221	#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /!< 0x40000000 /
		2222	#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /!< Port x Reset bit 14 /
		2223	#define GPIO_BSRR_BR15_Pos (31U)
		2224	#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /!< 0x80000000 /
		2225	#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /!< Port x Reset bit 15 /
2	mjames	2226
		2227	/***************** Bit definition for GPIO_BRR register *****************/
5	mjames	2228	#define GPIO_BRR_BR0_Pos (0U)
		2229	#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /!< 0x00000001 /
		2230	#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /!< Port x Reset bit 0 /
		2231	#define GPIO_BRR_BR1_Pos (1U)
		2232	#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /!< 0x00000002 /
		2233	#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /!< Port x Reset bit 1 /
		2234	#define GPIO_BRR_BR2_Pos (2U)
		2235	#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /!< 0x00000004 /
		2236	#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /!< Port x Reset bit 2 /
		2237	#define GPIO_BRR_BR3_Pos (3U)
		2238	#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /!< 0x00000008 /
		2239	#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /!< Port x Reset bit 3 /
		2240	#define GPIO_BRR_BR4_Pos (4U)
		2241	#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /!< 0x00000010 /
		2242	#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /!< Port x Reset bit 4 /
		2243	#define GPIO_BRR_BR5_Pos (5U)
		2244	#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /!< 0x00000020 /
		2245	#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /!< Port x Reset bit 5 /
		2246	#define GPIO_BRR_BR6_Pos (6U)
		2247	#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /!< 0x00000040 /
		2248	#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /!< Port x Reset bit 6 /
		2249	#define GPIO_BRR_BR7_Pos (7U)
		2250	#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /!< 0x00000080 /
		2251	#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /!< Port x Reset bit 7 /
		2252	#define GPIO_BRR_BR8_Pos (8U)
		2253	#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /!< 0x00000100 /
		2254	#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /!< Port x Reset bit 8 /
		2255	#define GPIO_BRR_BR9_Pos (9U)
		2256	#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /!< 0x00000200 /
		2257	#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /!< Port x Reset bit 9 /
		2258	#define GPIO_BRR_BR10_Pos (10U)
		2259	#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /!< 0x00000400 /
		2260	#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /!< Port x Reset bit 10 /
		2261	#define GPIO_BRR_BR11_Pos (11U)
		2262	#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /!< 0x00000800 /
		2263	#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /!< Port x Reset bit 11 /
		2264	#define GPIO_BRR_BR12_Pos (12U)
		2265	#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /!< 0x00001000 /
		2266	#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /!< Port x Reset bit 12 /
		2267	#define GPIO_BRR_BR13_Pos (13U)
		2268	#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /!< 0x00002000 /
		2269	#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /!< Port x Reset bit 13 /
		2270	#define GPIO_BRR_BR14_Pos (14U)
		2271	#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /!< 0x00004000 /
		2272	#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /!< Port x Reset bit 14 /
		2273	#define GPIO_BRR_BR15_Pos (15U)
		2274	#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /!< 0x00008000 /
		2275	#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /!< Port x Reset bit 15 /
2	mjames	2276
		2277	/**************** Bit definition for GPIO_LCKR register *****************/
5	mjames	2278	#define GPIO_LCKR_LCK0_Pos (0U)
		2279	#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /!< 0x00000001 /
		2280	#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /!< Port x Lock bit 0 /
		2281	#define GPIO_LCKR_LCK1_Pos (1U)
		2282	#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /!< 0x00000002 /
		2283	#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /!< Port x Lock bit 1 /
		2284	#define GPIO_LCKR_LCK2_Pos (2U)
		2285	#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /!< 0x00000004 /
		2286	#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /!< Port x Lock bit 2 /
		2287	#define GPIO_LCKR_LCK3_Pos (3U)
		2288	#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /!< 0x00000008 /
		2289	#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /!< Port x Lock bit 3 /
		2290	#define GPIO_LCKR_LCK4_Pos (4U)
		2291	#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /!< 0x00000010 /
		2292	#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /!< Port x Lock bit 4 /
		2293	#define GPIO_LCKR_LCK5_Pos (5U)
		2294	#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /!< 0x00000020 /
		2295	#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /!< Port x Lock bit 5 /
		2296	#define GPIO_LCKR_LCK6_Pos (6U)
		2297	#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /!< 0x00000040 /
		2298	#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /!< Port x Lock bit 6 /
		2299	#define GPIO_LCKR_LCK7_Pos (7U)
		2300	#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /!< 0x00000080 /
		2301	#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /!< Port x Lock bit 7 /
		2302	#define GPIO_LCKR_LCK8_Pos (8U)
		2303	#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /!< 0x00000100 /
		2304	#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /!< Port x Lock bit 8 /
		2305	#define GPIO_LCKR_LCK9_Pos (9U)
		2306	#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /!< 0x00000200 /
		2307	#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /!< Port x Lock bit 9 /
		2308	#define GPIO_LCKR_LCK10_Pos (10U)
		2309	#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /!< 0x00000400 /
		2310	#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /!< Port x Lock bit 10 /
		2311	#define GPIO_LCKR_LCK11_Pos (11U)
		2312	#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /!< 0x00000800 /
		2313	#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /!< Port x Lock bit 11 /
		2314	#define GPIO_LCKR_LCK12_Pos (12U)
		2315	#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /!< 0x00001000 /
		2316	#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /!< Port x Lock bit 12 /
		2317	#define GPIO_LCKR_LCK13_Pos (13U)
		2318	#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /!< 0x00002000 /
		2319	#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /!< Port x Lock bit 13 /
		2320	#define GPIO_LCKR_LCK14_Pos (14U)
		2321	#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /!< 0x00004000 /
		2322	#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /!< Port x Lock bit 14 /
		2323	#define GPIO_LCKR_LCK15_Pos (15U)
		2324	#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /!< 0x00008000 /
		2325	#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /!< Port x Lock bit 15 /
		2326	#define GPIO_LCKR_LCKK_Pos (16U)
		2327	#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /!< 0x00010000 /
		2328	#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /!< Lock key /
2	mjames	2329
		2330	/----------------------------------------------------------------------------/
		2331
		2332	/**************** Bit definition for AFIO_EVCR register *****************/
5	mjames	2333	#define AFIO_EVCR_PIN_Pos (0U)
		2334	#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /!< 0x0000000F /
		2335	#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /!< PIN[3:0] bits (Pin selection) /
		2336	#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /!< 0x00000001 /
		2337	#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /!< 0x00000002 /
		2338	#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /!< 0x00000004 /
		2339	#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /!< 0x00000008 /
2	mjames	2340
		2341	/!< PIN configuration /
5	mjames	2342	#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /!< Pin 0 selected /
		2343	#define AFIO_EVCR_PIN_PX1_Pos (0U)
		2344	#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /!< 0x00000001 /
		2345	#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /!< Pin 1 selected /
		2346	#define AFIO_EVCR_PIN_PX2_Pos (1U)
		2347	#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /!< 0x00000002 /
		2348	#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /!< Pin 2 selected /
		2349	#define AFIO_EVCR_PIN_PX3_Pos (0U)
		2350	#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /!< 0x00000003 /
		2351	#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /!< Pin 3 selected /
		2352	#define AFIO_EVCR_PIN_PX4_Pos (2U)
		2353	#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /!< 0x00000004 /
		2354	#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /!< Pin 4 selected /
		2355	#define AFIO_EVCR_PIN_PX5_Pos (0U)
		2356	#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /!< 0x00000005 /
		2357	#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /!< Pin 5 selected /
		2358	#define AFIO_EVCR_PIN_PX6_Pos (1U)
		2359	#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /!< 0x00000006 /
		2360	#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /!< Pin 6 selected /
		2361	#define AFIO_EVCR_PIN_PX7_Pos (0U)
		2362	#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /!< 0x00000007 /
		2363	#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /!< Pin 7 selected /
		2364	#define AFIO_EVCR_PIN_PX8_Pos (3U)
		2365	#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /!< 0x00000008 /
		2366	#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /!< Pin 8 selected /
		2367	#define AFIO_EVCR_PIN_PX9_Pos (0U)
		2368	#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /!< 0x00000009 /
		2369	#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /!< Pin 9 selected /
		2370	#define AFIO_EVCR_PIN_PX10_Pos (1U)
		2371	#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /!< 0x0000000A /
		2372	#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /!< Pin 10 selected /
		2373	#define AFIO_EVCR_PIN_PX11_Pos (0U)
		2374	#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /!< 0x0000000B /
		2375	#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /!< Pin 11 selected /
		2376	#define AFIO_EVCR_PIN_PX12_Pos (2U)
		2377	#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /!< 0x0000000C /
		2378	#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /!< Pin 12 selected /
		2379	#define AFIO_EVCR_PIN_PX13_Pos (0U)
		2380	#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /!< 0x0000000D /
		2381	#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /!< Pin 13 selected /
		2382	#define AFIO_EVCR_PIN_PX14_Pos (1U)
		2383	#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /!< 0x0000000E /
		2384	#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /!< Pin 14 selected /
		2385	#define AFIO_EVCR_PIN_PX15_Pos (0U)
		2386	#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /!< 0x0000000F /
		2387	#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /!< Pin 15 selected /
2	mjames	2388
5	mjames	2389	#define AFIO_EVCR_PORT_Pos (4U)
		2390	#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /!< 0x00000070 /
		2391	#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /!< PORT[2:0] bits (Port selection) /
		2392	#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /!< 0x00000010 /
		2393	#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /!< 0x00000020 /
		2394	#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /!< 0x00000040 /
2	mjames	2395
		2396	/!< PORT configuration /
5	mjames	2397	#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /!< Port A selected /
		2398	#define AFIO_EVCR_PORT_PB_Pos (4U)
		2399	#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /!< 0x00000010 /
		2400	#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /!< Port B selected /
		2401	#define AFIO_EVCR_PORT_PC_Pos (5U)
		2402	#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /!< 0x00000020 /
		2403	#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /!< Port C selected /
		2404	#define AFIO_EVCR_PORT_PD_Pos (4U)
		2405	#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /!< 0x00000030 /
		2406	#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /!< Port D selected /
		2407	#define AFIO_EVCR_PORT_PE_Pos (6U)
		2408	#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /!< 0x00000040 /
		2409	#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /!< Port E selected /
2	mjames	2410
5	mjames	2411	#define AFIO_EVCR_EVOE_Pos (7U)
		2412	#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /!< 0x00000080 /
		2413	#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /!< Event Output Enable /
2	mjames	2414
		2415	/**************** Bit definition for AFIO_MAPR register *****************/
5	mjames	2416	#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
		2417	#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /!< 0x00000001 /
		2418	#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /!< SPI1 remapping /
		2419	#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
		2420	#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /!< 0x00000002 /
		2421	#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /!< I2C1 remapping /
		2422	#define AFIO_MAPR_USART1_REMAP_Pos (2U)
		2423	#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /!< 0x00000004 /
		2424	#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /!< USART1 remapping /
		2425	#define AFIO_MAPR_USART2_REMAP_Pos (3U)
		2426	#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /!< 0x00000008 /
		2427	#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /!< USART2 remapping /
2	mjames	2428
5	mjames	2429	#define AFIO_MAPR_USART3_REMAP_Pos (4U)
		2430	#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000030 /
		2431	#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /!< USART3_REMAP[1:0] bits (USART3 remapping) /
		2432	#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000010 /
		2433	#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000020 /
2	mjames	2434
		2435	/* USART3_REMAP configuration */
5	mjames	2436	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
		2437	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
		2438	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /!< 0x00000010 /
		2439	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
		2440	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
		2441	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /!< 0x00000030 /
		2442	#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
2	mjames	2443
5	mjames	2444	#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
		2445	#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x000000C0 /
		2446	#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
		2447	#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000040 /
		2448	#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000080 /
2	mjames	2449
		2450	/!< TIM1_REMAP configuration /
5	mjames	2451	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
		2452	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
		2453	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /!< 0x00000040 /
		2454	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
		2455	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
		2456	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /!< 0x000000C0 /
		2457	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
2	mjames	2458
5	mjames	2459	#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
		2460	#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000300 /
		2461	#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
		2462	#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000100 /
		2463	#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000200 /
2	mjames	2464
		2465	/!< TIM2_REMAP configuration /
5	mjames	2466	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
		2467	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
		2468	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /!< 0x00000100 /
		2469	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
		2470	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
		2471	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /!< 0x00000200 /
		2472	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
		2473	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
		2474	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /!< 0x00000300 /
		2475	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
2	mjames	2476
5	mjames	2477	#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
		2478	#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000C00 /
		2479	#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
		2480	#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000400 /
		2481	#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000800 /
2	mjames	2482
		2483	/!< TIM3_REMAP configuration /
5	mjames	2484	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
		2485	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
		2486	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /!< 0x00000800 /
		2487	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
		2488	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
		2489	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /!< 0x00000C00 /
		2490	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
2	mjames	2491
5	mjames	2492	#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
		2493	#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /!< 0x00001000 /
		2494	#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /!< TIM4_REMAP bit (TIM4 remapping) /
2	mjames	2495
		2496
5	mjames	2497	#define AFIO_MAPR_PD01_REMAP_Pos (15U)
		2498	#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /!< 0x00008000 /
		2499	#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
		2500	#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
		2501	#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1U << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /!< 0x00010000 /
		2502	#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /!< TIM5 Channel4 Internal Remap /
2	mjames	2503
		2504	/!< SWJ_CFG configuration /
5	mjames	2505	#define AFIO_MAPR_SWJ_CFG_Pos (24U)
		2506	#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x07000000 /
		2507	#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
		2508	#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x01000000 /
		2509	#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x02000000 /
		2510	#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x04000000 /
2	mjames	2511
5	mjames	2512	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
		2513	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
		2514	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /!< 0x01000000 /
		2515	#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
		2516	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
		2517	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /!< 0x02000000 /
		2518	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /!< JTAG-DP Disabled and SW-DP Enabled /
		2519	#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
		2520	#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /!< 0x04000000 /
		2521	#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /!< JTAG-DP Disabled and SW-DP Disabled /
2	mjames	2522
		2523
		2524	/*************** Bit definition for AFIO_EXTICR1 register ***************/
5	mjames	2525	#define AFIO_EXTICR1_EXTI0_Pos (0U)
		2526	#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /!< 0x0000000F /
		2527	#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /!< EXTI 0 configuration /
		2528	#define AFIO_EXTICR1_EXTI1_Pos (4U)
		2529	#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /!< 0x000000F0 /
		2530	#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /!< EXTI 1 configuration /
		2531	#define AFIO_EXTICR1_EXTI2_Pos (8U)
		2532	#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /!< 0x00000F00 /
		2533	#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /!< EXTI 2 configuration /
		2534	#define AFIO_EXTICR1_EXTI3_Pos (12U)
		2535	#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /!< 0x0000F000 /
		2536	#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /!< EXTI 3 configuration /
2	mjames	2537
		2538	/!< EXTI0 configuration /
		2539	#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
5	mjames	2540	#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
		2541	#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /!< 0x00000001 /
		2542	#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /!< PB[0] pin /
		2543	#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
		2544	#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /!< 0x00000002 /
		2545	#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /!< PC[0] pin /
		2546	#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
		2547	#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /!< 0x00000003 /
		2548	#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /!< PD[0] pin /
		2549	#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
		2550	#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /!< 0x00000004 /
		2551	#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /!< PE[0] pin /
		2552	#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
		2553	#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /!< 0x00000005 /
		2554	#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /!< PF[0] pin /
		2555	#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
		2556	#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /!< 0x00000006 /
		2557	#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /!< PG[0] pin /
2	mjames	2558
		2559	/!< EXTI1 configuration /
		2560	#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
5	mjames	2561	#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
		2562	#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /!< 0x00000010 /
		2563	#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /!< PB[1] pin /
		2564	#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
		2565	#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /!< 0x00000020 /
		2566	#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /!< PC[1] pin /
		2567	#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
		2568	#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /!< 0x00000030 /
		2569	#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /!< PD[1] pin /
		2570	#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
		2571	#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /!< 0x00000040 /
		2572	#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /!< PE[1] pin /
		2573	#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
		2574	#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /!< 0x00000050 /
		2575	#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /!< PF[1] pin /
		2576	#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
		2577	#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /!< 0x00000060 /
		2578	#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /!< PG[1] pin /
2	mjames	2579
		2580	/!< EXTI2 configuration /
		2581	#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
5	mjames	2582	#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
		2583	#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /!< 0x00000100 /
		2584	#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /!< PB[2] pin /
		2585	#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
		2586	#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /!< 0x00000200 /
		2587	#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /!< PC[2] pin /
		2588	#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
		2589	#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /!< 0x00000300 /
		2590	#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /!< PD[2] pin /
		2591	#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
		2592	#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /!< 0x00000400 /
		2593	#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /!< PE[2] pin /
		2594	#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
		2595	#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /!< 0x00000500 /
		2596	#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /!< PF[2] pin /
		2597	#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
		2598	#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /!< 0x00000600 /
		2599	#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /!< PG[2] pin /
2	mjames	2600
		2601	/!< EXTI3 configuration /
		2602	#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
5	mjames	2603	#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
		2604	#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /!< 0x00001000 /
		2605	#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /!< PB[3] pin /
		2606	#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
		2607	#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /!< 0x00002000 /
		2608	#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /!< PC[3] pin /
		2609	#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
		2610	#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /!< 0x00003000 /
		2611	#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /!< PD[3] pin /
		2612	#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
		2613	#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /!< 0x00004000 /
		2614	#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /!< PE[3] pin /
		2615	#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
		2616	#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /!< 0x00005000 /
		2617	#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /!< PF[3] pin /
		2618	#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
		2619	#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /!< 0x00006000 /
		2620	#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /!< PG[3] pin /
2	mjames	2621
		2622	/*************** Bit definition for AFIO_EXTICR2 register ***************/
5	mjames	2623	#define AFIO_EXTICR2_EXTI4_Pos (0U)
		2624	#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /!< 0x0000000F /
		2625	#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /!< EXTI 4 configuration /
		2626	#define AFIO_EXTICR2_EXTI5_Pos (4U)
		2627	#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /!< 0x000000F0 /
		2628	#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /!< EXTI 5 configuration /
		2629	#define AFIO_EXTICR2_EXTI6_Pos (8U)
		2630	#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /!< 0x00000F00 /
		2631	#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /!< EXTI 6 configuration /
		2632	#define AFIO_EXTICR2_EXTI7_Pos (12U)
		2633	#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /!< 0x0000F000 /
		2634	#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /!< EXTI 7 configuration /
2	mjames	2635
		2636	/!< EXTI4 configuration /
		2637	#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
5	mjames	2638	#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
		2639	#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /!< 0x00000001 /
		2640	#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /!< PB[4] pin /
		2641	#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
		2642	#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /!< 0x00000002 /
		2643	#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /!< PC[4] pin /
		2644	#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
		2645	#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /!< 0x00000003 /
		2646	#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /!< PD[4] pin /
		2647	#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
		2648	#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /!< 0x00000004 /
		2649	#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /!< PE[4] pin /
		2650	#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
		2651	#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /!< 0x00000005 /
		2652	#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /!< PF[4] pin /
		2653	#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
		2654	#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /!< 0x00000006 /
		2655	#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /!< PG[4] pin /
2	mjames	2656
		2657	/* EXTI5 configuration */
		2658	#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
5	mjames	2659	#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
		2660	#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /!< 0x00000010 /
		2661	#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /!< PB[5] pin /
		2662	#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
		2663	#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /!< 0x00000020 /
		2664	#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /!< PC[5] pin /
		2665	#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
		2666	#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /!< 0x00000030 /
		2667	#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /!< PD[5] pin /
		2668	#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
		2669	#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /!< 0x00000040 /
		2670	#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /!< PE[5] pin /
		2671	#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
		2672	#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /!< 0x00000050 /
		2673	#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /!< PF[5] pin /
		2674	#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
		2675	#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /!< 0x00000060 /
		2676	#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /!< PG[5] pin /
2	mjames	2677
		2678	/!< EXTI6 configuration /
		2679	#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
5	mjames	2680	#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
		2681	#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /!< 0x00000100 /
		2682	#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /!< PB[6] pin /
		2683	#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
		2684	#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /!< 0x00000200 /
		2685	#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /!< PC[6] pin /
		2686	#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
		2687	#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /!< 0x00000300 /
		2688	#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /!< PD[6] pin /
		2689	#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
		2690	#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /!< 0x00000400 /
		2691	#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /!< PE[6] pin /
		2692	#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
		2693	#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /!< 0x00000500 /
		2694	#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /!< PF[6] pin /
		2695	#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
		2696	#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /!< 0x00000600 /
		2697	#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /!< PG[6] pin /
2	mjames	2698
		2699	/!< EXTI7 configuration /
		2700	#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
5	mjames	2701	#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
		2702	#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /!< 0x00001000 /
		2703	#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /!< PB[7] pin /
		2704	#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
		2705	#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /!< 0x00002000 /
		2706	#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /!< PC[7] pin /
		2707	#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
		2708	#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /!< 0x00003000 /
		2709	#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /!< PD[7] pin /
		2710	#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
		2711	#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /!< 0x00004000 /
		2712	#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /!< PE[7] pin /
		2713	#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
		2714	#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /!< 0x00005000 /
		2715	#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /!< PF[7] pin /
		2716	#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
		2717	#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /!< 0x00006000 /
		2718	#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /!< PG[7] pin /
2	mjames	2719
		2720	/*************** Bit definition for AFIO_EXTICR3 register ***************/
5	mjames	2721	#define AFIO_EXTICR3_EXTI8_Pos (0U)
		2722	#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /!< 0x0000000F /
		2723	#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /!< EXTI 8 configuration /
		2724	#define AFIO_EXTICR3_EXTI9_Pos (4U)
		2725	#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /!< 0x000000F0 /
		2726	#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /!< EXTI 9 configuration /
		2727	#define AFIO_EXTICR3_EXTI10_Pos (8U)
		2728	#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /!< 0x00000F00 /
		2729	#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /!< EXTI 10 configuration /
		2730	#define AFIO_EXTICR3_EXTI11_Pos (12U)
		2731	#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /!< 0x0000F000 /
		2732	#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /!< EXTI 11 configuration /
2	mjames	2733
		2734	/!< EXTI8 configuration /
		2735	#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
5	mjames	2736	#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
		2737	#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /!< 0x00000001 /
		2738	#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /!< PB[8] pin /
		2739	#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
		2740	#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /!< 0x00000002 /
		2741	#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /!< PC[8] pin /
		2742	#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
		2743	#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /!< 0x00000003 /
		2744	#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /!< PD[8] pin /
		2745	#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
		2746	#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /!< 0x00000004 /
		2747	#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /!< PE[8] pin /
		2748	#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
		2749	#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /!< 0x00000005 /
		2750	#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /!< PF[8] pin /
		2751	#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
		2752	#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /!< 0x00000006 /
		2753	#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /!< PG[8] pin /
2	mjames	2754
		2755	/!< EXTI9 configuration /
		2756	#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
5	mjames	2757	#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
		2758	#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /!< 0x00000010 /
		2759	#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /!< PB[9] pin /
		2760	#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
		2761	#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /!< 0x00000020 /
		2762	#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /!< PC[9] pin /
		2763	#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
		2764	#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /!< 0x00000030 /
		2765	#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /!< PD[9] pin /
		2766	#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
		2767	#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /!< 0x00000040 /
		2768	#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /!< PE[9] pin /
		2769	#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
		2770	#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /!< 0x00000050 /
		2771	#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /!< PF[9] pin /
		2772	#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
		2773	#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /!< 0x00000060 /
		2774	#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /!< PG[9] pin /
2	mjames	2775
		2776	/!< EXTI10 configuration /
		2777	#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
5	mjames	2778	#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
		2779	#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /!< 0x00000100 /
		2780	#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /!< PB[10] pin /
		2781	#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
		2782	#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /!< 0x00000200 /
		2783	#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /!< PC[10] pin /
		2784	#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
		2785	#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /!< 0x00000300 /
		2786	#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /!< PD[10] pin /
		2787	#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
		2788	#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /!< 0x00000400 /
		2789	#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /!< PE[10] pin /
		2790	#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
		2791	#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /!< 0x00000500 /
		2792	#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /!< PF[10] pin /
		2793	#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
		2794	#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /!< 0x00000600 /
		2795	#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /!< PG[10] pin /
2	mjames	2796
		2797	/!< EXTI11 configuration /
		2798	#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
5	mjames	2799	#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
		2800	#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /!< 0x00001000 /
		2801	#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /!< PB[11] pin /
		2802	#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
		2803	#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /!< 0x00002000 /
		2804	#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /!< PC[11] pin /
		2805	#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
		2806	#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /!< 0x00003000 /
		2807	#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /!< PD[11] pin /
		2808	#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
		2809	#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /!< 0x00004000 /
		2810	#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /!< PE[11] pin /
		2811	#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
		2812	#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /!< 0x00005000 /
		2813	#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /!< PF[11] pin /
		2814	#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
		2815	#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /!< 0x00006000 /
		2816	#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /!< PG[11] pin /
2	mjames	2817
		2818	/*************** Bit definition for AFIO_EXTICR4 register ***************/
5	mjames	2819	#define AFIO_EXTICR4_EXTI12_Pos (0U)
		2820	#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /!< 0x0000000F /
		2821	#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /!< EXTI 12 configuration /
		2822	#define AFIO_EXTICR4_EXTI13_Pos (4U)
		2823	#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /!< 0x000000F0 /
		2824	#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /!< EXTI 13 configuration /
		2825	#define AFIO_EXTICR4_EXTI14_Pos (8U)
		2826	#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /!< 0x00000F00 /
		2827	#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /!< EXTI 14 configuration /
		2828	#define AFIO_EXTICR4_EXTI15_Pos (12U)
		2829	#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /!< 0x0000F000 /
		2830	#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /!< EXTI 15 configuration /
2	mjames	2831
		2832	/* EXTI12 configuration */
		2833	#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
5	mjames	2834	#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
		2835	#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /!< 0x00000001 /
		2836	#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /!< PB[12] pin /
		2837	#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
		2838	#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /!< 0x00000002 /
		2839	#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /!< PC[12] pin /
		2840	#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
		2841	#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /!< 0x00000003 /
		2842	#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /!< PD[12] pin /
		2843	#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
		2844	#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /!< 0x00000004 /
		2845	#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /!< PE[12] pin /
		2846	#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
		2847	#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /!< 0x00000005 /
		2848	#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /!< PF[12] pin /
		2849	#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
		2850	#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /!< 0x00000006 /
		2851	#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /!< PG[12] pin /
2	mjames	2852
		2853	/* EXTI13 configuration */
		2854	#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
5	mjames	2855	#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
		2856	#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /!< 0x00000010 /
		2857	#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /!< PB[13] pin /
		2858	#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
		2859	#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /!< 0x00000020 /
		2860	#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /!< PC[13] pin /
		2861	#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
		2862	#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /!< 0x00000030 /
		2863	#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /!< PD[13] pin /
		2864	#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
		2865	#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /!< 0x00000040 /
		2866	#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /!< PE[13] pin /
		2867	#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
		2868	#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /!< 0x00000050 /
		2869	#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /!< PF[13] pin /
		2870	#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
		2871	#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /!< 0x00000060 /
		2872	#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /!< PG[13] pin /
2	mjames	2873
		2874	/!< EXTI14 configuration /
		2875	#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
5	mjames	2876	#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
		2877	#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /!< 0x00000100 /
		2878	#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /!< PB[14] pin /
		2879	#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
		2880	#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /!< 0x00000200 /
		2881	#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /!< PC[14] pin /
		2882	#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
		2883	#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /!< 0x00000300 /
		2884	#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /!< PD[14] pin /
		2885	#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
		2886	#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /!< 0x00000400 /
		2887	#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /!< PE[14] pin /
		2888	#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
		2889	#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /!< 0x00000500 /
		2890	#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /!< PF[14] pin /
		2891	#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
		2892	#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /!< 0x00000600 /
		2893	#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /!< PG[14] pin /
2	mjames	2894
		2895	/!< EXTI15 configuration /
		2896	#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
5	mjames	2897	#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
		2898	#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /!< 0x00001000 /
		2899	#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /!< PB[15] pin /
		2900	#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
		2901	#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /!< 0x00002000 /
		2902	#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /!< PC[15] pin /
		2903	#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
		2904	#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /!< 0x00003000 /
		2905	#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /!< PD[15] pin /
		2906	#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
		2907	#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /!< 0x00004000 /
		2908	#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /!< PE[15] pin /
		2909	#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
		2910	#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /!< 0x00005000 /
		2911	#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /!< PF[15] pin /
		2912	#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
		2913	#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /!< 0x00006000 /
		2914	#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /!< PG[15] pin /
2	mjames	2915
		2916	/**************** Bit definition for AFIO_MAPR2 register ****************/
5	mjames	2917	#define AFIO_MAPR2_TIM15_REMAP_Pos (0U)
		2918	#define AFIO_MAPR2_TIM15_REMAP_Msk (0x1U << AFIO_MAPR2_TIM15_REMAP_Pos) /!< 0x00000001 /
		2919	#define AFIO_MAPR2_TIM15_REMAP AFIO_MAPR2_TIM15_REMAP_Msk /!< TIM15 remapping /
		2920	#define AFIO_MAPR2_TIM16_REMAP_Pos (1U)
		2921	#define AFIO_MAPR2_TIM16_REMAP_Msk (0x1U << AFIO_MAPR2_TIM16_REMAP_Pos) /!< 0x00000002 /
		2922	#define AFIO_MAPR2_TIM16_REMAP AFIO_MAPR2_TIM16_REMAP_Msk /!< TIM16 remapping /
		2923	#define AFIO_MAPR2_TIM17_REMAP_Pos (2U)
		2924	#define AFIO_MAPR2_TIM17_REMAP_Msk (0x1U << AFIO_MAPR2_TIM17_REMAP_Pos) /!< 0x00000004 /
		2925	#define AFIO_MAPR2_TIM17_REMAP AFIO_MAPR2_TIM17_REMAP_Msk /!< TIM17 remapping /
		2926	#define AFIO_MAPR2_CEC_REMAP_Pos (3U)
		2927	#define AFIO_MAPR2_CEC_REMAP_Msk (0x1U << AFIO_MAPR2_CEC_REMAP_Pos) /!< 0x00000008 /
		2928	#define AFIO_MAPR2_CEC_REMAP AFIO_MAPR2_CEC_REMAP_Msk /!< CEC remapping /
		2929	#define AFIO_MAPR2_TIM1_DMA_REMAP_Pos (4U)
		2930	#define AFIO_MAPR2_TIM1_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM1_DMA_REMAP_Pos) /!< 0x00000010 /
		2931	#define AFIO_MAPR2_TIM1_DMA_REMAP AFIO_MAPR2_TIM1_DMA_REMAP_Msk /!< TIM1_DMA remapping /
2	mjames	2932
5	mjames	2933	#define AFIO_MAPR2_TIM13_REMAP_Pos (8U)
		2934	#define AFIO_MAPR2_TIM13_REMAP_Msk (0x1U << AFIO_MAPR2_TIM13_REMAP_Pos) /!< 0x00000100 /
		2935	#define AFIO_MAPR2_TIM13_REMAP AFIO_MAPR2_TIM13_REMAP_Msk /!< TIM13 remapping /
		2936	#define AFIO_MAPR2_TIM14_REMAP_Pos (9U)
		2937	#define AFIO_MAPR2_TIM14_REMAP_Msk (0x1U << AFIO_MAPR2_TIM14_REMAP_Pos) /!< 0x00000200 /
		2938	#define AFIO_MAPR2_TIM14_REMAP AFIO_MAPR2_TIM14_REMAP_Msk /!< TIM14 remapping /
		2939	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos (11U)
		2940	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos) /!< 0x00000800 /
		2941	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk /!< TIM6/TIM7 and DAC DMA remapping /
		2942	#define AFIO_MAPR2_TIM12_REMAP_Pos (12U)
		2943	#define AFIO_MAPR2_TIM12_REMAP_Msk (0x1U << AFIO_MAPR2_TIM12_REMAP_Pos) /!< 0x00001000 /
		2944	#define AFIO_MAPR2_TIM12_REMAP AFIO_MAPR2_TIM12_REMAP_Msk /!< TIM12 remapping /
		2945	#define AFIO_MAPR2_MISC_REMAP_Pos (13U)
		2946	#define AFIO_MAPR2_MISC_REMAP_Msk (0x1U << AFIO_MAPR2_MISC_REMAP_Pos) /!< 0x00002000 /
		2947	#define AFIO_MAPR2_MISC_REMAP AFIO_MAPR2_MISC_REMAP_Msk /!< Miscellaneous remapping /
2	mjames	2948
5	mjames	2949	#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U)
		2950	#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1U << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /!< 0x00000400 /
		2951	#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /!< FSMC NADV remapping /
2	mjames	2952
		2953	/******************************************************************************/
		2954	/* */
		2955	/* SystemTick */
		2956	/* */
		2957	/******************************************************************************/
		2958
		2959	/*************** Bit definition for SysTick_CTRL register ***************/
5	mjames	2960	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
		2961	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
		2962	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
		2963	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
2	mjames	2964
		2965	/*************** Bit definition for SysTick_LOAD register ***************/
5	mjames	2966	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
2	mjames	2967
		2968	/*************** Bit definition for SysTick_VAL register ****************/
5	mjames	2969	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
2	mjames	2970
		2971	/*************** Bit definition for SysTick_CALIB register **************/
5	mjames	2972	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
		2973	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
		2974	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
2	mjames	2975
		2976	/******************************************************************************/
		2977	/* */
		2978	/* Nested Vectored Interrupt Controller */
		2979	/* */
		2980	/******************************************************************************/
		2981
		2982	/**************** Bit definition for NVIC_ISER register *****************/
5	mjames	2983	#define NVIC_ISER_SETENA_Pos (0U)
		2984	#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /!< 0xFFFFFFFF /
		2985	#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /!< Interrupt set enable bits /
		2986	#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /!< 0x00000001 /
		2987	#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /!< 0x00000002 /
		2988	#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /!< 0x00000004 /
		2989	#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /!< 0x00000008 /
		2990	#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /!< 0x00000010 /
		2991	#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /!< 0x00000020 /
		2992	#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /!< 0x00000040 /
		2993	#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /!< 0x00000080 /
		2994	#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /!< 0x00000100 /
		2995	#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /!< 0x00000200 /
		2996	#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /!< 0x00000400 /
		2997	#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /!< 0x00000800 /
		2998	#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /!< 0x00001000 /
		2999	#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /!< 0x00002000 /
		3000	#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /!< 0x00004000 /
		3001	#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /!< 0x00008000 /
		3002	#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /!< 0x00010000 /
		3003	#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /!< 0x00020000 /
		3004	#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /!< 0x00040000 /
		3005	#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /!< 0x00080000 /
		3006	#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /!< 0x00100000 /
		3007	#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /!< 0x00200000 /
		3008	#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /!< 0x00400000 /
		3009	#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /!< 0x00800000 /
		3010	#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /!< 0x01000000 /
		3011	#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /!< 0x02000000 /
		3012	#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /!< 0x04000000 /
		3013	#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /!< 0x08000000 /
		3014	#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /!< 0x10000000 /
		3015	#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /!< 0x20000000 /
		3016	#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /!< 0x40000000 /
		3017	#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /!< 0x80000000 /
2	mjames	3018
		3019	/**************** Bit definition for NVIC_ICER register *****************/
5	mjames	3020	#define NVIC_ICER_CLRENA_Pos (0U)
		3021	#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /!< 0xFFFFFFFF /
		3022	#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /!< Interrupt clear-enable bits /
		3023	#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /!< 0x00000001 /
		3024	#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /!< 0x00000002 /
		3025	#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /!< 0x00000004 /
		3026	#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /!< 0x00000008 /
		3027	#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /!< 0x00000010 /
		3028	#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /!< 0x00000020 /
		3029	#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /!< 0x00000040 /
		3030	#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /!< 0x00000080 /
		3031	#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /!< 0x00000100 /
		3032	#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /!< 0x00000200 /
		3033	#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /!< 0x00000400 /
		3034	#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /!< 0x00000800 /
		3035	#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /!< 0x00001000 /
		3036	#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /!< 0x00002000 /
		3037	#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /!< 0x00004000 /
		3038	#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /!< 0x00008000 /
		3039	#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /!< 0x00010000 /
		3040	#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /!< 0x00020000 /
		3041	#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /!< 0x00040000 /
		3042	#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /!< 0x00080000 /
		3043	#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /!< 0x00100000 /
		3044	#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /!< 0x00200000 /
		3045	#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /!< 0x00400000 /
		3046	#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /!< 0x00800000 /
		3047	#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /!< 0x01000000 /
		3048	#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /!< 0x02000000 /
		3049	#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /!< 0x04000000 /
		3050	#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /!< 0x08000000 /
		3051	#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /!< 0x10000000 /
		3052	#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /!< 0x20000000 /
		3053	#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /!< 0x40000000 /
		3054	#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /!< 0x80000000 /
2	mjames	3055
		3056	/**************** Bit definition for NVIC_ISPR register *****************/
5	mjames	3057	#define NVIC_ISPR_SETPEND_Pos (0U)
		3058	#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /!< 0xFFFFFFFF /
		3059	#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /!< Interrupt set-pending bits /
		3060	#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000001 /
		3061	#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000002 /
		3062	#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000004 /
		3063	#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000008 /
		3064	#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000010 /
		3065	#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000020 /
		3066	#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000040 /
		3067	#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000080 /
		3068	#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000100 /
		3069	#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000200 /
		3070	#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000400 /
		3071	#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000800 /
		3072	#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00001000 /
		3073	#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00002000 /
		3074	#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00004000 /
		3075	#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00008000 /
		3076	#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00010000 /
		3077	#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00020000 /
		3078	#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00040000 /
		3079	#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00080000 /
		3080	#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00100000 /
		3081	#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00200000 /
		3082	#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00400000 /
		3083	#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00800000 /
		3084	#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x01000000 /
		3085	#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x02000000 /
		3086	#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x04000000 /
		3087	#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x08000000 /
		3088	#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x10000000 /
		3089	#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x20000000 /
		3090	#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x40000000 /
		3091	#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x80000000 /
2	mjames	3092
		3093	/**************** Bit definition for NVIC_ICPR register *****************/
5	mjames	3094	#define NVIC_ICPR_CLRPEND_Pos (0U)
		3095	#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /!< 0xFFFFFFFF /
		3096	#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /!< Interrupt clear-pending bits /
		3097	#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000001 /
		3098	#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000002 /
		3099	#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000004 /
		3100	#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000008 /
		3101	#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000010 /
		3102	#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000020 /
		3103	#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000040 /
		3104	#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000080 /
		3105	#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000100 /
		3106	#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000200 /
		3107	#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000400 /
		3108	#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000800 /
		3109	#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00001000 /
		3110	#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00002000 /
		3111	#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00004000 /
		3112	#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00008000 /
		3113	#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00010000 /
		3114	#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00020000 /
		3115	#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00040000 /
		3116	#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00080000 /
		3117	#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00100000 /
		3118	#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00200000 /
		3119	#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00400000 /
		3120	#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00800000 /
		3121	#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x01000000 /
		3122	#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x02000000 /
		3123	#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x04000000 /
		3124	#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x08000000 /
		3125	#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x10000000 /
		3126	#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x20000000 /
		3127	#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x40000000 /
		3128	#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x80000000 /
2	mjames	3129
		3130	/**************** Bit definition for NVIC_IABR register *****************/
5	mjames	3131	#define NVIC_IABR_ACTIVE_Pos (0U)
		3132	#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /!< 0xFFFFFFFF /
		3133	#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /!< Interrupt active flags /
		3134	#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000001 /
		3135	#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000002 /
		3136	#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000004 /
		3137	#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000008 /
		3138	#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000010 /
		3139	#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000020 /
		3140	#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000040 /
		3141	#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000080 /
		3142	#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000100 /
		3143	#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000200 /
		3144	#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000400 /
		3145	#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000800 /
		3146	#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00001000 /
		3147	#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00002000 /
		3148	#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00004000 /
		3149	#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00008000 /
		3150	#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00010000 /
		3151	#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00020000 /
		3152	#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00040000 /
		3153	#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00080000 /
		3154	#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00100000 /
		3155	#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00200000 /
		3156	#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00400000 /
		3157	#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00800000 /
		3158	#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x01000000 /
		3159	#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x02000000 /
		3160	#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x04000000 /
		3161	#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x08000000 /
		3162	#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x10000000 /
		3163	#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x20000000 /
		3164	#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x40000000 /
		3165	#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x80000000 /
2	mjames	3166
		3167	/**************** Bit definition for NVIC_PRI0 register *****************/
5	mjames	3168	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
		3169	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
		3170	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
		3171	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
2	mjames	3172
		3173	/**************** Bit definition for NVIC_PRI1 register *****************/
5	mjames	3174	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
		3175	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
		3176	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
		3177	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
2	mjames	3178
		3179	/**************** Bit definition for NVIC_PRI2 register *****************/
5	mjames	3180	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
		3181	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
		3182	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
		3183	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
2	mjames	3184
		3185	/**************** Bit definition for NVIC_PRI3 register *****************/
5	mjames	3186	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
		3187	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
		3188	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
		3189	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
2	mjames	3190
		3191	/**************** Bit definition for NVIC_PRI4 register *****************/
5	mjames	3192	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
		3193	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
		3194	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
		3195	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
2	mjames	3196
		3197	/**************** Bit definition for NVIC_PRI5 register *****************/
5	mjames	3198	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
		3199	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
		3200	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
		3201	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
2	mjames	3202
		3203	/**************** Bit definition for NVIC_PRI6 register *****************/
5	mjames	3204	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
		3205	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
		3206	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
		3207	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
2	mjames	3208
		3209	/**************** Bit definition for NVIC_PRI7 register *****************/
5	mjames	3210	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
		3211	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
		3212	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
		3213	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
2	mjames	3214
		3215	/**************** Bit definition for SCB_CPUID register *****************/
5	mjames	3216	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
		3217	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
		3218	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
		3219	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
		3220	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
2	mjames	3221
		3222	/***************** Bit definition for SCB_ICSR register *****************/
5	mjames	3223	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
		3224	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
		3225	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
		3226	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
		3227	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
		3228	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
		3229	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
		3230	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
		3231	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
		3232	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
2	mjames	3233
		3234	/***************** Bit definition for SCB_VTOR register *****************/
5	mjames	3235	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
		3236	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
2	mjames	3237
		3238	/!<************** Bit definition for SCB_AIRCR register *****************/
5	mjames	3239	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
		3240	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
		3241	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
2	mjames	3242
5	mjames	3243	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
		3244	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		3245	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		3246	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
2	mjames	3247
		3248	/* prority group configuration */
5	mjames	3249	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
		3250	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
		3251	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
		3252	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
		3253	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
		3254	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
		3255	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
		3256	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
2	mjames	3257
5	mjames	3258	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
		3259	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
2	mjames	3260
		3261	/***************** Bit definition for SCB_SCR register ******************/
5	mjames	3262	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
		3263	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
		3264	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
2	mjames	3265
		3266	/****************** Bit definition for SCB_CCR register *****************/
5	mjames	3267	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
		3268	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
		3269	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
		3270	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
		3271	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
		3272	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
2	mjames	3273
		3274	/***************** Bit definition for SCB_SHPR register ******************/
5	mjames	3275	#define SCB_SHPR_PRI_N_Pos (0U)
		3276	#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /!< 0x000000FF /
		3277	#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
		3278	#define SCB_SHPR_PRI_N1_Pos (8U)
		3279	#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /!< 0x0000FF00 /
		3280	#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
		3281	#define SCB_SHPR_PRI_N2_Pos (16U)
		3282	#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /!< 0x00FF0000 /
		3283	#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
		3284	#define SCB_SHPR_PRI_N3_Pos (24U)
		3285	#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /!< 0xFF000000 /
		3286	#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
2	mjames	3287
		3288	/**************** Bit definition for SCB_SHCSR register *****************/
5	mjames	3289	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
		3290	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
		3291	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
		3292	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
		3293	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
		3294	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
		3295	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
		3296	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
		3297	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
		3298	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
		3299	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
		3300	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
		3301	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
		3302	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
2	mjames	3303
		3304	/***************** Bit definition for SCB_CFSR register *****************/
		3305	/!< MFSR /
5	mjames	3306	#define SCB_CFSR_IACCVIOL_Pos (0U)
		3307	#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /!< 0x00000001 /
		3308	#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /!< Instruction access violation /
		3309	#define SCB_CFSR_DACCVIOL_Pos (1U)
		3310	#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /!< 0x00000002 /
		3311	#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /!< Data access violation /
		3312	#define SCB_CFSR_MUNSTKERR_Pos (3U)
		3313	#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /!< 0x00000008 /
		3314	#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /!< Unstacking error /
		3315	#define SCB_CFSR_MSTKERR_Pos (4U)
		3316	#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /!< 0x00000010 /
		3317	#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /!< Stacking error /
		3318	#define SCB_CFSR_MMARVALID_Pos (7U)
		3319	#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /!< 0x00000080 /
		3320	#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /!< Memory Manage Address Register address valid flag /
2	mjames	3321	/!< BFSR /
5	mjames	3322	#define SCB_CFSR_IBUSERR_Pos (8U)
		3323	#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /!< 0x00000100 /
		3324	#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /!< Instruction bus error flag /
		3325	#define SCB_CFSR_PRECISERR_Pos (9U)
		3326	#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /!< 0x00000200 /
		3327	#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /!< Precise data bus error /
		3328	#define SCB_CFSR_IMPRECISERR_Pos (10U)
		3329	#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /!< 0x00000400 /
		3330	#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /!< Imprecise data bus error /
		3331	#define SCB_CFSR_UNSTKERR_Pos (11U)
		3332	#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /!< 0x00000800 /
		3333	#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /!< Unstacking error /
		3334	#define SCB_CFSR_STKERR_Pos (12U)
		3335	#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /!< 0x00001000 /
		3336	#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /!< Stacking error /
		3337	#define SCB_CFSR_BFARVALID_Pos (15U)
		3338	#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /!< 0x00008000 /
		3339	#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /!< Bus Fault Address Register address valid flag /
2	mjames	3340	/!< UFSR /
5	mjames	3341	#define SCB_CFSR_UNDEFINSTR_Pos (16U)
		3342	#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /!< 0x00010000 /
		3343	#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /!< The processor attempt to execute an undefined instruction /
		3344	#define SCB_CFSR_INVSTATE_Pos (17U)
		3345	#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /!< 0x00020000 /
		3346	#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /!< Invalid combination of EPSR and instruction /
		3347	#define SCB_CFSR_INVPC_Pos (18U)
		3348	#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /!< 0x00040000 /
		3349	#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /!< Attempt to load EXC_RETURN into pc illegally /
		3350	#define SCB_CFSR_NOCP_Pos (19U)
		3351	#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /!< 0x00080000 /
		3352	#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /!< Attempt to use a coprocessor instruction /
		3353	#define SCB_CFSR_UNALIGNED_Pos (24U)
		3354	#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /!< 0x01000000 /
		3355	#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /!< Fault occurs when there is an attempt to make an unaligned memory access /
		3356	#define SCB_CFSR_DIVBYZERO_Pos (25U)
		3357	#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /!< 0x02000000 /
		3358	#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
2	mjames	3359
		3360	/***************** Bit definition for SCB_HFSR register *****************/
5	mjames	3361	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
		3362	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
		3363	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
2	mjames	3364
		3365	/***************** Bit definition for SCB_DFSR register *****************/
5	mjames	3366	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
		3367	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
		3368	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
		3369	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
		3370	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
2	mjames	3371
		3372	/***************** Bit definition for SCB_MMFAR register ****************/
5	mjames	3373	#define SCB_MMFAR_ADDRESS_Pos (0U)
		3374	#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /!< 0xFFFFFFFF /
		3375	#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /!< Mem Manage fault address field /
2	mjames	3376
		3377	/***************** Bit definition for SCB_BFAR register *****************/
5	mjames	3378	#define SCB_BFAR_ADDRESS_Pos (0U)
		3379	#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /!< 0xFFFFFFFF /
		3380	#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /!< Bus fault address field /
2	mjames	3381
		3382	/***************** Bit definition for SCB_afsr register *****************/
5	mjames	3383	#define SCB_AFSR_IMPDEF_Pos (0U)
		3384	#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /!< 0xFFFFFFFF /
		3385	#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /!< Implementation defined /
2	mjames	3386
		3387	/******************************************************************************/
		3388	/* */
		3389	/* External Interrupt/Event Controller */
		3390	/* */
		3391	/******************************************************************************/
		3392
		3393	/***************** Bit definition for EXTI_IMR register *****************/
5	mjames	3394	#define EXTI_IMR_MR0_Pos (0U)
		3395	#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /!< 0x00000001 /
		3396	#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /!< Interrupt Mask on line 0 /
		3397	#define EXTI_IMR_MR1_Pos (1U)
		3398	#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /!< 0x00000002 /
		3399	#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /!< Interrupt Mask on line 1 /
		3400	#define EXTI_IMR_MR2_Pos (2U)
		3401	#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /!< 0x00000004 /
		3402	#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /!< Interrupt Mask on line 2 /
		3403	#define EXTI_IMR_MR3_Pos (3U)
		3404	#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /!< 0x00000008 /
		3405	#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /!< Interrupt Mask on line 3 /
		3406	#define EXTI_IMR_MR4_Pos (4U)
		3407	#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /!< 0x00000010 /
		3408	#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /!< Interrupt Mask on line 4 /
		3409	#define EXTI_IMR_MR5_Pos (5U)
		3410	#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /!< 0x00000020 /
		3411	#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /!< Interrupt Mask on line 5 /
		3412	#define EXTI_IMR_MR6_Pos (6U)
		3413	#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /!< 0x00000040 /
		3414	#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /!< Interrupt Mask on line 6 /
		3415	#define EXTI_IMR_MR7_Pos (7U)
		3416	#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /!< 0x00000080 /
		3417	#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /!< Interrupt Mask on line 7 /
		3418	#define EXTI_IMR_MR8_Pos (8U)
		3419	#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /!< 0x00000100 /
		3420	#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /!< Interrupt Mask on line 8 /
		3421	#define EXTI_IMR_MR9_Pos (9U)
		3422	#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /!< 0x00000200 /
		3423	#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /!< Interrupt Mask on line 9 /
		3424	#define EXTI_IMR_MR10_Pos (10U)
		3425	#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /!< 0x00000400 /
		3426	#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /!< Interrupt Mask on line 10 /
		3427	#define EXTI_IMR_MR11_Pos (11U)
		3428	#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /!< 0x00000800 /
		3429	#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /!< Interrupt Mask on line 11 /
		3430	#define EXTI_IMR_MR12_Pos (12U)
		3431	#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /!< 0x00001000 /
		3432	#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /!< Interrupt Mask on line 12 /
		3433	#define EXTI_IMR_MR13_Pos (13U)
		3434	#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /!< 0x00002000 /
		3435	#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /!< Interrupt Mask on line 13 /
		3436	#define EXTI_IMR_MR14_Pos (14U)
		3437	#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /!< 0x00004000 /
		3438	#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /!< Interrupt Mask on line 14 /
		3439	#define EXTI_IMR_MR15_Pos (15U)
		3440	#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /!< 0x00008000 /
		3441	#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /!< Interrupt Mask on line 15 /
		3442	#define EXTI_IMR_MR16_Pos (16U)
		3443	#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /!< 0x00010000 /
		3444	#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /!< Interrupt Mask on line 16 /
		3445	#define EXTI_IMR_MR17_Pos (17U)
		3446	#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /!< 0x00020000 /
		3447	#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /!< Interrupt Mask on line 17 /
		3448	#define EXTI_IMR_MR18_Pos (18U)
		3449	#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /!< 0x00040000 /
		3450	#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /!< Interrupt Mask on line 18 /
		3451	#define EXTI_IMR_MR19_Pos (19U)
		3452	#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /!< 0x00080000 /
		3453	#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /!< Interrupt Mask on line 19 /
2	mjames	3454
5	mjames	3455	/* References Defines */
		3456	#define EXTI_IMR_IM0 EXTI_IMR_MR0
		3457	#define EXTI_IMR_IM1 EXTI_IMR_MR1
		3458	#define EXTI_IMR_IM2 EXTI_IMR_MR2
		3459	#define EXTI_IMR_IM3 EXTI_IMR_MR3
		3460	#define EXTI_IMR_IM4 EXTI_IMR_MR4
		3461	#define EXTI_IMR_IM5 EXTI_IMR_MR5
		3462	#define EXTI_IMR_IM6 EXTI_IMR_MR6
		3463	#define EXTI_IMR_IM7 EXTI_IMR_MR7
		3464	#define EXTI_IMR_IM8 EXTI_IMR_MR8
		3465	#define EXTI_IMR_IM9 EXTI_IMR_MR9
		3466	#define EXTI_IMR_IM10 EXTI_IMR_MR10
		3467	#define EXTI_IMR_IM11 EXTI_IMR_MR11
		3468	#define EXTI_IMR_IM12 EXTI_IMR_MR12
		3469	#define EXTI_IMR_IM13 EXTI_IMR_MR13
		3470	#define EXTI_IMR_IM14 EXTI_IMR_MR14
		3471	#define EXTI_IMR_IM15 EXTI_IMR_MR15
		3472	#define EXTI_IMR_IM16 EXTI_IMR_MR16
		3473	#define EXTI_IMR_IM17 EXTI_IMR_MR17
		3474	#define EXTI_IMR_IM18 EXTI_IMR_MR18
		3475	#define EXTI_IMR_IM19 EXTI_IMR_MR19
		3476
2	mjames	3477	/***************** Bit definition for EXTI_EMR register *****************/
5	mjames	3478	#define EXTI_EMR_MR0_Pos (0U)
		3479	#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /!< 0x00000001 /
		3480	#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /!< Event Mask on line 0 /
		3481	#define EXTI_EMR_MR1_Pos (1U)
		3482	#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /!< 0x00000002 /
		3483	#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /!< Event Mask on line 1 /
		3484	#define EXTI_EMR_MR2_Pos (2U)
		3485	#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /!< 0x00000004 /
		3486	#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /!< Event Mask on line 2 /
		3487	#define EXTI_EMR_MR3_Pos (3U)
		3488	#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /!< 0x00000008 /
		3489	#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /!< Event Mask on line 3 /
		3490	#define EXTI_EMR_MR4_Pos (4U)
		3491	#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /!< 0x00000010 /
		3492	#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /!< Event Mask on line 4 /
		3493	#define EXTI_EMR_MR5_Pos (5U)
		3494	#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /!< 0x00000020 /
		3495	#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /!< Event Mask on line 5 /
		3496	#define EXTI_EMR_MR6_Pos (6U)
		3497	#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /!< 0x00000040 /
		3498	#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /!< Event Mask on line 6 /
		3499	#define EXTI_EMR_MR7_Pos (7U)
		3500	#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /!< 0x00000080 /
		3501	#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /!< Event Mask on line 7 /
		3502	#define EXTI_EMR_MR8_Pos (8U)
		3503	#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /!< 0x00000100 /
		3504	#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /!< Event Mask on line 8 /
		3505	#define EXTI_EMR_MR9_Pos (9U)
		3506	#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /!< 0x00000200 /
		3507	#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /!< Event Mask on line 9 /
		3508	#define EXTI_EMR_MR10_Pos (10U)
		3509	#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /!< 0x00000400 /
		3510	#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /!< Event Mask on line 10 /
		3511	#define EXTI_EMR_MR11_Pos (11U)
		3512	#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /!< 0x00000800 /
		3513	#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /!< Event Mask on line 11 /
		3514	#define EXTI_EMR_MR12_Pos (12U)
		3515	#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /!< 0x00001000 /
		3516	#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /!< Event Mask on line 12 /
		3517	#define EXTI_EMR_MR13_Pos (13U)
		3518	#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /!< 0x00002000 /
		3519	#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /!< Event Mask on line 13 /
		3520	#define EXTI_EMR_MR14_Pos (14U)
		3521	#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /!< 0x00004000 /
		3522	#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /!< Event Mask on line 14 /
		3523	#define EXTI_EMR_MR15_Pos (15U)
		3524	#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /!< 0x00008000 /
		3525	#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /!< Event Mask on line 15 /
		3526	#define EXTI_EMR_MR16_Pos (16U)
		3527	#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /!< 0x00010000 /
		3528	#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /!< Event Mask on line 16 /
		3529	#define EXTI_EMR_MR17_Pos (17U)
		3530	#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /!< 0x00020000 /
		3531	#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /!< Event Mask on line 17 /
		3532	#define EXTI_EMR_MR18_Pos (18U)
		3533	#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /!< 0x00040000 /
		3534	#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /!< Event Mask on line 18 /
		3535	#define EXTI_EMR_MR19_Pos (19U)
		3536	#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /!< 0x00080000 /
		3537	#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /!< Event Mask on line 19 /
2	mjames	3538
5	mjames	3539	/* References Defines */
		3540	#define EXTI_EMR_EM0 EXTI_EMR_MR0
		3541	#define EXTI_EMR_EM1 EXTI_EMR_MR1
		3542	#define EXTI_EMR_EM2 EXTI_EMR_MR2
		3543	#define EXTI_EMR_EM3 EXTI_EMR_MR3
		3544	#define EXTI_EMR_EM4 EXTI_EMR_MR4
		3545	#define EXTI_EMR_EM5 EXTI_EMR_MR5
		3546	#define EXTI_EMR_EM6 EXTI_EMR_MR6
		3547	#define EXTI_EMR_EM7 EXTI_EMR_MR7
		3548	#define EXTI_EMR_EM8 EXTI_EMR_MR8
		3549	#define EXTI_EMR_EM9 EXTI_EMR_MR9
		3550	#define EXTI_EMR_EM10 EXTI_EMR_MR10
		3551	#define EXTI_EMR_EM11 EXTI_EMR_MR11
		3552	#define EXTI_EMR_EM12 EXTI_EMR_MR12
		3553	#define EXTI_EMR_EM13 EXTI_EMR_MR13
		3554	#define EXTI_EMR_EM14 EXTI_EMR_MR14
		3555	#define EXTI_EMR_EM15 EXTI_EMR_MR15
		3556	#define EXTI_EMR_EM16 EXTI_EMR_MR16
		3557	#define EXTI_EMR_EM17 EXTI_EMR_MR17
		3558	#define EXTI_EMR_EM18 EXTI_EMR_MR18
		3559	#define EXTI_EMR_EM19 EXTI_EMR_MR19
		3560
2	mjames	3561	/**************** Bit definition for EXTI_RTSR register *****************/
5	mjames	3562	#define EXTI_RTSR_TR0_Pos (0U)
		3563	#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /!< 0x00000001 /
		3564	#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /!< Rising trigger event configuration bit of line 0 /
		3565	#define EXTI_RTSR_TR1_Pos (1U)
		3566	#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /!< 0x00000002 /
		3567	#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /!< Rising trigger event configuration bit of line 1 /
		3568	#define EXTI_RTSR_TR2_Pos (2U)
		3569	#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /!< 0x00000004 /
		3570	#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /!< Rising trigger event configuration bit of line 2 /
		3571	#define EXTI_RTSR_TR3_Pos (3U)
		3572	#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /!< 0x00000008 /
		3573	#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /!< Rising trigger event configuration bit of line 3 /
		3574	#define EXTI_RTSR_TR4_Pos (4U)
		3575	#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /!< 0x00000010 /
		3576	#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /!< Rising trigger event configuration bit of line 4 /
		3577	#define EXTI_RTSR_TR5_Pos (5U)
		3578	#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /!< 0x00000020 /
		3579	#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /!< Rising trigger event configuration bit of line 5 /
		3580	#define EXTI_RTSR_TR6_Pos (6U)
		3581	#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /!< 0x00000040 /
		3582	#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /!< Rising trigger event configuration bit of line 6 /
		3583	#define EXTI_RTSR_TR7_Pos (7U)
		3584	#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /!< 0x00000080 /
		3585	#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /!< Rising trigger event configuration bit of line 7 /
		3586	#define EXTI_RTSR_TR8_Pos (8U)
		3587	#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /!< 0x00000100 /
		3588	#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /!< Rising trigger event configuration bit of line 8 /
		3589	#define EXTI_RTSR_TR9_Pos (9U)
		3590	#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /!< 0x00000200 /
		3591	#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /!< Rising trigger event configuration bit of line 9 /
		3592	#define EXTI_RTSR_TR10_Pos (10U)
		3593	#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /!< 0x00000400 /
		3594	#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /!< Rising trigger event configuration bit of line 10 /
		3595	#define EXTI_RTSR_TR11_Pos (11U)
		3596	#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /!< 0x00000800 /
		3597	#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /!< Rising trigger event configuration bit of line 11 /
		3598	#define EXTI_RTSR_TR12_Pos (12U)
		3599	#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /!< 0x00001000 /
		3600	#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /!< Rising trigger event configuration bit of line 12 /
		3601	#define EXTI_RTSR_TR13_Pos (13U)
		3602	#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /!< 0x00002000 /
		3603	#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /!< Rising trigger event configuration bit of line 13 /
		3604	#define EXTI_RTSR_TR14_Pos (14U)
		3605	#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /!< 0x00004000 /
		3606	#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /!< Rising trigger event configuration bit of line 14 /
		3607	#define EXTI_RTSR_TR15_Pos (15U)
		3608	#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /!< 0x00008000 /
		3609	#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /!< Rising trigger event configuration bit of line 15 /
		3610	#define EXTI_RTSR_TR16_Pos (16U)
		3611	#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /!< 0x00010000 /
		3612	#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /!< Rising trigger event configuration bit of line 16 /
		3613	#define EXTI_RTSR_TR17_Pos (17U)
		3614	#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /!< 0x00020000 /
		3615	#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /!< Rising trigger event configuration bit of line 17 /
		3616	#define EXTI_RTSR_TR18_Pos (18U)
		3617	#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /!< 0x00040000 /
		3618	#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /!< Rising trigger event configuration bit of line 18 /
		3619	#define EXTI_RTSR_TR19_Pos (19U)
		3620	#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /!< 0x00080000 /
		3621	#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /!< Rising trigger event configuration bit of line 19 /
2	mjames	3622
5	mjames	3623	/* References Defines */
		3624	#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
		3625	#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
		3626	#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
		3627	#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
		3628	#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
		3629	#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
		3630	#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
		3631	#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
		3632	#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
		3633	#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
		3634	#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
		3635	#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
		3636	#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
		3637	#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
		3638	#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
		3639	#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
		3640	#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
		3641	#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
		3642	#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
		3643	#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
		3644
2	mjames	3645	/**************** Bit definition for EXTI_FTSR register *****************/
5	mjames	3646	#define EXTI_FTSR_TR0_Pos (0U)
		3647	#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /!< 0x00000001 /
		3648	#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /!< Falling trigger event configuration bit of line 0 /
		3649	#define EXTI_FTSR_TR1_Pos (1U)
		3650	#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /!< 0x00000002 /
		3651	#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /!< Falling trigger event configuration bit of line 1 /
		3652	#define EXTI_FTSR_TR2_Pos (2U)
		3653	#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /!< 0x00000004 /
		3654	#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /!< Falling trigger event configuration bit of line 2 /
		3655	#define EXTI_FTSR_TR3_Pos (3U)
		3656	#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /!< 0x00000008 /
		3657	#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /!< Falling trigger event configuration bit of line 3 /
		3658	#define EXTI_FTSR_TR4_Pos (4U)
		3659	#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /!< 0x00000010 /
		3660	#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /!< Falling trigger event configuration bit of line 4 /
		3661	#define EXTI_FTSR_TR5_Pos (5U)
		3662	#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /!< 0x00000020 /
		3663	#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /!< Falling trigger event configuration bit of line 5 /
		3664	#define EXTI_FTSR_TR6_Pos (6U)
		3665	#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /!< 0x00000040 /
		3666	#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /!< Falling trigger event configuration bit of line 6 /
		3667	#define EXTI_FTSR_TR7_Pos (7U)
		3668	#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /!< 0x00000080 /
		3669	#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /!< Falling trigger event configuration bit of line 7 /
		3670	#define EXTI_FTSR_TR8_Pos (8U)
		3671	#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /!< 0x00000100 /
		3672	#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /!< Falling trigger event configuration bit of line 8 /
		3673	#define EXTI_FTSR_TR9_Pos (9U)
		3674	#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /!< 0x00000200 /
		3675	#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /!< Falling trigger event configuration bit of line 9 /
		3676	#define EXTI_FTSR_TR10_Pos (10U)
		3677	#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /!< 0x00000400 /
		3678	#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /!< Falling trigger event configuration bit of line 10 /
		3679	#define EXTI_FTSR_TR11_Pos (11U)
		3680	#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /!< 0x00000800 /
		3681	#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /!< Falling trigger event configuration bit of line 11 /
		3682	#define EXTI_FTSR_TR12_Pos (12U)
		3683	#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /!< 0x00001000 /
		3684	#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /!< Falling trigger event configuration bit of line 12 /
		3685	#define EXTI_FTSR_TR13_Pos (13U)
		3686	#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /!< 0x00002000 /
		3687	#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /!< Falling trigger event configuration bit of line 13 /
		3688	#define EXTI_FTSR_TR14_Pos (14U)
		3689	#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /!< 0x00004000 /
		3690	#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /!< Falling trigger event configuration bit of line 14 /
		3691	#define EXTI_FTSR_TR15_Pos (15U)
		3692	#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /!< 0x00008000 /
		3693	#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /!< Falling trigger event configuration bit of line 15 /
		3694	#define EXTI_FTSR_TR16_Pos (16U)
		3695	#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /!< 0x00010000 /
		3696	#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /!< Falling trigger event configuration bit of line 16 /
		3697	#define EXTI_FTSR_TR17_Pos (17U)
		3698	#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /!< 0x00020000 /
		3699	#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /!< Falling trigger event configuration bit of line 17 /
		3700	#define EXTI_FTSR_TR18_Pos (18U)
		3701	#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /!< 0x00040000 /
		3702	#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /!< Falling trigger event configuration bit of line 18 /
		3703	#define EXTI_FTSR_TR19_Pos (19U)
		3704	#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /!< 0x00080000 /
		3705	#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /!< Falling trigger event configuration bit of line 19 /
2	mjames	3706
5	mjames	3707	/* References Defines */
		3708	#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
		3709	#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
		3710	#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
		3711	#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
		3712	#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
		3713	#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
		3714	#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
		3715	#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
		3716	#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
		3717	#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
		3718	#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
		3719	#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
		3720	#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
		3721	#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
		3722	#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
		3723	#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
		3724	#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
		3725	#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
		3726	#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
		3727	#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
		3728
2	mjames	3729	/**************** Bit definition for EXTI_SWIER register ****************/
5	mjames	3730	#define EXTI_SWIER_SWIER0_Pos (0U)
		3731	#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /!< 0x00000001 /
		3732	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /!< Software Interrupt on line 0 /
		3733	#define EXTI_SWIER_SWIER1_Pos (1U)
		3734	#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /!< 0x00000002 /
		3735	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /!< Software Interrupt on line 1 /
		3736	#define EXTI_SWIER_SWIER2_Pos (2U)
		3737	#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /!< 0x00000004 /
		3738	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /!< Software Interrupt on line 2 /
		3739	#define EXTI_SWIER_SWIER3_Pos (3U)
		3740	#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /!< 0x00000008 /
		3741	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /!< Software Interrupt on line 3 /
		3742	#define EXTI_SWIER_SWIER4_Pos (4U)
		3743	#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /!< 0x00000010 /
		3744	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /!< Software Interrupt on line 4 /
		3745	#define EXTI_SWIER_SWIER5_Pos (5U)
		3746	#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /!< 0x00000020 /
		3747	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /!< Software Interrupt on line 5 /
		3748	#define EXTI_SWIER_SWIER6_Pos (6U)
		3749	#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /!< 0x00000040 /
		3750	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /!< Software Interrupt on line 6 /
		3751	#define EXTI_SWIER_SWIER7_Pos (7U)
		3752	#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /!< 0x00000080 /
		3753	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /!< Software Interrupt on line 7 /
		3754	#define EXTI_SWIER_SWIER8_Pos (8U)
		3755	#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /!< 0x00000100 /
		3756	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /!< Software Interrupt on line 8 /
		3757	#define EXTI_SWIER_SWIER9_Pos (9U)
		3758	#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /!< 0x00000200 /
		3759	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /!< Software Interrupt on line 9 /
		3760	#define EXTI_SWIER_SWIER10_Pos (10U)
		3761	#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /!< 0x00000400 /
		3762	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /!< Software Interrupt on line 10 /
		3763	#define EXTI_SWIER_SWIER11_Pos (11U)
		3764	#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /!< 0x00000800 /
		3765	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /!< Software Interrupt on line 11 /
		3766	#define EXTI_SWIER_SWIER12_Pos (12U)
		3767	#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /!< 0x00001000 /
		3768	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /!< Software Interrupt on line 12 /
		3769	#define EXTI_SWIER_SWIER13_Pos (13U)
		3770	#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /!< 0x00002000 /
		3771	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /!< Software Interrupt on line 13 /
		3772	#define EXTI_SWIER_SWIER14_Pos (14U)
		3773	#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /!< 0x00004000 /
		3774	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /!< Software Interrupt on line 14 /
		3775	#define EXTI_SWIER_SWIER15_Pos (15U)
		3776	#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /!< 0x00008000 /
		3777	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /!< Software Interrupt on line 15 /
		3778	#define EXTI_SWIER_SWIER16_Pos (16U)
		3779	#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /!< 0x00010000 /
		3780	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /!< Software Interrupt on line 16 /
		3781	#define EXTI_SWIER_SWIER17_Pos (17U)
		3782	#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /!< 0x00020000 /
		3783	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /!< Software Interrupt on line 17 /
		3784	#define EXTI_SWIER_SWIER18_Pos (18U)
		3785	#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /!< 0x00040000 /
		3786	#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /!< Software Interrupt on line 18 /
		3787	#define EXTI_SWIER_SWIER19_Pos (19U)
		3788	#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /!< 0x00080000 /
		3789	#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /!< Software Interrupt on line 19 /
2	mjames	3790
5	mjames	3791	/* References Defines */
		3792	#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
		3793	#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
		3794	#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
		3795	#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
		3796	#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
		3797	#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
		3798	#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
		3799	#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
		3800	#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
		3801	#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
		3802	#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
		3803	#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
		3804	#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
		3805	#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
		3806	#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
		3807	#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
		3808	#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
		3809	#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
		3810	#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
		3811	#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
		3812
2	mjames	3813	/***************** Bit definition for EXTI_PR register ******************/
5	mjames	3814	#define EXTI_PR_PR0_Pos (0U)
		3815	#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /!< 0x00000001 /
		3816	#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /!< Pending bit for line 0 /
		3817	#define EXTI_PR_PR1_Pos (1U)
		3818	#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /!< 0x00000002 /
		3819	#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /!< Pending bit for line 1 /
		3820	#define EXTI_PR_PR2_Pos (2U)
		3821	#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /!< 0x00000004 /
		3822	#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /!< Pending bit for line 2 /
		3823	#define EXTI_PR_PR3_Pos (3U)
		3824	#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /!< 0x00000008 /
		3825	#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /!< Pending bit for line 3 /
		3826	#define EXTI_PR_PR4_Pos (4U)
		3827	#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /!< 0x00000010 /
		3828	#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /!< Pending bit for line 4 /
		3829	#define EXTI_PR_PR5_Pos (5U)
		3830	#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /!< 0x00000020 /
		3831	#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /!< Pending bit for line 5 /
		3832	#define EXTI_PR_PR6_Pos (6U)
		3833	#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /!< 0x00000040 /
		3834	#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /!< Pending bit for line 6 /
		3835	#define EXTI_PR_PR7_Pos (7U)
		3836	#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /!< 0x00000080 /
		3837	#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /!< Pending bit for line 7 /
		3838	#define EXTI_PR_PR8_Pos (8U)
		3839	#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /!< 0x00000100 /
		3840	#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /!< Pending bit for line 8 /
		3841	#define EXTI_PR_PR9_Pos (9U)
		3842	#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /!< 0x00000200 /
		3843	#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /!< Pending bit for line 9 /
		3844	#define EXTI_PR_PR10_Pos (10U)
		3845	#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /!< 0x00000400 /
		3846	#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /!< Pending bit for line 10 /
		3847	#define EXTI_PR_PR11_Pos (11U)
		3848	#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /!< 0x00000800 /
		3849	#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /!< Pending bit for line 11 /
		3850	#define EXTI_PR_PR12_Pos (12U)
		3851	#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /!< 0x00001000 /
		3852	#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /!< Pending bit for line 12 /
		3853	#define EXTI_PR_PR13_Pos (13U)
		3854	#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /!< 0x00002000 /
		3855	#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /!< Pending bit for line 13 /
		3856	#define EXTI_PR_PR14_Pos (14U)
		3857	#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /!< 0x00004000 /
		3858	#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /!< Pending bit for line 14 /
		3859	#define EXTI_PR_PR15_Pos (15U)
		3860	#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /!< 0x00008000 /
		3861	#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /!< Pending bit for line 15 /
		3862	#define EXTI_PR_PR16_Pos (16U)
		3863	#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /!< 0x00010000 /
		3864	#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /!< Pending bit for line 16 /
		3865	#define EXTI_PR_PR17_Pos (17U)
		3866	#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /!< 0x00020000 /
		3867	#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /!< Pending bit for line 17 /
		3868	#define EXTI_PR_PR18_Pos (18U)
		3869	#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /!< 0x00040000 /
		3870	#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /!< Pending bit for line 18 /
		3871	#define EXTI_PR_PR19_Pos (19U)
		3872	#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /!< 0x00080000 /
		3873	#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /!< Pending bit for line 19 /
2	mjames	3874
5	mjames	3875	/* References Defines */
		3876	#define EXTI_PR_PIF0 EXTI_PR_PR0
		3877	#define EXTI_PR_PIF1 EXTI_PR_PR1
		3878	#define EXTI_PR_PIF2 EXTI_PR_PR2
		3879	#define EXTI_PR_PIF3 EXTI_PR_PR3
		3880	#define EXTI_PR_PIF4 EXTI_PR_PR4
		3881	#define EXTI_PR_PIF5 EXTI_PR_PR5
		3882	#define EXTI_PR_PIF6 EXTI_PR_PR6
		3883	#define EXTI_PR_PIF7 EXTI_PR_PR7
		3884	#define EXTI_PR_PIF8 EXTI_PR_PR8
		3885	#define EXTI_PR_PIF9 EXTI_PR_PR9
		3886	#define EXTI_PR_PIF10 EXTI_PR_PR10
		3887	#define EXTI_PR_PIF11 EXTI_PR_PR11
		3888	#define EXTI_PR_PIF12 EXTI_PR_PR12
		3889	#define EXTI_PR_PIF13 EXTI_PR_PR13
		3890	#define EXTI_PR_PIF14 EXTI_PR_PR14
		3891	#define EXTI_PR_PIF15 EXTI_PR_PR15
		3892	#define EXTI_PR_PIF16 EXTI_PR_PR16
		3893	#define EXTI_PR_PIF17 EXTI_PR_PR17
		3894	#define EXTI_PR_PIF18 EXTI_PR_PR18
		3895	#define EXTI_PR_PIF19 EXTI_PR_PR19
		3896
2	mjames	3897	/******************************************************************************/
		3898	/* */
		3899	/* DMA Controller */
		3900	/* */
		3901	/******************************************************************************/
		3902
		3903	/***************** Bit definition for DMA_ISR register ******************/
5	mjames	3904	#define DMA_ISR_GIF1_Pos (0U)
		3905	#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /!< 0x00000001 /
		3906	#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /!< Channel 1 Global interrupt flag /
		3907	#define DMA_ISR_TCIF1_Pos (1U)
		3908	#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /!< 0x00000002 /
		3909	#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /!< Channel 1 Transfer Complete flag /
		3910	#define DMA_ISR_HTIF1_Pos (2U)
		3911	#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /!< 0x00000004 /
		3912	#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /!< Channel 1 Half Transfer flag /
		3913	#define DMA_ISR_TEIF1_Pos (3U)
		3914	#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /!< 0x00000008 /
		3915	#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /!< Channel 1 Transfer Error flag /
		3916	#define DMA_ISR_GIF2_Pos (4U)
		3917	#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /!< 0x00000010 /
		3918	#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /!< Channel 2 Global interrupt flag /
		3919	#define DMA_ISR_TCIF2_Pos (5U)
		3920	#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /!< 0x00000020 /
		3921	#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /!< Channel 2 Transfer Complete flag /
		3922	#define DMA_ISR_HTIF2_Pos (6U)
		3923	#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /!< 0x00000040 /
		3924	#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /!< Channel 2 Half Transfer flag /
		3925	#define DMA_ISR_TEIF2_Pos (7U)
		3926	#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /!< 0x00000080 /
		3927	#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /!< Channel 2 Transfer Error flag /
		3928	#define DMA_ISR_GIF3_Pos (8U)
		3929	#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /!< 0x00000100 /
		3930	#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /!< Channel 3 Global interrupt flag /
		3931	#define DMA_ISR_TCIF3_Pos (9U)
		3932	#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /!< 0x00000200 /
		3933	#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /!< Channel 3 Transfer Complete flag /
		3934	#define DMA_ISR_HTIF3_Pos (10U)
		3935	#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /!< 0x00000400 /
		3936	#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /!< Channel 3 Half Transfer flag /
		3937	#define DMA_ISR_TEIF3_Pos (11U)
		3938	#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /!< 0x00000800 /
		3939	#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /!< Channel 3 Transfer Error flag /
		3940	#define DMA_ISR_GIF4_Pos (12U)
		3941	#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /!< 0x00001000 /
		3942	#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /!< Channel 4 Global interrupt flag /
		3943	#define DMA_ISR_TCIF4_Pos (13U)
		3944	#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /!< 0x00002000 /
		3945	#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /!< Channel 4 Transfer Complete flag /
		3946	#define DMA_ISR_HTIF4_Pos (14U)
		3947	#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /!< 0x00004000 /
		3948	#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /!< Channel 4 Half Transfer flag /
		3949	#define DMA_ISR_TEIF4_Pos (15U)
		3950	#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /!< 0x00008000 /
		3951	#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /!< Channel 4 Transfer Error flag /
		3952	#define DMA_ISR_GIF5_Pos (16U)
		3953	#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /!< 0x00010000 /
		3954	#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /!< Channel 5 Global interrupt flag /
		3955	#define DMA_ISR_TCIF5_Pos (17U)
		3956	#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /!< 0x00020000 /
		3957	#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /!< Channel 5 Transfer Complete flag /
		3958	#define DMA_ISR_HTIF5_Pos (18U)
		3959	#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /!< 0x00040000 /
		3960	#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /!< Channel 5 Half Transfer flag /
		3961	#define DMA_ISR_TEIF5_Pos (19U)
		3962	#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /!< 0x00080000 /
		3963	#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /!< Channel 5 Transfer Error flag /
		3964	#define DMA_ISR_GIF6_Pos (20U)
		3965	#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /!< 0x00100000 /
		3966	#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /!< Channel 6 Global interrupt flag /
		3967	#define DMA_ISR_TCIF6_Pos (21U)
		3968	#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /!< 0x00200000 /
		3969	#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /!< Channel 6 Transfer Complete flag /
		3970	#define DMA_ISR_HTIF6_Pos (22U)
		3971	#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /!< 0x00400000 /
		3972	#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /!< Channel 6 Half Transfer flag /
		3973	#define DMA_ISR_TEIF6_Pos (23U)
		3974	#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /!< 0x00800000 /
		3975	#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /!< Channel 6 Transfer Error flag /
		3976	#define DMA_ISR_GIF7_Pos (24U)
		3977	#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /!< 0x01000000 /
		3978	#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /!< Channel 7 Global interrupt flag /
		3979	#define DMA_ISR_TCIF7_Pos (25U)
		3980	#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /!< 0x02000000 /
		3981	#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /!< Channel 7 Transfer Complete flag /
		3982	#define DMA_ISR_HTIF7_Pos (26U)
		3983	#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /!< 0x04000000 /
		3984	#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /!< Channel 7 Half Transfer flag /
		3985	#define DMA_ISR_TEIF7_Pos (27U)
		3986	#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /!< 0x08000000 /
		3987	#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /!< Channel 7 Transfer Error flag /
2	mjames	3988
		3989	/***************** Bit definition for DMA_IFCR register *****************/
5	mjames	3990	#define DMA_IFCR_CGIF1_Pos (0U)
		3991	#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /!< 0x00000001 /
		3992	#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /!< Channel 1 Global interrupt clear /
		3993	#define DMA_IFCR_CTCIF1_Pos (1U)
		3994	#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /!< 0x00000002 /
		3995	#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /!< Channel 1 Transfer Complete clear /
		3996	#define DMA_IFCR_CHTIF1_Pos (2U)
		3997	#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /!< 0x00000004 /
		3998	#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /!< Channel 1 Half Transfer clear /
		3999	#define DMA_IFCR_CTEIF1_Pos (3U)
		4000	#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /!< 0x00000008 /
		4001	#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /!< Channel 1 Transfer Error clear /
		4002	#define DMA_IFCR_CGIF2_Pos (4U)
		4003	#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /!< 0x00000010 /
		4004	#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /!< Channel 2 Global interrupt clear /
		4005	#define DMA_IFCR_CTCIF2_Pos (5U)
		4006	#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /!< 0x00000020 /
		4007	#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /!< Channel 2 Transfer Complete clear /
		4008	#define DMA_IFCR_CHTIF2_Pos (6U)
		4009	#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /!< 0x00000040 /
		4010	#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /!< Channel 2 Half Transfer clear /
		4011	#define DMA_IFCR_CTEIF2_Pos (7U)
		4012	#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /!< 0x00000080 /
		4013	#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /!< Channel 2 Transfer Error clear /
		4014	#define DMA_IFCR_CGIF3_Pos (8U)
		4015	#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /!< 0x00000100 /
		4016	#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /!< Channel 3 Global interrupt clear /
		4017	#define DMA_IFCR_CTCIF3_Pos (9U)
		4018	#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /!< 0x00000200 /
		4019	#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /!< Channel 3 Transfer Complete clear /
		4020	#define DMA_IFCR_CHTIF3_Pos (10U)
		4021	#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /!< 0x00000400 /
		4022	#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /!< Channel 3 Half Transfer clear /
		4023	#define DMA_IFCR_CTEIF3_Pos (11U)
		4024	#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /!< 0x00000800 /
		4025	#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /!< Channel 3 Transfer Error clear /
		4026	#define DMA_IFCR_CGIF4_Pos (12U)
		4027	#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /!< 0x00001000 /
		4028	#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /!< Channel 4 Global interrupt clear /
		4029	#define DMA_IFCR_CTCIF4_Pos (13U)
		4030	#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /!< 0x00002000 /
		4031	#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /!< Channel 4 Transfer Complete clear /
		4032	#define DMA_IFCR_CHTIF4_Pos (14U)
		4033	#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /!< 0x00004000 /
		4034	#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /!< Channel 4 Half Transfer clear /
		4035	#define DMA_IFCR_CTEIF4_Pos (15U)
		4036	#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /!< 0x00008000 /
		4037	#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /!< Channel 4 Transfer Error clear /
		4038	#define DMA_IFCR_CGIF5_Pos (16U)
		4039	#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /!< 0x00010000 /
		4040	#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /!< Channel 5 Global interrupt clear /
		4041	#define DMA_IFCR_CTCIF5_Pos (17U)
		4042	#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /!< 0x00020000 /
		4043	#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /!< Channel 5 Transfer Complete clear /
		4044	#define DMA_IFCR_CHTIF5_Pos (18U)
		4045	#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /!< 0x00040000 /
		4046	#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /!< Channel 5 Half Transfer clear /
		4047	#define DMA_IFCR_CTEIF5_Pos (19U)
		4048	#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /!< 0x00080000 /
		4049	#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /!< Channel 5 Transfer Error clear /
		4050	#define DMA_IFCR_CGIF6_Pos (20U)
		4051	#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /!< 0x00100000 /
		4052	#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /!< Channel 6 Global interrupt clear /
		4053	#define DMA_IFCR_CTCIF6_Pos (21U)
		4054	#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /!< 0x00200000 /
		4055	#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /!< Channel 6 Transfer Complete clear /
		4056	#define DMA_IFCR_CHTIF6_Pos (22U)
		4057	#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /!< 0x00400000 /
		4058	#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /!< Channel 6 Half Transfer clear /
		4059	#define DMA_IFCR_CTEIF6_Pos (23U)
		4060	#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /!< 0x00800000 /
		4061	#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /!< Channel 6 Transfer Error clear /
		4062	#define DMA_IFCR_CGIF7_Pos (24U)
		4063	#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /!< 0x01000000 /
		4064	#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /!< Channel 7 Global interrupt clear /
		4065	#define DMA_IFCR_CTCIF7_Pos (25U)
		4066	#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /!< 0x02000000 /
		4067	#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /!< Channel 7 Transfer Complete clear /
		4068	#define DMA_IFCR_CHTIF7_Pos (26U)
		4069	#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /!< 0x04000000 /
		4070	#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /!< Channel 7 Half Transfer clear /
		4071	#define DMA_IFCR_CTEIF7_Pos (27U)
		4072	#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /!< 0x08000000 /
		4073	#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /!< Channel 7 Transfer Error clear /
2	mjames	4074
		4075	/***************** Bit definition for DMA_CCR register *****************/
5	mjames	4076	#define DMA_CCR_EN_Pos (0U)
		4077	#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /!< 0x00000001 /
		4078	#define DMA_CCR_EN DMA_CCR_EN_Msk /!< Channel enable /
		4079	#define DMA_CCR_TCIE_Pos (1U)
		4080	#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /!< 0x00000002 /
		4081	#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /!< Transfer complete interrupt enable /
		4082	#define DMA_CCR_HTIE_Pos (2U)
		4083	#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /!< 0x00000004 /
		4084	#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /!< Half Transfer interrupt enable /
		4085	#define DMA_CCR_TEIE_Pos (3U)
		4086	#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /!< 0x00000008 /
		4087	#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /!< Transfer error interrupt enable /
		4088	#define DMA_CCR_DIR_Pos (4U)
		4089	#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /!< 0x00000010 /
		4090	#define DMA_CCR_DIR DMA_CCR_DIR_Msk /!< Data transfer direction /
		4091	#define DMA_CCR_CIRC_Pos (5U)
		4092	#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /!< 0x00000020 /
		4093	#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /!< Circular mode /
		4094	#define DMA_CCR_PINC_Pos (6U)
		4095	#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /!< 0x00000040 /
		4096	#define DMA_CCR_PINC DMA_CCR_PINC_Msk /!< Peripheral increment mode /
		4097	#define DMA_CCR_MINC_Pos (7U)
		4098	#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /!< 0x00000080 /
		4099	#define DMA_CCR_MINC DMA_CCR_MINC_Msk /!< Memory increment mode /
2	mjames	4100
5	mjames	4101	#define DMA_CCR_PSIZE_Pos (8U)
		4102	#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /!< 0x00000300 /
		4103	#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /!< PSIZE[1:0] bits (Peripheral size) /
		4104	#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /!< 0x00000100 /
		4105	#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /!< 0x00000200 /
2	mjames	4106
5	mjames	4107	#define DMA_CCR_MSIZE_Pos (10U)
		4108	#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /!< 0x00000C00 /
		4109	#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /!< MSIZE[1:0] bits (Memory size) /
		4110	#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /!< 0x00000400 /
		4111	#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /!< 0x00000800 /
2	mjames	4112
5	mjames	4113	#define DMA_CCR_PL_Pos (12U)
		4114	#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /!< 0x00003000 /
		4115	#define DMA_CCR_PL DMA_CCR_PL_Msk /!< PL[1:0] bits(Channel Priority level) /
		4116	#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /!< 0x00001000 /
		4117	#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /!< 0x00002000 /
2	mjames	4118
5	mjames	4119	#define DMA_CCR_MEM2MEM_Pos (14U)
		4120	#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /!< 0x00004000 /
		4121	#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /!< Memory to memory mode /
2	mjames	4122
		4123	/**************** Bit definition for DMA_CNDTR register ****************/
5	mjames	4124	#define DMA_CNDTR_NDT_Pos (0U)
		4125	#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /!< 0x0000FFFF /
		4126	#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /!< Number of data to Transfer /
2	mjames	4127
		4128	/**************** Bit definition for DMA_CPAR register *****************/
5	mjames	4129	#define DMA_CPAR_PA_Pos (0U)
		4130	#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /!< 0xFFFFFFFF /
		4131	#define DMA_CPAR_PA DMA_CPAR_PA_Msk /!< Peripheral Address /
2	mjames	4132
		4133	/**************** Bit definition for DMA_CMAR register *****************/
5	mjames	4134	#define DMA_CMAR_MA_Pos (0U)
		4135	#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /!< 0xFFFFFFFF /
		4136	#define DMA_CMAR_MA DMA_CMAR_MA_Msk /!< Memory Address /
2	mjames	4137
		4138	/******************************************************************************/
		4139	/* */
5	mjames	4140	/* Analog to Digital Converter (ADC) */
2	mjames	4141	/* */
		4142	/******************************************************************************/
		4143
5	mjames	4144	/*
		4145	* @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
		4146	*/
		4147	/* Note: No specific macro feature on this device */
		4148
2	mjames	4149	/****************** Bit definition for ADC_SR register ******************/
5	mjames	4150	#define ADC_SR_AWD_Pos (0U)
		4151	#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /!< 0x00000001 /
		4152	#define ADC_SR_AWD ADC_SR_AWD_Msk /!< ADC analog watchdog 1 flag /
		4153	#define ADC_SR_EOS_Pos (1U)
		4154	#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /!< 0x00000002 /
		4155	#define ADC_SR_EOS ADC_SR_EOS_Msk /!< ADC group regular end of sequence conversions flag /
		4156	#define ADC_SR_JEOS_Pos (2U)
		4157	#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /!< 0x00000004 /
		4158	#define ADC_SR_JEOS ADC_SR_JEOS_Msk /!< ADC group injected end of sequence conversions flag /
		4159	#define ADC_SR_JSTRT_Pos (3U)
		4160	#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /!< 0x00000008 /
		4161	#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /!< ADC group injected conversion start flag /
		4162	#define ADC_SR_STRT_Pos (4U)
		4163	#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /!< 0x00000010 /
		4164	#define ADC_SR_STRT ADC_SR_STRT_Msk /!< ADC group regular conversion start flag /
2	mjames	4165
5	mjames	4166	/* Legacy defines */
		4167	#define ADC_SR_EOC (ADC_SR_EOS)
		4168	#define ADC_SR_JEOC (ADC_SR_JEOS)
		4169
2	mjames	4170	/***************** Bit definition for ADC_CR1 register ******************/
5	mjames	4171	#define ADC_CR1_AWDCH_Pos (0U)
		4172	#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /!< 0x0000001F /
		4173	#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /!< ADC analog watchdog 1 monitored channel selection /
		4174	#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /!< 0x00000001 /
		4175	#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /!< 0x00000002 /
		4176	#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /!< 0x00000004 /
		4177	#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /!< 0x00000008 /
		4178	#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /!< 0x00000010 /
2	mjames	4179
5	mjames	4180	#define ADC_CR1_EOSIE_Pos (5U)
		4181	#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /!< 0x00000020 /
		4182	#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /!< ADC group regular end of sequence conversions interrupt /
		4183	#define ADC_CR1_AWDIE_Pos (6U)
		4184	#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /!< 0x00000040 /
		4185	#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /!< ADC analog watchdog 1 interrupt /
		4186	#define ADC_CR1_JEOSIE_Pos (7U)
		4187	#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /!< 0x00000080 /
		4188	#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /!< ADC group injected end of sequence conversions interrupt /
		4189	#define ADC_CR1_SCAN_Pos (8U)
		4190	#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /!< 0x00000100 /
		4191	#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /!< ADC scan mode /
		4192	#define ADC_CR1_AWDSGL_Pos (9U)
		4193	#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /!< 0x00000200 /
		4194	#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /!< ADC analog watchdog 1 monitoring a single channel or all channels /
		4195	#define ADC_CR1_JAUTO_Pos (10U)
		4196	#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /!< 0x00000400 /
		4197	#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /!< ADC group injected automatic trigger mode /
		4198	#define ADC_CR1_DISCEN_Pos (11U)
		4199	#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /!< 0x00000800 /
		4200	#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /
		4201	#define ADC_CR1_JDISCEN_Pos (12U)
		4202	#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /!< 0x00001000 /
		4203	#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /!< ADC group injected sequencer discontinuous mode /
2	mjames	4204
5	mjames	4205	#define ADC_CR1_DISCNUM_Pos (13U)
		4206	#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /!< 0x0000E000 /
		4207	#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /!< ADC group regular sequencer discontinuous number of ranks /
		4208	#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /!< 0x00002000 /
		4209	#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /!< 0x00004000 /
		4210	#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /!< 0x00008000 /
2	mjames	4211
5	mjames	4212	#define ADC_CR1_JAWDEN_Pos (22U)
		4213	#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /!< 0x00400000 /
		4214	#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group injected /
		4215	#define ADC_CR1_AWDEN_Pos (23U)
		4216	#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /!< 0x00800000 /
		4217	#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group regular /
2	mjames	4218
5	mjames	4219	/* Legacy defines */
		4220	#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
		4221	#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
		4222
2	mjames	4223	/***************** Bit definition for ADC_CR2 register ******************/
5	mjames	4224	#define ADC_CR2_ADON_Pos (0U)
		4225	#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /!< 0x00000001 /
		4226	#define ADC_CR2_ADON ADC_CR2_ADON_Msk /!< ADC enable /
		4227	#define ADC_CR2_CONT_Pos (1U)
		4228	#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /!< 0x00000002 /
		4229	#define ADC_CR2_CONT ADC_CR2_CONT_Msk /!< ADC group regular continuous conversion mode /
		4230	#define ADC_CR2_CAL_Pos (2U)
		4231	#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /!< 0x00000004 /
		4232	#define ADC_CR2_CAL ADC_CR2_CAL_Msk /!< ADC calibration start /
		4233	#define ADC_CR2_RSTCAL_Pos (3U)
		4234	#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /!< 0x00000008 /
		4235	#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /!< ADC calibration reset /
		4236	#define ADC_CR2_DMA_Pos (8U)
		4237	#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /!< 0x00000100 /
		4238	#define ADC_CR2_DMA ADC_CR2_DMA_Msk /!< ADC DMA transfer enable /
		4239	#define ADC_CR2_ALIGN_Pos (11U)
		4240	#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /!< 0x00000800 /
		4241	#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /!< ADC data alignement /
2	mjames	4242
5	mjames	4243	#define ADC_CR2_JEXTSEL_Pos (12U)
		4244	#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /!< 0x00007000 /
		4245	#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /!< ADC group injected external trigger source /
		4246	#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /!< 0x00001000 /
		4247	#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /!< 0x00002000 /
		4248	#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /!< 0x00004000 /
2	mjames	4249
5	mjames	4250	#define ADC_CR2_JEXTTRIG_Pos (15U)
		4251	#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /!< 0x00008000 /
		4252	#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /!< ADC group injected external trigger enable /
2	mjames	4253
5	mjames	4254	#define ADC_CR2_EXTSEL_Pos (17U)
		4255	#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /!< 0x000E0000 /
		4256	#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /!< ADC group regular external trigger source /
		4257	#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /!< 0x00020000 /
		4258	#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /!< 0x00040000 /
		4259	#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /!< 0x00080000 /
2	mjames	4260
5	mjames	4261	#define ADC_CR2_EXTTRIG_Pos (20U)
		4262	#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /!< 0x00100000 /
		4263	#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /!< ADC group regular external trigger enable /
		4264	#define ADC_CR2_JSWSTART_Pos (21U)
		4265	#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /!< 0x00200000 /
		4266	#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /!< ADC group injected conversion start /
		4267	#define ADC_CR2_SWSTART_Pos (22U)
		4268	#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /!< 0x00400000 /
		4269	#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /!< ADC group regular conversion start /
		4270	#define ADC_CR2_TSVREFE_Pos (23U)
		4271	#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /!< 0x00800000 /
		4272	#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /!< ADC internal path to VrefInt and temperature sensor enable /
2	mjames	4273
		4274	/**************** Bit definition for ADC_SMPR1 register *****************/
5	mjames	4275	#define ADC_SMPR1_SMP10_Pos (0U)
		4276	#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /!< 0x00000007 /
		4277	#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /!< ADC channel 10 sampling time selection /
		4278	#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /!< 0x00000001 /
		4279	#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /!< 0x00000002 /
		4280	#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /!< 0x00000004 /
2	mjames	4281
5	mjames	4282	#define ADC_SMPR1_SMP11_Pos (3U)
		4283	#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /!< 0x00000038 /
		4284	#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /!< ADC channel 11 sampling time selection /
		4285	#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /!< 0x00000008 /
		4286	#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /!< 0x00000010 /
		4287	#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /!< 0x00000020 /
2	mjames	4288
5	mjames	4289	#define ADC_SMPR1_SMP12_Pos (6U)
		4290	#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /!< 0x000001C0 /
		4291	#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /!< ADC channel 12 sampling time selection /
		4292	#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /!< 0x00000040 /
		4293	#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /!< 0x00000080 /
		4294	#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /!< 0x00000100 /
2	mjames	4295
5	mjames	4296	#define ADC_SMPR1_SMP13_Pos (9U)
		4297	#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /!< 0x00000E00 /
		4298	#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /!< ADC channel 13 sampling time selection /
		4299	#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /!< 0x00000200 /
		4300	#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /!< 0x00000400 /
		4301	#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /!< 0x00000800 /
2	mjames	4302
5	mjames	4303	#define ADC_SMPR1_SMP14_Pos (12U)
		4304	#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /!< 0x00007000 /
		4305	#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /!< ADC channel 14 sampling time selection /
		4306	#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /!< 0x00001000 /
		4307	#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /!< 0x00002000 /
		4308	#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /!< 0x00004000 /
2	mjames	4309
5	mjames	4310	#define ADC_SMPR1_SMP15_Pos (15U)
		4311	#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /!< 0x00038000 /
		4312	#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /!< ADC channel 15 sampling time selection /
		4313	#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /!< 0x00008000 /
		4314	#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /!< 0x00010000 /
		4315	#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /!< 0x00020000 /
2	mjames	4316
5	mjames	4317	#define ADC_SMPR1_SMP16_Pos (18U)
		4318	#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /!< 0x001C0000 /
		4319	#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /!< ADC channel 16 sampling time selection /
		4320	#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /!< 0x00040000 /
		4321	#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /!< 0x00080000 /
		4322	#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /!< 0x00100000 /
2	mjames	4323
5	mjames	4324	#define ADC_SMPR1_SMP17_Pos (21U)
		4325	#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /!< 0x00E00000 /
		4326	#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /!< ADC channel 17 sampling time selection /
		4327	#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /!< 0x00200000 /
		4328	#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /!< 0x00400000 /
		4329	#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /!< 0x00800000 /
2	mjames	4330
		4331	/**************** Bit definition for ADC_SMPR2 register *****************/
5	mjames	4332	#define ADC_SMPR2_SMP0_Pos (0U)
		4333	#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /!< 0x00000007 /
		4334	#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /!< ADC channel 0 sampling time selection /
		4335	#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /!< 0x00000001 /
		4336	#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /!< 0x00000002 /
		4337	#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /!< 0x00000004 /
2	mjames	4338
5	mjames	4339	#define ADC_SMPR2_SMP1_Pos (3U)
		4340	#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /!< 0x00000038 /
		4341	#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /!< ADC channel 1 sampling time selection /
		4342	#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /!< 0x00000008 /
		4343	#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /!< 0x00000010 /
		4344	#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /!< 0x00000020 /
2	mjames	4345
5	mjames	4346	#define ADC_SMPR2_SMP2_Pos (6U)
		4347	#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /!< 0x000001C0 /
		4348	#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /!< ADC channel 2 sampling time selection /
		4349	#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /!< 0x00000040 /
		4350	#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /!< 0x00000080 /
		4351	#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /!< 0x00000100 /
2	mjames	4352
5	mjames	4353	#define ADC_SMPR2_SMP3_Pos (9U)
		4354	#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /!< 0x00000E00 /
		4355	#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /!< ADC channel 3 sampling time selection /
		4356	#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /!< 0x00000200 /
		4357	#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /!< 0x00000400 /
		4358	#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /!< 0x00000800 /
2	mjames	4359
5	mjames	4360	#define ADC_SMPR2_SMP4_Pos (12U)
		4361	#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /!< 0x00007000 /
		4362	#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /!< ADC channel 4 sampling time selection /
		4363	#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /!< 0x00001000 /
		4364	#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /!< 0x00002000 /
		4365	#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /!< 0x00004000 /
2	mjames	4366
5	mjames	4367	#define ADC_SMPR2_SMP5_Pos (15U)
		4368	#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /!< 0x00038000 /
		4369	#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /!< ADC channel 5 sampling time selection /
		4370	#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /!< 0x00008000 /
		4371	#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /!< 0x00010000 /
		4372	#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /!< 0x00020000 /
2	mjames	4373
5	mjames	4374	#define ADC_SMPR2_SMP6_Pos (18U)
		4375	#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /!< 0x001C0000 /
		4376	#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /!< ADC channel 6 sampling time selection /
		4377	#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /!< 0x00040000 /
		4378	#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /!< 0x00080000 /
		4379	#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /!< 0x00100000 /
2	mjames	4380
5	mjames	4381	#define ADC_SMPR2_SMP7_Pos (21U)
		4382	#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /!< 0x00E00000 /
		4383	#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /!< ADC channel 7 sampling time selection /
		4384	#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /!< 0x00200000 /
		4385	#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /!< 0x00400000 /
		4386	#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /!< 0x00800000 /
2	mjames	4387
5	mjames	4388	#define ADC_SMPR2_SMP8_Pos (24U)
		4389	#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /!< 0x07000000 /
		4390	#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /!< ADC channel 8 sampling time selection /
		4391	#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /!< 0x01000000 /
		4392	#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /!< 0x02000000 /
		4393	#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /!< 0x04000000 /
2	mjames	4394
5	mjames	4395	#define ADC_SMPR2_SMP9_Pos (27U)
		4396	#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /!< 0x38000000 /
		4397	#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /!< ADC channel 9 sampling time selection /
		4398	#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /!< 0x08000000 /
		4399	#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /!< 0x10000000 /
		4400	#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /!< 0x20000000 /
2	mjames	4401
		4402	/**************** Bit definition for ADC_JOFR1 register *****************/
5	mjames	4403	#define ADC_JOFR1_JOFFSET1_Pos (0U)
		4404	#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /!< 0x00000FFF /
		4405	#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /!< ADC group injected sequencer rank 1 offset value /
2	mjames	4406
		4407	/**************** Bit definition for ADC_JOFR2 register *****************/
5	mjames	4408	#define ADC_JOFR2_JOFFSET2_Pos (0U)
		4409	#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /!< 0x00000FFF /
		4410	#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /!< ADC group injected sequencer rank 2 offset value /
2	mjames	4411
		4412	/**************** Bit definition for ADC_JOFR3 register *****************/
5	mjames	4413	#define ADC_JOFR3_JOFFSET3_Pos (0U)
		4414	#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /!< 0x00000FFF /
		4415	#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /!< ADC group injected sequencer rank 3 offset value /
2	mjames	4416
		4417	/**************** Bit definition for ADC_JOFR4 register *****************/
5	mjames	4418	#define ADC_JOFR4_JOFFSET4_Pos (0U)
		4419	#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /!< 0x00000FFF /
		4420	#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /!< ADC group injected sequencer rank 4 offset value /
2	mjames	4421
		4422	/***************** Bit definition for ADC_HTR register ******************/
5	mjames	4423	#define ADC_HTR_HT_Pos (0U)
		4424	#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /!< 0x00000FFF /
		4425	#define ADC_HTR_HT ADC_HTR_HT_Msk /!< ADC analog watchdog 1 threshold high /
2	mjames	4426
		4427	/***************** Bit definition for ADC_LTR register ******************/
5	mjames	4428	#define ADC_LTR_LT_Pos (0U)
		4429	#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /!< 0x00000FFF /
		4430	#define ADC_LTR_LT ADC_LTR_LT_Msk /!< ADC analog watchdog 1 threshold low /
2	mjames	4431
		4432	/***************** Bit definition for ADC_SQR1 register *****************/
5	mjames	4433	#define ADC_SQR1_SQ13_Pos (0U)
		4434	#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /!< 0x0000001F /
		4435	#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /!< ADC group regular sequencer rank 13 /
		4436	#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /!< 0x00000001 /
		4437	#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /!< 0x00000002 /
		4438	#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /!< 0x00000004 /
		4439	#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /!< 0x00000008 /
		4440	#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /!< 0x00000010 /
2	mjames	4441
5	mjames	4442	#define ADC_SQR1_SQ14_Pos (5U)
		4443	#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /!< 0x000003E0 /
		4444	#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /!< ADC group regular sequencer rank 14 /
		4445	#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /!< 0x00000020 /
		4446	#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /!< 0x00000040 /
		4447	#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /!< 0x00000080 /
		4448	#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /!< 0x00000100 /
		4449	#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /!< 0x00000200 /
2	mjames	4450
5	mjames	4451	#define ADC_SQR1_SQ15_Pos (10U)
		4452	#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /!< 0x00007C00 /
		4453	#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /!< ADC group regular sequencer rank 15 /
		4454	#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /!< 0x00000400 /
		4455	#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /!< 0x00000800 /
		4456	#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /!< 0x00001000 /
		4457	#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /!< 0x00002000 /
		4458	#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /!< 0x00004000 /
2	mjames	4459
5	mjames	4460	#define ADC_SQR1_SQ16_Pos (15U)
		4461	#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /!< 0x000F8000 /
		4462	#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /!< ADC group regular sequencer rank 16 /
		4463	#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /!< 0x00008000 /
		4464	#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /!< 0x00010000 /
		4465	#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /!< 0x00020000 /
		4466	#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /!< 0x00040000 /
		4467	#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /!< 0x00080000 /
2	mjames	4468
5	mjames	4469	#define ADC_SQR1_L_Pos (20U)
		4470	#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /!< 0x00F00000 /
		4471	#define ADC_SQR1_L ADC_SQR1_L_Msk /!< ADC group regular sequencer scan length /
		4472	#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /!< 0x00100000 /
		4473	#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /!< 0x00200000 /
		4474	#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /!< 0x00400000 /
		4475	#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /!< 0x00800000 /
2	mjames	4476
		4477	/***************** Bit definition for ADC_SQR2 register *****************/
5	mjames	4478	#define ADC_SQR2_SQ7_Pos (0U)
		4479	#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /!< 0x0000001F /
		4480	#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /!< ADC group regular sequencer rank 7 /
		4481	#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /!< 0x00000001 /
		4482	#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /!< 0x00000002 /
		4483	#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /!< 0x00000004 /
		4484	#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /!< 0x00000008 /
		4485	#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /!< 0x00000010 /
2	mjames	4486
5	mjames	4487	#define ADC_SQR2_SQ8_Pos (5U)
		4488	#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /!< 0x000003E0 /
		4489	#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /!< ADC group regular sequencer rank 8 /
		4490	#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /!< 0x00000020 /
		4491	#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /!< 0x00000040 /
		4492	#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /!< 0x00000080 /
		4493	#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /!< 0x00000100 /
		4494	#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /!< 0x00000200 /
2	mjames	4495
5	mjames	4496	#define ADC_SQR2_SQ9_Pos (10U)
		4497	#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /!< 0x00007C00 /
		4498	#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /!< ADC group regular sequencer rank 9 /
		4499	#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /!< 0x00000400 /
		4500	#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /!< 0x00000800 /
		4501	#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /!< 0x00001000 /
		4502	#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /!< 0x00002000 /
		4503	#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /!< 0x00004000 /
2	mjames	4504
5	mjames	4505	#define ADC_SQR2_SQ10_Pos (15U)
		4506	#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /!< 0x000F8000 /
		4507	#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /!< ADC group regular sequencer rank 10 /
		4508	#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /!< 0x00008000 /
		4509	#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /!< 0x00010000 /
		4510	#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /!< 0x00020000 /
		4511	#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /!< 0x00040000 /
		4512	#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /!< 0x00080000 /
2	mjames	4513
5	mjames	4514	#define ADC_SQR2_SQ11_Pos (20U)
		4515	#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /!< 0x01F00000 /
		4516	#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /!< ADC group regular sequencer rank 1 /
		4517	#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /!< 0x00100000 /
		4518	#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /!< 0x00200000 /
		4519	#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /!< 0x00400000 /
		4520	#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /!< 0x00800000 /
		4521	#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /!< 0x01000000 /
2	mjames	4522
5	mjames	4523	#define ADC_SQR2_SQ12_Pos (25U)
		4524	#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /!< 0x3E000000 /
		4525	#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /!< ADC group regular sequencer rank 12 /
		4526	#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /!< 0x02000000 /
		4527	#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /!< 0x04000000 /
		4528	#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /!< 0x08000000 /
		4529	#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /!< 0x10000000 /
		4530	#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /!< 0x20000000 /
2	mjames	4531
		4532	/***************** Bit definition for ADC_SQR3 register *****************/
5	mjames	4533	#define ADC_SQR3_SQ1_Pos (0U)
		4534	#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /!< 0x0000001F /
		4535	#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /!< ADC group regular sequencer rank 1 /
		4536	#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /!< 0x00000001 /
		4537	#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /!< 0x00000002 /
		4538	#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /!< 0x00000004 /
		4539	#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /!< 0x00000008 /
		4540	#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /!< 0x00000010 /
2	mjames	4541
5	mjames	4542	#define ADC_SQR3_SQ2_Pos (5U)
		4543	#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /!< 0x000003E0 /
		4544	#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /!< ADC group regular sequencer rank 2 /
		4545	#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /!< 0x00000020 /
		4546	#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /!< 0x00000040 /
		4547	#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /!< 0x00000080 /
		4548	#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /!< 0x00000100 /
		4549	#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /!< 0x00000200 /
2	mjames	4550
5	mjames	4551	#define ADC_SQR3_SQ3_Pos (10U)
		4552	#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /!< 0x00007C00 /
		4553	#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /!< ADC group regular sequencer rank 3 /
		4554	#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /!< 0x00000400 /
		4555	#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /!< 0x00000800 /
		4556	#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /!< 0x00001000 /
		4557	#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /!< 0x00002000 /
		4558	#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /!< 0x00004000 /
2	mjames	4559
5	mjames	4560	#define ADC_SQR3_SQ4_Pos (15U)
		4561	#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /!< 0x000F8000 /
		4562	#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /!< ADC group regular sequencer rank 4 /
		4563	#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /!< 0x00008000 /
		4564	#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /!< 0x00010000 /
		4565	#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /!< 0x00020000 /
		4566	#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /!< 0x00040000 /
		4567	#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /!< 0x00080000 /
2	mjames	4568
5	mjames	4569	#define ADC_SQR3_SQ5_Pos (20U)
		4570	#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /!< 0x01F00000 /
		4571	#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /!< ADC group regular sequencer rank 5 /
		4572	#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /!< 0x00100000 /
		4573	#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /!< 0x00200000 /
		4574	#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /!< 0x00400000 /
		4575	#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /!< 0x00800000 /
		4576	#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /!< 0x01000000 /
2	mjames	4577
5	mjames	4578	#define ADC_SQR3_SQ6_Pos (25U)
		4579	#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /!< 0x3E000000 /
		4580	#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /!< ADC group regular sequencer rank 6 /
		4581	#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /!< 0x02000000 /
		4582	#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /!< 0x04000000 /
		4583	#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /!< 0x08000000 /
		4584	#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /!< 0x10000000 /
		4585	#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /!< 0x20000000 /
2	mjames	4586
		4587	/***************** Bit definition for ADC_JSQR register *****************/
5	mjames	4588	#define ADC_JSQR_JSQ1_Pos (0U)
		4589	#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /!< 0x0000001F /
		4590	#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /!< ADC group injected sequencer rank 1 /
		4591	#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /!< 0x00000001 /
		4592	#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /!< 0x00000002 /
		4593	#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /!< 0x00000004 /
		4594	#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /!< 0x00000008 /
		4595	#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /!< 0x00000010 /
2	mjames	4596
5	mjames	4597	#define ADC_JSQR_JSQ2_Pos (5U)
		4598	#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /!< 0x000003E0 /
		4599	#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /!< ADC group injected sequencer rank 2 /
		4600	#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /!< 0x00000020 /
		4601	#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /!< 0x00000040 /
		4602	#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /!< 0x00000080 /
		4603	#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /!< 0x00000100 /
		4604	#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /!< 0x00000200 /
2	mjames	4605
5	mjames	4606	#define ADC_JSQR_JSQ3_Pos (10U)
		4607	#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /!< 0x00007C00 /
		4608	#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /!< ADC group injected sequencer rank 3 /
		4609	#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /!< 0x00000400 /
		4610	#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /!< 0x00000800 /
		4611	#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /!< 0x00001000 /
		4612	#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /!< 0x00002000 /
		4613	#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /!< 0x00004000 /
2	mjames	4614
5	mjames	4615	#define ADC_JSQR_JSQ4_Pos (15U)
		4616	#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /!< 0x000F8000 /
		4617	#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /!< ADC group injected sequencer rank 4 /
		4618	#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /!< 0x00008000 /
		4619	#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /!< 0x00010000 /
		4620	#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /!< 0x00020000 /
		4621	#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /!< 0x00040000 /
		4622	#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /!< 0x00080000 /
2	mjames	4623
5	mjames	4624	#define ADC_JSQR_JL_Pos (20U)
		4625	#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /!< 0x00300000 /
		4626	#define ADC_JSQR_JL ADC_JSQR_JL_Msk /!< ADC group injected sequencer scan length /
		4627	#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /!< 0x00100000 /
		4628	#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /!< 0x00200000 /
2	mjames	4629
		4630	/***************** Bit definition for ADC_JDR1 register *****************/
5	mjames	4631	#define ADC_JDR1_JDATA_Pos (0U)
		4632	#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /!< 0x0000FFFF /
		4633	#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /!< ADC group injected sequencer rank 1 conversion data /
2	mjames	4634
		4635	/***************** Bit definition for ADC_JDR2 register *****************/
5	mjames	4636	#define ADC_JDR2_JDATA_Pos (0U)
		4637	#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /!< 0x0000FFFF /
		4638	#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /!< ADC group injected sequencer rank 2 conversion data /
2	mjames	4639
		4640	/***************** Bit definition for ADC_JDR3 register *****************/
5	mjames	4641	#define ADC_JDR3_JDATA_Pos (0U)
		4642	#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /!< 0x0000FFFF /
		4643	#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /!< ADC group injected sequencer rank 3 conversion data /
2	mjames	4644
		4645	/***************** Bit definition for ADC_JDR4 register *****************/
5	mjames	4646	#define ADC_JDR4_JDATA_Pos (0U)
		4647	#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /!< 0x0000FFFF /
		4648	#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /!< ADC group injected sequencer rank 4 conversion data /
2	mjames	4649
		4650	/****************** Bit definition for ADC_DR register ******************/
5	mjames	4651	#define ADC_DR_DATA_Pos (0U)
		4652	#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /!< 0x0000FFFF /
		4653	#define ADC_DR_DATA ADC_DR_DATA_Msk /!< ADC group regular conversion data /
2	mjames	4654	/******************************************************************************/
		4655	/* */
		4656	/* Digital to Analog Converter */
		4657	/* */
		4658	/******************************************************************************/
		4659
		4660	/****************** Bit definition for DAC_CR register ******************/
5	mjames	4661	#define DAC_CR_EN1_Pos (0U)
		4662	#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /!< 0x00000001 /
		4663	#define DAC_CR_EN1 DAC_CR_EN1_Msk /!< DAC channel1 enable /
		4664	#define DAC_CR_BOFF1_Pos (1U)
		4665	#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /!< 0x00000002 /
		4666	#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /!< DAC channel1 output buffer disable /
		4667	#define DAC_CR_TEN1_Pos (2U)
		4668	#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /!< 0x00000004 /
		4669	#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /!< DAC channel1 Trigger enable /
2	mjames	4670
5	mjames	4671	#define DAC_CR_TSEL1_Pos (3U)
		4672	#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /!< 0x00000038 /
		4673	#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
		4674	#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /!< 0x00000008 /
		4675	#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /!< 0x00000010 /
		4676	#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /!< 0x00000020 /
2	mjames	4677
5	mjames	4678	#define DAC_CR_WAVE1_Pos (6U)
		4679	#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /!< 0x000000C0 /
		4680	#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
		4681	#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /!< 0x00000040 /
		4682	#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /!< 0x00000080 /
2	mjames	4683
5	mjames	4684	#define DAC_CR_MAMP1_Pos (8U)
		4685	#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /!< 0x00000F00 /
		4686	#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
		4687	#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /!< 0x00000100 /
		4688	#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /!< 0x00000200 /
		4689	#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /!< 0x00000400 /
		4690	#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /!< 0x00000800 /
2	mjames	4691
5	mjames	4692	#define DAC_CR_DMAEN1_Pos (12U)
		4693	#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /!< 0x00001000 /
		4694	#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /!< DAC channel1 DMA enable /
		4695	#define DAC_CR_EN2_Pos (16U)
		4696	#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /!< 0x00010000 /
		4697	#define DAC_CR_EN2 DAC_CR_EN2_Msk /!< DAC channel2 enable /
		4698	#define DAC_CR_BOFF2_Pos (17U)
		4699	#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /!< 0x00020000 /
		4700	#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /!< DAC channel2 output buffer disable /
		4701	#define DAC_CR_TEN2_Pos (18U)
		4702	#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /!< 0x00040000 /
		4703	#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /!< DAC channel2 Trigger enable /
2	mjames	4704
5	mjames	4705	#define DAC_CR_TSEL2_Pos (19U)
		4706	#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /!< 0x00380000 /
		4707	#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
		4708	#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /!< 0x00080000 /
		4709	#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /!< 0x00100000 /
		4710	#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /!< 0x00200000 /
2	mjames	4711
5	mjames	4712	#define DAC_CR_WAVE2_Pos (22U)
		4713	#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /!< 0x00C00000 /
		4714	#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
		4715	#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /!< 0x00400000 /
		4716	#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /!< 0x00800000 /
2	mjames	4717
5	mjames	4718	#define DAC_CR_MAMP2_Pos (24U)
		4719	#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /!< 0x0F000000 /
		4720	#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
		4721	#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /!< 0x01000000 /
		4722	#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /!< 0x02000000 /
		4723	#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /!< 0x04000000 /
		4724	#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /!< 0x08000000 /
2	mjames	4725
5	mjames	4726	#define DAC_CR_DMAEN2_Pos (28U)
		4727	#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /!< 0x10000000 /
		4728	#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /!< DAC channel2 DMA enabled /
2	mjames	4729
5	mjames	4730	#define DAC_CR_DMAUDRIE1_Pos (13U)
		4731	#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /!< 0x00002000 /
		4732	#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /!< DAC channel1 DMA underrun interrupt enable /
		4733	#define DAC_CR_DMAUDRIE2_Pos (29U)
		4734	#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /!< 0x20000000 /
		4735	#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /!< DAC channel2 DMA underrun interrupt enable /
2	mjames	4736
		4737	/*************** Bit definition for DAC_SWTRIGR register ****************/
5	mjames	4738	#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
		4739	#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /!< 0x00000001 /
		4740	#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /!< DAC channel1 software trigger /
		4741	#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
		4742	#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /!< 0x00000002 /
		4743	#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /!< DAC channel2 software trigger /
2	mjames	4744
		4745	/*************** Bit definition for DAC_DHR12R1 register ****************/
5	mjames	4746	#define DAC_DHR12R1_DACC1DHR_Pos (0U)
		4747	#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /!< 0x00000FFF /
		4748	#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /!< DAC channel1 12-bit Right aligned data /
2	mjames	4749
		4750	/*************** Bit definition for DAC_DHR12L1 register ****************/
5	mjames	4751	#define DAC_DHR12L1_DACC1DHR_Pos (4U)
		4752	#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /!< 0x0000FFF0 /
		4753	#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /!< DAC channel1 12-bit Left aligned data /
2	mjames	4754
		4755	/**************** Bit definition for DAC_DHR8R1 register ****************/
5	mjames	4756	#define DAC_DHR8R1_DACC1DHR_Pos (0U)
		4757	#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /!< 0x000000FF /
		4758	#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /!< DAC channel1 8-bit Right aligned data /
2	mjames	4759
		4760	/*************** Bit definition for DAC_DHR12R2 register ****************/
5	mjames	4761	#define DAC_DHR12R2_DACC2DHR_Pos (0U)
		4762	#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /!< 0x00000FFF /
		4763	#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /!< DAC channel2 12-bit Right aligned data /
2	mjames	4764
		4765	/*************** Bit definition for DAC_DHR12L2 register ****************/
5	mjames	4766	#define DAC_DHR12L2_DACC2DHR_Pos (4U)
		4767	#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /!< 0x0000FFF0 /
		4768	#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /!< DAC channel2 12-bit Left aligned data /
2	mjames	4769
		4770	/**************** Bit definition for DAC_DHR8R2 register ****************/
5	mjames	4771	#define DAC_DHR8R2_DACC2DHR_Pos (0U)
		4772	#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /!< 0x000000FF /
		4773	#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /!< DAC channel2 8-bit Right aligned data /
2	mjames	4774
		4775	/*************** Bit definition for DAC_DHR12RD register ****************/
5	mjames	4776	#define DAC_DHR12RD_DACC1DHR_Pos (0U)
		4777	#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /!< 0x00000FFF /
		4778	#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /!< DAC channel1 12-bit Right aligned data /
		4779	#define DAC_DHR12RD_DACC2DHR_Pos (16U)
		4780	#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /!< 0x0FFF0000 /
		4781	#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /!< DAC channel2 12-bit Right aligned data /
2	mjames	4782
		4783	/*************** Bit definition for DAC_DHR12LD register ****************/
5	mjames	4784	#define DAC_DHR12LD_DACC1DHR_Pos (4U)
		4785	#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /!< 0x0000FFF0 /
		4786	#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /!< DAC channel1 12-bit Left aligned data /
		4787	#define DAC_DHR12LD_DACC2DHR_Pos (20U)
		4788	#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /!< 0xFFF00000 /
		4789	#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /!< DAC channel2 12-bit Left aligned data /
2	mjames	4790
		4791	/**************** Bit definition for DAC_DHR8RD register ****************/
5	mjames	4792	#define DAC_DHR8RD_DACC1DHR_Pos (0U)
		4793	#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /!< 0x000000FF /
		4794	#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /!< DAC channel1 8-bit Right aligned data /
		4795	#define DAC_DHR8RD_DACC2DHR_Pos (8U)
		4796	#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /!< 0x0000FF00 /
		4797	#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /!< DAC channel2 8-bit Right aligned data /
2	mjames	4798
		4799	/***************** Bit definition for DAC_DOR1 register *****************/
5	mjames	4800	#define DAC_DOR1_DACC1DOR_Pos (0U)
		4801	#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /!< 0x00000FFF /
		4802	#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /!< DAC channel1 data output /
2	mjames	4803
		4804	/***************** Bit definition for DAC_DOR2 register *****************/
5	mjames	4805	#define DAC_DOR2_DACC2DOR_Pos (0U)
		4806	#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /!< 0x00000FFF /
		4807	#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /!< DAC channel2 data output /
2	mjames	4808
		4809	/****************** Bit definition for DAC_SR register ******************/
5	mjames	4810	#define DAC_SR_DMAUDR1_Pos (13U)
		4811	#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /!< 0x00002000 /
		4812	#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /!< DAC channel1 DMA underrun flag /
		4813	#define DAC_SR_DMAUDR2_Pos (29U)
		4814	#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /!< 0x20000000 /
		4815	#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /!< DAC channel2 DMA underrun flag /
2	mjames	4816
		4817	/******************************************************************************/
		4818	/* */
		4819	/* CEC */
		4820	/* */
		4821	/******************************************************************************/
		4822	/****************** Bit definition for CEC_CFGR register ****************/
5	mjames	4823	#define CEC_CFGR_PE_Pos (0U)
		4824	#define CEC_CFGR_PE_Msk (0x1U << CEC_CFGR_PE_Pos) /!< 0x00000001 /
		4825	#define CEC_CFGR_PE CEC_CFGR_PE_Msk /!< Peripheral Enable /
		4826	#define CEC_CFGR_IE_Pos (1U)
		4827	#define CEC_CFGR_IE_Msk (0x1U << CEC_CFGR_IE_Pos) /!< 0x00000002 /
		4828	#define CEC_CFGR_IE CEC_CFGR_IE_Msk /!< Interrupt Enable /
		4829	#define CEC_CFGR_BTEM_Pos (2U)
		4830	#define CEC_CFGR_BTEM_Msk (0x1U << CEC_CFGR_BTEM_Pos) /!< 0x00000004 /
		4831	#define CEC_CFGR_BTEM CEC_CFGR_BTEM_Msk /!< Bit Timing Error Mode /
		4832	#define CEC_CFGR_BPEM_Pos (3U)
		4833	#define CEC_CFGR_BPEM_Msk (0x1U << CEC_CFGR_BPEM_Pos) /!< 0x00000008 /
		4834	#define CEC_CFGR_BPEM CEC_CFGR_BPEM_Msk /!< Bit Period Error Mode /
2	mjames	4835
		4836	/****************** Bit definition for CEC_OAR register ****************/
5	mjames	4837	#define CEC_OAR_OA_Pos (0U)
		4838	#define CEC_OAR_OA_Msk (0xFU << CEC_OAR_OA_Pos) /!< 0x0000000F /
		4839	#define CEC_OAR_OA CEC_OAR_OA_Msk /!< OA[3:0]: Own Address /
		4840	#define CEC_OAR_OA_0 (0x1U << CEC_OAR_OA_Pos) /!< 0x00000001 /
		4841	#define CEC_OAR_OA_1 (0x2U << CEC_OAR_OA_Pos) /!< 0x00000002 /
		4842	#define CEC_OAR_OA_2 (0x4U << CEC_OAR_OA_Pos) /!< 0x00000004 /
		4843	#define CEC_OAR_OA_3 (0x8U << CEC_OAR_OA_Pos) /!< 0x00000008 /
2	mjames	4844
		4845	/****************** Bit definition for CEC_PRES register ****************/
5	mjames	4846	#define CEC_PRES_PRES_Pos (0U)
		4847	#define CEC_PRES_PRES_Msk (0x3FFFU << CEC_PRES_PRES_Pos) /!< 0x00003FFF /
		4848	#define CEC_PRES_PRES CEC_PRES_PRES_Msk /!< Prescaler Counter Value /
2	mjames	4849
		4850	/****************** Bit definition for CEC_ESR register ****************/
5	mjames	4851	#define CEC_ESR_BTE_Pos (0U)
		4852	#define CEC_ESR_BTE_Msk (0x1U << CEC_ESR_BTE_Pos) /!< 0x00000001 /
		4853	#define CEC_ESR_BTE CEC_ESR_BTE_Msk /!< Bit Timing Error /
		4854	#define CEC_ESR_BPE_Pos (1U)
		4855	#define CEC_ESR_BPE_Msk (0x1U << CEC_ESR_BPE_Pos) /!< 0x00000002 /
		4856	#define CEC_ESR_BPE CEC_ESR_BPE_Msk /!< Bit Period Error /
		4857	#define CEC_ESR_RBTFE_Pos (2U)
		4858	#define CEC_ESR_RBTFE_Msk (0x1U << CEC_ESR_RBTFE_Pos) /!< 0x00000004 /
		4859	#define CEC_ESR_RBTFE CEC_ESR_RBTFE_Msk /!< Rx Block Transfer Finished Error /
		4860	#define CEC_ESR_SBE_Pos (3U)
		4861	#define CEC_ESR_SBE_Msk (0x1U << CEC_ESR_SBE_Pos) /!< 0x00000008 /
		4862	#define CEC_ESR_SBE CEC_ESR_SBE_Msk /!< Start Bit Error /
		4863	#define CEC_ESR_ACKE_Pos (4U)
		4864	#define CEC_ESR_ACKE_Msk (0x1U << CEC_ESR_ACKE_Pos) /!< 0x00000010 /
		4865	#define CEC_ESR_ACKE CEC_ESR_ACKE_Msk /!< Block Acknowledge Error /
		4866	#define CEC_ESR_LINE_Pos (5U)
		4867	#define CEC_ESR_LINE_Msk (0x1U << CEC_ESR_LINE_Pos) /!< 0x00000020 /
		4868	#define CEC_ESR_LINE CEC_ESR_LINE_Msk /!< Line Error /
		4869	#define CEC_ESR_TBTFE_Pos (6U)
		4870	#define CEC_ESR_TBTFE_Msk (0x1U << CEC_ESR_TBTFE_Pos) /!< 0x00000040 /
		4871	#define CEC_ESR_TBTFE CEC_ESR_TBTFE_Msk /!< Tx Block Transfer Finished Error /
2	mjames	4872
		4873	/****************** Bit definition for CEC_CSR register ****************/
5	mjames	4874	#define CEC_CSR_TSOM_Pos (0U)
		4875	#define CEC_CSR_TSOM_Msk (0x1U << CEC_CSR_TSOM_Pos) /!< 0x00000001 /
		4876	#define CEC_CSR_TSOM CEC_CSR_TSOM_Msk /!< Tx Start Of Message /
		4877	#define CEC_CSR_TEOM_Pos (1U)
		4878	#define CEC_CSR_TEOM_Msk (0x1U << CEC_CSR_TEOM_Pos) /!< 0x00000002 /
		4879	#define CEC_CSR_TEOM CEC_CSR_TEOM_Msk /!< Tx End Of Message /
		4880	#define CEC_CSR_TERR_Pos (2U)
		4881	#define CEC_CSR_TERR_Msk (0x1U << CEC_CSR_TERR_Pos) /!< 0x00000004 /
		4882	#define CEC_CSR_TERR CEC_CSR_TERR_Msk /!< Tx Error /
		4883	#define CEC_CSR_TBTRF_Pos (3U)
		4884	#define CEC_CSR_TBTRF_Msk (0x1U << CEC_CSR_TBTRF_Pos) /!< 0x00000008 /
		4885	#define CEC_CSR_TBTRF CEC_CSR_TBTRF_Msk /!< Tx Byte Transfer Request or Block Transfer Finished /
		4886	#define CEC_CSR_RSOM_Pos (4U)
		4887	#define CEC_CSR_RSOM_Msk (0x1U << CEC_CSR_RSOM_Pos) /!< 0x00000010 /
		4888	#define CEC_CSR_RSOM CEC_CSR_RSOM_Msk /!< Rx Start Of Message /
		4889	#define CEC_CSR_REOM_Pos (5U)
		4890	#define CEC_CSR_REOM_Msk (0x1U << CEC_CSR_REOM_Pos) /!< 0x00000020 /
		4891	#define CEC_CSR_REOM CEC_CSR_REOM_Msk /!< Rx End Of Message /
		4892	#define CEC_CSR_RERR_Pos (6U)
		4893	#define CEC_CSR_RERR_Msk (0x1U << CEC_CSR_RERR_Pos) /!< 0x00000040 /
		4894	#define CEC_CSR_RERR CEC_CSR_RERR_Msk /!< Rx Error /
		4895	#define CEC_CSR_RBTF_Pos (7U)
		4896	#define CEC_CSR_RBTF_Msk (0x1U << CEC_CSR_RBTF_Pos) /!< 0x00000080 /
		4897	#define CEC_CSR_RBTF CEC_CSR_RBTF_Msk /!< Rx Block Transfer Finished /
2	mjames	4898
		4899	/****************** Bit definition for CEC_TXD register ****************/
5	mjames	4900	#define CEC_TXD_TXD_Pos (0U)
		4901	#define CEC_TXD_TXD_Msk (0xFFU << CEC_TXD_TXD_Pos) /!< 0x000000FF /
		4902	#define CEC_TXD_TXD CEC_TXD_TXD_Msk /!< Tx Data register /
2	mjames	4903
		4904	/****************** Bit definition for CEC_RXD register ****************/
5	mjames	4905	#define CEC_RXD_RXD_Pos (0U)
		4906	#define CEC_RXD_RXD_Msk (0xFFU << CEC_RXD_RXD_Pos) /!< 0x000000FF /
		4907	#define CEC_RXD_RXD CEC_RXD_RXD_Msk /!< Rx Data register /
2	mjames	4908
		4909	/*****************************************************************************/
		4910	/* */
		4911	/* Timers (TIM) */
		4912	/* */
		4913	/*****************************************************************************/
		4914	/***************** Bit definition for TIM_CR1 register *****************/
5	mjames	4915	#define TIM_CR1_CEN_Pos (0U)
		4916	#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /!< 0x00000001 /
		4917	#define TIM_CR1_CEN TIM_CR1_CEN_Msk /!<Counter enable /
		4918	#define TIM_CR1_UDIS_Pos (1U)
		4919	#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /!< 0x00000002 /
		4920	#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /!<Update disable /
		4921	#define TIM_CR1_URS_Pos (2U)
		4922	#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /!< 0x00000004 /
		4923	#define TIM_CR1_URS TIM_CR1_URS_Msk /!<Update request source /
		4924	#define TIM_CR1_OPM_Pos (3U)
		4925	#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /!< 0x00000008 /
		4926	#define TIM_CR1_OPM TIM_CR1_OPM_Msk /!<One pulse mode /
		4927	#define TIM_CR1_DIR_Pos (4U)
		4928	#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /!< 0x00000010 /
		4929	#define TIM_CR1_DIR TIM_CR1_DIR_Msk /!<Direction /
2	mjames	4930
5	mjames	4931	#define TIM_CR1_CMS_Pos (5U)
		4932	#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /!< 0x00000060 /
		4933	#define TIM_CR1_CMS TIM_CR1_CMS_Msk /!<CMS[1:0] bits (Center-aligned mode selection) /
		4934	#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /!< 0x00000020 /
		4935	#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /!< 0x00000040 /
2	mjames	4936
5	mjames	4937	#define TIM_CR1_ARPE_Pos (7U)
		4938	#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /!< 0x00000080 /
		4939	#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /!<Auto-reload preload enable /
2	mjames	4940
5	mjames	4941	#define TIM_CR1_CKD_Pos (8U)
		4942	#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /!< 0x00000300 /
		4943	#define TIM_CR1_CKD TIM_CR1_CKD_Msk /!<CKD[1:0] bits (clock division) /
		4944	#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /!< 0x00000100 /
		4945	#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /!< 0x00000200 /
2	mjames	4946
		4947	/***************** Bit definition for TIM_CR2 register *****************/
5	mjames	4948	#define TIM_CR2_CCPC_Pos (0U)
		4949	#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /!< 0x00000001 /
		4950	#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /!<Capture/Compare Preloaded Control /
		4951	#define TIM_CR2_CCUS_Pos (2U)
		4952	#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /!< 0x00000004 /
		4953	#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /!<Capture/Compare Control Update Selection /
		4954	#define TIM_CR2_CCDS_Pos (3U)
		4955	#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /!< 0x00000008 /
		4956	#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /!<Capture/Compare DMA Selection /
2	mjames	4957
5	mjames	4958	#define TIM_CR2_MMS_Pos (4U)
		4959	#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /!< 0x00000070 /
		4960	#define TIM_CR2_MMS TIM_CR2_MMS_Msk /!<MMS[2:0] bits (Master Mode Selection) /
		4961	#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /!< 0x00000010 /
		4962	#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /!< 0x00000020 /
		4963	#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /!< 0x00000040 /
2	mjames	4964
5	mjames	4965	#define TIM_CR2_TI1S_Pos (7U)
		4966	#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /!< 0x00000080 /
		4967	#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /!<TI1 Selection /
		4968	#define TIM_CR2_OIS1_Pos (8U)
		4969	#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /!< 0x00000100 /
		4970	#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /!<Output Idle state 1 (OC1 output) /
		4971	#define TIM_CR2_OIS1N_Pos (9U)
		4972	#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /!< 0x00000200 /
		4973	#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /!<Output Idle state 1 (OC1N output) /
		4974	#define TIM_CR2_OIS2_Pos (10U)
		4975	#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /!< 0x00000400 /
		4976	#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /!<Output Idle state 2 (OC2 output) /
		4977	#define TIM_CR2_OIS2N_Pos (11U)
		4978	#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /!< 0x00000800 /
		4979	#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /!<Output Idle state 2 (OC2N output) /
		4980	#define TIM_CR2_OIS3_Pos (12U)
		4981	#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /!< 0x00001000 /
		4982	#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /!<Output Idle state 3 (OC3 output) /
		4983	#define TIM_CR2_OIS3N_Pos (13U)
		4984	#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /!< 0x00002000 /
		4985	#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /!<Output Idle state 3 (OC3N output) /
		4986	#define TIM_CR2_OIS4_Pos (14U)
		4987	#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /!< 0x00004000 /
		4988	#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /!<Output Idle state 4 (OC4 output) /
2	mjames	4989
		4990	/***************** Bit definition for TIM_SMCR register ****************/
5	mjames	4991	#define TIM_SMCR_SMS_Pos (0U)
		4992	#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /!< 0x00000007 /
		4993	#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /!<SMS[2:0] bits (Slave mode selection) /
		4994	#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /!< 0x00000001 /
		4995	#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /!< 0x00000002 /
		4996	#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /!< 0x00000004 /
2	mjames	4997
5	mjames	4998	#define TIM_SMCR_OCCS_Pos (3U)
		4999	#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /!< 0x00000008 /
		5000	#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /!< OCREF clear selection /
2	mjames	5001
5	mjames	5002	#define TIM_SMCR_TS_Pos (4U)
		5003	#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /!< 0x00000070 /
		5004	#define TIM_SMCR_TS TIM_SMCR_TS_Msk /!<TS[2:0] bits (Trigger selection) /
		5005	#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /!< 0x00000010 /
		5006	#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /!< 0x00000020 /
		5007	#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /!< 0x00000040 /
2	mjames	5008
5	mjames	5009	#define TIM_SMCR_MSM_Pos (7U)
		5010	#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /!< 0x00000080 /
		5011	#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /!<Master/slave mode /
2	mjames	5012
5	mjames	5013	#define TIM_SMCR_ETF_Pos (8U)
		5014	#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /!< 0x00000F00 /
		5015	#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /!<ETF[3:0] bits (External trigger filter) /
		5016	#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /!< 0x00000100 /
		5017	#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /!< 0x00000200 /
		5018	#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /!< 0x00000400 /
		5019	#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /!< 0x00000800 /
2	mjames	5020
5	mjames	5021	#define TIM_SMCR_ETPS_Pos (12U)
		5022	#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /!< 0x00003000 /
		5023	#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /!<ETPS[1:0] bits (External trigger prescaler) /
		5024	#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /!< 0x00001000 /
		5025	#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /!< 0x00002000 /
2	mjames	5026
5	mjames	5027	#define TIM_SMCR_ECE_Pos (14U)
		5028	#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /!< 0x00004000 /
		5029	#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /!<External clock enable /
		5030	#define TIM_SMCR_ETP_Pos (15U)
		5031	#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /!< 0x00008000 /
		5032	#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /!<External trigger polarity /
2	mjames	5033
		5034	/***************** Bit definition for TIM_DIER register ****************/
5	mjames	5035	#define TIM_DIER_UIE_Pos (0U)
		5036	#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /!< 0x00000001 /
		5037	#define TIM_DIER_UIE TIM_DIER_UIE_Msk /!<Update interrupt enable /
		5038	#define TIM_DIER_CC1IE_Pos (1U)
		5039	#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /!< 0x00000002 /
		5040	#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /!<Capture/Compare 1 interrupt enable /
		5041	#define TIM_DIER_CC2IE_Pos (2U)
		5042	#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /!< 0x00000004 /
		5043	#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /!<Capture/Compare 2 interrupt enable /
		5044	#define TIM_DIER_CC3IE_Pos (3U)
		5045	#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /!< 0x00000008 /
		5046	#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /!<Capture/Compare 3 interrupt enable /
		5047	#define TIM_DIER_CC4IE_Pos (4U)
		5048	#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /!< 0x00000010 /
		5049	#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /!<Capture/Compare 4 interrupt enable /
		5050	#define TIM_DIER_COMIE_Pos (5U)
		5051	#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /!< 0x00000020 /
		5052	#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /!<COM interrupt enable /
		5053	#define TIM_DIER_TIE_Pos (6U)
		5054	#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /!< 0x00000040 /
		5055	#define TIM_DIER_TIE TIM_DIER_TIE_Msk /!<Trigger interrupt enable /
		5056	#define TIM_DIER_BIE_Pos (7U)
		5057	#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /!< 0x00000080 /
		5058	#define TIM_DIER_BIE TIM_DIER_BIE_Msk /!<Break interrupt enable /
		5059	#define TIM_DIER_UDE_Pos (8U)
		5060	#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /!< 0x00000100 /
		5061	#define TIM_DIER_UDE TIM_DIER_UDE_Msk /!<Update DMA request enable /
		5062	#define TIM_DIER_CC1DE_Pos (9U)
		5063	#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /!< 0x00000200 /
		5064	#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /!<Capture/Compare 1 DMA request enable /
		5065	#define TIM_DIER_CC2DE_Pos (10U)
		5066	#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /!< 0x00000400 /
		5067	#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /!<Capture/Compare 2 DMA request enable /
		5068	#define TIM_DIER_CC3DE_Pos (11U)
		5069	#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /!< 0x00000800 /
		5070	#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /!<Capture/Compare 3 DMA request enable /
		5071	#define TIM_DIER_CC4DE_Pos (12U)
		5072	#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /!< 0x00001000 /
		5073	#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /!<Capture/Compare 4 DMA request enable /
		5074	#define TIM_DIER_COMDE_Pos (13U)
		5075	#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /!< 0x00002000 /
		5076	#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /!<COM DMA request enable /
		5077	#define TIM_DIER_TDE_Pos (14U)
		5078	#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /!< 0x00004000 /
		5079	#define TIM_DIER_TDE TIM_DIER_TDE_Msk /!<Trigger DMA request enable /
2	mjames	5080
		5081	/****************** Bit definition for TIM_SR register *****************/
5	mjames	5082	#define TIM_SR_UIF_Pos (0U)
		5083	#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /!< 0x00000001 /
		5084	#define TIM_SR_UIF TIM_SR_UIF_Msk /!<Update interrupt Flag /
		5085	#define TIM_SR_CC1IF_Pos (1U)
		5086	#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /!< 0x00000002 /
		5087	#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /!<Capture/Compare 1 interrupt Flag /
		5088	#define TIM_SR_CC2IF_Pos (2U)
		5089	#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /!< 0x00000004 /
		5090	#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /!<Capture/Compare 2 interrupt Flag /
		5091	#define TIM_SR_CC3IF_Pos (3U)
		5092	#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /!< 0x00000008 /
		5093	#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /!<Capture/Compare 3 interrupt Flag /
		5094	#define TIM_SR_CC4IF_Pos (4U)
		5095	#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /!< 0x00000010 /
		5096	#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /!<Capture/Compare 4 interrupt Flag /
		5097	#define TIM_SR_COMIF_Pos (5U)
		5098	#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /!< 0x00000020 /
		5099	#define TIM_SR_COMIF TIM_SR_COMIF_Msk /!<COM interrupt Flag /
		5100	#define TIM_SR_TIF_Pos (6U)
		5101	#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /!< 0x00000040 /
		5102	#define TIM_SR_TIF TIM_SR_TIF_Msk /!<Trigger interrupt Flag /
		5103	#define TIM_SR_BIF_Pos (7U)
		5104	#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /!< 0x00000080 /
		5105	#define TIM_SR_BIF TIM_SR_BIF_Msk /!<Break interrupt Flag /
		5106	#define TIM_SR_CC1OF_Pos (9U)
		5107	#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /!< 0x00000200 /
		5108	#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /!<Capture/Compare 1 Overcapture Flag /
		5109	#define TIM_SR_CC2OF_Pos (10U)
		5110	#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /!< 0x00000400 /
		5111	#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /!<Capture/Compare 2 Overcapture Flag /
		5112	#define TIM_SR_CC3OF_Pos (11U)
		5113	#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /!< 0x00000800 /
		5114	#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /!<Capture/Compare 3 Overcapture Flag /
		5115	#define TIM_SR_CC4OF_Pos (12U)
		5116	#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /!< 0x00001000 /
		5117	#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /!<Capture/Compare 4 Overcapture Flag /
2	mjames	5118
		5119	/***************** Bit definition for TIM_EGR register *****************/
5	mjames	5120	#define TIM_EGR_UG_Pos (0U)
		5121	#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /!< 0x00000001 /
		5122	#define TIM_EGR_UG TIM_EGR_UG_Msk /!<Update Generation /
		5123	#define TIM_EGR_CC1G_Pos (1U)
		5124	#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /!< 0x00000002 /
		5125	#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /!<Capture/Compare 1 Generation /
		5126	#define TIM_EGR_CC2G_Pos (2U)
		5127	#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /!< 0x00000004 /
		5128	#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /!<Capture/Compare 2 Generation /
		5129	#define TIM_EGR_CC3G_Pos (3U)
		5130	#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /!< 0x00000008 /
		5131	#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /!<Capture/Compare 3 Generation /
		5132	#define TIM_EGR_CC4G_Pos (4U)
		5133	#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /!< 0x00000010 /
		5134	#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /!<Capture/Compare 4 Generation /
		5135	#define TIM_EGR_COMG_Pos (5U)
		5136	#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /!< 0x00000020 /
		5137	#define TIM_EGR_COMG TIM_EGR_COMG_Msk /!<Capture/Compare Control Update Generation /
		5138	#define TIM_EGR_TG_Pos (6U)
		5139	#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /!< 0x00000040 /
		5140	#define TIM_EGR_TG TIM_EGR_TG_Msk /!<Trigger Generation /
		5141	#define TIM_EGR_BG_Pos (7U)
		5142	#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /!< 0x00000080 /
		5143	#define TIM_EGR_BG TIM_EGR_BG_Msk /!<Break Generation /
2	mjames	5144
		5145	/**************** Bit definition for TIM_CCMR1 register ****************/
5	mjames	5146	#define TIM_CCMR1_CC1S_Pos (0U)
		5147	#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /!< 0x00000003 /
		5148	#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
		5149	#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /!< 0x00000001 /
		5150	#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /!< 0x00000002 /
2	mjames	5151
5	mjames	5152	#define TIM_CCMR1_OC1FE_Pos (2U)
		5153	#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /!< 0x00000004 /
		5154	#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /!<Output Compare 1 Fast enable /
		5155	#define TIM_CCMR1_OC1PE_Pos (3U)
		5156	#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /!< 0x00000008 /
		5157	#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /!<Output Compare 1 Preload enable /
2	mjames	5158
5	mjames	5159	#define TIM_CCMR1_OC1M_Pos (4U)
		5160	#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /!< 0x00000070 /
		5161	#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /!<OC1M[2:0] bits (Output Compare 1 Mode) /
		5162	#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /!< 0x00000010 /
		5163	#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /!< 0x00000020 /
		5164	#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /!< 0x00000040 /
2	mjames	5165
5	mjames	5166	#define TIM_CCMR1_OC1CE_Pos (7U)
		5167	#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /!< 0x00000080 /
		5168	#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /!<Output Compare 1Clear Enable /
2	mjames	5169
5	mjames	5170	#define TIM_CCMR1_CC2S_Pos (8U)
		5171	#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /!< 0x00000300 /
		5172	#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
		5173	#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /!< 0x00000100 /
		5174	#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /!< 0x00000200 /
2	mjames	5175
5	mjames	5176	#define TIM_CCMR1_OC2FE_Pos (10U)
		5177	#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /!< 0x00000400 /
		5178	#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /!<Output Compare 2 Fast enable /
		5179	#define TIM_CCMR1_OC2PE_Pos (11U)
		5180	#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /!< 0x00000800 /
		5181	#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /!<Output Compare 2 Preload enable /
2	mjames	5182
5	mjames	5183	#define TIM_CCMR1_OC2M_Pos (12U)
		5184	#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /!< 0x00007000 /
		5185	#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /!<OC2M[2:0] bits (Output Compare 2 Mode) /
		5186	#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /!< 0x00001000 /
		5187	#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /!< 0x00002000 /
		5188	#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /!< 0x00004000 /
2	mjames	5189
5	mjames	5190	#define TIM_CCMR1_OC2CE_Pos (15U)
		5191	#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /!< 0x00008000 /
		5192	#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /!<Output Compare 2 Clear Enable /
2	mjames	5193
		5194	/---------------------------------------------------------------------------/
		5195
5	mjames	5196	#define TIM_CCMR1_IC1PSC_Pos (2U)
		5197	#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /!< 0x0000000C /
		5198	#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
		5199	#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000004 /
		5200	#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000008 /
2	mjames	5201
5	mjames	5202	#define TIM_CCMR1_IC1F_Pos (4U)
		5203	#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /!< 0x000000F0 /
		5204	#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /!<IC1F[3:0] bits (Input Capture 1 Filter) /
		5205	#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /!< 0x00000010 /
		5206	#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /!< 0x00000020 /
		5207	#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /!< 0x00000040 /
		5208	#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /!< 0x00000080 /
2	mjames	5209
5	mjames	5210	#define TIM_CCMR1_IC2PSC_Pos (10U)
		5211	#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000C00 /
		5212	#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
		5213	#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000400 /
		5214	#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000800 /
2	mjames	5215
5	mjames	5216	#define TIM_CCMR1_IC2F_Pos (12U)
		5217	#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /!< 0x0000F000 /
		5218	#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /!<IC2F[3:0] bits (Input Capture 2 Filter) /
		5219	#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /!< 0x00001000 /
		5220	#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /!< 0x00002000 /
		5221	#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /!< 0x00004000 /
		5222	#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /!< 0x00008000 /
2	mjames	5223
		5224	/**************** Bit definition for TIM_CCMR2 register ****************/
5	mjames	5225	#define TIM_CCMR2_CC3S_Pos (0U)
		5226	#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /!< 0x00000003 /
		5227	#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
		5228	#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /!< 0x00000001 /
		5229	#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /!< 0x00000002 /
2	mjames	5230
5	mjames	5231	#define TIM_CCMR2_OC3FE_Pos (2U)
		5232	#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /!< 0x00000004 /
		5233	#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /!<Output Compare 3 Fast enable /
		5234	#define TIM_CCMR2_OC3PE_Pos (3U)
		5235	#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /!< 0x00000008 /
		5236	#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /!<Output Compare 3 Preload enable /
2	mjames	5237
5	mjames	5238	#define TIM_CCMR2_OC3M_Pos (4U)
		5239	#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /!< 0x00000070 /
		5240	#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /!<OC3M[2:0] bits (Output Compare 3 Mode) /
		5241	#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /!< 0x00000010 /
		5242	#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /!< 0x00000020 /
		5243	#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /!< 0x00000040 /
2	mjames	5244
5	mjames	5245	#define TIM_CCMR2_OC3CE_Pos (7U)
		5246	#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /!< 0x00000080 /
		5247	#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /!<Output Compare 3 Clear Enable /
2	mjames	5248
5	mjames	5249	#define TIM_CCMR2_CC4S_Pos (8U)
		5250	#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /!< 0x00000300 /
		5251	#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
		5252	#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /!< 0x00000100 /
		5253	#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /!< 0x00000200 /
2	mjames	5254
5	mjames	5255	#define TIM_CCMR2_OC4FE_Pos (10U)
		5256	#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /!< 0x00000400 /
		5257	#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /!<Output Compare 4 Fast enable /
		5258	#define TIM_CCMR2_OC4PE_Pos (11U)
		5259	#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /!< 0x00000800 /
		5260	#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /!<Output Compare 4 Preload enable /
2	mjames	5261
5	mjames	5262	#define TIM_CCMR2_OC4M_Pos (12U)
		5263	#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /!< 0x00007000 /
		5264	#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /!<OC4M[2:0] bits (Output Compare 4 Mode) /
		5265	#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /!< 0x00001000 /
		5266	#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /!< 0x00002000 /
		5267	#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /!< 0x00004000 /
2	mjames	5268
5	mjames	5269	#define TIM_CCMR2_OC4CE_Pos (15U)
		5270	#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /!< 0x00008000 /
		5271	#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /!<Output Compare 4 Clear Enable /
2	mjames	5272
		5273	/---------------------------------------------------------------------------/
		5274
5	mjames	5275	#define TIM_CCMR2_IC3PSC_Pos (2U)
		5276	#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /!< 0x0000000C /
		5277	#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
		5278	#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000004 /
		5279	#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000008 /
2	mjames	5280
5	mjames	5281	#define TIM_CCMR2_IC3F_Pos (4U)
		5282	#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /!< 0x000000F0 /
		5283	#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /!<IC3F[3:0] bits (Input Capture 3 Filter) /
		5284	#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /!< 0x00000010 /
		5285	#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /!< 0x00000020 /
		5286	#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /!< 0x00000040 /
		5287	#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /!< 0x00000080 /
2	mjames	5288
5	mjames	5289	#define TIM_CCMR2_IC4PSC_Pos (10U)
		5290	#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000C00 /
		5291	#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
		5292	#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000400 /
		5293	#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000800 /
2	mjames	5294
5	mjames	5295	#define TIM_CCMR2_IC4F_Pos (12U)
		5296	#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /!< 0x0000F000 /
		5297	#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /!<IC4F[3:0] bits (Input Capture 4 Filter) /
		5298	#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /!< 0x00001000 /
		5299	#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /!< 0x00002000 /
		5300	#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /!< 0x00004000 /
		5301	#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /!< 0x00008000 /
2	mjames	5302
		5303	/***************** Bit definition for TIM_CCER register ****************/
5	mjames	5304	#define TIM_CCER_CC1E_Pos (0U)
		5305	#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /!< 0x00000001 /
		5306	#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /!<Capture/Compare 1 output enable /
		5307	#define TIM_CCER_CC1P_Pos (1U)
		5308	#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /!< 0x00000002 /
		5309	#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /!<Capture/Compare 1 output Polarity /
		5310	#define TIM_CCER_CC1NE_Pos (2U)
		5311	#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /!< 0x00000004 /
		5312	#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /!<Capture/Compare 1 Complementary output enable /
		5313	#define TIM_CCER_CC1NP_Pos (3U)
		5314	#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /!< 0x00000008 /
		5315	#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /!<Capture/Compare 1 Complementary output Polarity /
		5316	#define TIM_CCER_CC2E_Pos (4U)
		5317	#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /!< 0x00000010 /
		5318	#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /!<Capture/Compare 2 output enable /
		5319	#define TIM_CCER_CC2P_Pos (5U)
		5320	#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /!< 0x00000020 /
		5321	#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /!<Capture/Compare 2 output Polarity /
		5322	#define TIM_CCER_CC2NE_Pos (6U)
		5323	#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /!< 0x00000040 /
		5324	#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /!<Capture/Compare 2 Complementary output enable /
		5325	#define TIM_CCER_CC2NP_Pos (7U)
		5326	#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /!< 0x00000080 /
		5327	#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /!<Capture/Compare 2 Complementary output Polarity /
		5328	#define TIM_CCER_CC3E_Pos (8U)
		5329	#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /!< 0x00000100 /
		5330	#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /!<Capture/Compare 3 output enable /
		5331	#define TIM_CCER_CC3P_Pos (9U)
		5332	#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /!< 0x00000200 /
		5333	#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /!<Capture/Compare 3 output Polarity /
		5334	#define TIM_CCER_CC3NE_Pos (10U)
		5335	#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /!< 0x00000400 /
		5336	#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /!<Capture/Compare 3 Complementary output enable /
		5337	#define TIM_CCER_CC3NP_Pos (11U)
		5338	#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /!< 0x00000800 /
		5339	#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /!<Capture/Compare 3 Complementary output Polarity /
		5340	#define TIM_CCER_CC4E_Pos (12U)
		5341	#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /!< 0x00001000 /
		5342	#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /!<Capture/Compare 4 output enable /
		5343	#define TIM_CCER_CC4P_Pos (13U)
		5344	#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /!< 0x00002000 /
		5345	#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /!<Capture/Compare 4 output Polarity /
		5346	#define TIM_CCER_CC4NP_Pos (15U)
		5347	#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /!< 0x00008000 /
		5348	#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /!<Capture/Compare 4 Complementary output Polarity /
2	mjames	5349
		5350	/***************** Bit definition for TIM_CNT register *****************/
5	mjames	5351	#define TIM_CNT_CNT_Pos (0U)
		5352	#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /!< 0xFFFFFFFF /
		5353	#define TIM_CNT_CNT TIM_CNT_CNT_Msk /!<Counter Value /
2	mjames	5354
		5355	/***************** Bit definition for TIM_PSC register *****************/
5	mjames	5356	#define TIM_PSC_PSC_Pos (0U)
		5357	#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /!< 0x0000FFFF /
		5358	#define TIM_PSC_PSC TIM_PSC_PSC_Msk /!<Prescaler Value /
2	mjames	5359
		5360	/***************** Bit definition for TIM_ARR register *****************/
5	mjames	5361	#define TIM_ARR_ARR_Pos (0U)
		5362	#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /!< 0xFFFFFFFF /
		5363	#define TIM_ARR_ARR TIM_ARR_ARR_Msk /!<actual auto-reload Value /
2	mjames	5364
		5365	/***************** Bit definition for TIM_RCR register *****************/
5	mjames	5366	#define TIM_RCR_REP_Pos (0U)
		5367	#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /!< 0x000000FF /
		5368	#define TIM_RCR_REP TIM_RCR_REP_Msk /!<Repetition Counter Value /
2	mjames	5369
		5370	/***************** Bit definition for TIM_CCR1 register ****************/
5	mjames	5371	#define TIM_CCR1_CCR1_Pos (0U)
		5372	#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /!< 0x0000FFFF /
		5373	#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /!<Capture/Compare 1 Value /
2	mjames	5374
		5375	/***************** Bit definition for TIM_CCR2 register ****************/
5	mjames	5376	#define TIM_CCR2_CCR2_Pos (0U)
		5377	#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /!< 0x0000FFFF /
		5378	#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /!<Capture/Compare 2 Value /
2	mjames	5379
		5380	/***************** Bit definition for TIM_CCR3 register ****************/
5	mjames	5381	#define TIM_CCR3_CCR3_Pos (0U)
		5382	#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /!< 0x0000FFFF /
		5383	#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /!<Capture/Compare 3 Value /
2	mjames	5384
		5385	/***************** Bit definition for TIM_CCR4 register ****************/
5	mjames	5386	#define TIM_CCR4_CCR4_Pos (0U)
		5387	#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /!< 0x0000FFFF /
		5388	#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /!<Capture/Compare 4 Value /
2	mjames	5389
		5390	/***************** Bit definition for TIM_BDTR register ****************/
5	mjames	5391	#define TIM_BDTR_DTG_Pos (0U)
		5392	#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /!< 0x000000FF /
		5393	#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /!<DTG[0:7] bits (Dead-Time Generator set-up) /
		5394	#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /!< 0x00000001 /
		5395	#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /!< 0x00000002 /
		5396	#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /!< 0x00000004 /
		5397	#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /!< 0x00000008 /
		5398	#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /!< 0x00000010 /
		5399	#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /!< 0x00000020 /
		5400	#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /!< 0x00000040 /
		5401	#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /!< 0x00000080 /
2	mjames	5402
5	mjames	5403	#define TIM_BDTR_LOCK_Pos (8U)
		5404	#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /!< 0x00000300 /
		5405	#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /!<LOCK[1:0] bits (Lock Configuration) /
		5406	#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /!< 0x00000100 /
		5407	#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /!< 0x00000200 /
2	mjames	5408
5	mjames	5409	#define TIM_BDTR_OSSI_Pos (10U)
		5410	#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /!< 0x00000400 /
		5411	#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /!<Off-State Selection for Idle mode /
		5412	#define TIM_BDTR_OSSR_Pos (11U)
		5413	#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /!< 0x00000800 /
		5414	#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /!<Off-State Selection for Run mode /
		5415	#define TIM_BDTR_BKE_Pos (12U)
		5416	#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /!< 0x00001000 /
		5417	#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /!<Break enable /
		5418	#define TIM_BDTR_BKP_Pos (13U)
		5419	#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /!< 0x00002000 /
		5420	#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /!<Break Polarity /
		5421	#define TIM_BDTR_AOE_Pos (14U)
		5422	#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /!< 0x00004000 /
		5423	#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /!<Automatic Output enable /
		5424	#define TIM_BDTR_MOE_Pos (15U)
		5425	#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /!< 0x00008000 /
		5426	#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /!<Main Output enable /
2	mjames	5427
		5428	/***************** Bit definition for TIM_DCR register *****************/
5	mjames	5429	#define TIM_DCR_DBA_Pos (0U)
		5430	#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /!< 0x0000001F /
		5431	#define TIM_DCR_DBA TIM_DCR_DBA_Msk /!<DBA[4:0] bits (DMA Base Address) /
		5432	#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /!< 0x00000001 /
		5433	#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /!< 0x00000002 /
		5434	#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /!< 0x00000004 /
		5435	#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /!< 0x00000008 /
		5436	#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /!< 0x00000010 /
2	mjames	5437
5	mjames	5438	#define TIM_DCR_DBL_Pos (8U)
		5439	#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /!< 0x00001F00 /
		5440	#define TIM_DCR_DBL TIM_DCR_DBL_Msk /!<DBL[4:0] bits (DMA Burst Length) /
		5441	#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /!< 0x00000100 /
		5442	#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /!< 0x00000200 /
		5443	#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /!< 0x00000400 /
		5444	#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /!< 0x00000800 /
		5445	#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /!< 0x00001000 /
2	mjames	5446
		5447	/***************** Bit definition for TIM_DMAR register ****************/
5	mjames	5448	#define TIM_DMAR_DMAB_Pos (0U)
		5449	#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /!< 0x0000FFFF /
		5450	#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /!<DMA register for burst accesses /
2	mjames	5451
		5452	/***************** Bit definition for TIM_OR register ******************/
		5453
		5454	/******************************************************************************/
		5455	/* */
		5456	/* Real-Time Clock */
		5457	/* */
		5458	/******************************************************************************/
		5459
		5460	/***************** Bit definition for RTC_CRH register ******************/
5	mjames	5461	#define RTC_CRH_SECIE_Pos (0U)
		5462	#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /!< 0x00000001 /
		5463	#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /!< Second Interrupt Enable /
		5464	#define RTC_CRH_ALRIE_Pos (1U)
		5465	#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /!< 0x00000002 /
		5466	#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /!< Alarm Interrupt Enable /
		5467	#define RTC_CRH_OWIE_Pos (2U)
		5468	#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /!< 0x00000004 /
		5469	#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /!< OverfloW Interrupt Enable /
2	mjames	5470
		5471	/***************** Bit definition for RTC_CRL register ******************/
5	mjames	5472	#define RTC_CRL_SECF_Pos (0U)
		5473	#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /!< 0x00000001 /
		5474	#define RTC_CRL_SECF RTC_CRL_SECF_Msk /!< Second Flag /
		5475	#define RTC_CRL_ALRF_Pos (1U)
		5476	#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /!< 0x00000002 /
		5477	#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /!< Alarm Flag /
		5478	#define RTC_CRL_OWF_Pos (2U)
		5479	#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /!< 0x00000004 /
		5480	#define RTC_CRL_OWF RTC_CRL_OWF_Msk /!< OverfloW Flag /
		5481	#define RTC_CRL_RSF_Pos (3U)
		5482	#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /!< 0x00000008 /
		5483	#define RTC_CRL_RSF RTC_CRL_RSF_Msk /!< Registers Synchronized Flag /
		5484	#define RTC_CRL_CNF_Pos (4U)
		5485	#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /!< 0x00000010 /
		5486	#define RTC_CRL_CNF RTC_CRL_CNF_Msk /!< Configuration Flag /
		5487	#define RTC_CRL_RTOFF_Pos (5U)
		5488	#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /!< 0x00000020 /
		5489	#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /!< RTC operation OFF /
2	mjames	5490
		5491	/***************** Bit definition for RTC_PRLH register *****************/
5	mjames	5492	#define RTC_PRLH_PRL_Pos (0U)
		5493	#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /!< 0x0000000F /
		5494	#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /!< RTC Prescaler Reload Value High /
2	mjames	5495
		5496	/***************** Bit definition for RTC_PRLL register *****************/
5	mjames	5497	#define RTC_PRLL_PRL_Pos (0U)
		5498	#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /!< 0x0000FFFF /
		5499	#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /!< RTC Prescaler Reload Value Low /
2	mjames	5500
		5501	/***************** Bit definition for RTC_DIVH register *****************/
5	mjames	5502	#define RTC_DIVH_RTC_DIV_Pos (0U)
		5503	#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /!< 0x0000000F /
		5504	#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /!< RTC Clock Divider High /
2	mjames	5505
		5506	/***************** Bit definition for RTC_DIVL register *****************/
5	mjames	5507	#define RTC_DIVL_RTC_DIV_Pos (0U)
		5508	#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /!< 0x0000FFFF /
		5509	#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /!< RTC Clock Divider Low /
2	mjames	5510
		5511	/***************** Bit definition for RTC_CNTH register *****************/
5	mjames	5512	#define RTC_CNTH_RTC_CNT_Pos (0U)
		5513	#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /!< 0x0000FFFF /
		5514	#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /!< RTC Counter High /
2	mjames	5515
		5516	/***************** Bit definition for RTC_CNTL register *****************/
5	mjames	5517	#define RTC_CNTL_RTC_CNT_Pos (0U)
		5518	#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /!< 0x0000FFFF /
		5519	#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /!< RTC Counter Low /
2	mjames	5520
		5521	/***************** Bit definition for RTC_ALRH register *****************/
5	mjames	5522	#define RTC_ALRH_RTC_ALR_Pos (0U)
		5523	#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /!< 0x0000FFFF /
		5524	#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /!< RTC Alarm High /
2	mjames	5525
		5526	/***************** Bit definition for RTC_ALRL register *****************/
5	mjames	5527	#define RTC_ALRL_RTC_ALR_Pos (0U)
		5528	#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /!< 0x0000FFFF /
		5529	#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /!< RTC Alarm Low /
2	mjames	5530
		5531	/******************************************************************************/
		5532	/* */
		5533	/* Independent WATCHDOG (IWDG) */
		5534	/* */
		5535	/******************************************************************************/
		5536
		5537	/***************** Bit definition for IWDG_KR register ******************/
5	mjames	5538	#define IWDG_KR_KEY_Pos (0U)
		5539	#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /!< 0x0000FFFF /
		5540	#define IWDG_KR_KEY IWDG_KR_KEY_Msk /!< Key value (write only, read 0000h) /
2	mjames	5541
		5542	/***************** Bit definition for IWDG_PR register ******************/
5	mjames	5543	#define IWDG_PR_PR_Pos (0U)
		5544	#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /!< 0x00000007 /
		5545	#define IWDG_PR_PR IWDG_PR_PR_Msk /!< PR[2:0] (Prescaler divider) /
		5546	#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /!< 0x00000001 /
		5547	#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /!< 0x00000002 /
		5548	#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /!< 0x00000004 /
2	mjames	5549
		5550	/***************** Bit definition for IWDG_RLR register *****************/
5	mjames	5551	#define IWDG_RLR_RL_Pos (0U)
		5552	#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /!< 0x00000FFF /
		5553	#define IWDG_RLR_RL IWDG_RLR_RL_Msk /!< Watchdog counter reload value /
2	mjames	5554
		5555	/***************** Bit definition for IWDG_SR register ******************/
5	mjames	5556	#define IWDG_SR_PVU_Pos (0U)
		5557	#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /!< 0x00000001 /
		5558	#define IWDG_SR_PVU IWDG_SR_PVU_Msk /!< Watchdog prescaler value update /
		5559	#define IWDG_SR_RVU_Pos (1U)
		5560	#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /!< 0x00000002 /
		5561	#define IWDG_SR_RVU IWDG_SR_RVU_Msk /!< Watchdog counter reload value update /
2	mjames	5562
		5563	/******************************************************************************/
		5564	/* */
5	mjames	5565	/* Window WATCHDOG (WWDG) */
2	mjames	5566	/* */
		5567	/******************************************************************************/
		5568
		5569	/***************** Bit definition for WWDG_CR register ******************/
5	mjames	5570	#define WWDG_CR_T_Pos (0U)
		5571	#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /!< 0x0000007F /
		5572	#define WWDG_CR_T WWDG_CR_T_Msk /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
		5573	#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /!< 0x00000001 /
		5574	#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /!< 0x00000002 /
		5575	#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /!< 0x00000004 /
		5576	#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /!< 0x00000008 /
		5577	#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /!< 0x00000010 /
		5578	#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /!< 0x00000020 /
		5579	#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /!< 0x00000040 /
2	mjames	5580
5	mjames	5581	/* Legacy defines */
		5582	#define WWDG_CR_T0 WWDG_CR_T_0
		5583	#define WWDG_CR_T1 WWDG_CR_T_1
		5584	#define WWDG_CR_T2 WWDG_CR_T_2
		5585	#define WWDG_CR_T3 WWDG_CR_T_3
		5586	#define WWDG_CR_T4 WWDG_CR_T_4
		5587	#define WWDG_CR_T5 WWDG_CR_T_5
		5588	#define WWDG_CR_T6 WWDG_CR_T_6
2	mjames	5589
5	mjames	5590	#define WWDG_CR_WDGA_Pos (7U)
		5591	#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /!< 0x00000080 /
		5592	#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /!< Activation bit /
		5593
2	mjames	5594	/***************** Bit definition for WWDG_CFR register *****************/
5	mjames	5595	#define WWDG_CFR_W_Pos (0U)
		5596	#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /!< 0x0000007F /
		5597	#define WWDG_CFR_W WWDG_CFR_W_Msk /!< W[6:0] bits (7-bit window value) /
		5598	#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /!< 0x00000001 /
		5599	#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /!< 0x00000002 /
		5600	#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /!< 0x00000004 /
		5601	#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /!< 0x00000008 /
		5602	#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /!< 0x00000010 /
		5603	#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /!< 0x00000020 /
		5604	#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /!< 0x00000040 /
2	mjames	5605
5	mjames	5606	/* Legacy defines */
		5607	#define WWDG_CFR_W0 WWDG_CFR_W_0
		5608	#define WWDG_CFR_W1 WWDG_CFR_W_1
		5609	#define WWDG_CFR_W2 WWDG_CFR_W_2
		5610	#define WWDG_CFR_W3 WWDG_CFR_W_3
		5611	#define WWDG_CFR_W4 WWDG_CFR_W_4
		5612	#define WWDG_CFR_W5 WWDG_CFR_W_5
		5613	#define WWDG_CFR_W6 WWDG_CFR_W_6
2	mjames	5614
5	mjames	5615	#define WWDG_CFR_WDGTB_Pos (7U)
		5616	#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /!< 0x00000180 /
		5617	#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /!< WDGTB[1:0] bits (Timer Base) /
		5618	#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /!< 0x00000080 /
		5619	#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /!< 0x00000100 /
2	mjames	5620
5	mjames	5621	/* Legacy defines */
		5622	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
		5623	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
		5624
		5625	#define WWDG_CFR_EWI_Pos (9U)
		5626	#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /!< 0x00000200 /
		5627	#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /!< Early Wakeup Interrupt /
		5628
2	mjames	5629	/***************** Bit definition for WWDG_SR register ******************/
5	mjames	5630	#define WWDG_SR_EWIF_Pos (0U)
		5631	#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /!< 0x00000001 /
		5632	#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /!< Early Wakeup Interrupt Flag /
2	mjames	5633
		5634	/******************************************************************************/
		5635	/* */
		5636	/* Flexible Static Memory Controller */
		5637	/* */
		5638	/******************************************************************************/
		5639
		5640	/**************** Bit definition for FSMC_BCRx (x=1..4) register ********/
5	mjames	5641	#define FSMC_BCRx_MBKEN_Pos (0U)
		5642	#define FSMC_BCRx_MBKEN_Msk (0x1U << FSMC_BCRx_MBKEN_Pos) /!< 0x00000001 /
		5643	#define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /!< Memory bank enable bit /
		5644	#define FSMC_BCRx_MUXEN_Pos (1U)
		5645	#define FSMC_BCRx_MUXEN_Msk (0x1U << FSMC_BCRx_MUXEN_Pos) /!< 0x00000002 /
		5646	#define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /!< Address/data multiplexing enable bit /
2	mjames	5647
5	mjames	5648	#define FSMC_BCRx_MTYP_Pos (2U)
		5649	#define FSMC_BCRx_MTYP_Msk (0x3U << FSMC_BCRx_MTYP_Pos) /!< 0x0000000C /
		5650	#define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /!< MTYP[1:0] bits (Memory type) /
		5651	#define FSMC_BCRx_MTYP_0 (0x1U << FSMC_BCRx_MTYP_Pos) /!< 0x00000004 /
		5652	#define FSMC_BCRx_MTYP_1 (0x2U << FSMC_BCRx_MTYP_Pos) /!< 0x00000008 /
2	mjames	5653
5	mjames	5654	#define FSMC_BCRx_MWID_Pos (4U)
		5655	#define FSMC_BCRx_MWID_Msk (0x3U << FSMC_BCRx_MWID_Pos) /!< 0x00000030 /
		5656	#define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /!< MWID[1:0] bits (Memory data bus width) /
		5657	#define FSMC_BCRx_MWID_0 (0x1U << FSMC_BCRx_MWID_Pos) /!< 0x00000010 /
		5658	#define FSMC_BCRx_MWID_1 (0x2U << FSMC_BCRx_MWID_Pos) /!< 0x00000020 /
2	mjames	5659
5	mjames	5660	#define FSMC_BCRx_FACCEN_Pos (6U)
		5661	#define FSMC_BCRx_FACCEN_Msk (0x1U << FSMC_BCRx_FACCEN_Pos) /!< 0x00000040 /
		5662	#define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /!< Flash access enable /
		5663	#define FSMC_BCRx_BURSTEN_Pos (8U)
		5664	#define FSMC_BCRx_BURSTEN_Msk (0x1U << FSMC_BCRx_BURSTEN_Pos) /!< 0x00000100 /
		5665	#define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /!< Burst enable bit /
		5666	#define FSMC_BCRx_WAITPOL_Pos (9U)
		5667	#define FSMC_BCRx_WAITPOL_Msk (0x1U << FSMC_BCRx_WAITPOL_Pos) /!< 0x00000200 /
		5668	#define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /!< Wait signal polarity bit /
		5669	#define FSMC_BCRx_WRAPMOD_Pos (10U)
		5670	#define FSMC_BCRx_WRAPMOD_Msk (0x1U << FSMC_BCRx_WRAPMOD_Pos) /!< 0x00000400 /
		5671	#define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /!< Wrapped burst mode support /
		5672	#define FSMC_BCRx_WAITCFG_Pos (11U)
		5673	#define FSMC_BCRx_WAITCFG_Msk (0x1U << FSMC_BCRx_WAITCFG_Pos) /!< 0x00000800 /
		5674	#define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /!< Wait timing configuration /
		5675	#define FSMC_BCRx_WREN_Pos (12U)
		5676	#define FSMC_BCRx_WREN_Msk (0x1U << FSMC_BCRx_WREN_Pos) /!< 0x00001000 /
		5677	#define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /!< Write enable bit /
		5678	#define FSMC_BCRx_WAITEN_Pos (13U)
		5679	#define FSMC_BCRx_WAITEN_Msk (0x1U << FSMC_BCRx_WAITEN_Pos) /!< 0x00002000 /
		5680	#define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /!< Wait enable bit /
		5681	#define FSMC_BCRx_EXTMOD_Pos (14U)
		5682	#define FSMC_BCRx_EXTMOD_Msk (0x1U << FSMC_BCRx_EXTMOD_Pos) /!< 0x00004000 /
		5683	#define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /!< Extended mode enable /
		5684	#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
		5685	#define FSMC_BCRx_ASYNCWAIT_Msk (0x1U << FSMC_BCRx_ASYNCWAIT_Pos) /!< 0x00008000 /
		5686	#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /!< Asynchronous wait /
		5687	#define FSMC_BCRx_CBURSTRW_Pos (19U)
		5688	#define FSMC_BCRx_CBURSTRW_Msk (0x1U << FSMC_BCRx_CBURSTRW_Pos) /!< 0x00080000 /
		5689	#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /!< Write burst enable /
2	mjames	5690
		5691	/**************** Bit definition for FSMC_BTRx (x=1..4) register ****/
5	mjames	5692	#define FSMC_BTRx_ADDSET_Pos (0U)
		5693	#define FSMC_BTRx_ADDSET_Msk (0xFU << FSMC_BTRx_ADDSET_Pos) /!< 0x0000000F /
		5694	#define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /!< ADDSET[3:0] bits (Address setup phase duration) /
		5695	#define FSMC_BTRx_ADDSET_0 (0x1U << FSMC_BTRx_ADDSET_Pos) /!< 0x00000001 /
		5696	#define FSMC_BTRx_ADDSET_1 (0x2U << FSMC_BTRx_ADDSET_Pos) /!< 0x00000002 /
		5697	#define FSMC_BTRx_ADDSET_2 (0x4U << FSMC_BTRx_ADDSET_Pos) /!< 0x00000004 /
		5698	#define FSMC_BTRx_ADDSET_3 (0x8U << FSMC_BTRx_ADDSET_Pos) /!< 0x00000008 /
2	mjames	5699
5	mjames	5700	#define FSMC_BTRx_ADDHLD_Pos (4U)
		5701	#define FSMC_BTRx_ADDHLD_Msk (0xFU << FSMC_BTRx_ADDHLD_Pos) /!< 0x000000F0 /
		5702	#define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		5703	#define FSMC_BTRx_ADDHLD_0 (0x1U << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000010 /
		5704	#define FSMC_BTRx_ADDHLD_1 (0x2U << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000020 /
		5705	#define FSMC_BTRx_ADDHLD_2 (0x4U << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000040 /
		5706	#define FSMC_BTRx_ADDHLD_3 (0x8U << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000080 /
2	mjames	5707
5	mjames	5708	#define FSMC_BTRx_DATAST_Pos (8U)
		5709	#define FSMC_BTRx_DATAST_Msk (0xFFU << FSMC_BTRx_DATAST_Pos) /!< 0x0000FF00 /
		5710	#define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /!< DATAST [3:0] bits (Data-phase duration) /
		5711	#define FSMC_BTRx_DATAST_0 (0x01U << FSMC_BTRx_DATAST_Pos) /!< 0x00000100 /
		5712	#define FSMC_BTRx_DATAST_1 (0x02U << FSMC_BTRx_DATAST_Pos) /!< 0x00000200 /
		5713	#define FSMC_BTRx_DATAST_2 (0x04U << FSMC_BTRx_DATAST_Pos) /!< 0x00000400 /
		5714	#define FSMC_BTRx_DATAST_3 (0x08U << FSMC_BTRx_DATAST_Pos) /!< 0x00000800 /
		5715	#define FSMC_BTRx_DATAST_4 (0x10U << FSMC_BTRx_DATAST_Pos) /!< 0x00001000 /
		5716	#define FSMC_BTRx_DATAST_5 (0x20U << FSMC_BTRx_DATAST_Pos) /!< 0x00002000 /
		5717	#define FSMC_BTRx_DATAST_6 (0x40U << FSMC_BTRx_DATAST_Pos) /!< 0x00004000 /
		5718	#define FSMC_BTRx_DATAST_7 (0x80U << FSMC_BTRx_DATAST_Pos) /!< 0x00008000 /
2	mjames	5719
5	mjames	5720	#define FSMC_BTRx_BUSTURN_Pos (16U)
		5721	#define FSMC_BTRx_BUSTURN_Msk (0xFU << FSMC_BTRx_BUSTURN_Pos) /!< 0x000F0000 /
		5722	#define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
		5723	#define FSMC_BTRx_BUSTURN_0 (0x1U << FSMC_BTRx_BUSTURN_Pos) /!< 0x00010000 /
		5724	#define FSMC_BTRx_BUSTURN_1 (0x2U << FSMC_BTRx_BUSTURN_Pos) /!< 0x00020000 /
		5725	#define FSMC_BTRx_BUSTURN_2 (0x4U << FSMC_BTRx_BUSTURN_Pos) /!< 0x00040000 /
		5726	#define FSMC_BTRx_BUSTURN_3 (0x8U << FSMC_BTRx_BUSTURN_Pos) /!< 0x00080000 /
2	mjames	5727
5	mjames	5728	#define FSMC_BTRx_CLKDIV_Pos (20U)
		5729	#define FSMC_BTRx_CLKDIV_Msk (0xFU << FSMC_BTRx_CLKDIV_Pos) /!< 0x00F00000 /
		5730	#define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /!< CLKDIV[3:0] bits (Clock divide ratio) /
		5731	#define FSMC_BTRx_CLKDIV_0 (0x1U << FSMC_BTRx_CLKDIV_Pos) /!< 0x00100000 /
		5732	#define FSMC_BTRx_CLKDIV_1 (0x2U << FSMC_BTRx_CLKDIV_Pos) /!< 0x00200000 /
		5733	#define FSMC_BTRx_CLKDIV_2 (0x4U << FSMC_BTRx_CLKDIV_Pos) /!< 0x00400000 /
		5734	#define FSMC_BTRx_CLKDIV_3 (0x8U << FSMC_BTRx_CLKDIV_Pos) /!< 0x00800000 /
2	mjames	5735
5	mjames	5736	#define FSMC_BTRx_DATLAT_Pos (24U)
		5737	#define FSMC_BTRx_DATLAT_Msk (0xFU << FSMC_BTRx_DATLAT_Pos) /!< 0x0F000000 /
		5738	#define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /!< DATLA[3:0] bits (Data latency) /
		5739	#define FSMC_BTRx_DATLAT_0 (0x1U << FSMC_BTRx_DATLAT_Pos) /!< 0x01000000 /
		5740	#define FSMC_BTRx_DATLAT_1 (0x2U << FSMC_BTRx_DATLAT_Pos) /!< 0x02000000 /
		5741	#define FSMC_BTRx_DATLAT_2 (0x4U << FSMC_BTRx_DATLAT_Pos) /!< 0x04000000 /
		5742	#define FSMC_BTRx_DATLAT_3 (0x8U << FSMC_BTRx_DATLAT_Pos) /!< 0x08000000 /
2	mjames	5743
5	mjames	5744	#define FSMC_BTRx_ACCMOD_Pos (28U)
		5745	#define FSMC_BTRx_ACCMOD_Msk (0x3U << FSMC_BTRx_ACCMOD_Pos) /!< 0x30000000 /
		5746	#define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /!< ACCMOD[1:0] bits (Access mode) /
		5747	#define FSMC_BTRx_ACCMOD_0 (0x1U << FSMC_BTRx_ACCMOD_Pos) /!< 0x10000000 /
		5748	#define FSMC_BTRx_ACCMOD_1 (0x2U << FSMC_BTRx_ACCMOD_Pos) /!< 0x20000000 /
2	mjames	5749
		5750	/**************** Bit definition for FSMC_BWTRx (x=1..4) register ****/
5	mjames	5751	#define FSMC_BWTRx_ADDSET_Pos (0U)
		5752	#define FSMC_BWTRx_ADDSET_Msk (0xFU << FSMC_BWTRx_ADDSET_Pos) /!< 0x0000000F /
		5753	#define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /!< ADDSET[3:0] bits (Address setup phase duration) /
		5754	#define FSMC_BWTRx_ADDSET_0 (0x1U << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000001 /
		5755	#define FSMC_BWTRx_ADDSET_1 (0x2U << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000002 /
		5756	#define FSMC_BWTRx_ADDSET_2 (0x4U << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000004 /
		5757	#define FSMC_BWTRx_ADDSET_3 (0x8U << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000008 /
2	mjames	5758
5	mjames	5759	#define FSMC_BWTRx_ADDHLD_Pos (4U)
		5760	#define FSMC_BWTRx_ADDHLD_Msk (0xFU << FSMC_BWTRx_ADDHLD_Pos) /!< 0x000000F0 /
		5761	#define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		5762	#define FSMC_BWTRx_ADDHLD_0 (0x1U << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000010 /
		5763	#define FSMC_BWTRx_ADDHLD_1 (0x2U << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000020 /
		5764	#define FSMC_BWTRx_ADDHLD_2 (0x4U << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000040 /
		5765	#define FSMC_BWTRx_ADDHLD_3 (0x8U << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000080 /
2	mjames	5766
5	mjames	5767	#define FSMC_BWTRx_DATAST_Pos (8U)
		5768	#define FSMC_BWTRx_DATAST_Msk (0xFFU << FSMC_BWTRx_DATAST_Pos) /!< 0x0000FF00 /
		5769	#define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /!< DATAST [3:0] bits (Data-phase duration) /
		5770	#define FSMC_BWTRx_DATAST_0 (0x01U << FSMC_BWTRx_DATAST_Pos) /!< 0x00000100 /
		5771	#define FSMC_BWTRx_DATAST_1 (0x02U << FSMC_BWTRx_DATAST_Pos) /!< 0x00000200 /
		5772	#define FSMC_BWTRx_DATAST_2 (0x04U << FSMC_BWTRx_DATAST_Pos) /!< 0x00000400 /
		5773	#define FSMC_BWTRx_DATAST_3 (0x08U << FSMC_BWTRx_DATAST_Pos) /!< 0x00000800 /
		5774	#define FSMC_BWTRx_DATAST_4 (0x10U << FSMC_BWTRx_DATAST_Pos) /!< 0x00001000 /
		5775	#define FSMC_BWTRx_DATAST_5 (0x20U << FSMC_BWTRx_DATAST_Pos) /!< 0x00002000 /
		5776	#define FSMC_BWTRx_DATAST_6 (0x40U << FSMC_BWTRx_DATAST_Pos) /!< 0x00004000 /
		5777	#define FSMC_BWTRx_DATAST_7 (0x80U << FSMC_BWTRx_DATAST_Pos) /!< 0x00008000 /
2	mjames	5778
5	mjames	5779	#define FSMC_BWTRx_CLKDIV_Pos (20U)
		5780	#define FSMC_BWTRx_CLKDIV_Msk (0xFU << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00F00000 /
		5781	#define FSMC_BWTRx_CLKDIV FSMC_BWTRx_CLKDIV_Msk /!< CLKDIV[3:0] bits (Clock divide ratio) /
		5782	#define FSMC_BWTRx_CLKDIV_0 (0x1U << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00100000 /
		5783	#define FSMC_BWTRx_CLKDIV_1 (0x2U << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00200000 /
		5784	#define FSMC_BWTRx_CLKDIV_2 (0x4U << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00400000 /
		5785	#define FSMC_BWTRx_CLKDIV_3 (0x8U << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00800000 /
2	mjames	5786
5	mjames	5787	#define FSMC_BWTRx_DATLAT_Pos (24U)
		5788	#define FSMC_BWTRx_DATLAT_Msk (0xFU << FSMC_BWTRx_DATLAT_Pos) /!< 0x0F000000 /
		5789	#define FSMC_BWTRx_DATLAT FSMC_BWTRx_DATLAT_Msk /!< DATLA[3:0] bits (Data latency) /
		5790	#define FSMC_BWTRx_DATLAT_0 (0x1U << FSMC_BWTRx_DATLAT_Pos) /!< 0x01000000 /
		5791	#define FSMC_BWTRx_DATLAT_1 (0x2U << FSMC_BWTRx_DATLAT_Pos) /!< 0x02000000 /
		5792	#define FSMC_BWTRx_DATLAT_2 (0x4U << FSMC_BWTRx_DATLAT_Pos) /!< 0x04000000 /
		5793	#define FSMC_BWTRx_DATLAT_3 (0x8U << FSMC_BWTRx_DATLAT_Pos) /!< 0x08000000 /
2	mjames	5794
5	mjames	5795	#define FSMC_BWTRx_ACCMOD_Pos (28U)
		5796	#define FSMC_BWTRx_ACCMOD_Msk (0x3U << FSMC_BWTRx_ACCMOD_Pos) /!< 0x30000000 /
		5797	#define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /!< ACCMOD[1:0] bits (Access mode) /
		5798	#define FSMC_BWTRx_ACCMOD_0 (0x1U << FSMC_BWTRx_ACCMOD_Pos) /!< 0x10000000 /
		5799	#define FSMC_BWTRx_ACCMOD_1 (0x2U << FSMC_BWTRx_ACCMOD_Pos) /!< 0x20000000 /
2	mjames	5800
		5801
		5802	/******************************************************************************/
		5803	/* */
		5804	/* SD host Interface */
		5805	/* */
		5806	/******************************************************************************/
		5807
		5808	/**************** Bit definition for SDIO_POWER register ****************/
5	mjames	5809	#define SDIO_POWER_PWRCTRL_Pos (0U)
		5810	#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /!< 0x00000003 /
		5811	#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /!< PWRCTRL[1:0] bits (Power supply control bits) /
		5812	#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /!< 0x01 /
		5813	#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /!< 0x02 /
2	mjames	5814
		5815	/**************** Bit definition for SDIO_CLKCR register ****************/
5	mjames	5816	#define SDIO_CLKCR_CLKDIV_Pos (0U)
		5817	#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /!< 0x000000FF /
		5818	#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /!< Clock divide factor /
		5819	#define SDIO_CLKCR_CLKEN_Pos (8U)
		5820	#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /!< 0x00000100 /
		5821	#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /!< Clock enable bit /
		5822	#define SDIO_CLKCR_PWRSAV_Pos (9U)
		5823	#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /!< 0x00000200 /
		5824	#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /!< Power saving configuration bit /
		5825	#define SDIO_CLKCR_BYPASS_Pos (10U)
		5826	#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /!< 0x00000400 /
		5827	#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /!< Clock divider bypass enable bit /
2	mjames	5828
5	mjames	5829	#define SDIO_CLKCR_WIDBUS_Pos (11U)
		5830	#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /!< 0x00001800 /
		5831	#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
		5832	#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /!< 0x0800 /
		5833	#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /!< 0x1000 /
2	mjames	5834
5	mjames	5835	#define SDIO_CLKCR_NEGEDGE_Pos (13U)
		5836	#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /!< 0x00002000 /
		5837	#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /!< SDIO_CK dephasing selection bit /
		5838	#define SDIO_CLKCR_HWFC_EN_Pos (14U)
		5839	#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /!< 0x00004000 /
		5840	#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /!< HW Flow Control enable /
2	mjames	5841
		5842	/***************** Bit definition for SDIO_ARG register *****************/
5	mjames	5843	#define SDIO_ARG_CMDARG_Pos (0U)
		5844	#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /!< 0xFFFFFFFF /
		5845	#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /!< Command argument /
2	mjames	5846
		5847	/***************** Bit definition for SDIO_CMD register *****************/
5	mjames	5848	#define SDIO_CMD_CMDINDEX_Pos (0U)
		5849	#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /!< 0x0000003F /
		5850	#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /!< Command Index /
2	mjames	5851
5	mjames	5852	#define SDIO_CMD_WAITRESP_Pos (6U)
		5853	#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /!< 0x000000C0 /
		5854	#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /!< WAITRESP[1:0] bits (Wait for response bits) /
		5855	#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /!< 0x0040 /
		5856	#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /!< 0x0080 /
2	mjames	5857
5	mjames	5858	#define SDIO_CMD_WAITINT_Pos (8U)
		5859	#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /!< 0x00000100 /
		5860	#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /!< CPSM Waits for Interrupt Request /
		5861	#define SDIO_CMD_WAITPEND_Pos (9U)
		5862	#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /!< 0x00000200 /
		5863	#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
		5864	#define SDIO_CMD_CPSMEN_Pos (10U)
		5865	#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /!< 0x00000400 /
		5866	#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /!< Command path state machine (CPSM) Enable bit /
		5867	#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
		5868	#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /!< 0x00000800 /
		5869	#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /!< SD I/O suspend command /
		5870	#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
		5871	#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /!< 0x00001000 /
		5872	#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /!< Enable CMD completion /
		5873	#define SDIO_CMD_NIEN_Pos (13U)
		5874	#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /!< 0x00002000 /
		5875	#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /!< Not Interrupt Enable /
		5876	#define SDIO_CMD_CEATACMD_Pos (14U)
		5877	#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /!< 0x00004000 /
		5878	#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /!< CE-ATA command /
2	mjames	5879
		5880	/*************** Bit definition for SDIO_RESPCMD register ***************/
5	mjames	5881	#define SDIO_RESPCMD_RESPCMD_Pos (0U)
		5882	#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /!< 0x0000003F /
		5883	#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /!< Response command index /
2	mjames	5884
		5885	/**************** Bit definition for SDIO_RESP0 register ****************/
5	mjames	5886	#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
		5887	#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /!< 0xFFFFFFFF /
		5888	#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /!< Card Status /
2	mjames	5889
		5890	/**************** Bit definition for SDIO_RESP1 register ****************/
5	mjames	5891	#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
		5892	#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /!< 0xFFFFFFFF /
		5893	#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /!< Card Status /
2	mjames	5894
		5895	/**************** Bit definition for SDIO_RESP2 register ****************/
5	mjames	5896	#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
		5897	#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /!< 0xFFFFFFFF /
		5898	#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /!< Card Status /
2	mjames	5899
		5900	/**************** Bit definition for SDIO_RESP3 register ****************/
5	mjames	5901	#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
		5902	#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /!< 0xFFFFFFFF /
		5903	#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /!< Card Status /
2	mjames	5904
		5905	/**************** Bit definition for SDIO_RESP4 register ****************/
5	mjames	5906	#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
		5907	#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /!< 0xFFFFFFFF /
		5908	#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /!< Card Status /
2	mjames	5909
		5910	/**************** Bit definition for SDIO_DTIMER register ***************/
5	mjames	5911	#define SDIO_DTIMER_DATATIME_Pos (0U)
		5912	#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /!< 0xFFFFFFFF /
		5913	#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /!< Data timeout period. /
2	mjames	5914
		5915	/**************** Bit definition for SDIO_DLEN register *****************/
5	mjames	5916	#define SDIO_DLEN_DATALENGTH_Pos (0U)
		5917	#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /!< 0x01FFFFFF /
		5918	#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /!< Data length value /
2	mjames	5919
		5920	/**************** Bit definition for SDIO_DCTRL register ****************/
5	mjames	5921	#define SDIO_DCTRL_DTEN_Pos (0U)
		5922	#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /!< 0x00000001 /
		5923	#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /!< Data transfer enabled bit /
		5924	#define SDIO_DCTRL_DTDIR_Pos (1U)
		5925	#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /!< 0x00000002 /
		5926	#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /!< Data transfer direction selection /
		5927	#define SDIO_DCTRL_DTMODE_Pos (2U)
		5928	#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /!< 0x00000004 /
		5929	#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /!< Data transfer mode selection /
		5930	#define SDIO_DCTRL_DMAEN_Pos (3U)
		5931	#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /!< 0x00000008 /
		5932	#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /!< DMA enabled bit /
2	mjames	5933
5	mjames	5934	#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
		5935	#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x000000F0 /
		5936	#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /!< DBLOCKSIZE[3:0] bits (Data block size) /
		5937	#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0010 /
		5938	#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0020 /
		5939	#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0040 /
		5940	#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0080 /
2	mjames	5941
5	mjames	5942	#define SDIO_DCTRL_RWSTART_Pos (8U)
		5943	#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /!< 0x00000100 /
		5944	#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /!< Read wait start /
		5945	#define SDIO_DCTRL_RWSTOP_Pos (9U)
		5946	#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /!< 0x00000200 /
		5947	#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /!< Read wait stop /
		5948	#define SDIO_DCTRL_RWMOD_Pos (10U)
		5949	#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /!< 0x00000400 /
		5950	#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /!< Read wait mode /
		5951	#define SDIO_DCTRL_SDIOEN_Pos (11U)
		5952	#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /!< 0x00000800 /
		5953	#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /!< SD I/O enable functions /
2	mjames	5954
		5955	/**************** Bit definition for SDIO_DCOUNT register ***************/
5	mjames	5956	#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
		5957	#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /!< 0x01FFFFFF /
		5958	#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /!< Data count value /
2	mjames	5959
		5960	/**************** Bit definition for SDIO_STA register ******************/
5	mjames	5961	#define SDIO_STA_CCRCFAIL_Pos (0U)
		5962	#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /!< 0x00000001 /
		5963	#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /!< Command response received (CRC check failed) /
		5964	#define SDIO_STA_DCRCFAIL_Pos (1U)
		5965	#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /!< 0x00000002 /
		5966	#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /!< Data block sent/received (CRC check failed) /
		5967	#define SDIO_STA_CTIMEOUT_Pos (2U)
		5968	#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /!< 0x00000004 /
		5969	#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /!< Command response timeout /
		5970	#define SDIO_STA_DTIMEOUT_Pos (3U)
		5971	#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /!< 0x00000008 /
		5972	#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /!< Data timeout /
		5973	#define SDIO_STA_TXUNDERR_Pos (4U)
		5974	#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /!< 0x00000010 /
		5975	#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /!< Transmit FIFO underrun error /
		5976	#define SDIO_STA_RXOVERR_Pos (5U)
		5977	#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /!< 0x00000020 /
		5978	#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /!< Received FIFO overrun error /
		5979	#define SDIO_STA_CMDREND_Pos (6U)
		5980	#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /!< 0x00000040 /
		5981	#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /!< Command response received (CRC check passed) /
		5982	#define SDIO_STA_CMDSENT_Pos (7U)
		5983	#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /!< 0x00000080 /
		5984	#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /!< Command sent (no response required) /
		5985	#define SDIO_STA_DATAEND_Pos (8U)
		5986	#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /!< 0x00000100 /
		5987	#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /!< Data end (data counter, SDIDCOUNT, is zero) /
		5988	#define SDIO_STA_STBITERR_Pos (9U)
		5989	#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /!< 0x00000200 /
		5990	#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /!< Start bit not detected on all data signals in wide bus mode /
		5991	#define SDIO_STA_DBCKEND_Pos (10U)
		5992	#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /!< 0x00000400 /
		5993	#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /!< Data block sent/received (CRC check passed) /
		5994	#define SDIO_STA_CMDACT_Pos (11U)
		5995	#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /!< 0x00000800 /
		5996	#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /!< Command transfer in progress /
		5997	#define SDIO_STA_TXACT_Pos (12U)
		5998	#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /!< 0x00001000 /
		5999	#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /!< Data transmit in progress /
		6000	#define SDIO_STA_RXACT_Pos (13U)
		6001	#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /!< 0x00002000 /
		6002	#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /!< Data receive in progress /
		6003	#define SDIO_STA_TXFIFOHE_Pos (14U)
		6004	#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /!< 0x00004000 /
		6005	#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
		6006	#define SDIO_STA_RXFIFOHF_Pos (15U)
		6007	#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /!< 0x00008000 /
		6008	#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
		6009	#define SDIO_STA_TXFIFOF_Pos (16U)
		6010	#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /!< 0x00010000 /
		6011	#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /!< Transmit FIFO full /
		6012	#define SDIO_STA_RXFIFOF_Pos (17U)
		6013	#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /!< 0x00020000 /
		6014	#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /!< Receive FIFO full /
		6015	#define SDIO_STA_TXFIFOE_Pos (18U)
		6016	#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /!< 0x00040000 /
		6017	#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /!< Transmit FIFO empty /
		6018	#define SDIO_STA_RXFIFOE_Pos (19U)
		6019	#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /!< 0x00080000 /
		6020	#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /!< Receive FIFO empty /
		6021	#define SDIO_STA_TXDAVL_Pos (20U)
		6022	#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /!< 0x00100000 /
		6023	#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /!< Data available in transmit FIFO /
		6024	#define SDIO_STA_RXDAVL_Pos (21U)
		6025	#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /!< 0x00200000 /
		6026	#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /!< Data available in receive FIFO /
		6027	#define SDIO_STA_SDIOIT_Pos (22U)
		6028	#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /!< 0x00400000 /
		6029	#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /!< SDIO interrupt received /
		6030	#define SDIO_STA_CEATAEND_Pos (23U)
		6031	#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /!< 0x00800000 /
		6032	#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /!< CE-ATA command completion signal received for CMD61 /
2	mjames	6033
		6034	/***************** Bit definition for SDIO_ICR register *****************/
5	mjames	6035	#define SDIO_ICR_CCRCFAILC_Pos (0U)
		6036	#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /!< 0x00000001 /
		6037	#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /!< CCRCFAIL flag clear bit /
		6038	#define SDIO_ICR_DCRCFAILC_Pos (1U)
		6039	#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /!< 0x00000002 /
		6040	#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /!< DCRCFAIL flag clear bit /
		6041	#define SDIO_ICR_CTIMEOUTC_Pos (2U)
		6042	#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /!< 0x00000004 /
		6043	#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /!< CTIMEOUT flag clear bit /
		6044	#define SDIO_ICR_DTIMEOUTC_Pos (3U)
		6045	#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /!< 0x00000008 /
		6046	#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /!< DTIMEOUT flag clear bit /
		6047	#define SDIO_ICR_TXUNDERRC_Pos (4U)
		6048	#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /!< 0x00000010 /
		6049	#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /!< TXUNDERR flag clear bit /
		6050	#define SDIO_ICR_RXOVERRC_Pos (5U)
		6051	#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /!< 0x00000020 /
		6052	#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /!< RXOVERR flag clear bit /
		6053	#define SDIO_ICR_CMDRENDC_Pos (6U)
		6054	#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /!< 0x00000040 /
		6055	#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /!< CMDREND flag clear bit /
		6056	#define SDIO_ICR_CMDSENTC_Pos (7U)
		6057	#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /!< 0x00000080 /
		6058	#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /!< CMDSENT flag clear bit /
		6059	#define SDIO_ICR_DATAENDC_Pos (8U)
		6060	#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /!< 0x00000100 /
		6061	#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /!< DATAEND flag clear bit /
		6062	#define SDIO_ICR_STBITERRC_Pos (9U)
		6063	#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /!< 0x00000200 /
		6064	#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /!< STBITERR flag clear bit /
		6065	#define SDIO_ICR_DBCKENDC_Pos (10U)
		6066	#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /!< 0x00000400 /
		6067	#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /!< DBCKEND flag clear bit /
		6068	#define SDIO_ICR_SDIOITC_Pos (22U)
		6069	#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /!< 0x00400000 /
		6070	#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /!< SDIOIT flag clear bit /
		6071	#define SDIO_ICR_CEATAENDC_Pos (23U)
		6072	#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /!< 0x00800000 /
		6073	#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /!< CEATAEND flag clear bit /
2	mjames	6074
		6075	/**************** Bit definition for SDIO_MASK register *****************/
5	mjames	6076	#define SDIO_MASK_CCRCFAILIE_Pos (0U)
		6077	#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /!< 0x00000001 /
		6078	#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /!< Command CRC Fail Interrupt Enable /
		6079	#define SDIO_MASK_DCRCFAILIE_Pos (1U)
		6080	#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /!< 0x00000002 /
		6081	#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /!< Data CRC Fail Interrupt Enable /
		6082	#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
		6083	#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /!< 0x00000004 /
		6084	#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /!< Command TimeOut Interrupt Enable /
		6085	#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
		6086	#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /!< 0x00000008 /
		6087	#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /!< Data TimeOut Interrupt Enable /
		6088	#define SDIO_MASK_TXUNDERRIE_Pos (4U)
		6089	#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /!< 0x00000010 /
		6090	#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /!< Tx FIFO UnderRun Error Interrupt Enable /
		6091	#define SDIO_MASK_RXOVERRIE_Pos (5U)
		6092	#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /!< 0x00000020 /
		6093	#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /!< Rx FIFO OverRun Error Interrupt Enable /
		6094	#define SDIO_MASK_CMDRENDIE_Pos (6U)
		6095	#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /!< 0x00000040 /
		6096	#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /!< Command Response Received Interrupt Enable /
		6097	#define SDIO_MASK_CMDSENTIE_Pos (7U)
		6098	#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /!< 0x00000080 /
		6099	#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /!< Command Sent Interrupt Enable /
		6100	#define SDIO_MASK_DATAENDIE_Pos (8U)
		6101	#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /!< 0x00000100 /
		6102	#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /!< Data End Interrupt Enable /
		6103	#define SDIO_MASK_STBITERRIE_Pos (9U)
		6104	#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /!< 0x00000200 /
		6105	#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /!< Start Bit Error Interrupt Enable /
		6106	#define SDIO_MASK_DBCKENDIE_Pos (10U)
		6107	#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /!< 0x00000400 /
		6108	#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /!< Data Block End Interrupt Enable /
		6109	#define SDIO_MASK_CMDACTIE_Pos (11U)
		6110	#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /!< 0x00000800 /
		6111	#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /!< Command Acting Interrupt Enable /
		6112	#define SDIO_MASK_TXACTIE_Pos (12U)
		6113	#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /!< 0x00001000 /
		6114	#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /!< Data Transmit Acting Interrupt Enable /
		6115	#define SDIO_MASK_RXACTIE_Pos (13U)
		6116	#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /!< 0x00002000 /
		6117	#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /!< Data receive acting interrupt enabled /
		6118	#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
		6119	#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /!< 0x00004000 /
		6120	#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /!< Tx FIFO Half Empty interrupt Enable /
		6121	#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
		6122	#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /!< 0x00008000 /
		6123	#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /!< Rx FIFO Half Full interrupt Enable /
		6124	#define SDIO_MASK_TXFIFOFIE_Pos (16U)
		6125	#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /!< 0x00010000 /
		6126	#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /!< Tx FIFO Full interrupt Enable /
		6127	#define SDIO_MASK_RXFIFOFIE_Pos (17U)
		6128	#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /!< 0x00020000 /
		6129	#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /!< Rx FIFO Full interrupt Enable /
		6130	#define SDIO_MASK_TXFIFOEIE_Pos (18U)
		6131	#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /!< 0x00040000 /
		6132	#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /!< Tx FIFO Empty interrupt Enable /
		6133	#define SDIO_MASK_RXFIFOEIE_Pos (19U)
		6134	#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /!< 0x00080000 /
		6135	#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /!< Rx FIFO Empty interrupt Enable /
		6136	#define SDIO_MASK_TXDAVLIE_Pos (20U)
		6137	#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /!< 0x00100000 /
		6138	#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /!< Data available in Tx FIFO interrupt Enable /
		6139	#define SDIO_MASK_RXDAVLIE_Pos (21U)
		6140	#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /!< 0x00200000 /
		6141	#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /!< Data available in Rx FIFO interrupt Enable /
		6142	#define SDIO_MASK_SDIOITIE_Pos (22U)
		6143	#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /!< 0x00400000 /
		6144	#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /!< SDIO Mode Interrupt Received interrupt Enable /
		6145	#define SDIO_MASK_CEATAENDIE_Pos (23U)
		6146	#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /!< 0x00800000 /
		6147	#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /!< CE-ATA command completion signal received Interrupt Enable /
2	mjames	6148
		6149	/*************** Bit definition for SDIO_FIFOCNT register ***************/
5	mjames	6150	#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
		6151	#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /!< 0x00FFFFFF /
		6152	#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /!< Remaining number of words to be written to or read from the FIFO /
2	mjames	6153
		6154	/**************** Bit definition for SDIO_FIFO register *****************/
5	mjames	6155	#define SDIO_FIFO_FIFODATA_Pos (0U)
		6156	#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /!< 0xFFFFFFFF /
		6157	#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /!< Receive and transmit FIFO data /
2	mjames	6158
		6159
		6160
		6161	/******************************************************************************/
		6162	/* */
		6163	/* Serial Peripheral Interface */
		6164	/* */
		6165	/******************************************************************************/
		6166
		6167	/***************** Bit definition for SPI_CR1 register ******************/
5	mjames	6168	#define SPI_CR1_CPHA_Pos (0U)
		6169	#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /!< 0x00000001 /
		6170	#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /!< Clock Phase /
		6171	#define SPI_CR1_CPOL_Pos (1U)
		6172	#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /!< 0x00000002 /
		6173	#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /!< Clock Polarity /
		6174	#define SPI_CR1_MSTR_Pos (2U)
		6175	#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /!< 0x00000004 /
		6176	#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /!< Master Selection /
2	mjames	6177
5	mjames	6178	#define SPI_CR1_BR_Pos (3U)
		6179	#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /!< 0x00000038 /
		6180	#define SPI_CR1_BR SPI_CR1_BR_Msk /!< BR[2:0] bits (Baud Rate Control) /
		6181	#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /!< 0x00000008 /
		6182	#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /!< 0x00000010 /
		6183	#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /!< 0x00000020 /
2	mjames	6184
5	mjames	6185	#define SPI_CR1_SPE_Pos (6U)
		6186	#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /!< 0x00000040 /
		6187	#define SPI_CR1_SPE SPI_CR1_SPE_Msk /!< SPI Enable /
		6188	#define SPI_CR1_LSBFIRST_Pos (7U)
		6189	#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /!< 0x00000080 /
		6190	#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /!< Frame Format /
		6191	#define SPI_CR1_SSI_Pos (8U)
		6192	#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /!< 0x00000100 /
		6193	#define SPI_CR1_SSI SPI_CR1_SSI_Msk /!< Internal slave select /
		6194	#define SPI_CR1_SSM_Pos (9U)
		6195	#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /!< 0x00000200 /
		6196	#define SPI_CR1_SSM SPI_CR1_SSM_Msk /!< Software slave management /
		6197	#define SPI_CR1_RXONLY_Pos (10U)
		6198	#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /!< 0x00000400 /
		6199	#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /!< Receive only /
		6200	#define SPI_CR1_DFF_Pos (11U)
		6201	#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /!< 0x00000800 /
		6202	#define SPI_CR1_DFF SPI_CR1_DFF_Msk /!< Data Frame Format /
		6203	#define SPI_CR1_CRCNEXT_Pos (12U)
		6204	#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /!< 0x00001000 /
		6205	#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /!< Transmit CRC next /
		6206	#define SPI_CR1_CRCEN_Pos (13U)
		6207	#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /!< 0x00002000 /
		6208	#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /!< Hardware CRC calculation enable /
		6209	#define SPI_CR1_BIDIOE_Pos (14U)
		6210	#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /!< 0x00004000 /
		6211	#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /!< Output enable in bidirectional mode /
		6212	#define SPI_CR1_BIDIMODE_Pos (15U)
		6213	#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /!< 0x00008000 /
		6214	#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /!< Bidirectional data mode enable /
2	mjames	6215
		6216	/***************** Bit definition for SPI_CR2 register ******************/
5	mjames	6217	#define SPI_CR2_RXDMAEN_Pos (0U)
		6218	#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /!< 0x00000001 /
		6219	#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /!< Rx Buffer DMA Enable /
		6220	#define SPI_CR2_TXDMAEN_Pos (1U)
		6221	#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /!< 0x00000002 /
		6222	#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /!< Tx Buffer DMA Enable /
		6223	#define SPI_CR2_SSOE_Pos (2U)
		6224	#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /!< 0x00000004 /
		6225	#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /!< SS Output Enable /
		6226	#define SPI_CR2_ERRIE_Pos (5U)
		6227	#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /!< 0x00000020 /
		6228	#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /!< Error Interrupt Enable /
		6229	#define SPI_CR2_RXNEIE_Pos (6U)
		6230	#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /!< 0x00000040 /
		6231	#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /!< RX buffer Not Empty Interrupt Enable /
		6232	#define SPI_CR2_TXEIE_Pos (7U)
		6233	#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /!< 0x00000080 /
		6234	#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /!< Tx buffer Empty Interrupt Enable /
2	mjames	6235
		6236	/****************** Bit definition for SPI_SR register ******************/
5	mjames	6237	#define SPI_SR_RXNE_Pos (0U)
		6238	#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /!< 0x00000001 /
		6239	#define SPI_SR_RXNE SPI_SR_RXNE_Msk /!< Receive buffer Not Empty /
		6240	#define SPI_SR_TXE_Pos (1U)
		6241	#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /!< 0x00000002 /
		6242	#define SPI_SR_TXE SPI_SR_TXE_Msk /!< Transmit buffer Empty /
		6243	#define SPI_SR_CHSIDE_Pos (2U)
		6244	#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /!< 0x00000004 /
		6245	#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /!< Channel side /
		6246	#define SPI_SR_UDR_Pos (3U)
		6247	#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /!< 0x00000008 /
		6248	#define SPI_SR_UDR SPI_SR_UDR_Msk /!< Underrun flag /
		6249	#define SPI_SR_CRCERR_Pos (4U)
		6250	#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /!< 0x00000010 /
		6251	#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /!< CRC Error flag /
		6252	#define SPI_SR_MODF_Pos (5U)
		6253	#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /!< 0x00000020 /
		6254	#define SPI_SR_MODF SPI_SR_MODF_Msk /!< Mode fault /
		6255	#define SPI_SR_OVR_Pos (6U)
		6256	#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /!< 0x00000040 /
		6257	#define SPI_SR_OVR SPI_SR_OVR_Msk /!< Overrun flag /
		6258	#define SPI_SR_BSY_Pos (7U)
		6259	#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /!< 0x00000080 /
		6260	#define SPI_SR_BSY SPI_SR_BSY_Msk /!< Busy flag /
2	mjames	6261
		6262	/****************** Bit definition for SPI_DR register ******************/
5	mjames	6263	#define SPI_DR_DR_Pos (0U)
		6264	#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /!< 0x0000FFFF /
		6265	#define SPI_DR_DR SPI_DR_DR_Msk /!< Data Register /
2	mjames	6266
		6267	/***************** Bit definition for SPI_CRCPR register ****************/
5	mjames	6268	#define SPI_CRCPR_CRCPOLY_Pos (0U)
		6269	#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /!< 0x0000FFFF /
		6270	#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /!< CRC polynomial register /
2	mjames	6271
		6272	/**************** Bit definition for SPI_RXCRCR register ****************/
5	mjames	6273	#define SPI_RXCRCR_RXCRC_Pos (0U)
		6274	#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /!< 0x0000FFFF /
		6275	#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /!< Rx CRC Register /
2	mjames	6276
		6277	/**************** Bit definition for SPI_TXCRCR register ****************/
5	mjames	6278	#define SPI_TXCRCR_TXCRC_Pos (0U)
		6279	#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /!< 0x0000FFFF /
		6280	#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /!< Tx CRC Register /
2	mjames	6281
		6282
		6283
		6284	/******************************************************************************/
		6285	/* */
		6286	/* Inter-integrated Circuit Interface */
		6287	/* */
		6288	/******************************************************************************/
		6289
		6290	/***************** Bit definition for I2C_CR1 register ******************/
5	mjames	6291	#define I2C_CR1_PE_Pos (0U)
		6292	#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /!< 0x00000001 /
		6293	#define I2C_CR1_PE I2C_CR1_PE_Msk /!< Peripheral Enable /
		6294	#define I2C_CR1_SMBUS_Pos (1U)
		6295	#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /!< 0x00000002 /
		6296	#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /!< SMBus Mode /
		6297	#define I2C_CR1_SMBTYPE_Pos (3U)
		6298	#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /!< 0x00000008 /
		6299	#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /!< SMBus Type /
		6300	#define I2C_CR1_ENARP_Pos (4U)
		6301	#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /!< 0x00000010 /
		6302	#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /!< ARP Enable /
		6303	#define I2C_CR1_ENPEC_Pos (5U)
		6304	#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /!< 0x00000020 /
		6305	#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /!< PEC Enable /
		6306	#define I2C_CR1_ENGC_Pos (6U)
		6307	#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /!< 0x00000040 /
		6308	#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /!< General Call Enable /
		6309	#define I2C_CR1_NOSTRETCH_Pos (7U)
		6310	#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /!< 0x00000080 /
		6311	#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /!< Clock Stretching Disable (Slave mode) /
		6312	#define I2C_CR1_START_Pos (8U)
		6313	#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /!< 0x00000100 /
		6314	#define I2C_CR1_START I2C_CR1_START_Msk /!< Start Generation /
		6315	#define I2C_CR1_STOP_Pos (9U)
		6316	#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /!< 0x00000200 /
		6317	#define I2C_CR1_STOP I2C_CR1_STOP_Msk /!< Stop Generation /
		6318	#define I2C_CR1_ACK_Pos (10U)
		6319	#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /!< 0x00000400 /
		6320	#define I2C_CR1_ACK I2C_CR1_ACK_Msk /!< Acknowledge Enable /
		6321	#define I2C_CR1_POS_Pos (11U)
		6322	#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /!< 0x00000800 /
		6323	#define I2C_CR1_POS I2C_CR1_POS_Msk /!< Acknowledge/PEC Position (for data reception) /
		6324	#define I2C_CR1_PEC_Pos (12U)
		6325	#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /!< 0x00001000 /
		6326	#define I2C_CR1_PEC I2C_CR1_PEC_Msk /!< Packet Error Checking /
		6327	#define I2C_CR1_ALERT_Pos (13U)
		6328	#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /!< 0x00002000 /
		6329	#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /!< SMBus Alert /
		6330	#define I2C_CR1_SWRST_Pos (15U)
		6331	#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /!< 0x00008000 /
		6332	#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /!< Software Reset /
2	mjames	6333
		6334	/***************** Bit definition for I2C_CR2 register ******************/
5	mjames	6335	#define I2C_CR2_FREQ_Pos (0U)
		6336	#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /!< 0x0000003F /
		6337	#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
		6338	#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /!< 0x00000001 /
		6339	#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /!< 0x00000002 /
		6340	#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /!< 0x00000004 /
		6341	#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /!< 0x00000008 /
		6342	#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /!< 0x00000010 /
		6343	#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /!< 0x00000020 /
2	mjames	6344
5	mjames	6345	#define I2C_CR2_ITERREN_Pos (8U)
		6346	#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /!< 0x00000100 /
		6347	#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /!< Error Interrupt Enable /
		6348	#define I2C_CR2_ITEVTEN_Pos (9U)
		6349	#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /!< 0x00000200 /
		6350	#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /!< Event Interrupt Enable /
		6351	#define I2C_CR2_ITBUFEN_Pos (10U)
		6352	#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /!< 0x00000400 /
		6353	#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /!< Buffer Interrupt Enable /
		6354	#define I2C_CR2_DMAEN_Pos (11U)
		6355	#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /!< 0x00000800 /
		6356	#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /!< DMA Requests Enable /
		6357	#define I2C_CR2_LAST_Pos (12U)
		6358	#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /!< 0x00001000 /
		6359	#define I2C_CR2_LAST I2C_CR2_LAST_Msk /!< DMA Last Transfer /
2	mjames	6360
		6361	/***************** Bit definition for I2C_OAR1 register *****************/
5	mjames	6362	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
		6363	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
2	mjames	6364
5	mjames	6365	#define I2C_OAR1_ADD0_Pos (0U)
		6366	#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /!< 0x00000001 /
		6367	#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /!< Bit 0 /
		6368	#define I2C_OAR1_ADD1_Pos (1U)
		6369	#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /!< 0x00000002 /
		6370	#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /!< Bit 1 /
		6371	#define I2C_OAR1_ADD2_Pos (2U)
		6372	#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /!< 0x00000004 /
		6373	#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /!< Bit 2 /
		6374	#define I2C_OAR1_ADD3_Pos (3U)
		6375	#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /!< 0x00000008 /
		6376	#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /!< Bit 3 /
		6377	#define I2C_OAR1_ADD4_Pos (4U)
		6378	#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /!< 0x00000010 /
		6379	#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /!< Bit 4 /
		6380	#define I2C_OAR1_ADD5_Pos (5U)
		6381	#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /!< 0x00000020 /
		6382	#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /!< Bit 5 /
		6383	#define I2C_OAR1_ADD6_Pos (6U)
		6384	#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /!< 0x00000040 /
		6385	#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /!< Bit 6 /
		6386	#define I2C_OAR1_ADD7_Pos (7U)
		6387	#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /!< 0x00000080 /
		6388	#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /!< Bit 7 /
		6389	#define I2C_OAR1_ADD8_Pos (8U)
		6390	#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /!< 0x00000100 /
		6391	#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /!< Bit 8 /
		6392	#define I2C_OAR1_ADD9_Pos (9U)
		6393	#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /!< 0x00000200 /
		6394	#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /!< Bit 9 /
2	mjames	6395
5	mjames	6396	#define I2C_OAR1_ADDMODE_Pos (15U)
		6397	#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /!< 0x00008000 /
		6398	#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /!< Addressing Mode (Slave mode) /
2	mjames	6399
		6400	/***************** Bit definition for I2C_OAR2 register *****************/
5	mjames	6401	#define I2C_OAR2_ENDUAL_Pos (0U)
		6402	#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /!< 0x00000001 /
		6403	#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /!< Dual addressing mode enable /
		6404	#define I2C_OAR2_ADD2_Pos (1U)
		6405	#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /!< 0x000000FE /
		6406	#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /!< Interface address /
2	mjames	6407
		6408	/***************** Bit definition for I2C_SR1 register ******************/
5	mjames	6409	#define I2C_SR1_SB_Pos (0U)
		6410	#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /!< 0x00000001 /
		6411	#define I2C_SR1_SB I2C_SR1_SB_Msk /!< Start Bit (Master mode) /
		6412	#define I2C_SR1_ADDR_Pos (1U)
		6413	#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /!< 0x00000002 /
		6414	#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /!< Address sent (master mode)/matched (slave mode) /
		6415	#define I2C_SR1_BTF_Pos (2U)
		6416	#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /!< 0x00000004 /
		6417	#define I2C_SR1_BTF I2C_SR1_BTF_Msk /!< Byte Transfer Finished /
		6418	#define I2C_SR1_ADD10_Pos (3U)
		6419	#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /!< 0x00000008 /
		6420	#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /!< 10-bit header sent (Master mode) /
		6421	#define I2C_SR1_STOPF_Pos (4U)
		6422	#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /!< 0x00000010 /
		6423	#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /!< Stop detection (Slave mode) /
		6424	#define I2C_SR1_RXNE_Pos (6U)
		6425	#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /!< 0x00000040 /
		6426	#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /!< Data Register not Empty (receivers) /
		6427	#define I2C_SR1_TXE_Pos (7U)
		6428	#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /!< 0x00000080 /
		6429	#define I2C_SR1_TXE I2C_SR1_TXE_Msk /!< Data Register Empty (transmitters) /
		6430	#define I2C_SR1_BERR_Pos (8U)
		6431	#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /!< 0x00000100 /
		6432	#define I2C_SR1_BERR I2C_SR1_BERR_Msk /!< Bus Error /
		6433	#define I2C_SR1_ARLO_Pos (9U)
		6434	#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /!< 0x00000200 /
		6435	#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /!< Arbitration Lost (master mode) /
		6436	#define I2C_SR1_AF_Pos (10U)
		6437	#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /!< 0x00000400 /
		6438	#define I2C_SR1_AF I2C_SR1_AF_Msk /!< Acknowledge Failure /
		6439	#define I2C_SR1_OVR_Pos (11U)
		6440	#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /!< 0x00000800 /
		6441	#define I2C_SR1_OVR I2C_SR1_OVR_Msk /!< Overrun/Underrun /
		6442	#define I2C_SR1_PECERR_Pos (12U)
		6443	#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /!< 0x00001000 /
		6444	#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /!< PEC Error in reception /
		6445	#define I2C_SR1_TIMEOUT_Pos (14U)
		6446	#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /!< 0x00004000 /
		6447	#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /!< Timeout or Tlow Error /
		6448	#define I2C_SR1_SMBALERT_Pos (15U)
		6449	#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /!< 0x00008000 /
		6450	#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /!< SMBus Alert /
2	mjames	6451
		6452	/***************** Bit definition for I2C_SR2 register ******************/
5	mjames	6453	#define I2C_SR2_MSL_Pos (0U)
		6454	#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /!< 0x00000001 /
		6455	#define I2C_SR2_MSL I2C_SR2_MSL_Msk /!< Master/Slave /
		6456	#define I2C_SR2_BUSY_Pos (1U)
		6457	#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /!< 0x00000002 /
		6458	#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /!< Bus Busy /
		6459	#define I2C_SR2_TRA_Pos (2U)
		6460	#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /!< 0x00000004 /
		6461	#define I2C_SR2_TRA I2C_SR2_TRA_Msk /!< Transmitter/Receiver /
		6462	#define I2C_SR2_GENCALL_Pos (4U)
		6463	#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /!< 0x00000010 /
		6464	#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /!< General Call Address (Slave mode) /
		6465	#define I2C_SR2_SMBDEFAULT_Pos (5U)
		6466	#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /!< 0x00000020 /
		6467	#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /!< SMBus Device Default Address (Slave mode) /
		6468	#define I2C_SR2_SMBHOST_Pos (6U)
		6469	#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /!< 0x00000040 /
		6470	#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /!< SMBus Host Header (Slave mode) /
		6471	#define I2C_SR2_DUALF_Pos (7U)
		6472	#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /!< 0x00000080 /
		6473	#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /!< Dual Flag (Slave mode) /
		6474	#define I2C_SR2_PEC_Pos (8U)
		6475	#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /!< 0x0000FF00 /
		6476	#define I2C_SR2_PEC I2C_SR2_PEC_Msk /!< Packet Error Checking Register /
2	mjames	6477
		6478	/***************** Bit definition for I2C_CCR register ******************/
5	mjames	6479	#define I2C_CCR_CCR_Pos (0U)
		6480	#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /!< 0x00000FFF /
		6481	#define I2C_CCR_CCR I2C_CCR_CCR_Msk /!< Clock Control Register in Fast/Standard mode (Master mode) /
		6482	#define I2C_CCR_DUTY_Pos (14U)
		6483	#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /!< 0x00004000 /
		6484	#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /!< Fast Mode Duty Cycle /
		6485	#define I2C_CCR_FS_Pos (15U)
		6486	#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /!< 0x00008000 /
		6487	#define I2C_CCR_FS I2C_CCR_FS_Msk /!< I2C Master Mode Selection /
2	mjames	6488
		6489	/**************** Bit definition for I2C_TRISE register *****************/
5	mjames	6490	#define I2C_TRISE_TRISE_Pos (0U)
		6491	#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /!< 0x0000003F /
		6492	#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
2	mjames	6493
		6494	/******************************************************************************/
		6495	/* */
		6496	/* Universal Synchronous Asynchronous Receiver Transmitter */
		6497	/* */
		6498	/******************************************************************************/
		6499
		6500	/***************** Bit definition for USART_SR register *****************/
5	mjames	6501	#define USART_SR_PE_Pos (0U)
		6502	#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /!< 0x00000001 /
		6503	#define USART_SR_PE USART_SR_PE_Msk /!< Parity Error /
		6504	#define USART_SR_FE_Pos (1U)
		6505	#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /!< 0x00000002 /
		6506	#define USART_SR_FE USART_SR_FE_Msk /!< Framing Error /
		6507	#define USART_SR_NE_Pos (2U)
		6508	#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /!< 0x00000004 /
		6509	#define USART_SR_NE USART_SR_NE_Msk /!< Noise Error Flag /
		6510	#define USART_SR_ORE_Pos (3U)
		6511	#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /!< 0x00000008 /
		6512	#define USART_SR_ORE USART_SR_ORE_Msk /!< OverRun Error /
		6513	#define USART_SR_IDLE_Pos (4U)
		6514	#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /!< 0x00000010 /
		6515	#define USART_SR_IDLE USART_SR_IDLE_Msk /!< IDLE line detected /
		6516	#define USART_SR_RXNE_Pos (5U)
		6517	#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /!< 0x00000020 /
		6518	#define USART_SR_RXNE USART_SR_RXNE_Msk /!< Read Data Register Not Empty /
		6519	#define USART_SR_TC_Pos (6U)
		6520	#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /!< 0x00000040 /
		6521	#define USART_SR_TC USART_SR_TC_Msk /!< Transmission Complete /
		6522	#define USART_SR_TXE_Pos (7U)
		6523	#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /!< 0x00000080 /
		6524	#define USART_SR_TXE USART_SR_TXE_Msk /!< Transmit Data Register Empty /
		6525	#define USART_SR_LBD_Pos (8U)
		6526	#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /!< 0x00000100 /
		6527	#define USART_SR_LBD USART_SR_LBD_Msk /!< LIN Break Detection Flag /
		6528	#define USART_SR_CTS_Pos (9U)
		6529	#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /!< 0x00000200 /
		6530	#define USART_SR_CTS USART_SR_CTS_Msk /!< CTS Flag /
2	mjames	6531
		6532	/***************** Bit definition for USART_DR register *****************/
5	mjames	6533	#define USART_DR_DR_Pos (0U)
		6534	#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /!< 0x000001FF /
		6535	#define USART_DR_DR USART_DR_DR_Msk /!< Data value /
2	mjames	6536
		6537	/**************** Bit definition for USART_BRR register *****************/
5	mjames	6538	#define USART_BRR_DIV_Fraction_Pos (0U)
		6539	#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /!< 0x0000000F /
		6540	#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /!< Fraction of USARTDIV /
		6541	#define USART_BRR_DIV_Mantissa_Pos (4U)
		6542	#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /!< 0x0000FFF0 /
		6543	#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /!< Mantissa of USARTDIV /
2	mjames	6544
		6545	/**************** Bit definition for USART_CR1 register *****************/
5	mjames	6546	#define USART_CR1_SBK_Pos (0U)
		6547	#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /!< 0x00000001 /
		6548	#define USART_CR1_SBK USART_CR1_SBK_Msk /!< Send Break /
		6549	#define USART_CR1_RWU_Pos (1U)
		6550	#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /!< 0x00000002 /
		6551	#define USART_CR1_RWU USART_CR1_RWU_Msk /!< Receiver wakeup /
		6552	#define USART_CR1_RE_Pos (2U)
		6553	#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /!< 0x00000004 /
		6554	#define USART_CR1_RE USART_CR1_RE_Msk /!< Receiver Enable /
		6555	#define USART_CR1_TE_Pos (3U)
		6556	#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /!< 0x00000008 /
		6557	#define USART_CR1_TE USART_CR1_TE_Msk /!< Transmitter Enable /
		6558	#define USART_CR1_IDLEIE_Pos (4U)
		6559	#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /!< 0x00000010 /
		6560	#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /!< IDLE Interrupt Enable /
		6561	#define USART_CR1_RXNEIE_Pos (5U)
		6562	#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /!< 0x00000020 /
		6563	#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /!< RXNE Interrupt Enable /
		6564	#define USART_CR1_TCIE_Pos (6U)
		6565	#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /!< 0x00000040 /
		6566	#define USART_CR1_TCIE USART_CR1_TCIE_Msk /!< Transmission Complete Interrupt Enable /
		6567	#define USART_CR1_TXEIE_Pos (7U)
		6568	#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /!< 0x00000080 /
		6569	#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /!< PE Interrupt Enable /
		6570	#define USART_CR1_PEIE_Pos (8U)
		6571	#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /!< 0x00000100 /
		6572	#define USART_CR1_PEIE USART_CR1_PEIE_Msk /!< PE Interrupt Enable /
		6573	#define USART_CR1_PS_Pos (9U)
		6574	#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /!< 0x00000200 /
		6575	#define USART_CR1_PS USART_CR1_PS_Msk /!< Parity Selection /
		6576	#define USART_CR1_PCE_Pos (10U)
		6577	#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /!< 0x00000400 /
		6578	#define USART_CR1_PCE USART_CR1_PCE_Msk /!< Parity Control Enable /
		6579	#define USART_CR1_WAKE_Pos (11U)
		6580	#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /!< 0x00000800 /
		6581	#define USART_CR1_WAKE USART_CR1_WAKE_Msk /!< Wakeup method /
		6582	#define USART_CR1_M_Pos (12U)
		6583	#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /!< 0x00001000 /
		6584	#define USART_CR1_M USART_CR1_M_Msk /!< Word length /
		6585	#define USART_CR1_UE_Pos (13U)
		6586	#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /!< 0x00002000 /
		6587	#define USART_CR1_UE USART_CR1_UE_Msk /!< USART Enable /
2	mjames	6588
		6589	/**************** Bit definition for USART_CR2 register *****************/
5	mjames	6590	#define USART_CR2_ADD_Pos (0U)
		6591	#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /!< 0x0000000F /
		6592	#define USART_CR2_ADD USART_CR2_ADD_Msk /!< Address of the USART node /
		6593	#define USART_CR2_LBDL_Pos (5U)
		6594	#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /!< 0x00000020 /
		6595	#define USART_CR2_LBDL USART_CR2_LBDL_Msk /!< LIN Break Detection Length /
		6596	#define USART_CR2_LBDIE_Pos (6U)
		6597	#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /!< 0x00000040 /
		6598	#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /!< LIN Break Detection Interrupt Enable /
		6599	#define USART_CR2_LBCL_Pos (8U)
		6600	#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /!< 0x00000100 /
		6601	#define USART_CR2_LBCL USART_CR2_LBCL_Msk /!< Last Bit Clock pulse /
		6602	#define USART_CR2_CPHA_Pos (9U)
		6603	#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /!< 0x00000200 /
		6604	#define USART_CR2_CPHA USART_CR2_CPHA_Msk /!< Clock Phase /
		6605	#define USART_CR2_CPOL_Pos (10U)
		6606	#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /!< 0x00000400 /
		6607	#define USART_CR2_CPOL USART_CR2_CPOL_Msk /!< Clock Polarity /
		6608	#define USART_CR2_CLKEN_Pos (11U)
		6609	#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /!< 0x00000800 /
		6610	#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /!< Clock Enable /
2	mjames	6611
5	mjames	6612	#define USART_CR2_STOP_Pos (12U)
		6613	#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /!< 0x00003000 /
		6614	#define USART_CR2_STOP USART_CR2_STOP_Msk /!< STOP[1:0] bits (STOP bits) /
		6615	#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /!< 0x00001000 /
		6616	#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /!< 0x00002000 /
2	mjames	6617
5	mjames	6618	#define USART_CR2_LINEN_Pos (14U)
		6619	#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /!< 0x00004000 /
		6620	#define USART_CR2_LINEN USART_CR2_LINEN_Msk /!< LIN mode enable /
2	mjames	6621
		6622	/**************** Bit definition for USART_CR3 register *****************/
5	mjames	6623	#define USART_CR3_EIE_Pos (0U)
		6624	#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /!< 0x00000001 /
		6625	#define USART_CR3_EIE USART_CR3_EIE_Msk /!< Error Interrupt Enable /
		6626	#define USART_CR3_IREN_Pos (1U)
		6627	#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /!< 0x00000002 /
		6628	#define USART_CR3_IREN USART_CR3_IREN_Msk /!< IrDA mode Enable /
		6629	#define USART_CR3_IRLP_Pos (2U)
		6630	#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /!< 0x00000004 /
		6631	#define USART_CR3_IRLP USART_CR3_IRLP_Msk /!< IrDA Low-Power /
		6632	#define USART_CR3_HDSEL_Pos (3U)
		6633	#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /!< 0x00000008 /
		6634	#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /!< Half-Duplex Selection /
		6635	#define USART_CR3_NACK_Pos (4U)
		6636	#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /!< 0x00000010 /
		6637	#define USART_CR3_NACK USART_CR3_NACK_Msk /!< Smartcard NACK enable /
		6638	#define USART_CR3_SCEN_Pos (5U)
		6639	#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /!< 0x00000020 /
		6640	#define USART_CR3_SCEN USART_CR3_SCEN_Msk /!< Smartcard mode enable /
		6641	#define USART_CR3_DMAR_Pos (6U)
		6642	#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /!< 0x00000040 /
		6643	#define USART_CR3_DMAR USART_CR3_DMAR_Msk /!< DMA Enable Receiver /
		6644	#define USART_CR3_DMAT_Pos (7U)
		6645	#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /!< 0x00000080 /
		6646	#define USART_CR3_DMAT USART_CR3_DMAT_Msk /!< DMA Enable Transmitter /
		6647	#define USART_CR3_RTSE_Pos (8U)
		6648	#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /!< 0x00000100 /
		6649	#define USART_CR3_RTSE USART_CR3_RTSE_Msk /!< RTS Enable /
		6650	#define USART_CR3_CTSE_Pos (9U)
		6651	#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /!< 0x00000200 /
		6652	#define USART_CR3_CTSE USART_CR3_CTSE_Msk /!< CTS Enable /
		6653	#define USART_CR3_CTSIE_Pos (10U)
		6654	#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /!< 0x00000400 /
		6655	#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /!< CTS Interrupt Enable /
2	mjames	6656
		6657	/**************** Bit definition for USART_GTPR register ****************/
5	mjames	6658	#define USART_GTPR_PSC_Pos (0U)
		6659	#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /!< 0x000000FF /
		6660	#define USART_GTPR_PSC USART_GTPR_PSC_Msk /!< PSC[7:0] bits (Prescaler value) /
		6661	#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /!< 0x00000001 /
		6662	#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /!< 0x00000002 /
		6663	#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /!< 0x00000004 /
		6664	#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /!< 0x00000008 /
		6665	#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /!< 0x00000010 /
		6666	#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /!< 0x00000020 /
		6667	#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /!< 0x00000040 /
		6668	#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /!< 0x00000080 /
2	mjames	6669
5	mjames	6670	#define USART_GTPR_GT_Pos (8U)
		6671	#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /!< 0x0000FF00 /
		6672	#define USART_GTPR_GT USART_GTPR_GT_Msk /!< Guard time value /
2	mjames	6673
		6674	/******************************************************************************/
		6675	/* */
		6676	/* Debug MCU */
		6677	/* */
		6678	/******************************************************************************/
		6679
		6680	/************** Bit definition for DBGMCU_IDCODE register ***************/
5	mjames	6681	#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
		6682	#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /!< 0x00000FFF /
		6683	#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /!< Device Identifier /
2	mjames	6684
5	mjames	6685	#define DBGMCU_IDCODE_REV_ID_Pos (16U)
		6686	#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /!< 0xFFFF0000 /
		6687	#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /!< REV_ID[15:0] bits (Revision Identifier) /
		6688	#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00010000 /
		6689	#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00020000 /
		6690	#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00040000 /
		6691	#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00080000 /
		6692	#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00100000 /
		6693	#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00200000 /
		6694	#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00400000 /
		6695	#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00800000 /
		6696	#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x01000000 /
		6697	#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x02000000 /
		6698	#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x04000000 /
		6699	#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x08000000 /
		6700	#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x10000000 /
		6701	#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x20000000 /
		6702	#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x40000000 /
		6703	#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x80000000 /
2	mjames	6704
		6705	/**************** Bit definition for DBGMCU_CR register *****************/
5	mjames	6706	#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
		6707	#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /!< 0x00000001 /
		6708	#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /!< Debug Sleep Mode /
		6709	#define DBGMCU_CR_DBG_STOP_Pos (1U)
		6710	#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /!< 0x00000002 /
		6711	#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /!< Debug Stop Mode /
		6712	#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
		6713	#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /!< 0x00000004 /
		6714	#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /!< Debug Standby mode /
		6715	#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
		6716	#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /!< 0x00000020 /
		6717	#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /!< Trace Pin Assignment Control /
2	mjames	6718
5	mjames	6719	#define DBGMCU_CR_TRACE_MODE_Pos (6U)
		6720	#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x000000C0 /
		6721	#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
		6722	#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000040 /
		6723	#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000080 /
2	mjames	6724
5	mjames	6725	#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
		6726	#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /!< 0x00000100 /
		6727	#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /!< Debug Independent Watchdog stopped when Core is halted /
		6728	#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
		6729	#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /!< 0x00000200 /
		6730	#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /!< Debug Window Watchdog stopped when Core is halted /
		6731	#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
		6732	#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /!< 0x00000400 /
		6733	#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /!< TIM1 counter stopped when core is halted /
		6734	#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
		6735	#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /!< 0x00000800 /
		6736	#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /!< TIM2 counter stopped when core is halted /
		6737	#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
		6738	#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /!< 0x00001000 /
		6739	#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /!< TIM3 counter stopped when core is halted /
		6740	#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
		6741	#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /!< 0x00002000 /
		6742	#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /!< TIM4 counter stopped when core is halted /
		6743	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
		6744	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /!< 0x00008000 /
		6745	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		6746	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
		6747	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /!< 0x00010000 /
		6748	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		6749	#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
		6750	#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /!< 0x00040000 /
		6751	#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /!< TIM5 counter stopped when core is halted /
		6752	#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
		6753	#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /!< 0x00080000 /
		6754	#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /!< TIM6 counter stopped when core is halted /
		6755	#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
		6756	#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /!< 0x00100000 /
		6757	#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /!< TIM7 counter stopped when core is halted /
		6758	#define DBGMCU_CR_DBG_TIM15_STOP_Pos (22U)
		6759	#define DBGMCU_CR_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM15_STOP_Pos) /!< 0x00400000 /
		6760	#define DBGMCU_CR_DBG_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP_Msk /!< Debug TIM15 stopped when Core is halted /
		6761	#define DBGMCU_CR_DBG_TIM16_STOP_Pos (23U)
		6762	#define DBGMCU_CR_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM16_STOP_Pos) /!< 0x00800000 /
		6763	#define DBGMCU_CR_DBG_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP_Msk /!< Debug TIM16 stopped when Core is halted /
		6764	#define DBGMCU_CR_DBG_TIM17_STOP_Pos (24U)
		6765	#define DBGMCU_CR_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM17_STOP_Pos) /!< 0x01000000 /
		6766	#define DBGMCU_CR_DBG_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP_Msk /!< Debug TIM17 stopped when Core is halted /
		6767	#define DBGMCU_CR_DBG_TIM12_STOP_Pos (25U)
		6768	#define DBGMCU_CR_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM12_STOP_Pos) /!< 0x02000000 /
		6769	#define DBGMCU_CR_DBG_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP_Msk /!< Debug TIM12 stopped when Core is halted /
		6770	#define DBGMCU_CR_DBG_TIM13_STOP_Pos (26U)
		6771	#define DBGMCU_CR_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM13_STOP_Pos) /!< 0x04000000 /
		6772	#define DBGMCU_CR_DBG_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP_Msk /!< Debug TIM13 stopped when Core is halted /
		6773	#define DBGMCU_CR_DBG_TIM14_STOP_Pos (27U)
		6774	#define DBGMCU_CR_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM14_STOP_Pos) /!< 0x08000000 /
		6775	#define DBGMCU_CR_DBG_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP_Msk /!< Debug TIM14 stopped when Core is halted /
2	mjames	6776
		6777	/******************************************************************************/
		6778	/* */
		6779	/* FLASH and Option Bytes Registers */
		6780	/* */
		6781	/******************************************************************************/
		6782	/***************** Bit definition for FLASH_ACR register ****************/
5	mjames	6783	#define FLASH_ACR_HLFCYA_Pos (3U)
		6784	#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /!< 0x00000008 /
		6785	#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /!< Flash Half Cycle Access Enable /
2	mjames	6786
		6787	/**************** Bit definition for FLASH_KEYR register ****************/
5	mjames	6788	#define FLASH_KEYR_FKEYR_Pos (0U)
		6789	#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /!< 0xFFFFFFFF /
		6790	#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /!< FPEC Key /
2	mjames	6791
5	mjames	6792	#define RDP_KEY_Pos (0U)
		6793	#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /!< 0x000000A5 /
		6794	#define RDP_KEY RDP_KEY_Msk /!< RDP Key /
		6795	#define FLASH_KEY1_Pos (0U)
		6796	#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /!< 0x45670123 /
		6797	#define FLASH_KEY1 FLASH_KEY1_Msk /!< FPEC Key1 /
		6798	#define FLASH_KEY2_Pos (0U)
		6799	#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /!< 0xCDEF89AB /
		6800	#define FLASH_KEY2 FLASH_KEY2_Msk /!< FPEC Key2 /
2	mjames	6801
		6802	/*************** Bit definition for FLASH_OPTKEYR register **************/
5	mjames	6803	#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
		6804	#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /!< 0xFFFFFFFF /
		6805	#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /!< Option Byte Key /
2	mjames	6806
		6807	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
		6808	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
		6809
		6810	/**************** Bit definition for FLASH_SR register ******************/
5	mjames	6811	#define FLASH_SR_BSY_Pos (0U)
		6812	#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /!< 0x00000001 /
		6813	#define FLASH_SR_BSY FLASH_SR_BSY_Msk /!< Busy /
		6814	#define FLASH_SR_PGERR_Pos (2U)
		6815	#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /!< 0x00000004 /
		6816	#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /!< Programming Error /
		6817	#define FLASH_SR_WRPRTERR_Pos (4U)
		6818	#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /!< 0x00000010 /
		6819	#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /!< Write Protection Error /
		6820	#define FLASH_SR_EOP_Pos (5U)
		6821	#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /!< 0x00000020 /
		6822	#define FLASH_SR_EOP FLASH_SR_EOP_Msk /!< End of operation /
2	mjames	6823
		6824	/***************** Bit definition for FLASH_CR register *****************/
5	mjames	6825	#define FLASH_CR_PG_Pos (0U)
		6826	#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /!< 0x00000001 /
		6827	#define FLASH_CR_PG FLASH_CR_PG_Msk /!< Programming /
		6828	#define FLASH_CR_PER_Pos (1U)
		6829	#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /!< 0x00000002 /
		6830	#define FLASH_CR_PER FLASH_CR_PER_Msk /!< Page Erase /
		6831	#define FLASH_CR_MER_Pos (2U)
		6832	#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /!< 0x00000004 /
		6833	#define FLASH_CR_MER FLASH_CR_MER_Msk /!< Mass Erase /
		6834	#define FLASH_CR_OPTPG_Pos (4U)
		6835	#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /!< 0x00000010 /
		6836	#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /!< Option Byte Programming /
		6837	#define FLASH_CR_OPTER_Pos (5U)
		6838	#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /!< 0x00000020 /
		6839	#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /!< Option Byte Erase /
		6840	#define FLASH_CR_STRT_Pos (6U)
		6841	#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /!< 0x00000040 /
		6842	#define FLASH_CR_STRT FLASH_CR_STRT_Msk /!< Start /
		6843	#define FLASH_CR_LOCK_Pos (7U)
		6844	#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /!< 0x00000080 /
		6845	#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /!< Lock /
		6846	#define FLASH_CR_OPTWRE_Pos (9U)
		6847	#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /!< 0x00000200 /
		6848	#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /!< Option Bytes Write Enable /
		6849	#define FLASH_CR_ERRIE_Pos (10U)
		6850	#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /!< 0x00000400 /
		6851	#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /!< Error Interrupt Enable /
		6852	#define FLASH_CR_EOPIE_Pos (12U)
		6853	#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /!< 0x00001000 /
		6854	#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /!< End of operation interrupt enable /
2	mjames	6855
		6856	/***************** Bit definition for FLASH_AR register *****************/
5	mjames	6857	#define FLASH_AR_FAR_Pos (0U)
		6858	#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /!< 0xFFFFFFFF /
		6859	#define FLASH_AR_FAR FLASH_AR_FAR_Msk /!< Flash Address /
2	mjames	6860
		6861	/**************** Bit definition for FLASH_OBR register *****************/
5	mjames	6862	#define FLASH_OBR_OPTERR_Pos (0U)
		6863	#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /!< 0x00000001 /
		6864	#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /!< Option Byte Error /
		6865	#define FLASH_OBR_RDPRT_Pos (1U)
		6866	#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /!< 0x00000002 /
		6867	#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /!< Read protection /
2	mjames	6868
5	mjames	6869	#define FLASH_OBR_IWDG_SW_Pos (2U)
		6870	#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /!< 0x00000004 /
		6871	#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /!< IWDG SW /
		6872	#define FLASH_OBR_nRST_STOP_Pos (3U)
		6873	#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /!< 0x00000008 /
		6874	#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /!< nRST_STOP /
		6875	#define FLASH_OBR_nRST_STDBY_Pos (4U)
		6876	#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /!< 0x00000010 /
		6877	#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /!< nRST_STDBY /
		6878	#define FLASH_OBR_USER_Pos (2U)
		6879	#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /!< 0x0000001C /
		6880	#define FLASH_OBR_USER FLASH_OBR_USER_Msk /!< User Option Bytes /
		6881	#define FLASH_OBR_DATA0_Pos (10U)
		6882	#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /!< 0x0003FC00 /
		6883	#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /!< Data0 /
		6884	#define FLASH_OBR_DATA1_Pos (18U)
		6885	#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /!< 0x03FC0000 /
		6886	#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /!< Data1 /
2	mjames	6887
		6888	/**************** Bit definition for FLASH_WRPR register ****************/
5	mjames	6889	#define FLASH_WRPR_WRP_Pos (0U)
		6890	#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /!< 0xFFFFFFFF /
		6891	#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /!< Write Protect /
2	mjames	6892
		6893	/----------------------------------------------------------------------------/
		6894
		6895	/**************** Bit definition for FLASH_RDP register *****************/
5	mjames	6896	#define FLASH_RDP_RDP_Pos (0U)
		6897	#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /!< 0x000000FF /
		6898	#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /!< Read protection option byte /
		6899	#define FLASH_RDP_nRDP_Pos (8U)
		6900	#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /!< 0x0000FF00 /
		6901	#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /!< Read protection complemented option byte /
2	mjames	6902
		6903	/**************** Bit definition for FLASH_USER register ****************/
5	mjames	6904	#define FLASH_USER_USER_Pos (16U)
		6905	#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /!< 0x00FF0000 /
		6906	#define FLASH_USER_USER FLASH_USER_USER_Msk /!< User option byte /
		6907	#define FLASH_USER_nUSER_Pos (24U)
		6908	#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /!< 0xFF000000 /
		6909	#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /!< User complemented option byte /
2	mjames	6910
		6911	/**************** Bit definition for FLASH_Data0 register ***************/
5	mjames	6912	#define FLASH_DATA0_DATA0_Pos (0U)
		6913	#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /!< 0x000000FF /
		6914	#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /!< User data storage option byte /
		6915	#define FLASH_DATA0_nDATA0_Pos (8U)
		6916	#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /!< 0x0000FF00 /
		6917	#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /!< User data storage complemented option byte /
2	mjames	6918
		6919	/**************** Bit definition for FLASH_Data1 register ***************/
5	mjames	6920	#define FLASH_DATA1_DATA1_Pos (16U)
		6921	#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /!< 0x00FF0000 /
		6922	#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /!< User data storage option byte /
		6923	#define FLASH_DATA1_nDATA1_Pos (24U)
		6924	#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /!< 0xFF000000 /
		6925	#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /!< User data storage complemented option byte /
2	mjames	6926
		6927	/**************** Bit definition for FLASH_WRP0 register ****************/
5	mjames	6928	#define FLASH_WRP0_WRP0_Pos (0U)
		6929	#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /!< 0x000000FF /
		6930	#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /!< Flash memory write protection option bytes /
		6931	#define FLASH_WRP0_nWRP0_Pos (8U)
		6932	#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /!< 0x0000FF00 /
		6933	#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /!< Flash memory write protection complemented option bytes /
2	mjames	6934
		6935	/**************** Bit definition for FLASH_WRP1 register ****************/
5	mjames	6936	#define FLASH_WRP1_WRP1_Pos (16U)
		6937	#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /!< 0x00FF0000 /
		6938	#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /!< Flash memory write protection option bytes /
		6939	#define FLASH_WRP1_nWRP1_Pos (24U)
		6940	#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /!< 0xFF000000 /
		6941	#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /!< Flash memory write protection complemented option bytes /
2	mjames	6942
		6943	/**************** Bit definition for FLASH_WRP2 register ****************/
5	mjames	6944	#define FLASH_WRP2_WRP2_Pos (0U)
		6945	#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /!< 0x000000FF /
		6946	#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /!< Flash memory write protection option bytes /
		6947	#define FLASH_WRP2_nWRP2_Pos (8U)
		6948	#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /!< 0x0000FF00 /
		6949	#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /!< Flash memory write protection complemented option bytes /
2	mjames	6950
		6951	/**************** Bit definition for FLASH_WRP3 register ****************/
5	mjames	6952	#define FLASH_WRP3_WRP3_Pos (16U)
		6953	#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /!< 0x00FF0000 /
		6954	#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /!< Flash memory write protection option bytes /
		6955	#define FLASH_WRP3_nWRP3_Pos (24U)
		6956	#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /!< 0xFF000000 /
		6957	#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /!< Flash memory write protection complemented option bytes /
2	mjames	6958
		6959
		6960
		6961	/**
		6962	* @}
		6963	*/
		6964
		6965	/**
		6966	* @}
		6967	*/
		6968
		6969	/** @addtogroup Exported_macro
		6970	* @{
		6971	*/
		6972
		6973	/**************************** ADC Instances *******************************/
		6974	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
		6975
5	mjames	6976	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
		6977
2	mjames	6978	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		6979
		6980	/**************************** CEC Instances *******************************/
		6981	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
		6982
		6983	/**************************** CRC Instances *******************************/
		6984	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		6985
		6986	/**************************** DAC Instances *******************************/
		6987	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
		6988
		6989	/**************************** DMA Instances *******************************/
		6990	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		6991	((INSTANCE) == DMA1_Channel2) \|\| \
		6992	((INSTANCE) == DMA1_Channel3) \|\| \
		6993	((INSTANCE) == DMA1_Channel4) \|\| \
		6994	((INSTANCE) == DMA1_Channel5) \|\| \
		6995	((INSTANCE) == DMA1_Channel6) \|\| \
		6996	((INSTANCE) == DMA1_Channel7) \|\| \
		6997	((INSTANCE) == DMA2_Channel1) \|\| \
		6998	((INSTANCE) == DMA2_Channel2) \|\| \
		6999	((INSTANCE) == DMA2_Channel3) \|\| \
		7000	((INSTANCE) == DMA2_Channel4) \|\| \
		7001	((INSTANCE) == DMA2_Channel5))
		7002
		7003	/***************************** GPIO Instances *****************************/
		7004	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		7005	((INSTANCE) == GPIOB) \|\| \
		7006	((INSTANCE) == GPIOC) \|\| \
		7007	((INSTANCE) == GPIOD) \|\| \
		7008	((INSTANCE) == GPIOE) \|\| \
		7009	((INSTANCE) == GPIOF) \|\| \
		7010	((INSTANCE) == GPIOG))
		7011
		7012	/************************** GPIO Alternate Function Instances *************/
		7013	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		7014
		7015	/************************** GPIO Lock Instances ***************************/
		7016	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		7017
		7018	/****************************** I2C Instances *****************************/
		7019	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		7020	((INSTANCE) == I2C2))
		7021
		7022	/**************************** IWDG Instances ******************************/
		7023	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		7024
		7025	/****************************** SPI Instances *****************************/
		7026	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		7027	((INSTANCE) == SPI2) \|\| \
		7028	((INSTANCE) == SPI3))
		7029
		7030	/**************************** START TIM Instances *************************/
		7031	/**************************** TIM Instances *******************************/
		7032	#define IS_TIM_INSTANCE(INSTANCE)\
		7033	(((INSTANCE) == TIM1) \|\| \
		7034	((INSTANCE) == TIM2) \|\| \
		7035	((INSTANCE) == TIM3) \|\| \
		7036	((INSTANCE) == TIM4) \|\| \
		7037	((INSTANCE) == TIM5) \|\| \
		7038	((INSTANCE) == TIM6) \|\| \
		7039	((INSTANCE) == TIM7) \|\| \
		7040	((INSTANCE) == TIM12) \|\| \
		7041	((INSTANCE) == TIM13) \|\| \
		7042	((INSTANCE) == TIM14) \|\| \
		7043	((INSTANCE) == TIM15) \|\| \
		7044	((INSTANCE) == TIM16) \|\| \
		7045	((INSTANCE) == TIM17))
		7046
		7047	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
		7048	(((INSTANCE) == TIM1) \|\| \
		7049	((INSTANCE) == TIM2) \|\| \
		7050	((INSTANCE) == TIM3) \|\| \
		7051	((INSTANCE) == TIM4) \|\| \
		7052	((INSTANCE) == TIM5) \|\| \
		7053	((INSTANCE) == TIM12) \|\| \
		7054	((INSTANCE) == TIM13) \|\| \
		7055	((INSTANCE) == TIM14) \|\| \
		7056	((INSTANCE) == TIM15) \|\| \
		7057	((INSTANCE) == TIM16) \|\| \
		7058	((INSTANCE) == TIM17))
		7059
		7060	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
		7061	(((INSTANCE) == TIM1) \|\| \
		7062	((INSTANCE) == TIM2) \|\| \
		7063	((INSTANCE) == TIM3) \|\| \
		7064	((INSTANCE) == TIM4) \|\| \
		7065	((INSTANCE) == TIM5) \|\| \
		7066	((INSTANCE) == TIM12) \|\| \
		7067	((INSTANCE) == TIM15))
		7068
		7069	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
		7070	(((INSTANCE) == TIM1) \|\| \
		7071	((INSTANCE) == TIM2) \|\| \
		7072	((INSTANCE) == TIM3) \|\| \
		7073	((INSTANCE) == TIM4) \|\| \
		7074	((INSTANCE) == TIM5))
		7075
		7076	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
		7077	(((INSTANCE) == TIM1) \|\| \
		7078	((INSTANCE) == TIM2) \|\| \
		7079	((INSTANCE) == TIM3) \|\| \
		7080	((INSTANCE) == TIM4) \|\| \
		7081	((INSTANCE) == TIM5))
		7082
		7083	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
		7084	(((INSTANCE) == TIM1) \|\| \
		7085	((INSTANCE) == TIM2) \|\| \
		7086	((INSTANCE) == TIM3) \|\| \
		7087	((INSTANCE) == TIM4) \|\| \
		7088	((INSTANCE) == TIM5))
		7089
		7090	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
		7091	(((INSTANCE) == TIM1) \|\| \
		7092	((INSTANCE) == TIM2) \|\| \
		7093	((INSTANCE) == TIM3) \|\| \
		7094	((INSTANCE) == TIM4) \|\| \
		7095	((INSTANCE) == TIM5))
		7096
		7097	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
		7098	(((INSTANCE) == TIM1) \|\| \
		7099	((INSTANCE) == TIM2) \|\| \
		7100	((INSTANCE) == TIM3) \|\| \
		7101	((INSTANCE) == TIM4) \|\| \
		7102	((INSTANCE) == TIM5) \|\| \
		7103	((INSTANCE) == TIM12) \|\| \
		7104	((INSTANCE) == TIM15))
		7105
		7106	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
		7107	(((INSTANCE) == TIM1) \|\| \
		7108	((INSTANCE) == TIM2) \|\| \
		7109	((INSTANCE) == TIM3) \|\| \
		7110	((INSTANCE) == TIM4) \|\| \
		7111	((INSTANCE) == TIM5) \|\| \
		7112	((INSTANCE) == TIM12) \|\| \
		7113	((INSTANCE) == TIM15))
		7114
		7115	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
		7116	(((INSTANCE) == TIM1) \|\| \
		7117	((INSTANCE) == TIM2) \|\| \
		7118	((INSTANCE) == TIM3) \|\| \
		7119	((INSTANCE) == TIM4) \|\| \
		7120	((INSTANCE) == TIM5))
		7121
		7122	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
		7123	(((INSTANCE) == TIM1) \|\| \
		7124	((INSTANCE) == TIM2) \|\| \
		7125	((INSTANCE) == TIM3) \|\| \
		7126	((INSTANCE) == TIM4) \|\| \
		7127	((INSTANCE) == TIM5))
		7128
		7129	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
		7130	(((INSTANCE) == TIM1) \|\| \
		7131	((INSTANCE) == TIM2) \|\| \
		7132	((INSTANCE) == TIM3) \|\| \
		7133	((INSTANCE) == TIM4) \|\| \
		7134	((INSTANCE) == TIM5))
		7135
		7136	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
		7137	(((INSTANCE) == TIM1) \|\| \
		7138	((INSTANCE) == TIM2) \|\| \
		7139	((INSTANCE) == TIM3) \|\| \
		7140	((INSTANCE) == TIM4) \|\| \
		7141	((INSTANCE) == TIM5) \|\| \
		7142	((INSTANCE) == TIM6) \|\| \
		7143	((INSTANCE) == TIM7) \|\| \
		7144	((INSTANCE) == TIM12) \|\| \
		7145	((INSTANCE) == TIM15))
		7146
		7147	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
		7148	(((INSTANCE) == TIM1) \|\| \
		7149	((INSTANCE) == TIM2) \|\| \
		7150	((INSTANCE) == TIM3) \|\| \
		7151	((INSTANCE) == TIM4) \|\| \
		7152	((INSTANCE) == TIM5) \|\| \
		7153	((INSTANCE) == TIM12) \|\| \
		7154	((INSTANCE) == TIM15))
		7155
		7156	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
		7157	(((INSTANCE) == TIM1) \|\| \
		7158	((INSTANCE) == TIM2) \|\| \
		7159	((INSTANCE) == TIM3) \|\| \
		7160	((INSTANCE) == TIM4) \|\| \
		7161	((INSTANCE) == TIM5) \|\| \
		7162	((INSTANCE) == TIM15) \|\| \
		7163	((INSTANCE) == TIM16) \|\| \
		7164	((INSTANCE) == TIM17))
		7165
		7166	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
		7167	(((INSTANCE) == TIM1) \|\| \
		7168	((INSTANCE) == TIM15) \|\| \
		7169	((INSTANCE) == TIM16) \|\| \
		7170	((INSTANCE) == TIM17))
		7171
		7172	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		7173	((((INSTANCE) == TIM1) && \
		7174	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7175	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7176	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7177	((CHANNEL) == TIM_CHANNEL_4))) \
		7178	\|\| \
		7179	(((INSTANCE) == TIM2) && \
		7180	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7181	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7182	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7183	((CHANNEL) == TIM_CHANNEL_4))) \
		7184	\|\| \
		7185	(((INSTANCE) == TIM3) && \
		7186	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7187	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7188	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7189	((CHANNEL) == TIM_CHANNEL_4))) \
		7190	\|\| \
		7191	(((INSTANCE) == TIM4) && \
		7192	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7193	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7194	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7195	((CHANNEL) == TIM_CHANNEL_4))) \
		7196	\|\| \
		7197	(((INSTANCE) == TIM5) && \
		7198	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7199	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7200	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7201	((CHANNEL) == TIM_CHANNEL_4))) \
		7202	\|\| \
		7203	(((INSTANCE) == TIM12) && \
		7204	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7205	((CHANNEL) == TIM_CHANNEL_2))) \
		7206	\|\| \
		7207	(((INSTANCE) == TIM13) && \
		7208	(((CHANNEL) == TIM_CHANNEL_1))) \
		7209	\|\| \
		7210	(((INSTANCE) == TIM14) && \
		7211	(((CHANNEL) == TIM_CHANNEL_1))) \
		7212	\|\| \
		7213	(((INSTANCE) == TIM15) && \
		7214	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7215	((CHANNEL) == TIM_CHANNEL_2))) \
		7216	\|\| \
		7217	(((INSTANCE) == TIM16) && \
		7218	(((CHANNEL) == TIM_CHANNEL_1))) \
		7219	\|\| \
		7220	(((INSTANCE) == TIM17) && \
		7221	(((CHANNEL) == TIM_CHANNEL_1))))
		7222
		7223	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
		7224	((((INSTANCE) == TIM1) && \
		7225	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7226	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7227	((CHANNEL) == TIM_CHANNEL_3))) \
		7228	\|\| \
		7229	(((INSTANCE) == TIM15) && \
		7230	((CHANNEL) == TIM_CHANNEL_1)) \
		7231	\|\| \
		7232	(((INSTANCE) == TIM16) && \
		7233	((CHANNEL) == TIM_CHANNEL_1)) \
		7234	\|\| \
		7235	(((INSTANCE) == TIM17) && \
		7236	((CHANNEL) == TIM_CHANNEL_1)))
		7237
		7238	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
		7239	(((INSTANCE) == TIM1) \|\| \
		7240	((INSTANCE) == TIM2) \|\| \
		7241	((INSTANCE) == TIM3) \|\| \
		7242	((INSTANCE) == TIM4) \|\| \
		7243	((INSTANCE) == TIM5))
		7244
		7245	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
		7246	(((INSTANCE) == TIM1) \|\| \
		7247	((INSTANCE) == TIM15) \|\| \
		7248	((INSTANCE) == TIM16) \|\| \
		7249	((INSTANCE) == TIM17))
		7250
		7251	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
		7252	(((INSTANCE) == TIM1) \|\| \
		7253	((INSTANCE) == TIM2) \|\| \
		7254	((INSTANCE) == TIM3) \|\| \
		7255	((INSTANCE) == TIM4) \|\| \
		7256	((INSTANCE) == TIM5) \|\| \
		7257	((INSTANCE) == TIM12) \|\| \
		7258	((INSTANCE) == TIM13) \|\| \
		7259	((INSTANCE) == TIM14) \|\| \
		7260	((INSTANCE) == TIM15) \|\| \
		7261	((INSTANCE) == TIM16) \|\| \
		7262	((INSTANCE) == TIM17))
		7263
		7264	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
		7265	(((INSTANCE) == TIM1) \|\| \
		7266	((INSTANCE) == TIM2) \|\| \
		7267	((INSTANCE) == TIM3) \|\| \
		7268	((INSTANCE) == TIM4) \|\| \
		7269	((INSTANCE) == TIM5) \|\| \
		7270	((INSTANCE) == TIM6) \|\| \
		7271	((INSTANCE) == TIM7) \|\| \
		7272	((INSTANCE) == TIM15) \|\| \
		7273	((INSTANCE) == TIM16) \|\| \
		7274	((INSTANCE) == TIM17))
		7275
		7276	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
		7277	(((INSTANCE) == TIM1) \|\| \
		7278	((INSTANCE) == TIM2) \|\| \
		7279	((INSTANCE) == TIM3) \|\| \
		7280	((INSTANCE) == TIM4) \|\| \
		7281	((INSTANCE) == TIM5) \|\| \
		7282	((INSTANCE) == TIM15) \|\| \
		7283	((INSTANCE) == TIM16) \|\| \
		7284	((INSTANCE) == TIM17))
		7285
		7286	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
		7287	(((INSTANCE) == TIM1) \|\| \
		7288	((INSTANCE) == TIM15) \|\| \
		7289	((INSTANCE) == TIM16) \|\| \
		7290	((INSTANCE) == TIM17))
		7291
		7292	/**************************** END TIM Instances ***************************/
		7293
		7294
		7295	/****************** USART Instances : Synchronous mode ********************/
		7296	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7297	((INSTANCE) == USART2) \|\| \
		7298	((INSTANCE) == USART3))
		7299
		7300	/****************** UART Instances : Asynchronous mode ********************/
		7301	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7302	((INSTANCE) == USART2) \|\| \
		7303	((INSTANCE) == USART3) \|\| \
		7304	((INSTANCE) == UART4) \|\| \
		7305	((INSTANCE) == UART5))
		7306
		7307	/****************** UART Instances : Half-Duplex mode ********************/
		7308	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7309	((INSTANCE) == USART2) \|\| \
		7310	((INSTANCE) == USART3) \|\| \
		7311	((INSTANCE) == UART4) \|\| \
		7312	((INSTANCE) == UART5))
		7313
		7314	/****************** UART Instances : LIN mode ********************/
		7315	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7316	((INSTANCE) == USART2) \|\| \
		7317	((INSTANCE) == USART3) \|\| \
		7318	((INSTANCE) == UART4) \|\| \
		7319	((INSTANCE) == UART5))
		7320
		7321	/**************** UART Instances : Hardware Flow control ******************/
		7322	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7323	((INSTANCE) == USART2) \|\| \
		7324	((INSTANCE) == USART3))
		7325
		7326	/******************* UART Instances : Smard card mode *********************/
		7327	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7328	((INSTANCE) == USART2) \|\| \
		7329	((INSTANCE) == USART3))
		7330
		7331	/********************* UART Instances : IRDA mode *************************/
		7332	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7333	((INSTANCE) == USART2) \|\| \
		7334	((INSTANCE) == USART3) \|\| \
		7335	((INSTANCE) == UART4) \|\| \
		7336	((INSTANCE) == UART5))
		7337
		7338	/*************** UART Instances : Multi-Processor mode ********************/
		7339	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7340	((INSTANCE) == USART2) \|\| \
		7341	((INSTANCE) == USART3) \|\| \
		7342	((INSTANCE) == UART4) \|\| \
		7343	((INSTANCE) == UART5))
		7344
		7345	/*************** UART Instances : DMA mode available ********************/
		7346	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7347	((INSTANCE) == USART2) \|\| \
		7348	((INSTANCE) == USART3) \|\| \
		7349	((INSTANCE) == UART4) \|\| \
		7350	((INSTANCE) == UART5))
		7351
		7352	/**************************** RTC Instances *******************************/
		7353	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		7354
		7355	/************************** WWDG Instances ***************************/
		7356	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		7357
		7358
		7359
		7360
		7361
		7362	/**
		7363	* @}
		7364	*/
		7365	/******************************************************************************/
		7366	/* For a painless codes migration between the STM32F1xx device product */
		7367	/* lines, the aliases defined below are put in place to overcome the */
		7368	/* differences in the interrupt handlers and IRQn definitions. */
		7369	/* No need to update developed interrupt code when moving across */
		7370	/* product lines within the same STM32F1 Family */
		7371	/******************************************************************************/
		7372
		7373	/* Aliases for __IRQn */
		7374	#define ADC1_2_IRQn ADC1_IRQn
		7375	#define USBWakeUp_IRQn CEC_IRQn
		7376	#define OTG_FS_WKUP_IRQn CEC_IRQn
		7377	#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
		7378	#define TIM8_BRK_IRQn TIM12_IRQn
		7379	#define TIM8_UP_IRQn TIM13_IRQn
		7380	#define TIM8_UP_TIM13_IRQn TIM13_IRQn
		7381	#define TIM8_TRG_COM_IRQn TIM14_IRQn
		7382	#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
		7383	#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
		7384	#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
		7385	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
		7386	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
		7387	#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
		7388	#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
		7389	#define TIM10_IRQn TIM1_UP_TIM16_IRQn
		7390	#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
		7391	#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
		7392	#define TIM6_IRQn TIM6_DAC_IRQn
		7393
		7394
		7395	/* Aliases for __IRQHandler */
		7396	#define ADC1_2_IRQHandler ADC1_IRQHandler
		7397	#define USBWakeUp_IRQHandler CEC_IRQHandler
		7398	#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
		7399	#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
		7400	#define TIM8_BRK_IRQHandler TIM12_IRQHandler
		7401	#define TIM8_UP_IRQHandler TIM13_IRQHandler
		7402	#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
		7403	#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
		7404	#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
		7405	#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
		7406	#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
		7407	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
		7408	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		7409	#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		7410	#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		7411	#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
		7412	#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
		7413	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
		7414	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
		7415
		7416
		7417	/**
		7418	* @}
		7419	*/
		7420
		7421	/**
		7422	* @}
		7423	*/
		7424
		7425
		7426	#ifdef __cplusplus
		7427	}
		7428	#endif /* __cplusplus */
		7429
		7430	#endif /* __STM32F100xE_H */
		7431
		7432
		7433
		7434	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h – Rev 5