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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f100xb.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V4.2.0 |
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| 6 | * @date 31-March-2017 |
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| 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
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| 8 | * This file contains all the peripheral register's definitions, bits |
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| 9 | * definitions and memory mapping for STM32F1xx devices. |
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| 10 | * |
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| 11 | * This file contains: |
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| 12 | * - Data structures and the address mapping for all peripherals |
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| 13 | * - Peripheral's registers declarations and bits definition |
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| 14 | * - Macros to access peripheral’s registers hardware |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | * @attention |
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| 18 | * |
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| 19 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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| 20 | * |
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| 21 | * Redistribution and use in source and binary forms, with or without modification, |
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| 22 | * are permitted provided that the following conditions are met: |
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| 23 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 24 | * this list of conditions and the following disclaimer. |
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| 25 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 26 | * this list of conditions and the following disclaimer in the documentation |
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| 27 | * and/or other materials provided with the distribution. |
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| 28 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 29 | * may be used to endorse or promote products derived from this software |
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| 30 | * without specific prior written permission. |
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| 31 | * |
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| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 33 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 34 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 35 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 36 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 37 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 38 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 39 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 40 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 41 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 42 | * |
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| 43 | ****************************************************************************** |
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| 44 | */ |
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| 45 | |||
| 46 | |||
| 47 | /** @addtogroup CMSIS |
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| 48 | * @{ |
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| 49 | */ |
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| 50 | |||
| 51 | /** @addtogroup stm32f100xb |
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| 52 | * @{ |
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| 53 | */ |
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| 54 | |||
| 55 | #ifndef __STM32F100xB_H |
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| 56 | #define __STM32F100xB_H |
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| 57 | |||
| 58 | #ifdef __cplusplus |
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| 59 | extern "C" { |
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| 60 | #endif |
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| 61 | |||
| 62 | /** @addtogroup Configuration_section_for_CMSIS |
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| 63 | * @{ |
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| 64 | */ |
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| 65 | /** |
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| 66 | * @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
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| 67 | */ |
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| 68 | #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ |
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| 69 | #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ |
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| 70 | #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ |
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| 71 | #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ |
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| 72 | |||
| 73 | /** |
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| 74 | * @} |
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| 75 | */ |
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| 76 | |||
| 77 | /** @addtogroup Peripheral_interrupt_number_definition |
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| 78 | * @{ |
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| 79 | */ |
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| 80 | |||
| 81 | /** |
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| 82 | * @brief STM32F10x Interrupt Number Definition, according to the selected device |
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| 83 | * in @ref Library_configuration_section |
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| 84 | */ |
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| 85 | |||
| 86 | /*!< Interrupt Number Definition */ |
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| 87 | typedef enum |
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| 88 | { |
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| 89 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
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| 90 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
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| 91 | HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ |
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| 92 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
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| 93 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
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| 94 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
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| 95 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
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| 96 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
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| 97 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
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| 98 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
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| 99 | |||
| 100 | /****** STM32 specific Interrupt Numbers *********************************************************/ |
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| 101 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
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| 102 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
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| 103 | TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
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| 104 | RTC_IRQn = 3, /*!< RTC global Interrupt */ |
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| 105 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
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| 106 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
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| 107 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
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| 108 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
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| 109 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
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| 110 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
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| 111 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
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| 112 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
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| 113 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
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| 114 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
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| 115 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
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| 116 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
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| 117 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
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| 118 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
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| 119 | ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
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| 120 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
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| 121 | TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
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| 122 | TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
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| 123 | TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
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| 124 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
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| 125 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
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| 126 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
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| 127 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
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| 128 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
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| 129 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
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| 130 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
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| 131 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
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| 132 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
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| 133 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
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| 134 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
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| 135 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
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| 136 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
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| 137 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
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| 138 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
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| 139 | CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ |
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| 140 | TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ |
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| 141 | TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
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| 142 | } IRQn_Type; |
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| 143 | |||
| 144 | /** |
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| 145 | * @} |
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| 146 | */ |
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| 147 | |||
| 148 | #include "core_cm3.h" |
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| 149 | #include "system_stm32f1xx.h" |
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| 150 | #include <stdint.h> |
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| 151 | |||
| 152 | /** @addtogroup Peripheral_registers_structures |
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| 153 | * @{ |
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| 154 | */ |
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| 155 | |||
| 156 | /** |
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| 157 | * @brief Analog to Digital Converter |
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| 158 | */ |
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| 159 | |||
| 160 | typedef struct |
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| 161 | { |
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| 162 | __IO uint32_t SR; |
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| 163 | __IO uint32_t CR1; |
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| 164 | __IO uint32_t CR2; |
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| 165 | __IO uint32_t SMPR1; |
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| 166 | __IO uint32_t SMPR2; |
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| 167 | __IO uint32_t JOFR1; |
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| 168 | __IO uint32_t JOFR2; |
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| 169 | __IO uint32_t JOFR3; |
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| 170 | __IO uint32_t JOFR4; |
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| 171 | __IO uint32_t HTR; |
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| 172 | __IO uint32_t LTR; |
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| 173 | __IO uint32_t SQR1; |
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| 174 | __IO uint32_t SQR2; |
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| 175 | __IO uint32_t SQR3; |
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| 176 | __IO uint32_t JSQR; |
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| 177 | __IO uint32_t JDR1; |
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| 178 | __IO uint32_t JDR2; |
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| 179 | __IO uint32_t JDR3; |
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| 180 | __IO uint32_t JDR4; |
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| 181 | __IO uint32_t DR; |
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| 182 | } ADC_TypeDef; |
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| 183 | |||
| 184 | typedef struct |
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| 185 | { |
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| 186 | __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ |
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| 187 | __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ |
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| 188 | __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ |
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| 189 | uint32_t RESERVED[16]; |
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| 190 | __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ |
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| 191 | } ADC_Common_TypeDef; |
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| 192 | |||
| 193 | /** |
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| 194 | * @brief Backup Registers |
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| 195 | */ |
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| 196 | |||
| 197 | typedef struct |
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| 198 | { |
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| 199 | uint32_t RESERVED0; |
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| 200 | __IO uint32_t DR1; |
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| 201 | __IO uint32_t DR2; |
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| 202 | __IO uint32_t DR3; |
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| 203 | __IO uint32_t DR4; |
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| 204 | __IO uint32_t DR5; |
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| 205 | __IO uint32_t DR6; |
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| 206 | __IO uint32_t DR7; |
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| 207 | __IO uint32_t DR8; |
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| 208 | __IO uint32_t DR9; |
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| 209 | __IO uint32_t DR10; |
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| 210 | __IO uint32_t RTCCR; |
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| 211 | __IO uint32_t CR; |
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| 212 | __IO uint32_t CSR; |
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| 213 | } BKP_TypeDef; |
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| 214 | |||
| 215 | |||
| 216 | /** |
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| 217 | * @brief Consumer Electronics Control (CEC) |
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| 218 | */ |
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| 219 | typedef struct |
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| 220 | { |
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| 221 | __IO uint32_t CFGR; |
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| 222 | __IO uint32_t OAR; |
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| 223 | __IO uint32_t PRES; |
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| 224 | __IO uint32_t ESR; |
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| 225 | __IO uint32_t CSR; |
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| 226 | __IO uint32_t TXD; |
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| 227 | __IO uint32_t RXD; |
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| 228 | } CEC_TypeDef; |
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| 229 | |||
| 230 | /** |
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| 231 | * @brief CRC calculation unit |
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| 232 | */ |
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| 233 | |||
| 234 | typedef struct |
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| 235 | { |
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| 236 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
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| 237 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
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| 238 | uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ |
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| 239 | uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ |
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| 240 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
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| 241 | } CRC_TypeDef; |
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| 242 | |||
| 243 | /** |
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| 244 | * @brief Digital to Analog Converter |
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| 245 | */ |
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| 246 | |||
| 247 | typedef struct |
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| 248 | { |
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| 249 | __IO uint32_t CR; |
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| 250 | __IO uint32_t SWTRIGR; |
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| 251 | __IO uint32_t DHR12R1; |
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| 252 | __IO uint32_t DHR12L1; |
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| 253 | __IO uint32_t DHR8R1; |
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| 254 | __IO uint32_t DHR12R2; |
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| 255 | __IO uint32_t DHR12L2; |
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| 256 | __IO uint32_t DHR8R2; |
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| 257 | __IO uint32_t DHR12RD; |
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| 258 | __IO uint32_t DHR12LD; |
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| 259 | __IO uint32_t DHR8RD; |
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| 260 | __IO uint32_t DOR1; |
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| 261 | __IO uint32_t DOR2; |
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| 262 | __IO uint32_t SR; |
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| 263 | } DAC_TypeDef; |
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| 264 | |||
| 265 | /** |
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| 266 | * @brief Debug MCU |
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| 267 | */ |
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| 268 | |||
| 269 | typedef struct |
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| 270 | { |
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| 271 | __IO uint32_t IDCODE; |
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| 272 | __IO uint32_t CR; |
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| 273 | }DBGMCU_TypeDef; |
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| 274 | |||
| 275 | /** |
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| 276 | * @brief DMA Controller |
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| 277 | */ |
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| 278 | |||
| 279 | typedef struct |
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| 280 | { |
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| 281 | __IO uint32_t CCR; |
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| 282 | __IO uint32_t CNDTR; |
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| 283 | __IO uint32_t CPAR; |
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| 284 | __IO uint32_t CMAR; |
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| 285 | } DMA_Channel_TypeDef; |
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| 286 | |||
| 287 | typedef struct |
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| 288 | { |
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| 289 | __IO uint32_t ISR; |
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| 290 | __IO uint32_t IFCR; |
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| 291 | } DMA_TypeDef; |
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| 292 | |||
| 293 | |||
| 294 | |||
| 295 | /** |
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| 296 | * @brief External Interrupt/Event Controller |
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| 297 | */ |
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| 298 | |||
| 299 | typedef struct |
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| 300 | { |
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| 301 | __IO uint32_t IMR; |
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| 302 | __IO uint32_t EMR; |
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| 303 | __IO uint32_t RTSR; |
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| 304 | __IO uint32_t FTSR; |
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| 305 | __IO uint32_t SWIER; |
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| 306 | __IO uint32_t PR; |
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| 307 | } EXTI_TypeDef; |
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| 308 | |||
| 309 | /** |
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| 310 | * @brief FLASH Registers |
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| 311 | */ |
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| 312 | |||
| 313 | typedef struct |
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| 314 | { |
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| 315 | __IO uint32_t ACR; |
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| 316 | __IO uint32_t KEYR; |
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| 317 | __IO uint32_t OPTKEYR; |
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| 318 | __IO uint32_t SR; |
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| 319 | __IO uint32_t CR; |
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| 320 | __IO uint32_t AR; |
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| 321 | __IO uint32_t RESERVED; |
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| 322 | __IO uint32_t OBR; |
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| 323 | __IO uint32_t WRPR; |
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| 324 | } FLASH_TypeDef; |
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| 325 | |||
| 326 | /** |
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| 327 | * @brief Option Bytes Registers |
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| 328 | */ |
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| 329 | |||
| 330 | typedef struct |
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| 331 | { |
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| 332 | __IO uint16_t RDP; |
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| 333 | __IO uint16_t USER; |
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| 334 | __IO uint16_t Data0; |
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| 335 | __IO uint16_t Data1; |
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| 336 | __IO uint16_t WRP0; |
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| 337 | __IO uint16_t WRP1; |
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| 338 | __IO uint16_t WRP2; |
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| 339 | __IO uint16_t WRP3; |
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| 340 | } OB_TypeDef; |
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| 341 | |||
| 342 | /** |
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| 343 | * @brief General Purpose I/O |
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| 344 | */ |
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| 345 | |||
| 346 | typedef struct |
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| 347 | { |
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| 348 | __IO uint32_t CRL; |
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| 349 | __IO uint32_t CRH; |
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| 350 | __IO uint32_t IDR; |
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| 351 | __IO uint32_t ODR; |
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| 352 | __IO uint32_t BSRR; |
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| 353 | __IO uint32_t BRR; |
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| 354 | __IO uint32_t LCKR; |
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| 355 | } GPIO_TypeDef; |
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| 356 | |||
| 357 | /** |
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| 358 | * @brief Alternate Function I/O |
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| 359 | */ |
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| 360 | |||
| 361 | typedef struct |
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| 362 | { |
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| 363 | __IO uint32_t EVCR; |
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| 364 | __IO uint32_t MAPR; |
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| 365 | __IO uint32_t EXTICR[4]; |
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| 366 | uint32_t RESERVED0; |
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| 367 | __IO uint32_t MAPR2; |
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| 368 | } AFIO_TypeDef; |
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| 369 | /** |
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| 370 | * @brief Inter Integrated Circuit Interface |
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| 371 | */ |
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| 372 | |||
| 373 | typedef struct |
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| 374 | { |
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| 375 | __IO uint32_t CR1; |
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| 376 | __IO uint32_t CR2; |
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| 377 | __IO uint32_t OAR1; |
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| 378 | __IO uint32_t OAR2; |
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| 379 | __IO uint32_t DR; |
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| 380 | __IO uint32_t SR1; |
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| 381 | __IO uint32_t SR2; |
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| 382 | __IO uint32_t CCR; |
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| 383 | __IO uint32_t TRISE; |
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| 384 | } I2C_TypeDef; |
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| 385 | |||
| 386 | /** |
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| 387 | * @brief Independent WATCHDOG |
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| 388 | */ |
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| 389 | |||
| 390 | typedef struct |
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| 391 | { |
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| 392 | __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ |
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| 393 | __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ |
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| 394 | __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ |
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| 395 | __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ |
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| 396 | } IWDG_TypeDef; |
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| 397 | |||
| 398 | /** |
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| 399 | * @brief Power Control |
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| 400 | */ |
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| 401 | |||
| 402 | typedef struct |
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| 403 | { |
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| 404 | __IO uint32_t CR; |
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| 405 | __IO uint32_t CSR; |
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| 406 | } PWR_TypeDef; |
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| 407 | |||
| 408 | /** |
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| 409 | * @brief Reset and Clock Control |
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| 410 | */ |
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| 411 | |||
| 412 | typedef struct |
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| 413 | { |
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| 414 | __IO uint32_t CR; |
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| 415 | __IO uint32_t CFGR; |
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| 416 | __IO uint32_t CIR; |
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| 417 | __IO uint32_t APB2RSTR; |
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| 418 | __IO uint32_t APB1RSTR; |
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| 419 | __IO uint32_t AHBENR; |
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| 420 | __IO uint32_t APB2ENR; |
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| 421 | __IO uint32_t APB1ENR; |
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| 422 | __IO uint32_t BDCR; |
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| 423 | __IO uint32_t CSR; |
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| 424 | |||
| 425 | |||
| 426 | uint32_t RESERVED0; |
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| 427 | __IO uint32_t CFGR2; |
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| 428 | } RCC_TypeDef; |
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| 429 | |||
| 430 | /** |
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| 431 | * @brief Real-Time Clock |
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| 432 | */ |
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| 433 | |||
| 434 | typedef struct |
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| 435 | { |
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| 436 | __IO uint32_t CRH; |
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| 437 | __IO uint32_t CRL; |
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| 438 | __IO uint32_t PRLH; |
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| 439 | __IO uint32_t PRLL; |
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| 440 | __IO uint32_t DIVH; |
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| 441 | __IO uint32_t DIVL; |
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| 442 | __IO uint32_t CNTH; |
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| 443 | __IO uint32_t CNTL; |
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| 444 | __IO uint32_t ALRH; |
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| 445 | __IO uint32_t ALRL; |
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| 446 | } RTC_TypeDef; |
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| 447 | |||
| 448 | /** |
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| 449 | * @brief SD host Interface |
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| 450 | */ |
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| 451 | |||
| 452 | typedef struct |
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| 453 | { |
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| 454 | __IO uint32_t POWER; |
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| 455 | __IO uint32_t CLKCR; |
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| 456 | __IO uint32_t ARG; |
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| 457 | __IO uint32_t CMD; |
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| 458 | __I uint32_t RESPCMD; |
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| 459 | __I uint32_t RESP1; |
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| 460 | __I uint32_t RESP2; |
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| 461 | __I uint32_t RESP3; |
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| 462 | __I uint32_t RESP4; |
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| 463 | __IO uint32_t DTIMER; |
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| 464 | __IO uint32_t DLEN; |
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| 465 | __IO uint32_t DCTRL; |
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| 466 | __I uint32_t DCOUNT; |
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| 467 | __I uint32_t STA; |
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| 468 | __IO uint32_t ICR; |
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| 469 | __IO uint32_t MASK; |
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| 470 | uint32_t RESERVED0[2]; |
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| 471 | __I uint32_t FIFOCNT; |
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| 472 | uint32_t RESERVED1[13]; |
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| 473 | __IO uint32_t FIFO; |
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| 474 | } SDIO_TypeDef; |
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| 475 | |||
| 476 | /** |
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| 477 | * @brief Serial Peripheral Interface |
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| 478 | */ |
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| 479 | |||
| 480 | typedef struct |
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| 481 | { |
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| 482 | __IO uint32_t CR1; |
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| 483 | __IO uint32_t CR2; |
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| 484 | __IO uint32_t SR; |
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| 485 | __IO uint32_t DR; |
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| 486 | __IO uint32_t CRCPR; |
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| 487 | __IO uint32_t RXCRCR; |
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| 488 | __IO uint32_t TXCRCR; |
||
| 489 | } SPI_TypeDef; |
||
| 490 | |||
| 491 | /** |
||
| 492 | * @brief TIM Timers |
||
| 493 | */ |
||
| 494 | typedef struct |
||
| 495 | { |
||
| 496 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
||
| 497 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
||
| 498 | __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
||
| 499 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
||
| 500 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
||
| 501 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
||
| 502 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
||
| 503 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
||
| 504 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
||
| 505 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
||
| 506 | __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
||
| 507 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
||
| 508 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
||
| 509 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
||
| 510 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
||
| 511 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
||
| 512 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
||
| 513 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
||
| 514 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
||
| 515 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ |
||
| 516 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
||
| 517 | }TIM_TypeDef; |
||
| 518 | |||
| 519 | |||
| 520 | /** |
||
| 521 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
||
| 522 | */ |
||
| 523 | |||
| 524 | typedef struct |
||
| 525 | { |
||
| 526 | __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
||
| 527 | __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
||
| 528 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
||
| 529 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
||
| 530 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
||
| 531 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
||
| 532 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
||
| 533 | } USART_TypeDef; |
||
| 534 | |||
| 535 | |||
| 536 | |||
| 537 | /** |
||
| 538 | * @brief Window WATCHDOG |
||
| 539 | */ |
||
| 540 | |||
| 541 | typedef struct |
||
| 542 | { |
||
| 543 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
||
| 544 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
||
| 545 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
||
| 546 | } WWDG_TypeDef; |
||
| 547 | |||
| 548 | /** |
||
| 549 | * @} |
||
| 550 | */ |
||
| 551 | |||
| 552 | /** @addtogroup Peripheral_memory_map |
||
| 553 | * @{ |
||
| 554 | */ |
||
| 555 | |||
| 556 | |||
| 557 | #define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ |
||
| 558 | #define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ |
||
| 559 | #define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ |
||
| 560 | #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ |
||
| 561 | |||
| 562 | #define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ |
||
| 563 | #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ |
||
| 564 | |||
| 565 | |||
| 566 | /*!< Peripheral memory map */ |
||
| 567 | #define APB1PERIPH_BASE PERIPH_BASE |
||
| 568 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) |
||
| 569 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) |
||
| 570 | |||
| 571 | #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) |
||
| 572 | #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) |
||
| 573 | #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) |
||
| 574 | #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) |
||
| 575 | #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) |
||
| 576 | #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) |
||
| 577 | #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) |
||
| 578 | #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) |
||
| 579 | #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) |
||
| 580 | #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) |
||
| 581 | #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) |
||
| 582 | #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) |
||
| 583 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
||
| 584 | #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U) |
||
| 585 | #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) |
||
| 586 | #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U) |
||
| 587 | #define CEC_BASE (APB1PERIPH_BASE + 0x00007800U) |
||
| 588 | #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U) |
||
| 589 | #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) |
||
| 590 | #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) |
||
| 591 | #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) |
||
| 592 | #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) |
||
| 593 | #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) |
||
| 594 | #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U) |
||
| 595 | #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) |
||
| 596 | #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) |
||
| 597 | #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) |
||
| 598 | #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) |
||
| 599 | #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000U) |
||
| 600 | #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400U) |
||
| 601 | #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800U) |
||
| 602 | |||
| 603 | #define SDIO_BASE (PERIPH_BASE + 0x00018000U) |
||
| 604 | |||
| 605 | #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) |
||
| 606 | #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) |
||
| 607 | #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) |
||
| 608 | #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) |
||
| 609 | #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) |
||
| 610 | #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) |
||
| 611 | #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) |
||
| 612 | #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) |
||
| 613 | #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) |
||
| 614 | #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) |
||
| 615 | |||
| 616 | #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ |
||
| 617 | #define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ |
||
| 618 | #define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ |
||
| 619 | #define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ |
||
| 620 | |||
| 621 | |||
| 622 | |||
| 623 | #define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ |
||
| 624 | |||
| 625 | |||
| 626 | |||
| 627 | /** |
||
| 628 | * @} |
||
| 629 | */ |
||
| 630 | |||
| 631 | /** @addtogroup Peripheral_declaration |
||
| 632 | * @{ |
||
| 633 | */ |
||
| 634 | |||
| 635 | #define TIM2 ((TIM_TypeDef *)TIM2_BASE) |
||
| 636 | #define TIM3 ((TIM_TypeDef *)TIM3_BASE) |
||
| 637 | #define TIM4 ((TIM_TypeDef *)TIM4_BASE) |
||
| 638 | #define TIM6 ((TIM_TypeDef *)TIM6_BASE) |
||
| 639 | #define TIM7 ((TIM_TypeDef *)TIM7_BASE) |
||
| 640 | #define RTC ((RTC_TypeDef *)RTC_BASE) |
||
| 641 | #define WWDG ((WWDG_TypeDef *)WWDG_BASE) |
||
| 642 | #define IWDG ((IWDG_TypeDef *)IWDG_BASE) |
||
| 643 | #define SPI2 ((SPI_TypeDef *)SPI2_BASE) |
||
| 644 | #define USART2 ((USART_TypeDef *)USART2_BASE) |
||
| 645 | #define USART3 ((USART_TypeDef *)USART3_BASE) |
||
| 646 | #define I2C1 ((I2C_TypeDef *)I2C1_BASE) |
||
| 647 | #define I2C2 ((I2C_TypeDef *)I2C2_BASE) |
||
| 648 | #define BKP ((BKP_TypeDef *)BKP_BASE) |
||
| 649 | #define PWR ((PWR_TypeDef *)PWR_BASE) |
||
| 650 | #define DAC1 ((DAC_TypeDef *)DAC_BASE) |
||
| 651 | #define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */ |
||
| 652 | #define CEC ((CEC_TypeDef *)CEC_BASE) |
||
| 653 | #define AFIO ((AFIO_TypeDef *)AFIO_BASE) |
||
| 654 | #define EXTI ((EXTI_TypeDef *)EXTI_BASE) |
||
| 655 | #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) |
||
| 656 | #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) |
||
| 657 | #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) |
||
| 658 | #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) |
||
| 659 | #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) |
||
| 660 | #define ADC1 ((ADC_TypeDef *)ADC1_BASE) |
||
| 661 | #define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) |
||
| 662 | #define TIM1 ((TIM_TypeDef *)TIM1_BASE) |
||
| 663 | #define SPI1 ((SPI_TypeDef *)SPI1_BASE) |
||
| 664 | #define USART1 ((USART_TypeDef *)USART1_BASE) |
||
| 665 | #define TIM15 ((TIM_TypeDef *)TIM15_BASE) |
||
| 666 | #define TIM16 ((TIM_TypeDef *)TIM16_BASE) |
||
| 667 | #define TIM17 ((TIM_TypeDef *)TIM17_BASE) |
||
| 668 | #define SDIO ((SDIO_TypeDef *)SDIO_BASE) |
||
| 669 | #define DMA1 ((DMA_TypeDef *)DMA1_BASE) |
||
| 670 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) |
||
| 671 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) |
||
| 672 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) |
||
| 673 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) |
||
| 674 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) |
||
| 675 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) |
||
| 676 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) |
||
| 677 | #define RCC ((RCC_TypeDef *)RCC_BASE) |
||
| 678 | #define CRC ((CRC_TypeDef *)CRC_BASE) |
||
| 679 | #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) |
||
| 680 | #define OB ((OB_TypeDef *)OB_BASE) |
||
| 681 | #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) |
||
| 682 | |||
| 683 | |||
| 684 | /** |
||
| 685 | * @} |
||
| 686 | */ |
||
| 687 | |||
| 688 | /** @addtogroup Exported_constants |
||
| 689 | * @{ |
||
| 690 | */ |
||
| 691 | |||
| 692 | /** @addtogroup Peripheral_Registers_Bits_Definition |
||
| 693 | * @{ |
||
| 694 | */ |
||
| 695 | |||
| 696 | /******************************************************************************/ |
||
| 697 | /* Peripheral Registers_Bits_Definition */ |
||
| 698 | /******************************************************************************/ |
||
| 699 | |||
| 700 | /******************************************************************************/ |
||
| 701 | /* */ |
||
| 702 | /* CRC calculation unit (CRC) */ |
||
| 703 | /* */ |
||
| 704 | /******************************************************************************/ |
||
| 705 | |||
| 706 | /******************* Bit definition for CRC_DR register *********************/ |
||
| 707 | #define CRC_DR_DR_Pos (0U) |
||
| 708 | #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
||
| 709 | #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
||
| 710 | |||
| 711 | /******************* Bit definition for CRC_IDR register ********************/ |
||
| 712 | #define CRC_IDR_IDR_Pos (0U) |
||
| 713 | #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ |
||
| 714 | #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ |
||
| 715 | |||
| 716 | /******************** Bit definition for CRC_CR register ********************/ |
||
| 717 | #define CRC_CR_RESET_Pos (0U) |
||
| 718 | #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
||
| 719 | #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ |
||
| 720 | |||
| 721 | /******************************************************************************/ |
||
| 722 | /* */ |
||
| 723 | /* Power Control */ |
||
| 724 | /* */ |
||
| 725 | /******************************************************************************/ |
||
| 726 | |||
| 727 | /******************** Bit definition for PWR_CR register ********************/ |
||
| 728 | #define PWR_CR_LPDS_Pos (0U) |
||
| 729 | #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ |
||
| 730 | #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ |
||
| 731 | #define PWR_CR_PDDS_Pos (1U) |
||
| 732 | #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ |
||
| 733 | #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ |
||
| 734 | #define PWR_CR_CWUF_Pos (2U) |
||
| 735 | #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ |
||
| 736 | #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ |
||
| 737 | #define PWR_CR_CSBF_Pos (3U) |
||
| 738 | #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ |
||
| 739 | #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ |
||
| 740 | #define PWR_CR_PVDE_Pos (4U) |
||
| 741 | #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ |
||
| 742 | #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ |
||
| 743 | |||
| 744 | #define PWR_CR_PLS_Pos (5U) |
||
| 745 | #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ |
||
| 746 | #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ |
||
| 747 | #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ |
||
| 748 | #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ |
||
| 749 | #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ |
||
| 750 | |||
| 751 | /*!< PVD level configuration */ |
||
| 752 | #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ |
||
| 753 | #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ |
||
| 754 | #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ |
||
| 755 | #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ |
||
| 756 | #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ |
||
| 757 | #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ |
||
| 758 | #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ |
||
| 759 | #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ |
||
| 760 | |||
| 761 | /* Legacy defines */ |
||
| 762 | #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 |
||
| 763 | #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 |
||
| 764 | #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 |
||
| 765 | #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 |
||
| 766 | #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 |
||
| 767 | #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 |
||
| 768 | #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 |
||
| 769 | #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 |
||
| 770 | |||
| 771 | #define PWR_CR_DBP_Pos (8U) |
||
| 772 | #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ |
||
| 773 | #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ |
||
| 774 | |||
| 775 | |||
| 776 | /******************* Bit definition for PWR_CSR register ********************/ |
||
| 777 | #define PWR_CSR_WUF_Pos (0U) |
||
| 778 | #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ |
||
| 779 | #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ |
||
| 780 | #define PWR_CSR_SBF_Pos (1U) |
||
| 781 | #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ |
||
| 782 | #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ |
||
| 783 | #define PWR_CSR_PVDO_Pos (2U) |
||
| 784 | #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ |
||
| 785 | #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ |
||
| 786 | #define PWR_CSR_EWUP_Pos (8U) |
||
| 787 | #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ |
||
| 788 | #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ |
||
| 789 | |||
| 790 | /******************************************************************************/ |
||
| 791 | /* */ |
||
| 792 | /* Backup registers */ |
||
| 793 | /* */ |
||
| 794 | /******************************************************************************/ |
||
| 795 | |||
| 796 | /******************* Bit definition for BKP_DR1 register ********************/ |
||
| 797 | #define BKP_DR1_D_Pos (0U) |
||
| 798 | #define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ |
||
| 799 | #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ |
||
| 800 | |||
| 801 | /******************* Bit definition for BKP_DR2 register ********************/ |
||
| 802 | #define BKP_DR2_D_Pos (0U) |
||
| 803 | #define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ |
||
| 804 | #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ |
||
| 805 | |||
| 806 | /******************* Bit definition for BKP_DR3 register ********************/ |
||
| 807 | #define BKP_DR3_D_Pos (0U) |
||
| 808 | #define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ |
||
| 809 | #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ |
||
| 810 | |||
| 811 | /******************* Bit definition for BKP_DR4 register ********************/ |
||
| 812 | #define BKP_DR4_D_Pos (0U) |
||
| 813 | #define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ |
||
| 814 | #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ |
||
| 815 | |||
| 816 | /******************* Bit definition for BKP_DR5 register ********************/ |
||
| 817 | #define BKP_DR5_D_Pos (0U) |
||
| 818 | #define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ |
||
| 819 | #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ |
||
| 820 | |||
| 821 | /******************* Bit definition for BKP_DR6 register ********************/ |
||
| 822 | #define BKP_DR6_D_Pos (0U) |
||
| 823 | #define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ |
||
| 824 | #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ |
||
| 825 | |||
| 826 | /******************* Bit definition for BKP_DR7 register ********************/ |
||
| 827 | #define BKP_DR7_D_Pos (0U) |
||
| 828 | #define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ |
||
| 829 | #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ |
||
| 830 | |||
| 831 | /******************* Bit definition for BKP_DR8 register ********************/ |
||
| 832 | #define BKP_DR8_D_Pos (0U) |
||
| 833 | #define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ |
||
| 834 | #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ |
||
| 835 | |||
| 836 | /******************* Bit definition for BKP_DR9 register ********************/ |
||
| 837 | #define BKP_DR9_D_Pos (0U) |
||
| 838 | #define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ |
||
| 839 | #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ |
||
| 840 | |||
| 841 | /******************* Bit definition for BKP_DR10 register *******************/ |
||
| 842 | #define BKP_DR10_D_Pos (0U) |
||
| 843 | #define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ |
||
| 844 | #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ |
||
| 845 | |||
| 846 | #define RTC_BKP_NUMBER 10 |
||
| 847 | |||
| 848 | /****************** Bit definition for BKP_RTCCR register *******************/ |
||
| 849 | #define BKP_RTCCR_CAL_Pos (0U) |
||
| 850 | #define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ |
||
| 851 | #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ |
||
| 852 | #define BKP_RTCCR_CCO_Pos (7U) |
||
| 853 | #define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ |
||
| 854 | #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ |
||
| 855 | #define BKP_RTCCR_ASOE_Pos (8U) |
||
| 856 | #define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ |
||
| 857 | #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ |
||
| 858 | #define BKP_RTCCR_ASOS_Pos (9U) |
||
| 859 | #define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ |
||
| 860 | #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ |
||
| 861 | |||
| 862 | /******************** Bit definition for BKP_CR register ********************/ |
||
| 863 | #define BKP_CR_TPE_Pos (0U) |
||
| 864 | #define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */ |
||
| 865 | #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ |
||
| 866 | #define BKP_CR_TPAL_Pos (1U) |
||
| 867 | #define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ |
||
| 868 | #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ |
||
| 869 | |||
| 870 | /******************* Bit definition for BKP_CSR register ********************/ |
||
| 871 | #define BKP_CSR_CTE_Pos (0U) |
||
| 872 | #define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ |
||
| 873 | #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ |
||
| 874 | #define BKP_CSR_CTI_Pos (1U) |
||
| 875 | #define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ |
||
| 876 | #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ |
||
| 877 | #define BKP_CSR_TPIE_Pos (2U) |
||
| 878 | #define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ |
||
| 879 | #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ |
||
| 880 | #define BKP_CSR_TEF_Pos (8U) |
||
| 881 | #define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ |
||
| 882 | #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ |
||
| 883 | #define BKP_CSR_TIF_Pos (9U) |
||
| 884 | #define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ |
||
| 885 | #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ |
||
| 886 | |||
| 887 | /******************************************************************************/ |
||
| 888 | /* */ |
||
| 889 | /* Reset and Clock Control */ |
||
| 890 | /* */ |
||
| 891 | /******************************************************************************/ |
||
| 892 | |||
| 893 | /******************** Bit definition for RCC_CR register ********************/ |
||
| 894 | #define RCC_CR_HSION_Pos (0U) |
||
| 895 | #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ |
||
| 896 | #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ |
||
| 897 | #define RCC_CR_HSIRDY_Pos (1U) |
||
| 898 | #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ |
||
| 899 | #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ |
||
| 900 | #define RCC_CR_HSITRIM_Pos (3U) |
||
| 901 | #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ |
||
| 902 | #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ |
||
| 903 | #define RCC_CR_HSICAL_Pos (8U) |
||
| 904 | #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ |
||
| 905 | #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ |
||
| 906 | #define RCC_CR_HSEON_Pos (16U) |
||
| 907 | #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ |
||
| 908 | #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ |
||
| 909 | #define RCC_CR_HSERDY_Pos (17U) |
||
| 910 | #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ |
||
| 911 | #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ |
||
| 912 | #define RCC_CR_HSEBYP_Pos (18U) |
||
| 913 | #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ |
||
| 914 | #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ |
||
| 915 | #define RCC_CR_CSSON_Pos (19U) |
||
| 916 | #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ |
||
| 917 | #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ |
||
| 918 | #define RCC_CR_PLLON_Pos (24U) |
||
| 919 | #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ |
||
| 920 | #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ |
||
| 921 | #define RCC_CR_PLLRDY_Pos (25U) |
||
| 922 | #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ |
||
| 923 | #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ |
||
| 924 | |||
| 925 | |||
| 926 | /******************* Bit definition for RCC_CFGR register *******************/ |
||
| 927 | /*!< SW configuration */ |
||
| 928 | #define RCC_CFGR_SW_Pos (0U) |
||
| 929 | #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ |
||
| 930 | #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ |
||
| 931 | #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ |
||
| 932 | #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ |
||
| 933 | |||
| 934 | #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ |
||
| 935 | #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ |
||
| 936 | #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ |
||
| 937 | |||
| 938 | /*!< SWS configuration */ |
||
| 939 | #define RCC_CFGR_SWS_Pos (2U) |
||
| 940 | #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ |
||
| 941 | #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ |
||
| 942 | #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ |
||
| 943 | #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ |
||
| 944 | |||
| 945 | #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ |
||
| 946 | #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ |
||
| 947 | #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ |
||
| 948 | |||
| 949 | /*!< HPRE configuration */ |
||
| 950 | #define RCC_CFGR_HPRE_Pos (4U) |
||
| 951 | #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ |
||
| 952 | #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ |
||
| 953 | #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ |
||
| 954 | #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ |
||
| 955 | #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ |
||
| 956 | #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ |
||
| 957 | |||
| 958 | #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ |
||
| 959 | #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ |
||
| 960 | #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ |
||
| 961 | #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ |
||
| 962 | #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ |
||
| 963 | #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ |
||
| 964 | #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ |
||
| 965 | #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ |
||
| 966 | #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ |
||
| 967 | |||
| 968 | /*!< PPRE1 configuration */ |
||
| 969 | #define RCC_CFGR_PPRE1_Pos (8U) |
||
| 970 | #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ |
||
| 971 | #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ |
||
| 972 | #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ |
||
| 973 | #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ |
||
| 974 | #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ |
||
| 975 | |||
| 976 | #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ |
||
| 977 | #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ |
||
| 978 | #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ |
||
| 979 | #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ |
||
| 980 | #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ |
||
| 981 | |||
| 982 | /*!< PPRE2 configuration */ |
||
| 983 | #define RCC_CFGR_PPRE2_Pos (11U) |
||
| 984 | #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ |
||
| 985 | #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ |
||
| 986 | #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ |
||
| 987 | #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ |
||
| 988 | #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ |
||
| 989 | |||
| 990 | #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ |
||
| 991 | #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ |
||
| 992 | #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ |
||
| 993 | #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ |
||
| 994 | #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ |
||
| 995 | |||
| 996 | /*!< ADCPPRE configuration */ |
||
| 997 | #define RCC_CFGR_ADCPRE_Pos (14U) |
||
| 998 | #define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ |
||
| 999 | #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
||
| 1000 | #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ |
||
| 1001 | #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ |
||
| 1002 | |||
| 1003 | #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ |
||
| 1004 | #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ |
||
| 1005 | #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ |
||
| 1006 | #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ |
||
| 1007 | |||
| 1008 | #define RCC_CFGR_PLLSRC_Pos (16U) |
||
| 1009 | #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ |
||
| 1010 | #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ |
||
| 1011 | |||
| 1012 | #define RCC_CFGR_PLLXTPRE_Pos (17U) |
||
| 1013 | #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ |
||
| 1014 | #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ |
||
| 1015 | |||
| 1016 | /*!< PLLMUL configuration */ |
||
| 1017 | #define RCC_CFGR_PLLMULL_Pos (18U) |
||
| 1018 | #define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ |
||
| 1019 | #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
||
| 1020 | #define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ |
||
| 1021 | #define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ |
||
| 1022 | #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ |
||
| 1023 | #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ |
||
| 1024 | |||
| 1025 | #define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */ |
||
| 1026 | #define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */ |
||
| 1027 | |||
| 1028 | #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ |
||
| 1029 | #define RCC_CFGR_PLLMULL3_Pos (18U) |
||
| 1030 | #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ |
||
| 1031 | #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ |
||
| 1032 | #define RCC_CFGR_PLLMULL4_Pos (19U) |
||
| 1033 | #define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ |
||
| 1034 | #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ |
||
| 1035 | #define RCC_CFGR_PLLMULL5_Pos (18U) |
||
| 1036 | #define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ |
||
| 1037 | #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ |
||
| 1038 | #define RCC_CFGR_PLLMULL6_Pos (20U) |
||
| 1039 | #define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ |
||
| 1040 | #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ |
||
| 1041 | #define RCC_CFGR_PLLMULL7_Pos (18U) |
||
| 1042 | #define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ |
||
| 1043 | #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ |
||
| 1044 | #define RCC_CFGR_PLLMULL8_Pos (19U) |
||
| 1045 | #define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ |
||
| 1046 | #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ |
||
| 1047 | #define RCC_CFGR_PLLMULL9_Pos (18U) |
||
| 1048 | #define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ |
||
| 1049 | #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ |
||
| 1050 | #define RCC_CFGR_PLLMULL10_Pos (21U) |
||
| 1051 | #define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ |
||
| 1052 | #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ |
||
| 1053 | #define RCC_CFGR_PLLMULL11_Pos (18U) |
||
| 1054 | #define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ |
||
| 1055 | #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ |
||
| 1056 | #define RCC_CFGR_PLLMULL12_Pos (19U) |
||
| 1057 | #define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ |
||
| 1058 | #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ |
||
| 1059 | #define RCC_CFGR_PLLMULL13_Pos (18U) |
||
| 1060 | #define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ |
||
| 1061 | #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ |
||
| 1062 | #define RCC_CFGR_PLLMULL14_Pos (20U) |
||
| 1063 | #define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ |
||
| 1064 | #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ |
||
| 1065 | #define RCC_CFGR_PLLMULL15_Pos (18U) |
||
| 1066 | #define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ |
||
| 1067 | #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ |
||
| 1068 | #define RCC_CFGR_PLLMULL16_Pos (19U) |
||
| 1069 | #define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ |
||
| 1070 | #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ |
||
| 1071 | |||
| 1072 | /*!< MCO configuration */ |
||
| 1073 | #define RCC_CFGR_MCO_Pos (24U) |
||
| 1074 | #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ |
||
| 1075 | #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
||
| 1076 | #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ |
||
| 1077 | #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ |
||
| 1078 | #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ |
||
| 1079 | |||
| 1080 | #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ |
||
| 1081 | #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ |
||
| 1082 | #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ |
||
| 1083 | #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ |
||
| 1084 | #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ |
||
| 1085 | |||
| 1086 | /* Reference defines */ |
||
| 1087 | #define RCC_CFGR_MCOSEL RCC_CFGR_MCO |
||
| 1088 | #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 |
||
| 1089 | #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 |
||
| 1090 | #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 |
||
| 1091 | #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK |
||
| 1092 | #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK |
||
| 1093 | #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI |
||
| 1094 | #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE |
||
| 1095 | #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 |
||
| 1096 | |||
| 1097 | /*!<****************** Bit definition for RCC_CIR register ********************/ |
||
| 1098 | #define RCC_CIR_LSIRDYF_Pos (0U) |
||
| 1099 | #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ |
||
| 1100 | #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ |
||
| 1101 | #define RCC_CIR_LSERDYF_Pos (1U) |
||
| 1102 | #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ |
||
| 1103 | #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ |
||
| 1104 | #define RCC_CIR_HSIRDYF_Pos (2U) |
||
| 1105 | #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ |
||
| 1106 | #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ |
||
| 1107 | #define RCC_CIR_HSERDYF_Pos (3U) |
||
| 1108 | #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ |
||
| 1109 | #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ |
||
| 1110 | #define RCC_CIR_PLLRDYF_Pos (4U) |
||
| 1111 | #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ |
||
| 1112 | #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ |
||
| 1113 | #define RCC_CIR_CSSF_Pos (7U) |
||
| 1114 | #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ |
||
| 1115 | #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ |
||
| 1116 | #define RCC_CIR_LSIRDYIE_Pos (8U) |
||
| 1117 | #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ |
||
| 1118 | #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ |
||
| 1119 | #define RCC_CIR_LSERDYIE_Pos (9U) |
||
| 1120 | #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ |
||
| 1121 | #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ |
||
| 1122 | #define RCC_CIR_HSIRDYIE_Pos (10U) |
||
| 1123 | #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ |
||
| 1124 | #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ |
||
| 1125 | #define RCC_CIR_HSERDYIE_Pos (11U) |
||
| 1126 | #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ |
||
| 1127 | #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ |
||
| 1128 | #define RCC_CIR_PLLRDYIE_Pos (12U) |
||
| 1129 | #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ |
||
| 1130 | #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ |
||
| 1131 | #define RCC_CIR_LSIRDYC_Pos (16U) |
||
| 1132 | #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ |
||
| 1133 | #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ |
||
| 1134 | #define RCC_CIR_LSERDYC_Pos (17U) |
||
| 1135 | #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ |
||
| 1136 | #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ |
||
| 1137 | #define RCC_CIR_HSIRDYC_Pos (18U) |
||
| 1138 | #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ |
||
| 1139 | #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ |
||
| 1140 | #define RCC_CIR_HSERDYC_Pos (19U) |
||
| 1141 | #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ |
||
| 1142 | #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ |
||
| 1143 | #define RCC_CIR_PLLRDYC_Pos (20U) |
||
| 1144 | #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ |
||
| 1145 | #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ |
||
| 1146 | #define RCC_CIR_CSSC_Pos (23U) |
||
| 1147 | #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ |
||
| 1148 | #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ |
||
| 1149 | |||
| 1150 | |||
| 1151 | /***************** Bit definition for RCC_APB2RSTR register *****************/ |
||
| 1152 | #define RCC_APB2RSTR_AFIORST_Pos (0U) |
||
| 1153 | #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ |
||
| 1154 | #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ |
||
| 1155 | #define RCC_APB2RSTR_IOPARST_Pos (2U) |
||
| 1156 | #define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ |
||
| 1157 | #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ |
||
| 1158 | #define RCC_APB2RSTR_IOPBRST_Pos (3U) |
||
| 1159 | #define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ |
||
| 1160 | #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ |
||
| 1161 | #define RCC_APB2RSTR_IOPCRST_Pos (4U) |
||
| 1162 | #define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ |
||
| 1163 | #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ |
||
| 1164 | #define RCC_APB2RSTR_IOPDRST_Pos (5U) |
||
| 1165 | #define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ |
||
| 1166 | #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ |
||
| 1167 | #define RCC_APB2RSTR_ADC1RST_Pos (9U) |
||
| 1168 | #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ |
||
| 1169 | #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ |
||
| 1170 | |||
| 1171 | |||
| 1172 | #define RCC_APB2RSTR_TIM1RST_Pos (11U) |
||
| 1173 | #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ |
||
| 1174 | #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ |
||
| 1175 | #define RCC_APB2RSTR_SPI1RST_Pos (12U) |
||
| 1176 | #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ |
||
| 1177 | #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ |
||
| 1178 | #define RCC_APB2RSTR_USART1RST_Pos (14U) |
||
| 1179 | #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ |
||
| 1180 | #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ |
||
| 1181 | |||
| 1182 | #define RCC_APB2RSTR_TIM15RST_Pos (16U) |
||
| 1183 | #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ |
||
| 1184 | #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 Timer reset */ |
||
| 1185 | #define RCC_APB2RSTR_TIM16RST_Pos (17U) |
||
| 1186 | #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ |
||
| 1187 | #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 Timer reset */ |
||
| 1188 | #define RCC_APB2RSTR_TIM17RST_Pos (18U) |
||
| 1189 | #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ |
||
| 1190 | #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 Timer reset */ |
||
| 1191 | |||
| 1192 | #define RCC_APB2RSTR_IOPERST_Pos (6U) |
||
| 1193 | #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ |
||
| 1194 | #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ |
||
| 1195 | |||
| 1196 | |||
| 1197 | |||
| 1198 | |||
| 1199 | /***************** Bit definition for RCC_APB1RSTR register *****************/ |
||
| 1200 | #define RCC_APB1RSTR_TIM2RST_Pos (0U) |
||
| 1201 | #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ |
||
| 1202 | #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ |
||
| 1203 | #define RCC_APB1RSTR_TIM3RST_Pos (1U) |
||
| 1204 | #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ |
||
| 1205 | #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ |
||
| 1206 | #define RCC_APB1RSTR_WWDGRST_Pos (11U) |
||
| 1207 | #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ |
||
| 1208 | #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ |
||
| 1209 | #define RCC_APB1RSTR_USART2RST_Pos (17U) |
||
| 1210 | #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ |
||
| 1211 | #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ |
||
| 1212 | #define RCC_APB1RSTR_I2C1RST_Pos (21U) |
||
| 1213 | #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ |
||
| 1214 | #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ |
||
| 1215 | |||
| 1216 | |||
| 1217 | #define RCC_APB1RSTR_BKPRST_Pos (27U) |
||
| 1218 | #define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ |
||
| 1219 | #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ |
||
| 1220 | #define RCC_APB1RSTR_PWRRST_Pos (28U) |
||
| 1221 | #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ |
||
| 1222 | #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ |
||
| 1223 | |||
| 1224 | #define RCC_APB1RSTR_TIM4RST_Pos (2U) |
||
| 1225 | #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ |
||
| 1226 | #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ |
||
| 1227 | #define RCC_APB1RSTR_SPI2RST_Pos (14U) |
||
| 1228 | #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ |
||
| 1229 | #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ |
||
| 1230 | #define RCC_APB1RSTR_USART3RST_Pos (18U) |
||
| 1231 | #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ |
||
| 1232 | #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ |
||
| 1233 | #define RCC_APB1RSTR_I2C2RST_Pos (22U) |
||
| 1234 | #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ |
||
| 1235 | #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ |
||
| 1236 | |||
| 1237 | |||
| 1238 | |||
| 1239 | #define RCC_APB1RSTR_TIM6RST_Pos (4U) |
||
| 1240 | #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ |
||
| 1241 | #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ |
||
| 1242 | #define RCC_APB1RSTR_TIM7RST_Pos (5U) |
||
| 1243 | #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ |
||
| 1244 | #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ |
||
| 1245 | #define RCC_APB1RSTR_CECRST_Pos (30U) |
||
| 1246 | #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ |
||
| 1247 | #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC interface reset */ |
||
| 1248 | |||
| 1249 | |||
| 1250 | |||
| 1251 | #define RCC_APB1RSTR_DACRST_Pos (29U) |
||
| 1252 | #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ |
||
| 1253 | #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ |
||
| 1254 | |||
| 1255 | /****************** Bit definition for RCC_AHBENR register ******************/ |
||
| 1256 | #define RCC_AHBENR_DMA1EN_Pos (0U) |
||
| 1257 | #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ |
||
| 1258 | #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ |
||
| 1259 | #define RCC_AHBENR_SRAMEN_Pos (2U) |
||
| 1260 | #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ |
||
| 1261 | #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ |
||
| 1262 | #define RCC_AHBENR_FLITFEN_Pos (4U) |
||
| 1263 | #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ |
||
| 1264 | #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ |
||
| 1265 | #define RCC_AHBENR_CRCEN_Pos (6U) |
||
| 1266 | #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ |
||
| 1267 | #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ |
||
| 1268 | |||
| 1269 | |||
| 1270 | |||
| 1271 | |||
| 1272 | /****************** Bit definition for RCC_APB2ENR register *****************/ |
||
| 1273 | #define RCC_APB2ENR_AFIOEN_Pos (0U) |
||
| 1274 | #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ |
||
| 1275 | #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ |
||
| 1276 | #define RCC_APB2ENR_IOPAEN_Pos (2U) |
||
| 1277 | #define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ |
||
| 1278 | #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ |
||
| 1279 | #define RCC_APB2ENR_IOPBEN_Pos (3U) |
||
| 1280 | #define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ |
||
| 1281 | #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ |
||
| 1282 | #define RCC_APB2ENR_IOPCEN_Pos (4U) |
||
| 1283 | #define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ |
||
| 1284 | #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ |
||
| 1285 | #define RCC_APB2ENR_IOPDEN_Pos (5U) |
||
| 1286 | #define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ |
||
| 1287 | #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ |
||
| 1288 | #define RCC_APB2ENR_ADC1EN_Pos (9U) |
||
| 1289 | #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ |
||
| 1290 | #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ |
||
| 1291 | |||
| 1292 | |||
| 1293 | #define RCC_APB2ENR_TIM1EN_Pos (11U) |
||
| 1294 | #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ |
||
| 1295 | #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ |
||
| 1296 | #define RCC_APB2ENR_SPI1EN_Pos (12U) |
||
| 1297 | #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ |
||
| 1298 | #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ |
||
| 1299 | #define RCC_APB2ENR_USART1EN_Pos (14U) |
||
| 1300 | #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ |
||
| 1301 | #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ |
||
| 1302 | |||
| 1303 | #define RCC_APB2ENR_TIM15EN_Pos (16U) |
||
| 1304 | #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ |
||
| 1305 | #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 Timer clock enable */ |
||
| 1306 | #define RCC_APB2ENR_TIM16EN_Pos (17U) |
||
| 1307 | #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ |
||
| 1308 | #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 Timer clock enable */ |
||
| 1309 | #define RCC_APB2ENR_TIM17EN_Pos (18U) |
||
| 1310 | #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ |
||
| 1311 | #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 Timer clock enable */ |
||
| 1312 | |||
| 1313 | #define RCC_APB2ENR_IOPEEN_Pos (6U) |
||
| 1314 | #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ |
||
| 1315 | #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ |
||
| 1316 | |||
| 1317 | |||
| 1318 | |||
| 1319 | |||
| 1320 | /***************** Bit definition for RCC_APB1ENR register ******************/ |
||
| 1321 | #define RCC_APB1ENR_TIM2EN_Pos (0U) |
||
| 1322 | #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ |
||
| 1323 | #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ |
||
| 1324 | #define RCC_APB1ENR_TIM3EN_Pos (1U) |
||
| 1325 | #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ |
||
| 1326 | #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ |
||
| 1327 | #define RCC_APB1ENR_WWDGEN_Pos (11U) |
||
| 1328 | #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ |
||
| 1329 | #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ |
||
| 1330 | #define RCC_APB1ENR_USART2EN_Pos (17U) |
||
| 1331 | #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ |
||
| 1332 | #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ |
||
| 1333 | #define RCC_APB1ENR_I2C1EN_Pos (21U) |
||
| 1334 | #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ |
||
| 1335 | #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ |
||
| 1336 | |||
| 1337 | |||
| 1338 | #define RCC_APB1ENR_BKPEN_Pos (27U) |
||
| 1339 | #define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ |
||
| 1340 | #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ |
||
| 1341 | #define RCC_APB1ENR_PWREN_Pos (28U) |
||
| 1342 | #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ |
||
| 1343 | #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ |
||
| 1344 | |||
| 1345 | #define RCC_APB1ENR_TIM4EN_Pos (2U) |
||
| 1346 | #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ |
||
| 1347 | #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ |
||
| 1348 | #define RCC_APB1ENR_SPI2EN_Pos (14U) |
||
| 1349 | #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ |
||
| 1350 | #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ |
||
| 1351 | #define RCC_APB1ENR_USART3EN_Pos (18U) |
||
| 1352 | #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ |
||
| 1353 | #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ |
||
| 1354 | #define RCC_APB1ENR_I2C2EN_Pos (22U) |
||
| 1355 | #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ |
||
| 1356 | #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ |
||
| 1357 | |||
| 1358 | |||
| 1359 | |||
| 1360 | #define RCC_APB1ENR_TIM6EN_Pos (4U) |
||
| 1361 | #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ |
||
| 1362 | #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ |
||
| 1363 | #define RCC_APB1ENR_TIM7EN_Pos (5U) |
||
| 1364 | #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ |
||
| 1365 | #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ |
||
| 1366 | #define RCC_APB1ENR_CECEN_Pos (30U) |
||
| 1367 | #define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */ |
||
| 1368 | #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC interface clock enable */ |
||
| 1369 | |||
| 1370 | |||
| 1371 | |||
| 1372 | #define RCC_APB1ENR_DACEN_Pos (29U) |
||
| 1373 | #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ |
||
| 1374 | #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ |
||
| 1375 | |||
| 1376 | /******************* Bit definition for RCC_BDCR register *******************/ |
||
| 1377 | #define RCC_BDCR_LSEON_Pos (0U) |
||
| 1378 | #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ |
||
| 1379 | #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ |
||
| 1380 | #define RCC_BDCR_LSERDY_Pos (1U) |
||
| 1381 | #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ |
||
| 1382 | #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ |
||
| 1383 | #define RCC_BDCR_LSEBYP_Pos (2U) |
||
| 1384 | #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ |
||
| 1385 | #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ |
||
| 1386 | |||
| 1387 | #define RCC_BDCR_RTCSEL_Pos (8U) |
||
| 1388 | #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ |
||
| 1389 | #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
||
| 1390 | #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ |
||
| 1391 | #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ |
||
| 1392 | |||
| 1393 | /*!< RTC congiguration */ |
||
| 1394 | #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ |
||
| 1395 | #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ |
||
| 1396 | #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ |
||
| 1397 | #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
||
| 1398 | |||
| 1399 | #define RCC_BDCR_RTCEN_Pos (15U) |
||
| 1400 | #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ |
||
| 1401 | #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ |
||
| 1402 | #define RCC_BDCR_BDRST_Pos (16U) |
||
| 1403 | #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ |
||
| 1404 | #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ |
||
| 1405 | |||
| 1406 | /******************* Bit definition for RCC_CSR register ********************/ |
||
| 1407 | #define RCC_CSR_LSION_Pos (0U) |
||
| 1408 | #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ |
||
| 1409 | #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ |
||
| 1410 | #define RCC_CSR_LSIRDY_Pos (1U) |
||
| 1411 | #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ |
||
| 1412 | #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ |
||
| 1413 | #define RCC_CSR_RMVF_Pos (24U) |
||
| 1414 | #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ |
||
| 1415 | #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ |
||
| 1416 | #define RCC_CSR_PINRSTF_Pos (26U) |
||
| 1417 | #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ |
||
| 1418 | #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ |
||
| 1419 | #define RCC_CSR_PORRSTF_Pos (27U) |
||
| 1420 | #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ |
||
| 1421 | #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ |
||
| 1422 | #define RCC_CSR_SFTRSTF_Pos (28U) |
||
| 1423 | #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ |
||
| 1424 | #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ |
||
| 1425 | #define RCC_CSR_IWDGRSTF_Pos (29U) |
||
| 1426 | #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ |
||
| 1427 | #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ |
||
| 1428 | #define RCC_CSR_WWDGRSTF_Pos (30U) |
||
| 1429 | #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ |
||
| 1430 | #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ |
||
| 1431 | #define RCC_CSR_LPWRRSTF_Pos (31U) |
||
| 1432 | #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ |
||
| 1433 | #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ |
||
| 1434 | |||
| 1435 | |||
| 1436 | /******************* Bit definition for RCC_CFGR2 register ******************/ |
||
| 1437 | /*!< PREDIV1 configuration */ |
||
| 1438 | #define RCC_CFGR2_PREDIV1_Pos (0U) |
||
| 1439 | #define RCC_CFGR2_PREDIV1_Msk (0xFU << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */ |
||
| 1440 | #define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */ |
||
| 1441 | #define RCC_CFGR2_PREDIV1_0 (0x1U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */ |
||
| 1442 | #define RCC_CFGR2_PREDIV1_1 (0x2U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */ |
||
| 1443 | #define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */ |
||
| 1444 | #define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */ |
||
| 1445 | |||
| 1446 | #define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */ |
||
| 1447 | #define RCC_CFGR2_PREDIV1_DIV2_Pos (0U) |
||
| 1448 | #define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */ |
||
| 1449 | #define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */ |
||
| 1450 | #define RCC_CFGR2_PREDIV1_DIV3_Pos (1U) |
||
| 1451 | #define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */ |
||
| 1452 | #define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */ |
||
| 1453 | #define RCC_CFGR2_PREDIV1_DIV4_Pos (0U) |
||
| 1454 | #define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */ |
||
| 1455 | #define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */ |
||
| 1456 | #define RCC_CFGR2_PREDIV1_DIV5_Pos (2U) |
||
| 1457 | #define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */ |
||
| 1458 | #define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */ |
||
| 1459 | #define RCC_CFGR2_PREDIV1_DIV6_Pos (0U) |
||
| 1460 | #define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */ |
||
| 1461 | #define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */ |
||
| 1462 | #define RCC_CFGR2_PREDIV1_DIV7_Pos (1U) |
||
| 1463 | #define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */ |
||
| 1464 | #define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */ |
||
| 1465 | #define RCC_CFGR2_PREDIV1_DIV8_Pos (0U) |
||
| 1466 | #define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */ |
||
| 1467 | #define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */ |
||
| 1468 | #define RCC_CFGR2_PREDIV1_DIV9_Pos (3U) |
||
| 1469 | #define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */ |
||
| 1470 | #define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */ |
||
| 1471 | #define RCC_CFGR2_PREDIV1_DIV10_Pos (0U) |
||
| 1472 | #define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */ |
||
| 1473 | #define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */ |
||
| 1474 | #define RCC_CFGR2_PREDIV1_DIV11_Pos (1U) |
||
| 1475 | #define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */ |
||
| 1476 | #define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */ |
||
| 1477 | #define RCC_CFGR2_PREDIV1_DIV12_Pos (0U) |
||
| 1478 | #define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */ |
||
| 1479 | #define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */ |
||
| 1480 | #define RCC_CFGR2_PREDIV1_DIV13_Pos (2U) |
||
| 1481 | #define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */ |
||
| 1482 | #define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */ |
||
| 1483 | #define RCC_CFGR2_PREDIV1_DIV14_Pos (0U) |
||
| 1484 | #define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */ |
||
| 1485 | #define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */ |
||
| 1486 | #define RCC_CFGR2_PREDIV1_DIV15_Pos (1U) |
||
| 1487 | #define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */ |
||
| 1488 | #define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */ |
||
| 1489 | #define RCC_CFGR2_PREDIV1_DIV16_Pos (0U) |
||
| 1490 | #define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */ |
||
| 1491 | #define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */ |
||
| 1492 | |||
| 1493 | /******************************************************************************/ |
||
| 1494 | /* */ |
||
| 1495 | /* General Purpose and Alternate Function I/O */ |
||
| 1496 | /* */ |
||
| 1497 | /******************************************************************************/ |
||
| 1498 | |||
| 1499 | /******************* Bit definition for GPIO_CRL register *******************/ |
||
| 1500 | #define GPIO_CRL_MODE_Pos (0U) |
||
| 1501 | #define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ |
||
| 1502 | #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ |
||
| 1503 | |||
| 1504 | #define GPIO_CRL_MODE0_Pos (0U) |
||
| 1505 | #define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ |
||
| 1506 | #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
||
| 1507 | #define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ |
||
| 1508 | #define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ |
||
| 1509 | |||
| 1510 | #define GPIO_CRL_MODE1_Pos (4U) |
||
| 1511 | #define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ |
||
| 1512 | #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
||
| 1513 | #define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ |
||
| 1514 | #define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ |
||
| 1515 | |||
| 1516 | #define GPIO_CRL_MODE2_Pos (8U) |
||
| 1517 | #define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ |
||
| 1518 | #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
||
| 1519 | #define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ |
||
| 1520 | #define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ |
||
| 1521 | |||
| 1522 | #define GPIO_CRL_MODE3_Pos (12U) |
||
| 1523 | #define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ |
||
| 1524 | #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
||
| 1525 | #define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ |
||
| 1526 | #define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ |
||
| 1527 | |||
| 1528 | #define GPIO_CRL_MODE4_Pos (16U) |
||
| 1529 | #define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ |
||
| 1530 | #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
||
| 1531 | #define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ |
||
| 1532 | #define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ |
||
| 1533 | |||
| 1534 | #define GPIO_CRL_MODE5_Pos (20U) |
||
| 1535 | #define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ |
||
| 1536 | #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
||
| 1537 | #define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ |
||
| 1538 | #define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ |
||
| 1539 | |||
| 1540 | #define GPIO_CRL_MODE6_Pos (24U) |
||
| 1541 | #define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ |
||
| 1542 | #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
||
| 1543 | #define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ |
||
| 1544 | #define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ |
||
| 1545 | |||
| 1546 | #define GPIO_CRL_MODE7_Pos (28U) |
||
| 1547 | #define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ |
||
| 1548 | #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
||
| 1549 | #define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ |
||
| 1550 | #define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ |
||
| 1551 | |||
| 1552 | #define GPIO_CRL_CNF_Pos (2U) |
||
| 1553 | #define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ |
||
| 1554 | #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ |
||
| 1555 | |||
| 1556 | #define GPIO_CRL_CNF0_Pos (2U) |
||
| 1557 | #define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ |
||
| 1558 | #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
||
| 1559 | #define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ |
||
| 1560 | #define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ |
||
| 1561 | |||
| 1562 | #define GPIO_CRL_CNF1_Pos (6U) |
||
| 1563 | #define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ |
||
| 1564 | #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
||
| 1565 | #define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ |
||
| 1566 | #define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ |
||
| 1567 | |||
| 1568 | #define GPIO_CRL_CNF2_Pos (10U) |
||
| 1569 | #define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ |
||
| 1570 | #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
||
| 1571 | #define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ |
||
| 1572 | #define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ |
||
| 1573 | |||
| 1574 | #define GPIO_CRL_CNF3_Pos (14U) |
||
| 1575 | #define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ |
||
| 1576 | #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
||
| 1577 | #define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ |
||
| 1578 | #define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ |
||
| 1579 | |||
| 1580 | #define GPIO_CRL_CNF4_Pos (18U) |
||
| 1581 | #define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ |
||
| 1582 | #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
||
| 1583 | #define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ |
||
| 1584 | #define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ |
||
| 1585 | |||
| 1586 | #define GPIO_CRL_CNF5_Pos (22U) |
||
| 1587 | #define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ |
||
| 1588 | #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
||
| 1589 | #define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ |
||
| 1590 | #define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ |
||
| 1591 | |||
| 1592 | #define GPIO_CRL_CNF6_Pos (26U) |
||
| 1593 | #define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ |
||
| 1594 | #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
||
| 1595 | #define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ |
||
| 1596 | #define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ |
||
| 1597 | |||
| 1598 | #define GPIO_CRL_CNF7_Pos (30U) |
||
| 1599 | #define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ |
||
| 1600 | #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
||
| 1601 | #define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ |
||
| 1602 | #define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ |
||
| 1603 | |||
| 1604 | /******************* Bit definition for GPIO_CRH register *******************/ |
||
| 1605 | #define GPIO_CRH_MODE_Pos (0U) |
||
| 1606 | #define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ |
||
| 1607 | #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ |
||
| 1608 | |||
| 1609 | #define GPIO_CRH_MODE8_Pos (0U) |
||
| 1610 | #define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ |
||
| 1611 | #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
||
| 1612 | #define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ |
||
| 1613 | #define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ |
||
| 1614 | |||
| 1615 | #define GPIO_CRH_MODE9_Pos (4U) |
||
| 1616 | #define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ |
||
| 1617 | #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
||
| 1618 | #define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ |
||
| 1619 | #define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ |
||
| 1620 | |||
| 1621 | #define GPIO_CRH_MODE10_Pos (8U) |
||
| 1622 | #define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ |
||
| 1623 | #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
||
| 1624 | #define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ |
||
| 1625 | #define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ |
||
| 1626 | |||
| 1627 | #define GPIO_CRH_MODE11_Pos (12U) |
||
| 1628 | #define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ |
||
| 1629 | #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
||
| 1630 | #define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ |
||
| 1631 | #define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ |
||
| 1632 | |||
| 1633 | #define GPIO_CRH_MODE12_Pos (16U) |
||
| 1634 | #define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ |
||
| 1635 | #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
||
| 1636 | #define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ |
||
| 1637 | #define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ |
||
| 1638 | |||
| 1639 | #define GPIO_CRH_MODE13_Pos (20U) |
||
| 1640 | #define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ |
||
| 1641 | #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
||
| 1642 | #define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ |
||
| 1643 | #define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ |
||
| 1644 | |||
| 1645 | #define GPIO_CRH_MODE14_Pos (24U) |
||
| 1646 | #define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ |
||
| 1647 | #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
||
| 1648 | #define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ |
||
| 1649 | #define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ |
||
| 1650 | |||
| 1651 | #define GPIO_CRH_MODE15_Pos (28U) |
||
| 1652 | #define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ |
||
| 1653 | #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
||
| 1654 | #define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ |
||
| 1655 | #define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ |
||
| 1656 | |||
| 1657 | #define GPIO_CRH_CNF_Pos (2U) |
||
| 1658 | #define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ |
||
| 1659 | #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ |
||
| 1660 | |||
| 1661 | #define GPIO_CRH_CNF8_Pos (2U) |
||
| 1662 | #define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ |
||
| 1663 | #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
||
| 1664 | #define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ |
||
| 1665 | #define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ |
||
| 1666 | |||
| 1667 | #define GPIO_CRH_CNF9_Pos (6U) |
||
| 1668 | #define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ |
||
| 1669 | #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
||
| 1670 | #define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ |
||
| 1671 | #define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ |
||
| 1672 | |||
| 1673 | #define GPIO_CRH_CNF10_Pos (10U) |
||
| 1674 | #define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ |
||
| 1675 | #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
||
| 1676 | #define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ |
||
| 1677 | #define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ |
||
| 1678 | |||
| 1679 | #define GPIO_CRH_CNF11_Pos (14U) |
||
| 1680 | #define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ |
||
| 1681 | #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
||
| 1682 | #define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ |
||
| 1683 | #define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ |
||
| 1684 | |||
| 1685 | #define GPIO_CRH_CNF12_Pos (18U) |
||
| 1686 | #define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ |
||
| 1687 | #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
||
| 1688 | #define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ |
||
| 1689 | #define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ |
||
| 1690 | |||
| 1691 | #define GPIO_CRH_CNF13_Pos (22U) |
||
| 1692 | #define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ |
||
| 1693 | #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
||
| 1694 | #define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ |
||
| 1695 | #define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ |
||
| 1696 | |||
| 1697 | #define GPIO_CRH_CNF14_Pos (26U) |
||
| 1698 | #define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ |
||
| 1699 | #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
||
| 1700 | #define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ |
||
| 1701 | #define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ |
||
| 1702 | |||
| 1703 | #define GPIO_CRH_CNF15_Pos (30U) |
||
| 1704 | #define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ |
||
| 1705 | #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
||
| 1706 | #define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ |
||
| 1707 | #define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ |
||
| 1708 | |||
| 1709 | /*!<****************** Bit definition for GPIO_IDR register *******************/ |
||
| 1710 | #define GPIO_IDR_IDR0_Pos (0U) |
||
| 1711 | #define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ |
||
| 1712 | #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ |
||
| 1713 | #define GPIO_IDR_IDR1_Pos (1U) |
||
| 1714 | #define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ |
||
| 1715 | #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ |
||
| 1716 | #define GPIO_IDR_IDR2_Pos (2U) |
||
| 1717 | #define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ |
||
| 1718 | #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ |
||
| 1719 | #define GPIO_IDR_IDR3_Pos (3U) |
||
| 1720 | #define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ |
||
| 1721 | #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ |
||
| 1722 | #define GPIO_IDR_IDR4_Pos (4U) |
||
| 1723 | #define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ |
||
| 1724 | #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ |
||
| 1725 | #define GPIO_IDR_IDR5_Pos (5U) |
||
| 1726 | #define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ |
||
| 1727 | #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ |
||
| 1728 | #define GPIO_IDR_IDR6_Pos (6U) |
||
| 1729 | #define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ |
||
| 1730 | #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ |
||
| 1731 | #define GPIO_IDR_IDR7_Pos (7U) |
||
| 1732 | #define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ |
||
| 1733 | #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ |
||
| 1734 | #define GPIO_IDR_IDR8_Pos (8U) |
||
| 1735 | #define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ |
||
| 1736 | #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ |
||
| 1737 | #define GPIO_IDR_IDR9_Pos (9U) |
||
| 1738 | #define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ |
||
| 1739 | #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ |
||
| 1740 | #define GPIO_IDR_IDR10_Pos (10U) |
||
| 1741 | #define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ |
||
| 1742 | #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ |
||
| 1743 | #define GPIO_IDR_IDR11_Pos (11U) |
||
| 1744 | #define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ |
||
| 1745 | #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ |
||
| 1746 | #define GPIO_IDR_IDR12_Pos (12U) |
||
| 1747 | #define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ |
||
| 1748 | #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ |
||
| 1749 | #define GPIO_IDR_IDR13_Pos (13U) |
||
| 1750 | #define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ |
||
| 1751 | #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ |
||
| 1752 | #define GPIO_IDR_IDR14_Pos (14U) |
||
| 1753 | #define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ |
||
| 1754 | #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ |
||
| 1755 | #define GPIO_IDR_IDR15_Pos (15U) |
||
| 1756 | #define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ |
||
| 1757 | #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ |
||
| 1758 | |||
| 1759 | /******************* Bit definition for GPIO_ODR register *******************/ |
||
| 1760 | #define GPIO_ODR_ODR0_Pos (0U) |
||
| 1761 | #define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ |
||
| 1762 | #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ |
||
| 1763 | #define GPIO_ODR_ODR1_Pos (1U) |
||
| 1764 | #define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ |
||
| 1765 | #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ |
||
| 1766 | #define GPIO_ODR_ODR2_Pos (2U) |
||
| 1767 | #define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ |
||
| 1768 | #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ |
||
| 1769 | #define GPIO_ODR_ODR3_Pos (3U) |
||
| 1770 | #define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ |
||
| 1771 | #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ |
||
| 1772 | #define GPIO_ODR_ODR4_Pos (4U) |
||
| 1773 | #define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ |
||
| 1774 | #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ |
||
| 1775 | #define GPIO_ODR_ODR5_Pos (5U) |
||
| 1776 | #define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ |
||
| 1777 | #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ |
||
| 1778 | #define GPIO_ODR_ODR6_Pos (6U) |
||
| 1779 | #define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ |
||
| 1780 | #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ |
||
| 1781 | #define GPIO_ODR_ODR7_Pos (7U) |
||
| 1782 | #define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ |
||
| 1783 | #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ |
||
| 1784 | #define GPIO_ODR_ODR8_Pos (8U) |
||
| 1785 | #define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ |
||
| 1786 | #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ |
||
| 1787 | #define GPIO_ODR_ODR9_Pos (9U) |
||
| 1788 | #define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ |
||
| 1789 | #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ |
||
| 1790 | #define GPIO_ODR_ODR10_Pos (10U) |
||
| 1791 | #define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ |
||
| 1792 | #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ |
||
| 1793 | #define GPIO_ODR_ODR11_Pos (11U) |
||
| 1794 | #define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ |
||
| 1795 | #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ |
||
| 1796 | #define GPIO_ODR_ODR12_Pos (12U) |
||
| 1797 | #define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ |
||
| 1798 | #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ |
||
| 1799 | #define GPIO_ODR_ODR13_Pos (13U) |
||
| 1800 | #define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ |
||
| 1801 | #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ |
||
| 1802 | #define GPIO_ODR_ODR14_Pos (14U) |
||
| 1803 | #define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ |
||
| 1804 | #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ |
||
| 1805 | #define GPIO_ODR_ODR15_Pos (15U) |
||
| 1806 | #define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ |
||
| 1807 | #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ |
||
| 1808 | |||
| 1809 | /****************** Bit definition for GPIO_BSRR register *******************/ |
||
| 1810 | #define GPIO_BSRR_BS0_Pos (0U) |
||
| 1811 | #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ |
||
| 1812 | #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ |
||
| 1813 | #define GPIO_BSRR_BS1_Pos (1U) |
||
| 1814 | #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ |
||
| 1815 | #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ |
||
| 1816 | #define GPIO_BSRR_BS2_Pos (2U) |
||
| 1817 | #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ |
||
| 1818 | #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ |
||
| 1819 | #define GPIO_BSRR_BS3_Pos (3U) |
||
| 1820 | #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ |
||
| 1821 | #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ |
||
| 1822 | #define GPIO_BSRR_BS4_Pos (4U) |
||
| 1823 | #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ |
||
| 1824 | #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ |
||
| 1825 | #define GPIO_BSRR_BS5_Pos (5U) |
||
| 1826 | #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ |
||
| 1827 | #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ |
||
| 1828 | #define GPIO_BSRR_BS6_Pos (6U) |
||
| 1829 | #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ |
||
| 1830 | #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ |
||
| 1831 | #define GPIO_BSRR_BS7_Pos (7U) |
||
| 1832 | #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ |
||
| 1833 | #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ |
||
| 1834 | #define GPIO_BSRR_BS8_Pos (8U) |
||
| 1835 | #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ |
||
| 1836 | #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ |
||
| 1837 | #define GPIO_BSRR_BS9_Pos (9U) |
||
| 1838 | #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ |
||
| 1839 | #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ |
||
| 1840 | #define GPIO_BSRR_BS10_Pos (10U) |
||
| 1841 | #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ |
||
| 1842 | #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ |
||
| 1843 | #define GPIO_BSRR_BS11_Pos (11U) |
||
| 1844 | #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ |
||
| 1845 | #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ |
||
| 1846 | #define GPIO_BSRR_BS12_Pos (12U) |
||
| 1847 | #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ |
||
| 1848 | #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ |
||
| 1849 | #define GPIO_BSRR_BS13_Pos (13U) |
||
| 1850 | #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ |
||
| 1851 | #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ |
||
| 1852 | #define GPIO_BSRR_BS14_Pos (14U) |
||
| 1853 | #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ |
||
| 1854 | #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ |
||
| 1855 | #define GPIO_BSRR_BS15_Pos (15U) |
||
| 1856 | #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ |
||
| 1857 | #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ |
||
| 1858 | |||
| 1859 | #define GPIO_BSRR_BR0_Pos (16U) |
||
| 1860 | #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ |
||
| 1861 | #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ |
||
| 1862 | #define GPIO_BSRR_BR1_Pos (17U) |
||
| 1863 | #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ |
||
| 1864 | #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ |
||
| 1865 | #define GPIO_BSRR_BR2_Pos (18U) |
||
| 1866 | #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ |
||
| 1867 | #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ |
||
| 1868 | #define GPIO_BSRR_BR3_Pos (19U) |
||
| 1869 | #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ |
||
| 1870 | #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ |
||
| 1871 | #define GPIO_BSRR_BR4_Pos (20U) |
||
| 1872 | #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ |
||
| 1873 | #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ |
||
| 1874 | #define GPIO_BSRR_BR5_Pos (21U) |
||
| 1875 | #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ |
||
| 1876 | #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ |
||
| 1877 | #define GPIO_BSRR_BR6_Pos (22U) |
||
| 1878 | #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ |
||
| 1879 | #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ |
||
| 1880 | #define GPIO_BSRR_BR7_Pos (23U) |
||
| 1881 | #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ |
||
| 1882 | #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ |
||
| 1883 | #define GPIO_BSRR_BR8_Pos (24U) |
||
| 1884 | #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ |
||
| 1885 | #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ |
||
| 1886 | #define GPIO_BSRR_BR9_Pos (25U) |
||
| 1887 | #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ |
||
| 1888 | #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ |
||
| 1889 | #define GPIO_BSRR_BR10_Pos (26U) |
||
| 1890 | #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ |
||
| 1891 | #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ |
||
| 1892 | #define GPIO_BSRR_BR11_Pos (27U) |
||
| 1893 | #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ |
||
| 1894 | #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ |
||
| 1895 | #define GPIO_BSRR_BR12_Pos (28U) |
||
| 1896 | #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ |
||
| 1897 | #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ |
||
| 1898 | #define GPIO_BSRR_BR13_Pos (29U) |
||
| 1899 | #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ |
||
| 1900 | #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ |
||
| 1901 | #define GPIO_BSRR_BR14_Pos (30U) |
||
| 1902 | #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ |
||
| 1903 | #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ |
||
| 1904 | #define GPIO_BSRR_BR15_Pos (31U) |
||
| 1905 | #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ |
||
| 1906 | #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ |
||
| 1907 | |||
| 1908 | /******************* Bit definition for GPIO_BRR register *******************/ |
||
| 1909 | #define GPIO_BRR_BR0_Pos (0U) |
||
| 1910 | #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ |
||
| 1911 | #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ |
||
| 1912 | #define GPIO_BRR_BR1_Pos (1U) |
||
| 1913 | #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ |
||
| 1914 | #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ |
||
| 1915 | #define GPIO_BRR_BR2_Pos (2U) |
||
| 1916 | #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ |
||
| 1917 | #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ |
||
| 1918 | #define GPIO_BRR_BR3_Pos (3U) |
||
| 1919 | #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ |
||
| 1920 | #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ |
||
| 1921 | #define GPIO_BRR_BR4_Pos (4U) |
||
| 1922 | #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ |
||
| 1923 | #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ |
||
| 1924 | #define GPIO_BRR_BR5_Pos (5U) |
||
| 1925 | #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ |
||
| 1926 | #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ |
||
| 1927 | #define GPIO_BRR_BR6_Pos (6U) |
||
| 1928 | #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ |
||
| 1929 | #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ |
||
| 1930 | #define GPIO_BRR_BR7_Pos (7U) |
||
| 1931 | #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ |
||
| 1932 | #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ |
||
| 1933 | #define GPIO_BRR_BR8_Pos (8U) |
||
| 1934 | #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ |
||
| 1935 | #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ |
||
| 1936 | #define GPIO_BRR_BR9_Pos (9U) |
||
| 1937 | #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ |
||
| 1938 | #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ |
||
| 1939 | #define GPIO_BRR_BR10_Pos (10U) |
||
| 1940 | #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ |
||
| 1941 | #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ |
||
| 1942 | #define GPIO_BRR_BR11_Pos (11U) |
||
| 1943 | #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ |
||
| 1944 | #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ |
||
| 1945 | #define GPIO_BRR_BR12_Pos (12U) |
||
| 1946 | #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ |
||
| 1947 | #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ |
||
| 1948 | #define GPIO_BRR_BR13_Pos (13U) |
||
| 1949 | #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ |
||
| 1950 | #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ |
||
| 1951 | #define GPIO_BRR_BR14_Pos (14U) |
||
| 1952 | #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ |
||
| 1953 | #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ |
||
| 1954 | #define GPIO_BRR_BR15_Pos (15U) |
||
| 1955 | #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ |
||
| 1956 | #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ |
||
| 1957 | |||
| 1958 | /****************** Bit definition for GPIO_LCKR register *******************/ |
||
| 1959 | #define GPIO_LCKR_LCK0_Pos (0U) |
||
| 1960 | #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
||
| 1961 | #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ |
||
| 1962 | #define GPIO_LCKR_LCK1_Pos (1U) |
||
| 1963 | #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
||
| 1964 | #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ |
||
| 1965 | #define GPIO_LCKR_LCK2_Pos (2U) |
||
| 1966 | #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
||
| 1967 | #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ |
||
| 1968 | #define GPIO_LCKR_LCK3_Pos (3U) |
||
| 1969 | #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
||
| 1970 | #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ |
||
| 1971 | #define GPIO_LCKR_LCK4_Pos (4U) |
||
| 1972 | #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
||
| 1973 | #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ |
||
| 1974 | #define GPIO_LCKR_LCK5_Pos (5U) |
||
| 1975 | #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
||
| 1976 | #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ |
||
| 1977 | #define GPIO_LCKR_LCK6_Pos (6U) |
||
| 1978 | #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
||
| 1979 | #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ |
||
| 1980 | #define GPIO_LCKR_LCK7_Pos (7U) |
||
| 1981 | #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
||
| 1982 | #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ |
||
| 1983 | #define GPIO_LCKR_LCK8_Pos (8U) |
||
| 1984 | #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
||
| 1985 | #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ |
||
| 1986 | #define GPIO_LCKR_LCK9_Pos (9U) |
||
| 1987 | #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
||
| 1988 | #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ |
||
| 1989 | #define GPIO_LCKR_LCK10_Pos (10U) |
||
| 1990 | #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
||
| 1991 | #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ |
||
| 1992 | #define GPIO_LCKR_LCK11_Pos (11U) |
||
| 1993 | #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
||
| 1994 | #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ |
||
| 1995 | #define GPIO_LCKR_LCK12_Pos (12U) |
||
| 1996 | #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
||
| 1997 | #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ |
||
| 1998 | #define GPIO_LCKR_LCK13_Pos (13U) |
||
| 1999 | #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
||
| 2000 | #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ |
||
| 2001 | #define GPIO_LCKR_LCK14_Pos (14U) |
||
| 2002 | #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
||
| 2003 | #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ |
||
| 2004 | #define GPIO_LCKR_LCK15_Pos (15U) |
||
| 2005 | #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
||
| 2006 | #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ |
||
| 2007 | #define GPIO_LCKR_LCKK_Pos (16U) |
||
| 2008 | #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
||
| 2009 | #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ |
||
| 2010 | |||
| 2011 | /*----------------------------------------------------------------------------*/ |
||
| 2012 | |||
| 2013 | /****************** Bit definition for AFIO_EVCR register *******************/ |
||
| 2014 | #define AFIO_EVCR_PIN_Pos (0U) |
||
| 2015 | #define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ |
||
| 2016 | #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ |
||
| 2017 | #define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ |
||
| 2018 | #define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ |
||
| 2019 | #define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ |
||
| 2020 | #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ |
||
| 2021 | |||
| 2022 | /*!< PIN configuration */ |
||
| 2023 | #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ |
||
| 2024 | #define AFIO_EVCR_PIN_PX1_Pos (0U) |
||
| 2025 | #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ |
||
| 2026 | #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ |
||
| 2027 | #define AFIO_EVCR_PIN_PX2_Pos (1U) |
||
| 2028 | #define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ |
||
| 2029 | #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ |
||
| 2030 | #define AFIO_EVCR_PIN_PX3_Pos (0U) |
||
| 2031 | #define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ |
||
| 2032 | #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ |
||
| 2033 | #define AFIO_EVCR_PIN_PX4_Pos (2U) |
||
| 2034 | #define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ |
||
| 2035 | #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ |
||
| 2036 | #define AFIO_EVCR_PIN_PX5_Pos (0U) |
||
| 2037 | #define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ |
||
| 2038 | #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ |
||
| 2039 | #define AFIO_EVCR_PIN_PX6_Pos (1U) |
||
| 2040 | #define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ |
||
| 2041 | #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ |
||
| 2042 | #define AFIO_EVCR_PIN_PX7_Pos (0U) |
||
| 2043 | #define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ |
||
| 2044 | #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ |
||
| 2045 | #define AFIO_EVCR_PIN_PX8_Pos (3U) |
||
| 2046 | #define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ |
||
| 2047 | #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ |
||
| 2048 | #define AFIO_EVCR_PIN_PX9_Pos (0U) |
||
| 2049 | #define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ |
||
| 2050 | #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ |
||
| 2051 | #define AFIO_EVCR_PIN_PX10_Pos (1U) |
||
| 2052 | #define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ |
||
| 2053 | #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ |
||
| 2054 | #define AFIO_EVCR_PIN_PX11_Pos (0U) |
||
| 2055 | #define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ |
||
| 2056 | #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ |
||
| 2057 | #define AFIO_EVCR_PIN_PX12_Pos (2U) |
||
| 2058 | #define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ |
||
| 2059 | #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ |
||
| 2060 | #define AFIO_EVCR_PIN_PX13_Pos (0U) |
||
| 2061 | #define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ |
||
| 2062 | #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ |
||
| 2063 | #define AFIO_EVCR_PIN_PX14_Pos (1U) |
||
| 2064 | #define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ |
||
| 2065 | #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ |
||
| 2066 | #define AFIO_EVCR_PIN_PX15_Pos (0U) |
||
| 2067 | #define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ |
||
| 2068 | #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ |
||
| 2069 | |||
| 2070 | #define AFIO_EVCR_PORT_Pos (4U) |
||
| 2071 | #define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ |
||
| 2072 | #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ |
||
| 2073 | #define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ |
||
| 2074 | #define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ |
||
| 2075 | #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ |
||
| 2076 | |||
| 2077 | /*!< PORT configuration */ |
||
| 2078 | #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ |
||
| 2079 | #define AFIO_EVCR_PORT_PB_Pos (4U) |
||
| 2080 | #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ |
||
| 2081 | #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ |
||
| 2082 | #define AFIO_EVCR_PORT_PC_Pos (5U) |
||
| 2083 | #define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ |
||
| 2084 | #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ |
||
| 2085 | #define AFIO_EVCR_PORT_PD_Pos (4U) |
||
| 2086 | #define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ |
||
| 2087 | #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ |
||
| 2088 | #define AFIO_EVCR_PORT_PE_Pos (6U) |
||
| 2089 | #define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ |
||
| 2090 | #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ |
||
| 2091 | |||
| 2092 | #define AFIO_EVCR_EVOE_Pos (7U) |
||
| 2093 | #define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ |
||
| 2094 | #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ |
||
| 2095 | |||
| 2096 | /****************** Bit definition for AFIO_MAPR register *******************/ |
||
| 2097 | #define AFIO_MAPR_SPI1_REMAP_Pos (0U) |
||
| 2098 | #define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ |
||
| 2099 | #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ |
||
| 2100 | #define AFIO_MAPR_I2C1_REMAP_Pos (1U) |
||
| 2101 | #define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ |
||
| 2102 | #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ |
||
| 2103 | #define AFIO_MAPR_USART1_REMAP_Pos (2U) |
||
| 2104 | #define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ |
||
| 2105 | #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ |
||
| 2106 | #define AFIO_MAPR_USART2_REMAP_Pos (3U) |
||
| 2107 | #define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ |
||
| 2108 | #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ |
||
| 2109 | |||
| 2110 | #define AFIO_MAPR_USART3_REMAP_Pos (4U) |
||
| 2111 | #define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ |
||
| 2112 | #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
||
| 2113 | #define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ |
||
| 2114 | #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ |
||
| 2115 | |||
| 2116 | /* USART3_REMAP configuration */ |
||
| 2117 | #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
||
| 2118 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) |
||
| 2119 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ |
||
| 2120 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
||
| 2121 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) |
||
| 2122 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ |
||
| 2123 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
||
| 2124 | |||
| 2125 | #define AFIO_MAPR_TIM1_REMAP_Pos (6U) |
||
| 2126 | #define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ |
||
| 2127 | #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
||
| 2128 | #define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ |
||
| 2129 | #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ |
||
| 2130 | |||
| 2131 | /*!< TIM1_REMAP configuration */ |
||
| 2132 | #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
||
| 2133 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) |
||
| 2134 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ |
||
| 2135 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
||
| 2136 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) |
||
| 2137 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ |
||
| 2138 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
||
| 2139 | |||
| 2140 | #define AFIO_MAPR_TIM2_REMAP_Pos (8U) |
||
| 2141 | #define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ |
||
| 2142 | #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
||
| 2143 | #define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ |
||
| 2144 | #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ |
||
| 2145 | |||
| 2146 | /*!< TIM2_REMAP configuration */ |
||
| 2147 | #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
||
| 2148 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) |
||
| 2149 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ |
||
| 2150 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
||
| 2151 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) |
||
| 2152 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ |
||
| 2153 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
||
| 2154 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) |
||
| 2155 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ |
||
| 2156 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
||
| 2157 | |||
| 2158 | #define AFIO_MAPR_TIM3_REMAP_Pos (10U) |
||
| 2159 | #define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ |
||
| 2160 | #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
||
| 2161 | #define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ |
||
| 2162 | #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ |
||
| 2163 | |||
| 2164 | /*!< TIM3_REMAP configuration */ |
||
| 2165 | #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
||
| 2166 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) |
||
| 2167 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ |
||
| 2168 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
||
| 2169 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) |
||
| 2170 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ |
||
| 2171 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
||
| 2172 | |||
| 2173 | #define AFIO_MAPR_TIM4_REMAP_Pos (12U) |
||
| 2174 | #define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ |
||
| 2175 | #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ |
||
| 2176 | |||
| 2177 | |||
| 2178 | #define AFIO_MAPR_PD01_REMAP_Pos (15U) |
||
| 2179 | #define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ |
||
| 2180 | #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
||
| 2181 | |||
| 2182 | /*!< SWJ_CFG configuration */ |
||
| 2183 | #define AFIO_MAPR_SWJ_CFG_Pos (24U) |
||
| 2184 | #define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ |
||
| 2185 | #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
||
| 2186 | #define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ |
||
| 2187 | #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ |
||
| 2188 | #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ |
||
| 2189 | |||
| 2190 | #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
||
| 2191 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) |
||
| 2192 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ |
||
| 2193 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
||
| 2194 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) |
||
| 2195 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ |
||
| 2196 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ |
||
| 2197 | #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) |
||
| 2198 | #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ |
||
| 2199 | #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ |
||
| 2200 | |||
| 2201 | |||
| 2202 | /***************** Bit definition for AFIO_EXTICR1 register *****************/ |
||
| 2203 | #define AFIO_EXTICR1_EXTI0_Pos (0U) |
||
| 2204 | #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ |
||
| 2205 | #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ |
||
| 2206 | #define AFIO_EXTICR1_EXTI1_Pos (4U) |
||
| 2207 | #define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ |
||
| 2208 | #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ |
||
| 2209 | #define AFIO_EXTICR1_EXTI2_Pos (8U) |
||
| 2210 | #define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ |
||
| 2211 | #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ |
||
| 2212 | #define AFIO_EXTICR1_EXTI3_Pos (12U) |
||
| 2213 | #define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ |
||
| 2214 | #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ |
||
| 2215 | |||
| 2216 | /*!< EXTI0 configuration */ |
||
| 2217 | #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ |
||
| 2218 | #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) |
||
| 2219 | #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ |
||
| 2220 | #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ |
||
| 2221 | #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) |
||
| 2222 | #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ |
||
| 2223 | #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ |
||
| 2224 | #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) |
||
| 2225 | #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ |
||
| 2226 | #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ |
||
| 2227 | #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) |
||
| 2228 | #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ |
||
| 2229 | #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ |
||
| 2230 | #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) |
||
| 2231 | #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ |
||
| 2232 | #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ |
||
| 2233 | #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) |
||
| 2234 | #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ |
||
| 2235 | #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ |
||
| 2236 | |||
| 2237 | /*!< EXTI1 configuration */ |
||
| 2238 | #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ |
||
| 2239 | #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) |
||
| 2240 | #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ |
||
| 2241 | #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ |
||
| 2242 | #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) |
||
| 2243 | #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ |
||
| 2244 | #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ |
||
| 2245 | #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) |
||
| 2246 | #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ |
||
| 2247 | #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ |
||
| 2248 | #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) |
||
| 2249 | #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ |
||
| 2250 | #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ |
||
| 2251 | #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) |
||
| 2252 | #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ |
||
| 2253 | #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ |
||
| 2254 | #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) |
||
| 2255 | #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ |
||
| 2256 | #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ |
||
| 2257 | |||
| 2258 | /*!< EXTI2 configuration */ |
||
| 2259 | #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ |
||
| 2260 | #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) |
||
| 2261 | #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ |
||
| 2262 | #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ |
||
| 2263 | #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) |
||
| 2264 | #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ |
||
| 2265 | #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ |
||
| 2266 | #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) |
||
| 2267 | #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ |
||
| 2268 | #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ |
||
| 2269 | #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) |
||
| 2270 | #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ |
||
| 2271 | #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ |
||
| 2272 | #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) |
||
| 2273 | #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ |
||
| 2274 | #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ |
||
| 2275 | #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) |
||
| 2276 | #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ |
||
| 2277 | #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ |
||
| 2278 | |||
| 2279 | /*!< EXTI3 configuration */ |
||
| 2280 | #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ |
||
| 2281 | #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) |
||
| 2282 | #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ |
||
| 2283 | #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ |
||
| 2284 | #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) |
||
| 2285 | #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ |
||
| 2286 | #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ |
||
| 2287 | #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) |
||
| 2288 | #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ |
||
| 2289 | #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ |
||
| 2290 | #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) |
||
| 2291 | #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ |
||
| 2292 | #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ |
||
| 2293 | #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) |
||
| 2294 | #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ |
||
| 2295 | #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ |
||
| 2296 | #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) |
||
| 2297 | #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ |
||
| 2298 | #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ |
||
| 2299 | |||
| 2300 | /***************** Bit definition for AFIO_EXTICR2 register *****************/ |
||
| 2301 | #define AFIO_EXTICR2_EXTI4_Pos (0U) |
||
| 2302 | #define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
||
| 2303 | #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
||
| 2304 | #define AFIO_EXTICR2_EXTI5_Pos (4U) |
||
| 2305 | #define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ |
||
| 2306 | #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ |
||
| 2307 | #define AFIO_EXTICR2_EXTI6_Pos (8U) |
||
| 2308 | #define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ |
||
| 2309 | #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ |
||
| 2310 | #define AFIO_EXTICR2_EXTI7_Pos (12U) |
||
| 2311 | #define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ |
||
| 2312 | #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ |
||
| 2313 | |||
| 2314 | /*!< EXTI4 configuration */ |
||
| 2315 | #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ |
||
| 2316 | #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) |
||
| 2317 | #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ |
||
| 2318 | #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ |
||
| 2319 | #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) |
||
| 2320 | #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ |
||
| 2321 | #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ |
||
| 2322 | #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) |
||
| 2323 | #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ |
||
| 2324 | #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ |
||
| 2325 | #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) |
||
| 2326 | #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ |
||
| 2327 | #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ |
||
| 2328 | #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) |
||
| 2329 | #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ |
||
| 2330 | #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ |
||
| 2331 | #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) |
||
| 2332 | #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ |
||
| 2333 | #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ |
||
| 2334 | |||
| 2335 | /* EXTI5 configuration */ |
||
| 2336 | #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ |
||
| 2337 | #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) |
||
| 2338 | #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ |
||
| 2339 | #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ |
||
| 2340 | #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) |
||
| 2341 | #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ |
||
| 2342 | #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ |
||
| 2343 | #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) |
||
| 2344 | #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ |
||
| 2345 | #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ |
||
| 2346 | #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) |
||
| 2347 | #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ |
||
| 2348 | #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ |
||
| 2349 | #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) |
||
| 2350 | #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ |
||
| 2351 | #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ |
||
| 2352 | #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) |
||
| 2353 | #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ |
||
| 2354 | #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ |
||
| 2355 | |||
| 2356 | /*!< EXTI6 configuration */ |
||
| 2357 | #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ |
||
| 2358 | #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) |
||
| 2359 | #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ |
||
| 2360 | #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ |
||
| 2361 | #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) |
||
| 2362 | #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ |
||
| 2363 | #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ |
||
| 2364 | #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) |
||
| 2365 | #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ |
||
| 2366 | #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ |
||
| 2367 | #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) |
||
| 2368 | #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ |
||
| 2369 | #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ |
||
| 2370 | #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) |
||
| 2371 | #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ |
||
| 2372 | #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ |
||
| 2373 | #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) |
||
| 2374 | #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ |
||
| 2375 | #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ |
||
| 2376 | |||
| 2377 | /*!< EXTI7 configuration */ |
||
| 2378 | #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ |
||
| 2379 | #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) |
||
| 2380 | #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ |
||
| 2381 | #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ |
||
| 2382 | #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) |
||
| 2383 | #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ |
||
| 2384 | #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ |
||
| 2385 | #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) |
||
| 2386 | #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ |
||
| 2387 | #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ |
||
| 2388 | #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) |
||
| 2389 | #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ |
||
| 2390 | #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ |
||
| 2391 | #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) |
||
| 2392 | #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ |
||
| 2393 | #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ |
||
| 2394 | #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) |
||
| 2395 | #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ |
||
| 2396 | #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ |
||
| 2397 | |||
| 2398 | /***************** Bit definition for AFIO_EXTICR3 register *****************/ |
||
| 2399 | #define AFIO_EXTICR3_EXTI8_Pos (0U) |
||
| 2400 | #define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ |
||
| 2401 | #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ |
||
| 2402 | #define AFIO_EXTICR3_EXTI9_Pos (4U) |
||
| 2403 | #define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ |
||
| 2404 | #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ |
||
| 2405 | #define AFIO_EXTICR3_EXTI10_Pos (8U) |
||
| 2406 | #define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ |
||
| 2407 | #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ |
||
| 2408 | #define AFIO_EXTICR3_EXTI11_Pos (12U) |
||
| 2409 | #define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ |
||
| 2410 | #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ |
||
| 2411 | |||
| 2412 | /*!< EXTI8 configuration */ |
||
| 2413 | #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ |
||
| 2414 | #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) |
||
| 2415 | #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ |
||
| 2416 | #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ |
||
| 2417 | #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) |
||
| 2418 | #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ |
||
| 2419 | #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ |
||
| 2420 | #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) |
||
| 2421 | #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ |
||
| 2422 | #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ |
||
| 2423 | #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) |
||
| 2424 | #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ |
||
| 2425 | #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ |
||
| 2426 | #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) |
||
| 2427 | #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ |
||
| 2428 | #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ |
||
| 2429 | #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) |
||
| 2430 | #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ |
||
| 2431 | #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ |
||
| 2432 | |||
| 2433 | /*!< EXTI9 configuration */ |
||
| 2434 | #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ |
||
| 2435 | #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) |
||
| 2436 | #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ |
||
| 2437 | #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ |
||
| 2438 | #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) |
||
| 2439 | #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ |
||
| 2440 | #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ |
||
| 2441 | #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) |
||
| 2442 | #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ |
||
| 2443 | #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ |
||
| 2444 | #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) |
||
| 2445 | #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ |
||
| 2446 | #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ |
||
| 2447 | #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) |
||
| 2448 | #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ |
||
| 2449 | #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ |
||
| 2450 | #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) |
||
| 2451 | #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ |
||
| 2452 | #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ |
||
| 2453 | |||
| 2454 | /*!< EXTI10 configuration */ |
||
| 2455 | #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ |
||
| 2456 | #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) |
||
| 2457 | #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ |
||
| 2458 | #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ |
||
| 2459 | #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) |
||
| 2460 | #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ |
||
| 2461 | #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ |
||
| 2462 | #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) |
||
| 2463 | #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ |
||
| 2464 | #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ |
||
| 2465 | #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) |
||
| 2466 | #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ |
||
| 2467 | #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ |
||
| 2468 | #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) |
||
| 2469 | #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ |
||
| 2470 | #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ |
||
| 2471 | #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) |
||
| 2472 | #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ |
||
| 2473 | #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ |
||
| 2474 | |||
| 2475 | /*!< EXTI11 configuration */ |
||
| 2476 | #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ |
||
| 2477 | #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) |
||
| 2478 | #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ |
||
| 2479 | #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ |
||
| 2480 | #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) |
||
| 2481 | #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ |
||
| 2482 | #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ |
||
| 2483 | #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) |
||
| 2484 | #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ |
||
| 2485 | #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ |
||
| 2486 | #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) |
||
| 2487 | #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ |
||
| 2488 | #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ |
||
| 2489 | #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) |
||
| 2490 | #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ |
||
| 2491 | #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ |
||
| 2492 | #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) |
||
| 2493 | #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ |
||
| 2494 | #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ |
||
| 2495 | |||
| 2496 | /***************** Bit definition for AFIO_EXTICR4 register *****************/ |
||
| 2497 | #define AFIO_EXTICR4_EXTI12_Pos (0U) |
||
| 2498 | #define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ |
||
| 2499 | #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ |
||
| 2500 | #define AFIO_EXTICR4_EXTI13_Pos (4U) |
||
| 2501 | #define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ |
||
| 2502 | #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ |
||
| 2503 | #define AFIO_EXTICR4_EXTI14_Pos (8U) |
||
| 2504 | #define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ |
||
| 2505 | #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ |
||
| 2506 | #define AFIO_EXTICR4_EXTI15_Pos (12U) |
||
| 2507 | #define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ |
||
| 2508 | #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ |
||
| 2509 | |||
| 2510 | /* EXTI12 configuration */ |
||
| 2511 | #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ |
||
| 2512 | #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) |
||
| 2513 | #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ |
||
| 2514 | #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ |
||
| 2515 | #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) |
||
| 2516 | #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ |
||
| 2517 | #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ |
||
| 2518 | #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) |
||
| 2519 | #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ |
||
| 2520 | #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ |
||
| 2521 | #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) |
||
| 2522 | #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ |
||
| 2523 | #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ |
||
| 2524 | #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) |
||
| 2525 | #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ |
||
| 2526 | #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ |
||
| 2527 | #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) |
||
| 2528 | #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ |
||
| 2529 | #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ |
||
| 2530 | |||
| 2531 | /* EXTI13 configuration */ |
||
| 2532 | #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ |
||
| 2533 | #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) |
||
| 2534 | #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ |
||
| 2535 | #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ |
||
| 2536 | #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) |
||
| 2537 | #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ |
||
| 2538 | #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ |
||
| 2539 | #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) |
||
| 2540 | #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ |
||
| 2541 | #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ |
||
| 2542 | #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) |
||
| 2543 | #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ |
||
| 2544 | #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ |
||
| 2545 | #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) |
||
| 2546 | #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ |
||
| 2547 | #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ |
||
| 2548 | #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) |
||
| 2549 | #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ |
||
| 2550 | #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ |
||
| 2551 | |||
| 2552 | /*!< EXTI14 configuration */ |
||
| 2553 | #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ |
||
| 2554 | #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) |
||
| 2555 | #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ |
||
| 2556 | #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ |
||
| 2557 | #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) |
||
| 2558 | #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ |
||
| 2559 | #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ |
||
| 2560 | #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) |
||
| 2561 | #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ |
||
| 2562 | #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ |
||
| 2563 | #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) |
||
| 2564 | #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ |
||
| 2565 | #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ |
||
| 2566 | #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) |
||
| 2567 | #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ |
||
| 2568 | #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ |
||
| 2569 | #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) |
||
| 2570 | #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ |
||
| 2571 | #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ |
||
| 2572 | |||
| 2573 | /*!< EXTI15 configuration */ |
||
| 2574 | #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ |
||
| 2575 | #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) |
||
| 2576 | #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ |
||
| 2577 | #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ |
||
| 2578 | #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) |
||
| 2579 | #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ |
||
| 2580 | #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ |
||
| 2581 | #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) |
||
| 2582 | #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ |
||
| 2583 | #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ |
||
| 2584 | #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) |
||
| 2585 | #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ |
||
| 2586 | #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ |
||
| 2587 | #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) |
||
| 2588 | #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ |
||
| 2589 | #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ |
||
| 2590 | #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) |
||
| 2591 | #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ |
||
| 2592 | #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ |
||
| 2593 | |||
| 2594 | /****************** Bit definition for AFIO_MAPR2 register ******************/ |
||
| 2595 | #define AFIO_MAPR2_TIM15_REMAP_Pos (0U) |
||
| 2596 | #define AFIO_MAPR2_TIM15_REMAP_Msk (0x1U << AFIO_MAPR2_TIM15_REMAP_Pos) /*!< 0x00000001 */ |
||
| 2597 | #define AFIO_MAPR2_TIM15_REMAP AFIO_MAPR2_TIM15_REMAP_Msk /*!< TIM15 remapping */ |
||
| 2598 | #define AFIO_MAPR2_TIM16_REMAP_Pos (1U) |
||
| 2599 | #define AFIO_MAPR2_TIM16_REMAP_Msk (0x1U << AFIO_MAPR2_TIM16_REMAP_Pos) /*!< 0x00000002 */ |
||
| 2600 | #define AFIO_MAPR2_TIM16_REMAP AFIO_MAPR2_TIM16_REMAP_Msk /*!< TIM16 remapping */ |
||
| 2601 | #define AFIO_MAPR2_TIM17_REMAP_Pos (2U) |
||
| 2602 | #define AFIO_MAPR2_TIM17_REMAP_Msk (0x1U << AFIO_MAPR2_TIM17_REMAP_Pos) /*!< 0x00000004 */ |
||
| 2603 | #define AFIO_MAPR2_TIM17_REMAP AFIO_MAPR2_TIM17_REMAP_Msk /*!< TIM17 remapping */ |
||
| 2604 | #define AFIO_MAPR2_CEC_REMAP_Pos (3U) |
||
| 2605 | #define AFIO_MAPR2_CEC_REMAP_Msk (0x1U << AFIO_MAPR2_CEC_REMAP_Pos) /*!< 0x00000008 */ |
||
| 2606 | #define AFIO_MAPR2_CEC_REMAP AFIO_MAPR2_CEC_REMAP_Msk /*!< CEC remapping */ |
||
| 2607 | #define AFIO_MAPR2_TIM1_DMA_REMAP_Pos (4U) |
||
| 2608 | #define AFIO_MAPR2_TIM1_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM1_DMA_REMAP_Pos) /*!< 0x00000010 */ |
||
| 2609 | #define AFIO_MAPR2_TIM1_DMA_REMAP AFIO_MAPR2_TIM1_DMA_REMAP_Msk /*!< TIM1_DMA remapping */ |
||
| 2610 | |||
| 2611 | #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos (11U) |
||
| 2612 | #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos) /*!< 0x00000800 */ |
||
| 2613 | #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk /*!< TIM6/TIM7 and DAC DMA remapping */ |
||
| 2614 | |||
| 2615 | |||
| 2616 | /******************************************************************************/ |
||
| 2617 | /* */ |
||
| 2618 | /* External Interrupt/Event Controller */ |
||
| 2619 | /* */ |
||
| 2620 | /******************************************************************************/ |
||
| 2621 | |||
| 2622 | /******************* Bit definition for EXTI_IMR register *******************/ |
||
| 2623 | #define EXTI_IMR_MR0_Pos (0U) |
||
| 2624 | #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ |
||
| 2625 | #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ |
||
| 2626 | #define EXTI_IMR_MR1_Pos (1U) |
||
| 2627 | #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ |
||
| 2628 | #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ |
||
| 2629 | #define EXTI_IMR_MR2_Pos (2U) |
||
| 2630 | #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ |
||
| 2631 | #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ |
||
| 2632 | #define EXTI_IMR_MR3_Pos (3U) |
||
| 2633 | #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ |
||
| 2634 | #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ |
||
| 2635 | #define EXTI_IMR_MR4_Pos (4U) |
||
| 2636 | #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ |
||
| 2637 | #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ |
||
| 2638 | #define EXTI_IMR_MR5_Pos (5U) |
||
| 2639 | #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ |
||
| 2640 | #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ |
||
| 2641 | #define EXTI_IMR_MR6_Pos (6U) |
||
| 2642 | #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ |
||
| 2643 | #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ |
||
| 2644 | #define EXTI_IMR_MR7_Pos (7U) |
||
| 2645 | #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ |
||
| 2646 | #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ |
||
| 2647 | #define EXTI_IMR_MR8_Pos (8U) |
||
| 2648 | #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ |
||
| 2649 | #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ |
||
| 2650 | #define EXTI_IMR_MR9_Pos (9U) |
||
| 2651 | #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ |
||
| 2652 | #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ |
||
| 2653 | #define EXTI_IMR_MR10_Pos (10U) |
||
| 2654 | #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ |
||
| 2655 | #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ |
||
| 2656 | #define EXTI_IMR_MR11_Pos (11U) |
||
| 2657 | #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ |
||
| 2658 | #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ |
||
| 2659 | #define EXTI_IMR_MR12_Pos (12U) |
||
| 2660 | #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ |
||
| 2661 | #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ |
||
| 2662 | #define EXTI_IMR_MR13_Pos (13U) |
||
| 2663 | #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ |
||
| 2664 | #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ |
||
| 2665 | #define EXTI_IMR_MR14_Pos (14U) |
||
| 2666 | #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ |
||
| 2667 | #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ |
||
| 2668 | #define EXTI_IMR_MR15_Pos (15U) |
||
| 2669 | #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ |
||
| 2670 | #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ |
||
| 2671 | #define EXTI_IMR_MR16_Pos (16U) |
||
| 2672 | #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ |
||
| 2673 | #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ |
||
| 2674 | #define EXTI_IMR_MR17_Pos (17U) |
||
| 2675 | #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ |
||
| 2676 | #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ |
||
| 2677 | |||
| 2678 | /* References Defines */ |
||
| 2679 | #define EXTI_IMR_IM0 EXTI_IMR_MR0 |
||
| 2680 | #define EXTI_IMR_IM1 EXTI_IMR_MR1 |
||
| 2681 | #define EXTI_IMR_IM2 EXTI_IMR_MR2 |
||
| 2682 | #define EXTI_IMR_IM3 EXTI_IMR_MR3 |
||
| 2683 | #define EXTI_IMR_IM4 EXTI_IMR_MR4 |
||
| 2684 | #define EXTI_IMR_IM5 EXTI_IMR_MR5 |
||
| 2685 | #define EXTI_IMR_IM6 EXTI_IMR_MR6 |
||
| 2686 | #define EXTI_IMR_IM7 EXTI_IMR_MR7 |
||
| 2687 | #define EXTI_IMR_IM8 EXTI_IMR_MR8 |
||
| 2688 | #define EXTI_IMR_IM9 EXTI_IMR_MR9 |
||
| 2689 | #define EXTI_IMR_IM10 EXTI_IMR_MR10 |
||
| 2690 | #define EXTI_IMR_IM11 EXTI_IMR_MR11 |
||
| 2691 | #define EXTI_IMR_IM12 EXTI_IMR_MR12 |
||
| 2692 | #define EXTI_IMR_IM13 EXTI_IMR_MR13 |
||
| 2693 | #define EXTI_IMR_IM14 EXTI_IMR_MR14 |
||
| 2694 | #define EXTI_IMR_IM15 EXTI_IMR_MR15 |
||
| 2695 | #define EXTI_IMR_IM16 EXTI_IMR_MR16 |
||
| 2696 | #define EXTI_IMR_IM17 EXTI_IMR_MR17 |
||
| 2697 | #define EXTI_IMR_IM 0x0003FFFFU /*!< Interrupt Mask All */ |
||
| 2698 | |||
| 2699 | /******************* Bit definition for EXTI_EMR register *******************/ |
||
| 2700 | #define EXTI_EMR_MR0_Pos (0U) |
||
| 2701 | #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ |
||
| 2702 | #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ |
||
| 2703 | #define EXTI_EMR_MR1_Pos (1U) |
||
| 2704 | #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ |
||
| 2705 | #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ |
||
| 2706 | #define EXTI_EMR_MR2_Pos (2U) |
||
| 2707 | #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ |
||
| 2708 | #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ |
||
| 2709 | #define EXTI_EMR_MR3_Pos (3U) |
||
| 2710 | #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ |
||
| 2711 | #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ |
||
| 2712 | #define EXTI_EMR_MR4_Pos (4U) |
||
| 2713 | #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ |
||
| 2714 | #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ |
||
| 2715 | #define EXTI_EMR_MR5_Pos (5U) |
||
| 2716 | #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ |
||
| 2717 | #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ |
||
| 2718 | #define EXTI_EMR_MR6_Pos (6U) |
||
| 2719 | #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ |
||
| 2720 | #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ |
||
| 2721 | #define EXTI_EMR_MR7_Pos (7U) |
||
| 2722 | #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ |
||
| 2723 | #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ |
||
| 2724 | #define EXTI_EMR_MR8_Pos (8U) |
||
| 2725 | #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ |
||
| 2726 | #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ |
||
| 2727 | #define EXTI_EMR_MR9_Pos (9U) |
||
| 2728 | #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ |
||
| 2729 | #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ |
||
| 2730 | #define EXTI_EMR_MR10_Pos (10U) |
||
| 2731 | #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ |
||
| 2732 | #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ |
||
| 2733 | #define EXTI_EMR_MR11_Pos (11U) |
||
| 2734 | #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ |
||
| 2735 | #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ |
||
| 2736 | #define EXTI_EMR_MR12_Pos (12U) |
||
| 2737 | #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ |
||
| 2738 | #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ |
||
| 2739 | #define EXTI_EMR_MR13_Pos (13U) |
||
| 2740 | #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ |
||
| 2741 | #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ |
||
| 2742 | #define EXTI_EMR_MR14_Pos (14U) |
||
| 2743 | #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ |
||
| 2744 | #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ |
||
| 2745 | #define EXTI_EMR_MR15_Pos (15U) |
||
| 2746 | #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ |
||
| 2747 | #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ |
||
| 2748 | #define EXTI_EMR_MR16_Pos (16U) |
||
| 2749 | #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ |
||
| 2750 | #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ |
||
| 2751 | #define EXTI_EMR_MR17_Pos (17U) |
||
| 2752 | #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ |
||
| 2753 | #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ |
||
| 2754 | |||
| 2755 | /* References Defines */ |
||
| 2756 | #define EXTI_EMR_EM0 EXTI_EMR_MR0 |
||
| 2757 | #define EXTI_EMR_EM1 EXTI_EMR_MR1 |
||
| 2758 | #define EXTI_EMR_EM2 EXTI_EMR_MR2 |
||
| 2759 | #define EXTI_EMR_EM3 EXTI_EMR_MR3 |
||
| 2760 | #define EXTI_EMR_EM4 EXTI_EMR_MR4 |
||
| 2761 | #define EXTI_EMR_EM5 EXTI_EMR_MR5 |
||
| 2762 | #define EXTI_EMR_EM6 EXTI_EMR_MR6 |
||
| 2763 | #define EXTI_EMR_EM7 EXTI_EMR_MR7 |
||
| 2764 | #define EXTI_EMR_EM8 EXTI_EMR_MR8 |
||
| 2765 | #define EXTI_EMR_EM9 EXTI_EMR_MR9 |
||
| 2766 | #define EXTI_EMR_EM10 EXTI_EMR_MR10 |
||
| 2767 | #define EXTI_EMR_EM11 EXTI_EMR_MR11 |
||
| 2768 | #define EXTI_EMR_EM12 EXTI_EMR_MR12 |
||
| 2769 | #define EXTI_EMR_EM13 EXTI_EMR_MR13 |
||
| 2770 | #define EXTI_EMR_EM14 EXTI_EMR_MR14 |
||
| 2771 | #define EXTI_EMR_EM15 EXTI_EMR_MR15 |
||
| 2772 | #define EXTI_EMR_EM16 EXTI_EMR_MR16 |
||
| 2773 | #define EXTI_EMR_EM17 EXTI_EMR_MR17 |
||
| 2774 | |||
| 2775 | /****************** Bit definition for EXTI_RTSR register *******************/ |
||
| 2776 | #define EXTI_RTSR_TR0_Pos (0U) |
||
| 2777 | #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ |
||
| 2778 | #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
||
| 2779 | #define EXTI_RTSR_TR1_Pos (1U) |
||
| 2780 | #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ |
||
| 2781 | #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
||
| 2782 | #define EXTI_RTSR_TR2_Pos (2U) |
||
| 2783 | #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ |
||
| 2784 | #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
||
| 2785 | #define EXTI_RTSR_TR3_Pos (3U) |
||
| 2786 | #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ |
||
| 2787 | #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
||
| 2788 | #define EXTI_RTSR_TR4_Pos (4U) |
||
| 2789 | #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ |
||
| 2790 | #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
||
| 2791 | #define EXTI_RTSR_TR5_Pos (5U) |
||
| 2792 | #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ |
||
| 2793 | #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
||
| 2794 | #define EXTI_RTSR_TR6_Pos (6U) |
||
| 2795 | #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ |
||
| 2796 | #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
||
| 2797 | #define EXTI_RTSR_TR7_Pos (7U) |
||
| 2798 | #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ |
||
| 2799 | #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
||
| 2800 | #define EXTI_RTSR_TR8_Pos (8U) |
||
| 2801 | #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ |
||
| 2802 | #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
||
| 2803 | #define EXTI_RTSR_TR9_Pos (9U) |
||
| 2804 | #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ |
||
| 2805 | #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
||
| 2806 | #define EXTI_RTSR_TR10_Pos (10U) |
||
| 2807 | #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ |
||
| 2808 | #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
||
| 2809 | #define EXTI_RTSR_TR11_Pos (11U) |
||
| 2810 | #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ |
||
| 2811 | #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
||
| 2812 | #define EXTI_RTSR_TR12_Pos (12U) |
||
| 2813 | #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ |
||
| 2814 | #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
||
| 2815 | #define EXTI_RTSR_TR13_Pos (13U) |
||
| 2816 | #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ |
||
| 2817 | #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
||
| 2818 | #define EXTI_RTSR_TR14_Pos (14U) |
||
| 2819 | #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ |
||
| 2820 | #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
||
| 2821 | #define EXTI_RTSR_TR15_Pos (15U) |
||
| 2822 | #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ |
||
| 2823 | #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
||
| 2824 | #define EXTI_RTSR_TR16_Pos (16U) |
||
| 2825 | #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ |
||
| 2826 | #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
||
| 2827 | #define EXTI_RTSR_TR17_Pos (17U) |
||
| 2828 | #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ |
||
| 2829 | #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
||
| 2830 | |||
| 2831 | /* References Defines */ |
||
| 2832 | #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 |
||
| 2833 | #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 |
||
| 2834 | #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 |
||
| 2835 | #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 |
||
| 2836 | #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 |
||
| 2837 | #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 |
||
| 2838 | #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 |
||
| 2839 | #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 |
||
| 2840 | #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 |
||
| 2841 | #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 |
||
| 2842 | #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 |
||
| 2843 | #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 |
||
| 2844 | #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 |
||
| 2845 | #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 |
||
| 2846 | #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 |
||
| 2847 | #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 |
||
| 2848 | #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 |
||
| 2849 | #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 |
||
| 2850 | |||
| 2851 | /****************** Bit definition for EXTI_FTSR register *******************/ |
||
| 2852 | #define EXTI_FTSR_TR0_Pos (0U) |
||
| 2853 | #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ |
||
| 2854 | #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
||
| 2855 | #define EXTI_FTSR_TR1_Pos (1U) |
||
| 2856 | #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ |
||
| 2857 | #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
||
| 2858 | #define EXTI_FTSR_TR2_Pos (2U) |
||
| 2859 | #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ |
||
| 2860 | #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
||
| 2861 | #define EXTI_FTSR_TR3_Pos (3U) |
||
| 2862 | #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ |
||
| 2863 | #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
||
| 2864 | #define EXTI_FTSR_TR4_Pos (4U) |
||
| 2865 | #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ |
||
| 2866 | #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
||
| 2867 | #define EXTI_FTSR_TR5_Pos (5U) |
||
| 2868 | #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ |
||
| 2869 | #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
||
| 2870 | #define EXTI_FTSR_TR6_Pos (6U) |
||
| 2871 | #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ |
||
| 2872 | #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
||
| 2873 | #define EXTI_FTSR_TR7_Pos (7U) |
||
| 2874 | #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ |
||
| 2875 | #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
||
| 2876 | #define EXTI_FTSR_TR8_Pos (8U) |
||
| 2877 | #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ |
||
| 2878 | #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
||
| 2879 | #define EXTI_FTSR_TR9_Pos (9U) |
||
| 2880 | #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ |
||
| 2881 | #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
||
| 2882 | #define EXTI_FTSR_TR10_Pos (10U) |
||
| 2883 | #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ |
||
| 2884 | #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
||
| 2885 | #define EXTI_FTSR_TR11_Pos (11U) |
||
| 2886 | #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ |
||
| 2887 | #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
||
| 2888 | #define EXTI_FTSR_TR12_Pos (12U) |
||
| 2889 | #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ |
||
| 2890 | #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
||
| 2891 | #define EXTI_FTSR_TR13_Pos (13U) |
||
| 2892 | #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ |
||
| 2893 | #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
||
| 2894 | #define EXTI_FTSR_TR14_Pos (14U) |
||
| 2895 | #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ |
||
| 2896 | #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
||
| 2897 | #define EXTI_FTSR_TR15_Pos (15U) |
||
| 2898 | #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ |
||
| 2899 | #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
||
| 2900 | #define EXTI_FTSR_TR16_Pos (16U) |
||
| 2901 | #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ |
||
| 2902 | #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
||
| 2903 | #define EXTI_FTSR_TR17_Pos (17U) |
||
| 2904 | #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ |
||
| 2905 | #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
||
| 2906 | |||
| 2907 | /* References Defines */ |
||
| 2908 | #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 |
||
| 2909 | #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 |
||
| 2910 | #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 |
||
| 2911 | #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 |
||
| 2912 | #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 |
||
| 2913 | #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 |
||
| 2914 | #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 |
||
| 2915 | #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 |
||
| 2916 | #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 |
||
| 2917 | #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 |
||
| 2918 | #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 |
||
| 2919 | #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 |
||
| 2920 | #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 |
||
| 2921 | #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 |
||
| 2922 | #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 |
||
| 2923 | #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 |
||
| 2924 | #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 |
||
| 2925 | #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 |
||
| 2926 | |||
| 2927 | /****************** Bit definition for EXTI_SWIER register ******************/ |
||
| 2928 | #define EXTI_SWIER_SWIER0_Pos (0U) |
||
| 2929 | #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ |
||
| 2930 | #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ |
||
| 2931 | #define EXTI_SWIER_SWIER1_Pos (1U) |
||
| 2932 | #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ |
||
| 2933 | #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ |
||
| 2934 | #define EXTI_SWIER_SWIER2_Pos (2U) |
||
| 2935 | #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ |
||
| 2936 | #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ |
||
| 2937 | #define EXTI_SWIER_SWIER3_Pos (3U) |
||
| 2938 | #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ |
||
| 2939 | #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ |
||
| 2940 | #define EXTI_SWIER_SWIER4_Pos (4U) |
||
| 2941 | #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ |
||
| 2942 | #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ |
||
| 2943 | #define EXTI_SWIER_SWIER5_Pos (5U) |
||
| 2944 | #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ |
||
| 2945 | #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ |
||
| 2946 | #define EXTI_SWIER_SWIER6_Pos (6U) |
||
| 2947 | #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ |
||
| 2948 | #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ |
||
| 2949 | #define EXTI_SWIER_SWIER7_Pos (7U) |
||
| 2950 | #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ |
||
| 2951 | #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ |
||
| 2952 | #define EXTI_SWIER_SWIER8_Pos (8U) |
||
| 2953 | #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ |
||
| 2954 | #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ |
||
| 2955 | #define EXTI_SWIER_SWIER9_Pos (9U) |
||
| 2956 | #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ |
||
| 2957 | #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ |
||
| 2958 | #define EXTI_SWIER_SWIER10_Pos (10U) |
||
| 2959 | #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ |
||
| 2960 | #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ |
||
| 2961 | #define EXTI_SWIER_SWIER11_Pos (11U) |
||
| 2962 | #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ |
||
| 2963 | #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ |
||
| 2964 | #define EXTI_SWIER_SWIER12_Pos (12U) |
||
| 2965 | #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ |
||
| 2966 | #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ |
||
| 2967 | #define EXTI_SWIER_SWIER13_Pos (13U) |
||
| 2968 | #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ |
||
| 2969 | #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ |
||
| 2970 | #define EXTI_SWIER_SWIER14_Pos (14U) |
||
| 2971 | #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ |
||
| 2972 | #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ |
||
| 2973 | #define EXTI_SWIER_SWIER15_Pos (15U) |
||
| 2974 | #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ |
||
| 2975 | #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ |
||
| 2976 | #define EXTI_SWIER_SWIER16_Pos (16U) |
||
| 2977 | #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ |
||
| 2978 | #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ |
||
| 2979 | #define EXTI_SWIER_SWIER17_Pos (17U) |
||
| 2980 | #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ |
||
| 2981 | #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ |
||
| 2982 | |||
| 2983 | /* References Defines */ |
||
| 2984 | #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 |
||
| 2985 | #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 |
||
| 2986 | #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 |
||
| 2987 | #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 |
||
| 2988 | #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 |
||
| 2989 | #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 |
||
| 2990 | #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 |
||
| 2991 | #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 |
||
| 2992 | #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 |
||
| 2993 | #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 |
||
| 2994 | #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 |
||
| 2995 | #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 |
||
| 2996 | #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 |
||
| 2997 | #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 |
||
| 2998 | #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 |
||
| 2999 | #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 |
||
| 3000 | #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 |
||
| 3001 | #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 |
||
| 3002 | |||
| 3003 | /******************* Bit definition for EXTI_PR register ********************/ |
||
| 3004 | #define EXTI_PR_PR0_Pos (0U) |
||
| 3005 | #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ |
||
| 3006 | #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ |
||
| 3007 | #define EXTI_PR_PR1_Pos (1U) |
||
| 3008 | #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ |
||
| 3009 | #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ |
||
| 3010 | #define EXTI_PR_PR2_Pos (2U) |
||
| 3011 | #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ |
||
| 3012 | #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ |
||
| 3013 | #define EXTI_PR_PR3_Pos (3U) |
||
| 3014 | #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ |
||
| 3015 | #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ |
||
| 3016 | #define EXTI_PR_PR4_Pos (4U) |
||
| 3017 | #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ |
||
| 3018 | #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ |
||
| 3019 | #define EXTI_PR_PR5_Pos (5U) |
||
| 3020 | #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ |
||
| 3021 | #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ |
||
| 3022 | #define EXTI_PR_PR6_Pos (6U) |
||
| 3023 | #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ |
||
| 3024 | #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ |
||
| 3025 | #define EXTI_PR_PR7_Pos (7U) |
||
| 3026 | #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ |
||
| 3027 | #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ |
||
| 3028 | #define EXTI_PR_PR8_Pos (8U) |
||
| 3029 | #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ |
||
| 3030 | #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ |
||
| 3031 | #define EXTI_PR_PR9_Pos (9U) |
||
| 3032 | #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ |
||
| 3033 | #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ |
||
| 3034 | #define EXTI_PR_PR10_Pos (10U) |
||
| 3035 | #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ |
||
| 3036 | #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ |
||
| 3037 | #define EXTI_PR_PR11_Pos (11U) |
||
| 3038 | #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ |
||
| 3039 | #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ |
||
| 3040 | #define EXTI_PR_PR12_Pos (12U) |
||
| 3041 | #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ |
||
| 3042 | #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ |
||
| 3043 | #define EXTI_PR_PR13_Pos (13U) |
||
| 3044 | #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ |
||
| 3045 | #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ |
||
| 3046 | #define EXTI_PR_PR14_Pos (14U) |
||
| 3047 | #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ |
||
| 3048 | #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ |
||
| 3049 | #define EXTI_PR_PR15_Pos (15U) |
||
| 3050 | #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ |
||
| 3051 | #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ |
||
| 3052 | #define EXTI_PR_PR16_Pos (16U) |
||
| 3053 | #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ |
||
| 3054 | #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ |
||
| 3055 | #define EXTI_PR_PR17_Pos (17U) |
||
| 3056 | #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ |
||
| 3057 | #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ |
||
| 3058 | |||
| 3059 | /* References Defines */ |
||
| 3060 | #define EXTI_PR_PIF0 EXTI_PR_PR0 |
||
| 3061 | #define EXTI_PR_PIF1 EXTI_PR_PR1 |
||
| 3062 | #define EXTI_PR_PIF2 EXTI_PR_PR2 |
||
| 3063 | #define EXTI_PR_PIF3 EXTI_PR_PR3 |
||
| 3064 | #define EXTI_PR_PIF4 EXTI_PR_PR4 |
||
| 3065 | #define EXTI_PR_PIF5 EXTI_PR_PR5 |
||
| 3066 | #define EXTI_PR_PIF6 EXTI_PR_PR6 |
||
| 3067 | #define EXTI_PR_PIF7 EXTI_PR_PR7 |
||
| 3068 | #define EXTI_PR_PIF8 EXTI_PR_PR8 |
||
| 3069 | #define EXTI_PR_PIF9 EXTI_PR_PR9 |
||
| 3070 | #define EXTI_PR_PIF10 EXTI_PR_PR10 |
||
| 3071 | #define EXTI_PR_PIF11 EXTI_PR_PR11 |
||
| 3072 | #define EXTI_PR_PIF12 EXTI_PR_PR12 |
||
| 3073 | #define EXTI_PR_PIF13 EXTI_PR_PR13 |
||
| 3074 | #define EXTI_PR_PIF14 EXTI_PR_PR14 |
||
| 3075 | #define EXTI_PR_PIF15 EXTI_PR_PR15 |
||
| 3076 | #define EXTI_PR_PIF16 EXTI_PR_PR16 |
||
| 3077 | #define EXTI_PR_PIF17 EXTI_PR_PR17 |
||
| 3078 | |||
| 3079 | /******************************************************************************/ |
||
| 3080 | /* */ |
||
| 3081 | /* DMA Controller */ |
||
| 3082 | /* */ |
||
| 3083 | /******************************************************************************/ |
||
| 3084 | |||
| 3085 | /******************* Bit definition for DMA_ISR register ********************/ |
||
| 3086 | #define DMA_ISR_GIF1_Pos (0U) |
||
| 3087 | #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ |
||
| 3088 | #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ |
||
| 3089 | #define DMA_ISR_TCIF1_Pos (1U) |
||
| 3090 | #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ |
||
| 3091 | #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ |
||
| 3092 | #define DMA_ISR_HTIF1_Pos (2U) |
||
| 3093 | #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ |
||
| 3094 | #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ |
||
| 3095 | #define DMA_ISR_TEIF1_Pos (3U) |
||
| 3096 | #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ |
||
| 3097 | #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ |
||
| 3098 | #define DMA_ISR_GIF2_Pos (4U) |
||
| 3099 | #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ |
||
| 3100 | #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ |
||
| 3101 | #define DMA_ISR_TCIF2_Pos (5U) |
||
| 3102 | #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ |
||
| 3103 | #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ |
||
| 3104 | #define DMA_ISR_HTIF2_Pos (6U) |
||
| 3105 | #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ |
||
| 3106 | #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ |
||
| 3107 | #define DMA_ISR_TEIF2_Pos (7U) |
||
| 3108 | #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ |
||
| 3109 | #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ |
||
| 3110 | #define DMA_ISR_GIF3_Pos (8U) |
||
| 3111 | #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ |
||
| 3112 | #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ |
||
| 3113 | #define DMA_ISR_TCIF3_Pos (9U) |
||
| 3114 | #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ |
||
| 3115 | #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ |
||
| 3116 | #define DMA_ISR_HTIF3_Pos (10U) |
||
| 3117 | #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ |
||
| 3118 | #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ |
||
| 3119 | #define DMA_ISR_TEIF3_Pos (11U) |
||
| 3120 | #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ |
||
| 3121 | #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ |
||
| 3122 | #define DMA_ISR_GIF4_Pos (12U) |
||
| 3123 | #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ |
||
| 3124 | #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ |
||
| 3125 | #define DMA_ISR_TCIF4_Pos (13U) |
||
| 3126 | #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ |
||
| 3127 | #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ |
||
| 3128 | #define DMA_ISR_HTIF4_Pos (14U) |
||
| 3129 | #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ |
||
| 3130 | #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ |
||
| 3131 | #define DMA_ISR_TEIF4_Pos (15U) |
||
| 3132 | #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ |
||
| 3133 | #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ |
||
| 3134 | #define DMA_ISR_GIF5_Pos (16U) |
||
| 3135 | #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ |
||
| 3136 | #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ |
||
| 3137 | #define DMA_ISR_TCIF5_Pos (17U) |
||
| 3138 | #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ |
||
| 3139 | #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ |
||
| 3140 | #define DMA_ISR_HTIF5_Pos (18U) |
||
| 3141 | #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ |
||
| 3142 | #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ |
||
| 3143 | #define DMA_ISR_TEIF5_Pos (19U) |
||
| 3144 | #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ |
||
| 3145 | #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ |
||
| 3146 | #define DMA_ISR_GIF6_Pos (20U) |
||
| 3147 | #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ |
||
| 3148 | #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ |
||
| 3149 | #define DMA_ISR_TCIF6_Pos (21U) |
||
| 3150 | #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ |
||
| 3151 | #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ |
||
| 3152 | #define DMA_ISR_HTIF6_Pos (22U) |
||
| 3153 | #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ |
||
| 3154 | #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ |
||
| 3155 | #define DMA_ISR_TEIF6_Pos (23U) |
||
| 3156 | #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ |
||
| 3157 | #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ |
||
| 3158 | #define DMA_ISR_GIF7_Pos (24U) |
||
| 3159 | #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ |
||
| 3160 | #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ |
||
| 3161 | #define DMA_ISR_TCIF7_Pos (25U) |
||
| 3162 | #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ |
||
| 3163 | #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ |
||
| 3164 | #define DMA_ISR_HTIF7_Pos (26U) |
||
| 3165 | #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ |
||
| 3166 | #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ |
||
| 3167 | #define DMA_ISR_TEIF7_Pos (27U) |
||
| 3168 | #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ |
||
| 3169 | #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ |
||
| 3170 | |||
| 3171 | /******************* Bit definition for DMA_IFCR register *******************/ |
||
| 3172 | #define DMA_IFCR_CGIF1_Pos (0U) |
||
| 3173 | #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ |
||
| 3174 | #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ |
||
| 3175 | #define DMA_IFCR_CTCIF1_Pos (1U) |
||
| 3176 | #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ |
||
| 3177 | #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ |
||
| 3178 | #define DMA_IFCR_CHTIF1_Pos (2U) |
||
| 3179 | #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ |
||
| 3180 | #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ |
||
| 3181 | #define DMA_IFCR_CTEIF1_Pos (3U) |
||
| 3182 | #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ |
||
| 3183 | #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ |
||
| 3184 | #define DMA_IFCR_CGIF2_Pos (4U) |
||
| 3185 | #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ |
||
| 3186 | #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ |
||
| 3187 | #define DMA_IFCR_CTCIF2_Pos (5U) |
||
| 3188 | #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ |
||
| 3189 | #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ |
||
| 3190 | #define DMA_IFCR_CHTIF2_Pos (6U) |
||
| 3191 | #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ |
||
| 3192 | #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ |
||
| 3193 | #define DMA_IFCR_CTEIF2_Pos (7U) |
||
| 3194 | #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ |
||
| 3195 | #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ |
||
| 3196 | #define DMA_IFCR_CGIF3_Pos (8U) |
||
| 3197 | #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ |
||
| 3198 | #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ |
||
| 3199 | #define DMA_IFCR_CTCIF3_Pos (9U) |
||
| 3200 | #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ |
||
| 3201 | #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ |
||
| 3202 | #define DMA_IFCR_CHTIF3_Pos (10U) |
||
| 3203 | #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ |
||
| 3204 | #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ |
||
| 3205 | #define DMA_IFCR_CTEIF3_Pos (11U) |
||
| 3206 | #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ |
||
| 3207 | #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ |
||
| 3208 | #define DMA_IFCR_CGIF4_Pos (12U) |
||
| 3209 | #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ |
||
| 3210 | #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ |
||
| 3211 | #define DMA_IFCR_CTCIF4_Pos (13U) |
||
| 3212 | #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ |
||
| 3213 | #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ |
||
| 3214 | #define DMA_IFCR_CHTIF4_Pos (14U) |
||
| 3215 | #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ |
||
| 3216 | #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ |
||
| 3217 | #define DMA_IFCR_CTEIF4_Pos (15U) |
||
| 3218 | #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ |
||
| 3219 | #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ |
||
| 3220 | #define DMA_IFCR_CGIF5_Pos (16U) |
||
| 3221 | #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ |
||
| 3222 | #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ |
||
| 3223 | #define DMA_IFCR_CTCIF5_Pos (17U) |
||
| 3224 | #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ |
||
| 3225 | #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ |
||
| 3226 | #define DMA_IFCR_CHTIF5_Pos (18U) |
||
| 3227 | #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ |
||
| 3228 | #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ |
||
| 3229 | #define DMA_IFCR_CTEIF5_Pos (19U) |
||
| 3230 | #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ |
||
| 3231 | #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ |
||
| 3232 | #define DMA_IFCR_CGIF6_Pos (20U) |
||
| 3233 | #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ |
||
| 3234 | #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ |
||
| 3235 | #define DMA_IFCR_CTCIF6_Pos (21U) |
||
| 3236 | #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
||
| 3237 | #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ |
||
| 3238 | #define DMA_IFCR_CHTIF6_Pos (22U) |
||
| 3239 | #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ |
||
| 3240 | #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ |
||
| 3241 | #define DMA_IFCR_CTEIF6_Pos (23U) |
||
| 3242 | #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ |
||
| 3243 | #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ |
||
| 3244 | #define DMA_IFCR_CGIF7_Pos (24U) |
||
| 3245 | #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ |
||
| 3246 | #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ |
||
| 3247 | #define DMA_IFCR_CTCIF7_Pos (25U) |
||
| 3248 | #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ |
||
| 3249 | #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ |
||
| 3250 | #define DMA_IFCR_CHTIF7_Pos (26U) |
||
| 3251 | #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
||
| 3252 | #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ |
||
| 3253 | #define DMA_IFCR_CTEIF7_Pos (27U) |
||
| 3254 | #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ |
||
| 3255 | #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ |
||
| 3256 | |||
| 3257 | /******************* Bit definition for DMA_CCR register *******************/ |
||
| 3258 | #define DMA_CCR_EN_Pos (0U) |
||
| 3259 | #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ |
||
| 3260 | #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ |
||
| 3261 | #define DMA_CCR_TCIE_Pos (1U) |
||
| 3262 | #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ |
||
| 3263 | #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ |
||
| 3264 | #define DMA_CCR_HTIE_Pos (2U) |
||
| 3265 | #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ |
||
| 3266 | #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ |
||
| 3267 | #define DMA_CCR_TEIE_Pos (3U) |
||
| 3268 | #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ |
||
| 3269 | #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ |
||
| 3270 | #define DMA_CCR_DIR_Pos (4U) |
||
| 3271 | #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ |
||
| 3272 | #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ |
||
| 3273 | #define DMA_CCR_CIRC_Pos (5U) |
||
| 3274 | #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ |
||
| 3275 | #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ |
||
| 3276 | #define DMA_CCR_PINC_Pos (6U) |
||
| 3277 | #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ |
||
| 3278 | #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ |
||
| 3279 | #define DMA_CCR_MINC_Pos (7U) |
||
| 3280 | #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ |
||
| 3281 | #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ |
||
| 3282 | |||
| 3283 | #define DMA_CCR_PSIZE_Pos (8U) |
||
| 3284 | #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ |
||
| 3285 | #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ |
||
| 3286 | #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ |
||
| 3287 | #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ |
||
| 3288 | |||
| 3289 | #define DMA_CCR_MSIZE_Pos (10U) |
||
| 3290 | #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ |
||
| 3291 | #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ |
||
| 3292 | #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ |
||
| 3293 | #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ |
||
| 3294 | |||
| 3295 | #define DMA_CCR_PL_Pos (12U) |
||
| 3296 | #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ |
||
| 3297 | #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ |
||
| 3298 | #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ |
||
| 3299 | #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ |
||
| 3300 | |||
| 3301 | #define DMA_CCR_MEM2MEM_Pos (14U) |
||
| 3302 | #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ |
||
| 3303 | #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ |
||
| 3304 | |||
| 3305 | /****************** Bit definition for DMA_CNDTR register ******************/ |
||
| 3306 | #define DMA_CNDTR_NDT_Pos (0U) |
||
| 3307 | #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ |
||
| 3308 | #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ |
||
| 3309 | |||
| 3310 | /****************** Bit definition for DMA_CPAR register *******************/ |
||
| 3311 | #define DMA_CPAR_PA_Pos (0U) |
||
| 3312 | #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
||
| 3313 | #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ |
||
| 3314 | |||
| 3315 | /****************** Bit definition for DMA_CMAR register *******************/ |
||
| 3316 | #define DMA_CMAR_MA_Pos (0U) |
||
| 3317 | #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
||
| 3318 | #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ |
||
| 3319 | |||
| 3320 | /******************************************************************************/ |
||
| 3321 | /* */ |
||
| 3322 | /* Analog to Digital Converter (ADC) */ |
||
| 3323 | /* */ |
||
| 3324 | /******************************************************************************/ |
||
| 3325 | |||
| 3326 | /* |
||
| 3327 | * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) |
||
| 3328 | */ |
||
| 3329 | /* Note: No specific macro feature on this device */ |
||
| 3330 | |||
| 3331 | /******************** Bit definition for ADC_SR register ********************/ |
||
| 3332 | #define ADC_SR_AWD_Pos (0U) |
||
| 3333 | #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ |
||
| 3334 | #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ |
||
| 3335 | #define ADC_SR_EOS_Pos (1U) |
||
| 3336 | #define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ |
||
| 3337 | #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ |
||
| 3338 | #define ADC_SR_JEOS_Pos (2U) |
||
| 3339 | #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ |
||
| 3340 | #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ |
||
| 3341 | #define ADC_SR_JSTRT_Pos (3U) |
||
| 3342 | #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ |
||
| 3343 | #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ |
||
| 3344 | #define ADC_SR_STRT_Pos (4U) |
||
| 3345 | #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ |
||
| 3346 | #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ |
||
| 3347 | |||
| 3348 | /* Legacy defines */ |
||
| 3349 | #define ADC_SR_EOC (ADC_SR_EOS) |
||
| 3350 | #define ADC_SR_JEOC (ADC_SR_JEOS) |
||
| 3351 | |||
| 3352 | /******************* Bit definition for ADC_CR1 register ********************/ |
||
| 3353 | #define ADC_CR1_AWDCH_Pos (0U) |
||
| 3354 | #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ |
||
| 3355 | #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
||
| 3356 | #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ |
||
| 3357 | #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ |
||
| 3358 | #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ |
||
| 3359 | #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ |
||
| 3360 | #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ |
||
| 3361 | |||
| 3362 | #define ADC_CR1_EOSIE_Pos (5U) |
||
| 3363 | #define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ |
||
| 3364 | #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ |
||
| 3365 | #define ADC_CR1_AWDIE_Pos (6U) |
||
| 3366 | #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ |
||
| 3367 | #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ |
||
| 3368 | #define ADC_CR1_JEOSIE_Pos (7U) |
||
| 3369 | #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ |
||
| 3370 | #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ |
||
| 3371 | #define ADC_CR1_SCAN_Pos (8U) |
||
| 3372 | #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ |
||
| 3373 | #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ |
||
| 3374 | #define ADC_CR1_AWDSGL_Pos (9U) |
||
| 3375 | #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ |
||
| 3376 | #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
||
| 3377 | #define ADC_CR1_JAUTO_Pos (10U) |
||
| 3378 | #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ |
||
| 3379 | #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ |
||
| 3380 | #define ADC_CR1_DISCEN_Pos (11U) |
||
| 3381 | #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ |
||
| 3382 | #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
||
| 3383 | #define ADC_CR1_JDISCEN_Pos (12U) |
||
| 3384 | #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ |
||
| 3385 | #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ |
||
| 3386 | |||
| 3387 | #define ADC_CR1_DISCNUM_Pos (13U) |
||
| 3388 | #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ |
||
| 3389 | #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ |
||
| 3390 | #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ |
||
| 3391 | #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ |
||
| 3392 | #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ |
||
| 3393 | |||
| 3394 | #define ADC_CR1_JAWDEN_Pos (22U) |
||
| 3395 | #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ |
||
| 3396 | #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ |
||
| 3397 | #define ADC_CR1_AWDEN_Pos (23U) |
||
| 3398 | #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ |
||
| 3399 | #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
||
| 3400 | |||
| 3401 | /* Legacy defines */ |
||
| 3402 | #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) |
||
| 3403 | #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) |
||
| 3404 | |||
| 3405 | /******************* Bit definition for ADC_CR2 register ********************/ |
||
| 3406 | #define ADC_CR2_ADON_Pos (0U) |
||
| 3407 | #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ |
||
| 3408 | #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ |
||
| 3409 | #define ADC_CR2_CONT_Pos (1U) |
||
| 3410 | #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ |
||
| 3411 | #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
||
| 3412 | #define ADC_CR2_CAL_Pos (2U) |
||
| 3413 | #define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ |
||
| 3414 | #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ |
||
| 3415 | #define ADC_CR2_RSTCAL_Pos (3U) |
||
| 3416 | #define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ |
||
| 3417 | #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ |
||
| 3418 | #define ADC_CR2_DMA_Pos (8U) |
||
| 3419 | #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ |
||
| 3420 | #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ |
||
| 3421 | #define ADC_CR2_ALIGN_Pos (11U) |
||
| 3422 | #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ |
||
| 3423 | #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ |
||
| 3424 | |||
| 3425 | #define ADC_CR2_JEXTSEL_Pos (12U) |
||
| 3426 | #define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ |
||
| 3427 | #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ |
||
| 3428 | #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ |
||
| 3429 | #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ |
||
| 3430 | #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ |
||
| 3431 | |||
| 3432 | #define ADC_CR2_JEXTTRIG_Pos (15U) |
||
| 3433 | #define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ |
||
| 3434 | #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ |
||
| 3435 | |||
| 3436 | #define ADC_CR2_EXTSEL_Pos (17U) |
||
| 3437 | #define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ |
||
| 3438 | #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
||
| 3439 | #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ |
||
| 3440 | #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ |
||
| 3441 | #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ |
||
| 3442 | |||
| 3443 | #define ADC_CR2_EXTTRIG_Pos (20U) |
||
| 3444 | #define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ |
||
| 3445 | #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ |
||
| 3446 | #define ADC_CR2_JSWSTART_Pos (21U) |
||
| 3447 | #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ |
||
| 3448 | #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ |
||
| 3449 | #define ADC_CR2_SWSTART_Pos (22U) |
||
| 3450 | #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ |
||
| 3451 | #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ |
||
| 3452 | #define ADC_CR2_TSVREFE_Pos (23U) |
||
| 3453 | #define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ |
||
| 3454 | #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ |
||
| 3455 | |||
| 3456 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
||
| 3457 | #define ADC_SMPR1_SMP10_Pos (0U) |
||
| 3458 | #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ |
||
| 3459 | #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ |
||
| 3460 | #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ |
||
| 3461 | #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ |
||
| 3462 | #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ |
||
| 3463 | |||
| 3464 | #define ADC_SMPR1_SMP11_Pos (3U) |
||
| 3465 | #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ |
||
| 3466 | #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ |
||
| 3467 | #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ |
||
| 3468 | #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ |
||
| 3469 | #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ |
||
| 3470 | |||
| 3471 | #define ADC_SMPR1_SMP12_Pos (6U) |
||
| 3472 | #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ |
||
| 3473 | #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ |
||
| 3474 | #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ |
||
| 3475 | #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ |
||
| 3476 | #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ |
||
| 3477 | |||
| 3478 | #define ADC_SMPR1_SMP13_Pos (9U) |
||
| 3479 | #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ |
||
| 3480 | #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ |
||
| 3481 | #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ |
||
| 3482 | #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ |
||
| 3483 | #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ |
||
| 3484 | |||
| 3485 | #define ADC_SMPR1_SMP14_Pos (12U) |
||
| 3486 | #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ |
||
| 3487 | #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ |
||
| 3488 | #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ |
||
| 3489 | #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ |
||
| 3490 | #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ |
||
| 3491 | |||
| 3492 | #define ADC_SMPR1_SMP15_Pos (15U) |
||
| 3493 | #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ |
||
| 3494 | #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ |
||
| 3495 | #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ |
||
| 3496 | #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ |
||
| 3497 | #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ |
||
| 3498 | |||
| 3499 | #define ADC_SMPR1_SMP16_Pos (18U) |
||
| 3500 | #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ |
||
| 3501 | #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ |
||
| 3502 | #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ |
||
| 3503 | #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ |
||
| 3504 | #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ |
||
| 3505 | |||
| 3506 | #define ADC_SMPR1_SMP17_Pos (21U) |
||
| 3507 | #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ |
||
| 3508 | #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ |
||
| 3509 | #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ |
||
| 3510 | #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ |
||
| 3511 | #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ |
||
| 3512 | |||
| 3513 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
||
| 3514 | #define ADC_SMPR2_SMP0_Pos (0U) |
||
| 3515 | #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ |
||
| 3516 | #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ |
||
| 3517 | #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ |
||
| 3518 | #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ |
||
| 3519 | #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ |
||
| 3520 | |||
| 3521 | #define ADC_SMPR2_SMP1_Pos (3U) |
||
| 3522 | #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ |
||
| 3523 | #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ |
||
| 3524 | #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ |
||
| 3525 | #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ |
||
| 3526 | #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ |
||
| 3527 | |||
| 3528 | #define ADC_SMPR2_SMP2_Pos (6U) |
||
| 3529 | #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ |
||
| 3530 | #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ |
||
| 3531 | #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ |
||
| 3532 | #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ |
||
| 3533 | #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ |
||
| 3534 | |||
| 3535 | #define ADC_SMPR2_SMP3_Pos (9U) |
||
| 3536 | #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ |
||
| 3537 | #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ |
||
| 3538 | #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ |
||
| 3539 | #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ |
||
| 3540 | #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ |
||
| 3541 | |||
| 3542 | #define ADC_SMPR2_SMP4_Pos (12U) |
||
| 3543 | #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ |
||
| 3544 | #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ |
||
| 3545 | #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ |
||
| 3546 | #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ |
||
| 3547 | #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ |
||
| 3548 | |||
| 3549 | #define ADC_SMPR2_SMP5_Pos (15U) |
||
| 3550 | #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ |
||
| 3551 | #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ |
||
| 3552 | #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ |
||
| 3553 | #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ |
||
| 3554 | #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ |
||
| 3555 | |||
| 3556 | #define ADC_SMPR2_SMP6_Pos (18U) |
||
| 3557 | #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ |
||
| 3558 | #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ |
||
| 3559 | #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ |
||
| 3560 | #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ |
||
| 3561 | #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ |
||
| 3562 | |||
| 3563 | #define ADC_SMPR2_SMP7_Pos (21U) |
||
| 3564 | #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ |
||
| 3565 | #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ |
||
| 3566 | #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ |
||
| 3567 | #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ |
||
| 3568 | #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ |
||
| 3569 | |||
| 3570 | #define ADC_SMPR2_SMP8_Pos (24U) |
||
| 3571 | #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ |
||
| 3572 | #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ |
||
| 3573 | #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ |
||
| 3574 | #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ |
||
| 3575 | #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ |
||
| 3576 | |||
| 3577 | #define ADC_SMPR2_SMP9_Pos (27U) |
||
| 3578 | #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ |
||
| 3579 | #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ |
||
| 3580 | #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ |
||
| 3581 | #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ |
||
| 3582 | #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ |
||
| 3583 | |||
| 3584 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
||
| 3585 | #define ADC_JOFR1_JOFFSET1_Pos (0U) |
||
| 3586 | #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ |
||
| 3587 | #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ |
||
| 3588 | |||
| 3589 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
||
| 3590 | #define ADC_JOFR2_JOFFSET2_Pos (0U) |
||
| 3591 | #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ |
||
| 3592 | #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ |
||
| 3593 | |||
| 3594 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
||
| 3595 | #define ADC_JOFR3_JOFFSET3_Pos (0U) |
||
| 3596 | #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ |
||
| 3597 | #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ |
||
| 3598 | |||
| 3599 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
||
| 3600 | #define ADC_JOFR4_JOFFSET4_Pos (0U) |
||
| 3601 | #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ |
||
| 3602 | #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ |
||
| 3603 | |||
| 3604 | /******************* Bit definition for ADC_HTR register ********************/ |
||
| 3605 | #define ADC_HTR_HT_Pos (0U) |
||
| 3606 | #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ |
||
| 3607 | #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ |
||
| 3608 | |||
| 3609 | /******************* Bit definition for ADC_LTR register ********************/ |
||
| 3610 | #define ADC_LTR_LT_Pos (0U) |
||
| 3611 | #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ |
||
| 3612 | #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ |
||
| 3613 | |||
| 3614 | /******************* Bit definition for ADC_SQR1 register *******************/ |
||
| 3615 | #define ADC_SQR1_SQ13_Pos (0U) |
||
| 3616 | #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ |
||
| 3617 | #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ |
||
| 3618 | #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ |
||
| 3619 | #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ |
||
| 3620 | #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ |
||
| 3621 | #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ |
||
| 3622 | #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ |
||
| 3623 | |||
| 3624 | #define ADC_SQR1_SQ14_Pos (5U) |
||
| 3625 | #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ |
||
| 3626 | #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ |
||
| 3627 | #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ |
||
| 3628 | #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ |
||
| 3629 | #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ |
||
| 3630 | #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ |
||
| 3631 | #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ |
||
| 3632 | |||
| 3633 | #define ADC_SQR1_SQ15_Pos (10U) |
||
| 3634 | #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ |
||
| 3635 | #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ |
||
| 3636 | #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ |
||
| 3637 | #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ |
||
| 3638 | #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ |
||
| 3639 | #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ |
||
| 3640 | #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ |
||
| 3641 | |||
| 3642 | #define ADC_SQR1_SQ16_Pos (15U) |
||
| 3643 | #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ |
||
| 3644 | #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ |
||
| 3645 | #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ |
||
| 3646 | #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ |
||
| 3647 | #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ |
||
| 3648 | #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ |
||
| 3649 | #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ |
||
| 3650 | |||
| 3651 | #define ADC_SQR1_L_Pos (20U) |
||
| 3652 | #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ |
||
| 3653 | #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ |
||
| 3654 | #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ |
||
| 3655 | #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ |
||
| 3656 | #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ |
||
| 3657 | #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ |
||
| 3658 | |||
| 3659 | /******************* Bit definition for ADC_SQR2 register *******************/ |
||
| 3660 | #define ADC_SQR2_SQ7_Pos (0U) |
||
| 3661 | #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ |
||
| 3662 | #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ |
||
| 3663 | #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ |
||
| 3664 | #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ |
||
| 3665 | #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ |
||
| 3666 | #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ |
||
| 3667 | #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ |
||
| 3668 | |||
| 3669 | #define ADC_SQR2_SQ8_Pos (5U) |
||
| 3670 | #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ |
||
| 3671 | #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ |
||
| 3672 | #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ |
||
| 3673 | #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ |
||
| 3674 | #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ |
||
| 3675 | #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ |
||
| 3676 | #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ |
||
| 3677 | |||
| 3678 | #define ADC_SQR2_SQ9_Pos (10U) |
||
| 3679 | #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ |
||
| 3680 | #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ |
||
| 3681 | #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ |
||
| 3682 | #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ |
||
| 3683 | #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ |
||
| 3684 | #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ |
||
| 3685 | #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ |
||
| 3686 | |||
| 3687 | #define ADC_SQR2_SQ10_Pos (15U) |
||
| 3688 | #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ |
||
| 3689 | #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ |
||
| 3690 | #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ |
||
| 3691 | #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ |
||
| 3692 | #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ |
||
| 3693 | #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ |
||
| 3694 | #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ |
||
| 3695 | |||
| 3696 | #define ADC_SQR2_SQ11_Pos (20U) |
||
| 3697 | #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ |
||
| 3698 | #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ |
||
| 3699 | #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ |
||
| 3700 | #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ |
||
| 3701 | #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ |
||
| 3702 | #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ |
||
| 3703 | #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ |
||
| 3704 | |||
| 3705 | #define ADC_SQR2_SQ12_Pos (25U) |
||
| 3706 | #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ |
||
| 3707 | #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ |
||
| 3708 | #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ |
||
| 3709 | #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ |
||
| 3710 | #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ |
||
| 3711 | #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ |
||
| 3712 | #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ |
||
| 3713 | |||
| 3714 | /******************* Bit definition for ADC_SQR3 register *******************/ |
||
| 3715 | #define ADC_SQR3_SQ1_Pos (0U) |
||
| 3716 | #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ |
||
| 3717 | #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ |
||
| 3718 | #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ |
||
| 3719 | #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ |
||
| 3720 | #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ |
||
| 3721 | #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ |
||
| 3722 | #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ |
||
| 3723 | |||
| 3724 | #define ADC_SQR3_SQ2_Pos (5U) |
||
| 3725 | #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ |
||
| 3726 | #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ |
||
| 3727 | #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ |
||
| 3728 | #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ |
||
| 3729 | #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ |
||
| 3730 | #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ |
||
| 3731 | #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ |
||
| 3732 | |||
| 3733 | #define ADC_SQR3_SQ3_Pos (10U) |
||
| 3734 | #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ |
||
| 3735 | #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ |
||
| 3736 | #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ |
||
| 3737 | #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ |
||
| 3738 | #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ |
||
| 3739 | #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ |
||
| 3740 | #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ |
||
| 3741 | |||
| 3742 | #define ADC_SQR3_SQ4_Pos (15U) |
||
| 3743 | #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ |
||
| 3744 | #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ |
||
| 3745 | #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ |
||
| 3746 | #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ |
||
| 3747 | #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ |
||
| 3748 | #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ |
||
| 3749 | #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ |
||
| 3750 | |||
| 3751 | #define ADC_SQR3_SQ5_Pos (20U) |
||
| 3752 | #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ |
||
| 3753 | #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ |
||
| 3754 | #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ |
||
| 3755 | #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ |
||
| 3756 | #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ |
||
| 3757 | #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ |
||
| 3758 | #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ |
||
| 3759 | |||
| 3760 | #define ADC_SQR3_SQ6_Pos (25U) |
||
| 3761 | #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ |
||
| 3762 | #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ |
||
| 3763 | #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ |
||
| 3764 | #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ |
||
| 3765 | #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ |
||
| 3766 | #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ |
||
| 3767 | #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ |
||
| 3768 | |||
| 3769 | /******************* Bit definition for ADC_JSQR register *******************/ |
||
| 3770 | #define ADC_JSQR_JSQ1_Pos (0U) |
||
| 3771 | #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ |
||
| 3772 | #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ |
||
| 3773 | #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ |
||
| 3774 | #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ |
||
| 3775 | #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ |
||
| 3776 | #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ |
||
| 3777 | #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ |
||
| 3778 | |||
| 3779 | #define ADC_JSQR_JSQ2_Pos (5U) |
||
| 3780 | #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ |
||
| 3781 | #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ |
||
| 3782 | #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ |
||
| 3783 | #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ |
||
| 3784 | #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ |
||
| 3785 | #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ |
||
| 3786 | #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ |
||
| 3787 | |||
| 3788 | #define ADC_JSQR_JSQ3_Pos (10U) |
||
| 3789 | #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ |
||
| 3790 | #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ |
||
| 3791 | #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ |
||
| 3792 | #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ |
||
| 3793 | #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ |
||
| 3794 | #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ |
||
| 3795 | #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ |
||
| 3796 | |||
| 3797 | #define ADC_JSQR_JSQ4_Pos (15U) |
||
| 3798 | #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ |
||
| 3799 | #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ |
||
| 3800 | #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ |
||
| 3801 | #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ |
||
| 3802 | #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ |
||
| 3803 | #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ |
||
| 3804 | #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ |
||
| 3805 | |||
| 3806 | #define ADC_JSQR_JL_Pos (20U) |
||
| 3807 | #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ |
||
| 3808 | #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ |
||
| 3809 | #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ |
||
| 3810 | #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ |
||
| 3811 | |||
| 3812 | /******************* Bit definition for ADC_JDR1 register *******************/ |
||
| 3813 | #define ADC_JDR1_JDATA_Pos (0U) |
||
| 3814 | #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
||
| 3815 | #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ |
||
| 3816 | |||
| 3817 | /******************* Bit definition for ADC_JDR2 register *******************/ |
||
| 3818 | #define ADC_JDR2_JDATA_Pos (0U) |
||
| 3819 | #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
||
| 3820 | #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ |
||
| 3821 | |||
| 3822 | /******************* Bit definition for ADC_JDR3 register *******************/ |
||
| 3823 | #define ADC_JDR3_JDATA_Pos (0U) |
||
| 3824 | #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ |
||
| 3825 | #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ |
||
| 3826 | |||
| 3827 | /******************* Bit definition for ADC_JDR4 register *******************/ |
||
| 3828 | #define ADC_JDR4_JDATA_Pos (0U) |
||
| 3829 | #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ |
||
| 3830 | #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ |
||
| 3831 | |||
| 3832 | /******************** Bit definition for ADC_DR register ********************/ |
||
| 3833 | #define ADC_DR_DATA_Pos (0U) |
||
| 3834 | #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
||
| 3835 | #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ |
||
| 3836 | /******************************************************************************/ |
||
| 3837 | /* */ |
||
| 3838 | /* Digital to Analog Converter */ |
||
| 3839 | /* */ |
||
| 3840 | /******************************************************************************/ |
||
| 3841 | |||
| 3842 | /******************** Bit definition for DAC_CR register ********************/ |
||
| 3843 | #define DAC_CR_EN1_Pos (0U) |
||
| 3844 | #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ |
||
| 3845 | #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ |
||
| 3846 | #define DAC_CR_BOFF1_Pos (1U) |
||
| 3847 | #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ |
||
| 3848 | #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ |
||
| 3849 | #define DAC_CR_TEN1_Pos (2U) |
||
| 3850 | #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ |
||
| 3851 | #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ |
||
| 3852 | |||
| 3853 | #define DAC_CR_TSEL1_Pos (3U) |
||
| 3854 | #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ |
||
| 3855 | #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ |
||
| 3856 | #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ |
||
| 3857 | #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ |
||
| 3858 | #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ |
||
| 3859 | |||
| 3860 | #define DAC_CR_WAVE1_Pos (6U) |
||
| 3861 | #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ |
||
| 3862 | #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
||
| 3863 | #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ |
||
| 3864 | #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ |
||
| 3865 | |||
| 3866 | #define DAC_CR_MAMP1_Pos (8U) |
||
| 3867 | #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ |
||
| 3868 | #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
||
| 3869 | #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ |
||
| 3870 | #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ |
||
| 3871 | #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ |
||
| 3872 | #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ |
||
| 3873 | |||
| 3874 | #define DAC_CR_DMAEN1_Pos (12U) |
||
| 3875 | #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ |
||
| 3876 | #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ |
||
| 3877 | #define DAC_CR_EN2_Pos (16U) |
||
| 3878 | #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ |
||
| 3879 | #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ |
||
| 3880 | #define DAC_CR_BOFF2_Pos (17U) |
||
| 3881 | #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ |
||
| 3882 | #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ |
||
| 3883 | #define DAC_CR_TEN2_Pos (18U) |
||
| 3884 | #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ |
||
| 3885 | #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ |
||
| 3886 | |||
| 3887 | #define DAC_CR_TSEL2_Pos (19U) |
||
| 3888 | #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ |
||
| 3889 | #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ |
||
| 3890 | #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ |
||
| 3891 | #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ |
||
| 3892 | #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ |
||
| 3893 | |||
| 3894 | #define DAC_CR_WAVE2_Pos (22U) |
||
| 3895 | #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ |
||
| 3896 | #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
||
| 3897 | #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ |
||
| 3898 | #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ |
||
| 3899 | |||
| 3900 | #define DAC_CR_MAMP2_Pos (24U) |
||
| 3901 | #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ |
||
| 3902 | #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
||
| 3903 | #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ |
||
| 3904 | #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ |
||
| 3905 | #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ |
||
| 3906 | #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ |
||
| 3907 | |||
| 3908 | #define DAC_CR_DMAEN2_Pos (28U) |
||
| 3909 | #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ |
||
| 3910 | #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ |
||
| 3911 | |||
| 3912 | #define DAC_CR_DMAUDRIE1_Pos (13U) |
||
| 3913 | #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ |
||
| 3914 | #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun interrupt enable */ |
||
| 3915 | #define DAC_CR_DMAUDRIE2_Pos (29U) |
||
| 3916 | #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ |
||
| 3917 | #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun interrupt enable */ |
||
| 3918 | |||
| 3919 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
||
| 3920 | #define DAC_SWTRIGR_SWTRIG1_Pos (0U) |
||
| 3921 | #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ |
||
| 3922 | #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ |
||
| 3923 | #define DAC_SWTRIGR_SWTRIG2_Pos (1U) |
||
| 3924 | #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ |
||
| 3925 | #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ |
||
| 3926 | |||
| 3927 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
||
| 3928 | #define DAC_DHR12R1_DACC1DHR_Pos (0U) |
||
| 3929 | #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ |
||
| 3930 | #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ |
||
| 3931 | |||
| 3932 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
||
| 3933 | #define DAC_DHR12L1_DACC1DHR_Pos (4U) |
||
| 3934 | #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
||
| 3935 | #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ |
||
| 3936 | |||
| 3937 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
||
| 3938 | #define DAC_DHR8R1_DACC1DHR_Pos (0U) |
||
| 3939 | #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ |
||
| 3940 | #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ |
||
| 3941 | |||
| 3942 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
||
| 3943 | #define DAC_DHR12R2_DACC2DHR_Pos (0U) |
||
| 3944 | #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ |
||
| 3945 | #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ |
||
| 3946 | |||
| 3947 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
||
| 3948 | #define DAC_DHR12L2_DACC2DHR_Pos (4U) |
||
| 3949 | #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ |
||
| 3950 | #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ |
||
| 3951 | |||
| 3952 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
||
| 3953 | #define DAC_DHR8R2_DACC2DHR_Pos (0U) |
||
| 3954 | #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ |
||
| 3955 | #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ |
||
| 3956 | |||
| 3957 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
||
| 3958 | #define DAC_DHR12RD_DACC1DHR_Pos (0U) |
||
| 3959 | #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ |
||
| 3960 | #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ |
||
| 3961 | #define DAC_DHR12RD_DACC2DHR_Pos (16U) |
||
| 3962 | #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ |
||
| 3963 | #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ |
||
| 3964 | |||
| 3965 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
||
| 3966 | #define DAC_DHR12LD_DACC1DHR_Pos (4U) |
||
| 3967 | #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
||
| 3968 | #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ |
||
| 3969 | #define DAC_DHR12LD_DACC2DHR_Pos (20U) |
||
| 3970 | #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ |
||
| 3971 | #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ |
||
| 3972 | |||
| 3973 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
||
| 3974 | #define DAC_DHR8RD_DACC1DHR_Pos (0U) |
||
| 3975 | #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ |
||
| 3976 | #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ |
||
| 3977 | #define DAC_DHR8RD_DACC2DHR_Pos (8U) |
||
| 3978 | #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ |
||
| 3979 | #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ |
||
| 3980 | |||
| 3981 | /******************* Bit definition for DAC_DOR1 register *******************/ |
||
| 3982 | #define DAC_DOR1_DACC1DOR_Pos (0U) |
||
| 3983 | #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ |
||
| 3984 | #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ |
||
| 3985 | |||
| 3986 | /******************* Bit definition for DAC_DOR2 register *******************/ |
||
| 3987 | #define DAC_DOR2_DACC2DOR_Pos (0U) |
||
| 3988 | #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ |
||
| 3989 | #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ |
||
| 3990 | |||
| 3991 | /******************** Bit definition for DAC_SR register ********************/ |
||
| 3992 | #define DAC_SR_DMAUDR1_Pos (13U) |
||
| 3993 | #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ |
||
| 3994 | #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ |
||
| 3995 | #define DAC_SR_DMAUDR2_Pos (29U) |
||
| 3996 | #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ |
||
| 3997 | #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ |
||
| 3998 | |||
| 3999 | /******************************************************************************/ |
||
| 4000 | /* */ |
||
| 4001 | /* CEC */ |
||
| 4002 | /* */ |
||
| 4003 | /******************************************************************************/ |
||
| 4004 | /******************** Bit definition for CEC_CFGR register ******************/ |
||
| 4005 | #define CEC_CFGR_PE_Pos (0U) |
||
| 4006 | #define CEC_CFGR_PE_Msk (0x1U << CEC_CFGR_PE_Pos) /*!< 0x00000001 */ |
||
| 4007 | #define CEC_CFGR_PE CEC_CFGR_PE_Msk /*!< Peripheral Enable */ |
||
| 4008 | #define CEC_CFGR_IE_Pos (1U) |
||
| 4009 | #define CEC_CFGR_IE_Msk (0x1U << CEC_CFGR_IE_Pos) /*!< 0x00000002 */ |
||
| 4010 | #define CEC_CFGR_IE CEC_CFGR_IE_Msk /*!< Interrupt Enable */ |
||
| 4011 | #define CEC_CFGR_BTEM_Pos (2U) |
||
| 4012 | #define CEC_CFGR_BTEM_Msk (0x1U << CEC_CFGR_BTEM_Pos) /*!< 0x00000004 */ |
||
| 4013 | #define CEC_CFGR_BTEM CEC_CFGR_BTEM_Msk /*!< Bit Timing Error Mode */ |
||
| 4014 | #define CEC_CFGR_BPEM_Pos (3U) |
||
| 4015 | #define CEC_CFGR_BPEM_Msk (0x1U << CEC_CFGR_BPEM_Pos) /*!< 0x00000008 */ |
||
| 4016 | #define CEC_CFGR_BPEM CEC_CFGR_BPEM_Msk /*!< Bit Period Error Mode */ |
||
| 4017 | |||
| 4018 | /******************** Bit definition for CEC_OAR register ******************/ |
||
| 4019 | #define CEC_OAR_OA_Pos (0U) |
||
| 4020 | #define CEC_OAR_OA_Msk (0xFU << CEC_OAR_OA_Pos) /*!< 0x0000000F */ |
||
| 4021 | #define CEC_OAR_OA CEC_OAR_OA_Msk /*!< OA[3:0]: Own Address */ |
||
| 4022 | #define CEC_OAR_OA_0 (0x1U << CEC_OAR_OA_Pos) /*!< 0x00000001 */ |
||
| 4023 | #define CEC_OAR_OA_1 (0x2U << CEC_OAR_OA_Pos) /*!< 0x00000002 */ |
||
| 4024 | #define CEC_OAR_OA_2 (0x4U << CEC_OAR_OA_Pos) /*!< 0x00000004 */ |
||
| 4025 | #define CEC_OAR_OA_3 (0x8U << CEC_OAR_OA_Pos) /*!< 0x00000008 */ |
||
| 4026 | |||
| 4027 | /******************** Bit definition for CEC_PRES register ******************/ |
||
| 4028 | #define CEC_PRES_PRES_Pos (0U) |
||
| 4029 | #define CEC_PRES_PRES_Msk (0x3FFFU << CEC_PRES_PRES_Pos) /*!< 0x00003FFF */ |
||
| 4030 | #define CEC_PRES_PRES CEC_PRES_PRES_Msk /*!< Prescaler Counter Value */ |
||
| 4031 | |||
| 4032 | /******************** Bit definition for CEC_ESR register ******************/ |
||
| 4033 | #define CEC_ESR_BTE_Pos (0U) |
||
| 4034 | #define CEC_ESR_BTE_Msk (0x1U << CEC_ESR_BTE_Pos) /*!< 0x00000001 */ |
||
| 4035 | #define CEC_ESR_BTE CEC_ESR_BTE_Msk /*!< Bit Timing Error */ |
||
| 4036 | #define CEC_ESR_BPE_Pos (1U) |
||
| 4037 | #define CEC_ESR_BPE_Msk (0x1U << CEC_ESR_BPE_Pos) /*!< 0x00000002 */ |
||
| 4038 | #define CEC_ESR_BPE CEC_ESR_BPE_Msk /*!< Bit Period Error */ |
||
| 4039 | #define CEC_ESR_RBTFE_Pos (2U) |
||
| 4040 | #define CEC_ESR_RBTFE_Msk (0x1U << CEC_ESR_RBTFE_Pos) /*!< 0x00000004 */ |
||
| 4041 | #define CEC_ESR_RBTFE CEC_ESR_RBTFE_Msk /*!< Rx Block Transfer Finished Error */ |
||
| 4042 | #define CEC_ESR_SBE_Pos (3U) |
||
| 4043 | #define CEC_ESR_SBE_Msk (0x1U << CEC_ESR_SBE_Pos) /*!< 0x00000008 */ |
||
| 4044 | #define CEC_ESR_SBE CEC_ESR_SBE_Msk /*!< Start Bit Error */ |
||
| 4045 | #define CEC_ESR_ACKE_Pos (4U) |
||
| 4046 | #define CEC_ESR_ACKE_Msk (0x1U << CEC_ESR_ACKE_Pos) /*!< 0x00000010 */ |
||
| 4047 | #define CEC_ESR_ACKE CEC_ESR_ACKE_Msk /*!< Block Acknowledge Error */ |
||
| 4048 | #define CEC_ESR_LINE_Pos (5U) |
||
| 4049 | #define CEC_ESR_LINE_Msk (0x1U << CEC_ESR_LINE_Pos) /*!< 0x00000020 */ |
||
| 4050 | #define CEC_ESR_LINE CEC_ESR_LINE_Msk /*!< Line Error */ |
||
| 4051 | #define CEC_ESR_TBTFE_Pos (6U) |
||
| 4052 | #define CEC_ESR_TBTFE_Msk (0x1U << CEC_ESR_TBTFE_Pos) /*!< 0x00000040 */ |
||
| 4053 | #define CEC_ESR_TBTFE CEC_ESR_TBTFE_Msk /*!< Tx Block Transfer Finished Error */ |
||
| 4054 | |||
| 4055 | /******************** Bit definition for CEC_CSR register ******************/ |
||
| 4056 | #define CEC_CSR_TSOM_Pos (0U) |
||
| 4057 | #define CEC_CSR_TSOM_Msk (0x1U << CEC_CSR_TSOM_Pos) /*!< 0x00000001 */ |
||
| 4058 | #define CEC_CSR_TSOM CEC_CSR_TSOM_Msk /*!< Tx Start Of Message */ |
||
| 4059 | #define CEC_CSR_TEOM_Pos (1U) |
||
| 4060 | #define CEC_CSR_TEOM_Msk (0x1U << CEC_CSR_TEOM_Pos) /*!< 0x00000002 */ |
||
| 4061 | #define CEC_CSR_TEOM CEC_CSR_TEOM_Msk /*!< Tx End Of Message */ |
||
| 4062 | #define CEC_CSR_TERR_Pos (2U) |
||
| 4063 | #define CEC_CSR_TERR_Msk (0x1U << CEC_CSR_TERR_Pos) /*!< 0x00000004 */ |
||
| 4064 | #define CEC_CSR_TERR CEC_CSR_TERR_Msk /*!< Tx Error */ |
||
| 4065 | #define CEC_CSR_TBTRF_Pos (3U) |
||
| 4066 | #define CEC_CSR_TBTRF_Msk (0x1U << CEC_CSR_TBTRF_Pos) /*!< 0x00000008 */ |
||
| 4067 | #define CEC_CSR_TBTRF CEC_CSR_TBTRF_Msk /*!< Tx Byte Transfer Request or Block Transfer Finished */ |
||
| 4068 | #define CEC_CSR_RSOM_Pos (4U) |
||
| 4069 | #define CEC_CSR_RSOM_Msk (0x1U << CEC_CSR_RSOM_Pos) /*!< 0x00000010 */ |
||
| 4070 | #define CEC_CSR_RSOM CEC_CSR_RSOM_Msk /*!< Rx Start Of Message */ |
||
| 4071 | #define CEC_CSR_REOM_Pos (5U) |
||
| 4072 | #define CEC_CSR_REOM_Msk (0x1U << CEC_CSR_REOM_Pos) /*!< 0x00000020 */ |
||
| 4073 | #define CEC_CSR_REOM CEC_CSR_REOM_Msk /*!< Rx End Of Message */ |
||
| 4074 | #define CEC_CSR_RERR_Pos (6U) |
||
| 4075 | #define CEC_CSR_RERR_Msk (0x1U << CEC_CSR_RERR_Pos) /*!< 0x00000040 */ |
||
| 4076 | #define CEC_CSR_RERR CEC_CSR_RERR_Msk /*!< Rx Error */ |
||
| 4077 | #define CEC_CSR_RBTF_Pos (7U) |
||
| 4078 | #define CEC_CSR_RBTF_Msk (0x1U << CEC_CSR_RBTF_Pos) /*!< 0x00000080 */ |
||
| 4079 | #define CEC_CSR_RBTF CEC_CSR_RBTF_Msk /*!< Rx Block Transfer Finished */ |
||
| 4080 | |||
| 4081 | /******************** Bit definition for CEC_TXD register ******************/ |
||
| 4082 | #define CEC_TXD_TXD_Pos (0U) |
||
| 4083 | #define CEC_TXD_TXD_Msk (0xFFU << CEC_TXD_TXD_Pos) /*!< 0x000000FF */ |
||
| 4084 | #define CEC_TXD_TXD CEC_TXD_TXD_Msk /*!< Tx Data register */ |
||
| 4085 | |||
| 4086 | /******************** Bit definition for CEC_RXD register ******************/ |
||
| 4087 | #define CEC_RXD_RXD_Pos (0U) |
||
| 4088 | #define CEC_RXD_RXD_Msk (0xFFU << CEC_RXD_RXD_Pos) /*!< 0x000000FF */ |
||
| 4089 | #define CEC_RXD_RXD CEC_RXD_RXD_Msk /*!< Rx Data register */ |
||
| 4090 | |||
| 4091 | /*****************************************************************************/ |
||
| 4092 | /* */ |
||
| 4093 | /* Timers (TIM) */ |
||
| 4094 | /* */ |
||
| 4095 | /*****************************************************************************/ |
||
| 4096 | /******************* Bit definition for TIM_CR1 register *******************/ |
||
| 4097 | #define TIM_CR1_CEN_Pos (0U) |
||
| 4098 | #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ |
||
| 4099 | #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ |
||
| 4100 | #define TIM_CR1_UDIS_Pos (1U) |
||
| 4101 | #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ |
||
| 4102 | #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ |
||
| 4103 | #define TIM_CR1_URS_Pos (2U) |
||
| 4104 | #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ |
||
| 4105 | #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ |
||
| 4106 | #define TIM_CR1_OPM_Pos (3U) |
||
| 4107 | #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ |
||
| 4108 | #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ |
||
| 4109 | #define TIM_CR1_DIR_Pos (4U) |
||
| 4110 | #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ |
||
| 4111 | #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ |
||
| 4112 | |||
| 4113 | #define TIM_CR1_CMS_Pos (5U) |
||
| 4114 | #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ |
||
| 4115 | #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
||
| 4116 | #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ |
||
| 4117 | #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ |
||
| 4118 | |||
| 4119 | #define TIM_CR1_ARPE_Pos (7U) |
||
| 4120 | #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ |
||
| 4121 | #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ |
||
| 4122 | |||
| 4123 | #define TIM_CR1_CKD_Pos (8U) |
||
| 4124 | #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ |
||
| 4125 | #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ |
||
| 4126 | #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ |
||
| 4127 | #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ |
||
| 4128 | |||
| 4129 | /******************* Bit definition for TIM_CR2 register *******************/ |
||
| 4130 | #define TIM_CR2_CCPC_Pos (0U) |
||
| 4131 | #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ |
||
| 4132 | #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ |
||
| 4133 | #define TIM_CR2_CCUS_Pos (2U) |
||
| 4134 | #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ |
||
| 4135 | #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ |
||
| 4136 | #define TIM_CR2_CCDS_Pos (3U) |
||
| 4137 | #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ |
||
| 4138 | #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ |
||
| 4139 | |||
| 4140 | #define TIM_CR2_MMS_Pos (4U) |
||
| 4141 | #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ |
||
| 4142 | #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
||
| 4143 | #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ |
||
| 4144 | #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ |
||
| 4145 | #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ |
||
| 4146 | |||
| 4147 | #define TIM_CR2_TI1S_Pos (7U) |
||
| 4148 | #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ |
||
| 4149 | #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ |
||
| 4150 | #define TIM_CR2_OIS1_Pos (8U) |
||
| 4151 | #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ |
||
| 4152 | #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ |
||
| 4153 | #define TIM_CR2_OIS1N_Pos (9U) |
||
| 4154 | #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ |
||
| 4155 | #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ |
||
| 4156 | #define TIM_CR2_OIS2_Pos (10U) |
||
| 4157 | #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ |
||
| 4158 | #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ |
||
| 4159 | #define TIM_CR2_OIS2N_Pos (11U) |
||
| 4160 | #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ |
||
| 4161 | #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ |
||
| 4162 | #define TIM_CR2_OIS3_Pos (12U) |
||
| 4163 | #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ |
||
| 4164 | #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ |
||
| 4165 | #define TIM_CR2_OIS3N_Pos (13U) |
||
| 4166 | #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ |
||
| 4167 | #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ |
||
| 4168 | #define TIM_CR2_OIS4_Pos (14U) |
||
| 4169 | #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ |
||
| 4170 | #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ |
||
| 4171 | |||
| 4172 | /******************* Bit definition for TIM_SMCR register ******************/ |
||
| 4173 | #define TIM_SMCR_SMS_Pos (0U) |
||
| 4174 | #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ |
||
| 4175 | #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ |
||
| 4176 | #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ |
||
| 4177 | #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ |
||
| 4178 | #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ |
||
| 4179 | |||
| 4180 | #define TIM_SMCR_TS_Pos (4U) |
||
| 4181 | #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ |
||
| 4182 | #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ |
||
| 4183 | #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ |
||
| 4184 | #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ |
||
| 4185 | #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ |
||
| 4186 | |||
| 4187 | #define TIM_SMCR_MSM_Pos (7U) |
||
| 4188 | #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ |
||
| 4189 | #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ |
||
| 4190 | |||
| 4191 | #define TIM_SMCR_ETF_Pos (8U) |
||
| 4192 | #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ |
||
| 4193 | #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ |
||
| 4194 | #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ |
||
| 4195 | #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ |
||
| 4196 | #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ |
||
| 4197 | #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ |
||
| 4198 | |||
| 4199 | #define TIM_SMCR_ETPS_Pos (12U) |
||
| 4200 | #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ |
||
| 4201 | #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ |
||
| 4202 | #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ |
||
| 4203 | #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ |
||
| 4204 | |||
| 4205 | #define TIM_SMCR_ECE_Pos (14U) |
||
| 4206 | #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ |
||
| 4207 | #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ |
||
| 4208 | #define TIM_SMCR_ETP_Pos (15U) |
||
| 4209 | #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ |
||
| 4210 | #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ |
||
| 4211 | |||
| 4212 | /******************* Bit definition for TIM_DIER register ******************/ |
||
| 4213 | #define TIM_DIER_UIE_Pos (0U) |
||
| 4214 | #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ |
||
| 4215 | #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ |
||
| 4216 | #define TIM_DIER_CC1IE_Pos (1U) |
||
| 4217 | #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ |
||
| 4218 | #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ |
||
| 4219 | #define TIM_DIER_CC2IE_Pos (2U) |
||
| 4220 | #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ |
||
| 4221 | #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ |
||
| 4222 | #define TIM_DIER_CC3IE_Pos (3U) |
||
| 4223 | #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ |
||
| 4224 | #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ |
||
| 4225 | #define TIM_DIER_CC4IE_Pos (4U) |
||
| 4226 | #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ |
||
| 4227 | #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ |
||
| 4228 | #define TIM_DIER_COMIE_Pos (5U) |
||
| 4229 | #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ |
||
| 4230 | #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ |
||
| 4231 | #define TIM_DIER_TIE_Pos (6U) |
||
| 4232 | #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ |
||
| 4233 | #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ |
||
| 4234 | #define TIM_DIER_BIE_Pos (7U) |
||
| 4235 | #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ |
||
| 4236 | #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ |
||
| 4237 | #define TIM_DIER_UDE_Pos (8U) |
||
| 4238 | #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ |
||
| 4239 | #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ |
||
| 4240 | #define TIM_DIER_CC1DE_Pos (9U) |
||
| 4241 | #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ |
||
| 4242 | #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ |
||
| 4243 | #define TIM_DIER_CC2DE_Pos (10U) |
||
| 4244 | #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ |
||
| 4245 | #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ |
||
| 4246 | #define TIM_DIER_CC3DE_Pos (11U) |
||
| 4247 | #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ |
||
| 4248 | #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ |
||
| 4249 | #define TIM_DIER_CC4DE_Pos (12U) |
||
| 4250 | #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ |
||
| 4251 | #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ |
||
| 4252 | #define TIM_DIER_COMDE_Pos (13U) |
||
| 4253 | #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ |
||
| 4254 | #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ |
||
| 4255 | #define TIM_DIER_TDE_Pos (14U) |
||
| 4256 | #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ |
||
| 4257 | #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ |
||
| 4258 | |||
| 4259 | /******************** Bit definition for TIM_SR register *******************/ |
||
| 4260 | #define TIM_SR_UIF_Pos (0U) |
||
| 4261 | #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ |
||
| 4262 | #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ |
||
| 4263 | #define TIM_SR_CC1IF_Pos (1U) |
||
| 4264 | #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ |
||
| 4265 | #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ |
||
| 4266 | #define TIM_SR_CC2IF_Pos (2U) |
||
| 4267 | #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ |
||
| 4268 | #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ |
||
| 4269 | #define TIM_SR_CC3IF_Pos (3U) |
||
| 4270 | #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ |
||
| 4271 | #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ |
||
| 4272 | #define TIM_SR_CC4IF_Pos (4U) |
||
| 4273 | #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ |
||
| 4274 | #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ |
||
| 4275 | #define TIM_SR_COMIF_Pos (5U) |
||
| 4276 | #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ |
||
| 4277 | #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ |
||
| 4278 | #define TIM_SR_TIF_Pos (6U) |
||
| 4279 | #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ |
||
| 4280 | #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ |
||
| 4281 | #define TIM_SR_BIF_Pos (7U) |
||
| 4282 | #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ |
||
| 4283 | #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ |
||
| 4284 | #define TIM_SR_CC1OF_Pos (9U) |
||
| 4285 | #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ |
||
| 4286 | #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ |
||
| 4287 | #define TIM_SR_CC2OF_Pos (10U) |
||
| 4288 | #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ |
||
| 4289 | #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ |
||
| 4290 | #define TIM_SR_CC3OF_Pos (11U) |
||
| 4291 | #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ |
||
| 4292 | #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ |
||
| 4293 | #define TIM_SR_CC4OF_Pos (12U) |
||
| 4294 | #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ |
||
| 4295 | #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ |
||
| 4296 | |||
| 4297 | /******************* Bit definition for TIM_EGR register *******************/ |
||
| 4298 | #define TIM_EGR_UG_Pos (0U) |
||
| 4299 | #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ |
||
| 4300 | #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ |
||
| 4301 | #define TIM_EGR_CC1G_Pos (1U) |
||
| 4302 | #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ |
||
| 4303 | #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ |
||
| 4304 | #define TIM_EGR_CC2G_Pos (2U) |
||
| 4305 | #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ |
||
| 4306 | #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ |
||
| 4307 | #define TIM_EGR_CC3G_Pos (3U) |
||
| 4308 | #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ |
||
| 4309 | #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ |
||
| 4310 | #define TIM_EGR_CC4G_Pos (4U) |
||
| 4311 | #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ |
||
| 4312 | #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ |
||
| 4313 | #define TIM_EGR_COMG_Pos (5U) |
||
| 4314 | #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ |
||
| 4315 | #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ |
||
| 4316 | #define TIM_EGR_TG_Pos (6U) |
||
| 4317 | #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ |
||
| 4318 | #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ |
||
| 4319 | #define TIM_EGR_BG_Pos (7U) |
||
| 4320 | #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ |
||
| 4321 | #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ |
||
| 4322 | |||
| 4323 | /****************** Bit definition for TIM_CCMR1 register ******************/ |
||
| 4324 | #define TIM_CCMR1_CC1S_Pos (0U) |
||
| 4325 | #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ |
||
| 4326 | #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
||
| 4327 | #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ |
||
| 4328 | #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ |
||
| 4329 | |||
| 4330 | #define TIM_CCMR1_OC1FE_Pos (2U) |
||
| 4331 | #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ |
||
| 4332 | #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ |
||
| 4333 | #define TIM_CCMR1_OC1PE_Pos (3U) |
||
| 4334 | #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ |
||
| 4335 | #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ |
||
| 4336 | |||
| 4337 | #define TIM_CCMR1_OC1M_Pos (4U) |
||
| 4338 | #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ |
||
| 4339 | #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
||
| 4340 | #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ |
||
| 4341 | #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ |
||
| 4342 | #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ |
||
| 4343 | |||
| 4344 | #define TIM_CCMR1_OC1CE_Pos (7U) |
||
| 4345 | #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ |
||
| 4346 | #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ |
||
| 4347 | |||
| 4348 | #define TIM_CCMR1_CC2S_Pos (8U) |
||
| 4349 | #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ |
||
| 4350 | #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
||
| 4351 | #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ |
||
| 4352 | #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ |
||
| 4353 | |||
| 4354 | #define TIM_CCMR1_OC2FE_Pos (10U) |
||
| 4355 | #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ |
||
| 4356 | #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ |
||
| 4357 | #define TIM_CCMR1_OC2PE_Pos (11U) |
||
| 4358 | #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ |
||
| 4359 | #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ |
||
| 4360 | |||
| 4361 | #define TIM_CCMR1_OC2M_Pos (12U) |
||
| 4362 | #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ |
||
| 4363 | #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
||
| 4364 | #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ |
||
| 4365 | #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ |
||
| 4366 | #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ |
||
| 4367 | |||
| 4368 | #define TIM_CCMR1_OC2CE_Pos (15U) |
||
| 4369 | #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ |
||
| 4370 | #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ |
||
| 4371 | |||
| 4372 | /*---------------------------------------------------------------------------*/ |
||
| 4373 | |||
| 4374 | #define TIM_CCMR1_IC1PSC_Pos (2U) |
||
| 4375 | #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ |
||
| 4376 | #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
||
| 4377 | #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ |
||
| 4378 | #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ |
||
| 4379 | |||
| 4380 | #define TIM_CCMR1_IC1F_Pos (4U) |
||
| 4381 | #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ |
||
| 4382 | #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
||
| 4383 | #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ |
||
| 4384 | #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ |
||
| 4385 | #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ |
||
| 4386 | #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ |
||
| 4387 | |||
| 4388 | #define TIM_CCMR1_IC2PSC_Pos (10U) |
||
| 4389 | #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ |
||
| 4390 | #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
||
| 4391 | #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ |
||
| 4392 | #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ |
||
| 4393 | |||
| 4394 | #define TIM_CCMR1_IC2F_Pos (12U) |
||
| 4395 | #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ |
||
| 4396 | #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
||
| 4397 | #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ |
||
| 4398 | #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ |
||
| 4399 | #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ |
||
| 4400 | #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ |
||
| 4401 | |||
| 4402 | /****************** Bit definition for TIM_CCMR2 register ******************/ |
||
| 4403 | #define TIM_CCMR2_CC3S_Pos (0U) |
||
| 4404 | #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ |
||
| 4405 | #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
||
| 4406 | #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ |
||
| 4407 | #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ |
||
| 4408 | |||
| 4409 | #define TIM_CCMR2_OC3FE_Pos (2U) |
||
| 4410 | #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ |
||
| 4411 | #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ |
||
| 4412 | #define TIM_CCMR2_OC3PE_Pos (3U) |
||
| 4413 | #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ |
||
| 4414 | #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ |
||
| 4415 | |||
| 4416 | #define TIM_CCMR2_OC3M_Pos (4U) |
||
| 4417 | #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ |
||
| 4418 | #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
||
| 4419 | #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ |
||
| 4420 | #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ |
||
| 4421 | #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ |
||
| 4422 | |||
| 4423 | #define TIM_CCMR2_OC3CE_Pos (7U) |
||
| 4424 | #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ |
||
| 4425 | #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ |
||
| 4426 | |||
| 4427 | #define TIM_CCMR2_CC4S_Pos (8U) |
||
| 4428 | #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ |
||
| 4429 | #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
||
| 4430 | #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ |
||
| 4431 | #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ |
||
| 4432 | |||
| 4433 | #define TIM_CCMR2_OC4FE_Pos (10U) |
||
| 4434 | #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ |
||
| 4435 | #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ |
||
| 4436 | #define TIM_CCMR2_OC4PE_Pos (11U) |
||
| 4437 | #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ |
||
| 4438 | #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ |
||
| 4439 | |||
| 4440 | #define TIM_CCMR2_OC4M_Pos (12U) |
||
| 4441 | #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ |
||
| 4442 | #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
||
| 4443 | #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ |
||
| 4444 | #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ |
||
| 4445 | #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ |
||
| 4446 | |||
| 4447 | #define TIM_CCMR2_OC4CE_Pos (15U) |
||
| 4448 | #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ |
||
| 4449 | #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ |
||
| 4450 | |||
| 4451 | /*---------------------------------------------------------------------------*/ |
||
| 4452 | |||
| 4453 | #define TIM_CCMR2_IC3PSC_Pos (2U) |
||
| 4454 | #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ |
||
| 4455 | #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
||
| 4456 | #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ |
||
| 4457 | #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ |
||
| 4458 | |||
| 4459 | #define TIM_CCMR2_IC3F_Pos (4U) |
||
| 4460 | #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ |
||
| 4461 | #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
||
| 4462 | #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ |
||
| 4463 | #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ |
||
| 4464 | #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ |
||
| 4465 | #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ |
||
| 4466 | |||
| 4467 | #define TIM_CCMR2_IC4PSC_Pos (10U) |
||
| 4468 | #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ |
||
| 4469 | #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
||
| 4470 | #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ |
||
| 4471 | #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ |
||
| 4472 | |||
| 4473 | #define TIM_CCMR2_IC4F_Pos (12U) |
||
| 4474 | #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ |
||
| 4475 | #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
||
| 4476 | #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ |
||
| 4477 | #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ |
||
| 4478 | #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ |
||
| 4479 | #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ |
||
| 4480 | |||
| 4481 | /******************* Bit definition for TIM_CCER register ******************/ |
||
| 4482 | #define TIM_CCER_CC1E_Pos (0U) |
||
| 4483 | #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ |
||
| 4484 | #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ |
||
| 4485 | #define TIM_CCER_CC1P_Pos (1U) |
||
| 4486 | #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ |
||
| 4487 | #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ |
||
| 4488 | #define TIM_CCER_CC1NE_Pos (2U) |
||
| 4489 | #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ |
||
| 4490 | #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ |
||
| 4491 | #define TIM_CCER_CC1NP_Pos (3U) |
||
| 4492 | #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ |
||
| 4493 | #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ |
||
| 4494 | #define TIM_CCER_CC2E_Pos (4U) |
||
| 4495 | #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ |
||
| 4496 | #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ |
||
| 4497 | #define TIM_CCER_CC2P_Pos (5U) |
||
| 4498 | #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ |
||
| 4499 | #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ |
||
| 4500 | #define TIM_CCER_CC2NE_Pos (6U) |
||
| 4501 | #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ |
||
| 4502 | #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ |
||
| 4503 | #define TIM_CCER_CC2NP_Pos (7U) |
||
| 4504 | #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ |
||
| 4505 | #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ |
||
| 4506 | #define TIM_CCER_CC3E_Pos (8U) |
||
| 4507 | #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ |
||
| 4508 | #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ |
||
| 4509 | #define TIM_CCER_CC3P_Pos (9U) |
||
| 4510 | #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ |
||
| 4511 | #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ |
||
| 4512 | #define TIM_CCER_CC3NE_Pos (10U) |
||
| 4513 | #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ |
||
| 4514 | #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ |
||
| 4515 | #define TIM_CCER_CC3NP_Pos (11U) |
||
| 4516 | #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ |
||
| 4517 | #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ |
||
| 4518 | #define TIM_CCER_CC4E_Pos (12U) |
||
| 4519 | #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ |
||
| 4520 | #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ |
||
| 4521 | #define TIM_CCER_CC4P_Pos (13U) |
||
| 4522 | #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ |
||
| 4523 | #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ |
||
| 4524 | |||
| 4525 | /******************* Bit definition for TIM_CNT register *******************/ |
||
| 4526 | #define TIM_CNT_CNT_Pos (0U) |
||
| 4527 | #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ |
||
| 4528 | #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ |
||
| 4529 | |||
| 4530 | /******************* Bit definition for TIM_PSC register *******************/ |
||
| 4531 | #define TIM_PSC_PSC_Pos (0U) |
||
| 4532 | #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ |
||
| 4533 | #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ |
||
| 4534 | |||
| 4535 | /******************* Bit definition for TIM_ARR register *******************/ |
||
| 4536 | #define TIM_ARR_ARR_Pos (0U) |
||
| 4537 | #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ |
||
| 4538 | #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ |
||
| 4539 | |||
| 4540 | /******************* Bit definition for TIM_RCR register *******************/ |
||
| 4541 | #define TIM_RCR_REP_Pos (0U) |
||
| 4542 | #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */ |
||
| 4543 | #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ |
||
| 4544 | |||
| 4545 | /******************* Bit definition for TIM_CCR1 register ******************/ |
||
| 4546 | #define TIM_CCR1_CCR1_Pos (0U) |
||
| 4547 | #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ |
||
| 4548 | #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ |
||
| 4549 | |||
| 4550 | /******************* Bit definition for TIM_CCR2 register ******************/ |
||
| 4551 | #define TIM_CCR2_CCR2_Pos (0U) |
||
| 4552 | #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ |
||
| 4553 | #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ |
||
| 4554 | |||
| 4555 | /******************* Bit definition for TIM_CCR3 register ******************/ |
||
| 4556 | #define TIM_CCR3_CCR3_Pos (0U) |
||
| 4557 | #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ |
||
| 4558 | #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ |
||
| 4559 | |||
| 4560 | /******************* Bit definition for TIM_CCR4 register ******************/ |
||
| 4561 | #define TIM_CCR4_CCR4_Pos (0U) |
||
| 4562 | #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ |
||
| 4563 | #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ |
||
| 4564 | |||
| 4565 | /******************* Bit definition for TIM_BDTR register ******************/ |
||
| 4566 | #define TIM_BDTR_DTG_Pos (0U) |
||
| 4567 | #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ |
||
| 4568 | #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
||
| 4569 | #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ |
||
| 4570 | #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ |
||
| 4571 | #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ |
||
| 4572 | #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ |
||
| 4573 | #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ |
||
| 4574 | #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ |
||
| 4575 | #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ |
||
| 4576 | #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ |
||
| 4577 | |||
| 4578 | #define TIM_BDTR_LOCK_Pos (8U) |
||
| 4579 | #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ |
||
| 4580 | #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ |
||
| 4581 | #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ |
||
| 4582 | #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ |
||
| 4583 | |||
| 4584 | #define TIM_BDTR_OSSI_Pos (10U) |
||
| 4585 | #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ |
||
| 4586 | #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ |
||
| 4587 | #define TIM_BDTR_OSSR_Pos (11U) |
||
| 4588 | #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ |
||
| 4589 | #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ |
||
| 4590 | #define TIM_BDTR_BKE_Pos (12U) |
||
| 4591 | #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ |
||
| 4592 | #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ |
||
| 4593 | #define TIM_BDTR_BKP_Pos (13U) |
||
| 4594 | #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ |
||
| 4595 | #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ |
||
| 4596 | #define TIM_BDTR_AOE_Pos (14U) |
||
| 4597 | #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ |
||
| 4598 | #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ |
||
| 4599 | #define TIM_BDTR_MOE_Pos (15U) |
||
| 4600 | #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ |
||
| 4601 | #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ |
||
| 4602 | |||
| 4603 | /******************* Bit definition for TIM_DCR register *******************/ |
||
| 4604 | #define TIM_DCR_DBA_Pos (0U) |
||
| 4605 | #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ |
||
| 4606 | #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ |
||
| 4607 | #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ |
||
| 4608 | #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ |
||
| 4609 | #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ |
||
| 4610 | #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ |
||
| 4611 | #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ |
||
| 4612 | |||
| 4613 | #define TIM_DCR_DBL_Pos (8U) |
||
| 4614 | #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ |
||
| 4615 | #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ |
||
| 4616 | #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ |
||
| 4617 | #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ |
||
| 4618 | #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ |
||
| 4619 | #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ |
||
| 4620 | #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ |
||
| 4621 | |||
| 4622 | /******************* Bit definition for TIM_DMAR register ******************/ |
||
| 4623 | #define TIM_DMAR_DMAB_Pos (0U) |
||
| 4624 | #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ |
||
| 4625 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ |
||
| 4626 | |||
| 4627 | /******************************************************************************/ |
||
| 4628 | /* */ |
||
| 4629 | /* Real-Time Clock */ |
||
| 4630 | /* */ |
||
| 4631 | /******************************************************************************/ |
||
| 4632 | |||
| 4633 | /******************* Bit definition for RTC_CRH register ********************/ |
||
| 4634 | #define RTC_CRH_SECIE_Pos (0U) |
||
| 4635 | #define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ |
||
| 4636 | #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ |
||
| 4637 | #define RTC_CRH_ALRIE_Pos (1U) |
||
| 4638 | #define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ |
||
| 4639 | #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ |
||
| 4640 | #define RTC_CRH_OWIE_Pos (2U) |
||
| 4641 | #define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ |
||
| 4642 | #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ |
||
| 4643 | |||
| 4644 | /******************* Bit definition for RTC_CRL register ********************/ |
||
| 4645 | #define RTC_CRL_SECF_Pos (0U) |
||
| 4646 | #define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ |
||
| 4647 | #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ |
||
| 4648 | #define RTC_CRL_ALRF_Pos (1U) |
||
| 4649 | #define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ |
||
| 4650 | #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ |
||
| 4651 | #define RTC_CRL_OWF_Pos (2U) |
||
| 4652 | #define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ |
||
| 4653 | #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ |
||
| 4654 | #define RTC_CRL_RSF_Pos (3U) |
||
| 4655 | #define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ |
||
| 4656 | #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ |
||
| 4657 | #define RTC_CRL_CNF_Pos (4U) |
||
| 4658 | #define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ |
||
| 4659 | #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ |
||
| 4660 | #define RTC_CRL_RTOFF_Pos (5U) |
||
| 4661 | #define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ |
||
| 4662 | #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ |
||
| 4663 | |||
| 4664 | /******************* Bit definition for RTC_PRLH register *******************/ |
||
| 4665 | #define RTC_PRLH_PRL_Pos (0U) |
||
| 4666 | #define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ |
||
| 4667 | #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ |
||
| 4668 | |||
| 4669 | /******************* Bit definition for RTC_PRLL register *******************/ |
||
| 4670 | #define RTC_PRLL_PRL_Pos (0U) |
||
| 4671 | #define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ |
||
| 4672 | #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ |
||
| 4673 | |||
| 4674 | /******************* Bit definition for RTC_DIVH register *******************/ |
||
| 4675 | #define RTC_DIVH_RTC_DIV_Pos (0U) |
||
| 4676 | #define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ |
||
| 4677 | #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ |
||
| 4678 | |||
| 4679 | /******************* Bit definition for RTC_DIVL register *******************/ |
||
| 4680 | #define RTC_DIVL_RTC_DIV_Pos (0U) |
||
| 4681 | #define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ |
||
| 4682 | #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ |
||
| 4683 | |||
| 4684 | /******************* Bit definition for RTC_CNTH register *******************/ |
||
| 4685 | #define RTC_CNTH_RTC_CNT_Pos (0U) |
||
| 4686 | #define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ |
||
| 4687 | #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ |
||
| 4688 | |||
| 4689 | /******************* Bit definition for RTC_CNTL register *******************/ |
||
| 4690 | #define RTC_CNTL_RTC_CNT_Pos (0U) |
||
| 4691 | #define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ |
||
| 4692 | #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ |
||
| 4693 | |||
| 4694 | /******************* Bit definition for RTC_ALRH register *******************/ |
||
| 4695 | #define RTC_ALRH_RTC_ALR_Pos (0U) |
||
| 4696 | #define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ |
||
| 4697 | #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ |
||
| 4698 | |||
| 4699 | /******************* Bit definition for RTC_ALRL register *******************/ |
||
| 4700 | #define RTC_ALRL_RTC_ALR_Pos (0U) |
||
| 4701 | #define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ |
||
| 4702 | #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ |
||
| 4703 | |||
| 4704 | /******************************************************************************/ |
||
| 4705 | /* */ |
||
| 4706 | /* Independent WATCHDOG (IWDG) */ |
||
| 4707 | /* */ |
||
| 4708 | /******************************************************************************/ |
||
| 4709 | |||
| 4710 | /******************* Bit definition for IWDG_KR register ********************/ |
||
| 4711 | #define IWDG_KR_KEY_Pos (0U) |
||
| 4712 | #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ |
||
| 4713 | #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ |
||
| 4714 | |||
| 4715 | /******************* Bit definition for IWDG_PR register ********************/ |
||
| 4716 | #define IWDG_PR_PR_Pos (0U) |
||
| 4717 | #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ |
||
| 4718 | #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ |
||
| 4719 | #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ |
||
| 4720 | #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ |
||
| 4721 | #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ |
||
| 4722 | |||
| 4723 | /******************* Bit definition for IWDG_RLR register *******************/ |
||
| 4724 | #define IWDG_RLR_RL_Pos (0U) |
||
| 4725 | #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ |
||
| 4726 | #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ |
||
| 4727 | |||
| 4728 | /******************* Bit definition for IWDG_SR register ********************/ |
||
| 4729 | #define IWDG_SR_PVU_Pos (0U) |
||
| 4730 | #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ |
||
| 4731 | #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ |
||
| 4732 | #define IWDG_SR_RVU_Pos (1U) |
||
| 4733 | #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ |
||
| 4734 | #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ |
||
| 4735 | |||
| 4736 | /******************************************************************************/ |
||
| 4737 | /* */ |
||
| 4738 | /* Window WATCHDOG (WWDG) */ |
||
| 4739 | /* */ |
||
| 4740 | /******************************************************************************/ |
||
| 4741 | |||
| 4742 | /******************* Bit definition for WWDG_CR register ********************/ |
||
| 4743 | #define WWDG_CR_T_Pos (0U) |
||
| 4744 | #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ |
||
| 4745 | #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
||
| 4746 | #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ |
||
| 4747 | #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ |
||
| 4748 | #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ |
||
| 4749 | #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ |
||
| 4750 | #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ |
||
| 4751 | #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ |
||
| 4752 | #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ |
||
| 4753 | |||
| 4754 | /* Legacy defines */ |
||
| 4755 | #define WWDG_CR_T0 WWDG_CR_T_0 |
||
| 4756 | #define WWDG_CR_T1 WWDG_CR_T_1 |
||
| 4757 | #define WWDG_CR_T2 WWDG_CR_T_2 |
||
| 4758 | #define WWDG_CR_T3 WWDG_CR_T_3 |
||
| 4759 | #define WWDG_CR_T4 WWDG_CR_T_4 |
||
| 4760 | #define WWDG_CR_T5 WWDG_CR_T_5 |
||
| 4761 | #define WWDG_CR_T6 WWDG_CR_T_6 |
||
| 4762 | |||
| 4763 | #define WWDG_CR_WDGA_Pos (7U) |
||
| 4764 | #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ |
||
| 4765 | #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ |
||
| 4766 | |||
| 4767 | /******************* Bit definition for WWDG_CFR register *******************/ |
||
| 4768 | #define WWDG_CFR_W_Pos (0U) |
||
| 4769 | #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ |
||
| 4770 | #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ |
||
| 4771 | #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ |
||
| 4772 | #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ |
||
| 4773 | #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ |
||
| 4774 | #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ |
||
| 4775 | #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ |
||
| 4776 | #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ |
||
| 4777 | #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ |
||
| 4778 | |||
| 4779 | /* Legacy defines */ |
||
| 4780 | #define WWDG_CFR_W0 WWDG_CFR_W_0 |
||
| 4781 | #define WWDG_CFR_W1 WWDG_CFR_W_1 |
||
| 4782 | #define WWDG_CFR_W2 WWDG_CFR_W_2 |
||
| 4783 | #define WWDG_CFR_W3 WWDG_CFR_W_3 |
||
| 4784 | #define WWDG_CFR_W4 WWDG_CFR_W_4 |
||
| 4785 | #define WWDG_CFR_W5 WWDG_CFR_W_5 |
||
| 4786 | #define WWDG_CFR_W6 WWDG_CFR_W_6 |
||
| 4787 | |||
| 4788 | #define WWDG_CFR_WDGTB_Pos (7U) |
||
| 4789 | #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ |
||
| 4790 | #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ |
||
| 4791 | #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ |
||
| 4792 | #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ |
||
| 4793 | |||
| 4794 | /* Legacy defines */ |
||
| 4795 | #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
||
| 4796 | #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
||
| 4797 | |||
| 4798 | #define WWDG_CFR_EWI_Pos (9U) |
||
| 4799 | #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ |
||
| 4800 | #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ |
||
| 4801 | |||
| 4802 | /******************* Bit definition for WWDG_SR register ********************/ |
||
| 4803 | #define WWDG_SR_EWIF_Pos (0U) |
||
| 4804 | #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ |
||
| 4805 | #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ |
||
| 4806 | |||
| 4807 | |||
| 4808 | /******************************************************************************/ |
||
| 4809 | /* */ |
||
| 4810 | /* SD host Interface */ |
||
| 4811 | /* */ |
||
| 4812 | /******************************************************************************/ |
||
| 4813 | |||
| 4814 | /****************** Bit definition for SDIO_POWER register ******************/ |
||
| 4815 | #define SDIO_POWER_PWRCTRL_Pos (0U) |
||
| 4816 | #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ |
||
| 4817 | #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */ |
||
| 4818 | #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */ |
||
| 4819 | #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */ |
||
| 4820 | |||
| 4821 | /****************** Bit definition for SDIO_CLKCR register ******************/ |
||
| 4822 | #define SDIO_CLKCR_CLKDIV_Pos (0U) |
||
| 4823 | #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ |
||
| 4824 | #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */ |
||
| 4825 | #define SDIO_CLKCR_CLKEN_Pos (8U) |
||
| 4826 | #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ |
||
| 4827 | #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */ |
||
| 4828 | #define SDIO_CLKCR_PWRSAV_Pos (9U) |
||
| 4829 | #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ |
||
| 4830 | #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */ |
||
| 4831 | #define SDIO_CLKCR_BYPASS_Pos (10U) |
||
| 4832 | #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ |
||
| 4833 | #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */ |
||
| 4834 | |||
| 4835 | #define SDIO_CLKCR_WIDBUS_Pos (11U) |
||
| 4836 | #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ |
||
| 4837 | #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
||
| 4838 | #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */ |
||
| 4839 | #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */ |
||
| 4840 | |||
| 4841 | #define SDIO_CLKCR_NEGEDGE_Pos (13U) |
||
| 4842 | #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ |
||
| 4843 | #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */ |
||
| 4844 | #define SDIO_CLKCR_HWFC_EN_Pos (14U) |
||
| 4845 | #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ |
||
| 4846 | #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */ |
||
| 4847 | |||
| 4848 | /******************* Bit definition for SDIO_ARG register *******************/ |
||
| 4849 | #define SDIO_ARG_CMDARG_Pos (0U) |
||
| 4850 | #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ |
||
| 4851 | #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */ |
||
| 4852 | |||
| 4853 | /******************* Bit definition for SDIO_CMD register *******************/ |
||
| 4854 | #define SDIO_CMD_CMDINDEX_Pos (0U) |
||
| 4855 | #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ |
||
| 4856 | #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */ |
||
| 4857 | |||
| 4858 | #define SDIO_CMD_WAITRESP_Pos (6U) |
||
| 4859 | #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ |
||
| 4860 | #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */ |
||
| 4861 | #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */ |
||
| 4862 | #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */ |
||
| 4863 | |||
| 4864 | #define SDIO_CMD_WAITINT_Pos (8U) |
||
| 4865 | #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ |
||
| 4866 | #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */ |
||
| 4867 | #define SDIO_CMD_WAITPEND_Pos (9U) |
||
| 4868 | #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ |
||
| 4869 | #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
||
| 4870 | #define SDIO_CMD_CPSMEN_Pos (10U) |
||
| 4871 | #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ |
||
| 4872 | #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */ |
||
| 4873 | #define SDIO_CMD_SDIOSUSPEND_Pos (11U) |
||
| 4874 | #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ |
||
| 4875 | #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */ |
||
| 4876 | #define SDIO_CMD_ENCMDCOMPL_Pos (12U) |
||
| 4877 | #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ |
||
| 4878 | #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */ |
||
| 4879 | #define SDIO_CMD_NIEN_Pos (13U) |
||
| 4880 | #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ |
||
| 4881 | #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */ |
||
| 4882 | #define SDIO_CMD_CEATACMD_Pos (14U) |
||
| 4883 | #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ |
||
| 4884 | #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */ |
||
| 4885 | |||
| 4886 | /***************** Bit definition for SDIO_RESPCMD register *****************/ |
||
| 4887 | #define SDIO_RESPCMD_RESPCMD_Pos (0U) |
||
| 4888 | #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ |
||
| 4889 | #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */ |
||
| 4890 | |||
| 4891 | /****************** Bit definition for SDIO_RESP0 register ******************/ |
||
| 4892 | #define SDIO_RESP0_CARDSTATUS0_Pos (0U) |
||
| 4893 | #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ |
||
| 4894 | #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */ |
||
| 4895 | |||
| 4896 | /****************** Bit definition for SDIO_RESP1 register ******************/ |
||
| 4897 | #define SDIO_RESP1_CARDSTATUS1_Pos (0U) |
||
| 4898 | #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ |
||
| 4899 | #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */ |
||
| 4900 | |||
| 4901 | /****************** Bit definition for SDIO_RESP2 register ******************/ |
||
| 4902 | #define SDIO_RESP2_CARDSTATUS2_Pos (0U) |
||
| 4903 | #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ |
||
| 4904 | #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */ |
||
| 4905 | |||
| 4906 | /****************** Bit definition for SDIO_RESP3 register ******************/ |
||
| 4907 | #define SDIO_RESP3_CARDSTATUS3_Pos (0U) |
||
| 4908 | #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ |
||
| 4909 | #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */ |
||
| 4910 | |||
| 4911 | /****************** Bit definition for SDIO_RESP4 register ******************/ |
||
| 4912 | #define SDIO_RESP4_CARDSTATUS4_Pos (0U) |
||
| 4913 | #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ |
||
| 4914 | #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */ |
||
| 4915 | |||
| 4916 | /****************** Bit definition for SDIO_DTIMER register *****************/ |
||
| 4917 | #define SDIO_DTIMER_DATATIME_Pos (0U) |
||
| 4918 | #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ |
||
| 4919 | #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */ |
||
| 4920 | |||
| 4921 | /****************** Bit definition for SDIO_DLEN register *******************/ |
||
| 4922 | #define SDIO_DLEN_DATALENGTH_Pos (0U) |
||
| 4923 | #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ |
||
| 4924 | #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */ |
||
| 4925 | |||
| 4926 | /****************** Bit definition for SDIO_DCTRL register ******************/ |
||
| 4927 | #define SDIO_DCTRL_DTEN_Pos (0U) |
||
| 4928 | #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ |
||
| 4929 | #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */ |
||
| 4930 | #define SDIO_DCTRL_DTDIR_Pos (1U) |
||
| 4931 | #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ |
||
| 4932 | #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */ |
||
| 4933 | #define SDIO_DCTRL_DTMODE_Pos (2U) |
||
| 4934 | #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ |
||
| 4935 | #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */ |
||
| 4936 | #define SDIO_DCTRL_DMAEN_Pos (3U) |
||
| 4937 | #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ |
||
| 4938 | #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */ |
||
| 4939 | |||
| 4940 | #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) |
||
| 4941 | #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ |
||
| 4942 | #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */ |
||
| 4943 | #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */ |
||
| 4944 | #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */ |
||
| 4945 | #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */ |
||
| 4946 | #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */ |
||
| 4947 | |||
| 4948 | #define SDIO_DCTRL_RWSTART_Pos (8U) |
||
| 4949 | #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ |
||
| 4950 | #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */ |
||
| 4951 | #define SDIO_DCTRL_RWSTOP_Pos (9U) |
||
| 4952 | #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ |
||
| 4953 | #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */ |
||
| 4954 | #define SDIO_DCTRL_RWMOD_Pos (10U) |
||
| 4955 | #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ |
||
| 4956 | #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */ |
||
| 4957 | #define SDIO_DCTRL_SDIOEN_Pos (11U) |
||
| 4958 | #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ |
||
| 4959 | #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */ |
||
| 4960 | |||
| 4961 | /****************** Bit definition for SDIO_DCOUNT register *****************/ |
||
| 4962 | #define SDIO_DCOUNT_DATACOUNT_Pos (0U) |
||
| 4963 | #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ |
||
| 4964 | #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */ |
||
| 4965 | |||
| 4966 | /****************** Bit definition for SDIO_STA register ********************/ |
||
| 4967 | #define SDIO_STA_CCRCFAIL_Pos (0U) |
||
| 4968 | #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ |
||
| 4969 | #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */ |
||
| 4970 | #define SDIO_STA_DCRCFAIL_Pos (1U) |
||
| 4971 | #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ |
||
| 4972 | #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */ |
||
| 4973 | #define SDIO_STA_CTIMEOUT_Pos (2U) |
||
| 4974 | #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ |
||
| 4975 | #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */ |
||
| 4976 | #define SDIO_STA_DTIMEOUT_Pos (3U) |
||
| 4977 | #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ |
||
| 4978 | #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */ |
||
| 4979 | #define SDIO_STA_TXUNDERR_Pos (4U) |
||
| 4980 | #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ |
||
| 4981 | #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */ |
||
| 4982 | #define SDIO_STA_RXOVERR_Pos (5U) |
||
| 4983 | #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ |
||
| 4984 | #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */ |
||
| 4985 | #define SDIO_STA_CMDREND_Pos (6U) |
||
| 4986 | #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ |
||
| 4987 | #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */ |
||
| 4988 | #define SDIO_STA_CMDSENT_Pos (7U) |
||
| 4989 | #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ |
||
| 4990 | #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */ |
||
| 4991 | #define SDIO_STA_DATAEND_Pos (8U) |
||
| 4992 | #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ |
||
| 4993 | #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */ |
||
| 4994 | #define SDIO_STA_STBITERR_Pos (9U) |
||
| 4995 | #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ |
||
| 4996 | #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ |
||
| 4997 | #define SDIO_STA_DBCKEND_Pos (10U) |
||
| 4998 | #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ |
||
| 4999 | #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */ |
||
| 5000 | #define SDIO_STA_CMDACT_Pos (11U) |
||
| 5001 | #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ |
||
| 5002 | #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */ |
||
| 5003 | #define SDIO_STA_TXACT_Pos (12U) |
||
| 5004 | #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ |
||
| 5005 | #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */ |
||
| 5006 | #define SDIO_STA_RXACT_Pos (13U) |
||
| 5007 | #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ |
||
| 5008 | #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */ |
||
| 5009 | #define SDIO_STA_TXFIFOHE_Pos (14U) |
||
| 5010 | #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ |
||
| 5011 | #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
||
| 5012 | #define SDIO_STA_RXFIFOHF_Pos (15U) |
||
| 5013 | #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ |
||
| 5014 | #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
||
| 5015 | #define SDIO_STA_TXFIFOF_Pos (16U) |
||
| 5016 | #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ |
||
| 5017 | #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */ |
||
| 5018 | #define SDIO_STA_RXFIFOF_Pos (17U) |
||
| 5019 | #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ |
||
| 5020 | #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */ |
||
| 5021 | #define SDIO_STA_TXFIFOE_Pos (18U) |
||
| 5022 | #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ |
||
| 5023 | #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */ |
||
| 5024 | #define SDIO_STA_RXFIFOE_Pos (19U) |
||
| 5025 | #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ |
||
| 5026 | #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */ |
||
| 5027 | #define SDIO_STA_TXDAVL_Pos (20U) |
||
| 5028 | #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ |
||
| 5029 | #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */ |
||
| 5030 | #define SDIO_STA_RXDAVL_Pos (21U) |
||
| 5031 | #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ |
||
| 5032 | #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */ |
||
| 5033 | #define SDIO_STA_SDIOIT_Pos (22U) |
||
| 5034 | #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ |
||
| 5035 | #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */ |
||
| 5036 | #define SDIO_STA_CEATAEND_Pos (23U) |
||
| 5037 | #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ |
||
| 5038 | #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */ |
||
| 5039 | |||
| 5040 | /******************* Bit definition for SDIO_ICR register *******************/ |
||
| 5041 | #define SDIO_ICR_CCRCFAILC_Pos (0U) |
||
| 5042 | #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ |
||
| 5043 | #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */ |
||
| 5044 | #define SDIO_ICR_DCRCFAILC_Pos (1U) |
||
| 5045 | #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ |
||
| 5046 | #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */ |
||
| 5047 | #define SDIO_ICR_CTIMEOUTC_Pos (2U) |
||
| 5048 | #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ |
||
| 5049 | #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */ |
||
| 5050 | #define SDIO_ICR_DTIMEOUTC_Pos (3U) |
||
| 5051 | #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ |
||
| 5052 | #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */ |
||
| 5053 | #define SDIO_ICR_TXUNDERRC_Pos (4U) |
||
| 5054 | #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ |
||
| 5055 | #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */ |
||
| 5056 | #define SDIO_ICR_RXOVERRC_Pos (5U) |
||
| 5057 | #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ |
||
| 5058 | #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */ |
||
| 5059 | #define SDIO_ICR_CMDRENDC_Pos (6U) |
||
| 5060 | #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ |
||
| 5061 | #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */ |
||
| 5062 | #define SDIO_ICR_CMDSENTC_Pos (7U) |
||
| 5063 | #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ |
||
| 5064 | #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */ |
||
| 5065 | #define SDIO_ICR_DATAENDC_Pos (8U) |
||
| 5066 | #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ |
||
| 5067 | #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */ |
||
| 5068 | #define SDIO_ICR_STBITERRC_Pos (9U) |
||
| 5069 | #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ |
||
| 5070 | #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */ |
||
| 5071 | #define SDIO_ICR_DBCKENDC_Pos (10U) |
||
| 5072 | #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ |
||
| 5073 | #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */ |
||
| 5074 | #define SDIO_ICR_SDIOITC_Pos (22U) |
||
| 5075 | #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ |
||
| 5076 | #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */ |
||
| 5077 | #define SDIO_ICR_CEATAENDC_Pos (23U) |
||
| 5078 | #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ |
||
| 5079 | #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */ |
||
| 5080 | |||
| 5081 | /****************** Bit definition for SDIO_MASK register *******************/ |
||
| 5082 | #define SDIO_MASK_CCRCFAILIE_Pos (0U) |
||
| 5083 | #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ |
||
| 5084 | #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */ |
||
| 5085 | #define SDIO_MASK_DCRCFAILIE_Pos (1U) |
||
| 5086 | #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ |
||
| 5087 | #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */ |
||
| 5088 | #define SDIO_MASK_CTIMEOUTIE_Pos (2U) |
||
| 5089 | #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ |
||
| 5090 | #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */ |
||
| 5091 | #define SDIO_MASK_DTIMEOUTIE_Pos (3U) |
||
| 5092 | #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ |
||
| 5093 | #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */ |
||
| 5094 | #define SDIO_MASK_TXUNDERRIE_Pos (4U) |
||
| 5095 | #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ |
||
| 5096 | #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */ |
||
| 5097 | #define SDIO_MASK_RXOVERRIE_Pos (5U) |
||
| 5098 | #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ |
||
| 5099 | #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */ |
||
| 5100 | #define SDIO_MASK_CMDRENDIE_Pos (6U) |
||
| 5101 | #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ |
||
| 5102 | #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */ |
||
| 5103 | #define SDIO_MASK_CMDSENTIE_Pos (7U) |
||
| 5104 | #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ |
||
| 5105 | #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */ |
||
| 5106 | #define SDIO_MASK_DATAENDIE_Pos (8U) |
||
| 5107 | #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ |
||
| 5108 | #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */ |
||
| 5109 | #define SDIO_MASK_STBITERRIE_Pos (9U) |
||
| 5110 | #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ |
||
| 5111 | #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */ |
||
| 5112 | #define SDIO_MASK_DBCKENDIE_Pos (10U) |
||
| 5113 | #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ |
||
| 5114 | #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */ |
||
| 5115 | #define SDIO_MASK_CMDACTIE_Pos (11U) |
||
| 5116 | #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ |
||
| 5117 | #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */ |
||
| 5118 | #define SDIO_MASK_TXACTIE_Pos (12U) |
||
| 5119 | #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ |
||
| 5120 | #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */ |
||
| 5121 | #define SDIO_MASK_RXACTIE_Pos (13U) |
||
| 5122 | #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ |
||
| 5123 | #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */ |
||
| 5124 | #define SDIO_MASK_TXFIFOHEIE_Pos (14U) |
||
| 5125 | #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ |
||
| 5126 | #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */ |
||
| 5127 | #define SDIO_MASK_RXFIFOHFIE_Pos (15U) |
||
| 5128 | #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ |
||
| 5129 | #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */ |
||
| 5130 | #define SDIO_MASK_TXFIFOFIE_Pos (16U) |
||
| 5131 | #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ |
||
| 5132 | #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */ |
||
| 5133 | #define SDIO_MASK_RXFIFOFIE_Pos (17U) |
||
| 5134 | #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ |
||
| 5135 | #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */ |
||
| 5136 | #define SDIO_MASK_TXFIFOEIE_Pos (18U) |
||
| 5137 | #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ |
||
| 5138 | #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */ |
||
| 5139 | #define SDIO_MASK_RXFIFOEIE_Pos (19U) |
||
| 5140 | #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ |
||
| 5141 | #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */ |
||
| 5142 | #define SDIO_MASK_TXDAVLIE_Pos (20U) |
||
| 5143 | #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ |
||
| 5144 | #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */ |
||
| 5145 | #define SDIO_MASK_RXDAVLIE_Pos (21U) |
||
| 5146 | #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ |
||
| 5147 | #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */ |
||
| 5148 | #define SDIO_MASK_SDIOITIE_Pos (22U) |
||
| 5149 | #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ |
||
| 5150 | #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */ |
||
| 5151 | #define SDIO_MASK_CEATAENDIE_Pos (23U) |
||
| 5152 | #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ |
||
| 5153 | #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */ |
||
| 5154 | |||
| 5155 | /***************** Bit definition for SDIO_FIFOCNT register *****************/ |
||
| 5156 | #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) |
||
| 5157 | #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ |
||
| 5158 | #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */ |
||
| 5159 | |||
| 5160 | /****************** Bit definition for SDIO_FIFO register *******************/ |
||
| 5161 | #define SDIO_FIFO_FIFODATA_Pos (0U) |
||
| 5162 | #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ |
||
| 5163 | #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */ |
||
| 5164 | |||
| 5165 | |||
| 5166 | |||
| 5167 | /******************************************************************************/ |
||
| 5168 | /* */ |
||
| 5169 | /* Serial Peripheral Interface */ |
||
| 5170 | /* */ |
||
| 5171 | /******************************************************************************/ |
||
| 5172 | |||
| 5173 | /******************* Bit definition for SPI_CR1 register ********************/ |
||
| 5174 | #define SPI_CR1_CPHA_Pos (0U) |
||
| 5175 | #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ |
||
| 5176 | #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ |
||
| 5177 | #define SPI_CR1_CPOL_Pos (1U) |
||
| 5178 | #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ |
||
| 5179 | #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ |
||
| 5180 | #define SPI_CR1_MSTR_Pos (2U) |
||
| 5181 | #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ |
||
| 5182 | #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ |
||
| 5183 | |||
| 5184 | #define SPI_CR1_BR_Pos (3U) |
||
| 5185 | #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ |
||
| 5186 | #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ |
||
| 5187 | #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ |
||
| 5188 | #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ |
||
| 5189 | #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ |
||
| 5190 | |||
| 5191 | #define SPI_CR1_SPE_Pos (6U) |
||
| 5192 | #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ |
||
| 5193 | #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ |
||
| 5194 | #define SPI_CR1_LSBFIRST_Pos (7U) |
||
| 5195 | #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ |
||
| 5196 | #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ |
||
| 5197 | #define SPI_CR1_SSI_Pos (8U) |
||
| 5198 | #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ |
||
| 5199 | #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ |
||
| 5200 | #define SPI_CR1_SSM_Pos (9U) |
||
| 5201 | #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ |
||
| 5202 | #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ |
||
| 5203 | #define SPI_CR1_RXONLY_Pos (10U) |
||
| 5204 | #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ |
||
| 5205 | #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ |
||
| 5206 | #define SPI_CR1_DFF_Pos (11U) |
||
| 5207 | #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ |
||
| 5208 | #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ |
||
| 5209 | #define SPI_CR1_CRCNEXT_Pos (12U) |
||
| 5210 | #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ |
||
| 5211 | #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ |
||
| 5212 | #define SPI_CR1_CRCEN_Pos (13U) |
||
| 5213 | #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ |
||
| 5214 | #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ |
||
| 5215 | #define SPI_CR1_BIDIOE_Pos (14U) |
||
| 5216 | #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ |
||
| 5217 | #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ |
||
| 5218 | #define SPI_CR1_BIDIMODE_Pos (15U) |
||
| 5219 | #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ |
||
| 5220 | #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ |
||
| 5221 | |||
| 5222 | /******************* Bit definition for SPI_CR2 register ********************/ |
||
| 5223 | #define SPI_CR2_RXDMAEN_Pos (0U) |
||
| 5224 | #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ |
||
| 5225 | #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ |
||
| 5226 | #define SPI_CR2_TXDMAEN_Pos (1U) |
||
| 5227 | #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ |
||
| 5228 | #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ |
||
| 5229 | #define SPI_CR2_SSOE_Pos (2U) |
||
| 5230 | #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ |
||
| 5231 | #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ |
||
| 5232 | #define SPI_CR2_ERRIE_Pos (5U) |
||
| 5233 | #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ |
||
| 5234 | #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ |
||
| 5235 | #define SPI_CR2_RXNEIE_Pos (6U) |
||
| 5236 | #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ |
||
| 5237 | #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ |
||
| 5238 | #define SPI_CR2_TXEIE_Pos (7U) |
||
| 5239 | #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ |
||
| 5240 | #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ |
||
| 5241 | |||
| 5242 | /******************** Bit definition for SPI_SR register ********************/ |
||
| 5243 | #define SPI_SR_RXNE_Pos (0U) |
||
| 5244 | #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ |
||
| 5245 | #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ |
||
| 5246 | #define SPI_SR_TXE_Pos (1U) |
||
| 5247 | #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ |
||
| 5248 | #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ |
||
| 5249 | #define SPI_SR_CHSIDE_Pos (2U) |
||
| 5250 | #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ |
||
| 5251 | #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ |
||
| 5252 | #define SPI_SR_UDR_Pos (3U) |
||
| 5253 | #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ |
||
| 5254 | #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ |
||
| 5255 | #define SPI_SR_CRCERR_Pos (4U) |
||
| 5256 | #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ |
||
| 5257 | #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ |
||
| 5258 | #define SPI_SR_MODF_Pos (5U) |
||
| 5259 | #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ |
||
| 5260 | #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ |
||
| 5261 | #define SPI_SR_OVR_Pos (6U) |
||
| 5262 | #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ |
||
| 5263 | #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ |
||
| 5264 | #define SPI_SR_BSY_Pos (7U) |
||
| 5265 | #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ |
||
| 5266 | #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ |
||
| 5267 | |||
| 5268 | /******************** Bit definition for SPI_DR register ********************/ |
||
| 5269 | #define SPI_DR_DR_Pos (0U) |
||
| 5270 | #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ |
||
| 5271 | #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ |
||
| 5272 | |||
| 5273 | /******************* Bit definition for SPI_CRCPR register ******************/ |
||
| 5274 | #define SPI_CRCPR_CRCPOLY_Pos (0U) |
||
| 5275 | #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ |
||
| 5276 | #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ |
||
| 5277 | |||
| 5278 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
||
| 5279 | #define SPI_RXCRCR_RXCRC_Pos (0U) |
||
| 5280 | #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ |
||
| 5281 | #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ |
||
| 5282 | |||
| 5283 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
||
| 5284 | #define SPI_TXCRCR_TXCRC_Pos (0U) |
||
| 5285 | #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ |
||
| 5286 | #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ |
||
| 5287 | |||
| 5288 | |||
| 5289 | |||
| 5290 | /******************************************************************************/ |
||
| 5291 | /* */ |
||
| 5292 | /* Inter-integrated Circuit Interface */ |
||
| 5293 | /* */ |
||
| 5294 | /******************************************************************************/ |
||
| 5295 | |||
| 5296 | /******************* Bit definition for I2C_CR1 register ********************/ |
||
| 5297 | #define I2C_CR1_PE_Pos (0U) |
||
| 5298 | #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
||
| 5299 | #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ |
||
| 5300 | #define I2C_CR1_SMBUS_Pos (1U) |
||
| 5301 | #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ |
||
| 5302 | #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ |
||
| 5303 | #define I2C_CR1_SMBTYPE_Pos (3U) |
||
| 5304 | #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ |
||
| 5305 | #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ |
||
| 5306 | #define I2C_CR1_ENARP_Pos (4U) |
||
| 5307 | #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ |
||
| 5308 | #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ |
||
| 5309 | #define I2C_CR1_ENPEC_Pos (5U) |
||
| 5310 | #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ |
||
| 5311 | #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ |
||
| 5312 | #define I2C_CR1_ENGC_Pos (6U) |
||
| 5313 | #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ |
||
| 5314 | #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ |
||
| 5315 | #define I2C_CR1_NOSTRETCH_Pos (7U) |
||
| 5316 | #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ |
||
| 5317 | #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ |
||
| 5318 | #define I2C_CR1_START_Pos (8U) |
||
| 5319 | #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ |
||
| 5320 | #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ |
||
| 5321 | #define I2C_CR1_STOP_Pos (9U) |
||
| 5322 | #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ |
||
| 5323 | #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ |
||
| 5324 | #define I2C_CR1_ACK_Pos (10U) |
||
| 5325 | #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ |
||
| 5326 | #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ |
||
| 5327 | #define I2C_CR1_POS_Pos (11U) |
||
| 5328 | #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ |
||
| 5329 | #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ |
||
| 5330 | #define I2C_CR1_PEC_Pos (12U) |
||
| 5331 | #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ |
||
| 5332 | #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ |
||
| 5333 | #define I2C_CR1_ALERT_Pos (13U) |
||
| 5334 | #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ |
||
| 5335 | #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ |
||
| 5336 | #define I2C_CR1_SWRST_Pos (15U) |
||
| 5337 | #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ |
||
| 5338 | #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ |
||
| 5339 | |||
| 5340 | /******************* Bit definition for I2C_CR2 register ********************/ |
||
| 5341 | #define I2C_CR2_FREQ_Pos (0U) |
||
| 5342 | #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ |
||
| 5343 | #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ |
||
| 5344 | #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ |
||
| 5345 | #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ |
||
| 5346 | #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ |
||
| 5347 | #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ |
||
| 5348 | #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ |
||
| 5349 | #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ |
||
| 5350 | |||
| 5351 | #define I2C_CR2_ITERREN_Pos (8U) |
||
| 5352 | #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ |
||
| 5353 | #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ |
||
| 5354 | #define I2C_CR2_ITEVTEN_Pos (9U) |
||
| 5355 | #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ |
||
| 5356 | #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ |
||
| 5357 | #define I2C_CR2_ITBUFEN_Pos (10U) |
||
| 5358 | #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ |
||
| 5359 | #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ |
||
| 5360 | #define I2C_CR2_DMAEN_Pos (11U) |
||
| 5361 | #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ |
||
| 5362 | #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ |
||
| 5363 | #define I2C_CR2_LAST_Pos (12U) |
||
| 5364 | #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ |
||
| 5365 | #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ |
||
| 5366 | |||
| 5367 | /******************* Bit definition for I2C_OAR1 register *******************/ |
||
| 5368 | #define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */ |
||
| 5369 | #define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */ |
||
| 5370 | |||
| 5371 | #define I2C_OAR1_ADD0_Pos (0U) |
||
| 5372 | #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ |
||
| 5373 | #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ |
||
| 5374 | #define I2C_OAR1_ADD1_Pos (1U) |
||
| 5375 | #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ |
||
| 5376 | #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ |
||
| 5377 | #define I2C_OAR1_ADD2_Pos (2U) |
||
| 5378 | #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ |
||
| 5379 | #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ |
||
| 5380 | #define I2C_OAR1_ADD3_Pos (3U) |
||
| 5381 | #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ |
||
| 5382 | #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ |
||
| 5383 | #define I2C_OAR1_ADD4_Pos (4U) |
||
| 5384 | #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ |
||
| 5385 | #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ |
||
| 5386 | #define I2C_OAR1_ADD5_Pos (5U) |
||
| 5387 | #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ |
||
| 5388 | #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ |
||
| 5389 | #define I2C_OAR1_ADD6_Pos (6U) |
||
| 5390 | #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ |
||
| 5391 | #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ |
||
| 5392 | #define I2C_OAR1_ADD7_Pos (7U) |
||
| 5393 | #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ |
||
| 5394 | #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ |
||
| 5395 | #define I2C_OAR1_ADD8_Pos (8U) |
||
| 5396 | #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ |
||
| 5397 | #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ |
||
| 5398 | #define I2C_OAR1_ADD9_Pos (9U) |
||
| 5399 | #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ |
||
| 5400 | #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ |
||
| 5401 | |||
| 5402 | #define I2C_OAR1_ADDMODE_Pos (15U) |
||
| 5403 | #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ |
||
| 5404 | #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ |
||
| 5405 | |||
| 5406 | /******************* Bit definition for I2C_OAR2 register *******************/ |
||
| 5407 | #define I2C_OAR2_ENDUAL_Pos (0U) |
||
| 5408 | #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ |
||
| 5409 | #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ |
||
| 5410 | #define I2C_OAR2_ADD2_Pos (1U) |
||
| 5411 | #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ |
||
| 5412 | #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ |
||
| 5413 | |||
| 5414 | /******************** Bit definition for I2C_DR register ********************/ |
||
| 5415 | #define I2C_DR_DR_Pos (0U) |
||
| 5416 | #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */ |
||
| 5417 | #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ |
||
| 5418 | |||
| 5419 | /******************* Bit definition for I2C_SR1 register ********************/ |
||
| 5420 | #define I2C_SR1_SB_Pos (0U) |
||
| 5421 | #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ |
||
| 5422 | #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ |
||
| 5423 | #define I2C_SR1_ADDR_Pos (1U) |
||
| 5424 | #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ |
||
| 5425 | #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ |
||
| 5426 | #define I2C_SR1_BTF_Pos (2U) |
||
| 5427 | #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ |
||
| 5428 | #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ |
||
| 5429 | #define I2C_SR1_ADD10_Pos (3U) |
||
| 5430 | #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ |
||
| 5431 | #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ |
||
| 5432 | #define I2C_SR1_STOPF_Pos (4U) |
||
| 5433 | #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ |
||
| 5434 | #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ |
||
| 5435 | #define I2C_SR1_RXNE_Pos (6U) |
||
| 5436 | #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ |
||
| 5437 | #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ |
||
| 5438 | #define I2C_SR1_TXE_Pos (7U) |
||
| 5439 | #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ |
||
| 5440 | #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ |
||
| 5441 | #define I2C_SR1_BERR_Pos (8U) |
||
| 5442 | #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ |
||
| 5443 | #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ |
||
| 5444 | #define I2C_SR1_ARLO_Pos (9U) |
||
| 5445 | #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ |
||
| 5446 | #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ |
||
| 5447 | #define I2C_SR1_AF_Pos (10U) |
||
| 5448 | #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ |
||
| 5449 | #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ |
||
| 5450 | #define I2C_SR1_OVR_Pos (11U) |
||
| 5451 | #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ |
||
| 5452 | #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ |
||
| 5453 | #define I2C_SR1_PECERR_Pos (12U) |
||
| 5454 | #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ |
||
| 5455 | #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ |
||
| 5456 | #define I2C_SR1_TIMEOUT_Pos (14U) |
||
| 5457 | #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ |
||
| 5458 | #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ |
||
| 5459 | #define I2C_SR1_SMBALERT_Pos (15U) |
||
| 5460 | #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ |
||
| 5461 | #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ |
||
| 5462 | |||
| 5463 | /******************* Bit definition for I2C_SR2 register ********************/ |
||
| 5464 | #define I2C_SR2_MSL_Pos (0U) |
||
| 5465 | #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ |
||
| 5466 | #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ |
||
| 5467 | #define I2C_SR2_BUSY_Pos (1U) |
||
| 5468 | #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ |
||
| 5469 | #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ |
||
| 5470 | #define I2C_SR2_TRA_Pos (2U) |
||
| 5471 | #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ |
||
| 5472 | #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ |
||
| 5473 | #define I2C_SR2_GENCALL_Pos (4U) |
||
| 5474 | #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ |
||
| 5475 | #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ |
||
| 5476 | #define I2C_SR2_SMBDEFAULT_Pos (5U) |
||
| 5477 | #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ |
||
| 5478 | #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ |
||
| 5479 | #define I2C_SR2_SMBHOST_Pos (6U) |
||
| 5480 | #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ |
||
| 5481 | #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ |
||
| 5482 | #define I2C_SR2_DUALF_Pos (7U) |
||
| 5483 | #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ |
||
| 5484 | #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ |
||
| 5485 | #define I2C_SR2_PEC_Pos (8U) |
||
| 5486 | #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ |
||
| 5487 | #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ |
||
| 5488 | |||
| 5489 | /******************* Bit definition for I2C_CCR register ********************/ |
||
| 5490 | #define I2C_CCR_CCR_Pos (0U) |
||
| 5491 | #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ |
||
| 5492 | #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ |
||
| 5493 | #define I2C_CCR_DUTY_Pos (14U) |
||
| 5494 | #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ |
||
| 5495 | #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ |
||
| 5496 | #define I2C_CCR_FS_Pos (15U) |
||
| 5497 | #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ |
||
| 5498 | #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ |
||
| 5499 | |||
| 5500 | /****************** Bit definition for I2C_TRISE register *******************/ |
||
| 5501 | #define I2C_TRISE_TRISE_Pos (0U) |
||
| 5502 | #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ |
||
| 5503 | #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ |
||
| 5504 | |||
| 5505 | /******************************************************************************/ |
||
| 5506 | /* */ |
||
| 5507 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
||
| 5508 | /* */ |
||
| 5509 | /******************************************************************************/ |
||
| 5510 | |||
| 5511 | /******************* Bit definition for USART_SR register *******************/ |
||
| 5512 | #define USART_SR_PE_Pos (0U) |
||
| 5513 | #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */ |
||
| 5514 | #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ |
||
| 5515 | #define USART_SR_FE_Pos (1U) |
||
| 5516 | #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */ |
||
| 5517 | #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ |
||
| 5518 | #define USART_SR_NE_Pos (2U) |
||
| 5519 | #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */ |
||
| 5520 | #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ |
||
| 5521 | #define USART_SR_ORE_Pos (3U) |
||
| 5522 | #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */ |
||
| 5523 | #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ |
||
| 5524 | #define USART_SR_IDLE_Pos (4U) |
||
| 5525 | #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */ |
||
| 5526 | #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ |
||
| 5527 | #define USART_SR_RXNE_Pos (5U) |
||
| 5528 | #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */ |
||
| 5529 | #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ |
||
| 5530 | #define USART_SR_TC_Pos (6U) |
||
| 5531 | #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */ |
||
| 5532 | #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ |
||
| 5533 | #define USART_SR_TXE_Pos (7U) |
||
| 5534 | #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */ |
||
| 5535 | #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ |
||
| 5536 | #define USART_SR_LBD_Pos (8U) |
||
| 5537 | #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */ |
||
| 5538 | #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ |
||
| 5539 | #define USART_SR_CTS_Pos (9U) |
||
| 5540 | #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */ |
||
| 5541 | #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ |
||
| 5542 | |||
| 5543 | /******************* Bit definition for USART_DR register *******************/ |
||
| 5544 | #define USART_DR_DR_Pos (0U) |
||
| 5545 | #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */ |
||
| 5546 | #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ |
||
| 5547 | |||
| 5548 | /****************** Bit definition for USART_BRR register *******************/ |
||
| 5549 | #define USART_BRR_DIV_Fraction_Pos (0U) |
||
| 5550 | #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ |
||
| 5551 | #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ |
||
| 5552 | #define USART_BRR_DIV_Mantissa_Pos (4U) |
||
| 5553 | #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ |
||
| 5554 | #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ |
||
| 5555 | |||
| 5556 | /****************** Bit definition for USART_CR1 register *******************/ |
||
| 5557 | #define USART_CR1_SBK_Pos (0U) |
||
| 5558 | #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */ |
||
| 5559 | #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ |
||
| 5560 | #define USART_CR1_RWU_Pos (1U) |
||
| 5561 | #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */ |
||
| 5562 | #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ |
||
| 5563 | #define USART_CR1_RE_Pos (2U) |
||
| 5564 | #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ |
||
| 5565 | #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ |
||
| 5566 | #define USART_CR1_TE_Pos (3U) |
||
| 5567 | #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ |
||
| 5568 | #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ |
||
| 5569 | #define USART_CR1_IDLEIE_Pos (4U) |
||
| 5570 | #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ |
||
| 5571 | #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ |
||
| 5572 | #define USART_CR1_RXNEIE_Pos (5U) |
||
| 5573 | #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ |
||
| 5574 | #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ |
||
| 5575 | #define USART_CR1_TCIE_Pos (6U) |
||
| 5576 | #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ |
||
| 5577 | #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ |
||
| 5578 | #define USART_CR1_TXEIE_Pos (7U) |
||
| 5579 | #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ |
||
| 5580 | #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ |
||
| 5581 | #define USART_CR1_PEIE_Pos (8U) |
||
| 5582 | #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ |
||
| 5583 | #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ |
||
| 5584 | #define USART_CR1_PS_Pos (9U) |
||
| 5585 | #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ |
||
| 5586 | #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ |
||
| 5587 | #define USART_CR1_PCE_Pos (10U) |
||
| 5588 | #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ |
||
| 5589 | #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ |
||
| 5590 | #define USART_CR1_WAKE_Pos (11U) |
||
| 5591 | #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ |
||
| 5592 | #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ |
||
| 5593 | #define USART_CR1_M_Pos (12U) |
||
| 5594 | #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ |
||
| 5595 | #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ |
||
| 5596 | #define USART_CR1_UE_Pos (13U) |
||
| 5597 | #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */ |
||
| 5598 | #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ |
||
| 5599 | #define USART_CR1_OVER8_Pos (15U) |
||
| 5600 | #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ |
||
| 5601 | #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< USART Oversmapling 8-bits */ |
||
| 5602 | |||
| 5603 | /****************** Bit definition for USART_CR2 register *******************/ |
||
| 5604 | #define USART_CR2_ADD_Pos (0U) |
||
| 5605 | #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */ |
||
| 5606 | #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ |
||
| 5607 | #define USART_CR2_LBDL_Pos (5U) |
||
| 5608 | #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ |
||
| 5609 | #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ |
||
| 5610 | #define USART_CR2_LBDIE_Pos (6U) |
||
| 5611 | #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ |
||
| 5612 | #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ |
||
| 5613 | #define USART_CR2_LBCL_Pos (8U) |
||
| 5614 | #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ |
||
| 5615 | #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ |
||
| 5616 | #define USART_CR2_CPHA_Pos (9U) |
||
| 5617 | #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ |
||
| 5618 | #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ |
||
| 5619 | #define USART_CR2_CPOL_Pos (10U) |
||
| 5620 | #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ |
||
| 5621 | #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ |
||
| 5622 | #define USART_CR2_CLKEN_Pos (11U) |
||
| 5623 | #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ |
||
| 5624 | #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ |
||
| 5625 | |||
| 5626 | #define USART_CR2_STOP_Pos (12U) |
||
| 5627 | #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ |
||
| 5628 | #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ |
||
| 5629 | #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ |
||
| 5630 | #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ |
||
| 5631 | |||
| 5632 | #define USART_CR2_LINEN_Pos (14U) |
||
| 5633 | #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ |
||
| 5634 | #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ |
||
| 5635 | |||
| 5636 | /****************** Bit definition for USART_CR3 register *******************/ |
||
| 5637 | #define USART_CR3_EIE_Pos (0U) |
||
| 5638 | #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ |
||
| 5639 | #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ |
||
| 5640 | #define USART_CR3_IREN_Pos (1U) |
||
| 5641 | #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ |
||
| 5642 | #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ |
||
| 5643 | #define USART_CR3_IRLP_Pos (2U) |
||
| 5644 | #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ |
||
| 5645 | #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ |
||
| 5646 | #define USART_CR3_HDSEL_Pos (3U) |
||
| 5647 | #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ |
||
| 5648 | #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ |
||
| 5649 | #define USART_CR3_NACK_Pos (4U) |
||
| 5650 | #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ |
||
| 5651 | #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ |
||
| 5652 | #define USART_CR3_SCEN_Pos (5U) |
||
| 5653 | #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ |
||
| 5654 | #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ |
||
| 5655 | #define USART_CR3_DMAR_Pos (6U) |
||
| 5656 | #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ |
||
| 5657 | #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ |
||
| 5658 | #define USART_CR3_DMAT_Pos (7U) |
||
| 5659 | #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ |
||
| 5660 | #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ |
||
| 5661 | #define USART_CR3_RTSE_Pos (8U) |
||
| 5662 | #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ |
||
| 5663 | #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ |
||
| 5664 | #define USART_CR3_CTSE_Pos (9U) |
||
| 5665 | #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ |
||
| 5666 | #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ |
||
| 5667 | #define USART_CR3_CTSIE_Pos (10U) |
||
| 5668 | #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ |
||
| 5669 | #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ |
||
| 5670 | #define USART_CR3_ONEBIT_Pos (11U) |
||
| 5671 | #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ |
||
| 5672 | #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One Bit method */ |
||
| 5673 | |||
| 5674 | /****************** Bit definition for USART_GTPR register ******************/ |
||
| 5675 | #define USART_GTPR_PSC_Pos (0U) |
||
| 5676 | #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ |
||
| 5677 | #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ |
||
| 5678 | #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ |
||
| 5679 | #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ |
||
| 5680 | #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ |
||
| 5681 | #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ |
||
| 5682 | #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ |
||
| 5683 | #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ |
||
| 5684 | #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ |
||
| 5685 | #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ |
||
| 5686 | |||
| 5687 | #define USART_GTPR_GT_Pos (8U) |
||
| 5688 | #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ |
||
| 5689 | #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ |
||
| 5690 | |||
| 5691 | /******************************************************************************/ |
||
| 5692 | /* */ |
||
| 5693 | /* Debug MCU */ |
||
| 5694 | /* */ |
||
| 5695 | /******************************************************************************/ |
||
| 5696 | |||
| 5697 | /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
||
| 5698 | #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
||
| 5699 | #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
||
| 5700 | #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ |
||
| 5701 | |||
| 5702 | #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
||
| 5703 | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
||
| 5704 | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ |
||
| 5705 | #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ |
||
| 5706 | #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ |
||
| 5707 | #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ |
||
| 5708 | #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ |
||
| 5709 | #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ |
||
| 5710 | #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ |
||
| 5711 | #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ |
||
| 5712 | #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ |
||
| 5713 | #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ |
||
| 5714 | #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ |
||
| 5715 | #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ |
||
| 5716 | #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ |
||
| 5717 | #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ |
||
| 5718 | #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ |
||
| 5719 | #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ |
||
| 5720 | #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ |
||
| 5721 | |||
| 5722 | /****************** Bit definition for DBGMCU_CR register *******************/ |
||
| 5723 | #define DBGMCU_CR_DBG_SLEEP_Pos (0U) |
||
| 5724 | #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ |
||
| 5725 | #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ |
||
| 5726 | #define DBGMCU_CR_DBG_STOP_Pos (1U) |
||
| 5727 | #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
||
| 5728 | #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ |
||
| 5729 | #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
||
| 5730 | #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
||
| 5731 | #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ |
||
| 5732 | #define DBGMCU_CR_TRACE_IOEN_Pos (5U) |
||
| 5733 | #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ |
||
| 5734 | #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ |
||
| 5735 | |||
| 5736 | #define DBGMCU_CR_TRACE_MODE_Pos (6U) |
||
| 5737 | #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ |
||
| 5738 | #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
||
| 5739 | #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ |
||
| 5740 | #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ |
||
| 5741 | |||
| 5742 | #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) |
||
| 5743 | #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ |
||
| 5744 | #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ |
||
| 5745 | #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) |
||
| 5746 | #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ |
||
| 5747 | #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ |
||
| 5748 | #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) |
||
| 5749 | #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */ |
||
| 5750 | #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ |
||
| 5751 | #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) |
||
| 5752 | #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ |
||
| 5753 | #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ |
||
| 5754 | #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) |
||
| 5755 | #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ |
||
| 5756 | #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ |
||
| 5757 | #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U) |
||
| 5758 | #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */ |
||
| 5759 | #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ |
||
| 5760 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) |
||
| 5761 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ |
||
| 5762 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
||
| 5763 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) |
||
| 5764 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */ |
||
| 5765 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
||
| 5766 | #define DBGMCU_CR_DBG_TIM15_STOP_Pos (22U) |
||
| 5767 | #define DBGMCU_CR_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM15_STOP_Pos) /*!< 0x00400000 */ |
||
| 5768 | #define DBGMCU_CR_DBG_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP_Msk /*!< Debug TIM15 stopped when Core is halted */ |
||
| 5769 | #define DBGMCU_CR_DBG_TIM16_STOP_Pos (23U) |
||
| 5770 | #define DBGMCU_CR_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM16_STOP_Pos) /*!< 0x00800000 */ |
||
| 5771 | #define DBGMCU_CR_DBG_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP_Msk /*!< Debug TIM16 stopped when Core is halted */ |
||
| 5772 | #define DBGMCU_CR_DBG_TIM17_STOP_Pos (24U) |
||
| 5773 | #define DBGMCU_CR_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM17_STOP_Pos) /*!< 0x01000000 */ |
||
| 5774 | #define DBGMCU_CR_DBG_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP_Msk /*!< Debug TIM17 stopped when Core is halted */ |
||
| 5775 | |||
| 5776 | /******************************************************************************/ |
||
| 5777 | /* */ |
||
| 5778 | /* FLASH and Option Bytes Registers */ |
||
| 5779 | /* */ |
||
| 5780 | /******************************************************************************/ |
||
| 5781 | /******************* Bit definition for FLASH_ACR register ******************/ |
||
| 5782 | #define FLASH_ACR_HLFCYA_Pos (3U) |
||
| 5783 | #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ |
||
| 5784 | #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ |
||
| 5785 | |||
| 5786 | /****************** Bit definition for FLASH_KEYR register ******************/ |
||
| 5787 | #define FLASH_KEYR_FKEYR_Pos (0U) |
||
| 5788 | #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ |
||
| 5789 | #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ |
||
| 5790 | |||
| 5791 | #define RDP_KEY_Pos (0U) |
||
| 5792 | #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */ |
||
| 5793 | #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ |
||
| 5794 | #define FLASH_KEY1_Pos (0U) |
||
| 5795 | #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ |
||
| 5796 | #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ |
||
| 5797 | #define FLASH_KEY2_Pos (0U) |
||
| 5798 | #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ |
||
| 5799 | #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ |
||
| 5800 | |||
| 5801 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
||
| 5802 | #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) |
||
| 5803 | #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ |
||
| 5804 | #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ |
||
| 5805 | |||
| 5806 | #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ |
||
| 5807 | #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ |
||
| 5808 | |||
| 5809 | /****************** Bit definition for FLASH_SR register ********************/ |
||
| 5810 | #define FLASH_SR_BSY_Pos (0U) |
||
| 5811 | #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ |
||
| 5812 | #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ |
||
| 5813 | #define FLASH_SR_PGERR_Pos (2U) |
||
| 5814 | #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ |
||
| 5815 | #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ |
||
| 5816 | #define FLASH_SR_WRPRTERR_Pos (4U) |
||
| 5817 | #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ |
||
| 5818 | #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ |
||
| 5819 | #define FLASH_SR_EOP_Pos (5U) |
||
| 5820 | #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ |
||
| 5821 | #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ |
||
| 5822 | |||
| 5823 | /******************* Bit definition for FLASH_CR register *******************/ |
||
| 5824 | #define FLASH_CR_PG_Pos (0U) |
||
| 5825 | #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ |
||
| 5826 | #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ |
||
| 5827 | #define FLASH_CR_PER_Pos (1U) |
||
| 5828 | #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */ |
||
| 5829 | #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ |
||
| 5830 | #define FLASH_CR_MER_Pos (2U) |
||
| 5831 | #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ |
||
| 5832 | #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ |
||
| 5833 | #define FLASH_CR_OPTPG_Pos (4U) |
||
| 5834 | #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ |
||
| 5835 | #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ |
||
| 5836 | #define FLASH_CR_OPTER_Pos (5U) |
||
| 5837 | #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ |
||
| 5838 | #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ |
||
| 5839 | #define FLASH_CR_STRT_Pos (6U) |
||
| 5840 | #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ |
||
| 5841 | #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ |
||
| 5842 | #define FLASH_CR_LOCK_Pos (7U) |
||
| 5843 | #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ |
||
| 5844 | #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ |
||
| 5845 | #define FLASH_CR_OPTWRE_Pos (9U) |
||
| 5846 | #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ |
||
| 5847 | #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ |
||
| 5848 | #define FLASH_CR_ERRIE_Pos (10U) |
||
| 5849 | #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ |
||
| 5850 | #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ |
||
| 5851 | #define FLASH_CR_EOPIE_Pos (12U) |
||
| 5852 | #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ |
||
| 5853 | #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ |
||
| 5854 | |||
| 5855 | /******************* Bit definition for FLASH_AR register *******************/ |
||
| 5856 | #define FLASH_AR_FAR_Pos (0U) |
||
| 5857 | #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ |
||
| 5858 | #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ |
||
| 5859 | |||
| 5860 | /****************** Bit definition for FLASH_OBR register *******************/ |
||
| 5861 | #define FLASH_OBR_OPTERR_Pos (0U) |
||
| 5862 | #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ |
||
| 5863 | #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ |
||
| 5864 | #define FLASH_OBR_RDPRT_Pos (1U) |
||
| 5865 | #define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ |
||
| 5866 | #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ |
||
| 5867 | |||
| 5868 | #define FLASH_OBR_IWDG_SW_Pos (2U) |
||
| 5869 | #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ |
||
| 5870 | #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ |
||
| 5871 | #define FLASH_OBR_nRST_STOP_Pos (3U) |
||
| 5872 | #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ |
||
| 5873 | #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ |
||
| 5874 | #define FLASH_OBR_nRST_STDBY_Pos (4U) |
||
| 5875 | #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ |
||
| 5876 | #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ |
||
| 5877 | #define FLASH_OBR_USER_Pos (2U) |
||
| 5878 | #define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ |
||
| 5879 | #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ |
||
| 5880 | #define FLASH_OBR_DATA0_Pos (10U) |
||
| 5881 | #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ |
||
| 5882 | #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ |
||
| 5883 | #define FLASH_OBR_DATA1_Pos (18U) |
||
| 5884 | #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ |
||
| 5885 | #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ |
||
| 5886 | |||
| 5887 | /****************** Bit definition for FLASH_WRPR register ******************/ |
||
| 5888 | #define FLASH_WRPR_WRP_Pos (0U) |
||
| 5889 | #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ |
||
| 5890 | #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ |
||
| 5891 | |||
| 5892 | /*----------------------------------------------------------------------------*/ |
||
| 5893 | |||
| 5894 | /****************** Bit definition for FLASH_RDP register *******************/ |
||
| 5895 | #define FLASH_RDP_RDP_Pos (0U) |
||
| 5896 | #define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ |
||
| 5897 | #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ |
||
| 5898 | #define FLASH_RDP_nRDP_Pos (8U) |
||
| 5899 | #define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ |
||
| 5900 | #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ |
||
| 5901 | |||
| 5902 | /****************** Bit definition for FLASH_USER register ******************/ |
||
| 5903 | #define FLASH_USER_USER_Pos (16U) |
||
| 5904 | #define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ |
||
| 5905 | #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ |
||
| 5906 | #define FLASH_USER_nUSER_Pos (24U) |
||
| 5907 | #define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ |
||
| 5908 | #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ |
||
| 5909 | |||
| 5910 | /****************** Bit definition for FLASH_Data0 register *****************/ |
||
| 5911 | #define FLASH_DATA0_DATA0_Pos (0U) |
||
| 5912 | #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ |
||
| 5913 | #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ |
||
| 5914 | #define FLASH_DATA0_nDATA0_Pos (8U) |
||
| 5915 | #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ |
||
| 5916 | #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ |
||
| 5917 | |||
| 5918 | /****************** Bit definition for FLASH_Data1 register *****************/ |
||
| 5919 | #define FLASH_DATA1_DATA1_Pos (16U) |
||
| 5920 | #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ |
||
| 5921 | #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ |
||
| 5922 | #define FLASH_DATA1_nDATA1_Pos (24U) |
||
| 5923 | #define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ |
||
| 5924 | #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ |
||
| 5925 | |||
| 5926 | /****************** Bit definition for FLASH_WRP0 register ******************/ |
||
| 5927 | #define FLASH_WRP0_WRP0_Pos (0U) |
||
| 5928 | #define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ |
||
| 5929 | #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ |
||
| 5930 | #define FLASH_WRP0_nWRP0_Pos (8U) |
||
| 5931 | #define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ |
||
| 5932 | #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ |
||
| 5933 | |||
| 5934 | /****************** Bit definition for FLASH_WRP1 register ******************/ |
||
| 5935 | #define FLASH_WRP1_WRP1_Pos (16U) |
||
| 5936 | #define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ |
||
| 5937 | #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ |
||
| 5938 | #define FLASH_WRP1_nWRP1_Pos (24U) |
||
| 5939 | #define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ |
||
| 5940 | #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ |
||
| 5941 | |||
| 5942 | /****************** Bit definition for FLASH_WRP2 register ******************/ |
||
| 5943 | #define FLASH_WRP2_WRP2_Pos (0U) |
||
| 5944 | #define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */ |
||
| 5945 | #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ |
||
| 5946 | #define FLASH_WRP2_nWRP2_Pos (8U) |
||
| 5947 | #define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ |
||
| 5948 | #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ |
||
| 5949 | |||
| 5950 | /****************** Bit definition for FLASH_WRP3 register ******************/ |
||
| 5951 | #define FLASH_WRP3_WRP3_Pos (16U) |
||
| 5952 | #define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ |
||
| 5953 | #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ |
||
| 5954 | #define FLASH_WRP3_nWRP3_Pos (24U) |
||
| 5955 | #define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ |
||
| 5956 | #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ |
||
| 5957 | |||
| 5958 | |||
| 5959 | |||
| 5960 | /** |
||
| 5961 | * @} |
||
| 5962 | */ |
||
| 5963 | |||
| 5964 | /** |
||
| 5965 | * @} |
||
| 5966 | */ |
||
| 5967 | |||
| 5968 | /** @addtogroup Exported_macro |
||
| 5969 | * @{ |
||
| 5970 | */ |
||
| 5971 | |||
| 5972 | /****************************** ADC Instances *********************************/ |
||
| 5973 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1)) |
||
| 5974 | |||
| 5975 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) |
||
| 5976 | |||
| 5977 | #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
||
| 5978 | |||
| 5979 | /****************************** CEC Instances *********************************/ |
||
| 5980 | #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC) |
||
| 5981 | |||
| 5982 | /****************************** CRC Instances *********************************/ |
||
| 5983 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
||
| 5984 | |||
| 5985 | /****************************** DAC Instances *********************************/ |
||
| 5986 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
||
| 5987 | |||
| 5988 | /****************************** DMA Instances *********************************/ |
||
| 5989 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
||
| 5990 | ((INSTANCE) == DMA1_Channel2) || \ |
||
| 5991 | ((INSTANCE) == DMA1_Channel3) || \ |
||
| 5992 | ((INSTANCE) == DMA1_Channel4) || \ |
||
| 5993 | ((INSTANCE) == DMA1_Channel5) || \ |
||
| 5994 | ((INSTANCE) == DMA1_Channel6) || \ |
||
| 5995 | ((INSTANCE) == DMA1_Channel7)) |
||
| 5996 | |||
| 5997 | /******************************* GPIO Instances *******************************/ |
||
| 5998 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
||
| 5999 | ((INSTANCE) == GPIOB) || \ |
||
| 6000 | ((INSTANCE) == GPIOC) || \ |
||
| 6001 | ((INSTANCE) == GPIOD) || \ |
||
| 6002 | ((INSTANCE) == GPIOE)) |
||
| 6003 | |||
| 6004 | /**************************** GPIO Alternate Function Instances ***************/ |
||
| 6005 | #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
||
| 6006 | |||
| 6007 | /**************************** GPIO Lock Instances *****************************/ |
||
| 6008 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
||
| 6009 | |||
| 6010 | /******************************** I2C Instances *******************************/ |
||
| 6011 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
||
| 6012 | ((INSTANCE) == I2C2)) |
||
| 6013 | |||
| 6014 | /******************************* SMBUS Instances ******************************/ |
||
| 6015 | #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE |
||
| 6016 | |||
| 6017 | /****************************** IWDG Instances ********************************/ |
||
| 6018 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
||
| 6019 | |||
| 6020 | /******************************** SPI Instances *******************************/ |
||
| 6021 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
||
| 6022 | ((INSTANCE) == SPI2)) |
||
| 6023 | |||
| 6024 | /****************************** START TIM Instances ***************************/ |
||
| 6025 | /****************************** TIM Instances *********************************/ |
||
| 6026 | #define IS_TIM_INSTANCE(INSTANCE)\ |
||
| 6027 | (((INSTANCE) == TIM1) || \ |
||
| 6028 | ((INSTANCE) == TIM2) || \ |
||
| 6029 | ((INSTANCE) == TIM3) || \ |
||
| 6030 | ((INSTANCE) == TIM4) || \ |
||
| 6031 | ((INSTANCE) == TIM6) || \ |
||
| 6032 | ((INSTANCE) == TIM7) || \ |
||
| 6033 | ((INSTANCE) == TIM15) || \ |
||
| 6034 | ((INSTANCE) == TIM16) || \ |
||
| 6035 | ((INSTANCE) == TIM17)) |
||
| 6036 | |||
| 6037 | #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) |
||
| 6038 | |||
| 6039 | #define IS_TIM_CC1_INSTANCE(INSTANCE)\ |
||
| 6040 | (((INSTANCE) == TIM1) || \ |
||
| 6041 | ((INSTANCE) == TIM2) || \ |
||
| 6042 | ((INSTANCE) == TIM3) || \ |
||
| 6043 | ((INSTANCE) == TIM4) || \ |
||
| 6044 | ((INSTANCE) == TIM15) || \ |
||
| 6045 | ((INSTANCE) == TIM16) || \ |
||
| 6046 | ((INSTANCE) == TIM17)) |
||
| 6047 | |||
| 6048 | #define IS_TIM_CC2_INSTANCE(INSTANCE)\ |
||
| 6049 | (((INSTANCE) == TIM1) || \ |
||
| 6050 | ((INSTANCE) == TIM2) || \ |
||
| 6051 | ((INSTANCE) == TIM3) || \ |
||
| 6052 | ((INSTANCE) == TIM4) || \ |
||
| 6053 | ((INSTANCE) == TIM15)) |
||
| 6054 | |||
| 6055 | #define IS_TIM_CC3_INSTANCE(INSTANCE)\ |
||
| 6056 | (((INSTANCE) == TIM1) || \ |
||
| 6057 | ((INSTANCE) == TIM2) || \ |
||
| 6058 | ((INSTANCE) == TIM3) || \ |
||
| 6059 | ((INSTANCE) == TIM4)) |
||
| 6060 | |||
| 6061 | #define IS_TIM_CC4_INSTANCE(INSTANCE)\ |
||
| 6062 | (((INSTANCE) == TIM1) || \ |
||
| 6063 | ((INSTANCE) == TIM2) || \ |
||
| 6064 | ((INSTANCE) == TIM3) || \ |
||
| 6065 | ((INSTANCE) == TIM4)) |
||
| 6066 | |||
| 6067 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ |
||
| 6068 | (((INSTANCE) == TIM1) || \ |
||
| 6069 | ((INSTANCE) == TIM2) || \ |
||
| 6070 | ((INSTANCE) == TIM3) || \ |
||
| 6071 | ((INSTANCE) == TIM4)) |
||
| 6072 | |||
| 6073 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ |
||
| 6074 | (((INSTANCE) == TIM1) || \ |
||
| 6075 | ((INSTANCE) == TIM2) || \ |
||
| 6076 | ((INSTANCE) == TIM3) || \ |
||
| 6077 | ((INSTANCE) == TIM4)) |
||
| 6078 | |||
| 6079 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ |
||
| 6080 | (((INSTANCE) == TIM1) || \ |
||
| 6081 | ((INSTANCE) == TIM2) || \ |
||
| 6082 | ((INSTANCE) == TIM3) || \ |
||
| 6083 | ((INSTANCE) == TIM4) || \ |
||
| 6084 | ((INSTANCE) == TIM15)) |
||
| 6085 | |||
| 6086 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ |
||
| 6087 | (((INSTANCE) == TIM1) || \ |
||
| 6088 | ((INSTANCE) == TIM2) || \ |
||
| 6089 | ((INSTANCE) == TIM3) || \ |
||
| 6090 | ((INSTANCE) == TIM4) || \ |
||
| 6091 | ((INSTANCE) == TIM15)) |
||
| 6092 | |||
| 6093 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ |
||
| 6094 | (((INSTANCE) == TIM1) || \ |
||
| 6095 | ((INSTANCE) == TIM2) || \ |
||
| 6096 | ((INSTANCE) == TIM3) || \ |
||
| 6097 | ((INSTANCE) == TIM4)) |
||
| 6098 | |||
| 6099 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ |
||
| 6100 | (((INSTANCE) == TIM1) || \ |
||
| 6101 | ((INSTANCE) == TIM2) || \ |
||
| 6102 | ((INSTANCE) == TIM3) || \ |
||
| 6103 | ((INSTANCE) == TIM4)) |
||
| 6104 | |||
| 6105 | #define IS_TIM_XOR_INSTANCE(INSTANCE)\ |
||
| 6106 | (((INSTANCE) == TIM1) || \ |
||
| 6107 | ((INSTANCE) == TIM2) || \ |
||
| 6108 | ((INSTANCE) == TIM3) || \ |
||
| 6109 | ((INSTANCE) == TIM4)) |
||
| 6110 | |||
| 6111 | #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ |
||
| 6112 | (((INSTANCE) == TIM1) || \ |
||
| 6113 | ((INSTANCE) == TIM2) || \ |
||
| 6114 | ((INSTANCE) == TIM3) || \ |
||
| 6115 | ((INSTANCE) == TIM4) || \ |
||
| 6116 | ((INSTANCE) == TIM6) || \ |
||
| 6117 | ((INSTANCE) == TIM7) || \ |
||
| 6118 | ((INSTANCE) == TIM15)) |
||
| 6119 | |||
| 6120 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ |
||
| 6121 | (((INSTANCE) == TIM1) || \ |
||
| 6122 | ((INSTANCE) == TIM2) || \ |
||
| 6123 | ((INSTANCE) == TIM3) || \ |
||
| 6124 | ((INSTANCE) == TIM4) || \ |
||
| 6125 | ((INSTANCE) == TIM15)) |
||
| 6126 | |||
| 6127 | #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) |
||
| 6128 | |||
| 6129 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ |
||
| 6130 | (((INSTANCE) == TIM1) || \ |
||
| 6131 | ((INSTANCE) == TIM2) || \ |
||
| 6132 | ((INSTANCE) == TIM3) || \ |
||
| 6133 | ((INSTANCE) == TIM4) || \ |
||
| 6134 | ((INSTANCE) == TIM15) || \ |
||
| 6135 | ((INSTANCE) == TIM16) || \ |
||
| 6136 | ((INSTANCE) == TIM17)) |
||
| 6137 | |||
| 6138 | #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ |
||
| 6139 | (((INSTANCE) == TIM1) || \ |
||
| 6140 | ((INSTANCE) == TIM15) || \ |
||
| 6141 | ((INSTANCE) == TIM16) || \ |
||
| 6142 | ((INSTANCE) == TIM17)) |
||
| 6143 | |||
| 6144 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
||
| 6145 | ((((INSTANCE) == TIM1) && \ |
||
| 6146 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6147 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6148 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6149 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6150 | || \ |
||
| 6151 | (((INSTANCE) == TIM2) && \ |
||
| 6152 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6153 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6154 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6155 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6156 | || \ |
||
| 6157 | (((INSTANCE) == TIM3) && \ |
||
| 6158 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6159 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6160 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6161 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6162 | || \ |
||
| 6163 | (((INSTANCE) == TIM4) && \ |
||
| 6164 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6165 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6166 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 6167 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 6168 | || \ |
||
| 6169 | (((INSTANCE) == TIM15) && \ |
||
| 6170 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6171 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
||
| 6172 | || \ |
||
| 6173 | (((INSTANCE) == TIM16) && \ |
||
| 6174 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
||
| 6175 | || \ |
||
| 6176 | (((INSTANCE) == TIM17) && \ |
||
| 6177 | (((CHANNEL) == TIM_CHANNEL_1)))) |
||
| 6178 | |||
| 6179 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
||
| 6180 | ((((INSTANCE) == TIM1) && \ |
||
| 6181 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 6182 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 6183 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
||
| 6184 | || \ |
||
| 6185 | (((INSTANCE) == TIM15) && \ |
||
| 6186 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
||
| 6187 | || \ |
||
| 6188 | (((INSTANCE) == TIM16) && \ |
||
| 6189 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
||
| 6190 | || \ |
||
| 6191 | (((INSTANCE) == TIM17) && \ |
||
| 6192 | ((CHANNEL) == TIM_CHANNEL_1))) |
||
| 6193 | |||
| 6194 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ |
||
| 6195 | (((INSTANCE) == TIM1) || \ |
||
| 6196 | ((INSTANCE) == TIM2) || \ |
||
| 6197 | ((INSTANCE) == TIM3) || \ |
||
| 6198 | ((INSTANCE) == TIM4)) |
||
| 6199 | |||
| 6200 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ |
||
| 6201 | (((INSTANCE) == TIM1) || \ |
||
| 6202 | ((INSTANCE) == TIM15) || \ |
||
| 6203 | ((INSTANCE) == TIM16) || \ |
||
| 6204 | ((INSTANCE) == TIM17)) |
||
| 6205 | |||
| 6206 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ |
||
| 6207 | (((INSTANCE) == TIM1) || \ |
||
| 6208 | ((INSTANCE) == TIM2) || \ |
||
| 6209 | ((INSTANCE) == TIM3) || \ |
||
| 6210 | ((INSTANCE) == TIM4) || \ |
||
| 6211 | ((INSTANCE) == TIM15) || \ |
||
| 6212 | ((INSTANCE) == TIM16) || \ |
||
| 6213 | ((INSTANCE) == TIM17)) |
||
| 6214 | |||
| 6215 | #define IS_TIM_DMA_INSTANCE(INSTANCE)\ |
||
| 6216 | (((INSTANCE) == TIM1) || \ |
||
| 6217 | ((INSTANCE) == TIM2) || \ |
||
| 6218 | ((INSTANCE) == TIM3) || \ |
||
| 6219 | ((INSTANCE) == TIM4) || \ |
||
| 6220 | ((INSTANCE) == TIM6) || \ |
||
| 6221 | ((INSTANCE) == TIM7) || \ |
||
| 6222 | ((INSTANCE) == TIM15) || \ |
||
| 6223 | ((INSTANCE) == TIM16) || \ |
||
| 6224 | ((INSTANCE) == TIM17)) |
||
| 6225 | |||
| 6226 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ |
||
| 6227 | (((INSTANCE) == TIM1) || \ |
||
| 6228 | ((INSTANCE) == TIM2) || \ |
||
| 6229 | ((INSTANCE) == TIM3) || \ |
||
| 6230 | ((INSTANCE) == TIM4) || \ |
||
| 6231 | ((INSTANCE) == TIM15) || \ |
||
| 6232 | ((INSTANCE) == TIM16) || \ |
||
| 6233 | ((INSTANCE) == TIM17)) |
||
| 6234 | |||
| 6235 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ |
||
| 6236 | (((INSTANCE) == TIM1) || \ |
||
| 6237 | ((INSTANCE) == TIM15) || \ |
||
| 6238 | ((INSTANCE) == TIM16) || \ |
||
| 6239 | ((INSTANCE) == TIM17)) |
||
| 6240 | |||
| 6241 | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
||
| 6242 | ((INSTANCE) == TIM2) || \ |
||
| 6243 | ((INSTANCE) == TIM3) || \ |
||
| 6244 | ((INSTANCE) == TIM4)) |
||
| 6245 | |||
| 6246 | #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
||
| 6247 | ((INSTANCE) == TIM2) || \ |
||
| 6248 | ((INSTANCE) == TIM3) || \ |
||
| 6249 | ((INSTANCE) == TIM4)) |
||
| 6250 | |||
| 6251 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U |
||
| 6252 | |||
| 6253 | /****************************** END TIM Instances *****************************/ |
||
| 6254 | |||
| 6255 | |||
| 6256 | /******************** USART Instances : Synchronous mode **********************/ |
||
| 6257 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6258 | ((INSTANCE) == USART2) || \ |
||
| 6259 | ((INSTANCE) == USART3)) |
||
| 6260 | |||
| 6261 | /******************** UART Instances : Asynchronous mode **********************/ |
||
| 6262 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6263 | ((INSTANCE) == USART2) || \ |
||
| 6264 | ((INSTANCE) == USART3)) |
||
| 6265 | |||
| 6266 | /******************** UART Instances : Half-Duplex mode **********************/ |
||
| 6267 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6268 | ((INSTANCE) == USART2) || \ |
||
| 6269 | ((INSTANCE) == USART3)) |
||
| 6270 | |||
| 6271 | /******************** UART Instances : LIN mode **********************/ |
||
| 6272 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6273 | ((INSTANCE) == USART2) || \ |
||
| 6274 | ((INSTANCE) == USART3)) |
||
| 6275 | |||
| 6276 | /****************** UART Instances : Hardware Flow control ********************/ |
||
| 6277 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6278 | ((INSTANCE) == USART2) || \ |
||
| 6279 | ((INSTANCE) == USART3)) |
||
| 6280 | |||
| 6281 | /********************* UART Instances : Smard card mode ***********************/ |
||
| 6282 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6283 | ((INSTANCE) == USART2) || \ |
||
| 6284 | ((INSTANCE) == USART3)) |
||
| 6285 | |||
| 6286 | /*********************** UART Instances : IRDA mode ***************************/ |
||
| 6287 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6288 | ((INSTANCE) == USART2) || \ |
||
| 6289 | ((INSTANCE) == USART3)) |
||
| 6290 | |||
| 6291 | /***************** UART Instances : Multi-Processor mode **********************/ |
||
| 6292 | #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6293 | ((INSTANCE) == USART2) || \ |
||
| 6294 | ((INSTANCE) == USART3)) |
||
| 6295 | |||
| 6296 | /***************** UART Instances : DMA mode available **********************/ |
||
| 6297 | #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 6298 | ((INSTANCE) == USART2) || \ |
||
| 6299 | ((INSTANCE) == USART3)) |
||
| 6300 | |||
| 6301 | /****************************** RTC Instances *********************************/ |
||
| 6302 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
||
| 6303 | |||
| 6304 | /**************************** WWDG Instances *****************************/ |
||
| 6305 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
||
| 6306 | |||
| 6307 | |||
| 6308 | |||
| 6309 | |||
| 6310 | #define RCC_HSE_MIN 4000000U |
||
| 6311 | #define RCC_HSE_MAX 26000000U |
||
| 6312 | |||
| 6313 | #define RCC_MAX_FREQUENCY 24000000U |
||
| 6314 | |||
| 6315 | /** |
||
| 6316 | * @} |
||
| 6317 | */ |
||
| 6318 | /******************************************************************************/ |
||
| 6319 | /* For a painless codes migration between the STM32F1xx device product */ |
||
| 6320 | /* lines, the aliases defined below are put in place to overcome the */ |
||
| 6321 | /* differences in the interrupt handlers and IRQn definitions. */ |
||
| 6322 | /* No need to update developed interrupt code when moving across */ |
||
| 6323 | /* product lines within the same STM32F1 Family */ |
||
| 6324 | /******************************************************************************/ |
||
| 6325 | |||
| 6326 | /* Aliases for __IRQn */ |
||
| 6327 | #define ADC1_2_IRQn ADC1_IRQn |
||
| 6328 | #define OTG_FS_WKUP_IRQn CEC_IRQn |
||
| 6329 | #define USBWakeUp_IRQn CEC_IRQn |
||
| 6330 | #define TIM9_IRQn TIM1_BRK_TIM15_IRQn |
||
| 6331 | #define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn |
||
| 6332 | #define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn |
||
| 6333 | #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn |
||
| 6334 | #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn |
||
| 6335 | #define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn |
||
| 6336 | #define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn |
||
| 6337 | #define TIM10_IRQn TIM1_UP_TIM16_IRQn |
||
| 6338 | #define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn |
||
| 6339 | #define TIM6_IRQn TIM6_DAC_IRQn |
||
| 6340 | |||
| 6341 | |||
| 6342 | /* Aliases for __IRQHandler */ |
||
| 6343 | #define ADC1_2_IRQHandler ADC1_IRQHandler |
||
| 6344 | #define OTG_FS_WKUP_IRQHandler CEC_IRQHandler |
||
| 6345 | #define USBWakeUp_IRQHandler CEC_IRQHandler |
||
| 6346 | #define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler |
||
| 6347 | #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler |
||
| 6348 | #define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler |
||
| 6349 | #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler |
||
| 6350 | #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler |
||
| 6351 | #define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler |
||
| 6352 | #define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler |
||
| 6353 | #define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler |
||
| 6354 | #define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler |
||
| 6355 | #define TIM6_IRQHandler TIM6_DAC_IRQHandler |
||
| 6356 | |||
| 6357 | |||
| 6358 | /** |
||
| 6359 | * @} |
||
| 6360 | */ |
||
| 6361 | |||
| 6362 | /** |
||
| 6363 | * @} |
||
| 6364 | */ |
||
| 6365 | |||
| 6366 | |||
| 6367 | #ifdef __cplusplus |
||
| 6368 | } |
||
| 6369 | #endif /* __cplusplus */ |
||
| 6370 | |||
| 6371 | #endif /* __STM32F100xB_H */ |
||
| 6372 | |||
| 6373 | |||
| 6374 | |||
| 6375 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |