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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f100xb.h
		4	* @author MCD Application Team
5	mjames	5	* @version V4.1.0
		6	* @date 29-April-2016
2	mjames	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		8	* This file contains all the peripheral register's definitions, bits
		9	* definitions and memory mapping for STM32F1xx devices.
		10	*
		11	* This file contains:
		12	* - Data structures and the address mapping for all peripherals
		13	* - Peripheral's registers declarations and bits definition
		14	* - Macros to access peripheral�s registers hardware
		15	*
		16	******************************************************************************
		17	* @attention
		18	*
5	mjames	19	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2	mjames	20	*
		21	* Redistribution and use in source and binary forms, with or without modification,
		22	* are permitted provided that the following conditions are met:
		23	* 1. Redistributions of source code must retain the above copyright notice,
		24	* this list of conditions and the following disclaimer.
		25	* 2. Redistributions in binary form must reproduce the above copyright notice,
		26	* this list of conditions and the following disclaimer in the documentation
		27	* and/or other materials provided with the distribution.
		28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		29	* may be used to endorse or promote products derived from this software
		30	* without specific prior written permission.
		31	*
		32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		42	*
		43	******************************************************************************
		44	*/
		45
		46
		47	/** @addtogroup CMSIS
		48	* @{
		49	*/
		50
		51	/** @addtogroup stm32f100xb
		52	* @{
		53	*/
		54
		55	#ifndef __STM32F100xB_H
		56	#define __STM32F100xB_H
		57
		58	#ifdef __cplusplus
		59	extern "C" {
		60	#endif
		61
		62	/** @addtogroup Configuration_section_for_CMSIS
		63	* @{
		64	*/
		65	/**
		66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		67	*/
		68	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
		69	#define __CM3_REV 0x0200 /!< Core Revision r2p0 /
		70	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
		71	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
		72
		73	/**
		74	* @}
		75	*/
		76
		77	/** @addtogroup Peripheral_interrupt_number_definition
		78	* @{
		79	*/
		80
		81	/**
		82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
		83	* in @ref Library_configuration_section
		84	*/
		85
		86	/!< Interrupt Number Definition /
		87	typedef enum
		88	{
		89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
		90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
5	mjames	91	HardFault_IRQn = -13, /!< 3 Cortex-M3 Hard Fault Interrupt /
2	mjames	92	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		93	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		94	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		95	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		96	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		97	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		98	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		99
		100	/**** STM32 specific Interrupt Numbers *******************************************************/
		101	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		102	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		103	TAMPER_IRQn = 2, /!< Tamper Interrupt /
		104	RTC_IRQn = 3, /!< RTC global Interrupt /
		105	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		106	RCC_IRQn = 5, /!< RCC global Interrupt /
		107	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		108	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		109	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		110	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		111	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		112	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		113	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		114	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		115	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		116	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		117	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		118	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		119	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
		120	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		121	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
		122	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
		123	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
		124	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
		125	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		126	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		127	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		128	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		129	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		130	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		131	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		132	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		133	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		134	USART1_IRQn = 37, /!< USART1 global Interrupt /
		135	USART2_IRQn = 38, /!< USART2 global Interrupt /
		136	USART3_IRQn = 39, /!< USART3 global Interrupt /
		137	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		138	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		139	CEC_IRQn = 42, /!< HDMI-CEC Interrupt /
		140	TIM6_DAC_IRQn = 54, /!< TIM6 and DAC underrun Interrupt /
		141	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
		142	} IRQn_Type;
		143
		144
		145	/**
		146	* @}
		147	*/
		148
		149	#include "core_cm3.h"
		150	#include "system_stm32f1xx.h"
		151	#include <stdint.h>
		152
		153	/** @addtogroup Peripheral_registers_structures
		154	* @{
		155	*/
		156
		157	/**
		158	* @brief Analog to Digital Converter
		159	*/
		160
		161	typedef struct
		162	{
		163	__IO uint32_t SR;
		164	__IO uint32_t CR1;
		165	__IO uint32_t CR2;
		166	__IO uint32_t SMPR1;
		167	__IO uint32_t SMPR2;
		168	__IO uint32_t JOFR1;
		169	__IO uint32_t JOFR2;
		170	__IO uint32_t JOFR3;
		171	__IO uint32_t JOFR4;
		172	__IO uint32_t HTR;
		173	__IO uint32_t LTR;
		174	__IO uint32_t SQR1;
		175	__IO uint32_t SQR2;
		176	__IO uint32_t SQR3;
		177	__IO uint32_t JSQR;
		178	__IO uint32_t JDR1;
		179	__IO uint32_t JDR2;
		180	__IO uint32_t JDR3;
		181	__IO uint32_t JDR4;
		182	__IO uint32_t DR;
		183	} ADC_TypeDef;
		184
5	mjames	185	typedef struct
		186	{
		187	__IO uint32_t SR; /!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address /
		188	__IO uint32_t CR1; /!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 /
		189	__IO uint32_t CR2; /!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 /
		190	uint32_t RESERVED[16];
		191	__IO uint32_t DR; /!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C /
		192	} ADC_Common_TypeDef;
		193
2	mjames	194	/**
		195	* @brief Backup Registers
		196	*/
		197
		198	typedef struct
		199	{
		200	uint32_t RESERVED0;
		201	__IO uint32_t DR1;
		202	__IO uint32_t DR2;
		203	__IO uint32_t DR3;
		204	__IO uint32_t DR4;
		205	__IO uint32_t DR5;
		206	__IO uint32_t DR6;
		207	__IO uint32_t DR7;
		208	__IO uint32_t DR8;
		209	__IO uint32_t DR9;
		210	__IO uint32_t DR10;
		211	__IO uint32_t RTCCR;
		212	__IO uint32_t CR;
		213	__IO uint32_t CSR;
		214	} BKP_TypeDef;
		215
		216
		217	/**
		218	* @brief Consumer Electronics Control (CEC)
		219	*/
		220	typedef struct
		221	{
		222	__IO uint32_t CFGR;
		223	__IO uint32_t OAR;
		224	__IO uint32_t PRES;
		225	__IO uint32_t ESR;
		226	__IO uint32_t CSR;
		227	__IO uint32_t TXD;
		228	__IO uint32_t RXD;
		229	} CEC_TypeDef;
		230
		231	/**
		232	* @brief CRC calculation unit
		233	*/
		234
		235	typedef struct
		236	{
		237	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		238	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		239	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		240	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		241	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		242	} CRC_TypeDef;
		243
		244	/**
		245	* @brief Digital to Analog Converter
		246	*/
		247
		248	typedef struct
		249	{
		250	__IO uint32_t CR;
		251	__IO uint32_t SWTRIGR;
		252	__IO uint32_t DHR12R1;
		253	__IO uint32_t DHR12L1;
		254	__IO uint32_t DHR8R1;
		255	__IO uint32_t DHR12R2;
		256	__IO uint32_t DHR12L2;
		257	__IO uint32_t DHR8R2;
		258	__IO uint32_t DHR12RD;
		259	__IO uint32_t DHR12LD;
		260	__IO uint32_t DHR8RD;
		261	__IO uint32_t DOR1;
		262	__IO uint32_t DOR2;
		263	__IO uint32_t SR;
		264	} DAC_TypeDef;
		265
		266	/**
		267	* @brief Debug MCU
		268	*/
		269
		270	typedef struct
		271	{
		272	__IO uint32_t IDCODE;
		273	__IO uint32_t CR;
		274	}DBGMCU_TypeDef;
		275
		276	/**
		277	* @brief DMA Controller
		278	*/
		279
		280	typedef struct
		281	{
		282	__IO uint32_t CCR;
		283	__IO uint32_t CNDTR;
		284	__IO uint32_t CPAR;
		285	__IO uint32_t CMAR;
		286	} DMA_Channel_TypeDef;
		287
		288	typedef struct
		289	{
		290	__IO uint32_t ISR;
		291	__IO uint32_t IFCR;
		292	} DMA_TypeDef;
		293
		294
		295
		296	/**
		297	* @brief External Interrupt/Event Controller
		298	*/
		299
		300	typedef struct
		301	{
		302	__IO uint32_t IMR;
		303	__IO uint32_t EMR;
		304	__IO uint32_t RTSR;
		305	__IO uint32_t FTSR;
		306	__IO uint32_t SWIER;
		307	__IO uint32_t PR;
		308	} EXTI_TypeDef;
		309
		310	/**
		311	* @brief FLASH Registers
		312	*/
		313
		314	typedef struct
		315	{
		316	__IO uint32_t ACR;
		317	__IO uint32_t KEYR;
		318	__IO uint32_t OPTKEYR;
		319	__IO uint32_t SR;
		320	__IO uint32_t CR;
		321	__IO uint32_t AR;
		322	__IO uint32_t RESERVED;
		323	__IO uint32_t OBR;
		324	__IO uint32_t WRPR;
		325	} FLASH_TypeDef;
		326
		327	/**
		328	* @brief Option Bytes Registers
		329	*/
		330
		331	typedef struct
		332	{
		333	__IO uint16_t RDP;
		334	__IO uint16_t USER;
		335	__IO uint16_t Data0;
		336	__IO uint16_t Data1;
		337	__IO uint16_t WRP0;
		338	__IO uint16_t WRP1;
		339	__IO uint16_t WRP2;
		340	__IO uint16_t WRP3;
		341	} OB_TypeDef;
		342
		343	/**
		344	* @brief General Purpose I/O
		345	*/
		346
		347	typedef struct
		348	{
		349	__IO uint32_t CRL;
		350	__IO uint32_t CRH;
		351	__IO uint32_t IDR;
		352	__IO uint32_t ODR;
		353	__IO uint32_t BSRR;
		354	__IO uint32_t BRR;
		355	__IO uint32_t LCKR;
		356	} GPIO_TypeDef;
		357
		358	/**
		359	* @brief Alternate Function I/O
		360	*/
		361
		362	typedef struct
		363	{
		364	__IO uint32_t EVCR;
		365	__IO uint32_t MAPR;
		366	__IO uint32_t EXTICR[4];
		367	uint32_t RESERVED0;
		368	__IO uint32_t MAPR2;
		369	} AFIO_TypeDef;
		370	/**
		371	* @brief Inter Integrated Circuit Interface
		372	*/
		373
		374	typedef struct
		375	{
		376	__IO uint32_t CR1;
		377	__IO uint32_t CR2;
		378	__IO uint32_t OAR1;
		379	__IO uint32_t OAR2;
		380	__IO uint32_t DR;
		381	__IO uint32_t SR1;
		382	__IO uint32_t SR2;
		383	__IO uint32_t CCR;
		384	__IO uint32_t TRISE;
		385	} I2C_TypeDef;
		386
		387	/**
		388	* @brief Independent WATCHDOG
		389	*/
		390
		391	typedef struct
		392	{
		393	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		394	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		395	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		396	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		397	} IWDG_TypeDef;
		398
		399	/**
		400	* @brief Power Control
		401	*/
		402
		403	typedef struct
		404	{
		405	__IO uint32_t CR;
		406	__IO uint32_t CSR;
		407	} PWR_TypeDef;
		408
		409	/**
		410	* @brief Reset and Clock Control
		411	*/
		412
		413	typedef struct
		414	{
		415	__IO uint32_t CR;
		416	__IO uint32_t CFGR;
		417	__IO uint32_t CIR;
		418	__IO uint32_t APB2RSTR;
		419	__IO uint32_t APB1RSTR;
		420	__IO uint32_t AHBENR;
		421	__IO uint32_t APB2ENR;
		422	__IO uint32_t APB1ENR;
		423	__IO uint32_t BDCR;
		424	__IO uint32_t CSR;
		425
		426
		427	uint32_t RESERVED0;
		428	__IO uint32_t CFGR2;
		429	} RCC_TypeDef;
		430
		431	/**
		432	* @brief Real-Time Clock
		433	*/
		434
		435	typedef struct
		436	{
		437	__IO uint32_t CRH;
		438	__IO uint32_t CRL;
		439	__IO uint32_t PRLH;
		440	__IO uint32_t PRLL;
		441	__IO uint32_t DIVH;
		442	__IO uint32_t DIVL;
		443	__IO uint32_t CNTH;
		444	__IO uint32_t CNTL;
		445	__IO uint32_t ALRH;
		446	__IO uint32_t ALRL;
		447	} RTC_TypeDef;
		448
		449	/**
		450	* @brief SD host Interface
		451	*/
		452
		453	typedef struct
		454	{
		455	__IO uint32_t POWER;
		456	__IO uint32_t CLKCR;
		457	__IO uint32_t ARG;
		458	__IO uint32_t CMD;
		459	__I uint32_t RESPCMD;
		460	__I uint32_t RESP1;
		461	__I uint32_t RESP2;
		462	__I uint32_t RESP3;
		463	__I uint32_t RESP4;
		464	__IO uint32_t DTIMER;
		465	__IO uint32_t DLEN;
		466	__IO uint32_t DCTRL;
		467	__I uint32_t DCOUNT;
		468	__I uint32_t STA;
		469	__IO uint32_t ICR;
		470	__IO uint32_t MASK;
		471	uint32_t RESERVED0[2];
		472	__I uint32_t FIFOCNT;
		473	uint32_t RESERVED1[13];
		474	__IO uint32_t FIFO;
		475	} SDIO_TypeDef;
		476
		477	/**
		478	* @brief Serial Peripheral Interface
		479	*/
		480
		481	typedef struct
		482	{
		483	__IO uint32_t CR1;
		484	__IO uint32_t CR2;
		485	__IO uint32_t SR;
		486	__IO uint32_t DR;
		487	__IO uint32_t CRCPR;
		488	__IO uint32_t RXCRCR;
		489	__IO uint32_t TXCRCR;
		490	} SPI_TypeDef;
		491
		492	/**
		493	* @brief TIM Timers
		494	*/
		495	typedef struct
		496	{
		497	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		498	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		499	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		500	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		501	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		502	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		503	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		504	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		505	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		506	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		507	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		508	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		509	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
		510	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		511	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		512	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		513	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		514	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
		515	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		516	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
		517	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		518	}TIM_TypeDef;
		519
		520
		521	/**
		522	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		523	*/
		524
		525	typedef struct
		526	{
		527	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		528	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		529	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		530	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		531	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		532	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		533	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		534	} USART_TypeDef;
		535
		536
		537
		538	/**
		539	* @brief Window WATCHDOG
		540	*/
		541
		542	typedef struct
		543	{
		544	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		545	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		546	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		547	} WWDG_TypeDef;
		548
		549	/**
		550	* @}
		551	*/
		552
		553	/** @addtogroup Peripheral_memory_map
		554	* @{
		555	*/
		556
		557
		558	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
		559	#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /!< FLASH END address of bank1 /
		560	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
		561	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
		562
		563	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
		564	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
		565
		566
		567	/!< Peripheral memory map /
		568	#define APB1PERIPH_BASE PERIPH_BASE
		569	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
		570	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
		571
		572	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
		573	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
		574	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
		575	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
		576	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
		577	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
		578	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
		579	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
		580	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
		581	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
		582	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
		583	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
		584	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
		585	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
		586	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
		587	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
		588	#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
		589	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
		590	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
		591	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
		592	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
		593	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
		594	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
		595	#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
		596	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
		597	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
		598	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
		599	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
		600	#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
		601	#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
		602	#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
		603
		604	#define SDIO_BASE (PERIPH_BASE + 0x18000)
		605
		606	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
		607	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
		608	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
		609	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
		610	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
		611	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
		612	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
		613	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
		614	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
		615	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
		616
		617	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
5	mjames	618	#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /!< FLASH Size register base address /
		619	#define UID_BASE ((uint32_t)0x1FFFF7E8) /!< Unique device ID register base address /
2	mjames	620	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
		621
		622
		623
		624	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
		625
		626
		627
		628	/**
		629	* @}
		630	*/
		631
		632	/** @addtogroup Peripheral_declaration
		633	* @{
		634	*/
		635
		636	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
		637	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
		638	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
		639	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
		640	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
		641	#define RTC ((RTC_TypeDef *) RTC_BASE)
		642	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
		643	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
		644	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
		645	#define USART2 ((USART_TypeDef *) USART2_BASE)
		646	#define USART3 ((USART_TypeDef *) USART3_BASE)
		647	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
		648	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
		649	#define BKP ((BKP_TypeDef *) BKP_BASE)
		650	#define PWR ((PWR_TypeDef *) PWR_BASE)
		651	#define DAC ((DAC_TypeDef *) DAC_BASE)
		652	#define CEC ((CEC_TypeDef *) CEC_BASE)
		653	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
		654	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
		655	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
		656	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
		657	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
		658	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
		659	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
		660	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
5	mjames	661	#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
2	mjames	662	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
		663	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
		664	#define USART1 ((USART_TypeDef *) USART1_BASE)
		665	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
		666	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
		667	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
		668	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
		669	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
		670	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
		671	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
		672	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
		673	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
		674	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
		675	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
		676	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
		677	#define RCC ((RCC_TypeDef *) RCC_BASE)
		678	#define CRC ((CRC_TypeDef *) CRC_BASE)
		679	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
		680	#define OB ((OB_TypeDef *) OB_BASE)
		681	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
		682
		683
		684	/**
		685	* @}
		686	*/
		687
		688	/** @addtogroup Exported_constants
		689	* @{
		690	*/
		691
		692	/** @addtogroup Peripheral_Registers_Bits_Definition
		693	* @{
		694	*/
		695
		696	/******************************************************************************/
		697	/* Peripheral Registers_Bits_Definition */
		698	/******************************************************************************/
		699
		700	/******************************************************************************/
		701	/* */
		702	/* CRC calculation unit (CRC) */
		703	/* */
		704	/******************************************************************************/
		705
		706	/***************** Bit definition for CRC_DR register *******************/
5	mjames	707	#define CRC_DR_DR_Pos (0U)
		708	#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /!< 0xFFFFFFFF /
		709	#define CRC_DR_DR CRC_DR_DR_Msk /!< Data register bits /
2	mjames	710
		711	/***************** Bit definition for CRC_IDR register ******************/
5	mjames	712	#define CRC_IDR_IDR_Pos (0U)
		713	#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /!< 0x000000FF /
		714	#define CRC_IDR_IDR CRC_IDR_IDR_Msk /!< General-purpose 8-bit data register bits /
2	mjames	715
		716	/****************** Bit definition for CRC_CR register ******************/
5	mjames	717	#define CRC_CR_RESET_Pos (0U)
		718	#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /!< 0x00000001 /
		719	#define CRC_CR_RESET CRC_CR_RESET_Msk /!< RESET bit /
2	mjames	720
		721	/******************************************************************************/
		722	/* */
		723	/* Power Control */
		724	/* */
		725	/******************************************************************************/
		726
		727	/****************** Bit definition for PWR_CR register ******************/
5	mjames	728	#define PWR_CR_LPDS_Pos (0U)
		729	#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /!< 0x00000001 /
		730	#define PWR_CR_LPDS PWR_CR_LPDS_Msk /!< Low-Power Deepsleep /
		731	#define PWR_CR_PDDS_Pos (1U)
		732	#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /!< 0x00000002 /
		733	#define PWR_CR_PDDS PWR_CR_PDDS_Msk /!< Power Down Deepsleep /
		734	#define PWR_CR_CWUF_Pos (2U)
		735	#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /!< 0x00000004 /
		736	#define PWR_CR_CWUF PWR_CR_CWUF_Msk /!< Clear Wakeup Flag /
		737	#define PWR_CR_CSBF_Pos (3U)
		738	#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /!< 0x00000008 /
		739	#define PWR_CR_CSBF PWR_CR_CSBF_Msk /!< Clear Standby Flag /
		740	#define PWR_CR_PVDE_Pos (4U)
		741	#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /!< 0x00000010 /
		742	#define PWR_CR_PVDE PWR_CR_PVDE_Msk /!< Power Voltage Detector Enable /
2	mjames	743
5	mjames	744	#define PWR_CR_PLS_Pos (5U)
		745	#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /!< 0x000000E0 /
		746	#define PWR_CR_PLS PWR_CR_PLS_Msk /!< PLS[2:0] bits (PVD Level Selection) /
		747	#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /!< 0x00000020 /
		748	#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /!< 0x00000040 /
		749	#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /!< 0x00000080 /
2	mjames	750
		751	/!< PVD level configuration /
5	mjames	752	#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /!< PVD level 2.2V /
		753	#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /!< PVD level 2.3V /
		754	#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /!< PVD level 2.4V /
		755	#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /!< PVD level 2.5V /
		756	#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /!< PVD level 2.6V /
		757	#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /!< PVD level 2.7V /
		758	#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /!< PVD level 2.8V /
		759	#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /!< PVD level 2.9V /
2	mjames	760
5	mjames	761	#define PWR_CR_DBP_Pos (8U)
		762	#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /!< 0x00000100 /
		763	#define PWR_CR_DBP PWR_CR_DBP_Msk /!< Disable Backup Domain write protection /
2	mjames	764
		765
		766	/***************** Bit definition for PWR_CSR register ******************/
5	mjames	767	#define PWR_CSR_WUF_Pos (0U)
		768	#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /!< 0x00000001 /
		769	#define PWR_CSR_WUF PWR_CSR_WUF_Msk /!< Wakeup Flag /
		770	#define PWR_CSR_SBF_Pos (1U)
		771	#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /!< 0x00000002 /
		772	#define PWR_CSR_SBF PWR_CSR_SBF_Msk /!< Standby Flag /
		773	#define PWR_CSR_PVDO_Pos (2U)
		774	#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /!< 0x00000004 /
		775	#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /!< PVD Output /
		776	#define PWR_CSR_EWUP_Pos (8U)
		777	#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /!< 0x00000100 /
		778	#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /!< Enable WKUP pin /
2	mjames	779
		780	/******************************************************************************/
		781	/* */
		782	/* Backup registers */
		783	/* */
		784	/******************************************************************************/
		785
		786	/***************** Bit definition for BKP_DR1 register ******************/
5	mjames	787	#define BKP_DR1_D_Pos (0U)
		788	#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /!< 0x0000FFFF /
		789	#define BKP_DR1_D BKP_DR1_D_Msk /!< Backup data /
2	mjames	790
		791	/***************** Bit definition for BKP_DR2 register ******************/
5	mjames	792	#define BKP_DR2_D_Pos (0U)
		793	#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /!< 0x0000FFFF /
		794	#define BKP_DR2_D BKP_DR2_D_Msk /!< Backup data /
2	mjames	795
		796	/***************** Bit definition for BKP_DR3 register ******************/
5	mjames	797	#define BKP_DR3_D_Pos (0U)
		798	#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /!< 0x0000FFFF /
		799	#define BKP_DR3_D BKP_DR3_D_Msk /!< Backup data /
2	mjames	800
		801	/***************** Bit definition for BKP_DR4 register ******************/
5	mjames	802	#define BKP_DR4_D_Pos (0U)
		803	#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /!< 0x0000FFFF /
		804	#define BKP_DR4_D BKP_DR4_D_Msk /!< Backup data /
2	mjames	805
		806	/***************** Bit definition for BKP_DR5 register ******************/
5	mjames	807	#define BKP_DR5_D_Pos (0U)
		808	#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /!< 0x0000FFFF /
		809	#define BKP_DR5_D BKP_DR5_D_Msk /!< Backup data /
2	mjames	810
		811	/***************** Bit definition for BKP_DR6 register ******************/
5	mjames	812	#define BKP_DR6_D_Pos (0U)
		813	#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /!< 0x0000FFFF /
		814	#define BKP_DR6_D BKP_DR6_D_Msk /!< Backup data /
2	mjames	815
		816	/***************** Bit definition for BKP_DR7 register ******************/
5	mjames	817	#define BKP_DR7_D_Pos (0U)
		818	#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /!< 0x0000FFFF /
		819	#define BKP_DR7_D BKP_DR7_D_Msk /!< Backup data /
2	mjames	820
		821	/***************** Bit definition for BKP_DR8 register ******************/
5	mjames	822	#define BKP_DR8_D_Pos (0U)
		823	#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /!< 0x0000FFFF /
		824	#define BKP_DR8_D BKP_DR8_D_Msk /!< Backup data /
2	mjames	825
		826	/***************** Bit definition for BKP_DR9 register ******************/
5	mjames	827	#define BKP_DR9_D_Pos (0U)
		828	#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /!< 0x0000FFFF /
		829	#define BKP_DR9_D BKP_DR9_D_Msk /!< Backup data /
2	mjames	830
		831	/***************** Bit definition for BKP_DR10 register *****************/
5	mjames	832	#define BKP_DR10_D_Pos (0U)
		833	#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /!< 0x0000FFFF /
		834	#define BKP_DR10_D BKP_DR10_D_Msk /!< Backup data /
2	mjames	835
		836	#define RTC_BKP_NUMBER 10
		837
		838	/**************** Bit definition for BKP_RTCCR register *****************/
5	mjames	839	#define BKP_RTCCR_CAL_Pos (0U)
		840	#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /!< 0x0000007F /
		841	#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /!< Calibration value /
		842	#define BKP_RTCCR_CCO_Pos (7U)
		843	#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /!< 0x00000080 /
		844	#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /!< Calibration Clock Output /
		845	#define BKP_RTCCR_ASOE_Pos (8U)
		846	#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /!< 0x00000100 /
		847	#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /!< Alarm or Second Output Enable /
		848	#define BKP_RTCCR_ASOS_Pos (9U)
		849	#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /!< 0x00000200 /
		850	#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /!< Alarm or Second Output Selection /
2	mjames	851
		852	/****************** Bit definition for BKP_CR register ******************/
5	mjames	853	#define BKP_CR_TPE_Pos (0U)
		854	#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /!< 0x00000001 /
		855	#define BKP_CR_TPE BKP_CR_TPE_Msk /!< TAMPER pin enable /
		856	#define BKP_CR_TPAL_Pos (1U)
		857	#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /!< 0x00000002 /
		858	#define BKP_CR_TPAL BKP_CR_TPAL_Msk /!< TAMPER pin active level /
2	mjames	859
		860	/***************** Bit definition for BKP_CSR register ******************/
5	mjames	861	#define BKP_CSR_CTE_Pos (0U)
		862	#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /!< 0x00000001 /
		863	#define BKP_CSR_CTE BKP_CSR_CTE_Msk /!< Clear Tamper event /
		864	#define BKP_CSR_CTI_Pos (1U)
		865	#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /!< 0x00000002 /
		866	#define BKP_CSR_CTI BKP_CSR_CTI_Msk /!< Clear Tamper Interrupt /
		867	#define BKP_CSR_TPIE_Pos (2U)
		868	#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /!< 0x00000004 /
		869	#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /!< TAMPER Pin interrupt enable /
		870	#define BKP_CSR_TEF_Pos (8U)
		871	#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /!< 0x00000100 /
		872	#define BKP_CSR_TEF BKP_CSR_TEF_Msk /!< Tamper Event Flag /
		873	#define BKP_CSR_TIF_Pos (9U)
		874	#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /!< 0x00000200 /
		875	#define BKP_CSR_TIF BKP_CSR_TIF_Msk /!< Tamper Interrupt Flag /
2	mjames	876
		877	/******************************************************************************/
		878	/* */
		879	/* Reset and Clock Control */
		880	/* */
		881	/******************************************************************************/
		882
		883	/****************** Bit definition for RCC_CR register ******************/
5	mjames	884	#define RCC_CR_HSION_Pos (0U)
		885	#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /!< 0x00000001 /
		886	#define RCC_CR_HSION RCC_CR_HSION_Msk /!< Internal High Speed clock enable /
		887	#define RCC_CR_HSIRDY_Pos (1U)
		888	#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /!< 0x00000002 /
		889	#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /!< Internal High Speed clock ready flag /
		890	#define RCC_CR_HSITRIM_Pos (3U)
		891	#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /!< 0x000000F8 /
		892	#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /!< Internal High Speed clock trimming /
		893	#define RCC_CR_HSICAL_Pos (8U)
		894	#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /!< 0x0000FF00 /
		895	#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /!< Internal High Speed clock Calibration /
		896	#define RCC_CR_HSEON_Pos (16U)
		897	#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /!< 0x00010000 /
		898	#define RCC_CR_HSEON RCC_CR_HSEON_Msk /!< External High Speed clock enable /
		899	#define RCC_CR_HSERDY_Pos (17U)
		900	#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /!< 0x00020000 /
		901	#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /!< External High Speed clock ready flag /
		902	#define RCC_CR_HSEBYP_Pos (18U)
		903	#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /!< 0x00040000 /
		904	#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /!< External High Speed clock Bypass /
		905	#define RCC_CR_CSSON_Pos (19U)
		906	#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /!< 0x00080000 /
		907	#define RCC_CR_CSSON RCC_CR_CSSON_Msk /!< Clock Security System enable /
		908	#define RCC_CR_PLLON_Pos (24U)
		909	#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /!< 0x01000000 /
		910	#define RCC_CR_PLLON RCC_CR_PLLON_Msk /!< PLL enable /
		911	#define RCC_CR_PLLRDY_Pos (25U)
		912	#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /!< 0x02000000 /
		913	#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /!< PLL clock ready flag /
2	mjames	914
		915
		916	/***************** Bit definition for RCC_CFGR register *****************/
		917	/!< SW configuration /
5	mjames	918	#define RCC_CFGR_SW_Pos (0U)
		919	#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /!< 0x00000003 /
		920	#define RCC_CFGR_SW RCC_CFGR_SW_Msk /!< SW[1:0] bits (System clock Switch) /
		921	#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /!< 0x00000001 /
		922	#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /!< 0x00000002 /
2	mjames	923
5	mjames	924	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
		925	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
		926	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
2	mjames	927
		928	/!< SWS configuration /
5	mjames	929	#define RCC_CFGR_SWS_Pos (2U)
		930	#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /!< 0x0000000C /
		931	#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /!< SWS[1:0] bits (System Clock Switch Status) /
		932	#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /!< 0x00000004 /
		933	#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /!< 0x00000008 /
2	mjames	934
5	mjames	935	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
		936	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
		937	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
2	mjames	938
		939	/!< HPRE configuration /
5	mjames	940	#define RCC_CFGR_HPRE_Pos (4U)
		941	#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /!< 0x000000F0 /
		942	#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /!< HPRE[3:0] bits (AHB prescaler) /
		943	#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /!< 0x00000010 /
		944	#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /!< 0x00000020 /
		945	#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /!< 0x00000040 /
		946	#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /!< 0x00000080 /
2	mjames	947
5	mjames	948	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
		949	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
		950	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
		951	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
		952	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
		953	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
		954	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
		955	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
		956	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
2	mjames	957
		958	/!< PPRE1 configuration /
5	mjames	959	#define RCC_CFGR_PPRE1_Pos (8U)
		960	#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /!< 0x00000700 /
		961	#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /!< PRE1[2:0] bits (APB1 prescaler) /
		962	#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /!< 0x00000100 /
		963	#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /!< 0x00000200 /
		964	#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /!< 0x00000400 /
2	mjames	965
5	mjames	966	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		967	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
		968	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
		969	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
		970	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
2	mjames	971
		972	/!< PPRE2 configuration /
5	mjames	973	#define RCC_CFGR_PPRE2_Pos (11U)
		974	#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /!< 0x00003800 /
		975	#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /!< PRE2[2:0] bits (APB2 prescaler) /
		976	#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /!< 0x00000800 /
		977	#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /!< 0x00001000 /
		978	#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /!< 0x00002000 /
2	mjames	979
5	mjames	980	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
		981	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
		982	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
		983	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
		984	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
2	mjames	985
		986	/!< ADCPPRE configuration /
5	mjames	987	#define RCC_CFGR_ADCPRE_Pos (14U)
		988	#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /!< 0x0000C000 /
		989	#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /!< ADCPRE[1:0] bits (ADC prescaler) /
		990	#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /!< 0x00004000 /
		991	#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /!< 0x00008000 /
2	mjames	992
5	mjames	993	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
		994	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
		995	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
		996	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
2	mjames	997
5	mjames	998	#define RCC_CFGR_PLLSRC_Pos (16U)
		999	#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /!< 0x00010000 /
		1000	#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /!< PLL entry clock source /
2	mjames	1001
5	mjames	1002	#define RCC_CFGR_PLLXTPRE_Pos (17U)
		1003	#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /!< 0x00020000 /
		1004	#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /!< HSE divider for PLL entry /
2	mjames	1005
		1006	/!< PLLMUL configuration /
5	mjames	1007	#define RCC_CFGR_PLLMULL_Pos (18U)
		1008	#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /!< 0x003C0000 /
		1009	#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /!< PLLMUL[3:0] bits (PLL multiplication factor) /
		1010	#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /!< 0x00040000 /
		1011	#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /!< 0x00080000 /
		1012	#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /!< 0x00100000 /
		1013	#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /!< 0x00200000 /
2	mjames	1014
5	mjames	1015	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
		1016	#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
2	mjames	1017
5	mjames	1018	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
		1019	#define RCC_CFGR_PLLMULL3_Pos (18U)
		1020	#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /!< 0x00040000 /
		1021	#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /!< PLL input clock3 */
		1022	#define RCC_CFGR_PLLMULL4_Pos (19U)
		1023	#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /!< 0x00080000 /
		1024	#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /!< PLL input clock4 */
		1025	#define RCC_CFGR_PLLMULL5_Pos (18U)
		1026	#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /!< 0x000C0000 /
		1027	#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /!< PLL input clock5 */
		1028	#define RCC_CFGR_PLLMULL6_Pos (20U)
		1029	#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /!< 0x00100000 /
		1030	#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /!< PLL input clock6 */
		1031	#define RCC_CFGR_PLLMULL7_Pos (18U)
		1032	#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /!< 0x00140000 /
		1033	#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /!< PLL input clock7 */
		1034	#define RCC_CFGR_PLLMULL8_Pos (19U)
		1035	#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /!< 0x00180000 /
		1036	#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /!< PLL input clock8 */
		1037	#define RCC_CFGR_PLLMULL9_Pos (18U)
		1038	#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /!< 0x001C0000 /
		1039	#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /!< PLL input clock9 */
		1040	#define RCC_CFGR_PLLMULL10_Pos (21U)
		1041	#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /!< 0x00200000 /
		1042	#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /!< PLL input clock10 /
		1043	#define RCC_CFGR_PLLMULL11_Pos (18U)
		1044	#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /!< 0x00240000 /
		1045	#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /!< PLL input clock11 */
		1046	#define RCC_CFGR_PLLMULL12_Pos (19U)
		1047	#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /!< 0x00280000 /
		1048	#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /!< PLL input clock12 */
		1049	#define RCC_CFGR_PLLMULL13_Pos (18U)
		1050	#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /!< 0x002C0000 /
		1051	#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /!< PLL input clock13 */
		1052	#define RCC_CFGR_PLLMULL14_Pos (20U)
		1053	#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /!< 0x00300000 /
		1054	#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /!< PLL input clock14 */
		1055	#define RCC_CFGR_PLLMULL15_Pos (18U)
		1056	#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /!< 0x00340000 /
		1057	#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /!< PLL input clock15 */
		1058	#define RCC_CFGR_PLLMULL16_Pos (19U)
		1059	#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /!< 0x00380000 /
		1060	#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /!< PLL input clock16 */
2	mjames	1061
		1062	/!< MCO configuration /
5	mjames	1063	#define RCC_CFGR_MCO_Pos (24U)
		1064	#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /!< 0x07000000 /
		1065	#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /!< MCO[2:0] bits (Microcontroller Clock Output) /
		1066	#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /!< 0x01000000 /
		1067	#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /!< 0x02000000 /
		1068	#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /!< 0x04000000 /
2	mjames	1069
5	mjames	1070	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1071	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
		1072	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
		1073	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
		1074	#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
2	mjames	1075
5	mjames	1076	/* Reference defines */
		1077	#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
		1078	#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
		1079	#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
		1080	#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
		1081	#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
		1082	#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
		1083	#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
		1084	#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
		1085	#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
		1086
2	mjames	1087	/!<*************** Bit definition for RCC_CIR register ******************/
5	mjames	1088	#define RCC_CIR_LSIRDYF_Pos (0U)
		1089	#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /!< 0x00000001 /
		1090	#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /!< LSI Ready Interrupt flag /
		1091	#define RCC_CIR_LSERDYF_Pos (1U)
		1092	#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /!< 0x00000002 /
		1093	#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /!< LSE Ready Interrupt flag /
		1094	#define RCC_CIR_HSIRDYF_Pos (2U)
		1095	#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /!< 0x00000004 /
		1096	#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /!< HSI Ready Interrupt flag /
		1097	#define RCC_CIR_HSERDYF_Pos (3U)
		1098	#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /!< 0x00000008 /
		1099	#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /!< HSE Ready Interrupt flag /
		1100	#define RCC_CIR_PLLRDYF_Pos (4U)
		1101	#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /!< 0x00000010 /
		1102	#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /!< PLL Ready Interrupt flag /
		1103	#define RCC_CIR_CSSF_Pos (7U)
		1104	#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /!< 0x00000080 /
		1105	#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /!< Clock Security System Interrupt flag /
		1106	#define RCC_CIR_LSIRDYIE_Pos (8U)
		1107	#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /!< 0x00000100 /
		1108	#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /!< LSI Ready Interrupt Enable /
		1109	#define RCC_CIR_LSERDYIE_Pos (9U)
		1110	#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /!< 0x00000200 /
		1111	#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /!< LSE Ready Interrupt Enable /
		1112	#define RCC_CIR_HSIRDYIE_Pos (10U)
		1113	#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /!< 0x00000400 /
		1114	#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /!< HSI Ready Interrupt Enable /
		1115	#define RCC_CIR_HSERDYIE_Pos (11U)
		1116	#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /!< 0x00000800 /
		1117	#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /!< HSE Ready Interrupt Enable /
		1118	#define RCC_CIR_PLLRDYIE_Pos (12U)
		1119	#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /!< 0x00001000 /
		1120	#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /!< PLL Ready Interrupt Enable /
		1121	#define RCC_CIR_LSIRDYC_Pos (16U)
		1122	#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /!< 0x00010000 /
		1123	#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /!< LSI Ready Interrupt Clear /
		1124	#define RCC_CIR_LSERDYC_Pos (17U)
		1125	#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /!< 0x00020000 /
		1126	#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /!< LSE Ready Interrupt Clear /
		1127	#define RCC_CIR_HSIRDYC_Pos (18U)
		1128	#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /!< 0x00040000 /
		1129	#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /!< HSI Ready Interrupt Clear /
		1130	#define RCC_CIR_HSERDYC_Pos (19U)
		1131	#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /!< 0x00080000 /
		1132	#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /!< HSE Ready Interrupt Clear /
		1133	#define RCC_CIR_PLLRDYC_Pos (20U)
		1134	#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /!< 0x00100000 /
		1135	#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /!< PLL Ready Interrupt Clear /
		1136	#define RCC_CIR_CSSC_Pos (23U)
		1137	#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /!< 0x00800000 /
		1138	#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /!< Clock Security System Interrupt Clear /
2	mjames	1139
		1140
		1141	/*************** Bit definition for RCC_APB2RSTR register ***************/
5	mjames	1142	#define RCC_APB2RSTR_AFIORST_Pos (0U)
		1143	#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /!< 0x00000001 /
		1144	#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /!< Alternate Function I/O reset /
		1145	#define RCC_APB2RSTR_IOPARST_Pos (2U)
		1146	#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /!< 0x00000004 /
		1147	#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /!< I/O port A reset /
		1148	#define RCC_APB2RSTR_IOPBRST_Pos (3U)
		1149	#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /!< 0x00000008 /
		1150	#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /!< I/O port B reset /
		1151	#define RCC_APB2RSTR_IOPCRST_Pos (4U)
		1152	#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /!< 0x00000010 /
		1153	#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /!< I/O port C reset /
		1154	#define RCC_APB2RSTR_IOPDRST_Pos (5U)
		1155	#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /!< 0x00000020 /
		1156	#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /!< I/O port D reset /
		1157	#define RCC_APB2RSTR_ADC1RST_Pos (9U)
		1158	#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /!< 0x00000200 /
		1159	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /!< ADC 1 interface reset /
2	mjames	1160
		1161
5	mjames	1162	#define RCC_APB2RSTR_TIM1RST_Pos (11U)
		1163	#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /!< 0x00000800 /
		1164	#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /!< TIM1 Timer reset /
		1165	#define RCC_APB2RSTR_SPI1RST_Pos (12U)
		1166	#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /!< 0x00001000 /
		1167	#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /!< SPI 1 reset /
		1168	#define RCC_APB2RSTR_USART1RST_Pos (14U)
		1169	#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /!< 0x00004000 /
		1170	#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /!< USART1 reset /
2	mjames	1171
5	mjames	1172	#define RCC_APB2RSTR_TIM15RST_Pos (16U)
		1173	#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /!< 0x00010000 /
		1174	#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /!< TIM15 Timer reset /
		1175	#define RCC_APB2RSTR_TIM16RST_Pos (17U)
		1176	#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /!< 0x00020000 /
		1177	#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /!< TIM16 Timer reset /
		1178	#define RCC_APB2RSTR_TIM17RST_Pos (18U)
		1179	#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /!< 0x00040000 /
		1180	#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /!< TIM17 Timer reset /
2	mjames	1181
5	mjames	1182	#define RCC_APB2RSTR_IOPERST_Pos (6U)
		1183	#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /!< 0x00000040 /
		1184	#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /!< I/O port E reset /
2	mjames	1185
		1186
		1187
		1188
		1189	/*************** Bit definition for RCC_APB1RSTR register ***************/
5	mjames	1190	#define RCC_APB1RSTR_TIM2RST_Pos (0U)
		1191	#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /!< 0x00000001 /
		1192	#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /!< Timer 2 reset /
		1193	#define RCC_APB1RSTR_TIM3RST_Pos (1U)
		1194	#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /!< 0x00000002 /
		1195	#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /!< Timer 3 reset /
		1196	#define RCC_APB1RSTR_WWDGRST_Pos (11U)
		1197	#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /!< 0x00000800 /
		1198	#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /!< Window Watchdog reset /
		1199	#define RCC_APB1RSTR_USART2RST_Pos (17U)
		1200	#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /!< 0x00020000 /
		1201	#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /!< USART 2 reset /
		1202	#define RCC_APB1RSTR_I2C1RST_Pos (21U)
		1203	#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /!< 0x00200000 /
		1204	#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /!< I2C 1 reset /
2	mjames	1205
		1206
5	mjames	1207	#define RCC_APB1RSTR_BKPRST_Pos (27U)
		1208	#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /!< 0x08000000 /
		1209	#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /!< Backup interface reset /
		1210	#define RCC_APB1RSTR_PWRRST_Pos (28U)
		1211	#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /!< 0x10000000 /
		1212	#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /!< Power interface reset /
2	mjames	1213
5	mjames	1214	#define RCC_APB1RSTR_TIM4RST_Pos (2U)
		1215	#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /!< 0x00000004 /
		1216	#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /!< Timer 4 reset /
		1217	#define RCC_APB1RSTR_SPI2RST_Pos (14U)
		1218	#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /!< 0x00004000 /
		1219	#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /!< SPI 2 reset /
		1220	#define RCC_APB1RSTR_USART3RST_Pos (18U)
		1221	#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /!< 0x00040000 /
		1222	#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /!< USART 3 reset /
		1223	#define RCC_APB1RSTR_I2C2RST_Pos (22U)
		1224	#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /!< 0x00400000 /
		1225	#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /!< I2C 2 reset /
2	mjames	1226
		1227
		1228
5	mjames	1229	#define RCC_APB1RSTR_TIM6RST_Pos (4U)
		1230	#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /!< 0x00000010 /
		1231	#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /!< Timer 6 reset /
		1232	#define RCC_APB1RSTR_TIM7RST_Pos (5U)
		1233	#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /!< 0x00000020 /
		1234	#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /!< Timer 7 reset /
		1235	#define RCC_APB1RSTR_CECRST_Pos (30U)
		1236	#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /!< 0x40000000 /
		1237	#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /!< CEC interface reset /
2	mjames	1238
		1239
		1240
5	mjames	1241	#define RCC_APB1RSTR_DACRST_Pos (29U)
		1242	#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /!< 0x20000000 /
		1243	#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /!< DAC interface reset /
2	mjames	1244
		1245	/**************** Bit definition for RCC_AHBENR register ****************/
5	mjames	1246	#define RCC_AHBENR_DMA1EN_Pos (0U)
		1247	#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /!< 0x00000001 /
		1248	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /!< DMA1 clock enable /
		1249	#define RCC_AHBENR_SRAMEN_Pos (2U)
		1250	#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /!< 0x00000004 /
		1251	#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /!< SRAM interface clock enable /
		1252	#define RCC_AHBENR_FLITFEN_Pos (4U)
		1253	#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /!< 0x00000010 /
		1254	#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /!< FLITF clock enable /
		1255	#define RCC_AHBENR_CRCEN_Pos (6U)
		1256	#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /!< 0x00000040 /
		1257	#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /!< CRC clock enable /
2	mjames	1258
		1259
		1260
		1261
		1262	/**************** Bit definition for RCC_APB2ENR register ***************/
5	mjames	1263	#define RCC_APB2ENR_AFIOEN_Pos (0U)
		1264	#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /!< 0x00000001 /
		1265	#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /!< Alternate Function I/O clock enable /
		1266	#define RCC_APB2ENR_IOPAEN_Pos (2U)
		1267	#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /!< 0x00000004 /
		1268	#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /!< I/O port A clock enable /
		1269	#define RCC_APB2ENR_IOPBEN_Pos (3U)
		1270	#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /!< 0x00000008 /
		1271	#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /!< I/O port B clock enable /
		1272	#define RCC_APB2ENR_IOPCEN_Pos (4U)
		1273	#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /!< 0x00000010 /
		1274	#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /!< I/O port C clock enable /
		1275	#define RCC_APB2ENR_IOPDEN_Pos (5U)
		1276	#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /!< 0x00000020 /
		1277	#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /!< I/O port D clock enable /
		1278	#define RCC_APB2ENR_ADC1EN_Pos (9U)
		1279	#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /!< 0x00000200 /
		1280	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /!< ADC 1 interface clock enable /
2	mjames	1281
		1282
5	mjames	1283	#define RCC_APB2ENR_TIM1EN_Pos (11U)
		1284	#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /!< 0x00000800 /
		1285	#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /!< TIM1 Timer clock enable /
		1286	#define RCC_APB2ENR_SPI1EN_Pos (12U)
		1287	#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /!< 0x00001000 /
		1288	#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /!< SPI 1 clock enable /
		1289	#define RCC_APB2ENR_USART1EN_Pos (14U)
		1290	#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /!< 0x00004000 /
		1291	#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /!< USART1 clock enable /
2	mjames	1292
5	mjames	1293	#define RCC_APB2ENR_TIM15EN_Pos (16U)
		1294	#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /!< 0x00010000 /
		1295	#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /!< TIM15 Timer clock enable /
		1296	#define RCC_APB2ENR_TIM16EN_Pos (17U)
		1297	#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /!< 0x00020000 /
		1298	#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /!< TIM16 Timer clock enable /
		1299	#define RCC_APB2ENR_TIM17EN_Pos (18U)
		1300	#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /!< 0x00040000 /
		1301	#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /!< TIM17 Timer clock enable /
2	mjames	1302
5	mjames	1303	#define RCC_APB2ENR_IOPEEN_Pos (6U)
		1304	#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /!< 0x00000040 /
		1305	#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /!< I/O port E clock enable /
2	mjames	1306
		1307
		1308
		1309
		1310	/*************** Bit definition for RCC_APB1ENR register ****************/
5	mjames	1311	#define RCC_APB1ENR_TIM2EN_Pos (0U)
		1312	#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /!< 0x00000001 /
		1313	#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /!< Timer 2 clock enabled/
		1314	#define RCC_APB1ENR_TIM3EN_Pos (1U)
		1315	#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /!< 0x00000002 /
		1316	#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /!< Timer 3 clock enable /
		1317	#define RCC_APB1ENR_WWDGEN_Pos (11U)
		1318	#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /!< 0x00000800 /
		1319	#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /!< Window Watchdog clock enable /
		1320	#define RCC_APB1ENR_USART2EN_Pos (17U)
		1321	#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /!< 0x00020000 /
		1322	#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /!< USART 2 clock enable /
		1323	#define RCC_APB1ENR_I2C1EN_Pos (21U)
		1324	#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /!< 0x00200000 /
		1325	#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /!< I2C 1 clock enable /
2	mjames	1326
		1327
5	mjames	1328	#define RCC_APB1ENR_BKPEN_Pos (27U)
		1329	#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /!< 0x08000000 /
		1330	#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /!< Backup interface clock enable /
		1331	#define RCC_APB1ENR_PWREN_Pos (28U)
		1332	#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /!< 0x10000000 /
		1333	#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /!< Power interface clock enable /
2	mjames	1334
5	mjames	1335	#define RCC_APB1ENR_TIM4EN_Pos (2U)
		1336	#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /!< 0x00000004 /
		1337	#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /!< Timer 4 clock enable /
		1338	#define RCC_APB1ENR_SPI2EN_Pos (14U)
		1339	#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /!< 0x00004000 /
		1340	#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /!< SPI 2 clock enable /
		1341	#define RCC_APB1ENR_USART3EN_Pos (18U)
		1342	#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /!< 0x00040000 /
		1343	#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /!< USART 3 clock enable /
		1344	#define RCC_APB1ENR_I2C2EN_Pos (22U)
		1345	#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /!< 0x00400000 /
		1346	#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /!< I2C 2 clock enable /
2	mjames	1347
		1348
		1349
5	mjames	1350	#define RCC_APB1ENR_TIM6EN_Pos (4U)
		1351	#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /!< 0x00000010 /
		1352	#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /!< Timer 6 clock enable /
		1353	#define RCC_APB1ENR_TIM7EN_Pos (5U)
		1354	#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /!< 0x00000020 /
		1355	#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /!< Timer 7 clock enable /
		1356	#define RCC_APB1ENR_CECEN_Pos (30U)
		1357	#define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /!< 0x40000000 /
		1358	#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /!< CEC interface clock enable /
2	mjames	1359
		1360
		1361
5	mjames	1362	#define RCC_APB1ENR_DACEN_Pos (29U)
		1363	#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /!< 0x20000000 /
		1364	#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /!< DAC interface clock enable /
2	mjames	1365
		1366	/***************** Bit definition for RCC_BDCR register *****************/
5	mjames	1367	#define RCC_BDCR_LSEON_Pos (0U)
		1368	#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /!< 0x00000001 /
		1369	#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /!< External Low Speed oscillator enable /
		1370	#define RCC_BDCR_LSERDY_Pos (1U)
		1371	#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /!< 0x00000002 /
		1372	#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /!< External Low Speed oscillator Ready /
		1373	#define RCC_BDCR_LSEBYP_Pos (2U)
		1374	#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /!< 0x00000004 /
		1375	#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /!< External Low Speed oscillator Bypass /
2	mjames	1376
5	mjames	1377	#define RCC_BDCR_RTCSEL_Pos (8U)
		1378	#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000300 /
		1379	#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /!< RTCSEL[1:0] bits (RTC clock source selection) /
		1380	#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000100 /
		1381	#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000200 /
2	mjames	1382
		1383	/!< RTC congiguration /
5	mjames	1384	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
		1385	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
		1386	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
		1387	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
2	mjames	1388
5	mjames	1389	#define RCC_BDCR_RTCEN_Pos (15U)
		1390	#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /!< 0x00008000 /
		1391	#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /!< RTC clock enable /
		1392	#define RCC_BDCR_BDRST_Pos (16U)
		1393	#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /!< 0x00010000 /
		1394	#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /!< Backup domain software reset /
2	mjames	1395
		1396	/***************** Bit definition for RCC_CSR register ******************/
5	mjames	1397	#define RCC_CSR_LSION_Pos (0U)
		1398	#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /!< 0x00000001 /
		1399	#define RCC_CSR_LSION RCC_CSR_LSION_Msk /!< Internal Low Speed oscillator enable /
		1400	#define RCC_CSR_LSIRDY_Pos (1U)
		1401	#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /!< 0x00000002 /
		1402	#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /!< Internal Low Speed oscillator Ready /
		1403	#define RCC_CSR_RMVF_Pos (24U)
		1404	#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /!< 0x01000000 /
		1405	#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /!< Remove reset flag /
		1406	#define RCC_CSR_PINRSTF_Pos (26U)
		1407	#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /!< 0x04000000 /
		1408	#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /!< PIN reset flag /
		1409	#define RCC_CSR_PORRSTF_Pos (27U)
		1410	#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /!< 0x08000000 /
		1411	#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /!< POR/PDR reset flag /
		1412	#define RCC_CSR_SFTRSTF_Pos (28U)
		1413	#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /!< 0x10000000 /
		1414	#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /!< Software Reset flag /
		1415	#define RCC_CSR_IWDGRSTF_Pos (29U)
		1416	#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /!< 0x20000000 /
		1417	#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /!< Independent Watchdog reset flag /
		1418	#define RCC_CSR_WWDGRSTF_Pos (30U)
		1419	#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /!< 0x40000000 /
		1420	#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /!< Window watchdog reset flag /
		1421	#define RCC_CSR_LPWRRSTF_Pos (31U)
		1422	#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /!< 0x80000000 /
		1423	#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /!< Low-Power reset flag /
2	mjames	1424
		1425
		1426	/***************** Bit definition for RCC_CFGR2 register ****************/
		1427	/!< PREDIV1 configuration /
5	mjames	1428	#define RCC_CFGR2_PREDIV1_Pos (0U)
		1429	#define RCC_CFGR2_PREDIV1_Msk (0xFU << RCC_CFGR2_PREDIV1_Pos) /!< 0x0000000F /
		1430	#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /!< PREDIV1[3:0] bits /
		1431	#define RCC_CFGR2_PREDIV1_0 (0x1U << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000001 /
		1432	#define RCC_CFGR2_PREDIV1_1 (0x2U << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000002 /
		1433	#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000004 /
		1434	#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000008 /
2	mjames	1435
5	mjames	1436	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
		1437	#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
		1438	#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /!< 0x00000001 /
		1439	#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /!< PREDIV1 input clock divided by 2 /
		1440	#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U)
		1441	#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV3_Pos) /!< 0x00000002 /
		1442	#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /!< PREDIV1 input clock divided by 3 /
		1443	#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U)
		1444	#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV4_Pos) /!< 0x00000003 /
		1445	#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /!< PREDIV1 input clock divided by 4 /
		1446	#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U)
		1447	#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV5_Pos) /!< 0x00000004 /
		1448	#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /!< PREDIV1 input clock divided by 5 /
		1449	#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U)
		1450	#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV6_Pos) /!< 0x00000005 /
		1451	#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /!< PREDIV1 input clock divided by 6 /
		1452	#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U)
		1453	#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV7_Pos) /!< 0x00000006 /
		1454	#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /!< PREDIV1 input clock divided by 7 /
		1455	#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U)
		1456	#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV8_Pos) /!< 0x00000007 /
		1457	#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /!< PREDIV1 input clock divided by 8 /
		1458	#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U)
		1459	#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV9_Pos) /!< 0x00000008 /
		1460	#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /!< PREDIV1 input clock divided by 9 /
		1461	#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U)
		1462	#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV1_DIV10_Pos) /!< 0x00000009 /
		1463	#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /!< PREDIV1 input clock divided by 10 /
		1464	#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U)
		1465	#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV11_Pos) /!< 0x0000000A /
		1466	#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /!< PREDIV1 input clock divided by 11 /
		1467	#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U)
		1468	#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV1_DIV12_Pos) /!< 0x0000000B /
		1469	#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /!< PREDIV1 input clock divided by 12 /
		1470	#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U)
		1471	#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV13_Pos) /!< 0x0000000C /
		1472	#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /!< PREDIV1 input clock divided by 13 /
		1473	#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U)
		1474	#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV1_DIV14_Pos) /!< 0x0000000D /
		1475	#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /!< PREDIV1 input clock divided by 14 /
		1476	#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U)
		1477	#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV15_Pos) /!< 0x0000000E /
		1478	#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /!< PREDIV1 input clock divided by 15 /
		1479	#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U)
		1480	#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV1_DIV16_Pos) /!< 0x0000000F /
		1481	#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /!< PREDIV1 input clock divided by 16 /
2	mjames	1482
		1483	/******************************************************************************/
		1484	/* */
		1485	/* General Purpose and Alternate Function I/O */
		1486	/* */
		1487	/******************************************************************************/
		1488
		1489	/***************** Bit definition for GPIO_CRL register *****************/
5	mjames	1490	#define GPIO_CRL_MODE_Pos (0U)
		1491	#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /!< 0x33333333 /
		1492	#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /!< Port x mode bits /
2	mjames	1493
5	mjames	1494	#define GPIO_CRL_MODE0_Pos (0U)
		1495	#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /!< 0x00000003 /
		1496	#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
		1497	#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /!< 0x00000001 /
		1498	#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /!< 0x00000002 /
2	mjames	1499
5	mjames	1500	#define GPIO_CRL_MODE1_Pos (4U)
		1501	#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /!< 0x00000030 /
		1502	#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
		1503	#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /!< 0x00000010 /
		1504	#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /!< 0x00000020 /
2	mjames	1505
5	mjames	1506	#define GPIO_CRL_MODE2_Pos (8U)
		1507	#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /!< 0x00000300 /
		1508	#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
		1509	#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /!< 0x00000100 /
		1510	#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /!< 0x00000200 /
2	mjames	1511
5	mjames	1512	#define GPIO_CRL_MODE3_Pos (12U)
		1513	#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /!< 0x00003000 /
		1514	#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
		1515	#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /!< 0x00001000 /
		1516	#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /!< 0x00002000 /
2	mjames	1517
5	mjames	1518	#define GPIO_CRL_MODE4_Pos (16U)
		1519	#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /!< 0x00030000 /
		1520	#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
		1521	#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /!< 0x00010000 /
		1522	#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /!< 0x00020000 /
2	mjames	1523
5	mjames	1524	#define GPIO_CRL_MODE5_Pos (20U)
		1525	#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /!< 0x00300000 /
		1526	#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
		1527	#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /!< 0x00100000 /
		1528	#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /!< 0x00200000 /
2	mjames	1529
5	mjames	1530	#define GPIO_CRL_MODE6_Pos (24U)
		1531	#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /!< 0x03000000 /
		1532	#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
		1533	#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /!< 0x01000000 /
		1534	#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /!< 0x02000000 /
2	mjames	1535
5	mjames	1536	#define GPIO_CRL_MODE7_Pos (28U)
		1537	#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /!< 0x30000000 /
		1538	#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
		1539	#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /!< 0x10000000 /
		1540	#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /!< 0x20000000 /
2	mjames	1541
5	mjames	1542	#define GPIO_CRL_CNF_Pos (2U)
		1543	#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /!< 0xCCCCCCCC /
		1544	#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /!< Port x configuration bits /
2	mjames	1545
5	mjames	1546	#define GPIO_CRL_CNF0_Pos (2U)
		1547	#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /!< 0x0000000C /
		1548	#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
		1549	#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /!< 0x00000004 /
		1550	#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /!< 0x00000008 /
2	mjames	1551
5	mjames	1552	#define GPIO_CRL_CNF1_Pos (6U)
		1553	#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /!< 0x000000C0 /
		1554	#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
		1555	#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /!< 0x00000040 /
		1556	#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /!< 0x00000080 /
2	mjames	1557
5	mjames	1558	#define GPIO_CRL_CNF2_Pos (10U)
		1559	#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /!< 0x00000C00 /
		1560	#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
		1561	#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /!< 0x00000400 /
		1562	#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /!< 0x00000800 /
2	mjames	1563
5	mjames	1564	#define GPIO_CRL_CNF3_Pos (14U)
		1565	#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /!< 0x0000C000 /
		1566	#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
		1567	#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /!< 0x00004000 /
		1568	#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /!< 0x00008000 /
2	mjames	1569
5	mjames	1570	#define GPIO_CRL_CNF4_Pos (18U)
		1571	#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /!< 0x000C0000 /
		1572	#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
		1573	#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /!< 0x00040000 /
		1574	#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /!< 0x00080000 /
2	mjames	1575
5	mjames	1576	#define GPIO_CRL_CNF5_Pos (22U)
		1577	#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /!< 0x00C00000 /
		1578	#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
		1579	#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /!< 0x00400000 /
		1580	#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /!< 0x00800000 /
2	mjames	1581
5	mjames	1582	#define GPIO_CRL_CNF6_Pos (26U)
		1583	#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /!< 0x0C000000 /
		1584	#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
		1585	#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /!< 0x04000000 /
		1586	#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /!< 0x08000000 /
2	mjames	1587
5	mjames	1588	#define GPIO_CRL_CNF7_Pos (30U)
		1589	#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /!< 0xC0000000 /
		1590	#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
		1591	#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /!< 0x40000000 /
		1592	#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /!< 0x80000000 /
2	mjames	1593
		1594	/***************** Bit definition for GPIO_CRH register *****************/
5	mjames	1595	#define GPIO_CRH_MODE_Pos (0U)
		1596	#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /!< 0x33333333 /
		1597	#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /!< Port x mode bits /
2	mjames	1598
5	mjames	1599	#define GPIO_CRH_MODE8_Pos (0U)
		1600	#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /!< 0x00000003 /
		1601	#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
		1602	#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /!< 0x00000001 /
		1603	#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /!< 0x00000002 /
2	mjames	1604
5	mjames	1605	#define GPIO_CRH_MODE9_Pos (4U)
		1606	#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /!< 0x00000030 /
		1607	#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
		1608	#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /!< 0x00000010 /
		1609	#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /!< 0x00000020 /
2	mjames	1610
5	mjames	1611	#define GPIO_CRH_MODE10_Pos (8U)
		1612	#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /!< 0x00000300 /
		1613	#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
		1614	#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /!< 0x00000100 /
		1615	#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /!< 0x00000200 /
2	mjames	1616
5	mjames	1617	#define GPIO_CRH_MODE11_Pos (12U)
		1618	#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /!< 0x00003000 /
		1619	#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
		1620	#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /!< 0x00001000 /
		1621	#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /!< 0x00002000 /
2	mjames	1622
5	mjames	1623	#define GPIO_CRH_MODE12_Pos (16U)
		1624	#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /!< 0x00030000 /
		1625	#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
		1626	#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /!< 0x00010000 /
		1627	#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /!< 0x00020000 /
2	mjames	1628
5	mjames	1629	#define GPIO_CRH_MODE13_Pos (20U)
		1630	#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /!< 0x00300000 /
		1631	#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
		1632	#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /!< 0x00100000 /
		1633	#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /!< 0x00200000 /
2	mjames	1634
5	mjames	1635	#define GPIO_CRH_MODE14_Pos (24U)
		1636	#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /!< 0x03000000 /
		1637	#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
		1638	#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /!< 0x01000000 /
		1639	#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /!< 0x02000000 /
2	mjames	1640
5	mjames	1641	#define GPIO_CRH_MODE15_Pos (28U)
		1642	#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /!< 0x30000000 /
		1643	#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
		1644	#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /!< 0x10000000 /
		1645	#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /!< 0x20000000 /
2	mjames	1646
5	mjames	1647	#define GPIO_CRH_CNF_Pos (2U)
		1648	#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /!< 0xCCCCCCCC /
		1649	#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /!< Port x configuration bits /
2	mjames	1650
5	mjames	1651	#define GPIO_CRH_CNF8_Pos (2U)
		1652	#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /!< 0x0000000C /
		1653	#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
		1654	#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /!< 0x00000004 /
		1655	#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /!< 0x00000008 /
2	mjames	1656
5	mjames	1657	#define GPIO_CRH_CNF9_Pos (6U)
		1658	#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /!< 0x000000C0 /
		1659	#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
		1660	#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /!< 0x00000040 /
		1661	#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /!< 0x00000080 /
2	mjames	1662
5	mjames	1663	#define GPIO_CRH_CNF10_Pos (10U)
		1664	#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /!< 0x00000C00 /
		1665	#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
		1666	#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /!< 0x00000400 /
		1667	#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /!< 0x00000800 /
2	mjames	1668
5	mjames	1669	#define GPIO_CRH_CNF11_Pos (14U)
		1670	#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /!< 0x0000C000 /
		1671	#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
		1672	#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /!< 0x00004000 /
		1673	#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /!< 0x00008000 /
2	mjames	1674
5	mjames	1675	#define GPIO_CRH_CNF12_Pos (18U)
		1676	#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /!< 0x000C0000 /
		1677	#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
		1678	#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /!< 0x00040000 /
		1679	#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /!< 0x00080000 /
2	mjames	1680
5	mjames	1681	#define GPIO_CRH_CNF13_Pos (22U)
		1682	#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /!< 0x00C00000 /
		1683	#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
		1684	#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /!< 0x00400000 /
		1685	#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /!< 0x00800000 /
2	mjames	1686
5	mjames	1687	#define GPIO_CRH_CNF14_Pos (26U)
		1688	#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /!< 0x0C000000 /
		1689	#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
		1690	#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /!< 0x04000000 /
		1691	#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /!< 0x08000000 /
2	mjames	1692
5	mjames	1693	#define GPIO_CRH_CNF15_Pos (30U)
		1694	#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /!< 0xC0000000 /
		1695	#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
		1696	#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /!< 0x40000000 /
		1697	#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /!< 0x80000000 /
2	mjames	1698
		1699	/!<*************** Bit definition for GPIO_IDR register *****************/
5	mjames	1700	#define GPIO_IDR_IDR0_Pos (0U)
		1701	#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /!< 0x00000001 /
		1702	#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /!< Port input data, bit 0 /
		1703	#define GPIO_IDR_IDR1_Pos (1U)
		1704	#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /!< 0x00000002 /
		1705	#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /!< Port input data, bit 1 /
		1706	#define GPIO_IDR_IDR2_Pos (2U)
		1707	#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /!< 0x00000004 /
		1708	#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /!< Port input data, bit 2 /
		1709	#define GPIO_IDR_IDR3_Pos (3U)
		1710	#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /!< 0x00000008 /
		1711	#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /!< Port input data, bit 3 /
		1712	#define GPIO_IDR_IDR4_Pos (4U)
		1713	#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /!< 0x00000010 /
		1714	#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /!< Port input data, bit 4 /
		1715	#define GPIO_IDR_IDR5_Pos (5U)
		1716	#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /!< 0x00000020 /
		1717	#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /!< Port input data, bit 5 /
		1718	#define GPIO_IDR_IDR6_Pos (6U)
		1719	#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /!< 0x00000040 /
		1720	#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /!< Port input data, bit 6 /
		1721	#define GPIO_IDR_IDR7_Pos (7U)
		1722	#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /!< 0x00000080 /
		1723	#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /!< Port input data, bit 7 /
		1724	#define GPIO_IDR_IDR8_Pos (8U)
		1725	#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /!< 0x00000100 /
		1726	#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /!< Port input data, bit 8 /
		1727	#define GPIO_IDR_IDR9_Pos (9U)
		1728	#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /!< 0x00000200 /
		1729	#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /!< Port input data, bit 9 /
		1730	#define GPIO_IDR_IDR10_Pos (10U)
		1731	#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /!< 0x00000400 /
		1732	#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /!< Port input data, bit 10 /
		1733	#define GPIO_IDR_IDR11_Pos (11U)
		1734	#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /!< 0x00000800 /
		1735	#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /!< Port input data, bit 11 /
		1736	#define GPIO_IDR_IDR12_Pos (12U)
		1737	#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /!< 0x00001000 /
		1738	#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /!< Port input data, bit 12 /
		1739	#define GPIO_IDR_IDR13_Pos (13U)
		1740	#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /!< 0x00002000 /
		1741	#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /!< Port input data, bit 13 /
		1742	#define GPIO_IDR_IDR14_Pos (14U)
		1743	#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /!< 0x00004000 /
		1744	#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /!< Port input data, bit 14 /
		1745	#define GPIO_IDR_IDR15_Pos (15U)
		1746	#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /!< 0x00008000 /
		1747	#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /!< Port input data, bit 15 /
2	mjames	1748
		1749	/***************** Bit definition for GPIO_ODR register *****************/
5	mjames	1750	#define GPIO_ODR_ODR0_Pos (0U)
		1751	#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /!< 0x00000001 /
		1752	#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /!< Port output data, bit 0 /
		1753	#define GPIO_ODR_ODR1_Pos (1U)
		1754	#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /!< 0x00000002 /
		1755	#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /!< Port output data, bit 1 /
		1756	#define GPIO_ODR_ODR2_Pos (2U)
		1757	#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /!< 0x00000004 /
		1758	#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /!< Port output data, bit 2 /
		1759	#define GPIO_ODR_ODR3_Pos (3U)
		1760	#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /!< 0x00000008 /
		1761	#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /!< Port output data, bit 3 /
		1762	#define GPIO_ODR_ODR4_Pos (4U)
		1763	#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /!< 0x00000010 /
		1764	#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /!< Port output data, bit 4 /
		1765	#define GPIO_ODR_ODR5_Pos (5U)
		1766	#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /!< 0x00000020 /
		1767	#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /!< Port output data, bit 5 /
		1768	#define GPIO_ODR_ODR6_Pos (6U)
		1769	#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /!< 0x00000040 /
		1770	#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /!< Port output data, bit 6 /
		1771	#define GPIO_ODR_ODR7_Pos (7U)
		1772	#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /!< 0x00000080 /
		1773	#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /!< Port output data, bit 7 /
		1774	#define GPIO_ODR_ODR8_Pos (8U)
		1775	#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /!< 0x00000100 /
		1776	#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /!< Port output data, bit 8 /
		1777	#define GPIO_ODR_ODR9_Pos (9U)
		1778	#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /!< 0x00000200 /
		1779	#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /!< Port output data, bit 9 /
		1780	#define GPIO_ODR_ODR10_Pos (10U)
		1781	#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /!< 0x00000400 /
		1782	#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /!< Port output data, bit 10 /
		1783	#define GPIO_ODR_ODR11_Pos (11U)
		1784	#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /!< 0x00000800 /
		1785	#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /!< Port output data, bit 11 /
		1786	#define GPIO_ODR_ODR12_Pos (12U)
		1787	#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /!< 0x00001000 /
		1788	#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /!< Port output data, bit 12 /
		1789	#define GPIO_ODR_ODR13_Pos (13U)
		1790	#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /!< 0x00002000 /
		1791	#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /!< Port output data, bit 13 /
		1792	#define GPIO_ODR_ODR14_Pos (14U)
		1793	#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /!< 0x00004000 /
		1794	#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /!< Port output data, bit 14 /
		1795	#define GPIO_ODR_ODR15_Pos (15U)
		1796	#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /!< 0x00008000 /
		1797	#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /!< Port output data, bit 15 /
2	mjames	1798
		1799	/**************** Bit definition for GPIO_BSRR register *****************/
5	mjames	1800	#define GPIO_BSRR_BS0_Pos (0U)
		1801	#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /!< 0x00000001 /
		1802	#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /!< Port x Set bit 0 /
		1803	#define GPIO_BSRR_BS1_Pos (1U)
		1804	#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /!< 0x00000002 /
		1805	#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /!< Port x Set bit 1 /
		1806	#define GPIO_BSRR_BS2_Pos (2U)
		1807	#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /!< 0x00000004 /
		1808	#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /!< Port x Set bit 2 /
		1809	#define GPIO_BSRR_BS3_Pos (3U)
		1810	#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /!< 0x00000008 /
		1811	#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /!< Port x Set bit 3 /
		1812	#define GPIO_BSRR_BS4_Pos (4U)
		1813	#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /!< 0x00000010 /
		1814	#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /!< Port x Set bit 4 /
		1815	#define GPIO_BSRR_BS5_Pos (5U)
		1816	#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /!< 0x00000020 /
		1817	#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /!< Port x Set bit 5 /
		1818	#define GPIO_BSRR_BS6_Pos (6U)
		1819	#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /!< 0x00000040 /
		1820	#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /!< Port x Set bit 6 /
		1821	#define GPIO_BSRR_BS7_Pos (7U)
		1822	#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /!< 0x00000080 /
		1823	#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /!< Port x Set bit 7 /
		1824	#define GPIO_BSRR_BS8_Pos (8U)
		1825	#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /!< 0x00000100 /
		1826	#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /!< Port x Set bit 8 /
		1827	#define GPIO_BSRR_BS9_Pos (9U)
		1828	#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /!< 0x00000200 /
		1829	#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /!< Port x Set bit 9 /
		1830	#define GPIO_BSRR_BS10_Pos (10U)
		1831	#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /!< 0x00000400 /
		1832	#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /!< Port x Set bit 10 /
		1833	#define GPIO_BSRR_BS11_Pos (11U)
		1834	#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /!< 0x00000800 /
		1835	#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /!< Port x Set bit 11 /
		1836	#define GPIO_BSRR_BS12_Pos (12U)
		1837	#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /!< 0x00001000 /
		1838	#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /!< Port x Set bit 12 /
		1839	#define GPIO_BSRR_BS13_Pos (13U)
		1840	#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /!< 0x00002000 /
		1841	#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /!< Port x Set bit 13 /
		1842	#define GPIO_BSRR_BS14_Pos (14U)
		1843	#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /!< 0x00004000 /
		1844	#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /!< Port x Set bit 14 /
		1845	#define GPIO_BSRR_BS15_Pos (15U)
		1846	#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /!< 0x00008000 /
		1847	#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /!< Port x Set bit 15 /
2	mjames	1848
5	mjames	1849	#define GPIO_BSRR_BR0_Pos (16U)
		1850	#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /!< 0x00010000 /
		1851	#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /!< Port x Reset bit 0 /
		1852	#define GPIO_BSRR_BR1_Pos (17U)
		1853	#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /!< 0x00020000 /
		1854	#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /!< Port x Reset bit 1 /
		1855	#define GPIO_BSRR_BR2_Pos (18U)
		1856	#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /!< 0x00040000 /
		1857	#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /!< Port x Reset bit 2 /
		1858	#define GPIO_BSRR_BR3_Pos (19U)
		1859	#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /!< 0x00080000 /
		1860	#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /!< Port x Reset bit 3 /
		1861	#define GPIO_BSRR_BR4_Pos (20U)
		1862	#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /!< 0x00100000 /
		1863	#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /!< Port x Reset bit 4 /
		1864	#define GPIO_BSRR_BR5_Pos (21U)
		1865	#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /!< 0x00200000 /
		1866	#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /!< Port x Reset bit 5 /
		1867	#define GPIO_BSRR_BR6_Pos (22U)
		1868	#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /!< 0x00400000 /
		1869	#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /!< Port x Reset bit 6 /
		1870	#define GPIO_BSRR_BR7_Pos (23U)
		1871	#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /!< 0x00800000 /
		1872	#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /!< Port x Reset bit 7 /
		1873	#define GPIO_BSRR_BR8_Pos (24U)
		1874	#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /!< 0x01000000 /
		1875	#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /!< Port x Reset bit 8 /
		1876	#define GPIO_BSRR_BR9_Pos (25U)
		1877	#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /!< 0x02000000 /
		1878	#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /!< Port x Reset bit 9 /
		1879	#define GPIO_BSRR_BR10_Pos (26U)
		1880	#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /!< 0x04000000 /
		1881	#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /!< Port x Reset bit 10 /
		1882	#define GPIO_BSRR_BR11_Pos (27U)
		1883	#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /!< 0x08000000 /
		1884	#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /!< Port x Reset bit 11 /
		1885	#define GPIO_BSRR_BR12_Pos (28U)
		1886	#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /!< 0x10000000 /
		1887	#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /!< Port x Reset bit 12 /
		1888	#define GPIO_BSRR_BR13_Pos (29U)
		1889	#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /!< 0x20000000 /
		1890	#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /!< Port x Reset bit 13 /
		1891	#define GPIO_BSRR_BR14_Pos (30U)
		1892	#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /!< 0x40000000 /
		1893	#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /!< Port x Reset bit 14 /
		1894	#define GPIO_BSRR_BR15_Pos (31U)
		1895	#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /!< 0x80000000 /
		1896	#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /!< Port x Reset bit 15 /
2	mjames	1897
		1898	/***************** Bit definition for GPIO_BRR register *****************/
5	mjames	1899	#define GPIO_BRR_BR0_Pos (0U)
		1900	#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /!< 0x00000001 /
		1901	#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /!< Port x Reset bit 0 /
		1902	#define GPIO_BRR_BR1_Pos (1U)
		1903	#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /!< 0x00000002 /
		1904	#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /!< Port x Reset bit 1 /
		1905	#define GPIO_BRR_BR2_Pos (2U)
		1906	#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /!< 0x00000004 /
		1907	#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /!< Port x Reset bit 2 /
		1908	#define GPIO_BRR_BR3_Pos (3U)
		1909	#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /!< 0x00000008 /
		1910	#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /!< Port x Reset bit 3 /
		1911	#define GPIO_BRR_BR4_Pos (4U)
		1912	#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /!< 0x00000010 /
		1913	#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /!< Port x Reset bit 4 /
		1914	#define GPIO_BRR_BR5_Pos (5U)
		1915	#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /!< 0x00000020 /
		1916	#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /!< Port x Reset bit 5 /
		1917	#define GPIO_BRR_BR6_Pos (6U)
		1918	#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /!< 0x00000040 /
		1919	#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /!< Port x Reset bit 6 /
		1920	#define GPIO_BRR_BR7_Pos (7U)
		1921	#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /!< 0x00000080 /
		1922	#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /!< Port x Reset bit 7 /
		1923	#define GPIO_BRR_BR8_Pos (8U)
		1924	#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /!< 0x00000100 /
		1925	#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /!< Port x Reset bit 8 /
		1926	#define GPIO_BRR_BR9_Pos (9U)
		1927	#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /!< 0x00000200 /
		1928	#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /!< Port x Reset bit 9 /
		1929	#define GPIO_BRR_BR10_Pos (10U)
		1930	#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /!< 0x00000400 /
		1931	#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /!< Port x Reset bit 10 /
		1932	#define GPIO_BRR_BR11_Pos (11U)
		1933	#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /!< 0x00000800 /
		1934	#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /!< Port x Reset bit 11 /
		1935	#define GPIO_BRR_BR12_Pos (12U)
		1936	#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /!< 0x00001000 /
		1937	#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /!< Port x Reset bit 12 /
		1938	#define GPIO_BRR_BR13_Pos (13U)
		1939	#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /!< 0x00002000 /
		1940	#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /!< Port x Reset bit 13 /
		1941	#define GPIO_BRR_BR14_Pos (14U)
		1942	#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /!< 0x00004000 /
		1943	#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /!< Port x Reset bit 14 /
		1944	#define GPIO_BRR_BR15_Pos (15U)
		1945	#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /!< 0x00008000 /
		1946	#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /!< Port x Reset bit 15 /
2	mjames	1947
		1948	/**************** Bit definition for GPIO_LCKR register *****************/
5	mjames	1949	#define GPIO_LCKR_LCK0_Pos (0U)
		1950	#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /!< 0x00000001 /
		1951	#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /!< Port x Lock bit 0 /
		1952	#define GPIO_LCKR_LCK1_Pos (1U)
		1953	#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /!< 0x00000002 /
		1954	#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /!< Port x Lock bit 1 /
		1955	#define GPIO_LCKR_LCK2_Pos (2U)
		1956	#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /!< 0x00000004 /
		1957	#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /!< Port x Lock bit 2 /
		1958	#define GPIO_LCKR_LCK3_Pos (3U)
		1959	#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /!< 0x00000008 /
		1960	#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /!< Port x Lock bit 3 /
		1961	#define GPIO_LCKR_LCK4_Pos (4U)
		1962	#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /!< 0x00000010 /
		1963	#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /!< Port x Lock bit 4 /
		1964	#define GPIO_LCKR_LCK5_Pos (5U)
		1965	#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /!< 0x00000020 /
		1966	#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /!< Port x Lock bit 5 /
		1967	#define GPIO_LCKR_LCK6_Pos (6U)
		1968	#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /!< 0x00000040 /
		1969	#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /!< Port x Lock bit 6 /
		1970	#define GPIO_LCKR_LCK7_Pos (7U)
		1971	#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /!< 0x00000080 /
		1972	#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /!< Port x Lock bit 7 /
		1973	#define GPIO_LCKR_LCK8_Pos (8U)
		1974	#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /!< 0x00000100 /
		1975	#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /!< Port x Lock bit 8 /
		1976	#define GPIO_LCKR_LCK9_Pos (9U)
		1977	#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /!< 0x00000200 /
		1978	#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /!< Port x Lock bit 9 /
		1979	#define GPIO_LCKR_LCK10_Pos (10U)
		1980	#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /!< 0x00000400 /
		1981	#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /!< Port x Lock bit 10 /
		1982	#define GPIO_LCKR_LCK11_Pos (11U)
		1983	#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /!< 0x00000800 /
		1984	#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /!< Port x Lock bit 11 /
		1985	#define GPIO_LCKR_LCK12_Pos (12U)
		1986	#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /!< 0x00001000 /
		1987	#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /!< Port x Lock bit 12 /
		1988	#define GPIO_LCKR_LCK13_Pos (13U)
		1989	#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /!< 0x00002000 /
		1990	#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /!< Port x Lock bit 13 /
		1991	#define GPIO_LCKR_LCK14_Pos (14U)
		1992	#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /!< 0x00004000 /
		1993	#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /!< Port x Lock bit 14 /
		1994	#define GPIO_LCKR_LCK15_Pos (15U)
		1995	#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /!< 0x00008000 /
		1996	#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /!< Port x Lock bit 15 /
		1997	#define GPIO_LCKR_LCKK_Pos (16U)
		1998	#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /!< 0x00010000 /
		1999	#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /!< Lock key /
2	mjames	2000
		2001	/----------------------------------------------------------------------------/
		2002
		2003	/**************** Bit definition for AFIO_EVCR register *****************/
5	mjames	2004	#define AFIO_EVCR_PIN_Pos (0U)
		2005	#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /!< 0x0000000F /
		2006	#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /!< PIN[3:0] bits (Pin selection) /
		2007	#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /!< 0x00000001 /
		2008	#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /!< 0x00000002 /
		2009	#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /!< 0x00000004 /
		2010	#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /!< 0x00000008 /
2	mjames	2011
		2012	/!< PIN configuration /
5	mjames	2013	#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /!< Pin 0 selected /
		2014	#define AFIO_EVCR_PIN_PX1_Pos (0U)
		2015	#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /!< 0x00000001 /
		2016	#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /!< Pin 1 selected /
		2017	#define AFIO_EVCR_PIN_PX2_Pos (1U)
		2018	#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /!< 0x00000002 /
		2019	#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /!< Pin 2 selected /
		2020	#define AFIO_EVCR_PIN_PX3_Pos (0U)
		2021	#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /!< 0x00000003 /
		2022	#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /!< Pin 3 selected /
		2023	#define AFIO_EVCR_PIN_PX4_Pos (2U)
		2024	#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /!< 0x00000004 /
		2025	#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /!< Pin 4 selected /
		2026	#define AFIO_EVCR_PIN_PX5_Pos (0U)
		2027	#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /!< 0x00000005 /
		2028	#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /!< Pin 5 selected /
		2029	#define AFIO_EVCR_PIN_PX6_Pos (1U)
		2030	#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /!< 0x00000006 /
		2031	#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /!< Pin 6 selected /
		2032	#define AFIO_EVCR_PIN_PX7_Pos (0U)
		2033	#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /!< 0x00000007 /
		2034	#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /!< Pin 7 selected /
		2035	#define AFIO_EVCR_PIN_PX8_Pos (3U)
		2036	#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /!< 0x00000008 /
		2037	#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /!< Pin 8 selected /
		2038	#define AFIO_EVCR_PIN_PX9_Pos (0U)
		2039	#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /!< 0x00000009 /
		2040	#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /!< Pin 9 selected /
		2041	#define AFIO_EVCR_PIN_PX10_Pos (1U)
		2042	#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /!< 0x0000000A /
		2043	#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /!< Pin 10 selected /
		2044	#define AFIO_EVCR_PIN_PX11_Pos (0U)
		2045	#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /!< 0x0000000B /
		2046	#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /!< Pin 11 selected /
		2047	#define AFIO_EVCR_PIN_PX12_Pos (2U)
		2048	#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /!< 0x0000000C /
		2049	#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /!< Pin 12 selected /
		2050	#define AFIO_EVCR_PIN_PX13_Pos (0U)
		2051	#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /!< 0x0000000D /
		2052	#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /!< Pin 13 selected /
		2053	#define AFIO_EVCR_PIN_PX14_Pos (1U)
		2054	#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /!< 0x0000000E /
		2055	#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /!< Pin 14 selected /
		2056	#define AFIO_EVCR_PIN_PX15_Pos (0U)
		2057	#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /!< 0x0000000F /
		2058	#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /!< Pin 15 selected /
2	mjames	2059
5	mjames	2060	#define AFIO_EVCR_PORT_Pos (4U)
		2061	#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /!< 0x00000070 /
		2062	#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /!< PORT[2:0] bits (Port selection) /
		2063	#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /!< 0x00000010 /
		2064	#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /!< 0x00000020 /
		2065	#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /!< 0x00000040 /
2	mjames	2066
		2067	/!< PORT configuration /
5	mjames	2068	#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /!< Port A selected /
		2069	#define AFIO_EVCR_PORT_PB_Pos (4U)
		2070	#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /!< 0x00000010 /
		2071	#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /!< Port B selected /
		2072	#define AFIO_EVCR_PORT_PC_Pos (5U)
		2073	#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /!< 0x00000020 /
		2074	#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /!< Port C selected /
		2075	#define AFIO_EVCR_PORT_PD_Pos (4U)
		2076	#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /!< 0x00000030 /
		2077	#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /!< Port D selected /
		2078	#define AFIO_EVCR_PORT_PE_Pos (6U)
		2079	#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /!< 0x00000040 /
		2080	#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /!< Port E selected /
2	mjames	2081
5	mjames	2082	#define AFIO_EVCR_EVOE_Pos (7U)
		2083	#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /!< 0x00000080 /
		2084	#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /!< Event Output Enable /
2	mjames	2085
		2086	/**************** Bit definition for AFIO_MAPR register *****************/
5	mjames	2087	#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
		2088	#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /!< 0x00000001 /
		2089	#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /!< SPI1 remapping /
		2090	#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
		2091	#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /!< 0x00000002 /
		2092	#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /!< I2C1 remapping /
		2093	#define AFIO_MAPR_USART1_REMAP_Pos (2U)
		2094	#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /!< 0x00000004 /
		2095	#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /!< USART1 remapping /
		2096	#define AFIO_MAPR_USART2_REMAP_Pos (3U)
		2097	#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /!< 0x00000008 /
		2098	#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /!< USART2 remapping /
2	mjames	2099
5	mjames	2100	#define AFIO_MAPR_USART3_REMAP_Pos (4U)
		2101	#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000030 /
		2102	#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /!< USART3_REMAP[1:0] bits (USART3 remapping) /
		2103	#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000010 /
		2104	#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000020 /
2	mjames	2105
		2106	/* USART3_REMAP configuration */
5	mjames	2107	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
		2108	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
		2109	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /!< 0x00000010 /
		2110	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
		2111	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
		2112	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /!< 0x00000030 /
		2113	#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
2	mjames	2114
5	mjames	2115	#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
		2116	#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x000000C0 /
		2117	#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
		2118	#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000040 /
		2119	#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000080 /
2	mjames	2120
		2121	/!< TIM1_REMAP configuration /
5	mjames	2122	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
		2123	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
		2124	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /!< 0x00000040 /
		2125	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
		2126	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
		2127	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /!< 0x000000C0 /
		2128	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
2	mjames	2129
5	mjames	2130	#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
		2131	#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000300 /
		2132	#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
		2133	#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000100 /
		2134	#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000200 /
2	mjames	2135
		2136	/!< TIM2_REMAP configuration /
5	mjames	2137	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
		2138	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
		2139	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /!< 0x00000100 /
		2140	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
		2141	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
		2142	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /!< 0x00000200 /
		2143	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
		2144	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
		2145	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /!< 0x00000300 /
		2146	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
2	mjames	2147
5	mjames	2148	#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
		2149	#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000C00 /
		2150	#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
		2151	#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000400 /
		2152	#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000800 /
2	mjames	2153
		2154	/!< TIM3_REMAP configuration /
5	mjames	2155	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
		2156	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
		2157	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /!< 0x00000800 /
		2158	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
		2159	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
		2160	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /!< 0x00000C00 /
		2161	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
2	mjames	2162
5	mjames	2163	#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
		2164	#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /!< 0x00001000 /
		2165	#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /!< TIM4_REMAP bit (TIM4 remapping) /
2	mjames	2166
		2167
5	mjames	2168	#define AFIO_MAPR_PD01_REMAP_Pos (15U)
		2169	#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /!< 0x00008000 /
		2170	#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
2	mjames	2171
		2172	/!< SWJ_CFG configuration /
5	mjames	2173	#define AFIO_MAPR_SWJ_CFG_Pos (24U)
		2174	#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x07000000 /
		2175	#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
		2176	#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x01000000 /
		2177	#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x02000000 /
		2178	#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x04000000 /
2	mjames	2179
5	mjames	2180	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
		2181	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
		2182	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /!< 0x01000000 /
		2183	#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
		2184	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
		2185	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /!< 0x02000000 /
		2186	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /!< JTAG-DP Disabled and SW-DP Enabled /
		2187	#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
		2188	#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /!< 0x04000000 /
		2189	#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /!< JTAG-DP Disabled and SW-DP Disabled /
2	mjames	2190
		2191
		2192	/*************** Bit definition for AFIO_EXTICR1 register ***************/
5	mjames	2193	#define AFIO_EXTICR1_EXTI0_Pos (0U)
		2194	#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /!< 0x0000000F /
		2195	#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /!< EXTI 0 configuration /
		2196	#define AFIO_EXTICR1_EXTI1_Pos (4U)
		2197	#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /!< 0x000000F0 /
		2198	#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /!< EXTI 1 configuration /
		2199	#define AFIO_EXTICR1_EXTI2_Pos (8U)
		2200	#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /!< 0x00000F00 /
		2201	#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /!< EXTI 2 configuration /
		2202	#define AFIO_EXTICR1_EXTI3_Pos (12U)
		2203	#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /!< 0x0000F000 /
		2204	#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /!< EXTI 3 configuration /
2	mjames	2205
		2206	/!< EXTI0 configuration /
		2207	#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!< PA[0] pin /
5	mjames	2208	#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
		2209	#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /!< 0x00000001 /
		2210	#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /!< PB[0] pin /
		2211	#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
		2212	#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /!< 0x00000002 /
		2213	#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /!< PC[0] pin /
		2214	#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
		2215	#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /!< 0x00000003 /
		2216	#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /!< PD[0] pin /
		2217	#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
		2218	#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /!< 0x00000004 /
		2219	#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /!< PE[0] pin /
		2220	#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
		2221	#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /!< 0x00000005 /
		2222	#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /!< PF[0] pin /
		2223	#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
		2224	#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /!< 0x00000006 /
		2225	#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /!< PG[0] pin /
2	mjames	2226
		2227	/!< EXTI1 configuration /
		2228	#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!< PA[1] pin /
5	mjames	2229	#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
		2230	#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /!< 0x00000010 /
		2231	#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /!< PB[1] pin /
		2232	#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
		2233	#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /!< 0x00000020 /
		2234	#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /!< PC[1] pin /
		2235	#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
		2236	#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /!< 0x00000030 /
		2237	#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /!< PD[1] pin /
		2238	#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
		2239	#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /!< 0x00000040 /
		2240	#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /!< PE[1] pin /
		2241	#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
		2242	#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /!< 0x00000050 /
		2243	#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /!< PF[1] pin /
		2244	#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
		2245	#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /!< 0x00000060 /
		2246	#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /!< PG[1] pin /
2	mjames	2247
		2248	/!< EXTI2 configuration /
		2249	#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!< PA[2] pin /
5	mjames	2250	#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
		2251	#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /!< 0x00000100 /
		2252	#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /!< PB[2] pin /
		2253	#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
		2254	#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /!< 0x00000200 /
		2255	#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /!< PC[2] pin /
		2256	#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
		2257	#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /!< 0x00000300 /
		2258	#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /!< PD[2] pin /
		2259	#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
		2260	#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /!< 0x00000400 /
		2261	#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /!< PE[2] pin /
		2262	#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
		2263	#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /!< 0x00000500 /
		2264	#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /!< PF[2] pin /
		2265	#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
		2266	#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /!< 0x00000600 /
		2267	#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /!< PG[2] pin /
2	mjames	2268
		2269	/!< EXTI3 configuration /
		2270	#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!< PA[3] pin /
5	mjames	2271	#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
		2272	#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /!< 0x00001000 /
		2273	#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /!< PB[3] pin /
		2274	#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
		2275	#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /!< 0x00002000 /
		2276	#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /!< PC[3] pin /
		2277	#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
		2278	#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /!< 0x00003000 /
		2279	#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /!< PD[3] pin /
		2280	#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
		2281	#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /!< 0x00004000 /
		2282	#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /!< PE[3] pin /
		2283	#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
		2284	#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /!< 0x00005000 /
		2285	#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /!< PF[3] pin /
		2286	#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
		2287	#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /!< 0x00006000 /
		2288	#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /!< PG[3] pin /
2	mjames	2289
		2290	/*************** Bit definition for AFIO_EXTICR2 register ***************/
5	mjames	2291	#define AFIO_EXTICR2_EXTI4_Pos (0U)
		2292	#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /!< 0x0000000F /
		2293	#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /!< EXTI 4 configuration /
		2294	#define AFIO_EXTICR2_EXTI5_Pos (4U)
		2295	#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /!< 0x000000F0 /
		2296	#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /!< EXTI 5 configuration /
		2297	#define AFIO_EXTICR2_EXTI6_Pos (8U)
		2298	#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /!< 0x00000F00 /
		2299	#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /!< EXTI 6 configuration /
		2300	#define AFIO_EXTICR2_EXTI7_Pos (12U)
		2301	#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /!< 0x0000F000 /
		2302	#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /!< EXTI 7 configuration /
2	mjames	2303
		2304	/!< EXTI4 configuration /
		2305	#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!< PA[4] pin /
5	mjames	2306	#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
		2307	#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /!< 0x00000001 /
		2308	#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /!< PB[4] pin /
		2309	#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
		2310	#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /!< 0x00000002 /
		2311	#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /!< PC[4] pin /
		2312	#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
		2313	#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /!< 0x00000003 /
		2314	#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /!< PD[4] pin /
		2315	#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
		2316	#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /!< 0x00000004 /
		2317	#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /!< PE[4] pin /
		2318	#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
		2319	#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /!< 0x00000005 /
		2320	#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /!< PF[4] pin /
		2321	#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
		2322	#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /!< 0x00000006 /
		2323	#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /!< PG[4] pin /
2	mjames	2324
		2325	/* EXTI5 configuration */
		2326	#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!< PA[5] pin /
5	mjames	2327	#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
		2328	#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /!< 0x00000010 /
		2329	#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /!< PB[5] pin /
		2330	#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
		2331	#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /!< 0x00000020 /
		2332	#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /!< PC[5] pin /
		2333	#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
		2334	#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /!< 0x00000030 /
		2335	#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /!< PD[5] pin /
		2336	#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
		2337	#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /!< 0x00000040 /
		2338	#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /!< PE[5] pin /
		2339	#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
		2340	#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /!< 0x00000050 /
		2341	#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /!< PF[5] pin /
		2342	#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
		2343	#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /!< 0x00000060 /
		2344	#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /!< PG[5] pin /
2	mjames	2345
		2346	/!< EXTI6 configuration /
		2347	#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!< PA[6] pin /
5	mjames	2348	#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
		2349	#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /!< 0x00000100 /
		2350	#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /!< PB[6] pin /
		2351	#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
		2352	#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /!< 0x00000200 /
		2353	#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /!< PC[6] pin /
		2354	#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
		2355	#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /!< 0x00000300 /
		2356	#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /!< PD[6] pin /
		2357	#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
		2358	#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /!< 0x00000400 /
		2359	#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /!< PE[6] pin /
		2360	#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
		2361	#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /!< 0x00000500 /
		2362	#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /!< PF[6] pin /
		2363	#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
		2364	#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /!< 0x00000600 /
		2365	#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /!< PG[6] pin /
2	mjames	2366
		2367	/!< EXTI7 configuration /
		2368	#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!< PA[7] pin /
5	mjames	2369	#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
		2370	#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /!< 0x00001000 /
		2371	#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /!< PB[7] pin /
		2372	#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
		2373	#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /!< 0x00002000 /
		2374	#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /!< PC[7] pin /
		2375	#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
		2376	#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /!< 0x00003000 /
		2377	#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /!< PD[7] pin /
		2378	#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
		2379	#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /!< 0x00004000 /
		2380	#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /!< PE[7] pin /
		2381	#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
		2382	#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /!< 0x00005000 /
		2383	#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /!< PF[7] pin /
		2384	#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
		2385	#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /!< 0x00006000 /
		2386	#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /!< PG[7] pin /
2	mjames	2387
		2388	/*************** Bit definition for AFIO_EXTICR3 register ***************/
5	mjames	2389	#define AFIO_EXTICR3_EXTI8_Pos (0U)
		2390	#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /!< 0x0000000F /
		2391	#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /!< EXTI 8 configuration /
		2392	#define AFIO_EXTICR3_EXTI9_Pos (4U)
		2393	#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /!< 0x000000F0 /
		2394	#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /!< EXTI 9 configuration /
		2395	#define AFIO_EXTICR3_EXTI10_Pos (8U)
		2396	#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /!< 0x00000F00 /
		2397	#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /!< EXTI 10 configuration /
		2398	#define AFIO_EXTICR3_EXTI11_Pos (12U)
		2399	#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /!< 0x0000F000 /
		2400	#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /!< EXTI 11 configuration /
2	mjames	2401
		2402	/!< EXTI8 configuration /
		2403	#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!< PA[8] pin /
5	mjames	2404	#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
		2405	#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /!< 0x00000001 /
		2406	#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /!< PB[8] pin /
		2407	#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
		2408	#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /!< 0x00000002 /
		2409	#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /!< PC[8] pin /
		2410	#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
		2411	#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /!< 0x00000003 /
		2412	#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /!< PD[8] pin /
		2413	#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
		2414	#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /!< 0x00000004 /
		2415	#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /!< PE[8] pin /
		2416	#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
		2417	#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /!< 0x00000005 /
		2418	#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /!< PF[8] pin /
		2419	#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
		2420	#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /!< 0x00000006 /
		2421	#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /!< PG[8] pin /
2	mjames	2422
		2423	/!< EXTI9 configuration /
		2424	#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!< PA[9] pin /
5	mjames	2425	#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
		2426	#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /!< 0x00000010 /
		2427	#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /!< PB[9] pin /
		2428	#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
		2429	#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /!< 0x00000020 /
		2430	#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /!< PC[9] pin /
		2431	#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
		2432	#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /!< 0x00000030 /
		2433	#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /!< PD[9] pin /
		2434	#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
		2435	#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /!< 0x00000040 /
		2436	#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /!< PE[9] pin /
		2437	#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
		2438	#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /!< 0x00000050 /
		2439	#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /!< PF[9] pin /
		2440	#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
		2441	#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /!< 0x00000060 /
		2442	#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /!< PG[9] pin /
2	mjames	2443
		2444	/!< EXTI10 configuration /
		2445	#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!< PA[10] pin /
5	mjames	2446	#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
		2447	#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /!< 0x00000100 /
		2448	#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /!< PB[10] pin /
		2449	#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
		2450	#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /!< 0x00000200 /
		2451	#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /!< PC[10] pin /
		2452	#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
		2453	#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /!< 0x00000300 /
		2454	#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /!< PD[10] pin /
		2455	#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
		2456	#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /!< 0x00000400 /
		2457	#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /!< PE[10] pin /
		2458	#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
		2459	#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /!< 0x00000500 /
		2460	#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /!< PF[10] pin /
		2461	#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
		2462	#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /!< 0x00000600 /
		2463	#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /!< PG[10] pin /
2	mjames	2464
		2465	/!< EXTI11 configuration /
		2466	#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!< PA[11] pin /
5	mjames	2467	#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
		2468	#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /!< 0x00001000 /
		2469	#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /!< PB[11] pin /
		2470	#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
		2471	#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /!< 0x00002000 /
		2472	#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /!< PC[11] pin /
		2473	#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
		2474	#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /!< 0x00003000 /
		2475	#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /!< PD[11] pin /
		2476	#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
		2477	#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /!< 0x00004000 /
		2478	#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /!< PE[11] pin /
		2479	#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
		2480	#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /!< 0x00005000 /
		2481	#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /!< PF[11] pin /
		2482	#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
		2483	#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /!< 0x00006000 /
		2484	#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /!< PG[11] pin /
2	mjames	2485
		2486	/*************** Bit definition for AFIO_EXTICR4 register ***************/
5	mjames	2487	#define AFIO_EXTICR4_EXTI12_Pos (0U)
		2488	#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /!< 0x0000000F /
		2489	#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /!< EXTI 12 configuration /
		2490	#define AFIO_EXTICR4_EXTI13_Pos (4U)
		2491	#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /!< 0x000000F0 /
		2492	#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /!< EXTI 13 configuration /
		2493	#define AFIO_EXTICR4_EXTI14_Pos (8U)
		2494	#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /!< 0x00000F00 /
		2495	#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /!< EXTI 14 configuration /
		2496	#define AFIO_EXTICR4_EXTI15_Pos (12U)
		2497	#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /!< 0x0000F000 /
		2498	#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /!< EXTI 15 configuration /
2	mjames	2499
		2500	/* EXTI12 configuration */
		2501	#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!< PA[12] pin /
5	mjames	2502	#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
		2503	#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /!< 0x00000001 /
		2504	#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /!< PB[12] pin /
		2505	#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
		2506	#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /!< 0x00000002 /
		2507	#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /!< PC[12] pin /
		2508	#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
		2509	#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /!< 0x00000003 /
		2510	#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /!< PD[12] pin /
		2511	#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
		2512	#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /!< 0x00000004 /
		2513	#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /!< PE[12] pin /
		2514	#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
		2515	#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /!< 0x00000005 /
		2516	#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /!< PF[12] pin /
		2517	#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
		2518	#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /!< 0x00000006 /
		2519	#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /!< PG[12] pin /
2	mjames	2520
		2521	/* EXTI13 configuration */
		2522	#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!< PA[13] pin /
5	mjames	2523	#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
		2524	#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /!< 0x00000010 /
		2525	#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /!< PB[13] pin /
		2526	#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
		2527	#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /!< 0x00000020 /
		2528	#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /!< PC[13] pin /
		2529	#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
		2530	#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /!< 0x00000030 /
		2531	#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /!< PD[13] pin /
		2532	#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
		2533	#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /!< 0x00000040 /
		2534	#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /!< PE[13] pin /
		2535	#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
		2536	#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /!< 0x00000050 /
		2537	#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /!< PF[13] pin /
		2538	#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
		2539	#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /!< 0x00000060 /
		2540	#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /!< PG[13] pin /
2	mjames	2541
		2542	/!< EXTI14 configuration /
		2543	#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!< PA[14] pin /
5	mjames	2544	#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
		2545	#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /!< 0x00000100 /
		2546	#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /!< PB[14] pin /
		2547	#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
		2548	#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /!< 0x00000200 /
		2549	#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /!< PC[14] pin /
		2550	#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
		2551	#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /!< 0x00000300 /
		2552	#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /!< PD[14] pin /
		2553	#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
		2554	#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /!< 0x00000400 /
		2555	#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /!< PE[14] pin /
		2556	#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
		2557	#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /!< 0x00000500 /
		2558	#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /!< PF[14] pin /
		2559	#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
		2560	#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /!< 0x00000600 /
		2561	#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /!< PG[14] pin /
2	mjames	2562
		2563	/!< EXTI15 configuration /
		2564	#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!< PA[15] pin /
5	mjames	2565	#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
		2566	#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /!< 0x00001000 /
		2567	#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /!< PB[15] pin /
		2568	#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
		2569	#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /!< 0x00002000 /
		2570	#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /!< PC[15] pin /
		2571	#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
		2572	#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /!< 0x00003000 /
		2573	#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /!< PD[15] pin /
		2574	#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
		2575	#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /!< 0x00004000 /
		2576	#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /!< PE[15] pin /
		2577	#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
		2578	#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /!< 0x00005000 /
		2579	#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /!< PF[15] pin /
		2580	#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
		2581	#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /!< 0x00006000 /
		2582	#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /!< PG[15] pin /
2	mjames	2583
		2584	/**************** Bit definition for AFIO_MAPR2 register ****************/
5	mjames	2585	#define AFIO_MAPR2_TIM15_REMAP_Pos (0U)
		2586	#define AFIO_MAPR2_TIM15_REMAP_Msk (0x1U << AFIO_MAPR2_TIM15_REMAP_Pos) /!< 0x00000001 /
		2587	#define AFIO_MAPR2_TIM15_REMAP AFIO_MAPR2_TIM15_REMAP_Msk /!< TIM15 remapping /
		2588	#define AFIO_MAPR2_TIM16_REMAP_Pos (1U)
		2589	#define AFIO_MAPR2_TIM16_REMAP_Msk (0x1U << AFIO_MAPR2_TIM16_REMAP_Pos) /!< 0x00000002 /
		2590	#define AFIO_MAPR2_TIM16_REMAP AFIO_MAPR2_TIM16_REMAP_Msk /!< TIM16 remapping /
		2591	#define AFIO_MAPR2_TIM17_REMAP_Pos (2U)
		2592	#define AFIO_MAPR2_TIM17_REMAP_Msk (0x1U << AFIO_MAPR2_TIM17_REMAP_Pos) /!< 0x00000004 /
		2593	#define AFIO_MAPR2_TIM17_REMAP AFIO_MAPR2_TIM17_REMAP_Msk /!< TIM17 remapping /
		2594	#define AFIO_MAPR2_CEC_REMAP_Pos (3U)
		2595	#define AFIO_MAPR2_CEC_REMAP_Msk (0x1U << AFIO_MAPR2_CEC_REMAP_Pos) /!< 0x00000008 /
		2596	#define AFIO_MAPR2_CEC_REMAP AFIO_MAPR2_CEC_REMAP_Msk /!< CEC remapping /
		2597	#define AFIO_MAPR2_TIM1_DMA_REMAP_Pos (4U)
		2598	#define AFIO_MAPR2_TIM1_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM1_DMA_REMAP_Pos) /!< 0x00000010 /
		2599	#define AFIO_MAPR2_TIM1_DMA_REMAP AFIO_MAPR2_TIM1_DMA_REMAP_Msk /!< TIM1_DMA remapping /
2	mjames	2600
5	mjames	2601	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos (11U)
		2602	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos) /!< 0x00000800 /
		2603	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk /!< TIM6/TIM7 and DAC DMA remapping /
2	mjames	2604
		2605
		2606	/******************************************************************************/
		2607	/* */
		2608	/* SystemTick */
		2609	/* */
		2610	/******************************************************************************/
		2611
		2612	/*************** Bit definition for SysTick_CTRL register ***************/
5	mjames	2613	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
		2614	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
		2615	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
		2616	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
2	mjames	2617
		2618	/*************** Bit definition for SysTick_LOAD register ***************/
5	mjames	2619	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
2	mjames	2620
		2621	/*************** Bit definition for SysTick_VAL register ****************/
5	mjames	2622	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
2	mjames	2623
		2624	/*************** Bit definition for SysTick_CALIB register **************/
5	mjames	2625	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
		2626	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
		2627	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
2	mjames	2628
		2629	/******************************************************************************/
		2630	/* */
		2631	/* Nested Vectored Interrupt Controller */
		2632	/* */
		2633	/******************************************************************************/
		2634
		2635	/**************** Bit definition for NVIC_ISER register *****************/
5	mjames	2636	#define NVIC_ISER_SETENA_Pos (0U)
		2637	#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /!< 0xFFFFFFFF /
		2638	#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /!< Interrupt set enable bits /
		2639	#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /!< 0x00000001 /
		2640	#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /!< 0x00000002 /
		2641	#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /!< 0x00000004 /
		2642	#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /!< 0x00000008 /
		2643	#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /!< 0x00000010 /
		2644	#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /!< 0x00000020 /
		2645	#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /!< 0x00000040 /
		2646	#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /!< 0x00000080 /
		2647	#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /!< 0x00000100 /
		2648	#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /!< 0x00000200 /
		2649	#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /!< 0x00000400 /
		2650	#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /!< 0x00000800 /
		2651	#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /!< 0x00001000 /
		2652	#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /!< 0x00002000 /
		2653	#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /!< 0x00004000 /
		2654	#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /!< 0x00008000 /
		2655	#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /!< 0x00010000 /
		2656	#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /!< 0x00020000 /
		2657	#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /!< 0x00040000 /
		2658	#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /!< 0x00080000 /
		2659	#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /!< 0x00100000 /
		2660	#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /!< 0x00200000 /
		2661	#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /!< 0x00400000 /
		2662	#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /!< 0x00800000 /
		2663	#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /!< 0x01000000 /
		2664	#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /!< 0x02000000 /
		2665	#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /!< 0x04000000 /
		2666	#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /!< 0x08000000 /
		2667	#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /!< 0x10000000 /
		2668	#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /!< 0x20000000 /
		2669	#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /!< 0x40000000 /
		2670	#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /!< 0x80000000 /
2	mjames	2671
		2672	/**************** Bit definition for NVIC_ICER register *****************/
5	mjames	2673	#define NVIC_ICER_CLRENA_Pos (0U)
		2674	#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /!< 0xFFFFFFFF /
		2675	#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /!< Interrupt clear-enable bits /
		2676	#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /!< 0x00000001 /
		2677	#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /!< 0x00000002 /
		2678	#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /!< 0x00000004 /
		2679	#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /!< 0x00000008 /
		2680	#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /!< 0x00000010 /
		2681	#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /!< 0x00000020 /
		2682	#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /!< 0x00000040 /
		2683	#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /!< 0x00000080 /
		2684	#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /!< 0x00000100 /
		2685	#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /!< 0x00000200 /
		2686	#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /!< 0x00000400 /
		2687	#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /!< 0x00000800 /
		2688	#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /!< 0x00001000 /
		2689	#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /!< 0x00002000 /
		2690	#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /!< 0x00004000 /
		2691	#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /!< 0x00008000 /
		2692	#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /!< 0x00010000 /
		2693	#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /!< 0x00020000 /
		2694	#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /!< 0x00040000 /
		2695	#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /!< 0x00080000 /
		2696	#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /!< 0x00100000 /
		2697	#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /!< 0x00200000 /
		2698	#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /!< 0x00400000 /
		2699	#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /!< 0x00800000 /
		2700	#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /!< 0x01000000 /
		2701	#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /!< 0x02000000 /
		2702	#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /!< 0x04000000 /
		2703	#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /!< 0x08000000 /
		2704	#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /!< 0x10000000 /
		2705	#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /!< 0x20000000 /
		2706	#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /!< 0x40000000 /
		2707	#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /!< 0x80000000 /
2	mjames	2708
		2709	/**************** Bit definition for NVIC_ISPR register *****************/
5	mjames	2710	#define NVIC_ISPR_SETPEND_Pos (0U)
		2711	#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /!< 0xFFFFFFFF /
		2712	#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /!< Interrupt set-pending bits /
		2713	#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000001 /
		2714	#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000002 /
		2715	#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000004 /
		2716	#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000008 /
		2717	#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000010 /
		2718	#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000020 /
		2719	#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000040 /
		2720	#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000080 /
		2721	#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000100 /
		2722	#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000200 /
		2723	#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000400 /
		2724	#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000800 /
		2725	#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00001000 /
		2726	#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00002000 /
		2727	#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00004000 /
		2728	#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00008000 /
		2729	#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00010000 /
		2730	#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00020000 /
		2731	#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00040000 /
		2732	#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00080000 /
		2733	#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00100000 /
		2734	#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00200000 /
		2735	#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00400000 /
		2736	#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00800000 /
		2737	#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x01000000 /
		2738	#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x02000000 /
		2739	#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x04000000 /
		2740	#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x08000000 /
		2741	#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x10000000 /
		2742	#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x20000000 /
		2743	#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x40000000 /
		2744	#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x80000000 /
2	mjames	2745
		2746	/**************** Bit definition for NVIC_ICPR register *****************/
5	mjames	2747	#define NVIC_ICPR_CLRPEND_Pos (0U)
		2748	#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /!< 0xFFFFFFFF /
		2749	#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /!< Interrupt clear-pending bits /
		2750	#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000001 /
		2751	#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000002 /
		2752	#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000004 /
		2753	#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000008 /
		2754	#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000010 /
		2755	#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000020 /
		2756	#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000040 /
		2757	#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000080 /
		2758	#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000100 /
		2759	#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000200 /
		2760	#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000400 /
		2761	#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000800 /
		2762	#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00001000 /
		2763	#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00002000 /
		2764	#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00004000 /
		2765	#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00008000 /
		2766	#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00010000 /
		2767	#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00020000 /
		2768	#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00040000 /
		2769	#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00080000 /
		2770	#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00100000 /
		2771	#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00200000 /
		2772	#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00400000 /
		2773	#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00800000 /
		2774	#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x01000000 /
		2775	#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x02000000 /
		2776	#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x04000000 /
		2777	#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x08000000 /
		2778	#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x10000000 /
		2779	#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x20000000 /
		2780	#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x40000000 /
		2781	#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x80000000 /
2	mjames	2782
		2783	/**************** Bit definition for NVIC_IABR register *****************/
5	mjames	2784	#define NVIC_IABR_ACTIVE_Pos (0U)
		2785	#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /!< 0xFFFFFFFF /
		2786	#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /!< Interrupt active flags /
		2787	#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000001 /
		2788	#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000002 /
		2789	#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000004 /
		2790	#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000008 /
		2791	#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000010 /
		2792	#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000020 /
		2793	#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000040 /
		2794	#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000080 /
		2795	#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000100 /
		2796	#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000200 /
		2797	#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000400 /
		2798	#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000800 /
		2799	#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00001000 /
		2800	#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00002000 /
		2801	#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00004000 /
		2802	#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00008000 /
		2803	#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00010000 /
		2804	#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00020000 /
		2805	#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00040000 /
		2806	#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00080000 /
		2807	#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00100000 /
		2808	#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00200000 /
		2809	#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00400000 /
		2810	#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00800000 /
		2811	#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x01000000 /
		2812	#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x02000000 /
		2813	#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x04000000 /
		2814	#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x08000000 /
		2815	#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x10000000 /
		2816	#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x20000000 /
		2817	#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x40000000 /
		2818	#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x80000000 /
2	mjames	2819
		2820	/**************** Bit definition for NVIC_PRI0 register *****************/
5	mjames	2821	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
		2822	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
		2823	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
		2824	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
2	mjames	2825
		2826	/**************** Bit definition for NVIC_PRI1 register *****************/
5	mjames	2827	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
		2828	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
		2829	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
		2830	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
2	mjames	2831
		2832	/**************** Bit definition for NVIC_PRI2 register *****************/
5	mjames	2833	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
		2834	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
		2835	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
		2836	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
2	mjames	2837
		2838	/**************** Bit definition for NVIC_PRI3 register *****************/
5	mjames	2839	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
		2840	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
		2841	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
		2842	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
2	mjames	2843
		2844	/**************** Bit definition for NVIC_PRI4 register *****************/
5	mjames	2845	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
		2846	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
		2847	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
		2848	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
2	mjames	2849
		2850	/**************** Bit definition for NVIC_PRI5 register *****************/
5	mjames	2851	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
		2852	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
		2853	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
		2854	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
2	mjames	2855
		2856	/**************** Bit definition for NVIC_PRI6 register *****************/
5	mjames	2857	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
		2858	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
		2859	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
		2860	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
2	mjames	2861
		2862	/**************** Bit definition for NVIC_PRI7 register *****************/
5	mjames	2863	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
		2864	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
		2865	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
		2866	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
2	mjames	2867
		2868	/**************** Bit definition for SCB_CPUID register *****************/
5	mjames	2869	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
		2870	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
		2871	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
		2872	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
		2873	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
2	mjames	2874
		2875	/***************** Bit definition for SCB_ICSR register *****************/
5	mjames	2876	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
		2877	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
		2878	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
		2879	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
		2880	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
		2881	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
		2882	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
		2883	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
		2884	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
		2885	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
2	mjames	2886
		2887	/***************** Bit definition for SCB_VTOR register *****************/
5	mjames	2888	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
		2889	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
2	mjames	2890
		2891	/!<************** Bit definition for SCB_AIRCR register *****************/
5	mjames	2892	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
		2893	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
		2894	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
2	mjames	2895
5	mjames	2896	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
		2897	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
		2898	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
		2899	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
2	mjames	2900
		2901	/* prority group configuration */
5	mjames	2902	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
		2903	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
		2904	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
		2905	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
		2906	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
		2907	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
		2908	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
		2909	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
2	mjames	2910
5	mjames	2911	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
		2912	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
2	mjames	2913
		2914	/***************** Bit definition for SCB_SCR register ******************/
5	mjames	2915	#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /!< Sleep on exit bit /
		2916	#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /!< Sleep deep bit /
		2917	#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /!< Wake up from WFE /
2	mjames	2918
		2919	/****************** Bit definition for SCB_CCR register *****************/
5	mjames	2920	#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
		2921	#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
		2922	#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /!< Trap for unaligned access /
		2923	#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /!< Trap on Divide by 0 /
		2924	#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /!< Handlers running at priority -1 and -2 /
		2925	#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
2	mjames	2926
		2927	/***************** Bit definition for SCB_SHPR register ******************/
5	mjames	2928	#define SCB_SHPR_PRI_N_Pos (0U)
		2929	#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /!< 0x000000FF /
		2930	#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
		2931	#define SCB_SHPR_PRI_N1_Pos (8U)
		2932	#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /!< 0x0000FF00 /
		2933	#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
		2934	#define SCB_SHPR_PRI_N2_Pos (16U)
		2935	#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /!< 0x00FF0000 /
		2936	#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
		2937	#define SCB_SHPR_PRI_N3_Pos (24U)
		2938	#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /!< 0xFF000000 /
		2939	#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
2	mjames	2940
		2941	/**************** Bit definition for SCB_SHCSR register *****************/
5	mjames	2942	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
		2943	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
		2944	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
		2945	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
		2946	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
		2947	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
		2948	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
		2949	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
		2950	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
		2951	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
		2952	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
		2953	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
		2954	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
		2955	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
2	mjames	2956
		2957	/***************** Bit definition for SCB_CFSR register *****************/
		2958	/!< MFSR /
5	mjames	2959	#define SCB_CFSR_IACCVIOL_Pos (0U)
		2960	#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /!< 0x00000001 /
		2961	#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /!< Instruction access violation /
		2962	#define SCB_CFSR_DACCVIOL_Pos (1U)
		2963	#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /!< 0x00000002 /
		2964	#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /!< Data access violation /
		2965	#define SCB_CFSR_MUNSTKERR_Pos (3U)
		2966	#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /!< 0x00000008 /
		2967	#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /!< Unstacking error /
		2968	#define SCB_CFSR_MSTKERR_Pos (4U)
		2969	#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /!< 0x00000010 /
		2970	#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /!< Stacking error /
		2971	#define SCB_CFSR_MMARVALID_Pos (7U)
		2972	#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /!< 0x00000080 /
		2973	#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /!< Memory Manage Address Register address valid flag /
2	mjames	2974	/!< BFSR /
5	mjames	2975	#define SCB_CFSR_IBUSERR_Pos (8U)
		2976	#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /!< 0x00000100 /
		2977	#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /!< Instruction bus error flag /
		2978	#define SCB_CFSR_PRECISERR_Pos (9U)
		2979	#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /!< 0x00000200 /
		2980	#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /!< Precise data bus error /
		2981	#define SCB_CFSR_IMPRECISERR_Pos (10U)
		2982	#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /!< 0x00000400 /
		2983	#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /!< Imprecise data bus error /
		2984	#define SCB_CFSR_UNSTKERR_Pos (11U)
		2985	#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /!< 0x00000800 /
		2986	#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /!< Unstacking error /
		2987	#define SCB_CFSR_STKERR_Pos (12U)
		2988	#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /!< 0x00001000 /
		2989	#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /!< Stacking error /
		2990	#define SCB_CFSR_BFARVALID_Pos (15U)
		2991	#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /!< 0x00008000 /
		2992	#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /!< Bus Fault Address Register address valid flag /
2	mjames	2993	/!< UFSR /
5	mjames	2994	#define SCB_CFSR_UNDEFINSTR_Pos (16U)
		2995	#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /!< 0x00010000 /
		2996	#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /!< The processor attempt to execute an undefined instruction /
		2997	#define SCB_CFSR_INVSTATE_Pos (17U)
		2998	#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /!< 0x00020000 /
		2999	#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /!< Invalid combination of EPSR and instruction /
		3000	#define SCB_CFSR_INVPC_Pos (18U)
		3001	#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /!< 0x00040000 /
		3002	#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /!< Attempt to load EXC_RETURN into pc illegally /
		3003	#define SCB_CFSR_NOCP_Pos (19U)
		3004	#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /!< 0x00080000 /
		3005	#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /!< Attempt to use a coprocessor instruction /
		3006	#define SCB_CFSR_UNALIGNED_Pos (24U)
		3007	#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /!< 0x01000000 /
		3008	#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /!< Fault occurs when there is an attempt to make an unaligned memory access /
		3009	#define SCB_CFSR_DIVBYZERO_Pos (25U)
		3010	#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /!< 0x02000000 /
		3011	#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
2	mjames	3012
		3013	/***************** Bit definition for SCB_HFSR register *****************/
5	mjames	3014	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
		3015	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
		3016	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
2	mjames	3017
		3018	/***************** Bit definition for SCB_DFSR register *****************/
5	mjames	3019	#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /!< Halt request flag /
		3020	#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /!< BKPT flag /
		3021	#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /!< Data Watchpoint and Trace (DWT) flag /
		3022	#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /!< Vector catch flag /
		3023	#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /!< External debug request flag /
2	mjames	3024
		3025	/***************** Bit definition for SCB_MMFAR register ****************/
5	mjames	3026	#define SCB_MMFAR_ADDRESS_Pos (0U)
		3027	#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /!< 0xFFFFFFFF /
		3028	#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /!< Mem Manage fault address field /
2	mjames	3029
		3030	/***************** Bit definition for SCB_BFAR register *****************/
5	mjames	3031	#define SCB_BFAR_ADDRESS_Pos (0U)
		3032	#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /!< 0xFFFFFFFF /
		3033	#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /!< Bus fault address field /
2	mjames	3034
		3035	/***************** Bit definition for SCB_afsr register *****************/
5	mjames	3036	#define SCB_AFSR_IMPDEF_Pos (0U)
		3037	#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /!< 0xFFFFFFFF /
		3038	#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /!< Implementation defined /
2	mjames	3039
		3040	/******************************************************************************/
		3041	/* */
		3042	/* External Interrupt/Event Controller */
		3043	/* */
		3044	/******************************************************************************/
		3045
		3046	/***************** Bit definition for EXTI_IMR register *****************/
5	mjames	3047	#define EXTI_IMR_MR0_Pos (0U)
		3048	#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /!< 0x00000001 /
		3049	#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /!< Interrupt Mask on line 0 /
		3050	#define EXTI_IMR_MR1_Pos (1U)
		3051	#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /!< 0x00000002 /
		3052	#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /!< Interrupt Mask on line 1 /
		3053	#define EXTI_IMR_MR2_Pos (2U)
		3054	#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /!< 0x00000004 /
		3055	#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /!< Interrupt Mask on line 2 /
		3056	#define EXTI_IMR_MR3_Pos (3U)
		3057	#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /!< 0x00000008 /
		3058	#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /!< Interrupt Mask on line 3 /
		3059	#define EXTI_IMR_MR4_Pos (4U)
		3060	#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /!< 0x00000010 /
		3061	#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /!< Interrupt Mask on line 4 /
		3062	#define EXTI_IMR_MR5_Pos (5U)
		3063	#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /!< 0x00000020 /
		3064	#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /!< Interrupt Mask on line 5 /
		3065	#define EXTI_IMR_MR6_Pos (6U)
		3066	#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /!< 0x00000040 /
		3067	#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /!< Interrupt Mask on line 6 /
		3068	#define EXTI_IMR_MR7_Pos (7U)
		3069	#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /!< 0x00000080 /
		3070	#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /!< Interrupt Mask on line 7 /
		3071	#define EXTI_IMR_MR8_Pos (8U)
		3072	#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /!< 0x00000100 /
		3073	#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /!< Interrupt Mask on line 8 /
		3074	#define EXTI_IMR_MR9_Pos (9U)
		3075	#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /!< 0x00000200 /
		3076	#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /!< Interrupt Mask on line 9 /
		3077	#define EXTI_IMR_MR10_Pos (10U)
		3078	#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /!< 0x00000400 /
		3079	#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /!< Interrupt Mask on line 10 /
		3080	#define EXTI_IMR_MR11_Pos (11U)
		3081	#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /!< 0x00000800 /
		3082	#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /!< Interrupt Mask on line 11 /
		3083	#define EXTI_IMR_MR12_Pos (12U)
		3084	#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /!< 0x00001000 /
		3085	#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /!< Interrupt Mask on line 12 /
		3086	#define EXTI_IMR_MR13_Pos (13U)
		3087	#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /!< 0x00002000 /
		3088	#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /!< Interrupt Mask on line 13 /
		3089	#define EXTI_IMR_MR14_Pos (14U)
		3090	#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /!< 0x00004000 /
		3091	#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /!< Interrupt Mask on line 14 /
		3092	#define EXTI_IMR_MR15_Pos (15U)
		3093	#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /!< 0x00008000 /
		3094	#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /!< Interrupt Mask on line 15 /
		3095	#define EXTI_IMR_MR16_Pos (16U)
		3096	#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /!< 0x00010000 /
		3097	#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /!< Interrupt Mask on line 16 /
		3098	#define EXTI_IMR_MR17_Pos (17U)
		3099	#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /!< 0x00020000 /
		3100	#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /!< Interrupt Mask on line 17 /
		3101	#define EXTI_IMR_MR18_Pos (18U)
		3102	#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /!< 0x00040000 /
		3103	#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /!< Interrupt Mask on line 18 /
		3104	#define EXTI_IMR_MR19_Pos (19U)
		3105	#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /!< 0x00080000 /
		3106	#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /!< Interrupt Mask on line 19 /
2	mjames	3107
5	mjames	3108	/* References Defines */
		3109	#define EXTI_IMR_IM0 EXTI_IMR_MR0
		3110	#define EXTI_IMR_IM1 EXTI_IMR_MR1
		3111	#define EXTI_IMR_IM2 EXTI_IMR_MR2
		3112	#define EXTI_IMR_IM3 EXTI_IMR_MR3
		3113	#define EXTI_IMR_IM4 EXTI_IMR_MR4
		3114	#define EXTI_IMR_IM5 EXTI_IMR_MR5
		3115	#define EXTI_IMR_IM6 EXTI_IMR_MR6
		3116	#define EXTI_IMR_IM7 EXTI_IMR_MR7
		3117	#define EXTI_IMR_IM8 EXTI_IMR_MR8
		3118	#define EXTI_IMR_IM9 EXTI_IMR_MR9
		3119	#define EXTI_IMR_IM10 EXTI_IMR_MR10
		3120	#define EXTI_IMR_IM11 EXTI_IMR_MR11
		3121	#define EXTI_IMR_IM12 EXTI_IMR_MR12
		3122	#define EXTI_IMR_IM13 EXTI_IMR_MR13
		3123	#define EXTI_IMR_IM14 EXTI_IMR_MR14
		3124	#define EXTI_IMR_IM15 EXTI_IMR_MR15
		3125	#define EXTI_IMR_IM16 EXTI_IMR_MR16
		3126	#define EXTI_IMR_IM17 EXTI_IMR_MR17
		3127	#define EXTI_IMR_IM18 EXTI_IMR_MR18
		3128	#define EXTI_IMR_IM19 EXTI_IMR_MR19
		3129
2	mjames	3130	/***************** Bit definition for EXTI_EMR register *****************/
5	mjames	3131	#define EXTI_EMR_MR0_Pos (0U)
		3132	#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /!< 0x00000001 /
		3133	#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /!< Event Mask on line 0 /
		3134	#define EXTI_EMR_MR1_Pos (1U)
		3135	#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /!< 0x00000002 /
		3136	#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /!< Event Mask on line 1 /
		3137	#define EXTI_EMR_MR2_Pos (2U)
		3138	#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /!< 0x00000004 /
		3139	#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /!< Event Mask on line 2 /
		3140	#define EXTI_EMR_MR3_Pos (3U)
		3141	#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /!< 0x00000008 /
		3142	#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /!< Event Mask on line 3 /
		3143	#define EXTI_EMR_MR4_Pos (4U)
		3144	#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /!< 0x00000010 /
		3145	#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /!< Event Mask on line 4 /
		3146	#define EXTI_EMR_MR5_Pos (5U)
		3147	#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /!< 0x00000020 /
		3148	#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /!< Event Mask on line 5 /
		3149	#define EXTI_EMR_MR6_Pos (6U)
		3150	#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /!< 0x00000040 /
		3151	#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /!< Event Mask on line 6 /
		3152	#define EXTI_EMR_MR7_Pos (7U)
		3153	#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /!< 0x00000080 /
		3154	#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /!< Event Mask on line 7 /
		3155	#define EXTI_EMR_MR8_Pos (8U)
		3156	#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /!< 0x00000100 /
		3157	#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /!< Event Mask on line 8 /
		3158	#define EXTI_EMR_MR9_Pos (9U)
		3159	#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /!< 0x00000200 /
		3160	#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /!< Event Mask on line 9 /
		3161	#define EXTI_EMR_MR10_Pos (10U)
		3162	#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /!< 0x00000400 /
		3163	#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /!< Event Mask on line 10 /
		3164	#define EXTI_EMR_MR11_Pos (11U)
		3165	#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /!< 0x00000800 /
		3166	#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /!< Event Mask on line 11 /
		3167	#define EXTI_EMR_MR12_Pos (12U)
		3168	#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /!< 0x00001000 /
		3169	#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /!< Event Mask on line 12 /
		3170	#define EXTI_EMR_MR13_Pos (13U)
		3171	#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /!< 0x00002000 /
		3172	#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /!< Event Mask on line 13 /
		3173	#define EXTI_EMR_MR14_Pos (14U)
		3174	#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /!< 0x00004000 /
		3175	#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /!< Event Mask on line 14 /
		3176	#define EXTI_EMR_MR15_Pos (15U)
		3177	#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /!< 0x00008000 /
		3178	#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /!< Event Mask on line 15 /
		3179	#define EXTI_EMR_MR16_Pos (16U)
		3180	#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /!< 0x00010000 /
		3181	#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /!< Event Mask on line 16 /
		3182	#define EXTI_EMR_MR17_Pos (17U)
		3183	#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /!< 0x00020000 /
		3184	#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /!< Event Mask on line 17 /
		3185	#define EXTI_EMR_MR18_Pos (18U)
		3186	#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /!< 0x00040000 /
		3187	#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /!< Event Mask on line 18 /
		3188	#define EXTI_EMR_MR19_Pos (19U)
		3189	#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /!< 0x00080000 /
		3190	#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /!< Event Mask on line 19 /
2	mjames	3191
5	mjames	3192	/* References Defines */
		3193	#define EXTI_EMR_EM0 EXTI_EMR_MR0
		3194	#define EXTI_EMR_EM1 EXTI_EMR_MR1
		3195	#define EXTI_EMR_EM2 EXTI_EMR_MR2
		3196	#define EXTI_EMR_EM3 EXTI_EMR_MR3
		3197	#define EXTI_EMR_EM4 EXTI_EMR_MR4
		3198	#define EXTI_EMR_EM5 EXTI_EMR_MR5
		3199	#define EXTI_EMR_EM6 EXTI_EMR_MR6
		3200	#define EXTI_EMR_EM7 EXTI_EMR_MR7
		3201	#define EXTI_EMR_EM8 EXTI_EMR_MR8
		3202	#define EXTI_EMR_EM9 EXTI_EMR_MR9
		3203	#define EXTI_EMR_EM10 EXTI_EMR_MR10
		3204	#define EXTI_EMR_EM11 EXTI_EMR_MR11
		3205	#define EXTI_EMR_EM12 EXTI_EMR_MR12
		3206	#define EXTI_EMR_EM13 EXTI_EMR_MR13
		3207	#define EXTI_EMR_EM14 EXTI_EMR_MR14
		3208	#define EXTI_EMR_EM15 EXTI_EMR_MR15
		3209	#define EXTI_EMR_EM16 EXTI_EMR_MR16
		3210	#define EXTI_EMR_EM17 EXTI_EMR_MR17
		3211	#define EXTI_EMR_EM18 EXTI_EMR_MR18
		3212	#define EXTI_EMR_EM19 EXTI_EMR_MR19
		3213
2	mjames	3214	/**************** Bit definition for EXTI_RTSR register *****************/
5	mjames	3215	#define EXTI_RTSR_TR0_Pos (0U)
		3216	#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /!< 0x00000001 /
		3217	#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /!< Rising trigger event configuration bit of line 0 /
		3218	#define EXTI_RTSR_TR1_Pos (1U)
		3219	#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /!< 0x00000002 /
		3220	#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /!< Rising trigger event configuration bit of line 1 /
		3221	#define EXTI_RTSR_TR2_Pos (2U)
		3222	#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /!< 0x00000004 /
		3223	#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /!< Rising trigger event configuration bit of line 2 /
		3224	#define EXTI_RTSR_TR3_Pos (3U)
		3225	#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /!< 0x00000008 /
		3226	#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /!< Rising trigger event configuration bit of line 3 /
		3227	#define EXTI_RTSR_TR4_Pos (4U)
		3228	#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /!< 0x00000010 /
		3229	#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /!< Rising trigger event configuration bit of line 4 /
		3230	#define EXTI_RTSR_TR5_Pos (5U)
		3231	#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /!< 0x00000020 /
		3232	#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /!< Rising trigger event configuration bit of line 5 /
		3233	#define EXTI_RTSR_TR6_Pos (6U)
		3234	#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /!< 0x00000040 /
		3235	#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /!< Rising trigger event configuration bit of line 6 /
		3236	#define EXTI_RTSR_TR7_Pos (7U)
		3237	#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /!< 0x00000080 /
		3238	#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /!< Rising trigger event configuration bit of line 7 /
		3239	#define EXTI_RTSR_TR8_Pos (8U)
		3240	#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /!< 0x00000100 /
		3241	#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /!< Rising trigger event configuration bit of line 8 /
		3242	#define EXTI_RTSR_TR9_Pos (9U)
		3243	#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /!< 0x00000200 /
		3244	#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /!< Rising trigger event configuration bit of line 9 /
		3245	#define EXTI_RTSR_TR10_Pos (10U)
		3246	#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /!< 0x00000400 /
		3247	#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /!< Rising trigger event configuration bit of line 10 /
		3248	#define EXTI_RTSR_TR11_Pos (11U)
		3249	#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /!< 0x00000800 /
		3250	#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /!< Rising trigger event configuration bit of line 11 /
		3251	#define EXTI_RTSR_TR12_Pos (12U)
		3252	#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /!< 0x00001000 /
		3253	#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /!< Rising trigger event configuration bit of line 12 /
		3254	#define EXTI_RTSR_TR13_Pos (13U)
		3255	#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /!< 0x00002000 /
		3256	#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /!< Rising trigger event configuration bit of line 13 /
		3257	#define EXTI_RTSR_TR14_Pos (14U)
		3258	#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /!< 0x00004000 /
		3259	#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /!< Rising trigger event configuration bit of line 14 /
		3260	#define EXTI_RTSR_TR15_Pos (15U)
		3261	#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /!< 0x00008000 /
		3262	#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /!< Rising trigger event configuration bit of line 15 /
		3263	#define EXTI_RTSR_TR16_Pos (16U)
		3264	#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /!< 0x00010000 /
		3265	#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /!< Rising trigger event configuration bit of line 16 /
		3266	#define EXTI_RTSR_TR17_Pos (17U)
		3267	#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /!< 0x00020000 /
		3268	#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /!< Rising trigger event configuration bit of line 17 /
		3269	#define EXTI_RTSR_TR18_Pos (18U)
		3270	#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /!< 0x00040000 /
		3271	#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /!< Rising trigger event configuration bit of line 18 /
		3272	#define EXTI_RTSR_TR19_Pos (19U)
		3273	#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /!< 0x00080000 /
		3274	#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /!< Rising trigger event configuration bit of line 19 /
2	mjames	3275
5	mjames	3276	/* References Defines */
		3277	#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
		3278	#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
		3279	#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
		3280	#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
		3281	#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
		3282	#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
		3283	#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
		3284	#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
		3285	#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
		3286	#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
		3287	#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
		3288	#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
		3289	#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
		3290	#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
		3291	#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
		3292	#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
		3293	#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
		3294	#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
		3295	#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
		3296	#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
		3297
2	mjames	3298	/**************** Bit definition for EXTI_FTSR register *****************/
5	mjames	3299	#define EXTI_FTSR_TR0_Pos (0U)
		3300	#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /!< 0x00000001 /
		3301	#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /!< Falling trigger event configuration bit of line 0 /
		3302	#define EXTI_FTSR_TR1_Pos (1U)
		3303	#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /!< 0x00000002 /
		3304	#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /!< Falling trigger event configuration bit of line 1 /
		3305	#define EXTI_FTSR_TR2_Pos (2U)
		3306	#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /!< 0x00000004 /
		3307	#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /!< Falling trigger event configuration bit of line 2 /
		3308	#define EXTI_FTSR_TR3_Pos (3U)
		3309	#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /!< 0x00000008 /
		3310	#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /!< Falling trigger event configuration bit of line 3 /
		3311	#define EXTI_FTSR_TR4_Pos (4U)
		3312	#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /!< 0x00000010 /
		3313	#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /!< Falling trigger event configuration bit of line 4 /
		3314	#define EXTI_FTSR_TR5_Pos (5U)
		3315	#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /!< 0x00000020 /
		3316	#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /!< Falling trigger event configuration bit of line 5 /
		3317	#define EXTI_FTSR_TR6_Pos (6U)
		3318	#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /!< 0x00000040 /
		3319	#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /!< Falling trigger event configuration bit of line 6 /
		3320	#define EXTI_FTSR_TR7_Pos (7U)
		3321	#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /!< 0x00000080 /
		3322	#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /!< Falling trigger event configuration bit of line 7 /
		3323	#define EXTI_FTSR_TR8_Pos (8U)
		3324	#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /!< 0x00000100 /
		3325	#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /!< Falling trigger event configuration bit of line 8 /
		3326	#define EXTI_FTSR_TR9_Pos (9U)
		3327	#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /!< 0x00000200 /
		3328	#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /!< Falling trigger event configuration bit of line 9 /
		3329	#define EXTI_FTSR_TR10_Pos (10U)
		3330	#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /!< 0x00000400 /
		3331	#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /!< Falling trigger event configuration bit of line 10 /
		3332	#define EXTI_FTSR_TR11_Pos (11U)
		3333	#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /!< 0x00000800 /
		3334	#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /!< Falling trigger event configuration bit of line 11 /
		3335	#define EXTI_FTSR_TR12_Pos (12U)
		3336	#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /!< 0x00001000 /
		3337	#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /!< Falling trigger event configuration bit of line 12 /
		3338	#define EXTI_FTSR_TR13_Pos (13U)
		3339	#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /!< 0x00002000 /
		3340	#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /!< Falling trigger event configuration bit of line 13 /
		3341	#define EXTI_FTSR_TR14_Pos (14U)
		3342	#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /!< 0x00004000 /
		3343	#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /!< Falling trigger event configuration bit of line 14 /
		3344	#define EXTI_FTSR_TR15_Pos (15U)
		3345	#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /!< 0x00008000 /
		3346	#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /!< Falling trigger event configuration bit of line 15 /
		3347	#define EXTI_FTSR_TR16_Pos (16U)
		3348	#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /!< 0x00010000 /
		3349	#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /!< Falling trigger event configuration bit of line 16 /
		3350	#define EXTI_FTSR_TR17_Pos (17U)
		3351	#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /!< 0x00020000 /
		3352	#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /!< Falling trigger event configuration bit of line 17 /
		3353	#define EXTI_FTSR_TR18_Pos (18U)
		3354	#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /!< 0x00040000 /
		3355	#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /!< Falling trigger event configuration bit of line 18 /
		3356	#define EXTI_FTSR_TR19_Pos (19U)
		3357	#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /!< 0x00080000 /
		3358	#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /!< Falling trigger event configuration bit of line 19 /
2	mjames	3359
5	mjames	3360	/* References Defines */
		3361	#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
		3362	#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
		3363	#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
		3364	#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
		3365	#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
		3366	#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
		3367	#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
		3368	#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
		3369	#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
		3370	#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
		3371	#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
		3372	#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
		3373	#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
		3374	#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
		3375	#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
		3376	#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
		3377	#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
		3378	#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
		3379	#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
		3380	#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
		3381
2	mjames	3382	/**************** Bit definition for EXTI_SWIER register ****************/
5	mjames	3383	#define EXTI_SWIER_SWIER0_Pos (0U)
		3384	#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /!< 0x00000001 /
		3385	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /!< Software Interrupt on line 0 /
		3386	#define EXTI_SWIER_SWIER1_Pos (1U)
		3387	#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /!< 0x00000002 /
		3388	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /!< Software Interrupt on line 1 /
		3389	#define EXTI_SWIER_SWIER2_Pos (2U)
		3390	#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /!< 0x00000004 /
		3391	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /!< Software Interrupt on line 2 /
		3392	#define EXTI_SWIER_SWIER3_Pos (3U)
		3393	#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /!< 0x00000008 /
		3394	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /!< Software Interrupt on line 3 /
		3395	#define EXTI_SWIER_SWIER4_Pos (4U)
		3396	#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /!< 0x00000010 /
		3397	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /!< Software Interrupt on line 4 /
		3398	#define EXTI_SWIER_SWIER5_Pos (5U)
		3399	#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /!< 0x00000020 /
		3400	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /!< Software Interrupt on line 5 /
		3401	#define EXTI_SWIER_SWIER6_Pos (6U)
		3402	#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /!< 0x00000040 /
		3403	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /!< Software Interrupt on line 6 /
		3404	#define EXTI_SWIER_SWIER7_Pos (7U)
		3405	#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /!< 0x00000080 /
		3406	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /!< Software Interrupt on line 7 /
		3407	#define EXTI_SWIER_SWIER8_Pos (8U)
		3408	#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /!< 0x00000100 /
		3409	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /!< Software Interrupt on line 8 /
		3410	#define EXTI_SWIER_SWIER9_Pos (9U)
		3411	#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /!< 0x00000200 /
		3412	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /!< Software Interrupt on line 9 /
		3413	#define EXTI_SWIER_SWIER10_Pos (10U)
		3414	#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /!< 0x00000400 /
		3415	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /!< Software Interrupt on line 10 /
		3416	#define EXTI_SWIER_SWIER11_Pos (11U)
		3417	#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /!< 0x00000800 /
		3418	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /!< Software Interrupt on line 11 /
		3419	#define EXTI_SWIER_SWIER12_Pos (12U)
		3420	#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /!< 0x00001000 /
		3421	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /!< Software Interrupt on line 12 /
		3422	#define EXTI_SWIER_SWIER13_Pos (13U)
		3423	#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /!< 0x00002000 /
		3424	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /!< Software Interrupt on line 13 /
		3425	#define EXTI_SWIER_SWIER14_Pos (14U)
		3426	#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /!< 0x00004000 /
		3427	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /!< Software Interrupt on line 14 /
		3428	#define EXTI_SWIER_SWIER15_Pos (15U)
		3429	#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /!< 0x00008000 /
		3430	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /!< Software Interrupt on line 15 /
		3431	#define EXTI_SWIER_SWIER16_Pos (16U)
		3432	#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /!< 0x00010000 /
		3433	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /!< Software Interrupt on line 16 /
		3434	#define EXTI_SWIER_SWIER17_Pos (17U)
		3435	#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /!< 0x00020000 /
		3436	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /!< Software Interrupt on line 17 /
		3437	#define EXTI_SWIER_SWIER18_Pos (18U)
		3438	#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /!< 0x00040000 /
		3439	#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /!< Software Interrupt on line 18 /
		3440	#define EXTI_SWIER_SWIER19_Pos (19U)
		3441	#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /!< 0x00080000 /
		3442	#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /!< Software Interrupt on line 19 /
2	mjames	3443
5	mjames	3444	/* References Defines */
		3445	#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
		3446	#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
		3447	#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
		3448	#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
		3449	#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
		3450	#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
		3451	#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
		3452	#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
		3453	#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
		3454	#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
		3455	#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
		3456	#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
		3457	#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
		3458	#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
		3459	#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
		3460	#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
		3461	#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
		3462	#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
		3463	#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
		3464	#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
		3465
2	mjames	3466	/***************** Bit definition for EXTI_PR register ******************/
5	mjames	3467	#define EXTI_PR_PR0_Pos (0U)
		3468	#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /!< 0x00000001 /
		3469	#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /!< Pending bit for line 0 /
		3470	#define EXTI_PR_PR1_Pos (1U)
		3471	#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /!< 0x00000002 /
		3472	#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /!< Pending bit for line 1 /
		3473	#define EXTI_PR_PR2_Pos (2U)
		3474	#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /!< 0x00000004 /
		3475	#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /!< Pending bit for line 2 /
		3476	#define EXTI_PR_PR3_Pos (3U)
		3477	#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /!< 0x00000008 /
		3478	#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /!< Pending bit for line 3 /
		3479	#define EXTI_PR_PR4_Pos (4U)
		3480	#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /!< 0x00000010 /
		3481	#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /!< Pending bit for line 4 /
		3482	#define EXTI_PR_PR5_Pos (5U)
		3483	#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /!< 0x00000020 /
		3484	#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /!< Pending bit for line 5 /
		3485	#define EXTI_PR_PR6_Pos (6U)
		3486	#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /!< 0x00000040 /
		3487	#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /!< Pending bit for line 6 /
		3488	#define EXTI_PR_PR7_Pos (7U)
		3489	#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /!< 0x00000080 /
		3490	#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /!< Pending bit for line 7 /
		3491	#define EXTI_PR_PR8_Pos (8U)
		3492	#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /!< 0x00000100 /
		3493	#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /!< Pending bit for line 8 /
		3494	#define EXTI_PR_PR9_Pos (9U)
		3495	#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /!< 0x00000200 /
		3496	#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /!< Pending bit for line 9 /
		3497	#define EXTI_PR_PR10_Pos (10U)
		3498	#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /!< 0x00000400 /
		3499	#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /!< Pending bit for line 10 /
		3500	#define EXTI_PR_PR11_Pos (11U)
		3501	#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /!< 0x00000800 /
		3502	#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /!< Pending bit for line 11 /
		3503	#define EXTI_PR_PR12_Pos (12U)
		3504	#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /!< 0x00001000 /
		3505	#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /!< Pending bit for line 12 /
		3506	#define EXTI_PR_PR13_Pos (13U)
		3507	#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /!< 0x00002000 /
		3508	#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /!< Pending bit for line 13 /
		3509	#define EXTI_PR_PR14_Pos (14U)
		3510	#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /!< 0x00004000 /
		3511	#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /!< Pending bit for line 14 /
		3512	#define EXTI_PR_PR15_Pos (15U)
		3513	#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /!< 0x00008000 /
		3514	#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /!< Pending bit for line 15 /
		3515	#define EXTI_PR_PR16_Pos (16U)
		3516	#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /!< 0x00010000 /
		3517	#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /!< Pending bit for line 16 /
		3518	#define EXTI_PR_PR17_Pos (17U)
		3519	#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /!< 0x00020000 /
		3520	#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /!< Pending bit for line 17 /
		3521	#define EXTI_PR_PR18_Pos (18U)
		3522	#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /!< 0x00040000 /
		3523	#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /!< Pending bit for line 18 /
		3524	#define EXTI_PR_PR19_Pos (19U)
		3525	#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /!< 0x00080000 /
		3526	#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /!< Pending bit for line 19 /
2	mjames	3527
5	mjames	3528	/* References Defines */
		3529	#define EXTI_PR_PIF0 EXTI_PR_PR0
		3530	#define EXTI_PR_PIF1 EXTI_PR_PR1
		3531	#define EXTI_PR_PIF2 EXTI_PR_PR2
		3532	#define EXTI_PR_PIF3 EXTI_PR_PR3
		3533	#define EXTI_PR_PIF4 EXTI_PR_PR4
		3534	#define EXTI_PR_PIF5 EXTI_PR_PR5
		3535	#define EXTI_PR_PIF6 EXTI_PR_PR6
		3536	#define EXTI_PR_PIF7 EXTI_PR_PR7
		3537	#define EXTI_PR_PIF8 EXTI_PR_PR8
		3538	#define EXTI_PR_PIF9 EXTI_PR_PR9
		3539	#define EXTI_PR_PIF10 EXTI_PR_PR10
		3540	#define EXTI_PR_PIF11 EXTI_PR_PR11
		3541	#define EXTI_PR_PIF12 EXTI_PR_PR12
		3542	#define EXTI_PR_PIF13 EXTI_PR_PR13
		3543	#define EXTI_PR_PIF14 EXTI_PR_PR14
		3544	#define EXTI_PR_PIF15 EXTI_PR_PR15
		3545	#define EXTI_PR_PIF16 EXTI_PR_PR16
		3546	#define EXTI_PR_PIF17 EXTI_PR_PR17
		3547	#define EXTI_PR_PIF18 EXTI_PR_PR18
		3548	#define EXTI_PR_PIF19 EXTI_PR_PR19
		3549
2	mjames	3550	/******************************************************************************/
		3551	/* */
		3552	/* DMA Controller */
		3553	/* */
		3554	/******************************************************************************/
		3555
		3556	/***************** Bit definition for DMA_ISR register ******************/
5	mjames	3557	#define DMA_ISR_GIF1_Pos (0U)
		3558	#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /!< 0x00000001 /
		3559	#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /!< Channel 1 Global interrupt flag /
		3560	#define DMA_ISR_TCIF1_Pos (1U)
		3561	#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /!< 0x00000002 /
		3562	#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /!< Channel 1 Transfer Complete flag /
		3563	#define DMA_ISR_HTIF1_Pos (2U)
		3564	#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /!< 0x00000004 /
		3565	#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /!< Channel 1 Half Transfer flag /
		3566	#define DMA_ISR_TEIF1_Pos (3U)
		3567	#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /!< 0x00000008 /
		3568	#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /!< Channel 1 Transfer Error flag /
		3569	#define DMA_ISR_GIF2_Pos (4U)
		3570	#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /!< 0x00000010 /
		3571	#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /!< Channel 2 Global interrupt flag /
		3572	#define DMA_ISR_TCIF2_Pos (5U)
		3573	#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /!< 0x00000020 /
		3574	#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /!< Channel 2 Transfer Complete flag /
		3575	#define DMA_ISR_HTIF2_Pos (6U)
		3576	#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /!< 0x00000040 /
		3577	#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /!< Channel 2 Half Transfer flag /
		3578	#define DMA_ISR_TEIF2_Pos (7U)
		3579	#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /!< 0x00000080 /
		3580	#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /!< Channel 2 Transfer Error flag /
		3581	#define DMA_ISR_GIF3_Pos (8U)
		3582	#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /!< 0x00000100 /
		3583	#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /!< Channel 3 Global interrupt flag /
		3584	#define DMA_ISR_TCIF3_Pos (9U)
		3585	#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /!< 0x00000200 /
		3586	#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /!< Channel 3 Transfer Complete flag /
		3587	#define DMA_ISR_HTIF3_Pos (10U)
		3588	#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /!< 0x00000400 /
		3589	#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /!< Channel 3 Half Transfer flag /
		3590	#define DMA_ISR_TEIF3_Pos (11U)
		3591	#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /!< 0x00000800 /
		3592	#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /!< Channel 3 Transfer Error flag /
		3593	#define DMA_ISR_GIF4_Pos (12U)
		3594	#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /!< 0x00001000 /
		3595	#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /!< Channel 4 Global interrupt flag /
		3596	#define DMA_ISR_TCIF4_Pos (13U)
		3597	#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /!< 0x00002000 /
		3598	#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /!< Channel 4 Transfer Complete flag /
		3599	#define DMA_ISR_HTIF4_Pos (14U)
		3600	#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /!< 0x00004000 /
		3601	#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /!< Channel 4 Half Transfer flag /
		3602	#define DMA_ISR_TEIF4_Pos (15U)
		3603	#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /!< 0x00008000 /
		3604	#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /!< Channel 4 Transfer Error flag /
		3605	#define DMA_ISR_GIF5_Pos (16U)
		3606	#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /!< 0x00010000 /
		3607	#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /!< Channel 5 Global interrupt flag /
		3608	#define DMA_ISR_TCIF5_Pos (17U)
		3609	#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /!< 0x00020000 /
		3610	#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /!< Channel 5 Transfer Complete flag /
		3611	#define DMA_ISR_HTIF5_Pos (18U)
		3612	#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /!< 0x00040000 /
		3613	#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /!< Channel 5 Half Transfer flag /
		3614	#define DMA_ISR_TEIF5_Pos (19U)
		3615	#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /!< 0x00080000 /
		3616	#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /!< Channel 5 Transfer Error flag /
		3617	#define DMA_ISR_GIF6_Pos (20U)
		3618	#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /!< 0x00100000 /
		3619	#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /!< Channel 6 Global interrupt flag /
		3620	#define DMA_ISR_TCIF6_Pos (21U)
		3621	#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /!< 0x00200000 /
		3622	#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /!< Channel 6 Transfer Complete flag /
		3623	#define DMA_ISR_HTIF6_Pos (22U)
		3624	#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /!< 0x00400000 /
		3625	#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /!< Channel 6 Half Transfer flag /
		3626	#define DMA_ISR_TEIF6_Pos (23U)
		3627	#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /!< 0x00800000 /
		3628	#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /!< Channel 6 Transfer Error flag /
		3629	#define DMA_ISR_GIF7_Pos (24U)
		3630	#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /!< 0x01000000 /
		3631	#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /!< Channel 7 Global interrupt flag /
		3632	#define DMA_ISR_TCIF7_Pos (25U)
		3633	#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /!< 0x02000000 /
		3634	#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /!< Channel 7 Transfer Complete flag /
		3635	#define DMA_ISR_HTIF7_Pos (26U)
		3636	#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /!< 0x04000000 /
		3637	#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /!< Channel 7 Half Transfer flag /
		3638	#define DMA_ISR_TEIF7_Pos (27U)
		3639	#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /!< 0x08000000 /
		3640	#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /!< Channel 7 Transfer Error flag /
2	mjames	3641
		3642	/***************** Bit definition for DMA_IFCR register *****************/
5	mjames	3643	#define DMA_IFCR_CGIF1_Pos (0U)
		3644	#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /!< 0x00000001 /
		3645	#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /!< Channel 1 Global interrupt clear /
		3646	#define DMA_IFCR_CTCIF1_Pos (1U)
		3647	#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /!< 0x00000002 /
		3648	#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /!< Channel 1 Transfer Complete clear /
		3649	#define DMA_IFCR_CHTIF1_Pos (2U)
		3650	#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /!< 0x00000004 /
		3651	#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /!< Channel 1 Half Transfer clear /
		3652	#define DMA_IFCR_CTEIF1_Pos (3U)
		3653	#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /!< 0x00000008 /
		3654	#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /!< Channel 1 Transfer Error clear /
		3655	#define DMA_IFCR_CGIF2_Pos (4U)
		3656	#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /!< 0x00000010 /
		3657	#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /!< Channel 2 Global interrupt clear /
		3658	#define DMA_IFCR_CTCIF2_Pos (5U)
		3659	#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /!< 0x00000020 /
		3660	#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /!< Channel 2 Transfer Complete clear /
		3661	#define DMA_IFCR_CHTIF2_Pos (6U)
		3662	#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /!< 0x00000040 /
		3663	#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /!< Channel 2 Half Transfer clear /
		3664	#define DMA_IFCR_CTEIF2_Pos (7U)
		3665	#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /!< 0x00000080 /
		3666	#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /!< Channel 2 Transfer Error clear /
		3667	#define DMA_IFCR_CGIF3_Pos (8U)
		3668	#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /!< 0x00000100 /
		3669	#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /!< Channel 3 Global interrupt clear /
		3670	#define DMA_IFCR_CTCIF3_Pos (9U)
		3671	#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /!< 0x00000200 /
		3672	#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /!< Channel 3 Transfer Complete clear /
		3673	#define DMA_IFCR_CHTIF3_Pos (10U)
		3674	#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /!< 0x00000400 /
		3675	#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /!< Channel 3 Half Transfer clear /
		3676	#define DMA_IFCR_CTEIF3_Pos (11U)
		3677	#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /!< 0x00000800 /
		3678	#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /!< Channel 3 Transfer Error clear /
		3679	#define DMA_IFCR_CGIF4_Pos (12U)
		3680	#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /!< 0x00001000 /
		3681	#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /!< Channel 4 Global interrupt clear /
		3682	#define DMA_IFCR_CTCIF4_Pos (13U)
		3683	#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /!< 0x00002000 /
		3684	#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /!< Channel 4 Transfer Complete clear /
		3685	#define DMA_IFCR_CHTIF4_Pos (14U)
		3686	#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /!< 0x00004000 /
		3687	#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /!< Channel 4 Half Transfer clear /
		3688	#define DMA_IFCR_CTEIF4_Pos (15U)
		3689	#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /!< 0x00008000 /
		3690	#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /!< Channel 4 Transfer Error clear /
		3691	#define DMA_IFCR_CGIF5_Pos (16U)
		3692	#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /!< 0x00010000 /
		3693	#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /!< Channel 5 Global interrupt clear /
		3694	#define DMA_IFCR_CTCIF5_Pos (17U)
		3695	#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /!< 0x00020000 /
		3696	#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /!< Channel 5 Transfer Complete clear /
		3697	#define DMA_IFCR_CHTIF5_Pos (18U)
		3698	#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /!< 0x00040000 /
		3699	#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /!< Channel 5 Half Transfer clear /
		3700	#define DMA_IFCR_CTEIF5_Pos (19U)
		3701	#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /!< 0x00080000 /
		3702	#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /!< Channel 5 Transfer Error clear /
		3703	#define DMA_IFCR_CGIF6_Pos (20U)
		3704	#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /!< 0x00100000 /
		3705	#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /!< Channel 6 Global interrupt clear /
		3706	#define DMA_IFCR_CTCIF6_Pos (21U)
		3707	#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /!< 0x00200000 /
		3708	#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /!< Channel 6 Transfer Complete clear /
		3709	#define DMA_IFCR_CHTIF6_Pos (22U)
		3710	#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /!< 0x00400000 /
		3711	#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /!< Channel 6 Half Transfer clear /
		3712	#define DMA_IFCR_CTEIF6_Pos (23U)
		3713	#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /!< 0x00800000 /
		3714	#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /!< Channel 6 Transfer Error clear /
		3715	#define DMA_IFCR_CGIF7_Pos (24U)
		3716	#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /!< 0x01000000 /
		3717	#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /!< Channel 7 Global interrupt clear /
		3718	#define DMA_IFCR_CTCIF7_Pos (25U)
		3719	#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /!< 0x02000000 /
		3720	#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /!< Channel 7 Transfer Complete clear /
		3721	#define DMA_IFCR_CHTIF7_Pos (26U)
		3722	#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /!< 0x04000000 /
		3723	#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /!< Channel 7 Half Transfer clear /
		3724	#define DMA_IFCR_CTEIF7_Pos (27U)
		3725	#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /!< 0x08000000 /
		3726	#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /!< Channel 7 Transfer Error clear /
2	mjames	3727
		3728	/***************** Bit definition for DMA_CCR register *****************/
5	mjames	3729	#define DMA_CCR_EN_Pos (0U)
		3730	#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /!< 0x00000001 /
		3731	#define DMA_CCR_EN DMA_CCR_EN_Msk /!< Channel enable /
		3732	#define DMA_CCR_TCIE_Pos (1U)
		3733	#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /!< 0x00000002 /
		3734	#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /!< Transfer complete interrupt enable /
		3735	#define DMA_CCR_HTIE_Pos (2U)
		3736	#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /!< 0x00000004 /
		3737	#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /!< Half Transfer interrupt enable /
		3738	#define DMA_CCR_TEIE_Pos (3U)
		3739	#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /!< 0x00000008 /
		3740	#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /!< Transfer error interrupt enable /
		3741	#define DMA_CCR_DIR_Pos (4U)
		3742	#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /!< 0x00000010 /
		3743	#define DMA_CCR_DIR DMA_CCR_DIR_Msk /!< Data transfer direction /
		3744	#define DMA_CCR_CIRC_Pos (5U)
		3745	#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /!< 0x00000020 /
		3746	#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /!< Circular mode /
		3747	#define DMA_CCR_PINC_Pos (6U)
		3748	#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /!< 0x00000040 /
		3749	#define DMA_CCR_PINC DMA_CCR_PINC_Msk /!< Peripheral increment mode /
		3750	#define DMA_CCR_MINC_Pos (7U)
		3751	#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /!< 0x00000080 /
		3752	#define DMA_CCR_MINC DMA_CCR_MINC_Msk /!< Memory increment mode /
2	mjames	3753
5	mjames	3754	#define DMA_CCR_PSIZE_Pos (8U)
		3755	#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /!< 0x00000300 /
		3756	#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /!< PSIZE[1:0] bits (Peripheral size) /
		3757	#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /!< 0x00000100 /
		3758	#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /!< 0x00000200 /
2	mjames	3759
5	mjames	3760	#define DMA_CCR_MSIZE_Pos (10U)
		3761	#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /!< 0x00000C00 /
		3762	#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /!< MSIZE[1:0] bits (Memory size) /
		3763	#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /!< 0x00000400 /
		3764	#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /!< 0x00000800 /
2	mjames	3765
5	mjames	3766	#define DMA_CCR_PL_Pos (12U)
		3767	#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /!< 0x00003000 /
		3768	#define DMA_CCR_PL DMA_CCR_PL_Msk /!< PL[1:0] bits(Channel Priority level) /
		3769	#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /!< 0x00001000 /
		3770	#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /!< 0x00002000 /
2	mjames	3771
5	mjames	3772	#define DMA_CCR_MEM2MEM_Pos (14U)
		3773	#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /!< 0x00004000 /
		3774	#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /!< Memory to memory mode /
2	mjames	3775
		3776	/**************** Bit definition for DMA_CNDTR register ****************/
5	mjames	3777	#define DMA_CNDTR_NDT_Pos (0U)
		3778	#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /!< 0x0000FFFF /
		3779	#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /!< Number of data to Transfer /
2	mjames	3780
		3781	/**************** Bit definition for DMA_CPAR register *****************/
5	mjames	3782	#define DMA_CPAR_PA_Pos (0U)
		3783	#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /!< 0xFFFFFFFF /
		3784	#define DMA_CPAR_PA DMA_CPAR_PA_Msk /!< Peripheral Address /
2	mjames	3785
		3786	/**************** Bit definition for DMA_CMAR register *****************/
5	mjames	3787	#define DMA_CMAR_MA_Pos (0U)
		3788	#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /!< 0xFFFFFFFF /
		3789	#define DMA_CMAR_MA DMA_CMAR_MA_Msk /!< Memory Address /
2	mjames	3790
		3791	/******************************************************************************/
		3792	/* */
5	mjames	3793	/* Analog to Digital Converter (ADC) */
2	mjames	3794	/* */
		3795	/******************************************************************************/
		3796
5	mjames	3797	/*
		3798	* @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
		3799	*/
		3800	/* Note: No specific macro feature on this device */
		3801
2	mjames	3802	/****************** Bit definition for ADC_SR register ******************/
5	mjames	3803	#define ADC_SR_AWD_Pos (0U)
		3804	#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /!< 0x00000001 /
		3805	#define ADC_SR_AWD ADC_SR_AWD_Msk /!< ADC analog watchdog 1 flag /
		3806	#define ADC_SR_EOS_Pos (1U)
		3807	#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /!< 0x00000002 /
		3808	#define ADC_SR_EOS ADC_SR_EOS_Msk /!< ADC group regular end of sequence conversions flag /
		3809	#define ADC_SR_JEOS_Pos (2U)
		3810	#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /!< 0x00000004 /
		3811	#define ADC_SR_JEOS ADC_SR_JEOS_Msk /!< ADC group injected end of sequence conversions flag /
		3812	#define ADC_SR_JSTRT_Pos (3U)
		3813	#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /!< 0x00000008 /
		3814	#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /!< ADC group injected conversion start flag /
		3815	#define ADC_SR_STRT_Pos (4U)
		3816	#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /!< 0x00000010 /
		3817	#define ADC_SR_STRT ADC_SR_STRT_Msk /!< ADC group regular conversion start flag /
2	mjames	3818
5	mjames	3819	/* Legacy defines */
		3820	#define ADC_SR_EOC (ADC_SR_EOS)
		3821	#define ADC_SR_JEOC (ADC_SR_JEOS)
		3822
2	mjames	3823	/***************** Bit definition for ADC_CR1 register ******************/
5	mjames	3824	#define ADC_CR1_AWDCH_Pos (0U)
		3825	#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /!< 0x0000001F /
		3826	#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /!< ADC analog watchdog 1 monitored channel selection /
		3827	#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /!< 0x00000001 /
		3828	#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /!< 0x00000002 /
		3829	#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /!< 0x00000004 /
		3830	#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /!< 0x00000008 /
		3831	#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /!< 0x00000010 /
2	mjames	3832
5	mjames	3833	#define ADC_CR1_EOSIE_Pos (5U)
		3834	#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /!< 0x00000020 /
		3835	#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /!< ADC group regular end of sequence conversions interrupt /
		3836	#define ADC_CR1_AWDIE_Pos (6U)
		3837	#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /!< 0x00000040 /
		3838	#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /!< ADC analog watchdog 1 interrupt /
		3839	#define ADC_CR1_JEOSIE_Pos (7U)
		3840	#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /!< 0x00000080 /
		3841	#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /!< ADC group injected end of sequence conversions interrupt /
		3842	#define ADC_CR1_SCAN_Pos (8U)
		3843	#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /!< 0x00000100 /
		3844	#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /!< ADC scan mode /
		3845	#define ADC_CR1_AWDSGL_Pos (9U)
		3846	#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /!< 0x00000200 /
		3847	#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /!< ADC analog watchdog 1 monitoring a single channel or all channels /
		3848	#define ADC_CR1_JAUTO_Pos (10U)
		3849	#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /!< 0x00000400 /
		3850	#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /!< ADC group injected automatic trigger mode /
		3851	#define ADC_CR1_DISCEN_Pos (11U)
		3852	#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /!< 0x00000800 /
		3853	#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /
		3854	#define ADC_CR1_JDISCEN_Pos (12U)
		3855	#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /!< 0x00001000 /
		3856	#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /!< ADC group injected sequencer discontinuous mode /
2	mjames	3857
5	mjames	3858	#define ADC_CR1_DISCNUM_Pos (13U)
		3859	#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /!< 0x0000E000 /
		3860	#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /!< ADC group regular sequencer discontinuous number of ranks /
		3861	#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /!< 0x00002000 /
		3862	#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /!< 0x00004000 /
		3863	#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /!< 0x00008000 /
2	mjames	3864
5	mjames	3865	#define ADC_CR1_JAWDEN_Pos (22U)
		3866	#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /!< 0x00400000 /
		3867	#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group injected /
		3868	#define ADC_CR1_AWDEN_Pos (23U)
		3869	#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /!< 0x00800000 /
		3870	#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group regular /
2	mjames	3871
5	mjames	3872	/* Legacy defines */
		3873	#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
		3874	#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
		3875
2	mjames	3876	/***************** Bit definition for ADC_CR2 register ******************/
5	mjames	3877	#define ADC_CR2_ADON_Pos (0U)
		3878	#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /!< 0x00000001 /
		3879	#define ADC_CR2_ADON ADC_CR2_ADON_Msk /!< ADC enable /
		3880	#define ADC_CR2_CONT_Pos (1U)
		3881	#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /!< 0x00000002 /
		3882	#define ADC_CR2_CONT ADC_CR2_CONT_Msk /!< ADC group regular continuous conversion mode /
		3883	#define ADC_CR2_CAL_Pos (2U)
		3884	#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /!< 0x00000004 /
		3885	#define ADC_CR2_CAL ADC_CR2_CAL_Msk /!< ADC calibration start /
		3886	#define ADC_CR2_RSTCAL_Pos (3U)
		3887	#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /!< 0x00000008 /
		3888	#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /!< ADC calibration reset /
		3889	#define ADC_CR2_DMA_Pos (8U)
		3890	#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /!< 0x00000100 /
		3891	#define ADC_CR2_DMA ADC_CR2_DMA_Msk /!< ADC DMA transfer enable /
		3892	#define ADC_CR2_ALIGN_Pos (11U)
		3893	#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /!< 0x00000800 /
		3894	#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /!< ADC data alignement /
2	mjames	3895
5	mjames	3896	#define ADC_CR2_JEXTSEL_Pos (12U)
		3897	#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /!< 0x00007000 /
		3898	#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /!< ADC group injected external trigger source /
		3899	#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /!< 0x00001000 /
		3900	#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /!< 0x00002000 /
		3901	#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /!< 0x00004000 /
2	mjames	3902
5	mjames	3903	#define ADC_CR2_JEXTTRIG_Pos (15U)
		3904	#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /!< 0x00008000 /
		3905	#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /!< ADC group injected external trigger enable /
2	mjames	3906
5	mjames	3907	#define ADC_CR2_EXTSEL_Pos (17U)
		3908	#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /!< 0x000E0000 /
		3909	#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /!< ADC group regular external trigger source /
		3910	#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /!< 0x00020000 /
		3911	#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /!< 0x00040000 /
		3912	#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /!< 0x00080000 /
2	mjames	3913
5	mjames	3914	#define ADC_CR2_EXTTRIG_Pos (20U)
		3915	#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /!< 0x00100000 /
		3916	#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /!< ADC group regular external trigger enable /
		3917	#define ADC_CR2_JSWSTART_Pos (21U)
		3918	#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /!< 0x00200000 /
		3919	#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /!< ADC group injected conversion start /
		3920	#define ADC_CR2_SWSTART_Pos (22U)
		3921	#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /!< 0x00400000 /
		3922	#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /!< ADC group regular conversion start /
		3923	#define ADC_CR2_TSVREFE_Pos (23U)
		3924	#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /!< 0x00800000 /
		3925	#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /!< ADC internal path to VrefInt and temperature sensor enable /
2	mjames	3926
		3927	/**************** Bit definition for ADC_SMPR1 register *****************/
5	mjames	3928	#define ADC_SMPR1_SMP10_Pos (0U)
		3929	#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /!< 0x00000007 /
		3930	#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /!< ADC channel 10 sampling time selection /
		3931	#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /!< 0x00000001 /
		3932	#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /!< 0x00000002 /
		3933	#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /!< 0x00000004 /
2	mjames	3934
5	mjames	3935	#define ADC_SMPR1_SMP11_Pos (3U)
		3936	#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /!< 0x00000038 /
		3937	#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /!< ADC channel 11 sampling time selection /
		3938	#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /!< 0x00000008 /
		3939	#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /!< 0x00000010 /
		3940	#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /!< 0x00000020 /
2	mjames	3941
5	mjames	3942	#define ADC_SMPR1_SMP12_Pos (6U)
		3943	#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /!< 0x000001C0 /
		3944	#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /!< ADC channel 12 sampling time selection /
		3945	#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /!< 0x00000040 /
		3946	#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /!< 0x00000080 /
		3947	#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /!< 0x00000100 /
2	mjames	3948
5	mjames	3949	#define ADC_SMPR1_SMP13_Pos (9U)
		3950	#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /!< 0x00000E00 /
		3951	#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /!< ADC channel 13 sampling time selection /
		3952	#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /!< 0x00000200 /
		3953	#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /!< 0x00000400 /
		3954	#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /!< 0x00000800 /
2	mjames	3955
5	mjames	3956	#define ADC_SMPR1_SMP14_Pos (12U)
		3957	#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /!< 0x00007000 /
		3958	#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /!< ADC channel 14 sampling time selection /
		3959	#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /!< 0x00001000 /
		3960	#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /!< 0x00002000 /
		3961	#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /!< 0x00004000 /
2	mjames	3962
5	mjames	3963	#define ADC_SMPR1_SMP15_Pos (15U)
		3964	#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /!< 0x00038000 /
		3965	#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /!< ADC channel 15 sampling time selection /
		3966	#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /!< 0x00008000 /
		3967	#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /!< 0x00010000 /
		3968	#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /!< 0x00020000 /
2	mjames	3969
5	mjames	3970	#define ADC_SMPR1_SMP16_Pos (18U)
		3971	#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /!< 0x001C0000 /
		3972	#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /!< ADC channel 16 sampling time selection /
		3973	#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /!< 0x00040000 /
		3974	#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /!< 0x00080000 /
		3975	#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /!< 0x00100000 /
2	mjames	3976
5	mjames	3977	#define ADC_SMPR1_SMP17_Pos (21U)
		3978	#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /!< 0x00E00000 /
		3979	#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /!< ADC channel 17 sampling time selection /
		3980	#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /!< 0x00200000 /
		3981	#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /!< 0x00400000 /
		3982	#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /!< 0x00800000 /
2	mjames	3983
		3984	/**************** Bit definition for ADC_SMPR2 register *****************/
5	mjames	3985	#define ADC_SMPR2_SMP0_Pos (0U)
		3986	#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /!< 0x00000007 /
		3987	#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /!< ADC channel 0 sampling time selection /
		3988	#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /!< 0x00000001 /
		3989	#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /!< 0x00000002 /
		3990	#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /!< 0x00000004 /
2	mjames	3991
5	mjames	3992	#define ADC_SMPR2_SMP1_Pos (3U)
		3993	#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /!< 0x00000038 /
		3994	#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /!< ADC channel 1 sampling time selection /
		3995	#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /!< 0x00000008 /
		3996	#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /!< 0x00000010 /
		3997	#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /!< 0x00000020 /
2	mjames	3998
5	mjames	3999	#define ADC_SMPR2_SMP2_Pos (6U)
		4000	#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /!< 0x000001C0 /
		4001	#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /!< ADC channel 2 sampling time selection /
		4002	#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /!< 0x00000040 /
		4003	#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /!< 0x00000080 /
		4004	#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /!< 0x00000100 /
2	mjames	4005
5	mjames	4006	#define ADC_SMPR2_SMP3_Pos (9U)
		4007	#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /!< 0x00000E00 /
		4008	#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /!< ADC channel 3 sampling time selection /
		4009	#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /!< 0x00000200 /
		4010	#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /!< 0x00000400 /
		4011	#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /!< 0x00000800 /
2	mjames	4012
5	mjames	4013	#define ADC_SMPR2_SMP4_Pos (12U)
		4014	#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /!< 0x00007000 /
		4015	#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /!< ADC channel 4 sampling time selection /
		4016	#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /!< 0x00001000 /
		4017	#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /!< 0x00002000 /
		4018	#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /!< 0x00004000 /
2	mjames	4019
5	mjames	4020	#define ADC_SMPR2_SMP5_Pos (15U)
		4021	#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /!< 0x00038000 /
		4022	#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /!< ADC channel 5 sampling time selection /
		4023	#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /!< 0x00008000 /
		4024	#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /!< 0x00010000 /
		4025	#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /!< 0x00020000 /
2	mjames	4026
5	mjames	4027	#define ADC_SMPR2_SMP6_Pos (18U)
		4028	#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /!< 0x001C0000 /
		4029	#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /!< ADC channel 6 sampling time selection /
		4030	#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /!< 0x00040000 /
		4031	#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /!< 0x00080000 /
		4032	#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /!< 0x00100000 /
2	mjames	4033
5	mjames	4034	#define ADC_SMPR2_SMP7_Pos (21U)
		4035	#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /!< 0x00E00000 /
		4036	#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /!< ADC channel 7 sampling time selection /
		4037	#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /!< 0x00200000 /
		4038	#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /!< 0x00400000 /
		4039	#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /!< 0x00800000 /
2	mjames	4040
5	mjames	4041	#define ADC_SMPR2_SMP8_Pos (24U)
		4042	#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /!< 0x07000000 /
		4043	#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /!< ADC channel 8 sampling time selection /
		4044	#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /!< 0x01000000 /
		4045	#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /!< 0x02000000 /
		4046	#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /!< 0x04000000 /
2	mjames	4047
5	mjames	4048	#define ADC_SMPR2_SMP9_Pos (27U)
		4049	#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /!< 0x38000000 /
		4050	#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /!< ADC channel 9 sampling time selection /
		4051	#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /!< 0x08000000 /
		4052	#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /!< 0x10000000 /
		4053	#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /!< 0x20000000 /
2	mjames	4054
		4055	/**************** Bit definition for ADC_JOFR1 register *****************/
5	mjames	4056	#define ADC_JOFR1_JOFFSET1_Pos (0U)
		4057	#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /!< 0x00000FFF /
		4058	#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /!< ADC group injected sequencer rank 1 offset value /
2	mjames	4059
		4060	/**************** Bit definition for ADC_JOFR2 register *****************/
5	mjames	4061	#define ADC_JOFR2_JOFFSET2_Pos (0U)
		4062	#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /!< 0x00000FFF /
		4063	#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /!< ADC group injected sequencer rank 2 offset value /
2	mjames	4064
		4065	/**************** Bit definition for ADC_JOFR3 register *****************/
5	mjames	4066	#define ADC_JOFR3_JOFFSET3_Pos (0U)
		4067	#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /!< 0x00000FFF /
		4068	#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /!< ADC group injected sequencer rank 3 offset value /
2	mjames	4069
		4070	/**************** Bit definition for ADC_JOFR4 register *****************/
5	mjames	4071	#define ADC_JOFR4_JOFFSET4_Pos (0U)
		4072	#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /!< 0x00000FFF /
		4073	#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /!< ADC group injected sequencer rank 4 offset value /
2	mjames	4074
		4075	/***************** Bit definition for ADC_HTR register ******************/
5	mjames	4076	#define ADC_HTR_HT_Pos (0U)
		4077	#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /!< 0x00000FFF /
		4078	#define ADC_HTR_HT ADC_HTR_HT_Msk /!< ADC analog watchdog 1 threshold high /
2	mjames	4079
		4080	/***************** Bit definition for ADC_LTR register ******************/
5	mjames	4081	#define ADC_LTR_LT_Pos (0U)
		4082	#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /!< 0x00000FFF /
		4083	#define ADC_LTR_LT ADC_LTR_LT_Msk /!< ADC analog watchdog 1 threshold low /
2	mjames	4084
		4085	/***************** Bit definition for ADC_SQR1 register *****************/
5	mjames	4086	#define ADC_SQR1_SQ13_Pos (0U)
		4087	#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /!< 0x0000001F /
		4088	#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /!< ADC group regular sequencer rank 13 /
		4089	#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /!< 0x00000001 /
		4090	#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /!< 0x00000002 /
		4091	#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /!< 0x00000004 /
		4092	#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /!< 0x00000008 /
		4093	#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /!< 0x00000010 /
2	mjames	4094
5	mjames	4095	#define ADC_SQR1_SQ14_Pos (5U)
		4096	#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /!< 0x000003E0 /
		4097	#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /!< ADC group regular sequencer rank 14 /
		4098	#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /!< 0x00000020 /
		4099	#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /!< 0x00000040 /
		4100	#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /!< 0x00000080 /
		4101	#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /!< 0x00000100 /
		4102	#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /!< 0x00000200 /
2	mjames	4103
5	mjames	4104	#define ADC_SQR1_SQ15_Pos (10U)
		4105	#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /!< 0x00007C00 /
		4106	#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /!< ADC group regular sequencer rank 15 /
		4107	#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /!< 0x00000400 /
		4108	#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /!< 0x00000800 /
		4109	#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /!< 0x00001000 /
		4110	#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /!< 0x00002000 /
		4111	#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /!< 0x00004000 /
2	mjames	4112
5	mjames	4113	#define ADC_SQR1_SQ16_Pos (15U)
		4114	#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /!< 0x000F8000 /
		4115	#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /!< ADC group regular sequencer rank 16 /
		4116	#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /!< 0x00008000 /
		4117	#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /!< 0x00010000 /
		4118	#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /!< 0x00020000 /
		4119	#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /!< 0x00040000 /
		4120	#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /!< 0x00080000 /
2	mjames	4121
5	mjames	4122	#define ADC_SQR1_L_Pos (20U)
		4123	#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /!< 0x00F00000 /
		4124	#define ADC_SQR1_L ADC_SQR1_L_Msk /!< ADC group regular sequencer scan length /
		4125	#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /!< 0x00100000 /
		4126	#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /!< 0x00200000 /
		4127	#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /!< 0x00400000 /
		4128	#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /!< 0x00800000 /
2	mjames	4129
		4130	/***************** Bit definition for ADC_SQR2 register *****************/
5	mjames	4131	#define ADC_SQR2_SQ7_Pos (0U)
		4132	#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /!< 0x0000001F /
		4133	#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /!< ADC group regular sequencer rank 7 /
		4134	#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /!< 0x00000001 /
		4135	#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /!< 0x00000002 /
		4136	#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /!< 0x00000004 /
		4137	#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /!< 0x00000008 /
		4138	#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /!< 0x00000010 /
2	mjames	4139
5	mjames	4140	#define ADC_SQR2_SQ8_Pos (5U)
		4141	#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /!< 0x000003E0 /
		4142	#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /!< ADC group regular sequencer rank 8 /
		4143	#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /!< 0x00000020 /
		4144	#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /!< 0x00000040 /
		4145	#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /!< 0x00000080 /
		4146	#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /!< 0x00000100 /
		4147	#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /!< 0x00000200 /
2	mjames	4148
5	mjames	4149	#define ADC_SQR2_SQ9_Pos (10U)
		4150	#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /!< 0x00007C00 /
		4151	#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /!< ADC group regular sequencer rank 9 /
		4152	#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /!< 0x00000400 /
		4153	#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /!< 0x00000800 /
		4154	#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /!< 0x00001000 /
		4155	#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /!< 0x00002000 /
		4156	#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /!< 0x00004000 /
2	mjames	4157
5	mjames	4158	#define ADC_SQR2_SQ10_Pos (15U)
		4159	#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /!< 0x000F8000 /
		4160	#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /!< ADC group regular sequencer rank 10 /
		4161	#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /!< 0x00008000 /
		4162	#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /!< 0x00010000 /
		4163	#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /!< 0x00020000 /
		4164	#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /!< 0x00040000 /
		4165	#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /!< 0x00080000 /
2	mjames	4166
5	mjames	4167	#define ADC_SQR2_SQ11_Pos (20U)
		4168	#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /!< 0x01F00000 /
		4169	#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /!< ADC group regular sequencer rank 1 /
		4170	#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /!< 0x00100000 /
		4171	#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /!< 0x00200000 /
		4172	#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /!< 0x00400000 /
		4173	#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /!< 0x00800000 /
		4174	#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /!< 0x01000000 /
2	mjames	4175
5	mjames	4176	#define ADC_SQR2_SQ12_Pos (25U)
		4177	#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /!< 0x3E000000 /
		4178	#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /!< ADC group regular sequencer rank 12 /
		4179	#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /!< 0x02000000 /
		4180	#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /!< 0x04000000 /
		4181	#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /!< 0x08000000 /
		4182	#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /!< 0x10000000 /
		4183	#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /!< 0x20000000 /
2	mjames	4184
		4185	/***************** Bit definition for ADC_SQR3 register *****************/
5	mjames	4186	#define ADC_SQR3_SQ1_Pos (0U)
		4187	#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /!< 0x0000001F /
		4188	#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /!< ADC group regular sequencer rank 1 /
		4189	#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /!< 0x00000001 /
		4190	#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /!< 0x00000002 /
		4191	#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /!< 0x00000004 /
		4192	#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /!< 0x00000008 /
		4193	#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /!< 0x00000010 /
2	mjames	4194
5	mjames	4195	#define ADC_SQR3_SQ2_Pos (5U)
		4196	#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /!< 0x000003E0 /
		4197	#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /!< ADC group regular sequencer rank 2 /
		4198	#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /!< 0x00000020 /
		4199	#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /!< 0x00000040 /
		4200	#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /!< 0x00000080 /
		4201	#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /!< 0x00000100 /
		4202	#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /!< 0x00000200 /
2	mjames	4203
5	mjames	4204	#define ADC_SQR3_SQ3_Pos (10U)
		4205	#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /!< 0x00007C00 /
		4206	#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /!< ADC group regular sequencer rank 3 /
		4207	#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /!< 0x00000400 /
		4208	#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /!< 0x00000800 /
		4209	#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /!< 0x00001000 /
		4210	#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /!< 0x00002000 /
		4211	#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /!< 0x00004000 /
2	mjames	4212
5	mjames	4213	#define ADC_SQR3_SQ4_Pos (15U)
		4214	#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /!< 0x000F8000 /
		4215	#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /!< ADC group regular sequencer rank 4 /
		4216	#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /!< 0x00008000 /
		4217	#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /!< 0x00010000 /
		4218	#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /!< 0x00020000 /
		4219	#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /!< 0x00040000 /
		4220	#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /!< 0x00080000 /
2	mjames	4221
5	mjames	4222	#define ADC_SQR3_SQ5_Pos (20U)
		4223	#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /!< 0x01F00000 /
		4224	#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /!< ADC group regular sequencer rank 5 /
		4225	#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /!< 0x00100000 /
		4226	#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /!< 0x00200000 /
		4227	#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /!< 0x00400000 /
		4228	#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /!< 0x00800000 /
		4229	#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /!< 0x01000000 /
2	mjames	4230
5	mjames	4231	#define ADC_SQR3_SQ6_Pos (25U)
		4232	#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /!< 0x3E000000 /
		4233	#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /!< ADC group regular sequencer rank 6 /
		4234	#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /!< 0x02000000 /
		4235	#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /!< 0x04000000 /
		4236	#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /!< 0x08000000 /
		4237	#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /!< 0x10000000 /
		4238	#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /!< 0x20000000 /
2	mjames	4239
		4240	/***************** Bit definition for ADC_JSQR register *****************/
5	mjames	4241	#define ADC_JSQR_JSQ1_Pos (0U)
		4242	#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /!< 0x0000001F /
		4243	#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /!< ADC group injected sequencer rank 1 /
		4244	#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /!< 0x00000001 /
		4245	#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /!< 0x00000002 /
		4246	#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /!< 0x00000004 /
		4247	#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /!< 0x00000008 /
		4248	#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /!< 0x00000010 /
2	mjames	4249
5	mjames	4250	#define ADC_JSQR_JSQ2_Pos (5U)
		4251	#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /!< 0x000003E0 /
		4252	#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /!< ADC group injected sequencer rank 2 /
		4253	#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /!< 0x00000020 /
		4254	#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /!< 0x00000040 /
		4255	#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /!< 0x00000080 /
		4256	#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /!< 0x00000100 /
		4257	#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /!< 0x00000200 /
2	mjames	4258
5	mjames	4259	#define ADC_JSQR_JSQ3_Pos (10U)
		4260	#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /!< 0x00007C00 /
		4261	#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /!< ADC group injected sequencer rank 3 /
		4262	#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /!< 0x00000400 /
		4263	#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /!< 0x00000800 /
		4264	#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /!< 0x00001000 /
		4265	#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /!< 0x00002000 /
		4266	#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /!< 0x00004000 /
2	mjames	4267
5	mjames	4268	#define ADC_JSQR_JSQ4_Pos (15U)
		4269	#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /!< 0x000F8000 /
		4270	#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /!< ADC group injected sequencer rank 4 /
		4271	#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /!< 0x00008000 /
		4272	#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /!< 0x00010000 /
		4273	#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /!< 0x00020000 /
		4274	#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /!< 0x00040000 /
		4275	#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /!< 0x00080000 /
2	mjames	4276
5	mjames	4277	#define ADC_JSQR_JL_Pos (20U)
		4278	#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /!< 0x00300000 /
		4279	#define ADC_JSQR_JL ADC_JSQR_JL_Msk /!< ADC group injected sequencer scan length /
		4280	#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /!< 0x00100000 /
		4281	#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /!< 0x00200000 /
2	mjames	4282
		4283	/***************** Bit definition for ADC_JDR1 register *****************/
5	mjames	4284	#define ADC_JDR1_JDATA_Pos (0U)
		4285	#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /!< 0x0000FFFF /
		4286	#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /!< ADC group injected sequencer rank 1 conversion data /
2	mjames	4287
		4288	/***************** Bit definition for ADC_JDR2 register *****************/
5	mjames	4289	#define ADC_JDR2_JDATA_Pos (0U)
		4290	#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /!< 0x0000FFFF /
		4291	#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /!< ADC group injected sequencer rank 2 conversion data /
2	mjames	4292
		4293	/***************** Bit definition for ADC_JDR3 register *****************/
5	mjames	4294	#define ADC_JDR3_JDATA_Pos (0U)
		4295	#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /!< 0x0000FFFF /
		4296	#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /!< ADC group injected sequencer rank 3 conversion data /
2	mjames	4297
		4298	/***************** Bit definition for ADC_JDR4 register *****************/
5	mjames	4299	#define ADC_JDR4_JDATA_Pos (0U)
		4300	#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /!< 0x0000FFFF /
		4301	#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /!< ADC group injected sequencer rank 4 conversion data /
2	mjames	4302
		4303	/****************** Bit definition for ADC_DR register ******************/
5	mjames	4304	#define ADC_DR_DATA_Pos (0U)
		4305	#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /!< 0x0000FFFF /
		4306	#define ADC_DR_DATA ADC_DR_DATA_Msk /!< ADC group regular conversion data /
2	mjames	4307	/******************************************************************************/
		4308	/* */
		4309	/* Digital to Analog Converter */
		4310	/* */
		4311	/******************************************************************************/
		4312
		4313	/****************** Bit definition for DAC_CR register ******************/
5	mjames	4314	#define DAC_CR_EN1_Pos (0U)
		4315	#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /!< 0x00000001 /
		4316	#define DAC_CR_EN1 DAC_CR_EN1_Msk /!< DAC channel1 enable /
		4317	#define DAC_CR_BOFF1_Pos (1U)
		4318	#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /!< 0x00000002 /
		4319	#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /!< DAC channel1 output buffer disable /
		4320	#define DAC_CR_TEN1_Pos (2U)
		4321	#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /!< 0x00000004 /
		4322	#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /!< DAC channel1 Trigger enable /
2	mjames	4323
5	mjames	4324	#define DAC_CR_TSEL1_Pos (3U)
		4325	#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /!< 0x00000038 /
		4326	#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
		4327	#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /!< 0x00000008 /
		4328	#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /!< 0x00000010 /
		4329	#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /!< 0x00000020 /
2	mjames	4330
5	mjames	4331	#define DAC_CR_WAVE1_Pos (6U)
		4332	#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /!< 0x000000C0 /
		4333	#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
		4334	#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /!< 0x00000040 /
		4335	#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /!< 0x00000080 /
2	mjames	4336
5	mjames	4337	#define DAC_CR_MAMP1_Pos (8U)
		4338	#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /!< 0x00000F00 /
		4339	#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
		4340	#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /!< 0x00000100 /
		4341	#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /!< 0x00000200 /
		4342	#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /!< 0x00000400 /
		4343	#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /!< 0x00000800 /
2	mjames	4344
5	mjames	4345	#define DAC_CR_DMAEN1_Pos (12U)
		4346	#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /!< 0x00001000 /
		4347	#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /!< DAC channel1 DMA enable /
		4348	#define DAC_CR_EN2_Pos (16U)
		4349	#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /!< 0x00010000 /
		4350	#define DAC_CR_EN2 DAC_CR_EN2_Msk /!< DAC channel2 enable /
		4351	#define DAC_CR_BOFF2_Pos (17U)
		4352	#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /!< 0x00020000 /
		4353	#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /!< DAC channel2 output buffer disable /
		4354	#define DAC_CR_TEN2_Pos (18U)
		4355	#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /!< 0x00040000 /
		4356	#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /!< DAC channel2 Trigger enable /
2	mjames	4357
5	mjames	4358	#define DAC_CR_TSEL2_Pos (19U)
		4359	#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /!< 0x00380000 /
		4360	#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
		4361	#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /!< 0x00080000 /
		4362	#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /!< 0x00100000 /
		4363	#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /!< 0x00200000 /
2	mjames	4364
5	mjames	4365	#define DAC_CR_WAVE2_Pos (22U)
		4366	#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /!< 0x00C00000 /
		4367	#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
		4368	#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /!< 0x00400000 /
		4369	#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /!< 0x00800000 /
2	mjames	4370
5	mjames	4371	#define DAC_CR_MAMP2_Pos (24U)
		4372	#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /!< 0x0F000000 /
		4373	#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
		4374	#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /!< 0x01000000 /
		4375	#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /!< 0x02000000 /
		4376	#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /!< 0x04000000 /
		4377	#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /!< 0x08000000 /
2	mjames	4378
5	mjames	4379	#define DAC_CR_DMAEN2_Pos (28U)
		4380	#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /!< 0x10000000 /
		4381	#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /!< DAC channel2 DMA enabled /
2	mjames	4382
5	mjames	4383	#define DAC_CR_DMAUDRIE1_Pos (13U)
		4384	#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /!< 0x00002000 /
		4385	#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /!< DAC channel1 DMA underrun interrupt enable /
		4386	#define DAC_CR_DMAUDRIE2_Pos (29U)
		4387	#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /!< 0x20000000 /
		4388	#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /!< DAC channel2 DMA underrun interrupt enable /
2	mjames	4389
		4390	/*************** Bit definition for DAC_SWTRIGR register ****************/
5	mjames	4391	#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
		4392	#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /!< 0x00000001 /
		4393	#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /!< DAC channel1 software trigger /
		4394	#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
		4395	#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /!< 0x00000002 /
		4396	#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /!< DAC channel2 software trigger /
2	mjames	4397
		4398	/*************** Bit definition for DAC_DHR12R1 register ****************/
5	mjames	4399	#define DAC_DHR12R1_DACC1DHR_Pos (0U)
		4400	#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /!< 0x00000FFF /
		4401	#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /!< DAC channel1 12-bit Right aligned data /
2	mjames	4402
		4403	/*************** Bit definition for DAC_DHR12L1 register ****************/
5	mjames	4404	#define DAC_DHR12L1_DACC1DHR_Pos (4U)
		4405	#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /!< 0x0000FFF0 /
		4406	#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /!< DAC channel1 12-bit Left aligned data /
2	mjames	4407
		4408	/**************** Bit definition for DAC_DHR8R1 register ****************/
5	mjames	4409	#define DAC_DHR8R1_DACC1DHR_Pos (0U)
		4410	#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /!< 0x000000FF /
		4411	#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /!< DAC channel1 8-bit Right aligned data /
2	mjames	4412
		4413	/*************** Bit definition for DAC_DHR12R2 register ****************/
5	mjames	4414	#define DAC_DHR12R2_DACC2DHR_Pos (0U)
		4415	#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /!< 0x00000FFF /
		4416	#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /!< DAC channel2 12-bit Right aligned data /
2	mjames	4417
		4418	/*************** Bit definition for DAC_DHR12L2 register ****************/
5	mjames	4419	#define DAC_DHR12L2_DACC2DHR_Pos (4U)
		4420	#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /!< 0x0000FFF0 /
		4421	#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /!< DAC channel2 12-bit Left aligned data /
2	mjames	4422
		4423	/**************** Bit definition for DAC_DHR8R2 register ****************/
5	mjames	4424	#define DAC_DHR8R2_DACC2DHR_Pos (0U)
		4425	#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /!< 0x000000FF /
		4426	#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /!< DAC channel2 8-bit Right aligned data /
2	mjames	4427
		4428	/*************** Bit definition for DAC_DHR12RD register ****************/
5	mjames	4429	#define DAC_DHR12RD_DACC1DHR_Pos (0U)
		4430	#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /!< 0x00000FFF /
		4431	#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /!< DAC channel1 12-bit Right aligned data /
		4432	#define DAC_DHR12RD_DACC2DHR_Pos (16U)
		4433	#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /!< 0x0FFF0000 /
		4434	#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /!< DAC channel2 12-bit Right aligned data /
2	mjames	4435
		4436	/*************** Bit definition for DAC_DHR12LD register ****************/
5	mjames	4437	#define DAC_DHR12LD_DACC1DHR_Pos (4U)
		4438	#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /!< 0x0000FFF0 /
		4439	#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /!< DAC channel1 12-bit Left aligned data /
		4440	#define DAC_DHR12LD_DACC2DHR_Pos (20U)
		4441	#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /!< 0xFFF00000 /
		4442	#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /!< DAC channel2 12-bit Left aligned data /
2	mjames	4443
		4444	/**************** Bit definition for DAC_DHR8RD register ****************/
5	mjames	4445	#define DAC_DHR8RD_DACC1DHR_Pos (0U)
		4446	#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /!< 0x000000FF /
		4447	#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /!< DAC channel1 8-bit Right aligned data /
		4448	#define DAC_DHR8RD_DACC2DHR_Pos (8U)
		4449	#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /!< 0x0000FF00 /
		4450	#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /!< DAC channel2 8-bit Right aligned data /
2	mjames	4451
		4452	/***************** Bit definition for DAC_DOR1 register *****************/
5	mjames	4453	#define DAC_DOR1_DACC1DOR_Pos (0U)
		4454	#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /!< 0x00000FFF /
		4455	#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /!< DAC channel1 data output /
2	mjames	4456
		4457	/***************** Bit definition for DAC_DOR2 register *****************/
5	mjames	4458	#define DAC_DOR2_DACC2DOR_Pos (0U)
		4459	#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /!< 0x00000FFF /
		4460	#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /!< DAC channel2 data output /
2	mjames	4461
		4462	/****************** Bit definition for DAC_SR register ******************/
5	mjames	4463	#define DAC_SR_DMAUDR1_Pos (13U)
		4464	#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /!< 0x00002000 /
		4465	#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /!< DAC channel1 DMA underrun flag /
		4466	#define DAC_SR_DMAUDR2_Pos (29U)
		4467	#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /!< 0x20000000 /
		4468	#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /!< DAC channel2 DMA underrun flag /
2	mjames	4469
		4470	/******************************************************************************/
		4471	/* */
		4472	/* CEC */
		4473	/* */
		4474	/******************************************************************************/
		4475	/****************** Bit definition for CEC_CFGR register ****************/
5	mjames	4476	#define CEC_CFGR_PE_Pos (0U)
		4477	#define CEC_CFGR_PE_Msk (0x1U << CEC_CFGR_PE_Pos) /!< 0x00000001 /
		4478	#define CEC_CFGR_PE CEC_CFGR_PE_Msk /!< Peripheral Enable /
		4479	#define CEC_CFGR_IE_Pos (1U)
		4480	#define CEC_CFGR_IE_Msk (0x1U << CEC_CFGR_IE_Pos) /!< 0x00000002 /
		4481	#define CEC_CFGR_IE CEC_CFGR_IE_Msk /!< Interrupt Enable /
		4482	#define CEC_CFGR_BTEM_Pos (2U)
		4483	#define CEC_CFGR_BTEM_Msk (0x1U << CEC_CFGR_BTEM_Pos) /!< 0x00000004 /
		4484	#define CEC_CFGR_BTEM CEC_CFGR_BTEM_Msk /!< Bit Timing Error Mode /
		4485	#define CEC_CFGR_BPEM_Pos (3U)
		4486	#define CEC_CFGR_BPEM_Msk (0x1U << CEC_CFGR_BPEM_Pos) /!< 0x00000008 /
		4487	#define CEC_CFGR_BPEM CEC_CFGR_BPEM_Msk /!< Bit Period Error Mode /
2	mjames	4488
		4489	/****************** Bit definition for CEC_OAR register ****************/
5	mjames	4490	#define CEC_OAR_OA_Pos (0U)
		4491	#define CEC_OAR_OA_Msk (0xFU << CEC_OAR_OA_Pos) /!< 0x0000000F /
		4492	#define CEC_OAR_OA CEC_OAR_OA_Msk /!< OA[3:0]: Own Address /
		4493	#define CEC_OAR_OA_0 (0x1U << CEC_OAR_OA_Pos) /!< 0x00000001 /
		4494	#define CEC_OAR_OA_1 (0x2U << CEC_OAR_OA_Pos) /!< 0x00000002 /
		4495	#define CEC_OAR_OA_2 (0x4U << CEC_OAR_OA_Pos) /!< 0x00000004 /
		4496	#define CEC_OAR_OA_3 (0x8U << CEC_OAR_OA_Pos) /!< 0x00000008 /
2	mjames	4497
		4498	/****************** Bit definition for CEC_PRES register ****************/
5	mjames	4499	#define CEC_PRES_PRES_Pos (0U)
		4500	#define CEC_PRES_PRES_Msk (0x3FFFU << CEC_PRES_PRES_Pos) /!< 0x00003FFF /
		4501	#define CEC_PRES_PRES CEC_PRES_PRES_Msk /!< Prescaler Counter Value /
2	mjames	4502
		4503	/****************** Bit definition for CEC_ESR register ****************/
5	mjames	4504	#define CEC_ESR_BTE_Pos (0U)
		4505	#define CEC_ESR_BTE_Msk (0x1U << CEC_ESR_BTE_Pos) /!< 0x00000001 /
		4506	#define CEC_ESR_BTE CEC_ESR_BTE_Msk /!< Bit Timing Error /
		4507	#define CEC_ESR_BPE_Pos (1U)
		4508	#define CEC_ESR_BPE_Msk (0x1U << CEC_ESR_BPE_Pos) /!< 0x00000002 /
		4509	#define CEC_ESR_BPE CEC_ESR_BPE_Msk /!< Bit Period Error /
		4510	#define CEC_ESR_RBTFE_Pos (2U)
		4511	#define CEC_ESR_RBTFE_Msk (0x1U << CEC_ESR_RBTFE_Pos) /!< 0x00000004 /
		4512	#define CEC_ESR_RBTFE CEC_ESR_RBTFE_Msk /!< Rx Block Transfer Finished Error /
		4513	#define CEC_ESR_SBE_Pos (3U)
		4514	#define CEC_ESR_SBE_Msk (0x1U << CEC_ESR_SBE_Pos) /!< 0x00000008 /
		4515	#define CEC_ESR_SBE CEC_ESR_SBE_Msk /!< Start Bit Error /
		4516	#define CEC_ESR_ACKE_Pos (4U)
		4517	#define CEC_ESR_ACKE_Msk (0x1U << CEC_ESR_ACKE_Pos) /!< 0x00000010 /
		4518	#define CEC_ESR_ACKE CEC_ESR_ACKE_Msk /!< Block Acknowledge Error /
		4519	#define CEC_ESR_LINE_Pos (5U)
		4520	#define CEC_ESR_LINE_Msk (0x1U << CEC_ESR_LINE_Pos) /!< 0x00000020 /
		4521	#define CEC_ESR_LINE CEC_ESR_LINE_Msk /!< Line Error /
		4522	#define CEC_ESR_TBTFE_Pos (6U)
		4523	#define CEC_ESR_TBTFE_Msk (0x1U << CEC_ESR_TBTFE_Pos) /!< 0x00000040 /
		4524	#define CEC_ESR_TBTFE CEC_ESR_TBTFE_Msk /!< Tx Block Transfer Finished Error /
2	mjames	4525
		4526	/****************** Bit definition for CEC_CSR register ****************/
5	mjames	4527	#define CEC_CSR_TSOM_Pos (0U)
		4528	#define CEC_CSR_TSOM_Msk (0x1U << CEC_CSR_TSOM_Pos) /!< 0x00000001 /
		4529	#define CEC_CSR_TSOM CEC_CSR_TSOM_Msk /!< Tx Start Of Message /
		4530	#define CEC_CSR_TEOM_Pos (1U)
		4531	#define CEC_CSR_TEOM_Msk (0x1U << CEC_CSR_TEOM_Pos) /!< 0x00000002 /
		4532	#define CEC_CSR_TEOM CEC_CSR_TEOM_Msk /!< Tx End Of Message /
		4533	#define CEC_CSR_TERR_Pos (2U)
		4534	#define CEC_CSR_TERR_Msk (0x1U << CEC_CSR_TERR_Pos) /!< 0x00000004 /
		4535	#define CEC_CSR_TERR CEC_CSR_TERR_Msk /!< Tx Error /
		4536	#define CEC_CSR_TBTRF_Pos (3U)
		4537	#define CEC_CSR_TBTRF_Msk (0x1U << CEC_CSR_TBTRF_Pos) /!< 0x00000008 /
		4538	#define CEC_CSR_TBTRF CEC_CSR_TBTRF_Msk /!< Tx Byte Transfer Request or Block Transfer Finished /
		4539	#define CEC_CSR_RSOM_Pos (4U)
		4540	#define CEC_CSR_RSOM_Msk (0x1U << CEC_CSR_RSOM_Pos) /!< 0x00000010 /
		4541	#define CEC_CSR_RSOM CEC_CSR_RSOM_Msk /!< Rx Start Of Message /
		4542	#define CEC_CSR_REOM_Pos (5U)
		4543	#define CEC_CSR_REOM_Msk (0x1U << CEC_CSR_REOM_Pos) /!< 0x00000020 /
		4544	#define CEC_CSR_REOM CEC_CSR_REOM_Msk /!< Rx End Of Message /
		4545	#define CEC_CSR_RERR_Pos (6U)
		4546	#define CEC_CSR_RERR_Msk (0x1U << CEC_CSR_RERR_Pos) /!< 0x00000040 /
		4547	#define CEC_CSR_RERR CEC_CSR_RERR_Msk /!< Rx Error /
		4548	#define CEC_CSR_RBTF_Pos (7U)
		4549	#define CEC_CSR_RBTF_Msk (0x1U << CEC_CSR_RBTF_Pos) /!< 0x00000080 /
		4550	#define CEC_CSR_RBTF CEC_CSR_RBTF_Msk /!< Rx Block Transfer Finished /
2	mjames	4551
		4552	/****************** Bit definition for CEC_TXD register ****************/
5	mjames	4553	#define CEC_TXD_TXD_Pos (0U)
		4554	#define CEC_TXD_TXD_Msk (0xFFU << CEC_TXD_TXD_Pos) /!< 0x000000FF /
		4555	#define CEC_TXD_TXD CEC_TXD_TXD_Msk /!< Tx Data register /
2	mjames	4556
		4557	/****************** Bit definition for CEC_RXD register ****************/
5	mjames	4558	#define CEC_RXD_RXD_Pos (0U)
		4559	#define CEC_RXD_RXD_Msk (0xFFU << CEC_RXD_RXD_Pos) /!< 0x000000FF /
		4560	#define CEC_RXD_RXD CEC_RXD_RXD_Msk /!< Rx Data register /
2	mjames	4561
		4562	/*****************************************************************************/
		4563	/* */
		4564	/* Timers (TIM) */
		4565	/* */
		4566	/*****************************************************************************/
		4567	/***************** Bit definition for TIM_CR1 register *****************/
5	mjames	4568	#define TIM_CR1_CEN_Pos (0U)
		4569	#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /!< 0x00000001 /
		4570	#define TIM_CR1_CEN TIM_CR1_CEN_Msk /!<Counter enable /
		4571	#define TIM_CR1_UDIS_Pos (1U)
		4572	#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /!< 0x00000002 /
		4573	#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /!<Update disable /
		4574	#define TIM_CR1_URS_Pos (2U)
		4575	#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /!< 0x00000004 /
		4576	#define TIM_CR1_URS TIM_CR1_URS_Msk /!<Update request source /
		4577	#define TIM_CR1_OPM_Pos (3U)
		4578	#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /!< 0x00000008 /
		4579	#define TIM_CR1_OPM TIM_CR1_OPM_Msk /!<One pulse mode /
		4580	#define TIM_CR1_DIR_Pos (4U)
		4581	#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /!< 0x00000010 /
		4582	#define TIM_CR1_DIR TIM_CR1_DIR_Msk /!<Direction /
2	mjames	4583
5	mjames	4584	#define TIM_CR1_CMS_Pos (5U)
		4585	#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /!< 0x00000060 /
		4586	#define TIM_CR1_CMS TIM_CR1_CMS_Msk /!<CMS[1:0] bits (Center-aligned mode selection) /
		4587	#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /!< 0x00000020 /
		4588	#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /!< 0x00000040 /
2	mjames	4589
5	mjames	4590	#define TIM_CR1_ARPE_Pos (7U)
		4591	#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /!< 0x00000080 /
		4592	#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /!<Auto-reload preload enable /
2	mjames	4593
5	mjames	4594	#define TIM_CR1_CKD_Pos (8U)
		4595	#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /!< 0x00000300 /
		4596	#define TIM_CR1_CKD TIM_CR1_CKD_Msk /!<CKD[1:0] bits (clock division) /
		4597	#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /!< 0x00000100 /
		4598	#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /!< 0x00000200 /
2	mjames	4599
		4600	/***************** Bit definition for TIM_CR2 register *****************/
5	mjames	4601	#define TIM_CR2_CCPC_Pos (0U)
		4602	#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /!< 0x00000001 /
		4603	#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /!<Capture/Compare Preloaded Control /
		4604	#define TIM_CR2_CCUS_Pos (2U)
		4605	#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /!< 0x00000004 /
		4606	#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /!<Capture/Compare Control Update Selection /
		4607	#define TIM_CR2_CCDS_Pos (3U)
		4608	#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /!< 0x00000008 /
		4609	#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /!<Capture/Compare DMA Selection /
2	mjames	4610
5	mjames	4611	#define TIM_CR2_MMS_Pos (4U)
		4612	#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /!< 0x00000070 /
		4613	#define TIM_CR2_MMS TIM_CR2_MMS_Msk /!<MMS[2:0] bits (Master Mode Selection) /
		4614	#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /!< 0x00000010 /
		4615	#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /!< 0x00000020 /
		4616	#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /!< 0x00000040 /
2	mjames	4617
5	mjames	4618	#define TIM_CR2_TI1S_Pos (7U)
		4619	#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /!< 0x00000080 /
		4620	#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /!<TI1 Selection /
		4621	#define TIM_CR2_OIS1_Pos (8U)
		4622	#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /!< 0x00000100 /
		4623	#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /!<Output Idle state 1 (OC1 output) /
		4624	#define TIM_CR2_OIS1N_Pos (9U)
		4625	#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /!< 0x00000200 /
		4626	#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /!<Output Idle state 1 (OC1N output) /
		4627	#define TIM_CR2_OIS2_Pos (10U)
		4628	#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /!< 0x00000400 /
		4629	#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /!<Output Idle state 2 (OC2 output) /
		4630	#define TIM_CR2_OIS2N_Pos (11U)
		4631	#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /!< 0x00000800 /
		4632	#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /!<Output Idle state 2 (OC2N output) /
		4633	#define TIM_CR2_OIS3_Pos (12U)
		4634	#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /!< 0x00001000 /
		4635	#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /!<Output Idle state 3 (OC3 output) /
		4636	#define TIM_CR2_OIS3N_Pos (13U)
		4637	#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /!< 0x00002000 /
		4638	#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /!<Output Idle state 3 (OC3N output) /
		4639	#define TIM_CR2_OIS4_Pos (14U)
		4640	#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /!< 0x00004000 /
		4641	#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /!<Output Idle state 4 (OC4 output) /
2	mjames	4642
		4643	/***************** Bit definition for TIM_SMCR register ****************/
5	mjames	4644	#define TIM_SMCR_SMS_Pos (0U)
		4645	#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /!< 0x00000007 /
		4646	#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /!<SMS[2:0] bits (Slave mode selection) /
		4647	#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /!< 0x00000001 /
		4648	#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /!< 0x00000002 /
		4649	#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /!< 0x00000004 /
2	mjames	4650
5	mjames	4651	#define TIM_SMCR_OCCS_Pos (3U)
		4652	#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /!< 0x00000008 /
		4653	#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /!< OCREF clear selection /
2	mjames	4654
5	mjames	4655	#define TIM_SMCR_TS_Pos (4U)
		4656	#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /!< 0x00000070 /
		4657	#define TIM_SMCR_TS TIM_SMCR_TS_Msk /!<TS[2:0] bits (Trigger selection) /
		4658	#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /!< 0x00000010 /
		4659	#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /!< 0x00000020 /
		4660	#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /!< 0x00000040 /
2	mjames	4661
5	mjames	4662	#define TIM_SMCR_MSM_Pos (7U)
		4663	#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /!< 0x00000080 /
		4664	#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /!<Master/slave mode /
2	mjames	4665
5	mjames	4666	#define TIM_SMCR_ETF_Pos (8U)
		4667	#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /!< 0x00000F00 /
		4668	#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /!<ETF[3:0] bits (External trigger filter) /
		4669	#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /!< 0x00000100 /
		4670	#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /!< 0x00000200 /
		4671	#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /!< 0x00000400 /
		4672	#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /!< 0x00000800 /
2	mjames	4673
5	mjames	4674	#define TIM_SMCR_ETPS_Pos (12U)
		4675	#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /!< 0x00003000 /
		4676	#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /!<ETPS[1:0] bits (External trigger prescaler) /
		4677	#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /!< 0x00001000 /
		4678	#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /!< 0x00002000 /
2	mjames	4679
5	mjames	4680	#define TIM_SMCR_ECE_Pos (14U)
		4681	#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /!< 0x00004000 /
		4682	#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /!<External clock enable /
		4683	#define TIM_SMCR_ETP_Pos (15U)
		4684	#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /!< 0x00008000 /
		4685	#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /!<External trigger polarity /
2	mjames	4686
		4687	/***************** Bit definition for TIM_DIER register ****************/
5	mjames	4688	#define TIM_DIER_UIE_Pos (0U)
		4689	#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /!< 0x00000001 /
		4690	#define TIM_DIER_UIE TIM_DIER_UIE_Msk /!<Update interrupt enable /
		4691	#define TIM_DIER_CC1IE_Pos (1U)
		4692	#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /!< 0x00000002 /
		4693	#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /!<Capture/Compare 1 interrupt enable /
		4694	#define TIM_DIER_CC2IE_Pos (2U)
		4695	#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /!< 0x00000004 /
		4696	#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /!<Capture/Compare 2 interrupt enable /
		4697	#define TIM_DIER_CC3IE_Pos (3U)
		4698	#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /!< 0x00000008 /
		4699	#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /!<Capture/Compare 3 interrupt enable /
		4700	#define TIM_DIER_CC4IE_Pos (4U)
		4701	#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /!< 0x00000010 /
		4702	#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /!<Capture/Compare 4 interrupt enable /
		4703	#define TIM_DIER_COMIE_Pos (5U)
		4704	#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /!< 0x00000020 /
		4705	#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /!<COM interrupt enable /
		4706	#define TIM_DIER_TIE_Pos (6U)
		4707	#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /!< 0x00000040 /
		4708	#define TIM_DIER_TIE TIM_DIER_TIE_Msk /!<Trigger interrupt enable /
		4709	#define TIM_DIER_BIE_Pos (7U)
		4710	#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /!< 0x00000080 /
		4711	#define TIM_DIER_BIE TIM_DIER_BIE_Msk /!<Break interrupt enable /
		4712	#define TIM_DIER_UDE_Pos (8U)
		4713	#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /!< 0x00000100 /
		4714	#define TIM_DIER_UDE TIM_DIER_UDE_Msk /!<Update DMA request enable /
		4715	#define TIM_DIER_CC1DE_Pos (9U)
		4716	#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /!< 0x00000200 /
		4717	#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /!<Capture/Compare 1 DMA request enable /
		4718	#define TIM_DIER_CC2DE_Pos (10U)
		4719	#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /!< 0x00000400 /
		4720	#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /!<Capture/Compare 2 DMA request enable /
		4721	#define TIM_DIER_CC3DE_Pos (11U)
		4722	#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /!< 0x00000800 /
		4723	#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /!<Capture/Compare 3 DMA request enable /
		4724	#define TIM_DIER_CC4DE_Pos (12U)
		4725	#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /!< 0x00001000 /
		4726	#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /!<Capture/Compare 4 DMA request enable /
		4727	#define TIM_DIER_COMDE_Pos (13U)
		4728	#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /!< 0x00002000 /
		4729	#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /!<COM DMA request enable /
		4730	#define TIM_DIER_TDE_Pos (14U)
		4731	#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /!< 0x00004000 /
		4732	#define TIM_DIER_TDE TIM_DIER_TDE_Msk /!<Trigger DMA request enable /
2	mjames	4733
		4734	/****************** Bit definition for TIM_SR register *****************/
5	mjames	4735	#define TIM_SR_UIF_Pos (0U)
		4736	#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /!< 0x00000001 /
		4737	#define TIM_SR_UIF TIM_SR_UIF_Msk /!<Update interrupt Flag /
		4738	#define TIM_SR_CC1IF_Pos (1U)
		4739	#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /!< 0x00000002 /
		4740	#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /!<Capture/Compare 1 interrupt Flag /
		4741	#define TIM_SR_CC2IF_Pos (2U)
		4742	#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /!< 0x00000004 /
		4743	#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /!<Capture/Compare 2 interrupt Flag /
		4744	#define TIM_SR_CC3IF_Pos (3U)
		4745	#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /!< 0x00000008 /
		4746	#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /!<Capture/Compare 3 interrupt Flag /
		4747	#define TIM_SR_CC4IF_Pos (4U)
		4748	#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /!< 0x00000010 /
		4749	#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /!<Capture/Compare 4 interrupt Flag /
		4750	#define TIM_SR_COMIF_Pos (5U)
		4751	#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /!< 0x00000020 /
		4752	#define TIM_SR_COMIF TIM_SR_COMIF_Msk /!<COM interrupt Flag /
		4753	#define TIM_SR_TIF_Pos (6U)
		4754	#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /!< 0x00000040 /
		4755	#define TIM_SR_TIF TIM_SR_TIF_Msk /!<Trigger interrupt Flag /
		4756	#define TIM_SR_BIF_Pos (7U)
		4757	#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /!< 0x00000080 /
		4758	#define TIM_SR_BIF TIM_SR_BIF_Msk /!<Break interrupt Flag /
		4759	#define TIM_SR_CC1OF_Pos (9U)
		4760	#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /!< 0x00000200 /
		4761	#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /!<Capture/Compare 1 Overcapture Flag /
		4762	#define TIM_SR_CC2OF_Pos (10U)
		4763	#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /!< 0x00000400 /
		4764	#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /!<Capture/Compare 2 Overcapture Flag /
		4765	#define TIM_SR_CC3OF_Pos (11U)
		4766	#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /!< 0x00000800 /
		4767	#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /!<Capture/Compare 3 Overcapture Flag /
		4768	#define TIM_SR_CC4OF_Pos (12U)
		4769	#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /!< 0x00001000 /
		4770	#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /!<Capture/Compare 4 Overcapture Flag /
2	mjames	4771
		4772	/***************** Bit definition for TIM_EGR register *****************/
5	mjames	4773	#define TIM_EGR_UG_Pos (0U)
		4774	#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /!< 0x00000001 /
		4775	#define TIM_EGR_UG TIM_EGR_UG_Msk /!<Update Generation /
		4776	#define TIM_EGR_CC1G_Pos (1U)
		4777	#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /!< 0x00000002 /
		4778	#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /!<Capture/Compare 1 Generation /
		4779	#define TIM_EGR_CC2G_Pos (2U)
		4780	#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /!< 0x00000004 /
		4781	#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /!<Capture/Compare 2 Generation /
		4782	#define TIM_EGR_CC3G_Pos (3U)
		4783	#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /!< 0x00000008 /
		4784	#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /!<Capture/Compare 3 Generation /
		4785	#define TIM_EGR_CC4G_Pos (4U)
		4786	#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /!< 0x00000010 /
		4787	#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /!<Capture/Compare 4 Generation /
		4788	#define TIM_EGR_COMG_Pos (5U)
		4789	#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /!< 0x00000020 /
		4790	#define TIM_EGR_COMG TIM_EGR_COMG_Msk /!<Capture/Compare Control Update Generation /
		4791	#define TIM_EGR_TG_Pos (6U)
		4792	#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /!< 0x00000040 /
		4793	#define TIM_EGR_TG TIM_EGR_TG_Msk /!<Trigger Generation /
		4794	#define TIM_EGR_BG_Pos (7U)
		4795	#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /!< 0x00000080 /
		4796	#define TIM_EGR_BG TIM_EGR_BG_Msk /!<Break Generation /
2	mjames	4797
		4798	/**************** Bit definition for TIM_CCMR1 register ****************/
5	mjames	4799	#define TIM_CCMR1_CC1S_Pos (0U)
		4800	#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /!< 0x00000003 /
		4801	#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
		4802	#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /!< 0x00000001 /
		4803	#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /!< 0x00000002 /
2	mjames	4804
5	mjames	4805	#define TIM_CCMR1_OC1FE_Pos (2U)
		4806	#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /!< 0x00000004 /
		4807	#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /!<Output Compare 1 Fast enable /
		4808	#define TIM_CCMR1_OC1PE_Pos (3U)
		4809	#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /!< 0x00000008 /
		4810	#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /!<Output Compare 1 Preload enable /
2	mjames	4811
5	mjames	4812	#define TIM_CCMR1_OC1M_Pos (4U)
		4813	#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /!< 0x00000070 /
		4814	#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /!<OC1M[2:0] bits (Output Compare 1 Mode) /
		4815	#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /!< 0x00000010 /
		4816	#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /!< 0x00000020 /
		4817	#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /!< 0x00000040 /
2	mjames	4818
5	mjames	4819	#define TIM_CCMR1_OC1CE_Pos (7U)
		4820	#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /!< 0x00000080 /
		4821	#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /!<Output Compare 1Clear Enable /
2	mjames	4822
5	mjames	4823	#define TIM_CCMR1_CC2S_Pos (8U)
		4824	#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /!< 0x00000300 /
		4825	#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
		4826	#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /!< 0x00000100 /
		4827	#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /!< 0x00000200 /
2	mjames	4828
5	mjames	4829	#define TIM_CCMR1_OC2FE_Pos (10U)
		4830	#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /!< 0x00000400 /
		4831	#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /!<Output Compare 2 Fast enable /
		4832	#define TIM_CCMR1_OC2PE_Pos (11U)
		4833	#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /!< 0x00000800 /
		4834	#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /!<Output Compare 2 Preload enable /
2	mjames	4835
5	mjames	4836	#define TIM_CCMR1_OC2M_Pos (12U)
		4837	#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /!< 0x00007000 /
		4838	#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /!<OC2M[2:0] bits (Output Compare 2 Mode) /
		4839	#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /!< 0x00001000 /
		4840	#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /!< 0x00002000 /
		4841	#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /!< 0x00004000 /
2	mjames	4842
5	mjames	4843	#define TIM_CCMR1_OC2CE_Pos (15U)
		4844	#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /!< 0x00008000 /
		4845	#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /!<Output Compare 2 Clear Enable /
2	mjames	4846
		4847	/---------------------------------------------------------------------------/
		4848
5	mjames	4849	#define TIM_CCMR1_IC1PSC_Pos (2U)
		4850	#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /!< 0x0000000C /
		4851	#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
		4852	#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000004 /
		4853	#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000008 /
2	mjames	4854
5	mjames	4855	#define TIM_CCMR1_IC1F_Pos (4U)
		4856	#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /!< 0x000000F0 /
		4857	#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /!<IC1F[3:0] bits (Input Capture 1 Filter) /
		4858	#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /!< 0x00000010 /
		4859	#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /!< 0x00000020 /
		4860	#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /!< 0x00000040 /
		4861	#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /!< 0x00000080 /
2	mjames	4862
5	mjames	4863	#define TIM_CCMR1_IC2PSC_Pos (10U)
		4864	#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000C00 /
		4865	#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
		4866	#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000400 /
		4867	#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000800 /
2	mjames	4868
5	mjames	4869	#define TIM_CCMR1_IC2F_Pos (12U)
		4870	#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /!< 0x0000F000 /
		4871	#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /!<IC2F[3:0] bits (Input Capture 2 Filter) /
		4872	#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /!< 0x00001000 /
		4873	#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /!< 0x00002000 /
		4874	#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /!< 0x00004000 /
		4875	#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /!< 0x00008000 /
2	mjames	4876
		4877	/**************** Bit definition for TIM_CCMR2 register ****************/
5	mjames	4878	#define TIM_CCMR2_CC3S_Pos (0U)
		4879	#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /!< 0x00000003 /
		4880	#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
		4881	#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /!< 0x00000001 /
		4882	#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /!< 0x00000002 /
2	mjames	4883
5	mjames	4884	#define TIM_CCMR2_OC3FE_Pos (2U)
		4885	#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /!< 0x00000004 /
		4886	#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /!<Output Compare 3 Fast enable /
		4887	#define TIM_CCMR2_OC3PE_Pos (3U)
		4888	#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /!< 0x00000008 /
		4889	#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /!<Output Compare 3 Preload enable /
2	mjames	4890
5	mjames	4891	#define TIM_CCMR2_OC3M_Pos (4U)
		4892	#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /!< 0x00000070 /
		4893	#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /!<OC3M[2:0] bits (Output Compare 3 Mode) /
		4894	#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /!< 0x00000010 /
		4895	#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /!< 0x00000020 /
		4896	#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /!< 0x00000040 /
2	mjames	4897
5	mjames	4898	#define TIM_CCMR2_OC3CE_Pos (7U)
		4899	#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /!< 0x00000080 /
		4900	#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /!<Output Compare 3 Clear Enable /
2	mjames	4901
5	mjames	4902	#define TIM_CCMR2_CC4S_Pos (8U)
		4903	#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /!< 0x00000300 /
		4904	#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
		4905	#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /!< 0x00000100 /
		4906	#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /!< 0x00000200 /
2	mjames	4907
5	mjames	4908	#define TIM_CCMR2_OC4FE_Pos (10U)
		4909	#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /!< 0x00000400 /
		4910	#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /!<Output Compare 4 Fast enable /
		4911	#define TIM_CCMR2_OC4PE_Pos (11U)
		4912	#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /!< 0x00000800 /
		4913	#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /!<Output Compare 4 Preload enable /
2	mjames	4914
5	mjames	4915	#define TIM_CCMR2_OC4M_Pos (12U)
		4916	#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /!< 0x00007000 /
		4917	#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /!<OC4M[2:0] bits (Output Compare 4 Mode) /
		4918	#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /!< 0x00001000 /
		4919	#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /!< 0x00002000 /
		4920	#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /!< 0x00004000 /
2	mjames	4921
5	mjames	4922	#define TIM_CCMR2_OC4CE_Pos (15U)
		4923	#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /!< 0x00008000 /
		4924	#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /!<Output Compare 4 Clear Enable /
2	mjames	4925
		4926	/---------------------------------------------------------------------------/
		4927
5	mjames	4928	#define TIM_CCMR2_IC3PSC_Pos (2U)
		4929	#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /!< 0x0000000C /
		4930	#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
		4931	#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000004 /
		4932	#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000008 /
2	mjames	4933
5	mjames	4934	#define TIM_CCMR2_IC3F_Pos (4U)
		4935	#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /!< 0x000000F0 /
		4936	#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /!<IC3F[3:0] bits (Input Capture 3 Filter) /
		4937	#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /!< 0x00000010 /
		4938	#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /!< 0x00000020 /
		4939	#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /!< 0x00000040 /
		4940	#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /!< 0x00000080 /
2	mjames	4941
5	mjames	4942	#define TIM_CCMR2_IC4PSC_Pos (10U)
		4943	#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000C00 /
		4944	#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
		4945	#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000400 /
		4946	#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000800 /
2	mjames	4947
5	mjames	4948	#define TIM_CCMR2_IC4F_Pos (12U)
		4949	#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /!< 0x0000F000 /
		4950	#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /!<IC4F[3:0] bits (Input Capture 4 Filter) /
		4951	#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /!< 0x00001000 /
		4952	#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /!< 0x00002000 /
		4953	#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /!< 0x00004000 /
		4954	#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /!< 0x00008000 /
2	mjames	4955
		4956	/***************** Bit definition for TIM_CCER register ****************/
5	mjames	4957	#define TIM_CCER_CC1E_Pos (0U)
		4958	#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /!< 0x00000001 /
		4959	#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /!<Capture/Compare 1 output enable /
		4960	#define TIM_CCER_CC1P_Pos (1U)
		4961	#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /!< 0x00000002 /
		4962	#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /!<Capture/Compare 1 output Polarity /
		4963	#define TIM_CCER_CC1NE_Pos (2U)
		4964	#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /!< 0x00000004 /
		4965	#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /!<Capture/Compare 1 Complementary output enable /
		4966	#define TIM_CCER_CC1NP_Pos (3U)
		4967	#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /!< 0x00000008 /
		4968	#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /!<Capture/Compare 1 Complementary output Polarity /
		4969	#define TIM_CCER_CC2E_Pos (4U)
		4970	#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /!< 0x00000010 /
		4971	#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /!<Capture/Compare 2 output enable /
		4972	#define TIM_CCER_CC2P_Pos (5U)
		4973	#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /!< 0x00000020 /
		4974	#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /!<Capture/Compare 2 output Polarity /
		4975	#define TIM_CCER_CC2NE_Pos (6U)
		4976	#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /!< 0x00000040 /
		4977	#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /!<Capture/Compare 2 Complementary output enable /
		4978	#define TIM_CCER_CC2NP_Pos (7U)
		4979	#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /!< 0x00000080 /
		4980	#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /!<Capture/Compare 2 Complementary output Polarity /
		4981	#define TIM_CCER_CC3E_Pos (8U)
		4982	#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /!< 0x00000100 /
		4983	#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /!<Capture/Compare 3 output enable /
		4984	#define TIM_CCER_CC3P_Pos (9U)
		4985	#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /!< 0x00000200 /
		4986	#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /!<Capture/Compare 3 output Polarity /
		4987	#define TIM_CCER_CC3NE_Pos (10U)
		4988	#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /!< 0x00000400 /
		4989	#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /!<Capture/Compare 3 Complementary output enable /
		4990	#define TIM_CCER_CC3NP_Pos (11U)
		4991	#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /!< 0x00000800 /
		4992	#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /!<Capture/Compare 3 Complementary output Polarity /
		4993	#define TIM_CCER_CC4E_Pos (12U)
		4994	#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /!< 0x00001000 /
		4995	#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /!<Capture/Compare 4 output enable /
		4996	#define TIM_CCER_CC4P_Pos (13U)
		4997	#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /!< 0x00002000 /
		4998	#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /!<Capture/Compare 4 output Polarity /
		4999	#define TIM_CCER_CC4NP_Pos (15U)
		5000	#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /!< 0x00008000 /
		5001	#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /!<Capture/Compare 4 Complementary output Polarity /
2	mjames	5002
		5003	/***************** Bit definition for TIM_CNT register *****************/
5	mjames	5004	#define TIM_CNT_CNT_Pos (0U)
		5005	#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /!< 0xFFFFFFFF /
		5006	#define TIM_CNT_CNT TIM_CNT_CNT_Msk /!<Counter Value /
2	mjames	5007
		5008	/***************** Bit definition for TIM_PSC register *****************/
5	mjames	5009	#define TIM_PSC_PSC_Pos (0U)
		5010	#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /!< 0x0000FFFF /
		5011	#define TIM_PSC_PSC TIM_PSC_PSC_Msk /!<Prescaler Value /
2	mjames	5012
		5013	/***************** Bit definition for TIM_ARR register *****************/
5	mjames	5014	#define TIM_ARR_ARR_Pos (0U)
		5015	#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /!< 0xFFFFFFFF /
		5016	#define TIM_ARR_ARR TIM_ARR_ARR_Msk /!<actual auto-reload Value /
2	mjames	5017
		5018	/***************** Bit definition for TIM_RCR register *****************/
5	mjames	5019	#define TIM_RCR_REP_Pos (0U)
		5020	#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /!< 0x000000FF /
		5021	#define TIM_RCR_REP TIM_RCR_REP_Msk /!<Repetition Counter Value /
2	mjames	5022
		5023	/***************** Bit definition for TIM_CCR1 register ****************/
5	mjames	5024	#define TIM_CCR1_CCR1_Pos (0U)
		5025	#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /!< 0x0000FFFF /
		5026	#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /!<Capture/Compare 1 Value /
2	mjames	5027
		5028	/***************** Bit definition for TIM_CCR2 register ****************/
5	mjames	5029	#define TIM_CCR2_CCR2_Pos (0U)
		5030	#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /!< 0x0000FFFF /
		5031	#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /!<Capture/Compare 2 Value /
2	mjames	5032
		5033	/***************** Bit definition for TIM_CCR3 register ****************/
5	mjames	5034	#define TIM_CCR3_CCR3_Pos (0U)
		5035	#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /!< 0x0000FFFF /
		5036	#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /!<Capture/Compare 3 Value /
2	mjames	5037
		5038	/***************** Bit definition for TIM_CCR4 register ****************/
5	mjames	5039	#define TIM_CCR4_CCR4_Pos (0U)
		5040	#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /!< 0x0000FFFF /
		5041	#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /!<Capture/Compare 4 Value /
2	mjames	5042
		5043	/***************** Bit definition for TIM_BDTR register ****************/
5	mjames	5044	#define TIM_BDTR_DTG_Pos (0U)
		5045	#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /!< 0x000000FF /
		5046	#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /!<DTG[0:7] bits (Dead-Time Generator set-up) /
		5047	#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /!< 0x00000001 /
		5048	#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /!< 0x00000002 /
		5049	#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /!< 0x00000004 /
		5050	#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /!< 0x00000008 /
		5051	#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /!< 0x00000010 /
		5052	#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /!< 0x00000020 /
		5053	#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /!< 0x00000040 /
		5054	#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /!< 0x00000080 /
2	mjames	5055
5	mjames	5056	#define TIM_BDTR_LOCK_Pos (8U)
		5057	#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /!< 0x00000300 /
		5058	#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /!<LOCK[1:0] bits (Lock Configuration) /
		5059	#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /!< 0x00000100 /
		5060	#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /!< 0x00000200 /
2	mjames	5061
5	mjames	5062	#define TIM_BDTR_OSSI_Pos (10U)
		5063	#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /!< 0x00000400 /
		5064	#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /!<Off-State Selection for Idle mode /
		5065	#define TIM_BDTR_OSSR_Pos (11U)
		5066	#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /!< 0x00000800 /
		5067	#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /!<Off-State Selection for Run mode /
		5068	#define TIM_BDTR_BKE_Pos (12U)
		5069	#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /!< 0x00001000 /
		5070	#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /!<Break enable /
		5071	#define TIM_BDTR_BKP_Pos (13U)
		5072	#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /!< 0x00002000 /
		5073	#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /!<Break Polarity /
		5074	#define TIM_BDTR_AOE_Pos (14U)
		5075	#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /!< 0x00004000 /
		5076	#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /!<Automatic Output enable /
		5077	#define TIM_BDTR_MOE_Pos (15U)
		5078	#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /!< 0x00008000 /
		5079	#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /!<Main Output enable /
2	mjames	5080
		5081	/***************** Bit definition for TIM_DCR register *****************/
5	mjames	5082	#define TIM_DCR_DBA_Pos (0U)
		5083	#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /!< 0x0000001F /
		5084	#define TIM_DCR_DBA TIM_DCR_DBA_Msk /!<DBA[4:0] bits (DMA Base Address) /
		5085	#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /!< 0x00000001 /
		5086	#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /!< 0x00000002 /
		5087	#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /!< 0x00000004 /
		5088	#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /!< 0x00000008 /
		5089	#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /!< 0x00000010 /
2	mjames	5090
5	mjames	5091	#define TIM_DCR_DBL_Pos (8U)
		5092	#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /!< 0x00001F00 /
		5093	#define TIM_DCR_DBL TIM_DCR_DBL_Msk /!<DBL[4:0] bits (DMA Burst Length) /
		5094	#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /!< 0x00000100 /
		5095	#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /!< 0x00000200 /
		5096	#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /!< 0x00000400 /
		5097	#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /!< 0x00000800 /
		5098	#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /!< 0x00001000 /
2	mjames	5099
		5100	/***************** Bit definition for TIM_DMAR register ****************/
5	mjames	5101	#define TIM_DMAR_DMAB_Pos (0U)
		5102	#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /!< 0x0000FFFF /
		5103	#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /!<DMA register for burst accesses /
2	mjames	5104
		5105	/***************** Bit definition for TIM_OR register ******************/
		5106
		5107	/******************************************************************************/
		5108	/* */
		5109	/* Real-Time Clock */
		5110	/* */
		5111	/******************************************************************************/
		5112
		5113	/***************** Bit definition for RTC_CRH register ******************/
5	mjames	5114	#define RTC_CRH_SECIE_Pos (0U)
		5115	#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /!< 0x00000001 /
		5116	#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /!< Second Interrupt Enable /
		5117	#define RTC_CRH_ALRIE_Pos (1U)
		5118	#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /!< 0x00000002 /
		5119	#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /!< Alarm Interrupt Enable /
		5120	#define RTC_CRH_OWIE_Pos (2U)
		5121	#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /!< 0x00000004 /
		5122	#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /!< OverfloW Interrupt Enable /
2	mjames	5123
		5124	/***************** Bit definition for RTC_CRL register ******************/
5	mjames	5125	#define RTC_CRL_SECF_Pos (0U)
		5126	#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /!< 0x00000001 /
		5127	#define RTC_CRL_SECF RTC_CRL_SECF_Msk /!< Second Flag /
		5128	#define RTC_CRL_ALRF_Pos (1U)
		5129	#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /!< 0x00000002 /
		5130	#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /!< Alarm Flag /
		5131	#define RTC_CRL_OWF_Pos (2U)
		5132	#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /!< 0x00000004 /
		5133	#define RTC_CRL_OWF RTC_CRL_OWF_Msk /!< OverfloW Flag /
		5134	#define RTC_CRL_RSF_Pos (3U)
		5135	#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /!< 0x00000008 /
		5136	#define RTC_CRL_RSF RTC_CRL_RSF_Msk /!< Registers Synchronized Flag /
		5137	#define RTC_CRL_CNF_Pos (4U)
		5138	#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /!< 0x00000010 /
		5139	#define RTC_CRL_CNF RTC_CRL_CNF_Msk /!< Configuration Flag /
		5140	#define RTC_CRL_RTOFF_Pos (5U)
		5141	#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /!< 0x00000020 /
		5142	#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /!< RTC operation OFF /
2	mjames	5143
		5144	/***************** Bit definition for RTC_PRLH register *****************/
5	mjames	5145	#define RTC_PRLH_PRL_Pos (0U)
		5146	#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /!< 0x0000000F /
		5147	#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /!< RTC Prescaler Reload Value High /
2	mjames	5148
		5149	/***************** Bit definition for RTC_PRLL register *****************/
5	mjames	5150	#define RTC_PRLL_PRL_Pos (0U)
		5151	#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /!< 0x0000FFFF /
		5152	#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /!< RTC Prescaler Reload Value Low /
2	mjames	5153
		5154	/***************** Bit definition for RTC_DIVH register *****************/
5	mjames	5155	#define RTC_DIVH_RTC_DIV_Pos (0U)
		5156	#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /!< 0x0000000F /
		5157	#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /!< RTC Clock Divider High /
2	mjames	5158
		5159	/***************** Bit definition for RTC_DIVL register *****************/
5	mjames	5160	#define RTC_DIVL_RTC_DIV_Pos (0U)
		5161	#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /!< 0x0000FFFF /
		5162	#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /!< RTC Clock Divider Low /
2	mjames	5163
		5164	/***************** Bit definition for RTC_CNTH register *****************/
5	mjames	5165	#define RTC_CNTH_RTC_CNT_Pos (0U)
		5166	#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /!< 0x0000FFFF /
		5167	#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /!< RTC Counter High /
2	mjames	5168
		5169	/***************** Bit definition for RTC_CNTL register *****************/
5	mjames	5170	#define RTC_CNTL_RTC_CNT_Pos (0U)
		5171	#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /!< 0x0000FFFF /
		5172	#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /!< RTC Counter Low /
2	mjames	5173
		5174	/***************** Bit definition for RTC_ALRH register *****************/
5	mjames	5175	#define RTC_ALRH_RTC_ALR_Pos (0U)
		5176	#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /!< 0x0000FFFF /
		5177	#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /!< RTC Alarm High /
2	mjames	5178
		5179	/***************** Bit definition for RTC_ALRL register *****************/
5	mjames	5180	#define RTC_ALRL_RTC_ALR_Pos (0U)
		5181	#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /!< 0x0000FFFF /
		5182	#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /!< RTC Alarm Low /
2	mjames	5183
		5184	/******************************************************************************/
		5185	/* */
		5186	/* Independent WATCHDOG (IWDG) */
		5187	/* */
		5188	/******************************************************************************/
		5189
		5190	/***************** Bit definition for IWDG_KR register ******************/
5	mjames	5191	#define IWDG_KR_KEY_Pos (0U)
		5192	#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /!< 0x0000FFFF /
		5193	#define IWDG_KR_KEY IWDG_KR_KEY_Msk /!< Key value (write only, read 0000h) /
2	mjames	5194
		5195	/***************** Bit definition for IWDG_PR register ******************/
5	mjames	5196	#define IWDG_PR_PR_Pos (0U)
		5197	#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /!< 0x00000007 /
		5198	#define IWDG_PR_PR IWDG_PR_PR_Msk /!< PR[2:0] (Prescaler divider) /
		5199	#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /!< 0x00000001 /
		5200	#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /!< 0x00000002 /
		5201	#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /!< 0x00000004 /
2	mjames	5202
		5203	/***************** Bit definition for IWDG_RLR register *****************/
5	mjames	5204	#define IWDG_RLR_RL_Pos (0U)
		5205	#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /!< 0x00000FFF /
		5206	#define IWDG_RLR_RL IWDG_RLR_RL_Msk /!< Watchdog counter reload value /
2	mjames	5207
		5208	/***************** Bit definition for IWDG_SR register ******************/
5	mjames	5209	#define IWDG_SR_PVU_Pos (0U)
		5210	#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /!< 0x00000001 /
		5211	#define IWDG_SR_PVU IWDG_SR_PVU_Msk /!< Watchdog prescaler value update /
		5212	#define IWDG_SR_RVU_Pos (1U)
		5213	#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /!< 0x00000002 /
		5214	#define IWDG_SR_RVU IWDG_SR_RVU_Msk /!< Watchdog counter reload value update /
2	mjames	5215
		5216	/******************************************************************************/
		5217	/* */
5	mjames	5218	/* Window WATCHDOG (WWDG) */
2	mjames	5219	/* */
		5220	/******************************************************************************/
		5221
		5222	/***************** Bit definition for WWDG_CR register ******************/
5	mjames	5223	#define WWDG_CR_T_Pos (0U)
		5224	#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /!< 0x0000007F /
		5225	#define WWDG_CR_T WWDG_CR_T_Msk /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
		5226	#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /!< 0x00000001 /
		5227	#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /!< 0x00000002 /
		5228	#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /!< 0x00000004 /
		5229	#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /!< 0x00000008 /
		5230	#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /!< 0x00000010 /
		5231	#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /!< 0x00000020 /
		5232	#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /!< 0x00000040 /
2	mjames	5233
5	mjames	5234	/* Legacy defines */
		5235	#define WWDG_CR_T0 WWDG_CR_T_0
		5236	#define WWDG_CR_T1 WWDG_CR_T_1
		5237	#define WWDG_CR_T2 WWDG_CR_T_2
		5238	#define WWDG_CR_T3 WWDG_CR_T_3
		5239	#define WWDG_CR_T4 WWDG_CR_T_4
		5240	#define WWDG_CR_T5 WWDG_CR_T_5
		5241	#define WWDG_CR_T6 WWDG_CR_T_6
2	mjames	5242
5	mjames	5243	#define WWDG_CR_WDGA_Pos (7U)
		5244	#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /!< 0x00000080 /
		5245	#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /!< Activation bit /
		5246
2	mjames	5247	/***************** Bit definition for WWDG_CFR register *****************/
5	mjames	5248	#define WWDG_CFR_W_Pos (0U)
		5249	#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /!< 0x0000007F /
		5250	#define WWDG_CFR_W WWDG_CFR_W_Msk /!< W[6:0] bits (7-bit window value) /
		5251	#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /!< 0x00000001 /
		5252	#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /!< 0x00000002 /
		5253	#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /!< 0x00000004 /
		5254	#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /!< 0x00000008 /
		5255	#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /!< 0x00000010 /
		5256	#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /!< 0x00000020 /
		5257	#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /!< 0x00000040 /
2	mjames	5258
5	mjames	5259	/* Legacy defines */
		5260	#define WWDG_CFR_W0 WWDG_CFR_W_0
		5261	#define WWDG_CFR_W1 WWDG_CFR_W_1
		5262	#define WWDG_CFR_W2 WWDG_CFR_W_2
		5263	#define WWDG_CFR_W3 WWDG_CFR_W_3
		5264	#define WWDG_CFR_W4 WWDG_CFR_W_4
		5265	#define WWDG_CFR_W5 WWDG_CFR_W_5
		5266	#define WWDG_CFR_W6 WWDG_CFR_W_6
2	mjames	5267
5	mjames	5268	#define WWDG_CFR_WDGTB_Pos (7U)
		5269	#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /!< 0x00000180 /
		5270	#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /!< WDGTB[1:0] bits (Timer Base) /
		5271	#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /!< 0x00000080 /
		5272	#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /!< 0x00000100 /
2	mjames	5273
5	mjames	5274	/* Legacy defines */
		5275	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
		5276	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
		5277
		5278	#define WWDG_CFR_EWI_Pos (9U)
		5279	#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /!< 0x00000200 /
		5280	#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /!< Early Wakeup Interrupt /
		5281
2	mjames	5282	/***************** Bit definition for WWDG_SR register ******************/
5	mjames	5283	#define WWDG_SR_EWIF_Pos (0U)
		5284	#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /!< 0x00000001 /
		5285	#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /!< Early Wakeup Interrupt Flag /
2	mjames	5286
		5287
		5288	/******************************************************************************/
		5289	/* */
		5290	/* SD host Interface */
		5291	/* */
		5292	/******************************************************************************/
		5293
		5294	/**************** Bit definition for SDIO_POWER register ****************/
5	mjames	5295	#define SDIO_POWER_PWRCTRL_Pos (0U)
		5296	#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /!< 0x00000003 /
		5297	#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /!< PWRCTRL[1:0] bits (Power supply control bits) /
		5298	#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /!< 0x01 /
		5299	#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /!< 0x02 /
2	mjames	5300
		5301	/**************** Bit definition for SDIO_CLKCR register ****************/
5	mjames	5302	#define SDIO_CLKCR_CLKDIV_Pos (0U)
		5303	#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /!< 0x000000FF /
		5304	#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /!< Clock divide factor /
		5305	#define SDIO_CLKCR_CLKEN_Pos (8U)
		5306	#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /!< 0x00000100 /
		5307	#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /!< Clock enable bit /
		5308	#define SDIO_CLKCR_PWRSAV_Pos (9U)
		5309	#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /!< 0x00000200 /
		5310	#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /!< Power saving configuration bit /
		5311	#define SDIO_CLKCR_BYPASS_Pos (10U)
		5312	#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /!< 0x00000400 /
		5313	#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /!< Clock divider bypass enable bit /
2	mjames	5314
5	mjames	5315	#define SDIO_CLKCR_WIDBUS_Pos (11U)
		5316	#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /!< 0x00001800 /
		5317	#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
		5318	#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /!< 0x0800 /
		5319	#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /!< 0x1000 /
2	mjames	5320
5	mjames	5321	#define SDIO_CLKCR_NEGEDGE_Pos (13U)
		5322	#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /!< 0x00002000 /
		5323	#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /!< SDIO_CK dephasing selection bit /
		5324	#define SDIO_CLKCR_HWFC_EN_Pos (14U)
		5325	#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /!< 0x00004000 /
		5326	#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /!< HW Flow Control enable /
2	mjames	5327
		5328	/***************** Bit definition for SDIO_ARG register *****************/
5	mjames	5329	#define SDIO_ARG_CMDARG_Pos (0U)
		5330	#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /!< 0xFFFFFFFF /
		5331	#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /!< Command argument /
2	mjames	5332
		5333	/***************** Bit definition for SDIO_CMD register *****************/
5	mjames	5334	#define SDIO_CMD_CMDINDEX_Pos (0U)
		5335	#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /!< 0x0000003F /
		5336	#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /!< Command Index /
2	mjames	5337
5	mjames	5338	#define SDIO_CMD_WAITRESP_Pos (6U)
		5339	#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /!< 0x000000C0 /
		5340	#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /!< WAITRESP[1:0] bits (Wait for response bits) /
		5341	#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /!< 0x0040 /
		5342	#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /!< 0x0080 /
2	mjames	5343
5	mjames	5344	#define SDIO_CMD_WAITINT_Pos (8U)
		5345	#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /!< 0x00000100 /
		5346	#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /!< CPSM Waits for Interrupt Request /
		5347	#define SDIO_CMD_WAITPEND_Pos (9U)
		5348	#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /!< 0x00000200 /
		5349	#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
		5350	#define SDIO_CMD_CPSMEN_Pos (10U)
		5351	#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /!< 0x00000400 /
		5352	#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /!< Command path state machine (CPSM) Enable bit /
		5353	#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
		5354	#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /!< 0x00000800 /
		5355	#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /!< SD I/O suspend command /
		5356	#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
		5357	#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /!< 0x00001000 /
		5358	#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /!< Enable CMD completion /
		5359	#define SDIO_CMD_NIEN_Pos (13U)
		5360	#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /!< 0x00002000 /
		5361	#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /!< Not Interrupt Enable /
		5362	#define SDIO_CMD_CEATACMD_Pos (14U)
		5363	#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /!< 0x00004000 /
		5364	#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /!< CE-ATA command /
2	mjames	5365
		5366	/*************** Bit definition for SDIO_RESPCMD register ***************/
5	mjames	5367	#define SDIO_RESPCMD_RESPCMD_Pos (0U)
		5368	#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /!< 0x0000003F /
		5369	#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /!< Response command index /
2	mjames	5370
		5371	/**************** Bit definition for SDIO_RESP0 register ****************/
5	mjames	5372	#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
		5373	#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /!< 0xFFFFFFFF /
		5374	#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /!< Card Status /
2	mjames	5375
		5376	/**************** Bit definition for SDIO_RESP1 register ****************/
5	mjames	5377	#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
		5378	#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /!< 0xFFFFFFFF /
		5379	#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /!< Card Status /
2	mjames	5380
		5381	/**************** Bit definition for SDIO_RESP2 register ****************/
5	mjames	5382	#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
		5383	#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /!< 0xFFFFFFFF /
		5384	#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /!< Card Status /
2	mjames	5385
		5386	/**************** Bit definition for SDIO_RESP3 register ****************/
5	mjames	5387	#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
		5388	#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /!< 0xFFFFFFFF /
		5389	#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /!< Card Status /
2	mjames	5390
		5391	/**************** Bit definition for SDIO_RESP4 register ****************/
5	mjames	5392	#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
		5393	#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /!< 0xFFFFFFFF /
		5394	#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /!< Card Status /
2	mjames	5395
		5396	/**************** Bit definition for SDIO_DTIMER register ***************/
5	mjames	5397	#define SDIO_DTIMER_DATATIME_Pos (0U)
		5398	#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /!< 0xFFFFFFFF /
		5399	#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /!< Data timeout period. /
2	mjames	5400
		5401	/**************** Bit definition for SDIO_DLEN register *****************/
5	mjames	5402	#define SDIO_DLEN_DATALENGTH_Pos (0U)
		5403	#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /!< 0x01FFFFFF /
		5404	#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /!< Data length value /
2	mjames	5405
		5406	/**************** Bit definition for SDIO_DCTRL register ****************/
5	mjames	5407	#define SDIO_DCTRL_DTEN_Pos (0U)
		5408	#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /!< 0x00000001 /
		5409	#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /!< Data transfer enabled bit /
		5410	#define SDIO_DCTRL_DTDIR_Pos (1U)
		5411	#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /!< 0x00000002 /
		5412	#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /!< Data transfer direction selection /
		5413	#define SDIO_DCTRL_DTMODE_Pos (2U)
		5414	#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /!< 0x00000004 /
		5415	#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /!< Data transfer mode selection /
		5416	#define SDIO_DCTRL_DMAEN_Pos (3U)
		5417	#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /!< 0x00000008 /
		5418	#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /!< DMA enabled bit /
2	mjames	5419
5	mjames	5420	#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
		5421	#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x000000F0 /
		5422	#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /!< DBLOCKSIZE[3:0] bits (Data block size) /
		5423	#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0010 /
		5424	#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0020 /
		5425	#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0040 /
		5426	#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0080 /
2	mjames	5427
5	mjames	5428	#define SDIO_DCTRL_RWSTART_Pos (8U)
		5429	#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /!< 0x00000100 /
		5430	#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /!< Read wait start /
		5431	#define SDIO_DCTRL_RWSTOP_Pos (9U)
		5432	#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /!< 0x00000200 /
		5433	#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /!< Read wait stop /
		5434	#define SDIO_DCTRL_RWMOD_Pos (10U)
		5435	#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /!< 0x00000400 /
		5436	#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /!< Read wait mode /
		5437	#define SDIO_DCTRL_SDIOEN_Pos (11U)
		5438	#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /!< 0x00000800 /
		5439	#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /!< SD I/O enable functions /
2	mjames	5440
		5441	/**************** Bit definition for SDIO_DCOUNT register ***************/
5	mjames	5442	#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
		5443	#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /!< 0x01FFFFFF /
		5444	#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /!< Data count value /
2	mjames	5445
		5446	/**************** Bit definition for SDIO_STA register ******************/
5	mjames	5447	#define SDIO_STA_CCRCFAIL_Pos (0U)
		5448	#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /!< 0x00000001 /
		5449	#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /!< Command response received (CRC check failed) /
		5450	#define SDIO_STA_DCRCFAIL_Pos (1U)
		5451	#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /!< 0x00000002 /
		5452	#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /!< Data block sent/received (CRC check failed) /
		5453	#define SDIO_STA_CTIMEOUT_Pos (2U)
		5454	#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /!< 0x00000004 /
		5455	#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /!< Command response timeout /
		5456	#define SDIO_STA_DTIMEOUT_Pos (3U)
		5457	#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /!< 0x00000008 /
		5458	#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /!< Data timeout /
		5459	#define SDIO_STA_TXUNDERR_Pos (4U)
		5460	#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /!< 0x00000010 /
		5461	#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /!< Transmit FIFO underrun error /
		5462	#define SDIO_STA_RXOVERR_Pos (5U)
		5463	#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /!< 0x00000020 /
		5464	#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /!< Received FIFO overrun error /
		5465	#define SDIO_STA_CMDREND_Pos (6U)
		5466	#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /!< 0x00000040 /
		5467	#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /!< Command response received (CRC check passed) /
		5468	#define SDIO_STA_CMDSENT_Pos (7U)
		5469	#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /!< 0x00000080 /
		5470	#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /!< Command sent (no response required) /
		5471	#define SDIO_STA_DATAEND_Pos (8U)
		5472	#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /!< 0x00000100 /
		5473	#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /!< Data end (data counter, SDIDCOUNT, is zero) /
		5474	#define SDIO_STA_STBITERR_Pos (9U)
		5475	#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /!< 0x00000200 /
		5476	#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /!< Start bit not detected on all data signals in wide bus mode /
		5477	#define SDIO_STA_DBCKEND_Pos (10U)
		5478	#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /!< 0x00000400 /
		5479	#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /!< Data block sent/received (CRC check passed) /
		5480	#define SDIO_STA_CMDACT_Pos (11U)
		5481	#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /!< 0x00000800 /
		5482	#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /!< Command transfer in progress /
		5483	#define SDIO_STA_TXACT_Pos (12U)
		5484	#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /!< 0x00001000 /
		5485	#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /!< Data transmit in progress /
		5486	#define SDIO_STA_RXACT_Pos (13U)
		5487	#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /!< 0x00002000 /
		5488	#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /!< Data receive in progress /
		5489	#define SDIO_STA_TXFIFOHE_Pos (14U)
		5490	#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /!< 0x00004000 /
		5491	#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
		5492	#define SDIO_STA_RXFIFOHF_Pos (15U)
		5493	#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /!< 0x00008000 /
		5494	#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
		5495	#define SDIO_STA_TXFIFOF_Pos (16U)
		5496	#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /!< 0x00010000 /
		5497	#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /!< Transmit FIFO full /
		5498	#define SDIO_STA_RXFIFOF_Pos (17U)
		5499	#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /!< 0x00020000 /
		5500	#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /!< Receive FIFO full /
		5501	#define SDIO_STA_TXFIFOE_Pos (18U)
		5502	#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /!< 0x00040000 /
		5503	#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /!< Transmit FIFO empty /
		5504	#define SDIO_STA_RXFIFOE_Pos (19U)
		5505	#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /!< 0x00080000 /
		5506	#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /!< Receive FIFO empty /
		5507	#define SDIO_STA_TXDAVL_Pos (20U)
		5508	#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /!< 0x00100000 /
		5509	#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /!< Data available in transmit FIFO /
		5510	#define SDIO_STA_RXDAVL_Pos (21U)
		5511	#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /!< 0x00200000 /
		5512	#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /!< Data available in receive FIFO /
		5513	#define SDIO_STA_SDIOIT_Pos (22U)
		5514	#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /!< 0x00400000 /
		5515	#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /!< SDIO interrupt received /
		5516	#define SDIO_STA_CEATAEND_Pos (23U)
		5517	#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /!< 0x00800000 /
		5518	#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /!< CE-ATA command completion signal received for CMD61 /
2	mjames	5519
		5520	/***************** Bit definition for SDIO_ICR register *****************/
5	mjames	5521	#define SDIO_ICR_CCRCFAILC_Pos (0U)
		5522	#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /!< 0x00000001 /
		5523	#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /!< CCRCFAIL flag clear bit /
		5524	#define SDIO_ICR_DCRCFAILC_Pos (1U)
		5525	#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /!< 0x00000002 /
		5526	#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /!< DCRCFAIL flag clear bit /
		5527	#define SDIO_ICR_CTIMEOUTC_Pos (2U)
		5528	#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /!< 0x00000004 /
		5529	#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /!< CTIMEOUT flag clear bit /
		5530	#define SDIO_ICR_DTIMEOUTC_Pos (3U)
		5531	#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /!< 0x00000008 /
		5532	#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /!< DTIMEOUT flag clear bit /
		5533	#define SDIO_ICR_TXUNDERRC_Pos (4U)
		5534	#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /!< 0x00000010 /
		5535	#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /!< TXUNDERR flag clear bit /
		5536	#define SDIO_ICR_RXOVERRC_Pos (5U)
		5537	#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /!< 0x00000020 /
		5538	#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /!< RXOVERR flag clear bit /
		5539	#define SDIO_ICR_CMDRENDC_Pos (6U)
		5540	#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /!< 0x00000040 /
		5541	#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /!< CMDREND flag clear bit /
		5542	#define SDIO_ICR_CMDSENTC_Pos (7U)
		5543	#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /!< 0x00000080 /
		5544	#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /!< CMDSENT flag clear bit /
		5545	#define SDIO_ICR_DATAENDC_Pos (8U)
		5546	#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /!< 0x00000100 /
		5547	#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /!< DATAEND flag clear bit /
		5548	#define SDIO_ICR_STBITERRC_Pos (9U)
		5549	#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /!< 0x00000200 /
		5550	#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /!< STBITERR flag clear bit /
		5551	#define SDIO_ICR_DBCKENDC_Pos (10U)
		5552	#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /!< 0x00000400 /
		5553	#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /!< DBCKEND flag clear bit /
		5554	#define SDIO_ICR_SDIOITC_Pos (22U)
		5555	#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /!< 0x00400000 /
		5556	#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /!< SDIOIT flag clear bit /
		5557	#define SDIO_ICR_CEATAENDC_Pos (23U)
		5558	#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /!< 0x00800000 /
		5559	#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /!< CEATAEND flag clear bit /
2	mjames	5560
		5561	/**************** Bit definition for SDIO_MASK register *****************/
5	mjames	5562	#define SDIO_MASK_CCRCFAILIE_Pos (0U)
		5563	#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /!< 0x00000001 /
		5564	#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /!< Command CRC Fail Interrupt Enable /
		5565	#define SDIO_MASK_DCRCFAILIE_Pos (1U)
		5566	#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /!< 0x00000002 /
		5567	#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /!< Data CRC Fail Interrupt Enable /
		5568	#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
		5569	#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /!< 0x00000004 /
		5570	#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /!< Command TimeOut Interrupt Enable /
		5571	#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
		5572	#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /!< 0x00000008 /
		5573	#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /!< Data TimeOut Interrupt Enable /
		5574	#define SDIO_MASK_TXUNDERRIE_Pos (4U)
		5575	#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /!< 0x00000010 /
		5576	#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /!< Tx FIFO UnderRun Error Interrupt Enable /
		5577	#define SDIO_MASK_RXOVERRIE_Pos (5U)
		5578	#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /!< 0x00000020 /
		5579	#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /!< Rx FIFO OverRun Error Interrupt Enable /
		5580	#define SDIO_MASK_CMDRENDIE_Pos (6U)
		5581	#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /!< 0x00000040 /
		5582	#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /!< Command Response Received Interrupt Enable /
		5583	#define SDIO_MASK_CMDSENTIE_Pos (7U)
		5584	#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /!< 0x00000080 /
		5585	#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /!< Command Sent Interrupt Enable /
		5586	#define SDIO_MASK_DATAENDIE_Pos (8U)
		5587	#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /!< 0x00000100 /
		5588	#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /!< Data End Interrupt Enable /
		5589	#define SDIO_MASK_STBITERRIE_Pos (9U)
		5590	#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /!< 0x00000200 /
		5591	#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /!< Start Bit Error Interrupt Enable /
		5592	#define SDIO_MASK_DBCKENDIE_Pos (10U)
		5593	#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /!< 0x00000400 /
		5594	#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /!< Data Block End Interrupt Enable /
		5595	#define SDIO_MASK_CMDACTIE_Pos (11U)
		5596	#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /!< 0x00000800 /
		5597	#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /!< Command Acting Interrupt Enable /
		5598	#define SDIO_MASK_TXACTIE_Pos (12U)
		5599	#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /!< 0x00001000 /
		5600	#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /!< Data Transmit Acting Interrupt Enable /
		5601	#define SDIO_MASK_RXACTIE_Pos (13U)
		5602	#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /!< 0x00002000 /
		5603	#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /!< Data receive acting interrupt enabled /
		5604	#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
		5605	#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /!< 0x00004000 /
		5606	#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /!< Tx FIFO Half Empty interrupt Enable /
		5607	#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
		5608	#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /!< 0x00008000 /
		5609	#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /!< Rx FIFO Half Full interrupt Enable /
		5610	#define SDIO_MASK_TXFIFOFIE_Pos (16U)
		5611	#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /!< 0x00010000 /
		5612	#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /!< Tx FIFO Full interrupt Enable /
		5613	#define SDIO_MASK_RXFIFOFIE_Pos (17U)
		5614	#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /!< 0x00020000 /
		5615	#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /!< Rx FIFO Full interrupt Enable /
		5616	#define SDIO_MASK_TXFIFOEIE_Pos (18U)
		5617	#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /!< 0x00040000 /
		5618	#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /!< Tx FIFO Empty interrupt Enable /
		5619	#define SDIO_MASK_RXFIFOEIE_Pos (19U)
		5620	#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /!< 0x00080000 /
		5621	#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /!< Rx FIFO Empty interrupt Enable /
		5622	#define SDIO_MASK_TXDAVLIE_Pos (20U)
		5623	#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /!< 0x00100000 /
		5624	#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /!< Data available in Tx FIFO interrupt Enable /
		5625	#define SDIO_MASK_RXDAVLIE_Pos (21U)
		5626	#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /!< 0x00200000 /
		5627	#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /!< Data available in Rx FIFO interrupt Enable /
		5628	#define SDIO_MASK_SDIOITIE_Pos (22U)
		5629	#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /!< 0x00400000 /
		5630	#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /!< SDIO Mode Interrupt Received interrupt Enable /
		5631	#define SDIO_MASK_CEATAENDIE_Pos (23U)
		5632	#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /!< 0x00800000 /
		5633	#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /!< CE-ATA command completion signal received Interrupt Enable /
2	mjames	5634
		5635	/*************** Bit definition for SDIO_FIFOCNT register ***************/
5	mjames	5636	#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
		5637	#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /!< 0x00FFFFFF /
		5638	#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /!< Remaining number of words to be written to or read from the FIFO /
2	mjames	5639
		5640	/**************** Bit definition for SDIO_FIFO register *****************/
5	mjames	5641	#define SDIO_FIFO_FIFODATA_Pos (0U)
		5642	#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /!< 0xFFFFFFFF /
		5643	#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /!< Receive and transmit FIFO data /
2	mjames	5644
		5645
		5646
		5647	/******************************************************************************/
		5648	/* */
		5649	/* Serial Peripheral Interface */
		5650	/* */
		5651	/******************************************************************************/
		5652
		5653	/***************** Bit definition for SPI_CR1 register ******************/
5	mjames	5654	#define SPI_CR1_CPHA_Pos (0U)
		5655	#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /!< 0x00000001 /
		5656	#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /!< Clock Phase /
		5657	#define SPI_CR1_CPOL_Pos (1U)
		5658	#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /!< 0x00000002 /
		5659	#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /!< Clock Polarity /
		5660	#define SPI_CR1_MSTR_Pos (2U)
		5661	#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /!< 0x00000004 /
		5662	#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /!< Master Selection /
2	mjames	5663
5	mjames	5664	#define SPI_CR1_BR_Pos (3U)
		5665	#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /!< 0x00000038 /
		5666	#define SPI_CR1_BR SPI_CR1_BR_Msk /!< BR[2:0] bits (Baud Rate Control) /
		5667	#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /!< 0x00000008 /
		5668	#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /!< 0x00000010 /
		5669	#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /!< 0x00000020 /
2	mjames	5670
5	mjames	5671	#define SPI_CR1_SPE_Pos (6U)
		5672	#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /!< 0x00000040 /
		5673	#define SPI_CR1_SPE SPI_CR1_SPE_Msk /!< SPI Enable /
		5674	#define SPI_CR1_LSBFIRST_Pos (7U)
		5675	#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /!< 0x00000080 /
		5676	#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /!< Frame Format /
		5677	#define SPI_CR1_SSI_Pos (8U)
		5678	#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /!< 0x00000100 /
		5679	#define SPI_CR1_SSI SPI_CR1_SSI_Msk /!< Internal slave select /
		5680	#define SPI_CR1_SSM_Pos (9U)
		5681	#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /!< 0x00000200 /
		5682	#define SPI_CR1_SSM SPI_CR1_SSM_Msk /!< Software slave management /
		5683	#define SPI_CR1_RXONLY_Pos (10U)
		5684	#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /!< 0x00000400 /
		5685	#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /!< Receive only /
		5686	#define SPI_CR1_DFF_Pos (11U)
		5687	#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /!< 0x00000800 /
		5688	#define SPI_CR1_DFF SPI_CR1_DFF_Msk /!< Data Frame Format /
		5689	#define SPI_CR1_CRCNEXT_Pos (12U)
		5690	#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /!< 0x00001000 /
		5691	#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /!< Transmit CRC next /
		5692	#define SPI_CR1_CRCEN_Pos (13U)
		5693	#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /!< 0x00002000 /
		5694	#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /!< Hardware CRC calculation enable /
		5695	#define SPI_CR1_BIDIOE_Pos (14U)
		5696	#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /!< 0x00004000 /
		5697	#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /!< Output enable in bidirectional mode /
		5698	#define SPI_CR1_BIDIMODE_Pos (15U)
		5699	#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /!< 0x00008000 /
		5700	#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /!< Bidirectional data mode enable /
2	mjames	5701
		5702	/***************** Bit definition for SPI_CR2 register ******************/
5	mjames	5703	#define SPI_CR2_RXDMAEN_Pos (0U)
		5704	#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /!< 0x00000001 /
		5705	#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /!< Rx Buffer DMA Enable /
		5706	#define SPI_CR2_TXDMAEN_Pos (1U)
		5707	#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /!< 0x00000002 /
		5708	#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /!< Tx Buffer DMA Enable /
		5709	#define SPI_CR2_SSOE_Pos (2U)
		5710	#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /!< 0x00000004 /
		5711	#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /!< SS Output Enable /
		5712	#define SPI_CR2_ERRIE_Pos (5U)
		5713	#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /!< 0x00000020 /
		5714	#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /!< Error Interrupt Enable /
		5715	#define SPI_CR2_RXNEIE_Pos (6U)
		5716	#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /!< 0x00000040 /
		5717	#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /!< RX buffer Not Empty Interrupt Enable /
		5718	#define SPI_CR2_TXEIE_Pos (7U)
		5719	#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /!< 0x00000080 /
		5720	#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /!< Tx buffer Empty Interrupt Enable /
2	mjames	5721
		5722	/****************** Bit definition for SPI_SR register ******************/
5	mjames	5723	#define SPI_SR_RXNE_Pos (0U)
		5724	#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /!< 0x00000001 /
		5725	#define SPI_SR_RXNE SPI_SR_RXNE_Msk /!< Receive buffer Not Empty /
		5726	#define SPI_SR_TXE_Pos (1U)
		5727	#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /!< 0x00000002 /
		5728	#define SPI_SR_TXE SPI_SR_TXE_Msk /!< Transmit buffer Empty /
		5729	#define SPI_SR_CHSIDE_Pos (2U)
		5730	#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /!< 0x00000004 /
		5731	#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /!< Channel side /
		5732	#define SPI_SR_UDR_Pos (3U)
		5733	#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /!< 0x00000008 /
		5734	#define SPI_SR_UDR SPI_SR_UDR_Msk /!< Underrun flag /
		5735	#define SPI_SR_CRCERR_Pos (4U)
		5736	#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /!< 0x00000010 /
		5737	#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /!< CRC Error flag /
		5738	#define SPI_SR_MODF_Pos (5U)
		5739	#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /!< 0x00000020 /
		5740	#define SPI_SR_MODF SPI_SR_MODF_Msk /!< Mode fault /
		5741	#define SPI_SR_OVR_Pos (6U)
		5742	#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /!< 0x00000040 /
		5743	#define SPI_SR_OVR SPI_SR_OVR_Msk /!< Overrun flag /
		5744	#define SPI_SR_BSY_Pos (7U)
		5745	#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /!< 0x00000080 /
		5746	#define SPI_SR_BSY SPI_SR_BSY_Msk /!< Busy flag /
2	mjames	5747
		5748	/****************** Bit definition for SPI_DR register ******************/
5	mjames	5749	#define SPI_DR_DR_Pos (0U)
		5750	#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /!< 0x0000FFFF /
		5751	#define SPI_DR_DR SPI_DR_DR_Msk /!< Data Register /
2	mjames	5752
		5753	/***************** Bit definition for SPI_CRCPR register ****************/
5	mjames	5754	#define SPI_CRCPR_CRCPOLY_Pos (0U)
		5755	#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /!< 0x0000FFFF /
		5756	#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /!< CRC polynomial register /
2	mjames	5757
		5758	/**************** Bit definition for SPI_RXCRCR register ****************/
5	mjames	5759	#define SPI_RXCRCR_RXCRC_Pos (0U)
		5760	#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /!< 0x0000FFFF /
		5761	#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /!< Rx CRC Register /
2	mjames	5762
		5763	/**************** Bit definition for SPI_TXCRCR register ****************/
5	mjames	5764	#define SPI_TXCRCR_TXCRC_Pos (0U)
		5765	#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /!< 0x0000FFFF /
		5766	#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /!< Tx CRC Register /
2	mjames	5767
		5768
		5769
		5770	/******************************************************************************/
		5771	/* */
		5772	/* Inter-integrated Circuit Interface */
		5773	/* */
		5774	/******************************************************************************/
		5775
		5776	/***************** Bit definition for I2C_CR1 register ******************/
5	mjames	5777	#define I2C_CR1_PE_Pos (0U)
		5778	#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /!< 0x00000001 /
		5779	#define I2C_CR1_PE I2C_CR1_PE_Msk /!< Peripheral Enable /
		5780	#define I2C_CR1_SMBUS_Pos (1U)
		5781	#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /!< 0x00000002 /
		5782	#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /!< SMBus Mode /
		5783	#define I2C_CR1_SMBTYPE_Pos (3U)
		5784	#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /!< 0x00000008 /
		5785	#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /!< SMBus Type /
		5786	#define I2C_CR1_ENARP_Pos (4U)
		5787	#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /!< 0x00000010 /
		5788	#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /!< ARP Enable /
		5789	#define I2C_CR1_ENPEC_Pos (5U)
		5790	#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /!< 0x00000020 /
		5791	#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /!< PEC Enable /
		5792	#define I2C_CR1_ENGC_Pos (6U)
		5793	#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /!< 0x00000040 /
		5794	#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /!< General Call Enable /
		5795	#define I2C_CR1_NOSTRETCH_Pos (7U)
		5796	#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /!< 0x00000080 /
		5797	#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /!< Clock Stretching Disable (Slave mode) /
		5798	#define I2C_CR1_START_Pos (8U)
		5799	#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /!< 0x00000100 /
		5800	#define I2C_CR1_START I2C_CR1_START_Msk /!< Start Generation /
		5801	#define I2C_CR1_STOP_Pos (9U)
		5802	#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /!< 0x00000200 /
		5803	#define I2C_CR1_STOP I2C_CR1_STOP_Msk /!< Stop Generation /
		5804	#define I2C_CR1_ACK_Pos (10U)
		5805	#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /!< 0x00000400 /
		5806	#define I2C_CR1_ACK I2C_CR1_ACK_Msk /!< Acknowledge Enable /
		5807	#define I2C_CR1_POS_Pos (11U)
		5808	#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /!< 0x00000800 /
		5809	#define I2C_CR1_POS I2C_CR1_POS_Msk /!< Acknowledge/PEC Position (for data reception) /
		5810	#define I2C_CR1_PEC_Pos (12U)
		5811	#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /!< 0x00001000 /
		5812	#define I2C_CR1_PEC I2C_CR1_PEC_Msk /!< Packet Error Checking /
		5813	#define I2C_CR1_ALERT_Pos (13U)
		5814	#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /!< 0x00002000 /
		5815	#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /!< SMBus Alert /
		5816	#define I2C_CR1_SWRST_Pos (15U)
		5817	#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /!< 0x00008000 /
		5818	#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /!< Software Reset /
2	mjames	5819
		5820	/***************** Bit definition for I2C_CR2 register ******************/
5	mjames	5821	#define I2C_CR2_FREQ_Pos (0U)
		5822	#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /!< 0x0000003F /
		5823	#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
		5824	#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /!< 0x00000001 /
		5825	#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /!< 0x00000002 /
		5826	#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /!< 0x00000004 /
		5827	#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /!< 0x00000008 /
		5828	#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /!< 0x00000010 /
		5829	#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /!< 0x00000020 /
2	mjames	5830
5	mjames	5831	#define I2C_CR2_ITERREN_Pos (8U)
		5832	#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /!< 0x00000100 /
		5833	#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /!< Error Interrupt Enable /
		5834	#define I2C_CR2_ITEVTEN_Pos (9U)
		5835	#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /!< 0x00000200 /
		5836	#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /!< Event Interrupt Enable /
		5837	#define I2C_CR2_ITBUFEN_Pos (10U)
		5838	#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /!< 0x00000400 /
		5839	#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /!< Buffer Interrupt Enable /
		5840	#define I2C_CR2_DMAEN_Pos (11U)
		5841	#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /!< 0x00000800 /
		5842	#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /!< DMA Requests Enable /
		5843	#define I2C_CR2_LAST_Pos (12U)
		5844	#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /!< 0x00001000 /
		5845	#define I2C_CR2_LAST I2C_CR2_LAST_Msk /!< DMA Last Transfer /
2	mjames	5846
		5847	/***************** Bit definition for I2C_OAR1 register *****************/
5	mjames	5848	#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /!< Interface Address /
		5849	#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /!< Interface Address /
2	mjames	5850
5	mjames	5851	#define I2C_OAR1_ADD0_Pos (0U)
		5852	#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /!< 0x00000001 /
		5853	#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /!< Bit 0 /
		5854	#define I2C_OAR1_ADD1_Pos (1U)
		5855	#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /!< 0x00000002 /
		5856	#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /!< Bit 1 /
		5857	#define I2C_OAR1_ADD2_Pos (2U)
		5858	#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /!< 0x00000004 /
		5859	#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /!< Bit 2 /
		5860	#define I2C_OAR1_ADD3_Pos (3U)
		5861	#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /!< 0x00000008 /
		5862	#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /!< Bit 3 /
		5863	#define I2C_OAR1_ADD4_Pos (4U)
		5864	#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /!< 0x00000010 /
		5865	#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /!< Bit 4 /
		5866	#define I2C_OAR1_ADD5_Pos (5U)
		5867	#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /!< 0x00000020 /
		5868	#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /!< Bit 5 /
		5869	#define I2C_OAR1_ADD6_Pos (6U)
		5870	#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /!< 0x00000040 /
		5871	#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /!< Bit 6 /
		5872	#define I2C_OAR1_ADD7_Pos (7U)
		5873	#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /!< 0x00000080 /
		5874	#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /!< Bit 7 /
		5875	#define I2C_OAR1_ADD8_Pos (8U)
		5876	#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /!< 0x00000100 /
		5877	#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /!< Bit 8 /
		5878	#define I2C_OAR1_ADD9_Pos (9U)
		5879	#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /!< 0x00000200 /
		5880	#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /!< Bit 9 /
2	mjames	5881
5	mjames	5882	#define I2C_OAR1_ADDMODE_Pos (15U)
		5883	#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /!< 0x00008000 /
		5884	#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /!< Addressing Mode (Slave mode) /
2	mjames	5885
		5886	/***************** Bit definition for I2C_OAR2 register *****************/
5	mjames	5887	#define I2C_OAR2_ENDUAL_Pos (0U)
		5888	#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /!< 0x00000001 /
		5889	#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /!< Dual addressing mode enable /
		5890	#define I2C_OAR2_ADD2_Pos (1U)
		5891	#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /!< 0x000000FE /
		5892	#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /!< Interface address /
2	mjames	5893
		5894	/***************** Bit definition for I2C_SR1 register ******************/
5	mjames	5895	#define I2C_SR1_SB_Pos (0U)
		5896	#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /!< 0x00000001 /
		5897	#define I2C_SR1_SB I2C_SR1_SB_Msk /!< Start Bit (Master mode) /
		5898	#define I2C_SR1_ADDR_Pos (1U)
		5899	#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /!< 0x00000002 /
		5900	#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /!< Address sent (master mode)/matched (slave mode) /
		5901	#define I2C_SR1_BTF_Pos (2U)
		5902	#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /!< 0x00000004 /
		5903	#define I2C_SR1_BTF I2C_SR1_BTF_Msk /!< Byte Transfer Finished /
		5904	#define I2C_SR1_ADD10_Pos (3U)
		5905	#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /!< 0x00000008 /
		5906	#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /!< 10-bit header sent (Master mode) /
		5907	#define I2C_SR1_STOPF_Pos (4U)
		5908	#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /!< 0x00000010 /
		5909	#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /!< Stop detection (Slave mode) /
		5910	#define I2C_SR1_RXNE_Pos (6U)
		5911	#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /!< 0x00000040 /
		5912	#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /!< Data Register not Empty (receivers) /
		5913	#define I2C_SR1_TXE_Pos (7U)
		5914	#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /!< 0x00000080 /
		5915	#define I2C_SR1_TXE I2C_SR1_TXE_Msk /!< Data Register Empty (transmitters) /
		5916	#define I2C_SR1_BERR_Pos (8U)
		5917	#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /!< 0x00000100 /
		5918	#define I2C_SR1_BERR I2C_SR1_BERR_Msk /!< Bus Error /
		5919	#define I2C_SR1_ARLO_Pos (9U)
		5920	#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /!< 0x00000200 /
		5921	#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /!< Arbitration Lost (master mode) /
		5922	#define I2C_SR1_AF_Pos (10U)
		5923	#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /!< 0x00000400 /
		5924	#define I2C_SR1_AF I2C_SR1_AF_Msk /!< Acknowledge Failure /
		5925	#define I2C_SR1_OVR_Pos (11U)
		5926	#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /!< 0x00000800 /
		5927	#define I2C_SR1_OVR I2C_SR1_OVR_Msk /!< Overrun/Underrun /
		5928	#define I2C_SR1_PECERR_Pos (12U)
		5929	#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /!< 0x00001000 /
		5930	#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /!< PEC Error in reception /
		5931	#define I2C_SR1_TIMEOUT_Pos (14U)
		5932	#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /!< 0x00004000 /
		5933	#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /!< Timeout or Tlow Error /
		5934	#define I2C_SR1_SMBALERT_Pos (15U)
		5935	#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /!< 0x00008000 /
		5936	#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /!< SMBus Alert /
2	mjames	5937
		5938	/***************** Bit definition for I2C_SR2 register ******************/
5	mjames	5939	#define I2C_SR2_MSL_Pos (0U)
		5940	#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /!< 0x00000001 /
		5941	#define I2C_SR2_MSL I2C_SR2_MSL_Msk /!< Master/Slave /
		5942	#define I2C_SR2_BUSY_Pos (1U)
		5943	#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /!< 0x00000002 /
		5944	#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /!< Bus Busy /
		5945	#define I2C_SR2_TRA_Pos (2U)
		5946	#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /!< 0x00000004 /
		5947	#define I2C_SR2_TRA I2C_SR2_TRA_Msk /!< Transmitter/Receiver /
		5948	#define I2C_SR2_GENCALL_Pos (4U)
		5949	#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /!< 0x00000010 /
		5950	#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /!< General Call Address (Slave mode) /
		5951	#define I2C_SR2_SMBDEFAULT_Pos (5U)
		5952	#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /!< 0x00000020 /
		5953	#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /!< SMBus Device Default Address (Slave mode) /
		5954	#define I2C_SR2_SMBHOST_Pos (6U)
		5955	#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /!< 0x00000040 /
		5956	#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /!< SMBus Host Header (Slave mode) /
		5957	#define I2C_SR2_DUALF_Pos (7U)
		5958	#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /!< 0x00000080 /
		5959	#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /!< Dual Flag (Slave mode) /
		5960	#define I2C_SR2_PEC_Pos (8U)
		5961	#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /!< 0x0000FF00 /
		5962	#define I2C_SR2_PEC I2C_SR2_PEC_Msk /!< Packet Error Checking Register /
2	mjames	5963
		5964	/***************** Bit definition for I2C_CCR register ******************/
5	mjames	5965	#define I2C_CCR_CCR_Pos (0U)
		5966	#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /!< 0x00000FFF /
		5967	#define I2C_CCR_CCR I2C_CCR_CCR_Msk /!< Clock Control Register in Fast/Standard mode (Master mode) /
		5968	#define I2C_CCR_DUTY_Pos (14U)
		5969	#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /!< 0x00004000 /
		5970	#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /!< Fast Mode Duty Cycle /
		5971	#define I2C_CCR_FS_Pos (15U)
		5972	#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /!< 0x00008000 /
		5973	#define I2C_CCR_FS I2C_CCR_FS_Msk /!< I2C Master Mode Selection /
2	mjames	5974
		5975	/**************** Bit definition for I2C_TRISE register *****************/
5	mjames	5976	#define I2C_TRISE_TRISE_Pos (0U)
		5977	#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /!< 0x0000003F /
		5978	#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
2	mjames	5979
		5980	/******************************************************************************/
		5981	/* */
		5982	/* Universal Synchronous Asynchronous Receiver Transmitter */
		5983	/* */
		5984	/******************************************************************************/
		5985
		5986	/***************** Bit definition for USART_SR register *****************/
5	mjames	5987	#define USART_SR_PE_Pos (0U)
		5988	#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /!< 0x00000001 /
		5989	#define USART_SR_PE USART_SR_PE_Msk /!< Parity Error /
		5990	#define USART_SR_FE_Pos (1U)
		5991	#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /!< 0x00000002 /
		5992	#define USART_SR_FE USART_SR_FE_Msk /!< Framing Error /
		5993	#define USART_SR_NE_Pos (2U)
		5994	#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /!< 0x00000004 /
		5995	#define USART_SR_NE USART_SR_NE_Msk /!< Noise Error Flag /
		5996	#define USART_SR_ORE_Pos (3U)
		5997	#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /!< 0x00000008 /
		5998	#define USART_SR_ORE USART_SR_ORE_Msk /!< OverRun Error /
		5999	#define USART_SR_IDLE_Pos (4U)
		6000	#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /!< 0x00000010 /
		6001	#define USART_SR_IDLE USART_SR_IDLE_Msk /!< IDLE line detected /
		6002	#define USART_SR_RXNE_Pos (5U)
		6003	#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /!< 0x00000020 /
		6004	#define USART_SR_RXNE USART_SR_RXNE_Msk /!< Read Data Register Not Empty /
		6005	#define USART_SR_TC_Pos (6U)
		6006	#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /!< 0x00000040 /
		6007	#define USART_SR_TC USART_SR_TC_Msk /!< Transmission Complete /
		6008	#define USART_SR_TXE_Pos (7U)
		6009	#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /!< 0x00000080 /
		6010	#define USART_SR_TXE USART_SR_TXE_Msk /!< Transmit Data Register Empty /
		6011	#define USART_SR_LBD_Pos (8U)
		6012	#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /!< 0x00000100 /
		6013	#define USART_SR_LBD USART_SR_LBD_Msk /!< LIN Break Detection Flag /
		6014	#define USART_SR_CTS_Pos (9U)
		6015	#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /!< 0x00000200 /
		6016	#define USART_SR_CTS USART_SR_CTS_Msk /!< CTS Flag /
2	mjames	6017
		6018	/***************** Bit definition for USART_DR register *****************/
5	mjames	6019	#define USART_DR_DR_Pos (0U)
		6020	#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /!< 0x000001FF /
		6021	#define USART_DR_DR USART_DR_DR_Msk /!< Data value /
2	mjames	6022
		6023	/**************** Bit definition for USART_BRR register *****************/
5	mjames	6024	#define USART_BRR_DIV_Fraction_Pos (0U)
		6025	#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /!< 0x0000000F /
		6026	#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /!< Fraction of USARTDIV /
		6027	#define USART_BRR_DIV_Mantissa_Pos (4U)
		6028	#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /!< 0x0000FFF0 /
		6029	#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /!< Mantissa of USARTDIV /
2	mjames	6030
		6031	/**************** Bit definition for USART_CR1 register *****************/
5	mjames	6032	#define USART_CR1_SBK_Pos (0U)
		6033	#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /!< 0x00000001 /
		6034	#define USART_CR1_SBK USART_CR1_SBK_Msk /!< Send Break /
		6035	#define USART_CR1_RWU_Pos (1U)
		6036	#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /!< 0x00000002 /
		6037	#define USART_CR1_RWU USART_CR1_RWU_Msk /!< Receiver wakeup /
		6038	#define USART_CR1_RE_Pos (2U)
		6039	#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /!< 0x00000004 /
		6040	#define USART_CR1_RE USART_CR1_RE_Msk /!< Receiver Enable /
		6041	#define USART_CR1_TE_Pos (3U)
		6042	#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /!< 0x00000008 /
		6043	#define USART_CR1_TE USART_CR1_TE_Msk /!< Transmitter Enable /
		6044	#define USART_CR1_IDLEIE_Pos (4U)
		6045	#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /!< 0x00000010 /
		6046	#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /!< IDLE Interrupt Enable /
		6047	#define USART_CR1_RXNEIE_Pos (5U)
		6048	#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /!< 0x00000020 /
		6049	#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /!< RXNE Interrupt Enable /
		6050	#define USART_CR1_TCIE_Pos (6U)
		6051	#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /!< 0x00000040 /
		6052	#define USART_CR1_TCIE USART_CR1_TCIE_Msk /!< Transmission Complete Interrupt Enable /
		6053	#define USART_CR1_TXEIE_Pos (7U)
		6054	#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /!< 0x00000080 /
		6055	#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /!< PE Interrupt Enable /
		6056	#define USART_CR1_PEIE_Pos (8U)
		6057	#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /!< 0x00000100 /
		6058	#define USART_CR1_PEIE USART_CR1_PEIE_Msk /!< PE Interrupt Enable /
		6059	#define USART_CR1_PS_Pos (9U)
		6060	#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /!< 0x00000200 /
		6061	#define USART_CR1_PS USART_CR1_PS_Msk /!< Parity Selection /
		6062	#define USART_CR1_PCE_Pos (10U)
		6063	#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /!< 0x00000400 /
		6064	#define USART_CR1_PCE USART_CR1_PCE_Msk /!< Parity Control Enable /
		6065	#define USART_CR1_WAKE_Pos (11U)
		6066	#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /!< 0x00000800 /
		6067	#define USART_CR1_WAKE USART_CR1_WAKE_Msk /!< Wakeup method /
		6068	#define USART_CR1_M_Pos (12U)
		6069	#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /!< 0x00001000 /
		6070	#define USART_CR1_M USART_CR1_M_Msk /!< Word length /
		6071	#define USART_CR1_UE_Pos (13U)
		6072	#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /!< 0x00002000 /
		6073	#define USART_CR1_UE USART_CR1_UE_Msk /!< USART Enable /
2	mjames	6074
		6075	/**************** Bit definition for USART_CR2 register *****************/
5	mjames	6076	#define USART_CR2_ADD_Pos (0U)
		6077	#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /!< 0x0000000F /
		6078	#define USART_CR2_ADD USART_CR2_ADD_Msk /!< Address of the USART node /
		6079	#define USART_CR2_LBDL_Pos (5U)
		6080	#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /!< 0x00000020 /
		6081	#define USART_CR2_LBDL USART_CR2_LBDL_Msk /!< LIN Break Detection Length /
		6082	#define USART_CR2_LBDIE_Pos (6U)
		6083	#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /!< 0x00000040 /
		6084	#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /!< LIN Break Detection Interrupt Enable /
		6085	#define USART_CR2_LBCL_Pos (8U)
		6086	#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /!< 0x00000100 /
		6087	#define USART_CR2_LBCL USART_CR2_LBCL_Msk /!< Last Bit Clock pulse /
		6088	#define USART_CR2_CPHA_Pos (9U)
		6089	#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /!< 0x00000200 /
		6090	#define USART_CR2_CPHA USART_CR2_CPHA_Msk /!< Clock Phase /
		6091	#define USART_CR2_CPOL_Pos (10U)
		6092	#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /!< 0x00000400 /
		6093	#define USART_CR2_CPOL USART_CR2_CPOL_Msk /!< Clock Polarity /
		6094	#define USART_CR2_CLKEN_Pos (11U)
		6095	#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /!< 0x00000800 /
		6096	#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /!< Clock Enable /
2	mjames	6097
5	mjames	6098	#define USART_CR2_STOP_Pos (12U)
		6099	#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /!< 0x00003000 /
		6100	#define USART_CR2_STOP USART_CR2_STOP_Msk /!< STOP[1:0] bits (STOP bits) /
		6101	#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /!< 0x00001000 /
		6102	#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /!< 0x00002000 /
2	mjames	6103
5	mjames	6104	#define USART_CR2_LINEN_Pos (14U)
		6105	#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /!< 0x00004000 /
		6106	#define USART_CR2_LINEN USART_CR2_LINEN_Msk /!< LIN mode enable /
2	mjames	6107
		6108	/**************** Bit definition for USART_CR3 register *****************/
5	mjames	6109	#define USART_CR3_EIE_Pos (0U)
		6110	#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /!< 0x00000001 /
		6111	#define USART_CR3_EIE USART_CR3_EIE_Msk /!< Error Interrupt Enable /
		6112	#define USART_CR3_IREN_Pos (1U)
		6113	#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /!< 0x00000002 /
		6114	#define USART_CR3_IREN USART_CR3_IREN_Msk /!< IrDA mode Enable /
		6115	#define USART_CR3_IRLP_Pos (2U)
		6116	#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /!< 0x00000004 /
		6117	#define USART_CR3_IRLP USART_CR3_IRLP_Msk /!< IrDA Low-Power /
		6118	#define USART_CR3_HDSEL_Pos (3U)
		6119	#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /!< 0x00000008 /
		6120	#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /!< Half-Duplex Selection /
		6121	#define USART_CR3_NACK_Pos (4U)
		6122	#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /!< 0x00000010 /
		6123	#define USART_CR3_NACK USART_CR3_NACK_Msk /!< Smartcard NACK enable /
		6124	#define USART_CR3_SCEN_Pos (5U)
		6125	#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /!< 0x00000020 /
		6126	#define USART_CR3_SCEN USART_CR3_SCEN_Msk /!< Smartcard mode enable /
		6127	#define USART_CR3_DMAR_Pos (6U)
		6128	#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /!< 0x00000040 /
		6129	#define USART_CR3_DMAR USART_CR3_DMAR_Msk /!< DMA Enable Receiver /
		6130	#define USART_CR3_DMAT_Pos (7U)
		6131	#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /!< 0x00000080 /
		6132	#define USART_CR3_DMAT USART_CR3_DMAT_Msk /!< DMA Enable Transmitter /
		6133	#define USART_CR3_RTSE_Pos (8U)
		6134	#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /!< 0x00000100 /
		6135	#define USART_CR3_RTSE USART_CR3_RTSE_Msk /!< RTS Enable /
		6136	#define USART_CR3_CTSE_Pos (9U)
		6137	#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /!< 0x00000200 /
		6138	#define USART_CR3_CTSE USART_CR3_CTSE_Msk /!< CTS Enable /
		6139	#define USART_CR3_CTSIE_Pos (10U)
		6140	#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /!< 0x00000400 /
		6141	#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /!< CTS Interrupt Enable /
2	mjames	6142
		6143	/**************** Bit definition for USART_GTPR register ****************/
5	mjames	6144	#define USART_GTPR_PSC_Pos (0U)
		6145	#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /!< 0x000000FF /
		6146	#define USART_GTPR_PSC USART_GTPR_PSC_Msk /!< PSC[7:0] bits (Prescaler value) /
		6147	#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /!< 0x00000001 /
		6148	#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /!< 0x00000002 /
		6149	#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /!< 0x00000004 /
		6150	#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /!< 0x00000008 /
		6151	#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /!< 0x00000010 /
		6152	#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /!< 0x00000020 /
		6153	#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /!< 0x00000040 /
		6154	#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /!< 0x00000080 /
2	mjames	6155
5	mjames	6156	#define USART_GTPR_GT_Pos (8U)
		6157	#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /!< 0x0000FF00 /
		6158	#define USART_GTPR_GT USART_GTPR_GT_Msk /!< Guard time value /
2	mjames	6159
		6160	/******************************************************************************/
		6161	/* */
		6162	/* Debug MCU */
		6163	/* */
		6164	/******************************************************************************/
		6165
		6166	/************** Bit definition for DBGMCU_IDCODE register ***************/
5	mjames	6167	#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
		6168	#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /!< 0x00000FFF /
		6169	#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /!< Device Identifier /
2	mjames	6170
5	mjames	6171	#define DBGMCU_IDCODE_REV_ID_Pos (16U)
		6172	#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /!< 0xFFFF0000 /
		6173	#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /!< REV_ID[15:0] bits (Revision Identifier) /
		6174	#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00010000 /
		6175	#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00020000 /
		6176	#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00040000 /
		6177	#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00080000 /
		6178	#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00100000 /
		6179	#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00200000 /
		6180	#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00400000 /
		6181	#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00800000 /
		6182	#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x01000000 /
		6183	#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x02000000 /
		6184	#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x04000000 /
		6185	#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x08000000 /
		6186	#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x10000000 /
		6187	#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x20000000 /
		6188	#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x40000000 /
		6189	#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x80000000 /
2	mjames	6190
		6191	/**************** Bit definition for DBGMCU_CR register *****************/
5	mjames	6192	#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
		6193	#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /!< 0x00000001 /
		6194	#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /!< Debug Sleep Mode /
		6195	#define DBGMCU_CR_DBG_STOP_Pos (1U)
		6196	#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /!< 0x00000002 /
		6197	#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /!< Debug Stop Mode /
		6198	#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
		6199	#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /!< 0x00000004 /
		6200	#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /!< Debug Standby mode /
		6201	#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
		6202	#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /!< 0x00000020 /
		6203	#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /!< Trace Pin Assignment Control /
2	mjames	6204
5	mjames	6205	#define DBGMCU_CR_TRACE_MODE_Pos (6U)
		6206	#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x000000C0 /
		6207	#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
		6208	#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000040 /
		6209	#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000080 /
2	mjames	6210
5	mjames	6211	#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
		6212	#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /!< 0x00000100 /
		6213	#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /!< Debug Independent Watchdog stopped when Core is halted /
		6214	#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
		6215	#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /!< 0x00000200 /
		6216	#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /!< Debug Window Watchdog stopped when Core is halted /
		6217	#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
		6218	#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /!< 0x00000400 /
		6219	#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /!< TIM1 counter stopped when core is halted /
		6220	#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
		6221	#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /!< 0x00000800 /
		6222	#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /!< TIM2 counter stopped when core is halted /
		6223	#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
		6224	#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /!< 0x00001000 /
		6225	#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /!< TIM3 counter stopped when core is halted /
		6226	#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
		6227	#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /!< 0x00002000 /
		6228	#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /!< TIM4 counter stopped when core is halted /
		6229	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
		6230	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /!< 0x00008000 /
		6231	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		6232	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
		6233	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /!< 0x00010000 /
		6234	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		6235	#define DBGMCU_CR_DBG_TIM15_STOP_Pos (22U)
		6236	#define DBGMCU_CR_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM15_STOP_Pos) /!< 0x00400000 /
		6237	#define DBGMCU_CR_DBG_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP_Msk /!< Debug TIM15 stopped when Core is halted /
		6238	#define DBGMCU_CR_DBG_TIM16_STOP_Pos (23U)
		6239	#define DBGMCU_CR_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM16_STOP_Pos) /!< 0x00800000 /
		6240	#define DBGMCU_CR_DBG_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP_Msk /!< Debug TIM16 stopped when Core is halted /
		6241	#define DBGMCU_CR_DBG_TIM17_STOP_Pos (24U)
		6242	#define DBGMCU_CR_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM17_STOP_Pos) /!< 0x01000000 /
		6243	#define DBGMCU_CR_DBG_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP_Msk /!< Debug TIM17 stopped when Core is halted /
2	mjames	6244
		6245	/******************************************************************************/
		6246	/* */
		6247	/* FLASH and Option Bytes Registers */
		6248	/* */
		6249	/******************************************************************************/
		6250	/***************** Bit definition for FLASH_ACR register ****************/
5	mjames	6251	#define FLASH_ACR_HLFCYA_Pos (3U)
		6252	#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /!< 0x00000008 /
		6253	#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /!< Flash Half Cycle Access Enable /
2	mjames	6254
		6255	/**************** Bit definition for FLASH_KEYR register ****************/
5	mjames	6256	#define FLASH_KEYR_FKEYR_Pos (0U)
		6257	#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /!< 0xFFFFFFFF /
		6258	#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /!< FPEC Key /
2	mjames	6259
5	mjames	6260	#define RDP_KEY_Pos (0U)
		6261	#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /!< 0x000000A5 /
		6262	#define RDP_KEY RDP_KEY_Msk /!< RDP Key /
		6263	#define FLASH_KEY1_Pos (0U)
		6264	#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /!< 0x45670123 /
		6265	#define FLASH_KEY1 FLASH_KEY1_Msk /!< FPEC Key1 /
		6266	#define FLASH_KEY2_Pos (0U)
		6267	#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /!< 0xCDEF89AB /
		6268	#define FLASH_KEY2 FLASH_KEY2_Msk /!< FPEC Key2 /
2	mjames	6269
		6270	/*************** Bit definition for FLASH_OPTKEYR register **************/
5	mjames	6271	#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
		6272	#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /!< 0xFFFFFFFF /
		6273	#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /!< Option Byte Key /
2	mjames	6274
		6275	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
		6276	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
		6277
		6278	/**************** Bit definition for FLASH_SR register ******************/
5	mjames	6279	#define FLASH_SR_BSY_Pos (0U)
		6280	#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /!< 0x00000001 /
		6281	#define FLASH_SR_BSY FLASH_SR_BSY_Msk /!< Busy /
		6282	#define FLASH_SR_PGERR_Pos (2U)
		6283	#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /!< 0x00000004 /
		6284	#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /!< Programming Error /
		6285	#define FLASH_SR_WRPRTERR_Pos (4U)
		6286	#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /!< 0x00000010 /
		6287	#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /!< Write Protection Error /
		6288	#define FLASH_SR_EOP_Pos (5U)
		6289	#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /!< 0x00000020 /
		6290	#define FLASH_SR_EOP FLASH_SR_EOP_Msk /!< End of operation /
2	mjames	6291
		6292	/***************** Bit definition for FLASH_CR register *****************/
5	mjames	6293	#define FLASH_CR_PG_Pos (0U)
		6294	#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /!< 0x00000001 /
		6295	#define FLASH_CR_PG FLASH_CR_PG_Msk /!< Programming /
		6296	#define FLASH_CR_PER_Pos (1U)
		6297	#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /!< 0x00000002 /
		6298	#define FLASH_CR_PER FLASH_CR_PER_Msk /!< Page Erase /
		6299	#define FLASH_CR_MER_Pos (2U)
		6300	#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /!< 0x00000004 /
		6301	#define FLASH_CR_MER FLASH_CR_MER_Msk /!< Mass Erase /
		6302	#define FLASH_CR_OPTPG_Pos (4U)
		6303	#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /!< 0x00000010 /
		6304	#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /!< Option Byte Programming /
		6305	#define FLASH_CR_OPTER_Pos (5U)
		6306	#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /!< 0x00000020 /
		6307	#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /!< Option Byte Erase /
		6308	#define FLASH_CR_STRT_Pos (6U)
		6309	#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /!< 0x00000040 /
		6310	#define FLASH_CR_STRT FLASH_CR_STRT_Msk /!< Start /
		6311	#define FLASH_CR_LOCK_Pos (7U)
		6312	#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /!< 0x00000080 /
		6313	#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /!< Lock /
		6314	#define FLASH_CR_OPTWRE_Pos (9U)
		6315	#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /!< 0x00000200 /
		6316	#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /!< Option Bytes Write Enable /
		6317	#define FLASH_CR_ERRIE_Pos (10U)
		6318	#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /!< 0x00000400 /
		6319	#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /!< Error Interrupt Enable /
		6320	#define FLASH_CR_EOPIE_Pos (12U)
		6321	#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /!< 0x00001000 /
		6322	#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /!< End of operation interrupt enable /
2	mjames	6323
		6324	/***************** Bit definition for FLASH_AR register *****************/
5	mjames	6325	#define FLASH_AR_FAR_Pos (0U)
		6326	#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /!< 0xFFFFFFFF /
		6327	#define FLASH_AR_FAR FLASH_AR_FAR_Msk /!< Flash Address /
2	mjames	6328
		6329	/**************** Bit definition for FLASH_OBR register *****************/
5	mjames	6330	#define FLASH_OBR_OPTERR_Pos (0U)
		6331	#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /!< 0x00000001 /
		6332	#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /!< Option Byte Error /
		6333	#define FLASH_OBR_RDPRT_Pos (1U)
		6334	#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /!< 0x00000002 /
		6335	#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /!< Read protection /
2	mjames	6336
5	mjames	6337	#define FLASH_OBR_IWDG_SW_Pos (2U)
		6338	#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /!< 0x00000004 /
		6339	#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /!< IWDG SW /
		6340	#define FLASH_OBR_nRST_STOP_Pos (3U)
		6341	#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /!< 0x00000008 /
		6342	#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /!< nRST_STOP /
		6343	#define FLASH_OBR_nRST_STDBY_Pos (4U)
		6344	#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /!< 0x00000010 /
		6345	#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /!< nRST_STDBY /
		6346	#define FLASH_OBR_USER_Pos (2U)
		6347	#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /!< 0x0000001C /
		6348	#define FLASH_OBR_USER FLASH_OBR_USER_Msk /!< User Option Bytes /
		6349	#define FLASH_OBR_DATA0_Pos (10U)
		6350	#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /!< 0x0003FC00 /
		6351	#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /!< Data0 /
		6352	#define FLASH_OBR_DATA1_Pos (18U)
		6353	#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /!< 0x03FC0000 /
		6354	#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /!< Data1 /
2	mjames	6355
		6356	/**************** Bit definition for FLASH_WRPR register ****************/
5	mjames	6357	#define FLASH_WRPR_WRP_Pos (0U)
		6358	#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /!< 0xFFFFFFFF /
		6359	#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /!< Write Protect /
2	mjames	6360
		6361	/----------------------------------------------------------------------------/
		6362
		6363	/**************** Bit definition for FLASH_RDP register *****************/
5	mjames	6364	#define FLASH_RDP_RDP_Pos (0U)
		6365	#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /!< 0x000000FF /
		6366	#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /!< Read protection option byte /
		6367	#define FLASH_RDP_nRDP_Pos (8U)
		6368	#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /!< 0x0000FF00 /
		6369	#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /!< Read protection complemented option byte /
2	mjames	6370
		6371	/**************** Bit definition for FLASH_USER register ****************/
5	mjames	6372	#define FLASH_USER_USER_Pos (16U)
		6373	#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /!< 0x00FF0000 /
		6374	#define FLASH_USER_USER FLASH_USER_USER_Msk /!< User option byte /
		6375	#define FLASH_USER_nUSER_Pos (24U)
		6376	#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /!< 0xFF000000 /
		6377	#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /!< User complemented option byte /
2	mjames	6378
		6379	/**************** Bit definition for FLASH_Data0 register ***************/
5	mjames	6380	#define FLASH_DATA0_DATA0_Pos (0U)
		6381	#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /!< 0x000000FF /
		6382	#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /!< User data storage option byte /
		6383	#define FLASH_DATA0_nDATA0_Pos (8U)
		6384	#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /!< 0x0000FF00 /
		6385	#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /!< User data storage complemented option byte /
2	mjames	6386
		6387	/**************** Bit definition for FLASH_Data1 register ***************/
5	mjames	6388	#define FLASH_DATA1_DATA1_Pos (16U)
		6389	#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /!< 0x00FF0000 /
		6390	#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /!< User data storage option byte /
		6391	#define FLASH_DATA1_nDATA1_Pos (24U)
		6392	#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /!< 0xFF000000 /
		6393	#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /!< User data storage complemented option byte /
2	mjames	6394
		6395	/**************** Bit definition for FLASH_WRP0 register ****************/
5	mjames	6396	#define FLASH_WRP0_WRP0_Pos (0U)
		6397	#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /!< 0x000000FF /
		6398	#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /!< Flash memory write protection option bytes /
		6399	#define FLASH_WRP0_nWRP0_Pos (8U)
		6400	#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /!< 0x0000FF00 /
		6401	#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /!< Flash memory write protection complemented option bytes /
2	mjames	6402
		6403	/**************** Bit definition for FLASH_WRP1 register ****************/
5	mjames	6404	#define FLASH_WRP1_WRP1_Pos (16U)
		6405	#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /!< 0x00FF0000 /
		6406	#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /!< Flash memory write protection option bytes /
		6407	#define FLASH_WRP1_nWRP1_Pos (24U)
		6408	#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /!< 0xFF000000 /
		6409	#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /!< Flash memory write protection complemented option bytes /
2	mjames	6410
		6411	/**************** Bit definition for FLASH_WRP2 register ****************/
5	mjames	6412	#define FLASH_WRP2_WRP2_Pos (0U)
		6413	#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /!< 0x000000FF /
		6414	#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /!< Flash memory write protection option bytes /
		6415	#define FLASH_WRP2_nWRP2_Pos (8U)
		6416	#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /!< 0x0000FF00 /
		6417	#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /!< Flash memory write protection complemented option bytes /
2	mjames	6418
		6419	/**************** Bit definition for FLASH_WRP3 register ****************/
5	mjames	6420	#define FLASH_WRP3_WRP3_Pos (16U)
		6421	#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /!< 0x00FF0000 /
		6422	#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /!< Flash memory write protection option bytes /
		6423	#define FLASH_WRP3_nWRP3_Pos (24U)
		6424	#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /!< 0xFF000000 /
		6425	#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /!< Flash memory write protection complemented option bytes /
2	mjames	6426
		6427
		6428
		6429	/**
		6430	* @}
		6431	*/
		6432
		6433	/**
		6434	* @}
		6435	*/
		6436
		6437	/** @addtogroup Exported_macro
		6438	* @{
		6439	*/
		6440
		6441	/**************************** ADC Instances *******************************/
		6442	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
		6443
5	mjames	6444	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
		6445
2	mjames	6446	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		6447
		6448	/**************************** CEC Instances *******************************/
		6449	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
		6450
		6451	/**************************** CRC Instances *******************************/
		6452	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		6453
		6454	/**************************** DAC Instances *******************************/
		6455	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
		6456
		6457	/**************************** DMA Instances *******************************/
		6458	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		6459	((INSTANCE) == DMA1_Channel2) \|\| \
		6460	((INSTANCE) == DMA1_Channel3) \|\| \
		6461	((INSTANCE) == DMA1_Channel4) \|\| \
		6462	((INSTANCE) == DMA1_Channel5) \|\| \
		6463	((INSTANCE) == DMA1_Channel6) \|\| \
		6464	((INSTANCE) == DMA1_Channel7))
		6465
		6466	/***************************** GPIO Instances *****************************/
		6467	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		6468	((INSTANCE) == GPIOB) \|\| \
		6469	((INSTANCE) == GPIOC) \|\| \
		6470	((INSTANCE) == GPIOD) \|\| \
		6471	((INSTANCE) == GPIOE))
		6472
		6473	/************************** GPIO Alternate Function Instances *************/
		6474	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		6475
		6476	/************************** GPIO Lock Instances ***************************/
		6477	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		6478
		6479	/****************************** I2C Instances *****************************/
		6480	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		6481	((INSTANCE) == I2C2))
		6482
		6483	/**************************** IWDG Instances ******************************/
		6484	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		6485
		6486	/****************************** SPI Instances *****************************/
		6487	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		6488	((INSTANCE) == SPI2))
		6489
		6490	/**************************** START TIM Instances *************************/
		6491	/**************************** TIM Instances *******************************/
		6492	#define IS_TIM_INSTANCE(INSTANCE)\
		6493	(((INSTANCE) == TIM1) \|\| \
		6494	((INSTANCE) == TIM2) \|\| \
		6495	((INSTANCE) == TIM3) \|\| \
		6496	((INSTANCE) == TIM4) \|\| \
		6497	((INSTANCE) == TIM6) \|\| \
		6498	((INSTANCE) == TIM7) \|\| \
		6499	((INSTANCE) == TIM15) \|\| \
		6500	((INSTANCE) == TIM16) \|\| \
		6501	((INSTANCE) == TIM17))
		6502
		6503	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
		6504	(((INSTANCE) == TIM1) \|\| \
		6505	((INSTANCE) == TIM2) \|\| \
		6506	((INSTANCE) == TIM3) \|\| \
		6507	((INSTANCE) == TIM4) \|\| \
		6508	((INSTANCE) == TIM15) \|\| \
		6509	((INSTANCE) == TIM16) \|\| \
		6510	((INSTANCE) == TIM17))
		6511
		6512	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
		6513	(((INSTANCE) == TIM1) \|\| \
		6514	((INSTANCE) == TIM2) \|\| \
		6515	((INSTANCE) == TIM3) \|\| \
		6516	((INSTANCE) == TIM4) \|\| \
		6517	((INSTANCE) == TIM15))
		6518
		6519	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
		6520	(((INSTANCE) == TIM1) \|\| \
		6521	((INSTANCE) == TIM2) \|\| \
		6522	((INSTANCE) == TIM3) \|\| \
		6523	((INSTANCE) == TIM4))
		6524
		6525	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
		6526	(((INSTANCE) == TIM1) \|\| \
		6527	((INSTANCE) == TIM2) \|\| \
		6528	((INSTANCE) == TIM3) \|\| \
		6529	((INSTANCE) == TIM4))
		6530
		6531	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
		6532	(((INSTANCE) == TIM1) \|\| \
		6533	((INSTANCE) == TIM2) \|\| \
		6534	((INSTANCE) == TIM3) \|\| \
		6535	((INSTANCE) == TIM4))
		6536
		6537	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
		6538	(((INSTANCE) == TIM1) \|\| \
		6539	((INSTANCE) == TIM2) \|\| \
		6540	((INSTANCE) == TIM3) \|\| \
		6541	((INSTANCE) == TIM4))
		6542
		6543	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
		6544	(((INSTANCE) == TIM1) \|\| \
		6545	((INSTANCE) == TIM2) \|\| \
		6546	((INSTANCE) == TIM3) \|\| \
		6547	((INSTANCE) == TIM4) \|\| \
		6548	((INSTANCE) == TIM15))
		6549
		6550	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
		6551	(((INSTANCE) == TIM1) \|\| \
		6552	((INSTANCE) == TIM2) \|\| \
		6553	((INSTANCE) == TIM3) \|\| \
		6554	((INSTANCE) == TIM4) \|\| \
		6555	((INSTANCE) == TIM15))
		6556
		6557	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
		6558	(((INSTANCE) == TIM1) \|\| \
		6559	((INSTANCE) == TIM2) \|\| \
		6560	((INSTANCE) == TIM3) \|\| \
		6561	((INSTANCE) == TIM4))
		6562
		6563	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
		6564	(((INSTANCE) == TIM1) \|\| \
		6565	((INSTANCE) == TIM2) \|\| \
		6566	((INSTANCE) == TIM3) \|\| \
		6567	((INSTANCE) == TIM4))
		6568
		6569	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
		6570	(((INSTANCE) == TIM1) \|\| \
		6571	((INSTANCE) == TIM2) \|\| \
		6572	((INSTANCE) == TIM3) \|\| \
		6573	((INSTANCE) == TIM4))
		6574
		6575	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
		6576	(((INSTANCE) == TIM1) \|\| \
		6577	((INSTANCE) == TIM2) \|\| \
		6578	((INSTANCE) == TIM3) \|\| \
		6579	((INSTANCE) == TIM4) \|\| \
		6580	((INSTANCE) == TIM6) \|\| \
		6581	((INSTANCE) == TIM7) \|\| \
		6582	((INSTANCE) == TIM15))
		6583
		6584	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
		6585	(((INSTANCE) == TIM1) \|\| \
		6586	((INSTANCE) == TIM2) \|\| \
		6587	((INSTANCE) == TIM3) \|\| \
		6588	((INSTANCE) == TIM4) \|\| \
		6589	((INSTANCE) == TIM15))
		6590
		6591	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
		6592	(((INSTANCE) == TIM1) \|\| \
		6593	((INSTANCE) == TIM2) \|\| \
		6594	((INSTANCE) == TIM3) \|\| \
		6595	((INSTANCE) == TIM4) \|\| \
		6596	((INSTANCE) == TIM15) \|\| \
		6597	((INSTANCE) == TIM16) \|\| \
		6598	((INSTANCE) == TIM17))
		6599
		6600	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
		6601	(((INSTANCE) == TIM1) \|\| \
		6602	((INSTANCE) == TIM15) \|\| \
		6603	((INSTANCE) == TIM16) \|\| \
		6604	((INSTANCE) == TIM17))
		6605
		6606	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		6607	((((INSTANCE) == TIM1) && \
		6608	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6609	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6610	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6611	((CHANNEL) == TIM_CHANNEL_4))) \
		6612	\|\| \
		6613	(((INSTANCE) == TIM2) && \
		6614	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6615	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6616	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6617	((CHANNEL) == TIM_CHANNEL_4))) \
		6618	\|\| \
		6619	(((INSTANCE) == TIM3) && \
		6620	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6621	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6622	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6623	((CHANNEL) == TIM_CHANNEL_4))) \
		6624	\|\| \
		6625	(((INSTANCE) == TIM4) && \
		6626	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6627	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6628	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6629	((CHANNEL) == TIM_CHANNEL_4))) \
		6630	\|\| \
		6631	(((INSTANCE) == TIM15) && \
		6632	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6633	((CHANNEL) == TIM_CHANNEL_2))) \
		6634	\|\| \
		6635	(((INSTANCE) == TIM16) && \
		6636	(((CHANNEL) == TIM_CHANNEL_1))) \
		6637	\|\| \
		6638	(((INSTANCE) == TIM17) && \
		6639	(((CHANNEL) == TIM_CHANNEL_1))))
		6640
		6641	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
		6642	((((INSTANCE) == TIM1) && \
		6643	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6644	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6645	((CHANNEL) == TIM_CHANNEL_3))) \
		6646	\|\| \
		6647	(((INSTANCE) == TIM15) && \
		6648	((CHANNEL) == TIM_CHANNEL_1)) \
		6649	\|\| \
		6650	(((INSTANCE) == TIM16) && \
		6651	((CHANNEL) == TIM_CHANNEL_1)) \
		6652	\|\| \
		6653	(((INSTANCE) == TIM17) && \
		6654	((CHANNEL) == TIM_CHANNEL_1)))
		6655
		6656	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
		6657	(((INSTANCE) == TIM1) \|\| \
		6658	((INSTANCE) == TIM2) \|\| \
		6659	((INSTANCE) == TIM3) \|\| \
		6660	((INSTANCE) == TIM4))
		6661
		6662	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
		6663	(((INSTANCE) == TIM1) \|\| \
		6664	((INSTANCE) == TIM15) \|\| \
		6665	((INSTANCE) == TIM16) \|\| \
		6666	((INSTANCE) == TIM17))
		6667
		6668	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
		6669	(((INSTANCE) == TIM1) \|\| \
		6670	((INSTANCE) == TIM2) \|\| \
		6671	((INSTANCE) == TIM3) \|\| \
		6672	((INSTANCE) == TIM4) \|\| \
		6673	((INSTANCE) == TIM15) \|\| \
		6674	((INSTANCE) == TIM16) \|\| \
		6675	((INSTANCE) == TIM17))
		6676
		6677	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
		6678	(((INSTANCE) == TIM1) \|\| \
		6679	((INSTANCE) == TIM2) \|\| \
		6680	((INSTANCE) == TIM3) \|\| \
		6681	((INSTANCE) == TIM4) \|\| \
		6682	((INSTANCE) == TIM6) \|\| \
		6683	((INSTANCE) == TIM7) \|\| \
		6684	((INSTANCE) == TIM15) \|\| \
		6685	((INSTANCE) == TIM16) \|\| \
		6686	((INSTANCE) == TIM17))
		6687
		6688	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
		6689	(((INSTANCE) == TIM1) \|\| \
		6690	((INSTANCE) == TIM2) \|\| \
		6691	((INSTANCE) == TIM3) \|\| \
		6692	((INSTANCE) == TIM4) \|\| \
		6693	((INSTANCE) == TIM15) \|\| \
		6694	((INSTANCE) == TIM16) \|\| \
		6695	((INSTANCE) == TIM17))
		6696
		6697	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
		6698	(((INSTANCE) == TIM1) \|\| \
		6699	((INSTANCE) == TIM15) \|\| \
		6700	((INSTANCE) == TIM16) \|\| \
		6701	((INSTANCE) == TIM17))
		6702
		6703	/**************************** END TIM Instances ***************************/
		6704
		6705
		6706	/****************** USART Instances : Synchronous mode ********************/
		6707	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6708	((INSTANCE) == USART2) \|\| \
		6709	((INSTANCE) == USART3))
		6710
		6711	/****************** UART Instances : Asynchronous mode ********************/
		6712	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6713	((INSTANCE) == USART2) \|\| \
		6714	((INSTANCE) == USART3))
		6715
		6716	/****************** UART Instances : Half-Duplex mode ********************/
		6717	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6718	((INSTANCE) == USART2) \|\| \
		6719	((INSTANCE) == USART3))
		6720
		6721	/****************** UART Instances : LIN mode ********************/
		6722	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6723	((INSTANCE) == USART2) \|\| \
		6724	((INSTANCE) == USART3))
		6725
		6726	/**************** UART Instances : Hardware Flow control ******************/
		6727	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6728	((INSTANCE) == USART2) \|\| \
		6729	((INSTANCE) == USART3))
		6730
		6731	/******************* UART Instances : Smard card mode *********************/
		6732	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6733	((INSTANCE) == USART2) \|\| \
		6734	((INSTANCE) == USART3))
		6735
		6736	/********************* UART Instances : IRDA mode *************************/
		6737	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6738	((INSTANCE) == USART2) \|\| \
		6739	((INSTANCE) == USART3))
		6740
		6741	/*************** UART Instances : Multi-Processor mode ********************/
		6742	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6743	((INSTANCE) == USART2) \|\| \
		6744	((INSTANCE) == USART3))
		6745
		6746	/*************** UART Instances : DMA mode available ********************/
		6747	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6748	((INSTANCE) == USART2) \|\| \
		6749	((INSTANCE) == USART3))
		6750
		6751	/**************************** RTC Instances *******************************/
		6752	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		6753
		6754	/************************** WWDG Instances ***************************/
		6755	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		6756
		6757
		6758
		6759
		6760
		6761	/**
		6762	* @}
		6763	*/
		6764	/******************************************************************************/
		6765	/* For a painless codes migration between the STM32F1xx device product */
		6766	/* lines, the aliases defined below are put in place to overcome the */
		6767	/* differences in the interrupt handlers and IRQn definitions. */
		6768	/* No need to update developed interrupt code when moving across */
		6769	/* product lines within the same STM32F1 Family */
		6770	/******************************************************************************/
		6771
		6772	/* Aliases for __IRQn */
		6773	#define ADC1_2_IRQn ADC1_IRQn
		6774	#define USBWakeUp_IRQn CEC_IRQn
		6775	#define OTG_FS_WKUP_IRQn CEC_IRQn
		6776	#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
		6777	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
		6778	#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
		6779	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
		6780	#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
		6781	#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
		6782	#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
		6783	#define TIM10_IRQn TIM1_UP_TIM16_IRQn
		6784	#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
		6785	#define TIM6_IRQn TIM6_DAC_IRQn
		6786
		6787
		6788	/* Aliases for __IRQHandler */
		6789	#define ADC1_2_IRQHandler ADC1_IRQHandler
		6790	#define USBWakeUp_IRQHandler CEC_IRQHandler
		6791	#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
		6792	#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
		6793	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
		6794	#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
		6795	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		6796	#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		6797	#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		6798	#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
		6799	#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
		6800	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
		6801	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
		6802
		6803
		6804	/**
		6805	* @}
		6806	*/
		6807
		6808	/**
		6809	* @}
		6810	*/
		6811
		6812
		6813	#ifdef __cplusplus
		6814	}
		6815	#endif /* __cplusplus */
		6816
		6817	#endif /* __STM32F100xB_H */
		6818
		6819
		6820
		6821	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h – Rev 5