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Rev	Author	Line No.	Line
2	mjames	1	;*******************************************************************************
		2	; File Name : startup_stm32f070x6.s*
		3	; Author : MCD Application Team*
		4	; Description : STM32F070x4/STM32F070x6 devices vector table for MDK-ARM toolchain.*
		5	; This module performs:*
		6	; - Set the initial SP*
		7	; - Set the initial PC == Reset_Handler*
		8	; - Set the vector table entries with the exceptions ISR address*
		9	; - Branches to __main in the C library (which eventually*
		10	; calls main()).*
		11	; After Reset the CortexM0 processor is in Thread mode,*
		12	; priority is Privileged, and the Stack is set to Main.*
		13	;********************************************************************************
		14	; @attention*
		15	;*
		16	; Copyright (c) 2016 STMicroelectronics.*
		17	; All rights reserved.*
		18	;*
		19	; This software component is licensed by ST under BSD 3-Clause license,*
		20	; the "License"; You may not use this file except in compliance with the*
		21	; License. You may obtain a copy of the License at:*
		22	; opensource.org/licenses/BSD-3-Clause*
		23	;*
		24	;*******************************************************************************
		25	; <<< Use Configuration Wizard in Context Menu >>>*
		26	;
		27
		28	; Amount of memory (in bytes) allocated for Stack
		29	; Tailor this value to your application needs
		30	; <h> Stack Configuration
		31	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
		32	; </h>
		33
		34	Stack_Size EQU 0x00000400
		35
		36	AREA STACK, NOINIT, READWRITE, ALIGN=3
		37	Stack_Mem SPACE Stack_Size
		38	__initial_sp
		39
		40
		41	; <h> Heap Configuration
		42	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
		43	; </h>
		44
		45	Heap_Size EQU 0x00000200
		46
		47	AREA HEAP, NOINIT, READWRITE, ALIGN=3
		48	__heap_base
		49	Heap_Mem SPACE Heap_Size
		50	__heap_limit
		51
		52	PRESERVE8
		53	THUMB
		54
		55
		56	; Vector Table Mapped to Address 0 at Reset
		57	AREA RESET, DATA, READONLY
		58	EXPORT __Vectors
		59	EXPORT __Vectors_End
		60	EXPORT __Vectors_Size
		61
		62	__Vectors DCD __initial_sp ; Top of Stack
		63	DCD Reset_Handler ; Reset Handler
		64	DCD NMI_Handler ; NMI Handler
		65	DCD HardFault_Handler ; Hard Fault Handler
		66	DCD 0 ; Reserved
		67	DCD 0 ; Reserved
		68	DCD 0 ; Reserved
		69	DCD 0 ; Reserved
		70	DCD 0 ; Reserved
		71	DCD 0 ; Reserved
		72	DCD 0 ; Reserved
		73	DCD SVC_Handler ; SVCall Handler
		74	DCD 0 ; Reserved
		75	DCD 0 ; Reserved
		76	DCD PendSV_Handler ; PendSV Handler
		77	DCD SysTick_Handler ; SysTick Handler
		78
		79	; External Interrupts
		80	DCD WWDG_IRQHandler ; Window Watchdog
		81	DCD 0 ; Reserved
		82	DCD RTC_IRQHandler ; RTC through EXTI Line
		83	DCD FLASH_IRQHandler ; FLASH
		84	DCD RCC_IRQHandler ; RCC
		85	DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
		86	DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
		87	DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
		88	DCD 0 ; Reserved
		89	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		90	DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
		91	DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
		92	DCD ADC1_IRQHandler ; ADC1
		93	DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
		94	DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
		95	DCD 0 ; Reserved
		96	DCD TIM3_IRQHandler ; TIM3
		97	DCD 0 ; Reserved
		98	DCD 0 ; Reserved
		99	DCD TIM14_IRQHandler ; TIM14
		100	DCD 0 ; Reserved
		101	DCD TIM16_IRQHandler ; TIM16
		102	DCD TIM17_IRQHandler ; TIM17
		103	DCD I2C1_IRQHandler ; I2C1
		104	DCD 0 ; Reserved
		105	DCD SPI1_IRQHandler ; SPI1
		106	DCD 0 ; Reserved
		107	DCD USART1_IRQHandler ; USART1
		108	DCD USART2_IRQHandler ; USART2
		109	DCD 0 ; Reserved
		110	DCD 0 ; Reserved
		111	DCD USB_IRQHandler ; USB
		112
		113	__Vectors_End
		114
		115	__Vectors_Size EQU __Vectors_End - __Vectors
		116
		117	AREA \|.text\|, CODE, READONLY
		118
		119	; Reset handler routine
		120	Reset_Handler PROC
		121	EXPORT Reset_Handler [WEAK]
		122	IMPORT __main
		123	IMPORT SystemInit
		124
		125
		126
		127	LDR R0, =__initial_sp ; set stack pointer
		128	MSR MSP, R0
		129
		130	;;Check if boot space corresponds to test memory
		131
		132	LDR R0,=0x00000004
		133	LDR R1, [R0]
		134	LSRS R1, R1, #24
		135	LDR R2,=0x1F
		136	CMP R1, R2
		137
		138	BNE ApplicationStart
		139
		140	;; SYSCFG clock enable
		141
		142	LDR R0,=0x40021018
		143	LDR R1,=0x00000001
		144	STR R1, [R0]
		145
		146	;; Set CFGR1 register with flash memory remap at address 0
		147
		148	LDR R0,=0x40010000
		149	LDR R1,=0x00000000
		150	STR R1, [R0]
		151	ApplicationStart
		152	LDR R0, =SystemInit
		153	BLX R0
		154	LDR R0, =__main
		155	BX R0
		156	ENDP
		157
		158	; Dummy Exception Handlers (infinite loops which can be modified)
		159
		160	NMI_Handler PROC
		161	EXPORT NMI_Handler [WEAK]
		162	B .
		163	ENDP
		164	HardFault_Handler\
		165	PROC
		166	EXPORT HardFault_Handler [WEAK]
		167	B .
		168	ENDP
		169	SVC_Handler PROC
		170	EXPORT SVC_Handler [WEAK]
		171	B .
		172	ENDP
		173	PendSV_Handler PROC
		174	EXPORT PendSV_Handler [WEAK]
		175	B .
		176	ENDP
		177	SysTick_Handler PROC
		178	EXPORT SysTick_Handler [WEAK]
		179	B .
		180	ENDP
		181
		182	Default_Handler PROC
		183
		184	EXPORT WWDG_IRQHandler [WEAK]
		185	EXPORT RTC_IRQHandler [WEAK]
		186	EXPORT FLASH_IRQHandler [WEAK]
		187	EXPORT RCC_IRQHandler [WEAK]
		188	EXPORT EXTI0_1_IRQHandler [WEAK]
		189	EXPORT EXTI2_3_IRQHandler [WEAK]
		190	EXPORT EXTI4_15_IRQHandler [WEAK]
		191	EXPORT DMA1_Channel1_IRQHandler [WEAK]
		192	EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
		193	EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
		194	EXPORT ADC1_IRQHandler [WEAK]
		195	EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
		196	EXPORT TIM1_CC_IRQHandler [WEAK]
		197	EXPORT TIM3_IRQHandler [WEAK]
		198	EXPORT TIM14_IRQHandler [WEAK]
		199	EXPORT TIM16_IRQHandler [WEAK]
		200	EXPORT TIM17_IRQHandler [WEAK]
		201	EXPORT I2C1_IRQHandler [WEAK]
		202	EXPORT SPI1_IRQHandler [WEAK]
		203	EXPORT USART1_IRQHandler [WEAK]
		204	EXPORT USART2_IRQHandler [WEAK]
		205	EXPORT USB_IRQHandler [WEAK]
		206
		207
		208	WWDG_IRQHandler
		209	RTC_IRQHandler
		210	FLASH_IRQHandler
		211	RCC_IRQHandler
		212	EXTI0_1_IRQHandler
		213	EXTI2_3_IRQHandler
		214	EXTI4_15_IRQHandler
		215	DMA1_Channel1_IRQHandler
		216	DMA1_Channel2_3_IRQHandler
		217	DMA1_Channel4_5_IRQHandler
		218	ADC1_IRQHandler
		219	TIM1_BRK_UP_TRG_COM_IRQHandler
		220	TIM1_CC_IRQHandler
		221	TIM3_IRQHandler
		222	TIM14_IRQHandler
		223	TIM16_IRQHandler
		224	TIM17_IRQHandler
		225	I2C1_IRQHandler
		226	SPI1_IRQHandler
		227	USART1_IRQHandler
		228	USART2_IRQHandler
		229	USB_IRQHandler
		230
		231	B .
		232
		233	ENDP
		234
		235	ALIGN
		236
		237	;*******************************************************************************
		238	; User Stack and Heap initialization
		239	;*******************************************************************************
		240	IF :DEF:__MICROLIB
		241
		242	EXPORT __initial_sp
		243	EXPORT __heap_base
		244	EXPORT __heap_limit
		245
		246	ELSE
		247
		248	IMPORT __use_two_region_memory
		249	EXPORT __user_initial_stackheap
		250
		251	__user_initial_stackheap
		252
		253	LDR R0, = Heap_Mem
		254	LDR R1, =(Stack_Mem + Stack_Size)
		255	LDR R2, = (Heap_Mem + Heap_Size)
		256	LDR R3, = Stack_Mem
		257	BX LR
		258
		259	ALIGN
		260
		261	ENDIF
		262
		263	END
		264
		265	;********************** (C) COPYRIGHT STMicroelectronics *END OF FILE***

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f070x6.s – Rev 2