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Rev	Author	Line No.	Line
2	mjames	1	;*******************************************************************************
		2	; File Name : startup_stm32f051x8.s*
		3	; Author : MCD Application Team*
		4	; Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain.*
		5	; This module performs:*
		6	; - Set the initial SP*
		7	; - Set the initial PC == Reset_Handler*
		8	; - Set the vector table entries with the exceptions ISR address*
		9	; - Branches to __main in the C library (which eventually*
		10	; calls main()).*
		11	; After Reset the CortexM0 processor is in Thread mode,*
		12	; priority is Privileged, and the Stack is set to Main.*
		13	;********************************************************************************
		14	; @attention*
		15	;*
		16	; Copyright (c) 2016 STMicroelectronics.*
		17	; All rights reserved.*
		18	;*
		19	; This software component is licensed by ST under BSD 3-Clause license,*
		20	; the "License"; You may not use this file except in compliance with the*
		21	; License. You may obtain a copy of the License at:*
		22	; opensource.org/licenses/BSD-3-Clause*
		23	;*
		24	;*******************************************************************************
		25	; <<< Use Configuration Wizard in Context Menu >>>*
		26	;
		27
		28	; Amount of memory (in bytes) allocated for Stack
		29	; Tailor this value to your application needs
		30	; <h> Stack Configuration
		31	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
		32	; </h>
		33
		34	Stack_Size EQU 0x00000400
		35
		36	AREA STACK, NOINIT, READWRITE, ALIGN=3
		37	Stack_Mem SPACE Stack_Size
		38	__initial_sp
		39
		40
		41	; <h> Heap Configuration
		42	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
		43	; </h>
		44
		45	Heap_Size EQU 0x00000200
		46
		47	AREA HEAP, NOINIT, READWRITE, ALIGN=3
		48	__heap_base
		49	Heap_Mem SPACE Heap_Size
		50	__heap_limit
		51
		52	PRESERVE8
		53	THUMB
		54
		55
		56	; Vector Table Mapped to Address 0 at Reset
		57	AREA RESET, DATA, READONLY
		58	EXPORT __Vectors
		59	EXPORT __Vectors_End
		60	EXPORT __Vectors_Size
		61
		62	__Vectors DCD __initial_sp ; Top of Stack
		63	DCD Reset_Handler ; Reset Handler
		64	DCD NMI_Handler ; NMI Handler
		65	DCD HardFault_Handler ; Hard Fault Handler
		66	DCD 0 ; Reserved
		67	DCD 0 ; Reserved
		68	DCD 0 ; Reserved
		69	DCD 0 ; Reserved
		70	DCD 0 ; Reserved
		71	DCD 0 ; Reserved
		72	DCD 0 ; Reserved
		73	DCD SVC_Handler ; SVCall Handler
		74	DCD 0 ; Reserved
		75	DCD 0 ; Reserved
		76	DCD PendSV_Handler ; PendSV Handler
		77	DCD SysTick_Handler ; SysTick Handler
		78
		79	; External Interrupts
		80	DCD WWDG_IRQHandler ; Window Watchdog
		81	DCD PVD_IRQHandler ; PVD through EXTI Line detect
		82	DCD RTC_IRQHandler ; RTC through EXTI Line
		83	DCD FLASH_IRQHandler ; FLASH
		84	DCD RCC_IRQHandler ; RCC
		85	DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
		86	DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
		87	DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
		88	DCD TSC_IRQHandler ; TS
		89	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		90	DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
		91	DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
		92	DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
		93	DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
		94	DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
		95	DCD TIM2_IRQHandler ; TIM2
		96	DCD TIM3_IRQHandler ; TIM3
		97	DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
		98	DCD 0 ; Reserved
		99	DCD TIM14_IRQHandler ; TIM14
		100	DCD TIM15_IRQHandler ; TIM15
		101	DCD TIM16_IRQHandler ; TIM16
		102	DCD TIM17_IRQHandler ; TIM17
		103	DCD I2C1_IRQHandler ; I2C1
		104	DCD I2C2_IRQHandler ; I2C2
		105	DCD SPI1_IRQHandler ; SPI1
		106	DCD SPI2_IRQHandler ; SPI2
		107	DCD USART1_IRQHandler ; USART1
		108	DCD USART2_IRQHandler ; USART2
		109	DCD 0 ; Reserved
		110	DCD CEC_IRQHandler ; CEC
		111
		112	__Vectors_End
		113
		114	__Vectors_Size EQU __Vectors_End - __Vectors
		115
		116	AREA \|.text\|, CODE, READONLY
		117
		118	; Reset handler routine
		119	Reset_Handler PROC
		120	EXPORT Reset_Handler [WEAK]
		121	IMPORT __main
		122	IMPORT SystemInit
		123	LDR R0, =SystemInit
		124	BLX R0
		125	LDR R0, =__main
		126	BX R0
		127	ENDP
		128
		129	; Dummy Exception Handlers (infinite loops which can be modified)
		130
		131	NMI_Handler PROC
		132	EXPORT NMI_Handler [WEAK]
		133	B .
		134	ENDP
		135	HardFault_Handler\
		136	PROC
		137	EXPORT HardFault_Handler [WEAK]
		138	B .
		139	ENDP
		140	SVC_Handler PROC
		141	EXPORT SVC_Handler [WEAK]
		142	B .
		143	ENDP
		144	PendSV_Handler PROC
		145	EXPORT PendSV_Handler [WEAK]
		146	B .
		147	ENDP
		148	SysTick_Handler PROC
		149	EXPORT SysTick_Handler [WEAK]
		150	B .
		151	ENDP
		152
		153	Default_Handler PROC
		154
		155	EXPORT WWDG_IRQHandler [WEAK]
		156	EXPORT PVD_IRQHandler [WEAK]
		157	EXPORT RTC_IRQHandler [WEAK]
		158	EXPORT FLASH_IRQHandler [WEAK]
		159	EXPORT RCC_IRQHandler [WEAK]
		160	EXPORT EXTI0_1_IRQHandler [WEAK]
		161	EXPORT EXTI2_3_IRQHandler [WEAK]
		162	EXPORT EXTI4_15_IRQHandler [WEAK]
		163	EXPORT TSC_IRQHandler [WEAK]
		164	EXPORT DMA1_Channel1_IRQHandler [WEAK]
		165	EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
		166	EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
		167	EXPORT ADC1_COMP_IRQHandler [WEAK]
		168	EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
		169	EXPORT TIM1_CC_IRQHandler [WEAK]
		170	EXPORT TIM2_IRQHandler [WEAK]
		171	EXPORT TIM3_IRQHandler [WEAK]
		172	EXPORT TIM6_DAC_IRQHandler [WEAK]
		173	EXPORT TIM14_IRQHandler [WEAK]
		174	EXPORT TIM15_IRQHandler [WEAK]
		175	EXPORT TIM16_IRQHandler [WEAK]
		176	EXPORT TIM17_IRQHandler [WEAK]
		177	EXPORT I2C1_IRQHandler [WEAK]
		178	EXPORT I2C2_IRQHandler [WEAK]
		179	EXPORT SPI1_IRQHandler [WEAK]
		180	EXPORT SPI2_IRQHandler [WEAK]
		181	EXPORT USART1_IRQHandler [WEAK]
		182	EXPORT USART2_IRQHandler [WEAK]
		183	EXPORT CEC_IRQHandler [WEAK]
		184
		185
		186	WWDG_IRQHandler
		187	PVD_IRQHandler
		188	RTC_IRQHandler
		189	FLASH_IRQHandler
		190	RCC_IRQHandler
		191	EXTI0_1_IRQHandler
		192	EXTI2_3_IRQHandler
		193	EXTI4_15_IRQHandler
		194	TSC_IRQHandler
		195	DMA1_Channel1_IRQHandler
		196	DMA1_Channel2_3_IRQHandler
		197	DMA1_Channel4_5_IRQHandler
		198	ADC1_COMP_IRQHandler
		199	TIM1_BRK_UP_TRG_COM_IRQHandler
		200	TIM1_CC_IRQHandler
		201	TIM2_IRQHandler
		202	TIM3_IRQHandler
		203	TIM6_DAC_IRQHandler
		204	TIM14_IRQHandler
		205	TIM15_IRQHandler
		206	TIM16_IRQHandler
		207	TIM17_IRQHandler
		208	I2C1_IRQHandler
		209	I2C2_IRQHandler
		210	SPI1_IRQHandler
		211	SPI2_IRQHandler
		212	USART1_IRQHandler
		213	USART2_IRQHandler
		214	CEC_IRQHandler
		215
		216	B .
		217
		218	ENDP
		219
		220	ALIGN
		221
		222	;*******************************************************************************
		223	; User Stack and Heap initialization
		224	;*******************************************************************************
		225	IF :DEF:__MICROLIB
		226
		227	EXPORT __initial_sp
		228	EXPORT __heap_base
		229	EXPORT __heap_limit
		230
		231	ELSE
		232
		233	IMPORT __use_two_region_memory
		234	EXPORT __user_initial_stackheap
		235
		236	__user_initial_stackheap
		237
		238	LDR R0, = Heap_Mem
		239	LDR R1, =(Stack_Mem + Stack_Size)
		240	LDR R2, = (Heap_Mem + Heap_Size)
		241	LDR R3, = Stack_Mem
		242	BX LR
		243
		244	ALIGN
		245
		246	ENDIF
		247
		248	END
		249
		250	;********************** (C) COPYRIGHT STMicroelectronics *END OF FILE***

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f051x8.s – Rev 2