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| 2 | mjames | 1 | /* ---------------------------------------------------------------------- |
| 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
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| 3 | * |
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| 4 | * $Date: 19. March 2015 |
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| 5 | * $Revision: V.1.4.5 |
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| 6 | * |
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| 7 | * Project: CMSIS DSP Library |
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| 8 | * Title: arm_cmplx_mult_cmplx_f32.c |
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| 9 | * |
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| 10 | * Description: Floating-point complex-by-complex multiplication |
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| 11 | * |
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| 12 | * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 |
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| 13 | * |
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| 14 | * Redistribution and use in source and binary forms, with or without |
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| 15 | * modification, are permitted provided that the following conditions |
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| 16 | * are met: |
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| 17 | * - Redistributions of source code must retain the above copyright |
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| 18 | * notice, this list of conditions and the following disclaimer. |
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| 19 | * - Redistributions in binary form must reproduce the above copyright |
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| 20 | * notice, this list of conditions and the following disclaimer in |
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| 21 | * the documentation and/or other materials provided with the |
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| 22 | * distribution. |
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| 23 | * - Neither the name of ARM LIMITED nor the names of its contributors |
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| 24 | * may be used to endorse or promote products derived from this |
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| 25 | * software without specific prior written permission. |
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| 26 | * |
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| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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| 30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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| 31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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| 33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 38 | * POSSIBILITY OF SUCH DAMAGE. |
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| 39 | * -------------------------------------------------------------------- */ |
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| 40 | #include "arm_math.h" |
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| 41 | |||
| 42 | /** |
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| 43 | * @ingroup groupCmplxMath |
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| 44 | */ |
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| 45 | |||
| 46 | /** |
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| 47 | * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication |
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| 48 | * |
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| 49 | * Multiplies a complex vector by another complex vector and generates a complex result. |
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| 50 | * The data in the complex arrays is stored in an interleaved fashion |
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| 51 | * (real, imag, real, imag, ...). |
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| 52 | * The parameter <code>numSamples</code> represents the number of complex |
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| 53 | * samples processed. The complex arrays have a total of <code>2*numSamples</code> |
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| 54 | * real values. |
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| 55 | * |
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| 56 | * The underlying algorithm is used: |
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| 57 | * |
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| 58 | * <pre> |
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| 59 | * for(n=0; n<numSamples; n++) { |
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| 60 | * pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1]; |
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| 61 | * pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0]; |
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| 62 | * } |
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| 63 | * </pre> |
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| 64 | * |
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| 65 | * There are separate functions for floating-point, Q15, and Q31 data types. |
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| 66 | */ |
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| 67 | |||
| 68 | /** |
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| 69 | * @addtogroup CmplxByCmplxMult |
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| 70 | * @{ |
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| 71 | */ |
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| 72 | |||
| 73 | |||
| 74 | /** |
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| 75 | * @brief Floating-point complex-by-complex multiplication |
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| 76 | * @param[in] *pSrcA points to the first input vector |
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| 77 | * @param[in] *pSrcB points to the second input vector |
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| 78 | * @param[out] *pDst points to the output vector |
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| 79 | * @param[in] numSamples number of complex samples in each vector |
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| 80 | * @return none. |
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| 81 | */ |
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| 82 | |||
| 83 | void arm_cmplx_mult_cmplx_f32( |
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| 84 | float32_t * pSrcA, |
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| 85 | float32_t * pSrcB, |
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| 86 | float32_t * pDst, |
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| 87 | uint32_t numSamples) |
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| 88 | { |
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| 89 | float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */ |
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| 90 | uint32_t blkCnt; /* loop counters */ |
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| 91 | |||
| 92 | #ifndef ARM_MATH_CM0_FAMILY |
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| 93 | |||
| 94 | /* Run the below code for Cortex-M4 and Cortex-M3 */ |
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| 95 | float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */ |
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| 96 | float32_t acc1, acc2, acc3, acc4; |
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| 97 | |||
| 98 | |||
| 99 | /* loop Unrolling */ |
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| 100 | blkCnt = numSamples >> 2u; |
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| 101 | |||
| 102 | /* First part of the processing with loop unrolling. Compute 4 outputs at a time. |
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| 103 | ** a second loop below computes the remaining 1 to 3 samples. */ |
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| 104 | while(blkCnt > 0u) |
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| 105 | { |
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| 106 | /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */ |
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| 107 | /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */ |
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| 108 | a1 = *pSrcA; /* A[2 * i] */ |
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| 109 | c1 = *pSrcB; /* B[2 * i] */ |
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| 110 | |||
| 111 | b1 = *(pSrcA + 1); /* A[2 * i + 1] */ |
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| 112 | acc1 = a1 * c1; /* acc1 = A[2 * i] * B[2 * i] */ |
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| 113 | |||
| 114 | a2 = *(pSrcA + 2); /* A[2 * i + 2] */ |
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| 115 | acc2 = (b1 * c1); /* acc2 = A[2 * i + 1] * B[2 * i] */ |
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| 116 | |||
| 117 | d1 = *(pSrcB + 1); /* B[2 * i + 1] */ |
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| 118 | c2 = *(pSrcB + 2); /* B[2 * i + 2] */ |
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| 119 | acc1 -= b1 * d1; /* acc1 = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */ |
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| 120 | |||
| 121 | d2 = *(pSrcB + 3); /* B[2 * i + 3] */ |
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| 122 | acc3 = a2 * c2; /* acc3 = A[2 * i + 2] * B[2 * i + 2] */ |
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| 123 | |||
| 124 | b2 = *(pSrcA + 3); /* A[2 * i + 3] */ |
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| 125 | acc2 += (a1 * d1); /* acc2 = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */ |
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| 126 | |||
| 127 | a1 = *(pSrcA + 4); /* A[2 * i + 4] */ |
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| 128 | acc4 = (a2 * d2); /* acc4 = A[2 * i + 2] * B[2 * i + 3] */ |
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| 129 | |||
| 130 | c1 = *(pSrcB + 4); /* B[2 * i + 4] */ |
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| 131 | acc3 -= (b2 * d2); /* acc3 = A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */ |
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| 132 | *pDst = acc1; /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */ |
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| 133 | |||
| 134 | b1 = *(pSrcA + 5); /* A[2 * i + 5] */ |
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| 135 | acc4 += b2 * c2; /* acc4 = A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */ |
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| 136 | |||
| 137 | *(pDst + 1) = acc2; /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */ |
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| 138 | acc1 = (a1 * c1); |
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| 139 | |||
| 140 | d1 = *(pSrcB + 5); |
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| 141 | acc2 = (b1 * c1); |
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| 142 | |||
| 143 | *(pDst + 2) = acc3; |
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| 144 | *(pDst + 3) = acc4; |
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| 145 | |||
| 146 | a2 = *(pSrcA + 6); |
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| 147 | acc1 -= (b1 * d1); |
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| 148 | |||
| 149 | c2 = *(pSrcB + 6); |
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| 150 | acc2 += (a1 * d1); |
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| 151 | |||
| 152 | b2 = *(pSrcA + 7); |
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| 153 | acc3 = (a2 * c2); |
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| 154 | |||
| 155 | d2 = *(pSrcB + 7); |
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| 156 | acc4 = (b2 * c2); |
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| 157 | |||
| 158 | *(pDst + 4) = acc1; |
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| 159 | pSrcA += 8u; |
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| 160 | |||
| 161 | acc3 -= (b2 * d2); |
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| 162 | acc4 += (a2 * d2); |
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| 163 | |||
| 164 | *(pDst + 5) = acc2; |
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| 165 | pSrcB += 8u; |
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| 166 | |||
| 167 | *(pDst + 6) = acc3; |
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| 168 | *(pDst + 7) = acc4; |
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| 169 | |||
| 170 | pDst += 8u; |
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| 171 | |||
| 172 | /* Decrement the numSamples loop counter */ |
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| 173 | blkCnt--; |
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| 174 | } |
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| 175 | |||
| 176 | /* If the numSamples is not a multiple of 4, compute any remaining output samples here. |
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| 177 | ** No loop unrolling is used. */ |
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| 178 | blkCnt = numSamples % 0x4u; |
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| 179 | |||
| 180 | #else |
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| 181 | |||
| 182 | /* Run the below code for Cortex-M0 */ |
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| 183 | blkCnt = numSamples; |
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| 184 | |||
| 185 | #endif /* #ifndef ARM_MATH_CM0_FAMILY */ |
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| 186 | |||
| 187 | while(blkCnt > 0u) |
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| 188 | { |
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| 189 | /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */ |
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| 190 | /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */ |
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| 191 | a1 = *pSrcA++; |
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| 192 | b1 = *pSrcA++; |
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| 193 | c1 = *pSrcB++; |
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| 194 | d1 = *pSrcB++; |
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| 195 | |||
| 196 | /* store the result in the destination buffer. */ |
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| 197 | *pDst++ = (a1 * c1) - (b1 * d1); |
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| 198 | *pDst++ = (a1 * d1) + (b1 * c1); |
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| 199 | |||
| 200 | /* Decrement the numSamples loop counter */ |
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| 201 | blkCnt--; |
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| 202 | } |
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| 203 | } |
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| 204 | |||
| 205 | /** |
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| 206 | * @} end of CmplxByCmplxMult group |
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| 207 | */ |