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| 2 | mjames | 1 | /* ---------------------------------------------------------------------- |
| 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
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| 3 | * |
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| 4 | * $Date: 19. March 2015 |
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| 5 | * $Revision: V.1.4.5 |
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| 6 | * |
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| 7 | * Project: CMSIS DSP Library |
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| 8 | * Title: arm_cmplx_mag_squared_q15.c |
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| 9 | * |
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| 10 | * Description: Q15 complex magnitude squared. |
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| 11 | * |
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| 12 | * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 |
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| 13 | * |
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| 14 | * Redistribution and use in source and binary forms, with or without |
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| 15 | * modification, are permitted provided that the following conditions |
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| 16 | * are met: |
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| 17 | * - Redistributions of source code must retain the above copyright |
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| 18 | * notice, this list of conditions and the following disclaimer. |
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| 19 | * - Redistributions in binary form must reproduce the above copyright |
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| 20 | * notice, this list of conditions and the following disclaimer in |
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| 21 | * the documentation and/or other materials provided with the |
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| 22 | * distribution. |
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| 23 | * - Neither the name of ARM LIMITED nor the names of its contributors |
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| 24 | * may be used to endorse or promote products derived from this |
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| 25 | * software without specific prior written permission. |
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| 26 | * |
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| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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| 30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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| 31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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| 33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 38 | * POSSIBILITY OF SUCH DAMAGE. |
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| 39 | * ---------------------------------------------------------------------------- */ |
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| 40 | |||
| 41 | #include "arm_math.h" |
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| 42 | |||
| 43 | /** |
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| 44 | * @ingroup groupCmplxMath |
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| 45 | */ |
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| 46 | |||
| 47 | /** |
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| 48 | * @addtogroup cmplx_mag_squared |
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| 49 | * @{ |
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| 50 | */ |
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| 51 | |||
| 52 | /** |
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| 53 | * @brief Q15 complex magnitude squared |
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| 54 | * @param *pSrc points to the complex input vector |
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| 55 | * @param *pDst points to the real output vector |
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| 56 | * @param numSamples number of complex samples in the input vector |
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| 57 | * @return none. |
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| 58 | * |
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| 59 | * <b>Scaling and Overflow Behavior:</b> |
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| 60 | * \par |
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| 61 | * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. |
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| 62 | */ |
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| 63 | |||
| 64 | void arm_cmplx_mag_squared_q15( |
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| 65 | q15_t * pSrc, |
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| 66 | q15_t * pDst, |
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| 67 | uint32_t numSamples) |
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| 68 | { |
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| 69 | q31_t acc0, acc1; /* Accumulators */ |
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| 70 | |||
| 71 | #ifndef ARM_MATH_CM0_FAMILY |
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| 72 | |||
| 73 | /* Run the below code for Cortex-M4 and Cortex-M3 */ |
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| 74 | uint32_t blkCnt; /* loop counter */ |
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| 75 | q31_t in1, in2, in3, in4; |
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| 76 | q31_t acc2, acc3; |
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| 77 | |||
| 78 | /*loop Unrolling */ |
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| 79 | blkCnt = numSamples >> 2u; |
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| 80 | |||
| 81 | /* First part of the processing with loop unrolling. Compute 4 outputs at a time. |
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| 82 | ** a second loop below computes the remaining 1 to 3 samples. */ |
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| 83 | while(blkCnt > 0u) |
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| 84 | { |
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| 85 | /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ |
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| 86 | in1 = *__SIMD32(pSrc)++; |
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| 87 | in2 = *__SIMD32(pSrc)++; |
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| 88 | in3 = *__SIMD32(pSrc)++; |
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| 89 | in4 = *__SIMD32(pSrc)++; |
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| 90 | |||
| 91 | acc0 = __SMUAD(in1, in1); |
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| 92 | acc1 = __SMUAD(in2, in2); |
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| 93 | acc2 = __SMUAD(in3, in3); |
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| 94 | acc3 = __SMUAD(in4, in4); |
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| 95 | |||
| 96 | /* store the result in 3.13 format in the destination buffer. */ |
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| 97 | *pDst++ = (q15_t) (acc0 >> 17); |
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| 98 | *pDst++ = (q15_t) (acc1 >> 17); |
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| 99 | *pDst++ = (q15_t) (acc2 >> 17); |
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| 100 | *pDst++ = (q15_t) (acc3 >> 17); |
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| 101 | |||
| 102 | /* Decrement the loop counter */ |
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| 103 | blkCnt--; |
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| 104 | } |
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| 105 | |||
| 106 | /* If the numSamples is not a multiple of 4, compute any remaining output samples here. |
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| 107 | ** No loop unrolling is used. */ |
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| 108 | blkCnt = numSamples % 0x4u; |
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| 109 | |||
| 110 | while(blkCnt > 0u) |
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| 111 | { |
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| 112 | /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ |
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| 113 | in1 = *__SIMD32(pSrc)++; |
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| 114 | acc0 = __SMUAD(in1, in1); |
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| 115 | |||
| 116 | /* store the result in 3.13 format in the destination buffer. */ |
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| 117 | *pDst++ = (q15_t) (acc0 >> 17); |
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| 118 | |||
| 119 | /* Decrement the loop counter */ |
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| 120 | blkCnt--; |
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| 121 | } |
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| 122 | |||
| 123 | #else |
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| 124 | |||
| 125 | /* Run the below code for Cortex-M0 */ |
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| 126 | q15_t real, imag; /* Temporary variables to store real and imaginary values */ |
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| 127 | |||
| 128 | while(numSamples > 0u) |
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| 129 | { |
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| 130 | /* out = ((real * real) + (imag * imag)) */ |
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| 131 | real = *pSrc++; |
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| 132 | imag = *pSrc++; |
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| 133 | acc0 = (real * real); |
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| 134 | acc1 = (imag * imag); |
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| 135 | /* store the result in 3.13 format in the destination buffer. */ |
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| 136 | *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); |
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| 137 | |||
| 138 | /* Decrement the loop counter */ |
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| 139 | numSamples--; |
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| 140 | } |
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| 141 | |||
| 142 | #endif /* #ifndef ARM_MATH_CM0_FAMILY */ |
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| 143 | |||
| 144 | } |
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| 145 | |||
| 146 | /** |
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| 147 | * @} end of cmplx_mag_squared group |
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| 148 | */ |