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/* ----------------------------------------------------------------------
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 * Project:      CMSIS DSP Library
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 * Title:        arm_offset_q15.c
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 * Description:  Q15 vector offset
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 *
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 * $Date:        27. January 2017
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 * $Revision:    V.1.5.1
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 *
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 * Target Processor: Cortex-M cores
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 * -------------------------------------------------------------------- */
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/*
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 * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
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 *
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 * SPDX-License-Identifier: Apache-2.0
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 *
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 * Licensed under the Apache License, Version 2.0 (the License); you may
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 * not use this file except in compliance with the License.
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 * You may obtain a copy of the License at
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 *
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 * www.apache.org/licenses/LICENSE-2.0
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 *
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 * Unless required by applicable law or agreed to in writing, software
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 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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 * See the License for the specific language governing permissions and
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 * limitations under the License.
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 */
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#include "arm_math.h"
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/**
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 * @ingroup groupMath
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 */
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/**
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 * @addtogroup offset
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 * @{
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 */
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/**
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 * @brief  Adds a constant offset to a Q15 vector.
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 * @param[in]  *pSrc points to the input vector
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 * @param[in]  offset is the offset to be added
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 * @param[out]  *pDst points to the output vector
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 * @param[in]  blockSize number of samples in the vector
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 * @return none.
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 *
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 * <b>Scaling and Overflow Behavior:</b>
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 * \par
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 * The function uses saturating arithmetic.
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 * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
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 */
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void arm_offset_q15(
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  q15_t * pSrc,
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  q15_t offset,
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  q15_t * pDst,
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  uint32_t blockSize)
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{
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  uint32_t blkCnt;                               /* loop counter */
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#if defined (ARM_MATH_DSP)
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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  q31_t offset_packed;                           /* Offset packed to 32 bit */
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  /*loop Unrolling */
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  blkCnt = blockSize >> 2U;
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  /* Offset is packed to 32 bit in order to use SIMD32 for addition */
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  offset_packed = __PKHBT(offset, offset, 16);
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  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
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   ** a second loop below computes the remaining 1 to 3 samples. */
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  while (blkCnt > 0U)
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  {
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    /* C = A + offset */
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    /* Add offset and then store the results in the destination buffer, 2 samples at a time. */
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    *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
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    *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
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    /* Decrement the loop counter */
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    blkCnt--;
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  }
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  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
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   ** No loop unrolling is used. */
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  blkCnt = blockSize % 0x4U;
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  while (blkCnt > 0U)
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  {
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    /* C = A + offset */
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    /* Add offset and then store the results in the destination buffer. */
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    *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
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    /* Decrement the loop counter */
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    blkCnt--;
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  }
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#else
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  /* Run the below code for Cortex-M0 */
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  /* Initialize blkCnt with number of samples */
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  blkCnt = blockSize;
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  while (blkCnt > 0U)
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  {
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    /* C = A + offset */
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    /* Add offset and then store the results in the destination buffer. */
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    *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);
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    /* Decrement the loop counter */
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    blkCnt--;
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  }
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#endif /* #if defined (ARM_MATH_DSP) */
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}
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/**
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 * @} end of offset group
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 */