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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_hal_pwr.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief PWR HAL module driver. |
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| 6 | * |
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| 7 | * This file provides firmware functions to manage the following |
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| 8 | * functionalities of the Power Controller (PWR) peripheral: |
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| 9 | * + Initialization/de-initialization functions |
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| 28 | mjames | 10 | * + Peripheral Control functions |
| 2 | mjames | 11 | * |
| 12 | ****************************************************************************** |
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| 13 | * @attention |
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| 14 | * |
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| 28 | mjames | 15 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
| 16 | * All rights reserved.</center></h2> |
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| 2 | mjames | 17 | * |
| 28 | mjames | 18 | * This software component is licensed by ST under BSD 3-Clause license, |
| 19 | * the "License"; You may not use this file except in compliance with the |
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| 20 | * License. You may obtain a copy of the License at: |
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| 21 | * opensource.org/licenses/BSD-3-Clause |
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| 2 | mjames | 22 | * |
| 23 | ****************************************************************************** |
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| 24 | */ |
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| 25 | |||
| 26 | /* Includes ------------------------------------------------------------------*/ |
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| 27 | #include "stm32l1xx_hal.h" |
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| 28 | |||
| 29 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | |||
| 33 | /** @defgroup PWR PWR |
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| 34 | * @brief PWR HAL module driver |
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| 35 | * @{ |
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| 36 | */ |
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| 37 | |||
| 38 | #ifdef HAL_PWR_MODULE_ENABLED |
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| 39 | |||
| 40 | /* Private typedef -----------------------------------------------------------*/ |
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| 41 | /* Private define ------------------------------------------------------------*/ |
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| 28 | mjames | 42 | #define PVD_MODE_IT (0x00010000U) |
| 43 | #define PVD_MODE_EVT (0x00020000U) |
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| 44 | #define PVD_RISING_EDGE (0x00000001U) |
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| 45 | #define PVD_FALLING_EDGE (0x00000002U) |
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| 2 | mjames | 46 | |
| 47 | /* Private macro -------------------------------------------------------------*/ |
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| 48 | /* Private variables ---------------------------------------------------------*/ |
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| 49 | /* Private function prototypes -----------------------------------------------*/ |
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| 50 | /* Private functions ---------------------------------------------------------*/ |
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| 51 | |||
| 52 | /** @defgroup PWR_Exported_Functions PWR Exported Functions |
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| 53 | * @{ |
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| 54 | */ |
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| 55 | |||
| 28 | mjames | 56 | /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
| 2 | mjames | 57 | * @brief Initialization and de-initialization functions |
| 58 | * |
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| 59 | @verbatim |
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| 60 | =============================================================================== |
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| 61 | ##### Initialization and de-initialization functions ##### |
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| 62 | =============================================================================== |
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| 63 | [..] |
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| 64 | After reset, the backup domain (RTC registers, RTC backup data |
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| 65 | registers) is protected against possible unwanted |
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| 66 | write accesses. |
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| 67 | To enable access to the RTC Domain and RTC registers, proceed as follows: |
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| 68 | (+) Enable the Power Controller (PWR) APB1 interface clock using the |
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| 69 | __HAL_RCC_PWR_CLK_ENABLE() macro. |
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| 70 | (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
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| 71 | |||
| 72 | @endverbatim |
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| 73 | * @{ |
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| 74 | */ |
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| 75 | |||
| 76 | /** |
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| 77 | * @brief Deinitializes the PWR peripheral registers to their default reset values. |
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| 28 | mjames | 78 | * @note Before calling this function, the VOS[1:0] bits should be configured |
| 79 | * to "10" and the system frequency has to be configured accordingly. |
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| 2 | mjames | 80 | * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig() |
| 28 | mjames | 81 | * function. |
| 82 | * @note ULP and FWU bits are not reset by this function. |
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| 2 | mjames | 83 | * @retval None |
| 84 | */ |
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| 85 | void HAL_PWR_DeInit(void) |
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| 86 | { |
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| 87 | __HAL_RCC_PWR_FORCE_RESET(); |
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| 88 | __HAL_RCC_PWR_RELEASE_RESET(); |
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| 89 | } |
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| 90 | |||
| 91 | /** |
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| 92 | * @brief Enables access to the backup domain (RTC registers, RTC |
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| 93 | * backup data registers ). |
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| 94 | * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the |
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| 95 | * Backup Domain Access should be kept enabled. |
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| 96 | * @retval None |
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| 97 | */ |
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| 98 | void HAL_PWR_EnableBkUpAccess(void) |
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| 99 | { |
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| 100 | /* Enable access to RTC and backup registers */ |
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| 101 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; |
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| 102 | } |
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| 103 | |||
| 104 | /** |
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| 105 | * @brief Disables access to the backup domain (RTC registers, RTC |
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| 106 | * backup data registers). |
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| 107 | * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the |
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| 108 | * Backup Domain Access should be kept enabled. |
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| 109 | * @retval None |
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| 110 | */ |
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| 111 | void HAL_PWR_DisableBkUpAccess(void) |
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| 112 | { |
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| 113 | /* Disable access to RTC and backup registers */ |
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| 114 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; |
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| 115 | } |
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| 116 | |||
| 117 | /** |
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| 118 | * @} |
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| 119 | */ |
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| 120 | |||
| 28 | mjames | 121 | /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions |
| 2 | mjames | 122 | * @brief Low Power modes configuration functions |
| 123 | * |
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| 124 | @verbatim |
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| 125 | |||
| 126 | =============================================================================== |
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| 127 | ##### Peripheral Control functions ##### |
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| 128 | =============================================================================== |
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| 28 | mjames | 129 | |
| 2 | mjames | 130 | *** PVD configuration *** |
| 131 | ========================= |
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| 132 | [..] |
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| 133 | (+) The PVD is used to monitor the VDD power supply by comparing it to a |
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| 134 | threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). |
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| 28 | mjames | 135 | (+) The PVD can use an external input analog voltage (PVD_IN) which is compared |
| 136 | internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode |
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| 2 | mjames | 137 | when PWR_PVDLevel_7 is selected (PLS[2:0] = 111). |
| 138 | |||
| 139 | (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower |
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| 140 | than the PVD threshold. This event is internally connected to the EXTI |
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| 141 | line16 and can generate an interrupt if enabled. This is done through |
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| 142 | __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. |
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| 143 | (+) The PVD is stopped in Standby mode. |
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| 144 | |||
| 145 | *** WakeUp pin configuration *** |
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| 146 | ================================ |
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| 147 | [..] |
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| 148 | (+) WakeUp pin is used to wake up the system from Standby mode. This pin is |
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| 149 | forced in input pull-down configuration and is active on rising edges. |
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| 150 | (+) There are two or three WakeUp pins: |
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| 151 | WakeUp Pin 1 on PA.00. |
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| 152 | WakeUp Pin 2 on PC.13. |
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| 28 | mjames | 153 | WakeUp Pin 3 on PE.06. : Only on product with GPIOE available |
| 2 | mjames | 154 | |
| 155 | [..] |
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| 156 | *** Main and Backup Regulators configuration *** |
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| 157 | ================================================ |
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| 158 | |||
| 159 | (+) The main internal regulator can be configured to have a tradeoff between |
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| 160 | performance and power consumption when the device does not operate at |
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| 161 | the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG() |
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| 162 | macro which configure VOS bit in PWR_CR register: |
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| 163 | (++) When this bit is set (Regulator voltage output Scale 1 mode selected) |
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| 164 | the System frequency can go up to 32 MHz. |
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| 165 | (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) |
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| 166 | the System frequency can go up to 16 MHz. |
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| 167 | (++) When this bit is reset (Regulator voltage output Scale 3 mode selected) |
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| 168 | the System frequency can go up to 4.2 MHz. |
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| 28 | mjames | 169 | |
| 2 | mjames | 170 | Refer to the datasheets for more details. |
| 171 | |||
| 172 | *** Low Power modes configuration *** |
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| 173 | ===================================== |
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| 174 | [..] |
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| 175 | The device features 5 low-power modes: |
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| 28 | mjames | 176 | (+) Low power run mode: regulator in low power mode, limited clock frequency, |
| 2 | mjames | 177 | limited number of peripherals running. |
| 178 | (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running. |
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| 28 | mjames | 179 | (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, |
| 2 | mjames | 180 | limited number of peripherals running, regulator in low power mode. |
| 181 | (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode. |
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| 182 | (+) Standby mode: VCORE domain powered off |
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| 28 | mjames | 183 | |
| 2 | mjames | 184 | *** Low power run mode *** |
| 185 | ========================= |
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| 186 | [..] |
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| 187 | To further reduce the consumption when the system is in Run mode, the regulator can be |
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| 188 | configured in low power mode. In this mode, the system frequency should not exceed |
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| 189 | MSI frequency range1. |
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| 190 | In Low power run mode, all I/O pins keep the same state as in Run mode. |
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| 28 | mjames | 191 | |
| 2 | mjames | 192 | (+) Entry: |
| 193 | (++) VCORE in range2 |
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| 194 | (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1. |
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| 195 | (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode() |
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| 196 | function. |
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| 197 | (+) Exit: |
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| 198 | (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode() |
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| 199 | function. |
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| 200 | (++) Increase the system frequency if needed. |
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| 28 | mjames | 201 | |
| 2 | mjames | 202 | *** Sleep mode *** |
| 203 | ================== |
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| 204 | [..] |
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| 205 | (+) Entry: |
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| 206 | The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
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| 207 | functions with |
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| 208 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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| 209 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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| 28 | mjames | 210 | |
| 2 | mjames | 211 | (+) Exit: |
| 212 | (++) Any peripheral interrupt acknowledged by the nested vectored interrupt |
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| 213 | controller (NVIC) can wake up the device from Sleep mode. |
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| 214 | |||
| 215 | *** Low power sleep mode *** |
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| 216 | ============================ |
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| 217 | [..] |
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| 218 | (+) Entry: |
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| 219 | The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
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| 220 | functions with |
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| 221 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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| 222 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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| 28 | mjames | 223 | (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. |
| 2 | mjames | 224 | This reduces power consumption but increases the wake-up time. |
| 28 | mjames | 225 | |
| 2 | mjames | 226 | (+) Exit: |
| 227 | (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt |
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| 228 | acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device |
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| 229 | from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode, |
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| 28 | mjames | 230 | the MCU exits Sleep mode as soon as an event occurs. |
| 231 | |||
| 2 | mjames | 232 | *** Stop mode *** |
| 233 | ================= |
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| 234 | [..] |
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| 235 | The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral |
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| 236 | clock gating. The voltage regulator can be configured either in normal or low-power mode. |
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| 237 | In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and |
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| 238 | the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. |
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| 239 | To get the lowest consumption in Stop mode, the internal Flash memory also enters low |
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| 240 | power mode. When the Flash memory is in power-down mode, an additional startup delay is |
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| 241 | incurred when waking up from Stop mode. |
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| 242 | To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature |
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| 243 | sensor can be switched off before entering Stop mode. They can be switched on again by |
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| 244 | software after exiting Stop mode using the ULP bit in the PWR_CR register. |
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| 245 | In Stop mode, all I/O pins keep the same state as in Run mode. |
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| 246 | |||
| 247 | (+) Entry: |
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| 248 | The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI ) |
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| 249 | function with: |
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| 250 | (++) Main regulator ON. |
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| 251 | (++) Low Power regulator ON. |
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| 252 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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| 253 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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| 254 | (+) Exit: |
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| 255 | (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock. |
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| 256 | |||
| 257 | *** Standby mode *** |
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| 258 | ==================== |
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| 259 | [..] |
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| 260 | The Standby mode allows to achieve the lowest power consumption. It is based on the |
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| 261 | Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is |
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| 262 | consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are |
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| 263 | also switched off. SRAM and register contents are lost except for the RTC registers, RTC |
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| 264 | backup registers and Standby circuitry. |
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| 28 | mjames | 265 | |
| 2 | mjames | 266 | To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature |
| 28 | mjames | 267 | sensor can be switched off before entering the Standby mode. They can be switched |
| 2 | mjames | 268 | on again by software after exiting the Standby mode. |
| 269 | function. |
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| 28 | mjames | 270 | |
| 2 | mjames | 271 | (+) Entry: |
| 272 | (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
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| 273 | (+) Exit: |
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| 274 | (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, |
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| 275 | tamper event, time-stamp event, external reset in NRST pin, IWDG reset. |
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| 276 | |||
| 277 | *** Auto-wakeup (AWU) from low-power mode *** |
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| 278 | ============================================= |
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| 279 | [..] |
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| 28 | mjames | 280 | The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC |
| 281 | Wakeup event, a tamper event, a time-stamp event, or a comparator event, |
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| 2 | mjames | 282 | without depending on an external interrupt (Auto-wakeup mode). |
| 283 | |||
| 284 | (+) RTC auto-wakeup (AWU) from the Stop mode |
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| 285 | (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: |
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| 28 | mjames | 286 | (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt |
| 2 | mjames | 287 | or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() |
| 288 | function |
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| 28 | mjames | 289 | (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() |
| 2 | mjames | 290 | and HAL_RTC_SetTime() functions. |
| 28 | mjames | 291 | (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it |
| 2 | mjames | 292 | is necessary to: |
| 293 | (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and |
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| 28 | mjames | 294 | Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT() |
| 2 | mjames | 295 | or HAL_RTCEx_SetTimeStamp_IT() functions. |
| 296 | (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: |
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| 297 | (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and |
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| 298 | Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function. |
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| 28 | mjames | 299 | (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer() |
| 2 | mjames | 300 | function. |
| 301 | |||
| 302 | (+) RTC auto-wakeup (AWU) from the Standby mode |
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| 303 | (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: |
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| 304 | (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function. |
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| 28 | mjames | 305 | (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() |
| 2 | mjames | 306 | and HAL_RTC_SetTime() functions. |
| 28 | mjames | 307 | (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it |
| 2 | mjames | 308 | is necessary to: |
| 28 | mjames | 309 | (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to |
| 2 | mjames | 310 | detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT() |
| 311 | or HAL_RTCEx_SetTamper_IT()functions. |
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| 312 | (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: |
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| 28 | mjames | 313 | (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event |
| 2 | mjames | 314 | using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions. |
| 315 | |||
| 316 | (+) Comparator auto-wakeup (AWU) from the Stop mode |
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| 317 | (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup |
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| 318 | event, it is necessary to: |
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| 28 | mjames | 319 | (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the |
| 320 | selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using |
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| 2 | mjames | 321 | the COMP functions. |
| 28 | mjames | 322 | (+++) Configure the comparator to generate the event. |
| 323 | |||
| 324 | |||
| 325 | |||
| 2 | mjames | 326 | @endverbatim |
| 327 | * @{ |
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| 328 | */ |
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| 329 | |||
| 330 | /** |
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| 331 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). |
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| 28 | mjames | 332 | * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration |
| 2 | mjames | 333 | * information for the PVD. |
| 334 | * @note Refer to the electrical characteristics of your device datasheet for |
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| 335 | * more details about the voltage threshold corresponding to each |
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| 336 | * detection level. |
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| 337 | * @retval None |
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| 338 | */ |
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| 339 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) |
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| 340 | { |
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| 341 | /* Check the parameters */ |
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| 342 | assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); |
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| 343 | assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); |
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| 344 | |||
| 345 | /* Set PLS[7:5] bits according to PVDLevel value */ |
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| 346 | MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); |
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| 28 | mjames | 347 | |
| 2 | mjames | 348 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
| 349 | __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); |
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| 350 | __HAL_PWR_PVD_EXTI_DISABLE_IT(); |
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| 351 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE(); |
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| 352 | |||
| 353 | /* Configure interrupt mode */ |
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| 354 | if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) |
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| 355 | { |
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| 356 | __HAL_PWR_PVD_EXTI_ENABLE_IT(); |
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| 357 | } |
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| 28 | mjames | 358 | |
| 2 | mjames | 359 | /* Configure event mode */ |
| 360 | if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) |
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| 361 | { |
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| 362 | __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); |
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| 363 | } |
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| 28 | mjames | 364 | |
| 2 | mjames | 365 | /* Configure the edge */ |
| 366 | if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) |
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| 367 | { |
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| 368 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); |
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| 369 | } |
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| 28 | mjames | 370 | |
| 2 | mjames | 371 | if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) |
| 372 | { |
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| 373 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
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| 374 | } |
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| 375 | } |
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| 376 | |||
| 377 | /** |
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| 378 | * @brief Enables the Power Voltage Detector(PVD). |
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| 379 | * @retval None |
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| 380 | */ |
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| 381 | void HAL_PWR_EnablePVD(void) |
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| 382 | { |
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| 383 | /* Enable the power voltage detector */ |
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| 384 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; |
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| 385 | } |
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| 386 | |||
| 387 | /** |
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| 388 | * @brief Disables the Power Voltage Detector(PVD). |
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| 389 | * @retval None |
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| 390 | */ |
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| 391 | void HAL_PWR_DisablePVD(void) |
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| 392 | { |
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| 393 | /* Disable the power voltage detector */ |
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| 394 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; |
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| 395 | } |
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| 396 | |||
| 397 | /** |
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| 398 | * @brief Enables the WakeUp PINx functionality. |
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| 399 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. |
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| 400 | * This parameter can be one of the following values: |
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| 401 | * @arg PWR_WAKEUP_PIN1 |
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| 402 | * @arg PWR_WAKEUP_PIN2 |
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| 28 | mjames | 403 | * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available |
| 2 | mjames | 404 | * @retval None |
| 405 | */ |
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| 406 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
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| 407 | { |
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| 408 | /* Check the parameter */ |
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| 409 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
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| 410 | /* Enable the EWUPx pin */ |
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| 411 | *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; |
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| 412 | } |
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| 413 | |||
| 414 | /** |
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| 415 | * @brief Disables the WakeUp PINx functionality. |
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| 416 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. |
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| 417 | * This parameter can be one of the following values: |
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| 418 | * @arg PWR_WAKEUP_PIN1 |
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| 28 | mjames | 419 | * @arg PWR_WAKEUP_PIN2 |
| 420 | * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available |
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| 2 | mjames | 421 | * @retval None |
| 422 | */ |
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| 423 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
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| 424 | { |
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| 425 | /* Check the parameter */ |
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| 426 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
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| 427 | /* Disable the EWUPx pin */ |
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| 428 | *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; |
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| 429 | } |
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| 430 | |||
| 431 | /** |
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| 432 | * @brief Enters Sleep mode. |
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| 433 | * @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
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| 434 | * @param Regulator: Specifies the regulator state in SLEEP mode. |
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| 435 | * This parameter can be one of the following values: |
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| 436 | * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON |
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| 437 | * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON |
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| 438 | * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. |
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| 28 | mjames | 439 | * When WFI entry is used, tick interrupt have to be disabled if not desired as |
| 2 | mjames | 440 | * the interrupt wake up source. |
| 441 | * This parameter can be one of the following values: |
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| 442 | * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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| 443 | * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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| 444 | * @retval None |
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| 445 | */ |
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| 446 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
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| 447 | { |
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| 448 | /* Check the parameters */ |
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| 449 | assert_param(IS_PWR_REGULATOR(Regulator)); |
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| 450 | assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
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| 451 | |||
| 452 | /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ |
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| 453 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); |
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| 454 | |||
| 455 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
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| 456 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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| 457 | |||
| 458 | /* Select SLEEP mode entry -------------------------------------------------*/ |
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| 459 | if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
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| 460 | { |
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| 461 | /* Request Wait For Interrupt */ |
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| 462 | __WFI(); |
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| 463 | } |
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| 464 | else |
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| 465 | { |
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| 466 | /* Request Wait For Event */ |
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| 467 | __SEV(); |
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| 468 | __WFE(); |
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| 469 | __WFE(); |
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| 470 | } |
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| 471 | } |
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| 472 | |||
| 473 | /** |
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| 28 | mjames | 474 | * @brief Enters Stop mode. |
| 2 | mjames | 475 | * @note In Stop mode, all I/O pins keep the same state as in Run mode. |
| 476 | * @note When exiting Stop mode by using an interrupt or a wakeup event, |
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| 477 | * MSI RC oscillator is selected as system clock. |
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| 478 | * @note When the voltage regulator operates in low power mode, an additional |
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| 28 | mjames | 479 | * startup delay is incurred when waking up from Stop mode. |
| 2 | mjames | 480 | * By keeping the internal regulator ON during Stop mode, the consumption |
| 28 | mjames | 481 | * is higher although the startup time is reduced. |
| 2 | mjames | 482 | * @param Regulator: Specifies the regulator state in Stop mode. |
| 483 | * This parameter can be one of the following values: |
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| 484 | * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON |
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| 485 | * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON |
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| 486 | * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. |
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| 487 | * This parameter can be one of the following values: |
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| 488 | * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction |
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| 28 | mjames | 489 | * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction |
| 2 | mjames | 490 | * @retval None |
| 491 | */ |
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| 492 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
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| 493 | { |
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| 494 | /* Check the parameters */ |
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| 495 | assert_param(IS_PWR_REGULATOR(Regulator)); |
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| 496 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
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| 497 | |||
| 498 | /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ |
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| 499 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); |
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| 500 | |||
| 501 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
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| 502 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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| 503 | |||
| 504 | /* Select Stop mode entry --------------------------------------------------*/ |
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| 505 | if(STOPEntry == PWR_STOPENTRY_WFI) |
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| 506 | { |
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| 507 | /* Request Wait For Interrupt */ |
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| 508 | __WFI(); |
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| 509 | } |
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| 510 | else |
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| 511 | { |
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| 512 | /* Request Wait For Event */ |
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| 513 | __SEV(); |
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| 514 | __WFE(); |
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| 515 | __WFE(); |
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| 516 | } |
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| 517 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
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| 518 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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| 519 | } |
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| 520 | |||
| 521 | /** |
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| 522 | * @brief Enters Standby mode. |
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| 523 | * @note In Standby mode, all I/O pins are high impedance except for: |
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| 28 | mjames | 524 | * - Reset pad (still available) |
| 2 | mjames | 525 | * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC |
| 526 | * Alarm out, or RTC clock calibration out. |
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| 527 | * - WKUP pin 1 (PA0) if enabled. |
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| 528 | * - WKUP pin 2 (PC13) if enabled. |
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| 529 | * - WKUP pin 3 (PE6) if enabled. |
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| 530 | * @retval None |
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| 531 | */ |
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| 532 | void HAL_PWR_EnterSTANDBYMode(void) |
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| 533 | { |
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| 534 | /* Select Standby mode */ |
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| 535 | SET_BIT(PWR->CR, PWR_CR_PDDS); |
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| 536 | |||
| 537 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
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| 538 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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| 539 | |||
| 540 | /* This option is used to ensure that store operations are completed */ |
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| 541 | #if defined ( __CC_ARM) |
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| 542 | __force_stores(); |
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| 543 | #endif |
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| 544 | /* Request Wait For Interrupt */ |
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| 545 | __WFI(); |
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| 546 | } |
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| 547 | |||
| 548 | |||
| 549 | /** |
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| 28 | mjames | 550 | * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. |
| 551 | * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
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| 2 | mjames | 552 | * re-enters SLEEP mode when an interruption handling is over. |
| 553 | * Setting this bit is useful when the processor is expected to run only on |
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| 28 | mjames | 554 | * interruptions handling. |
| 2 | mjames | 555 | * @retval None |
| 556 | */ |
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| 557 | void HAL_PWR_EnableSleepOnExit(void) |
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| 558 | { |
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| 559 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
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| 560 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
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| 561 | } |
||
| 562 | |||
| 563 | |||
| 564 | /** |
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| 28 | mjames | 565 | * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. |
| 566 | * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
||
| 567 | * re-enters SLEEP mode when an interruption handling is over. |
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| 2 | mjames | 568 | * @retval None |
| 569 | */ |
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| 570 | void HAL_PWR_DisableSleepOnExit(void) |
||
| 571 | { |
||
| 572 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
||
| 573 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
||
| 574 | } |
||
| 575 | |||
| 576 | |||
| 577 | /** |
||
| 28 | mjames | 578 | * @brief Enables CORTEX M3 SEVONPEND bit. |
| 579 | * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes |
||
| 2 | mjames | 580 | * WFE to wake up when an interrupt moves from inactive to pended. |
| 581 | * @retval None |
||
| 582 | */ |
||
| 583 | void HAL_PWR_EnableSEVOnPend(void) |
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| 584 | { |
||
| 585 | /* Set SEVONPEND bit of Cortex System Control Register */ |
||
| 586 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
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| 587 | } |
||
| 588 | |||
| 589 | |||
| 590 | /** |
||
| 28 | mjames | 591 | * @brief Disables CORTEX M3 SEVONPEND bit. |
| 592 | * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes |
||
| 593 | * WFE to wake up when an interrupt moves from inactive to pended. |
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| 2 | mjames | 594 | * @retval None |
| 595 | */ |
||
| 596 | void HAL_PWR_DisableSEVOnPend(void) |
||
| 597 | { |
||
| 598 | /* Clear SEVONPEND bit of Cortex System Control Register */ |
||
| 599 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
||
| 600 | } |
||
| 601 | |||
| 602 | |||
| 603 | |||
| 604 | /** |
||
| 605 | * @brief This function handles the PWR PVD interrupt request. |
||
| 606 | * @note This API should be called under the PVD_IRQHandler(). |
||
| 607 | * @retval None |
||
| 608 | */ |
||
| 609 | void HAL_PWR_PVD_IRQHandler(void) |
||
| 610 | { |
||
| 611 | /* Check PWR exti flag */ |
||
| 612 | if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) |
||
| 613 | { |
||
| 614 | /* PWR PVD interrupt user callback */ |
||
| 615 | HAL_PWR_PVDCallback(); |
||
| 616 | |||
| 617 | /* Clear PWR Exti pending bit */ |
||
| 618 | __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); |
||
| 619 | } |
||
| 620 | } |
||
| 621 | |||
| 622 | /** |
||
| 623 | * @brief PWR PVD interrupt callback |
||
| 624 | * @retval None |
||
| 625 | */ |
||
| 626 | __weak void HAL_PWR_PVDCallback(void) |
||
| 627 | { |
||
| 628 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
| 629 | the HAL_PWR_PVDCallback could be implemented in the user file |
||
| 28 | mjames | 630 | */ |
| 2 | mjames | 631 | } |
| 632 | |||
| 633 | /** |
||
| 634 | * @} |
||
| 635 | */ |
||
| 636 | |||
| 637 | /** |
||
| 638 | * @} |
||
| 639 | */ |
||
| 640 | |||
| 641 | #endif /* HAL_PWR_MODULE_ENABLED */ |
||
| 642 | /** |
||
| 643 | * @} |
||
| 644 | */ |
||
| 645 | |||
| 646 | /** |
||
| 647 | * @} |
||
| 648 | */ |
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| 649 | |||
| 650 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |