Rev 35 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
||
| 3 | * @file stm32l1xx_hal_tim_ex.h |
||
| 4 | * @author MCD Application Team |
||
| 28 | mjames | 5 | * @brief Header file of TIM HAL Extended module. |
| 2 | mjames | 6 | ****************************************************************************** |
| 7 | * @attention |
||
| 8 | * |
||
| 28 | mjames | 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
||
| 2 | mjames | 11 | * |
| 28 | mjames | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| 13 | * the "License"; You may not use this file except in compliance with the |
||
| 14 | * License. You may obtain a copy of the License at: |
||
| 15 | * opensource.org/licenses/BSD-3-Clause |
||
| 2 | mjames | 16 | * |
| 17 | ****************************************************************************** |
||
| 28 | mjames | 18 | */ |
| 2 | mjames | 19 | |
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
||
| 28 | mjames | 21 | #ifndef STM32L1xx_HAL_TIM_EX_H |
| 22 | #define STM32L1xx_HAL_TIM_EX_H |
||
| 2 | mjames | 23 | |
| 24 | #ifdef __cplusplus |
||
| 28 | mjames | 25 | extern "C" { |
| 2 | mjames | 26 | #endif |
| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
||
| 29 | #include "stm32l1xx_hal_def.h" |
||
| 30 | |||
| 31 | /** @addtogroup STM32L1xx_HAL_Driver |
||
| 32 | * @{ |
||
| 33 | */ |
||
| 34 | |||
| 35 | /** @addtogroup TIMEx |
||
| 36 | * @{ |
||
| 28 | mjames | 37 | */ |
| 2 | mjames | 38 | |
| 28 | mjames | 39 | /* Exported types ------------------------------------------------------------*/ |
| 40 | /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types |
||
| 2 | mjames | 41 | * @{ |
| 42 | */ |
||
| 43 | |||
| 44 | /** |
||
| 45 | * @} |
||
| 46 | */ |
||
| 28 | mjames | 47 | /* End of exported types -----------------------------------------------------*/ |
| 2 | mjames | 48 | |
| 49 | /* Exported constants --------------------------------------------------------*/ |
||
| 28 | mjames | 50 | /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants |
| 2 | mjames | 51 | * @{ |
| 52 | */ |
||
| 28 | mjames | 53 | |
| 54 | /** @defgroup TIMEx_Remap TIM Extended Remapping |
||
| 2 | mjames | 55 | * @{ |
| 56 | */ |
||
| 28 | mjames | 57 | /* @note STM32L1XX devices are organized in 6 categories: Cat.1, Cat.2, Cat.3, Cat.4, Cat.5, Cat.6. |
| 58 | Remap capabilities depend on the device category. As the DMA2 controller is available only in |
||
| 59 | Cat.3, Cat.4,Cat.5 and Cat.6 devices it is used to discriminate Cat.1 and Cat.2 devices v.s. |
||
| 60 | Cat.3, Cat.4, Cat.5 and Cat.6 devices. */ |
||
| 61 | #if defined(DMA2) |
||
| 2 | mjames | 62 | #define TIM_TIM2_ITR1_TIM10_OC (0x00000000) /*!< TIM2 ITR1 input is connected to TIM10 OC */ |
| 63 | #define TIM_TIM2_ITR1_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM2 ITR1 input is connected to TIM5 TGO */ |
||
| 28 | mjames | 64 | #endif /* DMA2 */ |
| 2 | mjames | 65 | |
| 28 | mjames | 66 | #if defined(DMA2) |
| 2 | mjames | 67 | #define TIM_TIM3_ITR2_TIM11_OC (0x00000000) /*!< TIM3 ITR2 input is connected to TIM11 OC */ |
| 68 | #define TIM_TIM3_ITR2_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM3 ITR2 input is connected to TIM5 TGO */ |
||
| 28 | mjames | 69 | #endif /* DMA2 */ |
| 2 | mjames | 70 | |
| 28 | mjames | 71 | #if defined(DMA2) |
| 2 | mjames | 72 | #define TIM_TIM9_ITR1_TIM3_TGO (0x00000000) /*!< TIM9 ITR1 input is connected to TIM3 TGO */ |
| 73 | #define TIM_TIM9_ITR1_TS TIM9_OR_ITR1_RMP /*!< TIM9 ITR1 input is connected to touch sensing I/O */ |
||
| 28 | mjames | 74 | #endif /* DMA2 */ |
| 2 | mjames | 75 | #define TIM_TIM9_GPIO (0x00000000) /*!< TIM9 Channel1 is connected to GPIO */ |
| 76 | #define TIM_TIM9_LSE TIM_OR_TI1RMP_0 /*!< TIM9 Channel1 is connected to LSE internal clock */ |
||
| 77 | #define TIM_TIM9_GPIO1 TIM_OR_TI1RMP_1 /*!< TIM9 Channel1 is connected to GPIO */ |
||
| 78 | #define TIM_TIM9_GPIO2 TIM_OR_TI1RMP /*!< TIM9 Channel1 is connected to GPIO */ |
||
| 79 | |||
| 28 | mjames | 80 | #if defined(DMA2) |
| 2 | mjames | 81 | #define TIM_TIM10_TI1RMP (0x00000000) /*!< TIM10 Channel 1 depends on TI1_RMP */ |
| 82 | #define TIM_TIM10_RI TIM_OR_TI1_RMP_RI /*!< TIM10 Channel 1 is connected to RI */ |
||
| 83 | #define TIM_TIM10_ETR_LSE (0x00000000) /*!< TIM10 ETR input is connected to LSE clock */ |
||
| 84 | #define TIM_TIM10_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM10 ETR input is connected to TIM9 TGO */ |
||
| 28 | mjames | 85 | #endif /* DMA2 */ |
| 2 | mjames | 86 | #define TIM_TIM10_GPIO (0x00000000) /*!< TIM10 Channel1 is connected to GPIO */ |
| 87 | #define TIM_TIM10_LSI TIM_OR_TI1RMP_0 /*!< TIM10 Channel1 is connected to LSI internal clock */ |
||
| 88 | #define TIM_TIM10_LSE TIM_OR_TI1RMP_1 /*!< TIM10 Channel1 is connected to LSE internal clock */ |
||
| 89 | #define TIM_TIM10_RTC TIM_OR_TI1RMP /*!< TIM10 Channel1 is connected to RTC wakeup interrupt */ |
||
| 90 | |||
| 28 | mjames | 91 | #if defined(DMA2) |
| 2 | mjames | 92 | #define TIM_TIM11_TI1RMP (0x00000000) /*!< TIM11 Channel 1 depends on TI1_RMP */ |
| 93 | #define TIM_TIM11_RI TIM_OR_TI1_RMP_RI /*!< TIM11 Channel 1 is connected to RI */ |
||
| 94 | #define TIM_TIM11_ETR_LSE (0x00000000) /*!< TIM11 ETR input is connected to LSE clock */ |
||
| 95 | #define TIM_TIM11_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM11 ETR input is connected to TIM9 TGO */ |
||
| 28 | mjames | 96 | #endif /* DMA2 */ |
| 2 | mjames | 97 | #define TIM_TIM11_GPIO (0x00000000) /*!< TIM11 Channel1 is connected to GPIO */ |
| 98 | #define TIM_TIM11_MSI TIM_OR_TI1RMP_0 /*!< TIM11 Channel1 is connected to MSI internal clock */ |
||
| 99 | #define TIM_TIM11_HSE_RTC TIM_OR_TI1RMP_1 /*!< TIM11 Channel1 is connected to HSE_RTC clock */ |
||
| 100 | #define TIM_TIM11_GPIO1 TIM_OR_TI1RMP /*!< TIM11 Channel1 is connected to GPIO */ |
||
| 28 | mjames | 101 | /** |
| 102 | * @} |
||
| 103 | */ |
||
| 2 | mjames | 104 | |
| 28 | mjames | 105 | /** |
| 106 | * @} |
||
| 107 | */ |
||
| 108 | /* End of exported constants -------------------------------------------------*/ |
||
| 2 | mjames | 109 | |
| 28 | mjames | 110 | /* Exported macro ------------------------------------------------------------*/ |
| 111 | /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros |
||
| 112 | * @{ |
||
| 113 | */ |
||
| 2 | mjames | 114 | |
| 115 | /** |
||
| 116 | * @} |
||
| 28 | mjames | 117 | */ |
| 118 | /* End of exported macro -----------------------------------------------------*/ |
||
| 2 | mjames | 119 | |
| 28 | mjames | 120 | /* Private macro -------------------------------------------------------------*/ |
| 121 | /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros |
||
| 122 | * @{ |
||
| 123 | */ |
||
| 124 | #if defined(DMA2) |
||
| 125 | #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ |
||
| 126 | ( (((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO))) || \ |
||
| 127 | (((INSTANCE) == TIM3) && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO))) || \ |
||
| 128 | (((INSTANCE) == TIM9) && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2))) || \ |
||
| 129 | (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC))) || \ |
||
| 130 | (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1))) \ |
||
| 131 | ) |
||
| 132 | #else |
||
| 133 | #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ |
||
| 134 | ( (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2))) || \ |
||
| 135 | (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC))) || \ |
||
| 136 | (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1))) \ |
||
| 137 | ) |
||
| 138 | #endif /* DMA2 */ |
||
| 139 | |||
| 2 | mjames | 140 | /** |
| 141 | * @} |
||
| 28 | mjames | 142 | */ |
| 143 | /* End of private macro ------------------------------------------------------*/ |
||
| 2 | mjames | 144 | |
| 145 | /* Exported functions --------------------------------------------------------*/ |
||
| 28 | mjames | 146 | /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions |
| 2 | mjames | 147 | * @{ |
| 28 | mjames | 148 | */ |
| 2 | mjames | 149 | |
| 28 | mjames | 150 | /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions |
| 151 | * @brief Peripheral Control functions |
||
| 2 | mjames | 152 | * @{ |
| 153 | */ |
||
| 28 | mjames | 154 | /* Extended Control functions ************************************************/ |
| 155 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, |
||
| 156 | TIM_MasterConfigTypeDef *sMasterConfig); |
||
| 2 | mjames | 157 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); |
| 158 | /** |
||
| 159 | * @} |
||
| 160 | */ |
||
| 28 | mjames | 161 | |
| 2 | mjames | 162 | /** |
| 163 | * @} |
||
| 164 | */ |
||
| 28 | mjames | 165 | /* End of exported functions -------------------------------------------------*/ |
| 2 | mjames | 166 | |
| 167 | /** |
||
| 168 | * @} |
||
| 169 | */ |
||
| 170 | |||
| 171 | /** |
||
| 172 | * @} |
||
| 28 | mjames | 173 | */ |
| 2 | mjames | 174 | |
| 175 | #ifdef __cplusplus |
||
| 176 | } |
||
| 177 | #endif |
||
| 178 | |||
| 179 | |||
| 28 | mjames | 180 | #endif /* STM32L1xx_HAL_TIM_EX_H */ |
| 2 | mjames | 181 | |
| 182 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |