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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_hal_adc_ex.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of ADC HAL Extension module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 28 | mjames | 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
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| 2 | mjames | 11 | * |
| 28 | mjames | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 2 | mjames | 16 | * |
| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32L1xx_HAL_ADC_EX_H |
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| 22 | #define __STM32L1xx_HAL_ADC_EX_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32l1xx_hal_def.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | /** @addtogroup ADCEx |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |||
| 39 | /* Exported types ------------------------------------------------------------*/ |
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| 40 | /** @defgroup ADCEx_Exported_Types ADCEx Exported Types |
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| 41 | * @{ |
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| 42 | */ |
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| 43 | |||
| 44 | /** |
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| 45 | * @brief ADC Configuration injected Channel structure definition |
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| 46 | * @note Parameters of this structure are shared within 2 scopes: |
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| 47 | * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset |
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| 48 | * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, |
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| 49 | * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. |
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| 50 | * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. |
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| 51 | * ADC state can be either: |
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| 52 | * - For all parameters: ADC disabled |
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| 53 | * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. |
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| 54 | * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. |
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| 55 | */ |
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| 56 | typedef struct |
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| 57 | { |
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| 58 | uint32_t InjectedChannel; /*!< Selection of ADC channel to configure |
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| 59 | This parameter can be a value of @ref ADC_channels |
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| 60 | Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ |
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| 61 | uint32_t InjectedRank; /*!< Rank in the injected group sequencer |
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| 62 | This parameter must be a value of @ref ADCEx_injected_rank |
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| 63 | Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ |
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| 64 | uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. |
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| 65 | Unit: ADC clock cycles |
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| 66 | Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). |
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| 67 | This parameter can be a value of @ref ADC_sampling_times |
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| 68 | Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
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| 69 | If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
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| 70 | Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
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| 71 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
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| 72 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ |
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| 73 | uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). |
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| 74 | Offset value must be a positive number. |
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| 75 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), |
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| 76 | this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
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| 77 | uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. |
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| 78 | To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
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| 79 | This parameter must be a number between Min_Data = 1 and Max_Data = 4. |
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| 80 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 81 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 28 | mjames | 82 | FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
| 2 | mjames | 83 | Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
| 84 | Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
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| 85 | This parameter can be set to ENABLE or DISABLE. |
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| 86 | Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. |
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| 87 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 88 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 28 | mjames | 89 | FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one |
| 2 | mjames | 90 | This parameter can be set to ENABLE or DISABLE. |
| 91 | Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) |
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| 92 | Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) |
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| 93 | Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. |
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| 94 | To maintain JAUTO always enabled, DMA must be configured in circular mode. |
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| 95 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 96 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 97 | uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. |
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| 98 | If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. |
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| 99 | If set to external trigger source, triggering is on event rising edge. |
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| 100 | This parameter can be a value of @ref ADCEx_External_trigger_source_Injected |
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| 101 | Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). |
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| 102 | If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) |
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| 103 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 104 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 105 | uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. |
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| 106 | This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. |
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| 107 | If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. |
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| 108 | Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
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| 109 | configure a channel on injected group can impact the configuration of other channels previously set. */ |
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| 110 | }ADC_InjectionConfTypeDef; |
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| 111 | /** |
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| 112 | * @} |
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| 113 | */ |
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| 114 | |||
| 115 | |||
| 116 | /* Exported constants --------------------------------------------------------*/ |
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| 117 | |||
| 118 | /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants |
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| 119 | * @{ |
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| 120 | */ |
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| 121 | |||
| 122 | /** @defgroup ADCEx_injected_rank ADCEx rank into injected group |
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| 123 | * @{ |
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| 124 | */ |
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| 28 | mjames | 125 | #define ADC_INJECTED_RANK_1 (0x00000001U) |
| 126 | #define ADC_INJECTED_RANK_2 (0x00000002U) |
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| 127 | #define ADC_INJECTED_RANK_3 (0x00000003U) |
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| 128 | #define ADC_INJECTED_RANK_4 (0x00000004U) |
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| 2 | mjames | 129 | /** |
| 130 | * @} |
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| 131 | */ |
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| 132 | |||
| 133 | /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group |
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| 134 | * @{ |
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| 135 | */ |
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| 28 | mjames | 136 | #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) |
| 2 | mjames | 137 | #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) |
| 138 | #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) |
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| 139 | #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) |
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| 140 | /** |
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| 141 | * @} |
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| 142 | */ |
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| 143 | |||
| 144 | /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected |
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| 145 | * @{ |
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| 146 | */ |
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| 147 | /* External triggers for injected groups of ADC1 */ |
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| 148 | #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1 |
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| 149 | #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO |
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| 150 | #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4 |
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| 151 | #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO |
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| 152 | #define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ADC_EXTERNALTRIGINJEC_T4_CC1 |
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| 153 | #define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ADC_EXTERNALTRIGINJEC_T4_CC2 |
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| 154 | #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC_EXTERNALTRIGINJEC_T4_CC3 |
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| 155 | #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC_EXTERNALTRIGINJEC_T7_TRGO |
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| 156 | #define ADC_EXTERNALTRIGINJECCONV_T9_CC1 ADC_EXTERNALTRIGINJEC_T9_CC1 |
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| 157 | #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO |
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| 158 | #define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1 |
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| 159 | #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 |
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| 28 | mjames | 160 | #define ADC_INJECTED_SOFTWARE_START (0x00000010U) |
| 2 | mjames | 161 | /** |
| 162 | * @} |
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| 163 | */ |
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| 164 | |||
| 165 | /** |
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| 166 | * @} |
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| 167 | */ |
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| 168 | |||
| 169 | |||
| 170 | /* Private constants ---------------------------------------------------------*/ |
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| 171 | |||
| 172 | /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants |
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| 173 | * @{ |
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| 174 | */ |
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| 175 | |||
| 176 | /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected |
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| 177 | * @{ |
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| 178 | */ |
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| 179 | |||
| 180 | /* List of external triggers of injected group for ADC1: */ |
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| 181 | /* (used internally by HAL driver. To not use into HAL structure parameters) */ |
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| 28 | mjames | 182 | #define ADC_EXTERNALTRIGINJEC_T9_CC1 (0x00000000U) |
| 2 | mjames | 183 | #define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0)) |
| 184 | #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) |
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| 185 | #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
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| 186 | #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_2 )) |
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| 187 | #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) |
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| 188 | #define ADC_EXTERNALTRIGINJEC_T4_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) |
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| 189 | #define ADC_EXTERNALTRIGINJEC_T4_CC2 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
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| 190 | #define ADC_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 )) |
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| 191 | #define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) |
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| 192 | #define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 )) |
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| 193 | #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
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| 194 | /** |
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| 195 | * @} |
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| 196 | */ |
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| 197 | |||
| 198 | /** |
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| 199 | * @} |
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| 200 | */ |
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| 201 | |||
| 202 | |||
| 203 | /* Exported macro ------------------------------------------------------------*/ |
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| 204 | |||
| 205 | /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros |
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| 206 | * @{ |
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| 207 | */ |
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| 208 | /* Macro for internal HAL driver usage, and possibly can be used into code of */ |
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| 209 | /* final user. */ |
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| 210 | |||
| 211 | /** |
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| 212 | * @brief Selection of channels bank. |
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| 213 | * Note: Banks availability depends on devices categories. |
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| 214 | * This macro is intended to change bank selection quickly on the fly, |
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| 215 | * without going through ADC init structure update and execution of function |
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| 216 | * 'HAL_ADC_Init()'. |
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| 217 | * @param __HANDLE__: ADC handle |
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| 218 | * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank. |
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| 219 | * @retval None |
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| 220 | */ |
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| 221 | #define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \ |
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| 222 | MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__)) |
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| 223 | |||
| 224 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 225 | /** |
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| 226 | * @brief Configures the ADC channels speed. |
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| 227 | * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5. |
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| 228 | * - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is |
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| 229 | * in power down mode. |
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| 230 | * - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is |
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| 231 | * in power down mode. |
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| 232 | * - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in |
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| 233 | * power down mode. Otherwise, channel 13 is connected to OPAMP3 output and |
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| 234 | * routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. |
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| 235 | * (Note: OPAMP3 is available on STM32L1 Cat.4 only). |
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| 236 | * @param __CHANNEL__: ADC channel |
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| 237 | * This parameter can be one of the following values: |
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| 238 | * @arg ADC_CHANNEL_3: Channel 3 is selected. |
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| 239 | * @arg ADC_CHANNEL_8: Channel 8 is selected. |
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| 240 | * @arg ADC_CHANNEL_13: Channel 13 is selected. |
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| 241 | * @retval None |
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| 242 | */ |
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| 243 | #define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__) \ |
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| 244 | ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ |
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| 245 | )? \ |
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| 246 | (SET_BIT(COMP->CSR, COMP_CSR_FCH3)) \ |
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| 247 | : \ |
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| 248 | ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ |
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| 249 | )? \ |
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| 250 | (SET_BIT(COMP->CSR, COMP_CSR_FCH8)) \ |
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| 251 | : \ |
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| 252 | ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ |
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| 253 | )? \ |
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| 254 | (SET_BIT(COMP->CSR, COMP_CSR_RCH13)) \ |
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| 255 | : \ |
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| 256 | (SET_BIT(COMP->CSR, 0x00000000)) \ |
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| 257 | ) \ |
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| 258 | ) \ |
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| 259 | ) |
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| 260 | |||
| 261 | #define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__) \ |
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| 262 | ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ |
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| 263 | )? \ |
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| 264 | (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3)) \ |
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| 265 | : \ |
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| 266 | ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ |
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| 267 | )? \ |
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| 268 | (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8)) \ |
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| 269 | : \ |
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| 270 | ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ |
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| 271 | )? \ |
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| 272 | (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13)) \ |
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| 273 | : \ |
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| 274 | (SET_BIT(COMP->CSR, 0x00000000)) \ |
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| 275 | ) \ |
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| 276 | ) \ |
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| 277 | ) |
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| 278 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 279 | |||
| 280 | /** |
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| 281 | * @} |
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| 282 | */ |
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| 283 | |||
| 284 | /* Private macro ------------------------------------------------------------*/ |
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| 285 | |||
| 286 | /** @defgroup ADCEx_Private_Macro ADCEx Private Macro |
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| 287 | * @{ |
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| 288 | */ |
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| 289 | /* Macro reserved for internal HAL driver usage, not intended to be used in */ |
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| 290 | /* code of final user. */ |
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| 291 | |||
| 292 | /** |
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| 293 | * @brief Set ADC ranks available in register SQR1. |
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| 294 | * Register SQR1 bits availability depends on device category. |
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| 295 | * @param _NbrOfConversion_: Regular channel sequence length |
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| 296 | * @retval None |
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| 297 | */ |
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| 298 | #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 299 | #define __ADC_SQR1_SQXX (ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) |
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| 300 | #else |
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| 301 | #define __ADC_SQR1_SQXX (ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) |
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| 302 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 303 | |||
| 304 | /** |
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| 305 | * @brief Set the ADC's sample time for channel numbers between 30 and 31. |
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| 306 | * Register SMPR0 availability depends on device category. If register is not |
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| 307 | * available on the current device, this macro does nothing. |
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| 308 | * @retval None |
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| 309 | * @param _SAMPLETIME_: Sample time parameter. |
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| 310 | * @param _CHANNELNB_: Channel number. |
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| 311 | * @retval None |
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| 312 | */ |
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| 313 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 314 | #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ |
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| 315 | ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30))) |
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| 316 | #else |
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| 317 | #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ |
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| 28 | mjames | 318 | (0x00000000U) |
| 2 | mjames | 319 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 320 | |||
| 321 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 322 | /** |
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| 323 | * @brief Set the ADC's sample time for channel numbers between 20 and 29. |
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| 324 | * @param _SAMPLETIME_: Sample time parameter. |
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| 325 | * @param _CHANNELNB_: Channel number. |
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| 326 | * @retval None |
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| 327 | */ |
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| 328 | #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ |
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| 329 | ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) |
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| 330 | #else |
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| 331 | /** |
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| 332 | * @brief Set the ADC's sample time for channel numbers between 20 and 26. |
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| 333 | * @param _SAMPLETIME_: Sample time parameter. |
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| 334 | * @param _CHANNELNB_: Channel number. |
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| 335 | * @retval None |
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| 336 | */ |
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| 337 | #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ |
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| 338 | ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) |
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| 339 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 340 | |||
| 341 | /** |
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| 342 | * @brief Defines the highest channel available in register SMPR1. Channels |
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| 343 | * availability depends on device category: |
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| 344 | * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3 |
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| 345 | * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5 |
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| 346 | * @param None |
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| 347 | * @retval None |
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| 348 | */ |
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| 349 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 350 | #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29 |
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| 351 | #else |
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| 352 | #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26 |
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| 353 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 354 | |||
| 355 | |||
| 356 | /** |
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| 357 | * @brief Define mask of configuration bits of ADC and regular group in |
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| 358 | * register CR2 (bits of ADC enable, conversion start and injected group are |
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| 359 | * excluded of this mask). |
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| 360 | * @retval None |
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| 361 | */ |
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| 362 | #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 363 | #define ADC_CR2_MASK_ADCINIT() \ |
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| 364 | (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT) |
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| 365 | #else |
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| 366 | #define ADC_CR2_MASK_ADCINIT() \ |
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| 367 | (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT) |
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| 368 | #endif |
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| 369 | |||
| 370 | |||
| 371 | /** |
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| 372 | * @brief Get the maximum ADC conversion cycles on all channels. |
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| 373 | * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) |
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| 374 | * Approximation of sampling time within 2 ranges, returns the highest value: |
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| 375 | * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles} |
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| 376 | * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles} |
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| 377 | * Unit: ADC clock cycles |
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| 378 | * @param __HANDLE__: ADC handle |
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| 379 | * @retval ADC conversion cycles on all channels |
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| 380 | */ |
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| 381 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 382 | #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ |
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| 383 | (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ |
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| 384 | (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ |
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| 385 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \ |
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| 386 | (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ? \ |
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| 387 | \ |
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| 388 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ |
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| 389 | ) |
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| 390 | #else |
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| 391 | #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ |
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| 392 | (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ |
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| 393 | (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ |
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| 394 | (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ |
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| 395 | \ |
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| 396 | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ |
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| 397 | ) |
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| 398 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 399 | |||
| 400 | /** |
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| 401 | * @brief Get the ADC clock prescaler from ADC common control register |
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| 402 | * and convert it to its decimal number setting (refer to reference manual) |
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| 403 | * @retval None |
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| 404 | */ |
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| 405 | #define ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \ |
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| 406 | ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE))) |
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| 407 | |||
| 408 | /** |
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| 409 | * @brief Clear register SMPR0. |
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| 410 | * Register SMPR0 availability depends on device category. If register is not |
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| 411 | * available on the current device, this macro performs no action. |
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| 412 | * @param __HANDLE__: ADC handle |
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| 413 | * @retval None |
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| 414 | */ |
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| 415 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 416 | #define ADC_SMPR1_CLEAR(__HANDLE__) \ |
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| 417 | CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | \ |
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| 418 | ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ |
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| 419 | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ |
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| 420 | ADC_SMPR1_SMP20 )) |
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| 421 | |||
| 422 | #define ADC_SMPR0_CLEAR(__HANDLE__) \ |
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| 423 | (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30))) |
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| 424 | #else |
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| 425 | #define ADC_SMPR1_CLEAR(__HANDLE__) \ |
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| 426 | CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ |
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| 427 | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ |
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| 428 | ADC_SMPR1_SMP20 )) |
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| 429 | |||
| 430 | #define ADC_SMPR0_CLEAR(__HANDLE__) __NOP() |
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| 431 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 432 | |||
| 433 | /** |
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| 434 | * @brief Clear register CR2. |
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| 435 | * @param __HANDLE__: ADC handle |
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| 436 | * @retval None |
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| 437 | */ |
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| 438 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 439 | #define ADC_CR2_CLEAR(__HANDLE__) \ |
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| 440 | (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ |
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| 441 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ |
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| 442 | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ |
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| 443 | ADC_CR2_DMA | ADC_CR2_DELS | ADC_CR2_CFG | \ |
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| 444 | ADC_CR2_CONT | ADC_CR2_ADON )) \ |
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| 445 | ) |
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| 446 | #else |
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| 447 | #define ADC_CR2_CLEAR(__HANDLE__) \ |
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| 448 | (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ |
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| 449 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ |
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| 450 | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ |
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| 451 | ADC_CR2_DMA | ADC_CR2_DELS | \ |
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| 452 | ADC_CR2_CONT | ADC_CR2_ADON )) \ |
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| 453 | ) |
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| 454 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 455 | |||
| 456 | /** |
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| 457 | * @brief Set the sampling time of selected channel on register SMPR0 |
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| 458 | * Register SMPR0 availability depends on device category. If register is not |
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| 459 | * available on the current device, this macro performs no action. |
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| 460 | * @param __HANDLE__: ADC handle |
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| 461 | * @param _SAMPLETIME_: Sample time parameter. |
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| 462 | * @param __CHANNEL__: Channel number. |
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| 463 | * @retval None |
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| 464 | */ |
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| 465 | #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 466 | #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \ |
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| 467 | MODIFY_REG((__HANDLE__)->Instance->SMPR0, \ |
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| 468 | ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \ |
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| 469 | ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) ) |
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| 470 | #else |
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| 471 | #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP() |
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| 472 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 473 | |||
| 474 | |||
| 475 | #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ |
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| 476 | ((CHANNEL) == ADC_INJECTED_RANK_2) || \ |
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| 477 | ((CHANNEL) == ADC_INJECTED_RANK_3) || \ |
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| 478 | ((CHANNEL) == ADC_INJECTED_RANK_4) ) |
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| 479 | |||
| 480 | #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ |
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| 481 | ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ |
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| 482 | ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ |
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| 483 | ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) |
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| 484 | |||
| 485 | #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ |
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| 486 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ |
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| 487 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ |
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| 488 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ |
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| 489 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ |
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| 490 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ |
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| 491 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ |
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| 492 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ |
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| 493 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \ |
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| 494 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \ |
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| 495 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \ |
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| 496 | ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ |
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| 497 | ((REGTRIG) == ADC_SOFTWARE_START) ) |
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| 498 | |||
| 499 | /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification |
||
| 500 | * @{ |
||
| 501 | */ |
||
| 28 | mjames | 502 | #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U))) |
| 2 | mjames | 503 | /** |
| 504 | * @} |
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| 505 | */ |
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| 506 | |||
| 507 | /** |
||
| 508 | * @} |
||
| 509 | */ |
||
| 510 | |||
| 511 | |||
| 512 | /* Exported functions --------------------------------------------------------*/ |
||
| 513 | /** @addtogroup ADCEx_Exported_Functions |
||
| 514 | * @{ |
||
| 515 | */ |
||
| 516 | |||
| 517 | /* IO operation functions *****************************************************/ |
||
| 518 | /** @addtogroup ADCEx_Exported_Functions_Group1 |
||
| 519 | * @{ |
||
| 520 | */ |
||
| 521 | |||
| 522 | /* Blocking mode: Polling */ |
||
| 523 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); |
||
| 524 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); |
||
| 525 | HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
||
| 526 | |||
| 527 | /* Non-blocking mode: Interruption */ |
||
| 528 | HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); |
||
| 529 | HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); |
||
| 530 | |||
| 531 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
||
| 532 | uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); |
||
| 533 | |||
| 534 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ |
||
| 535 | void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); |
||
| 536 | /** |
||
| 537 | * @} |
||
| 538 | */ |
||
| 539 | |||
| 540 | |||
| 541 | /* Peripheral Control functions ***********************************************/ |
||
| 542 | /** @addtogroup ADCEx_Exported_Functions_Group2 |
||
| 543 | * @{ |
||
| 544 | */ |
||
| 545 | |||
| 546 | HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); |
||
| 547 | /** |
||
| 548 | * @} |
||
| 549 | */ |
||
| 550 | |||
| 551 | |||
| 552 | /** |
||
| 553 | * @} |
||
| 554 | */ |
||
| 555 | |||
| 556 | |||
| 557 | /** |
||
| 558 | * @} |
||
| 559 | */ |
||
| 560 | |||
| 561 | /** |
||
| 562 | * @} |
||
| 563 | */ |
||
| 564 | |||
| 565 | #ifdef __cplusplus |
||
| 566 | } |
||
| 567 | #endif |
||
| 568 | |||
| 569 | #endif /* __STM32L1xx_HAL_ADC_EX_H */ |
||
| 570 | |||
| 571 | |||
| 572 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |