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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32l1xx_hal_tim_ex.c |
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4 | * @author MCD Application Team |
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5 | * @brief TIM HAL module driver. |
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6 | * This file provides firmware functions to manage the following |
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28 | mjames | 7 | * functionalities of the Timer Extended peripheral: |
2 | mjames | 8 | * + Time Master and Slave synchronization configuration |
28 | mjames | 9 | * + Time OCRef clear configuration |
2 | mjames | 10 | * + Timer remapping capabilities configuration |
11 | @verbatim |
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12 | ============================================================================== |
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13 | ##### TIMER Extended features ##### |
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14 | ============================================================================== |
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15 | [..] |
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28 | mjames | 16 | The Timer Extended features include: |
2 | mjames | 17 | (#) Synchronization circuit to control the timer with external signals and to |
18 | interconnect several timers together. |
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19 | |||
20 | @endverbatim |
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21 | ****************************************************************************** |
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22 | * @attention |
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23 | * |
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28 | mjames | 24 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
25 | * All rights reserved.</center></h2> |
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2 | mjames | 26 | * |
28 | mjames | 27 | * This software component is licensed by ST under BSD 3-Clause license, |
28 | * the "License"; You may not use this file except in compliance with the |
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29 | * License. You may obtain a copy of the License at: |
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30 | * opensource.org/licenses/BSD-3-Clause |
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2 | mjames | 31 | * |
32 | ****************************************************************************** |
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28 | mjames | 33 | */ |
2 | mjames | 34 | |
35 | /* Includes ------------------------------------------------------------------*/ |
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36 | #include "stm32l1xx_hal.h" |
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37 | |||
38 | /** @addtogroup STM32L1xx_HAL_Driver |
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39 | * @{ |
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40 | */ |
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41 | |||
42 | /** @defgroup TIMEx TIMEx |
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43 | * @brief TIM Extended HAL module driver |
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44 | * @{ |
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45 | */ |
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46 | |||
47 | #ifdef HAL_TIM_MODULE_ENABLED |
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48 | |||
49 | /* Private typedef -----------------------------------------------------------*/ |
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50 | /* Private define ------------------------------------------------------------*/ |
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28 | mjames | 51 | /* Private macros ------------------------------------------------------------*/ |
2 | mjames | 52 | /* Private variables ---------------------------------------------------------*/ |
53 | /* Private function prototypes -----------------------------------------------*/ |
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54 | |||
28 | mjames | 55 | /* Exported functions --------------------------------------------------------*/ |
56 | /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions |
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2 | mjames | 57 | * @{ |
58 | */ |
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28 | mjames | 59 | /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions |
60 | * @brief Peripheral Control functions |
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61 | * |
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2 | mjames | 62 | @verbatim |
63 | ============================================================================== |
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64 | ##### Peripheral Control functions ##### |
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65 | ============================================================================== |
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66 | [..] |
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67 | This section provides functions allowing to: |
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28 | mjames | 68 | (+) Configure Master synchronization. |
69 | (+) Configure timer remapping capabilities. |
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2 | mjames | 70 | |
71 | @endverbatim |
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72 | * @{ |
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73 | */ |
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74 | |||
75 | /** |
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76 | * @brief Configures the TIM in master mode. |
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28 | mjames | 77 | * @param htim TIM handle. |
78 | * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that |
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2 | mjames | 79 | * contains the selected trigger output (TRGO) and the Master/Slave |
80 | * mode. |
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81 | * @retval HAL status |
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82 | */ |
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28 | mjames | 83 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, |
84 | TIM_MasterConfigTypeDef *sMasterConfig) |
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2 | mjames | 85 | { |
28 | mjames | 86 | uint32_t tmpcr2; |
87 | uint32_t tmpsmcr; |
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88 | |||
2 | mjames | 89 | /* Check the parameters */ |
90 | assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); |
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91 | assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
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92 | assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
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93 | |||
28 | mjames | 94 | /* Check input state */ |
2 | mjames | 95 | __HAL_LOCK(htim); |
96 | |||
28 | mjames | 97 | /* Change the handler state */ |
2 | mjames | 98 | htim->State = HAL_TIM_STATE_BUSY; |
99 | |||
28 | mjames | 100 | /* Get the TIMx CR2 register value */ |
101 | tmpcr2 = htim->Instance->CR2; |
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102 | |||
103 | /* Get the TIMx SMCR register value */ |
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104 | tmpsmcr = htim->Instance->SMCR; |
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105 | |||
2 | mjames | 106 | /* Reset the MMS Bits */ |
28 | mjames | 107 | tmpcr2 &= ~TIM_CR2_MMS; |
2 | mjames | 108 | /* Select the TRGO source */ |
28 | mjames | 109 | tmpcr2 |= sMasterConfig->MasterOutputTrigger; |
2 | mjames | 110 | |
28 | mjames | 111 | /* Update TIMx CR2 */ |
112 | htim->Instance->CR2 = tmpcr2; |
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2 | mjames | 113 | |
28 | mjames | 114 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
115 | { |
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116 | /* Reset the MSM Bit */ |
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117 | tmpsmcr &= ~TIM_SMCR_MSM; |
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118 | /* Set master mode */ |
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119 | tmpsmcr |= sMasterConfig->MasterSlaveMode; |
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120 | |||
121 | /* Update TIMx SMCR */ |
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122 | htim->Instance->SMCR = tmpsmcr; |
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123 | } |
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124 | |||
125 | /* Change the htim state */ |
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2 | mjames | 126 | htim->State = HAL_TIM_STATE_READY; |
127 | |||
128 | __HAL_UNLOCK(htim); |
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129 | |||
130 | return HAL_OK; |
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131 | } |
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132 | |||
133 | /** |
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28 | mjames | 134 | * @brief Configures the TIMx Remapping input capabilities. |
135 | * @param htim TIM handle. |
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136 | * @param Remap specifies the TIM remapping source. |
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2 | mjames | 137 | * |
28 | mjames | 138 | * For TIM2, the parameter can have the following values:(see note) |
2 | mjames | 139 | * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC |
140 | * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO |
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141 | * |
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28 | mjames | 142 | * For TIM3, the parameter can have the following values:(see note) |
2 | mjames | 143 | * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC |
144 | * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO |
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145 | * |
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28 | mjames | 146 | * For TIM9, the parameter is a combination of 2 fields (field1 | field2): |
147 | * |
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148 | * field1 can have the following values:(see note) |
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2 | mjames | 149 | * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO |
150 | * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O |
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28 | mjames | 151 | * |
152 | * field2 can have the following values: |
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2 | mjames | 153 | * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO |
154 | * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock |
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155 | * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO |
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156 | * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO |
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157 | * |
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28 | mjames | 158 | * For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): |
159 | * |
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160 | * field1 can have the following values:(see note) |
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2 | mjames | 161 | * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP |
162 | * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI |
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28 | mjames | 163 | * |
164 | * field2 can have the following values:(see note) |
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2 | mjames | 165 | * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock |
166 | * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO |
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28 | mjames | 167 | * |
168 | * field3 can have the following values: |
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2 | mjames | 169 | * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO |
170 | * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock |
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171 | * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock |
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172 | * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt |
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173 | * |
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28 | mjames | 174 | * For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): |
175 | * |
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176 | * field1 can have the following values:(see note) |
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2 | mjames | 177 | * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP |
178 | * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI |
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28 | mjames | 179 | * |
180 | * field2 can have the following values:(see note) |
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2 | mjames | 181 | * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock |
28 | mjames | 182 | * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO |
183 | * |
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184 | * field3 can have the following values: |
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185 | * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO |
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2 | mjames | 186 | * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock |
187 | * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock |
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188 | * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO |
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189 | * |
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28 | mjames | 190 | * @note Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices. |
191 | * |
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192 | * @retval HAL status |
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2 | mjames | 193 | */ |
194 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) |
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195 | { |
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196 | __HAL_LOCK(htim); |
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197 | |||
198 | /* Check parameters */ |
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28 | mjames | 199 | assert_param(IS_TIM_REMAP(htim->Instance, Remap)); |
2 | mjames | 200 | |
201 | /* Set the Timer remapping configuration */ |
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28 | mjames | 202 | WRITE_REG(htim->Instance->OR, Remap); |
2 | mjames | 203 | |
204 | __HAL_UNLOCK(htim); |
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205 | |||
206 | return HAL_OK; |
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207 | } |
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208 | |||
209 | /** |
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210 | * @} |
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211 | */ |
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212 | |||
213 | /** |
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214 | * @} |
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215 | */ |
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216 | |||
28 | mjames | 217 | |
218 | #endif /* HAL_TIM_MODULE_ENABLED */ |
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2 | mjames | 219 | /** |
220 | * @} |
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221 | */ |
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222 | |||
223 | /** |
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224 | * @} |
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225 | */ |
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226 | |||
227 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |