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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32l1xx_hal_adc.h
		4	* @author MCD Application Team
		5	* @brief Header file containing functions prototypes of ADC HAL library.
		6	******************************************************************************
		7	* @attention
		8	*
28	mjames	9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
		10	* All rights reserved.</center></h2>
2	mjames	11	*
28	mjames	12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
2	mjames	16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef __STM32L1xx_HAL_ADC_H
		22	#define __STM32L1xx_HAL_ADC_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32l1xx_hal_def.h"
		30
		31	/** @addtogroup STM32L1xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup ADC
		36	* @{
		37	*/
		38
		39	/* Exported types ------------------------------------------------------------*/
		40	/** @defgroup ADC_Exported_Types ADC Exported Types
		41	* @{
		42	*/
		43
		44	/**
		45	* @brief Structure definition of ADC and regular group initialization
		46	* @note Parameters of this structure are shared within 2 scopes:
		47	* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
		48	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
		49	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
		50	* ADC state can be either:
		51	* - For all parameters: ADC disabled
		52	* - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
		53	* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
		54	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
		55	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
		56	*/
		57	typedef struct
		58	{
		59	uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler.
		60	This parameter can be a value of @ref ADC_ClockPrescaler
		61	Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
		62	AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
		63	Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */
		64	uint32_t Resolution; /*!< Configures the ADC resolution.
		65	This parameter can be a value of @ref ADC_Resolution */
		66	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
		67	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
		68	This parameter can be a value of @ref ADC_Data_align */
		69	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
		70	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
		71	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
		72	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
		73	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
		74	Scan direction is upward: from rank1 to rank 'n'.
		75	This parameter can be a value of @ref ADC_Scan_mode */
		76	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
		77	This parameter can be a value of @ref ADC_EOCSelection.
		78	Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
		79	Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
		80	or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
		81	Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
		82	If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
		83	uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
		84	conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
		85	This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
		86	This parameter can be a value of @ref ADC_LowPowerAutoWait.
		87	Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
		88	Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
		89	and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).
		90	Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */
		91	uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
		92	This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
		93	This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */
		94	uint32_t ChannelsBank; /*!< Selects the ADC channels bank.
		95	This parameter can be a value of @ref ADC_ChannelsBank.
		96	Note: Banks availability depends on devices categories.
		97	Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */
28	mjames	98	FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
2	mjames	99	after the selected trigger occurred (software start or external trigger).
		100	This parameter can be set to ENABLE or DISABLE. */
		101	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
		102	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
		103	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
		104	This parameter must be a number between Min_Data = 1 and Max_Data = 28. */
		105	#else
		106	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
		107	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
		108	This parameter must be a number between Min_Data = 1 and Max_Data = 27. */
		109	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
28	mjames	110	FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
2	mjames	111	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
		112	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
		113	This parameter can be set to ENABLE or DISABLE. */
		114	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
		115	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
		116	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
		117	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
		118	If set to ADC_SOFTWARE_START, external triggers are disabled.
		119	If set to external trigger source, triggering is on event rising edge by default.
		120	This parameter can be a value of @ref ADC_External_trigger_source_Regular */
		121	uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
		122	If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
		123	This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
28	mjames	124	FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
2	mjames	125	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
		126	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
		127	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
		128	This parameter can be set to ENABLE or DISABLE. */
		129	}ADC_InitTypeDef;
		130
		131	/**
		132	* @brief Structure definition of ADC channel for regular group
		133	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
		134	* ADC can be either disabled or enabled without conversion on going on regular group.
		135	*/
		136	typedef struct
		137	{
		138	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
		139	This parameter can be a value of @ref ADC_channels
		140	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
		141	Maximum number of channels by device category (without taking in account each device package constraints):
		142	STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26.
		143	STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
		144	STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
		145	Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '.
		146	Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */
		147	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
		148	This parameter can be a value of @ref ADC_regular_rank
		149	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
		150	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
		151	Unit: ADC clock cycles
		152	Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
		153	This parameter can be a value of @ref ADC_sampling_times
		154	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
		155	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
		156	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
		157	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
		158	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
		159	}ADC_ChannelConfTypeDef;
		160
		161	/**
		162	* @brief ADC Configuration analog watchdog definition
		163	* @note The setting of these parameters with function is conditioned to ADC state.
		164	* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
		165	*/
		166	typedef struct
		167	{
		168	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
		169	This parameter can be a value of @ref ADC_analog_watchdog_mode. */
		170	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
		171	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
		172	This parameter can be a value of @ref ADC_channels. */
28	mjames	173	FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
2	mjames	174	This parameter can be set to ENABLE or DISABLE */
		175	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		176	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		177	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		178	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		179	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
		180	}ADC_AnalogWDGConfTypeDef;
		181
		182	/**
		183	* @brief HAL ADC state machine: ADC states definition (bitfields)
		184	*/
		185	/* States of ADC global scope */
28	mjames	186	#define HAL_ADC_STATE_RESET (0x00000000U) /!< ADC not yet initialized or disabled /
		187	#define HAL_ADC_STATE_READY (0x00000001U) /!< ADC peripheral ready for use /
		188	#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /!< ADC is busy to internal process (initialization, calibration) /
		189	#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /!< TimeOut occurrence /
2	mjames	190
		191	/* States of ADC errors */
28	mjames	192	#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /!< Internal error occurrence /
		193	#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /!< Configuration error occurrence /
		194	#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /!< DMA error occurrence /
2	mjames	195
		196	/* States of ADC group regular */
28	mjames	197	#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
2	mjames	198	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
28	mjames	199	#define HAL_ADC_STATE_REG_EOC (0x00000200U) /!< Conversion data available on group regular /
		200	#define HAL_ADC_STATE_REG_OVR (0x00000400U) /!< Overrun occurrence /
		201	#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /!< Not available on STM32L1 device: End Of Sampling flag raised /
2	mjames	202
		203	/* States of ADC group injected */
28	mjames	204	#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
2	mjames	205	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
28	mjames	206	#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /!< Conversion data available on group injected /
		207	#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /!< Not available on STM32L1 device: Injected queue overflow occurrence /
2	mjames	208
		209	/* States of ADC analog watchdogs */
28	mjames	210	#define HAL_ADC_STATE_AWD1 (0x00010000U) /!< Out-of-window occurrence of analog watchdog 1 /
		211	#define HAL_ADC_STATE_AWD2 (0x00020000U) /!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 /
		212	#define HAL_ADC_STATE_AWD3 (0x00040000U) /!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 /
2	mjames	213
		214	/* States of ADC multi-mode */
28	mjames	215	#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( /
2	mjames	216
		217
28	mjames	218	/**
2	mjames	219	* @brief ADC handle Structure definition
		220	*/
28	mjames	221	typedef struct __ADC_HandleTypeDef
2	mjames	222	{
		223	ADC_TypeDef Instance; /!< Register base address */
		224
		225	ADC_InitTypeDef Init; /!< ADC required parameters /
		226
		227	__IO uint32_t NbrOfConversionRank ; /!< ADC conversion rank counter /
		228
		229	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
		230
		231	HAL_LockTypeDef Lock; /!< ADC locking object /
		232
		233	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
		234
		235	__IO uint32_t ErrorCode; /!< ADC Error code /
28	mjames	236
		237	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		238	void (* ConvCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC conversion complete callback */
		239	void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC conversion DMA half-transfer callback */
		240	void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC analog watchdog 1 callback */
		241	void (* ErrorCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC error callback */
		242	void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC group injected conversion complete callback / /!< ADC end of sampling callback */
		243	void (* MspInitCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC Msp Init callback */
		244	void (* MspDeInitCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC Msp DeInit callback */
		245	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2	mjames	246	}ADC_HandleTypeDef;
28	mjames	247
		248	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2	mjames	249	/**
28	mjames	250	* @brief HAL ADC Callback ID enumeration definition
		251	*/
		252	typedef enum
		253	{
		254	HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /!< ADC conversion complete callback ID /
		255	HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /!< ADC conversion DMA half-transfer callback ID /
		256	HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /!< ADC analog watchdog 1 callback ID /
		257	HAL_ADC_ERROR_CB_ID = 0x03U, /!< ADC error callback ID /
		258	HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /!< ADC group injected conversion complete callback ID /
		259	HAL_ADC_MSPINIT_CB_ID = 0x09U, /!< ADC Msp Init callback ID /
		260	HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /!< ADC Msp DeInit callback ID /
		261	} HAL_ADC_CallbackIDTypeDef;
		262
		263	/**
		264	* @brief HAL ADC Callback pointer definition
		265	*/
		266	typedef void (pADC_CallbackTypeDef)(ADC_HandleTypeDef hadc); /!< pointer to a ADC callback function /
		267
		268	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		269
		270	/**
2	mjames	271	* @}
		272	*/
		273
		274
		275
		276	/* Exported constants --------------------------------------------------------*/
		277
		278	/** @defgroup ADC_Exported_Constants ADC Exported Constants
		279	* @{
		280	*/
		281
		282	/** @defgroup ADC_Error_Code ADC Error Code
		283	* @{
		284	*/
28	mjames	285	#define HAL_ADC_ERROR_NONE (0x00U) /!< No error /
		286	#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
2	mjames	287	enable/disable, erroneous state */
28	mjames	288	#define HAL_ADC_ERROR_OVR (0x02U) /!< Overrun error /
		289	#define HAL_ADC_ERROR_DMA (0x04U) /!< DMA transfer error /
		290
		291	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		292	#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /!< Invalid Callback error /
		293	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2	mjames	294	/**
		295	* @}
		296	*/
		297
		298	/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
		299	* @{
		300	*/
28	mjames	301	#define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler /
2	mjames	302	#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 /
		303	#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 /
		304	/**
		305	* @}
		306	*/
		307
		308	/** @defgroup ADC_Resolution ADC Resolution
		309	* @{
		310	*/
28	mjames	311	#define ADC_RESOLUTION_12B (0x00000000U) /!< ADC 12-bit resolution /
2	mjames	312	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /!< ADC 10-bit resolution /
		313	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /!< ADC 8-bit resolution /
		314	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /!< ADC 6-bit resolution /
		315	/**
		316	* @}
		317	*/
		318
		319	/** @defgroup ADC_Data_align ADC Data_align
		320	* @{
		321	*/
28	mjames	322	#define ADC_DATAALIGN_RIGHT (0x00000000U)
2	mjames	323	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
		324	/**
		325	* @}
		326	*/
		327
		328	/** @defgroup ADC_Scan_mode ADC Scan mode
		329	* @{
		330	*/
28	mjames	331	#define ADC_SCAN_DISABLE (0x00000000U)
2	mjames	332	#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
		333	/**
		334	* @}
		335	*/
		336
		337	/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
		338	* @{
		339	*/
28	mjames	340	#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
2	mjames	341	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
		342	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
		343	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
		344	/**
		345	* @}
		346	*/
		347
		348	/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
		349	* @{
		350	*/
		351	/* List of external triggers with generic trigger name, sorted by trigger */
		352	/* name: */
		353
		354	/* External triggers of regular group for ADC1 */
		355	#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3
		356	#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
		357	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO
		358	#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1
		359	#define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3
		360	#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
		361	#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
		362	#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO
		363	#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO
		364	#define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2
		365	#define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO
		366	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
28	mjames	367	#define ADC_SOFTWARE_START (0x00000010U)
2	mjames	368	/**
		369	* @}
		370	*/
		371
		372	/** @defgroup ADC_EOCSelection ADC EOCSelection
		373	* @{
		374	*/
28	mjames	375	#define ADC_EOC_SEQ_CONV (0x00000000U)
2	mjames	376	#define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS)
		377	/**
		378	* @}
		379	*/
		380
		381	/** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait
		382	* @{
		383	*/
		384	/!< Note : For compatibility with other STM32 devices with ADC autowait /
		385	/* feature limited to enable or disable settings: */
		386	/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */
		387
28	mjames	388	#define ADC_AUTOWAIT_DISABLE (0x00000000U)
2	mjames	389	#define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read /
		390	#define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /!< Insert a delay between ADC conversions: 7 APB clock cycles /
		391	#define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 15 APB clock cycles /
		392	#define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /!< Insert a delay between ADC conversions: 31 APB clock cycles /
		393	#define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 63 APB clock cycles /
		394	#define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 )) /!< Insert a delay between ADC conversions: 127 APB clock cycles /
		395	#define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 255 APB clock cycles /
		396
		397	/**
		398	* @}
		399	*/
		400
		401	/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
		402	* @{
		403	*/
28	mjames	404	#define ADC_AUTOPOWEROFF_DISABLE (0x00000000U)
2	mjames	405	#define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /!< ADC power off when ADC is not converting (idle phase) /
		406	#define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) /
		407	#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI \| ADC_CR1_PDD)) /!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions /
		408	/**
		409	* @}
		410	*/
		411
		412
		413	/** @defgroup ADC_ChannelsBank ADC ChannelsBank
		414	* @{
		415	*/
		416	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
28	mjames	417	#define ADC_CHANNELS_BANK_A (0x00000000U)
2	mjames	418	#define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG)
		419
		420	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) \|\| \
		421	((BANK) == ADC_CHANNELS_BANK_B) )
		422	#else
28	mjames	423	#define ADC_CHANNELS_BANK_A (0x00000000U)
2	mjames	424
		425	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
		426	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		427	/**
		428	* @}
		429	*/
		430
		431	/** @defgroup ADC_channels ADC channels
		432	* @{
		433	*/
		434	/* Note: Depending on devices, some channels may not be available on package */
		435	/* pins. Refer to device datasheet for channels availability. */
28	mjames	436	#define ADC_CHANNEL_0 (0x00000000U) /* Channel different in bank A and bank B */
2	mjames	437	#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
		438	#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
		439	#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
		440	#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */
		441	#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
		442	#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
		443	#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
		444	#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */
		445	#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
		446	#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
		447	#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
		448	#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */
		449	#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
		450	#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
		451	#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
		452	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */
		453	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
		454	#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
		455	#define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
		456	#define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
		457	#define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
		458	#define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */
		459	#define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
		460	#define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */
		461	#define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
		462	#define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
		463	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
		464	#define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
		465	#define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
		466	#define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
		467	#define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
		468	#define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
		469	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		470
		471	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
		472	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
		473	#define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
		474
		475	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
		476	#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */
		477	#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */
		478	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD)
		479	#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */
		480	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD */
		481	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		482	/**
		483	* @}
		484	*/
		485
		486	/** @defgroup ADC_sampling_times ADC sampling times
		487	* @{
		488	*/
28	mjames	489	#define ADC_SAMPLETIME_4CYCLES (0x00000000U) /!< Sampling time 4 ADC clock cycles /
2	mjames	490	#define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /!< Sampling time 9 ADC clock cycles /
		491	#define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /!< Sampling time 16 ADC clock cycles /
		492	#define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 \| ADC_SMPR3_SMP0_0)) /!< Sampling time 24 ADC clock cycles /
		493	#define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /!< Sampling time 48 ADC clock cycles /
		494	#define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_0)) /!< Sampling time 96 ADC clock cycles /
		495	#define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_1)) /!< Sampling time 192 ADC clock cycles /
		496	#define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /!< Sampling time 384 ADC clock cycles /
		497	/**
		498	* @}
		499	*/
		500
		501	/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
		502	* @{
		503	*/
		504	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \
		505	(ADC_SMPR3_SMP9_2 \| ADC_SMPR3_SMP8_2 \| ADC_SMPR3_SMP7_2 \| ADC_SMPR3_SMP6_2 \| \
		506	ADC_SMPR3_SMP5_2 \| ADC_SMPR3_SMP4_2 \| ADC_SMPR3_SMP3_2 \| ADC_SMPR3_SMP2_2 \| \
		507	ADC_SMPR3_SMP1_2 \| ADC_SMPR3_SMP0_2)
		508	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
		509	(ADC_SMPR2_SMP19_2 \| ADC_SMPR2_SMP18_2 \| ADC_SMPR2_SMP17_2 \| ADC_SMPR2_SMP16_2 \| \
		510	ADC_SMPR2_SMP15_2 \| ADC_SMPR2_SMP14_2 \| ADC_SMPR2_SMP13_2 \| ADC_SMPR2_SMP12_2 \| \
		511	ADC_SMPR2_SMP11_2 \| ADC_SMPR2_SMP10_2)
		512	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
		513	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
		514	(ADC_SMPR1_SMP26_2 \| ADC_SMPR1_SMP25_2 \| ADC_SMPR1_SMP24_2 \| ADC_SMPR1_SMP23_2 \| \
		515	ADC_SMPR1_SMP22_2 \| ADC_SMPR1_SMP21_2 \| ADC_SMPR1_SMP20_2)
		516	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
		517	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
		518	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
		519	(ADC_SMPR1_SMP29_2 \| ADC_SMPR1_SMP28_2 \| ADC_SMPR1_SMP27_2 \| ADC_SMPR1_SMP26_2 \| \
		520	ADC_SMPR1_SMP25_2 \| ADC_SMPR1_SMP24_2 \| ADC_SMPR1_SMP23_2 \| ADC_SMPR1_SMP22_2 \| \
		521	ADC_SMPR1_SMP21_2 \| ADC_SMPR1_SMP20_2)
		522	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \
		523	(ADC_SMPR0_SMP31_2 \| ADC_SMPR0_SMP30_2 )
		524	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		525
		526	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \
		527	(ADC_SMPR3_SMP9_1 \| ADC_SMPR3_SMP8_1 \| ADC_SMPR3_SMP7_1 \| ADC_SMPR3_SMP6_1 \| \
		528	ADC_SMPR3_SMP5_1 \| ADC_SMPR3_SMP4_1 \| ADC_SMPR3_SMP3_1 \| ADC_SMPR3_SMP2_1 \| \
		529	ADC_SMPR3_SMP1_1 \| ADC_SMPR3_SMP0_1)
		530	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
		531	(ADC_SMPR2_SMP19_1 \| ADC_SMPR2_SMP18_1 \| ADC_SMPR2_SMP17_1 \| ADC_SMPR2_SMP16_1 \| \
		532	ADC_SMPR2_SMP15_1 \| ADC_SMPR2_SMP14_1 \| ADC_SMPR2_SMP13_1 \| ADC_SMPR2_SMP12_1 \| \
		533	ADC_SMPR2_SMP11_1 \| ADC_SMPR2_SMP10_1)
		534	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
		535	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
		536	(ADC_SMPR1_SMP26_1 \| ADC_SMPR1_SMP25_1 \| ADC_SMPR1_SMP24_1 \| ADC_SMPR1_SMP23_1 \| \
		537	ADC_SMPR1_SMP22_1 \| ADC_SMPR1_SMP21_1 \| ADC_SMPR1_SMP20_1)
		538	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
		539	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
		540	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
		541	(ADC_SMPR1_SMP29_1 \| ADC_SMPR1_SMP28_1 \| ADC_SMPR1_SMP27_1 \| ADC_SMPR1_SMP26_1 \| \
		542	ADC_SMPR1_SMP25_1 \| ADC_SMPR1_SMP24_1 \| ADC_SMPR1_SMP23_1 \| ADC_SMPR1_SMP22_1 \| \
		543	ADC_SMPR1_SMP21_1 \| ADC_SMPR1_SMP20_1)
		544	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \
		545	(ADC_SMPR0_SMP31_1 \| ADC_SMPR0_SMP30_1 )
		546	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		547
		548	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \
		549	(ADC_SMPR3_SMP9_0 \| ADC_SMPR3_SMP8_0 \| ADC_SMPR3_SMP7_0 \| ADC_SMPR3_SMP6_0 \| \
		550	ADC_SMPR3_SMP5_0 \| ADC_SMPR3_SMP4_0 \| ADC_SMPR3_SMP3_0 \| ADC_SMPR3_SMP2_0 \| \
		551	ADC_SMPR3_SMP1_0 \| ADC_SMPR3_SMP0_0)
		552	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
		553	(ADC_SMPR2_SMP19_0 \| ADC_SMPR2_SMP18_0 \| ADC_SMPR2_SMP17_0 \| ADC_SMPR2_SMP16_0 \| \
		554	ADC_SMPR2_SMP15_0 \| ADC_SMPR2_SMP14_0 \| ADC_SMPR2_SMP13_0 \| ADC_SMPR2_SMP12_0 \| \
		555	ADC_SMPR2_SMP11_0 \| ADC_SMPR2_SMP10_0)
		556	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
		557	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
		558	(ADC_SMPR1_SMP26_0 \| ADC_SMPR1_SMP25_0 \| ADC_SMPR1_SMP24_0 \| ADC_SMPR1_SMP23_0 \| \
		559	ADC_SMPR1_SMP22_0 \| ADC_SMPR1_SMP21_0 \| ADC_SMPR1_SMP20_0)
		560	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
		561	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
		562	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
		563	(ADC_SMPR1_SMP29_0 \| ADC_SMPR1_SMP28_0 \| ADC_SMPR1_SMP27_0 \| ADC_SMPR1_SMP26_0 \| \
		564	ADC_SMPR1_SMP25_0 \| ADC_SMPR1_SMP24_0 \| ADC_SMPR1_SMP23_0 \| ADC_SMPR1_SMP22_0 \| \
		565	ADC_SMPR1_SMP21_0 \| ADC_SMPR1_SMP20_0)
		566	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \
		567	(ADC_SMPR0_SMP31_0 \| ADC_SMPR0_SMP30_0 )
		568	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		569	/**
		570	* @}
		571	*/
		572
		573	/** @defgroup ADC_regular_rank ADC rank into regular group
		574	* @{
		575	*/
28	mjames	576	#define ADC_REGULAR_RANK_1 (0x00000001U)
		577	#define ADC_REGULAR_RANK_2 (0x00000002U)
		578	#define ADC_REGULAR_RANK_3 (0x00000003U)
		579	#define ADC_REGULAR_RANK_4 (0x00000004U)
		580	#define ADC_REGULAR_RANK_5 (0x00000005U)
		581	#define ADC_REGULAR_RANK_6 (0x00000006U)
		582	#define ADC_REGULAR_RANK_7 (0x00000007U)
		583	#define ADC_REGULAR_RANK_8 (0x00000008U)
		584	#define ADC_REGULAR_RANK_9 (0x00000009U)
		585	#define ADC_REGULAR_RANK_10 (0x0000000AU)
		586	#define ADC_REGULAR_RANK_11 (0x0000000BU)
		587	#define ADC_REGULAR_RANK_12 (0x0000000CU)
		588	#define ADC_REGULAR_RANK_13 (0x0000000DU)
		589	#define ADC_REGULAR_RANK_14 (0x0000000EU)
		590	#define ADC_REGULAR_RANK_15 (0x0000000FU)
		591	#define ADC_REGULAR_RANK_16 (0x00000010U)
		592	#define ADC_REGULAR_RANK_17 (0x00000011U)
		593	#define ADC_REGULAR_RANK_18 (0x00000012U)
		594	#define ADC_REGULAR_RANK_19 (0x00000013U)
		595	#define ADC_REGULAR_RANK_20 (0x00000014U)
		596	#define ADC_REGULAR_RANK_21 (0x00000015U)
		597	#define ADC_REGULAR_RANK_22 (0x00000016U)
		598	#define ADC_REGULAR_RANK_23 (0x00000017U)
		599	#define ADC_REGULAR_RANK_24 (0x00000018U)
		600	#define ADC_REGULAR_RANK_25 (0x00000019U)
		601	#define ADC_REGULAR_RANK_26 (0x0000001AU)
		602	#define ADC_REGULAR_RANK_27 (0x0000001BU)
2	mjames	603	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
28	mjames	604	#define ADC_REGULAR_RANK_28 (0x0000001CU)
2	mjames	605	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		606	/**
		607	* @}
		608	*/
		609
		610	/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
		611	* @{
		612	*/
28	mjames	613	#define ADC_ANALOGWATCHDOG_NONE (0x00000000U)
2	mjames	614	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
		615	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
		616	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		617	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
		618	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
		619	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		620	/**
		621	* @}
		622	*/
		623
		624	/** @defgroup ADC_conversion_group ADC conversion group
		625	* @{
		626	*/
		627	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
		628	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
		629	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
		630	/**
		631	* @}
		632	*/
		633
		634	/** @defgroup ADC_Event_type ADC Event type
		635	* @{
		636	*/
		637	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /!< ADC Analog watchdog event /
		638	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /!< ADC overrun event /
		639	/**
		640	* @}
		641	*/
		642
		643	/** @defgroup ADC_interrupts_definition ADC interrupts definition
		644	* @{
		645	*/
		646	#define ADC_IT_EOC ADC_CR1_EOCIE /!< ADC End of Regular Conversion interrupt source /
		647	#define ADC_IT_JEOC ADC_CR1_JEOCIE /!< ADC End of Injected Conversion interrupt source /
		648	#define ADC_IT_AWD ADC_CR1_AWDIE /!< ADC Analog watchdog interrupt source /
		649	#define ADC_IT_OVR ADC_CR1_OVRIE /!< ADC overrun interrupt source /
		650	/**
		651	* @}
		652	*/
		653
		654	/** @defgroup ADC_flags_definition ADC flags definition
		655	* @{
		656	*/
		657	#define ADC_FLAG_AWD ADC_SR_AWD /!< ADC Analog watchdog flag /
		658	#define ADC_FLAG_EOC ADC_SR_EOC /!< ADC End of Regular conversion flag /
		659	#define ADC_FLAG_JEOC ADC_SR_JEOC /!< ADC End of Injected conversion flag /
		660	#define ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC Injected group start flag /
		661	#define ADC_FLAG_STRT ADC_SR_STRT /!< ADC Regular group start flag /
		662	#define ADC_FLAG_OVR ADC_SR_OVR /!< ADC overrun flag /
		663	#define ADC_FLAG_ADONS ADC_SR_ADONS /!< ADC ready status flag /
		664	#define ADC_FLAG_RCNR ADC_SR_RCNR /!< ADC Regular group ready status flag /
		665	#define ADC_FLAG_JCNR ADC_SR_JCNR /!< ADC Injected group ready status flag /
		666	/**
		667	* @}
		668	*/
		669
		670	/**
		671	* @}
		672	*/
		673
		674
		675	/* Private constants ---------------------------------------------------------*/
		676
		677	/** @addtogroup ADC_Private_Constants ADC Private Constants
		678	* @{
		679	*/
		680
		681	/* List of external triggers of regular group for ADC1: */
		682	/* (used internally by HAL driver. To not use into HAL structure parameters) */
		683
		684	/* External triggers of regular group for ADC1 */
28	mjames	685	#define ADC_EXTERNALTRIG_T9_CC2 (0x00000000U)
2	mjames	686	#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0))
		687	#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
		688	#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
		689	#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 ))
		690	#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
		691	#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 ))
		692	#define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
		693	#define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 ))
		694	#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0))
		695	#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 ))
		696	#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
		697
		698	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
		699	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD \| \
		700	ADC_FLAG_OVR)
		701
		702	/**
		703	* @}
		704	*/
		705
		706
		707	/* Exported macro ------------------------------------------------------------*/
		708
		709	/** @defgroup ADC_Exported_Macros ADC Exported Macros
		710	* @{
		711	*/
		712	/* Macro for internal HAL driver usage, and possibly can be used into code of */
		713	/* final user. */
		714
		715	/**
		716	* @brief Enable the ADC peripheral
		717	* @param __HANDLE__: ADC handle
		718	* @retval None
		719	*/
		720	#define __HAL_ADC_ENABLE(__HANDLE__) \
		721	(__HANDLE__)->Instance->CR2 \|= ADC_CR2_ADON
		722
		723	/**
		724	* @brief Disable the ADC peripheral
		725	* @param __HANDLE__: ADC handle
		726	* @retval None
		727	*/
		728	#define __HAL_ADC_DISABLE(__HANDLE__) \
		729	(__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON
		730
		731	/**
		732	* @brief Enable the ADC end of conversion interrupt.
		733	* @param __HANDLE__: ADC handle
		734	* @param __INTERRUPT__: ADC Interrupt
		735	* This parameter can be any combination of the following values:
		736	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		737	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		738	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		739	* @arg ADC_IT_OVR: ADC overrun interrupt source
		740	* @retval None
		741	*/
		742	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
		743	(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		744
		745	/**
		746	* @brief Disable the ADC end of conversion interrupt.
		747	* @param __HANDLE__: ADC handle
		748	* @param __INTERRUPT__: ADC Interrupt
		749	* This parameter can be any combination of the following values:
		750	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		751	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		752	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		753	* @arg ADC_IT_OVR: ADC overrun interrupt source
		754	* @retval None
		755	*/
		756	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
		757	(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		758
		759	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
		760	* @param __HANDLE__: ADC handle
		761	* @param __INTERRUPT__: ADC interrupt source to check
		762	* This parameter can be any combination of the following values:
		763	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		764	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		765	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		766	* @arg ADC_IT_OVR: ADC overrun interrupt source
		767	* @retval State of interruption (SET or RESET)
		768	*/
		769	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
		770	(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
		771
		772	/**
		773	* @brief Get the selected ADC's flag status.
		774	* @param __HANDLE__: ADC handle
		775	* @param __FLAG__: ADC flag
		776	* This parameter can be any combination of the following values:
		777	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		778	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		779	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		780	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		781	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		782	* @arg ADC_FLAG_OVR: ADC overrun flag
		783	* @arg ADC_FLAG_ADONS: ADC ready status flag
		784	* @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
		785	* @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
		786	* @retval None
		787	*/
		788	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
		789	((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
		790
		791	/**
		792	* @brief Clear the ADC's pending flags
		793	* @param __HANDLE__: ADC handle
		794	* @param __FLAG__: ADC flag
		795	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		796	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		797	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		798	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		799	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		800	* @arg ADC_FLAG_OVR: ADC overrun flag
		801	* @arg ADC_FLAG_ADONS: ADC ready status flag
		802	* @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
		803	* @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
		804	* @retval None
		805	*/
		806	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
		807	(((__HANDLE__)->Instance->SR) = ~(__FLAG__))
		808
		809	/** @brief Reset ADC handle state
28	mjames	810	* @param __HANDLE__ ADC handle
2	mjames	811	* @retval None
		812	*/
28	mjames	813	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2	mjames	814	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
28	mjames	815	do{ \
		816	(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
		817	(__HANDLE__)->MspInitCallback = NULL; \
		818	(__HANDLE__)->MspDeInitCallback = NULL; \
		819	} while(0)
		820	#else
		821	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
2	mjames	822	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
28	mjames	823	#endif
2	mjames	824
		825	/**
		826	* @}
		827	*/
		828
		829	/* Private macro ------------------------------------------------------------*/
		830
		831	/** @defgroup ADC_Private_Macros ADC Private Macros
		832	* @{
		833	*/
		834	/* Macro reserved for internal HAL driver usage, not intended to be used in */
		835	/* code of final user. */
		836
		837	/**
		838	* @brief Verification of ADC state: enabled or disabled
		839	* @param __HANDLE__: ADC handle
		840	* @retval SET (ADC enabled) or RESET (ADC disabled)
		841	*/
		842	#define ADC_IS_ENABLE(__HANDLE__) \
		843	((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
		844	) ? SET : RESET)
		845
		846	/**
		847	* @brief Test if conversion trigger of regular group is software start
		848	* or external trigger.
		849	* @param __HANDLE__: ADC handle
		850	* @retval SET (software start) or RESET (external trigger)
		851	*/
		852	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
		853	(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
		854
		855	/**
		856	* @brief Test if conversion trigger of injected group is software start
		857	* or external trigger.
		858	* @param __HANDLE__: ADC handle
		859	* @retval SET (software start) or RESET (external trigger)
		860	*/
		861	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
		862	(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
		863
		864	/**
		865	* @brief Simultaneously clears and sets specific bits of the handle State
		866	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
		867	* the first parameter is the ADC handle State, the second parameter is the
		868	* bit field to clear, the third and last parameter is the bit field to set.
		869	* @retval None
		870	*/
		871	#define ADC_STATE_CLR_SET MODIFY_REG
		872
		873	/**
		874	* @brief Clear ADC error code (set it to error code: "no error")
		875	* @param __HANDLE__: ADC handle
		876	* @retval None
		877	*/
		878	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
		879	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
		880
		881	/**
		882	* @brief Set ADC number of ranks into regular channel sequence length.
		883	* @param _NbrOfConversion_: Regular channel sequence length
		884	* @retval None
		885	*/
		886	#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
		887	(((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
		888
		889	/**
		890	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
		891	* @param _SAMPLETIME_: Sample time parameter.
		892	* @param _CHANNELNB_: Channel number.
		893	* @retval None
		894	*/
		895	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
		896	((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
		897
		898	/**
		899	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
		900	* @param _SAMPLETIME_: Sample time parameter.
		901	* @param _CHANNELNB_: Channel number.
		902	* @retval None
		903	*/
		904	#define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) \
		905	((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
		906
		907	/**
		908	* @brief Set the selected regular channel rank for rank between 1 and 6.
		909	* @param _CHANNELNB_: Channel number.
		910	* @param _RANKNB_: Rank number.
		911	* @retval None
		912	*/
		913	#define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) \
		914	((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
		915
		916	/**
		917	* @brief Set the selected regular channel rank for rank between 7 and 12.
		918	* @param _CHANNELNB_: Channel number.
		919	* @param _RANKNB_: Rank number.
		920	* @retval None
		921	*/
		922	#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) \
		923	((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
		924
		925	/**
		926	* @brief Set the selected regular channel rank for rank between 13 and 18.
		927	* @param _CHANNELNB_: Channel number.
		928	* @param _RANKNB_: Rank number.
		929	* @retval None
		930	*/
		931	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
		932	((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
		933
		934	/**
		935	* @brief Set the selected regular channel rank for rank between 19 and 24.
		936	* @param _CHANNELNB_: Channel number.
		937	* @param _RANKNB_: Rank number.
		938	* @retval None
		939	*/
		940	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
		941	((_CHANNELNB_) << (5 * ((_RANKNB_) - 19)))
		942
		943	/**
		944	* @brief Set the selected regular channel rank for rank between 25 and 28.
		945	* @param _CHANNELNB_: Channel number.
		946	* @param _RANKNB_: Rank number.
		947	* @retval None
		948	*/
		949	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
		950	((_CHANNELNB_) << (5 * ((_RANKNB_) - 25)))
		951
		952	/**
		953	* @brief Set the injected sequence length.
		954	* @param _JSQR_JL_: Sequence length.
		955	* @retval None
		956	*/
		957	#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << 20)
		958
		959	/**
		960	* @brief Set the selected injected channel rank
		961	* Note: on STM32L1 devices, channel rank position in JSQR register
		962	* is depending on total number of ranks selected into
		963	* injected sequencer (ranks sequence starting from 4-JL)
		964	* @param _CHANNELNB_: Channel number.
		965	* @param _RANKNB_: Rank number.
		966	* @param _JSQR_JL_: Sequence length.
		967	* @retval None
		968	*/
		969	#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
		970	((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
		971
		972	/**
		973	* @brief Enable the ADC DMA continuous request.
		974	* @param _DMACONTREQ_MODE_: DMA continuous request mode.
		975	* @retval None
		976	*/
		977	#define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) \
		978	((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS))
		979
		980	/**
		981	* @brief Enable ADC continuous conversion mode.
		982	* @param _CONTINUOUS_MODE_: Continuous mode.
		983	* @retval None
		984	*/
		985	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
		986	((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
		987
		988	/**
		989	* @brief Configures the number of discontinuous conversions for the regular group channels.
		990	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
		991	* @retval None
		992	*/
		993	#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
		994	(((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
		995
		996	/**
		997	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
		998	* @param _SCAN_MODE_: Scan conversion mode.
		999	* @retval None
		1000	*/
		1001	/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
		1002	/* is equivalent to ADC_SCAN_ENABLE. */
		1003	#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
		1004	(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) \|\| ((_SCAN_MODE_) == ENABLE) \
		1005	)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
		1006	)
		1007
		1008
		1009	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\| \
		1010	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) \|\| \
		1011	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) )
		1012
		1013	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
		1014	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
		1015	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
		1016	((RESOLUTION) == ADC_RESOLUTION_6B) )
		1017
		1018	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
		1019	((RESOLUTION) == ADC_RESOLUTION_6B) )
		1020
		1021	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
		1022	((ALIGN) == ADC_DATAALIGN_LEFT) )
		1023
		1024	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
		1025	((SCAN_MODE) == ADC_SCAN_ENABLE) )
		1026
		1027	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
		1028	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
		1029	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
		1030	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
		1031
		1032	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \|\| \
		1033	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
		1034	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
		1035	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) \|\| \
		1036	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) \|\| \
		1037	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
		1038	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
		1039	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
		1040	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
		1041	((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) \|\| \
		1042	((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) \|\| \
		1043	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
		1044	((REGTRIG) == ADC_SOFTWARE_START) )
		1045
		1046	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
		1047	((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
		1048
		1049	#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) \|\| \
		1050	((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) \|\| \
		1051	((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) \|\| \
		1052	((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) \|\| \
		1053	((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) \|\| \
		1054	((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) \|\| \
		1055	((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) \|\| \
		1056	((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) )
		1057
		1058	#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) \|\| \
		1059	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) \|\| \
		1060	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) \|\| \
		1061	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) )
		1062
		1063	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
		1064
		1065	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) \|\| \
		1066	((BANK) == ADC_CHANNELS_BANK_B) )
		1067	#else
		1068
		1069	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
		1070	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		1071
		1072	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
		1073	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
		1074	((CHANNEL) == ADC_CHANNEL_1) \|\| \
		1075	((CHANNEL) == ADC_CHANNEL_2) \|\| \
		1076	((CHANNEL) == ADC_CHANNEL_3) \|\| \
		1077	((CHANNEL) == ADC_CHANNEL_4) \|\| \
		1078	((CHANNEL) == ADC_CHANNEL_5) \|\| \
		1079	((CHANNEL) == ADC_CHANNEL_6) \|\| \
		1080	((CHANNEL) == ADC_CHANNEL_7) \|\| \
		1081	((CHANNEL) == ADC_CHANNEL_8) \|\| \
		1082	((CHANNEL) == ADC_CHANNEL_9) \|\| \
		1083	((CHANNEL) == ADC_CHANNEL_10) \|\| \
		1084	((CHANNEL) == ADC_CHANNEL_11) \|\| \
		1085	((CHANNEL) == ADC_CHANNEL_12) \|\| \
		1086	((CHANNEL) == ADC_CHANNEL_13) \|\| \
		1087	((CHANNEL) == ADC_CHANNEL_14) \|\| \
		1088	((CHANNEL) == ADC_CHANNEL_15) \|\| \
		1089	((CHANNEL) == ADC_CHANNEL_16) \|\| \
		1090	((CHANNEL) == ADC_CHANNEL_17) \|\| \
		1091	((CHANNEL) == ADC_CHANNEL_18) \|\| \
		1092	((CHANNEL) == ADC_CHANNEL_19) \|\| \
		1093	((CHANNEL) == ADC_CHANNEL_20) \|\| \
		1094	((CHANNEL) == ADC_CHANNEL_21) \|\| \
		1095	((CHANNEL) == ADC_CHANNEL_22) \|\| \
		1096	((CHANNEL) == ADC_CHANNEL_23) \|\| \
		1097	((CHANNEL) == ADC_CHANNEL_24) \|\| \
		1098	((CHANNEL) == ADC_CHANNEL_25) \|\| \
		1099	((CHANNEL) == ADC_CHANNEL_26) )
		1100	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
		1101	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
		1102	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
		1103	((CHANNEL) == ADC_CHANNEL_1) \|\| \
		1104	((CHANNEL) == ADC_CHANNEL_2) \|\| \
		1105	((CHANNEL) == ADC_CHANNEL_3) \|\| \
		1106	((CHANNEL) == ADC_CHANNEL_4) \|\| \
		1107	((CHANNEL) == ADC_CHANNEL_5) \|\| \
		1108	((CHANNEL) == ADC_CHANNEL_6) \|\| \
		1109	((CHANNEL) == ADC_CHANNEL_7) \|\| \
		1110	((CHANNEL) == ADC_CHANNEL_8) \|\| \
		1111	((CHANNEL) == ADC_CHANNEL_9) \|\| \
		1112	((CHANNEL) == ADC_CHANNEL_10) \|\| \
		1113	((CHANNEL) == ADC_CHANNEL_11) \|\| \
		1114	((CHANNEL) == ADC_CHANNEL_12) \|\| \
		1115	((CHANNEL) == ADC_CHANNEL_13) \|\| \
		1116	((CHANNEL) == ADC_CHANNEL_14) \|\| \
		1117	((CHANNEL) == ADC_CHANNEL_15) \|\| \
		1118	((CHANNEL) == ADC_CHANNEL_16) \|\| \
		1119	((CHANNEL) == ADC_CHANNEL_17) \|\| \
		1120	((CHANNEL) == ADC_CHANNEL_18) \|\| \
		1121	((CHANNEL) == ADC_CHANNEL_19) \|\| \
		1122	((CHANNEL) == ADC_CHANNEL_20) \|\| \
		1123	((CHANNEL) == ADC_CHANNEL_21) \|\| \
		1124	((CHANNEL) == ADC_CHANNEL_22) \|\| \
		1125	((CHANNEL) == ADC_CHANNEL_23) \|\| \
		1126	((CHANNEL) == ADC_CHANNEL_24) \|\| \
		1127	((CHANNEL) == ADC_CHANNEL_25) \|\| \
		1128	((CHANNEL) == ADC_CHANNEL_26) \|\| \
		1129	((CHANNEL) == ADC_CHANNEL_27) \|\| \
		1130	((CHANNEL) == ADC_CHANNEL_28) \|\| \
		1131	((CHANNEL) == ADC_CHANNEL_29) \|\| \
		1132	((CHANNEL) == ADC_CHANNEL_30) \|\| \
		1133	((CHANNEL) == ADC_CHANNEL_31) )
		1134	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		1135
		1136	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) \|\| \
		1137	((TIME) == ADC_SAMPLETIME_9CYCLES) \|\| \
		1138	((TIME) == ADC_SAMPLETIME_16CYCLES) \|\| \
		1139	((TIME) == ADC_SAMPLETIME_24CYCLES) \|\| \
		1140	((TIME) == ADC_SAMPLETIME_48CYCLES) \|\| \
		1141	((TIME) == ADC_SAMPLETIME_96CYCLES) \|\| \
		1142	((TIME) == ADC_SAMPLETIME_192CYCLES) \|\| \
		1143	((TIME) == ADC_SAMPLETIME_384CYCLES) )
		1144
		1145	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
		1146
		1147	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
		1148	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
		1149	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
		1150	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
		1151	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
		1152	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
		1153	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
		1154	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
		1155	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
		1156	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
		1157	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
		1158	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
		1159	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
		1160	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
		1161	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
		1162	((CHANNEL) == ADC_REGULAR_RANK_16) \|\| \
		1163	((CHANNEL) == ADC_REGULAR_RANK_17) \|\| \
		1164	((CHANNEL) == ADC_REGULAR_RANK_18) \|\| \
		1165	((CHANNEL) == ADC_REGULAR_RANK_19) \|\| \
		1166	((CHANNEL) == ADC_REGULAR_RANK_20) \|\| \
		1167	((CHANNEL) == ADC_REGULAR_RANK_21) \|\| \
		1168	((CHANNEL) == ADC_REGULAR_RANK_22) \|\| \
		1169	((CHANNEL) == ADC_REGULAR_RANK_23) \|\| \
		1170	((CHANNEL) == ADC_REGULAR_RANK_24) \|\| \
		1171	((CHANNEL) == ADC_REGULAR_RANK_25) \|\| \
		1172	((CHANNEL) == ADC_REGULAR_RANK_26) \|\| \
		1173	((CHANNEL) == ADC_REGULAR_RANK_27) \|\| \
		1174	((CHANNEL) == ADC_REGULAR_RANK_28) )
		1175	#else
		1176
		1177	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
		1178	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
		1179	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
		1180	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
		1181	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
		1182	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
		1183	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
		1184	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
		1185	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
		1186	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
		1187	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
		1188	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
		1189	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
		1190	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
		1191	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
		1192	((CHANNEL) == ADC_REGULAR_RANK_16) \|\| \
		1193	((CHANNEL) == ADC_REGULAR_RANK_17) \|\| \
		1194	((CHANNEL) == ADC_REGULAR_RANK_18) \|\| \
		1195	((CHANNEL) == ADC_REGULAR_RANK_19) \|\| \
		1196	((CHANNEL) == ADC_REGULAR_RANK_20) \|\| \
		1197	((CHANNEL) == ADC_REGULAR_RANK_21) \|\| \
		1198	((CHANNEL) == ADC_REGULAR_RANK_22) \|\| \
		1199	((CHANNEL) == ADC_REGULAR_RANK_23) \|\| \
		1200	((CHANNEL) == ADC_REGULAR_RANK_24) \|\| \
		1201	((CHANNEL) == ADC_REGULAR_RANK_25) \|\| \
		1202	((CHANNEL) == ADC_REGULAR_RANK_26) \|\| \
		1203	((CHANNEL) == ADC_REGULAR_RANK_27) )
		1204	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
		1205
		1206	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
		1207	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
		1208	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
		1209	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
		1210	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
		1211	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
		1212	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
		1213
		1214	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) \|\| \
		1215	((CONVERSION) == ADC_INJECTED_GROUP) \|\| \
		1216	((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
		1217
		1218	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) \|\| \
		1219	((EVENT) == ADC_FLAG_OVR) )
		1220
		1221	/**
		1222	* @brief Verify that a ADC data is within range corresponding to
		1223	* ADC resolution.
		1224	* @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
		1225	* @param __ADC_DATA__: value checked against the resolution.
		1226	* @retval SET: ADC data is within range corresponding to ADC resolution
		1227	* RESET: ADC data is not within range corresponding to ADC resolution
		1228	*
		1229	*/
		1230	#define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \
28	mjames	1231	((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= (0x0FFFU))) \|\| \
		1232	(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= (0x03FFU))) \|\| \
		1233	(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= (0x00FFU))) \|\| \
		1234	(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= (0x003FU))) )
2	mjames	1235
		1236
		1237	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
28	mjames	1238	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (28U)))
2	mjames	1239	#else
28	mjames	1240	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (27U)))
2	mjames	1241	#endif
		1242
28	mjames	1243	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
2	mjames	1244
		1245	/**
		1246	* @}
		1247	*/
		1248
		1249
		1250	/* Include ADC HAL Extension module */
		1251	#include "stm32l1xx_hal_adc_ex.h"
		1252
		1253	/* Exported functions --------------------------------------------------------*/
		1254	/** @addtogroup ADC_Exported_Functions
		1255	* @{
		1256	*/
		1257
		1258	/** @addtogroup ADC_Exported_Functions_Group1
		1259	* @{
		1260	*/
		1261
		1262
		1263	/* Initialization and de-initialization functions **********************************/
		1264	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
		1265	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
		1266	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
		1267	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
28	mjames	1268
		1269	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		1270	/* Callbacks Register/UnRegister functions ***********************************/
		1271	HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
		1272	HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
		1273	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		1274
2	mjames	1275	/**
		1276	* @}
		1277	*/
		1278
		1279	/* IO operation functions *****************************************************/
		1280
		1281	/** @addtogroup ADC_Exported_Functions_Group2
		1282	* @{
		1283	*/
		1284
		1285
		1286	/* Blocking mode: Polling */
		1287	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
		1288	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
		1289	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
		1290	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
		1291
		1292	/* Non-blocking mode: Interruption */
		1293	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
		1294	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
		1295
		1296	/* Non-blocking mode: DMA */
		1297	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
		1298	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
		1299
		1300	/* ADC retrieve conversion value intended to be used with polling or interruption */
		1301	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
		1302
		1303	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
		1304	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
		1305	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
		1306	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
		1307	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
		1308	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
		1309	/**
		1310	* @}
		1311	*/
		1312
		1313
		1314	/* Peripheral Control functions ***********************************************/
		1315	/** @addtogroup ADC_Exported_Functions_Group3
		1316	* @{
		1317	*/
		1318	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
		1319	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
		1320	/**
		1321	* @}
		1322	*/
		1323
		1324
		1325	/* Peripheral State functions *************************************************/
		1326	/** @addtogroup ADC_Exported_Functions_Group4
		1327	* @{
		1328	*/
		1329	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
		1330	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
		1331	/**
		1332	* @}
		1333	*/
		1334
		1335
		1336	/**
		1337	* @}
		1338	*/
		1339
		1340
		1341	/* Internal HAL driver functions **********************************************/
		1342	/** @addtogroup ADC_Private_Functions
		1343	* @{
		1344	*/
		1345
		1346	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
		1347	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
		1348	/**
		1349	* @}
		1350	*/
		1351
		1352
		1353	/**
		1354	* @}
		1355	*/
		1356
		1357	/**
		1358	* @}
		1359	*/
		1360
		1361	#ifdef __cplusplus
		1362	}
		1363	#endif
		1364
		1365
		1366	#endif /* __STM32L1xx_HAL_ADC_H */
		1367
		1368	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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