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/*
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 * $Header: c:\\cygwin\\cvsroot/Vert03/vertlib/print_vhdl.h,v 1.1.1.1 2003/11/04 23:34:57 mjames Exp $
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 *
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 * $Log: print_vhdl.h,v $
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 * Revision 1.1.1.1  2003/11/04 23:34:57  mjames
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 * Imported into local repositrory
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 *
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 * Revision 1.5  2002/08/23 14:18:24  mjames
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 * Removed some constants to the header file
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 *
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 * Revision 1.4  2001/10/31 22:20:13  mjames
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 * Tidying up problematical comments caused by CVS
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 * 'intelligent' comment guessing
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 *
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 * Revision 1.3  2001/06/06 12:10:19  mjames
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 * Move from HPUX
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 *
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 * Revision 1.2  2000/11/29 23:25:39  mjames
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 * Corrected a failure to cope with integer type ports on entities
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 * in acf_yacc.y
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 *
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 * Altered the elaborate command to call up the template command aw well
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 *
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 * Altered equivalent pins handler to cope with the absence of any templates
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 *
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 * Altered printout routines to use correct datatype for expansion of
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 * VHDL constants
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 *
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 * Revision 1.1.1.1  2000/10/19 21:58:39  mjames
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 * Mike put it here
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 *
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 *
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 * Revision 1.13  2000/10/04  10:37:15  10:37:15  mjames (Mike James)
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 * Modified for Vertical2 : support COMPONENTS and SIGNALS
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 *
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 * Revision 1.13  2000/10/04  10:37:15  10:37:15  mjames (Mike James)
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 * Part of Release PSAVAT01
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 *
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 * Revision 1.12  2000/10/02  11:04:18  11:04:18  mjames (Mike James)
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 * new_vhdl
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 *
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 * Revision 1.11  2000/09/27  14:42:31  14:42:31  mjames (Mike James)
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 * Part of Release Sep_27_ST_2000
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 *
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 * Revision 1.10  2000/09/21  10:16:00  10:16:00  mjames (Mike James)
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 * Part of Release Sep21Alpha
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 *
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 * Revision 1.9  2000/08/25  09:57:24  09:57:24  mjames (Mike James)
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 * Part of Release Aug25_alpha
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 *
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 * Revision 1.8  2000/08/16  08:57:40  08:57:40  mjames (Mike James)
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 * Part of Release CD01_Aug2000
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 *
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 * Revision 1.7  2000/08/14  14:45:19  14:45:19  mjames (Mike James)
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 * Part of Release Aug_14_2000
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 *
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 * Revision 1.6  2000/08/11  08:30:40  08:30:40  mjames (Mike James)
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 * Part of Release Aug_11_2000
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 *
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 * Revision 1.5  2000/08/09  10:31:57  10:31:57  mjames (Mike James)
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 * Part of Release Aug__9_2000
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 *
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 * Revision 1.4  2000/05/31  11:43:11  11:43:11  mjames (Mike James)
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 * Part of Release May_31_2000
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 *
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 * Revision 1.3  2000/05/08  17:01:47  17:01:47  mjames (Mike James)
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 * Part of Release May__8_2000
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 *
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 * Revision 1.2  2000/05/08  16:59:40  16:59:40  mjames (Mike James)
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 * Part of Release May__8_2000
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 *
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 * Revision 1.1  99/11/23  13:52:31  13:52:31  mjames (Mike James)
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 * Initial revision
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 *
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 * Revision 1.1  1999/11/02 10:04:23  Mike_on_acorn
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 * Initial revision
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 */
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/* listing width */
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#define MAXWIDTH 60
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/* lessthan this pin count, connector pins are seen as wires not busses
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 in both VHDL and verilog bundles */
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#define MINBUNDLE 5
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extern char * make_vhdl_name(char * buffer,char * str);
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/* prints out the used subrange */
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extern void decode_vhdl_bus(FILE * f,vhdl_t * vhdl,generic_print_style recurse_generics);
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/* prints out the bus type and range if needed */
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extern void decode_vhdl_type(FILE * f,vhdl_t * vhdl,generic_print_style recurse_generics);
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extern void print_VHDL_component(FILE * f,socket_t * dev, int All);
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extern void print_VHDL_instance(FILE * f,socket_t * dev, int All);
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extern void produce_VHDL(FILE * f,char * entityname,char * template);