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Rev	Author	Line No.	Line
2	mjames	1	/*
		2	* $Id: print_ucf.c,v 1.1.1.1 2003/11/04 23:34:57 mjames Exp $
		3	*
		4	* $Log: print_ucf.c,v $
		5	* Revision 1.1.1.1 2003/11/04 23:34:57 mjames
		6	* Imported into local repositrory
		7	*
		8	* Revision 1.5 2003/01/02 21:37:16 mjames
		9	* Experiment on creating NOT_ROUTABLE_H and NOT_ROUTABLE_L
		10	* properties on the nets so that pin jumpers can be made without a problem.
		11	*
		12	* Still need to sort out pin assignments made to these not_routable nets
		13	* which will become legal in some cases so that pullups and pulldown
		14	* pins can be used on the FPGA.
		15	*
		16	* Revision 1.4 2002/10/02 18:38:26 MJAMES
		17	* Added semicolons to strings
		18	*
		19	* Revision 1.3 2002/09/16 11:03:31 mjames
		20	* Made the output compatible with Xilinx expectation, after testing with
		21	* Xilinx Alliance
		22	*
		23	* Revision 1.2 2002/09/09 10:12:02 mjames
		24	* Moved pin remapping function to pin ident editing function from
		25	* sorting pin name routine.
		26	*
		27	* Revision 1.1 2002/08/19 14:30:03 mjames
		28	* Added the 'write UCF' command for
		29	* listing pin assignments in Xilinx UCF file format
		30	*
		31	*
		32	*
		33	* This file contains routines for listing UCF files out for Xilinx Virtex
		34	* (and CoolRunner!)
		35	*
		36	* **********************************************************************
		37	* this file generates a list like this
		38
		39	#Pin location constraints for sheet X1, X2, X3 & X13
		40	NET "IOdata_out(1051)" LOC = "AW22";
		41	NET "IOdata_out(1052)" LOC = "AW24";
		42	NET "IOdata_out(1053)" LOC = "AW23";
		43	NET "IOdata_out(1054)" LOC = "AL21";
		44
		45
		46	*/
		47
		48	#include "print_ucf.h"
		49
		50	#include "cmdlog.h"
		51	#include "cmdparse.h"
		52	#include "database.h"
		53	#include "expression.h"
		54	#include "generic.h"
		55	#include "printout.h"
		56	#include "sorting.h"
		57	#include "vertcl_main.h"
		58
		59	#include <ctype.h>
		60	#include <regex.h>
		61	#include <stdio.h>
		62	#include <stdlib.h>
		63	#include <string.h>
		64	#include <time.h>
		65
		66	#define MAXWIDTH 60
		67
		68	#ident "$RCSId$"
		69
		70	/* ********************************************************************** */
		71	/* VHDL output of the entities */
		72	/* ********************************************************************** */
		73	static char illegal[] = "-+:\|/.\\$ ";
		74	static char replace[] = "NPCxxxxS_";
		75	char make_UCF_name (char buffer, char *str)
		76	{
		77	int i, l, j;
		78
		79	l = strlen (str);
		80	if (isdigit (str[0]))
		81	{
		82	l += 1;
		83	sprintf (buffer, "\%s", str); /* might as well use the verilog quotation method
		84	in this case */
		85	}
		86	else
		87	strcpy (buffer, str);
		88
		89	/* spot illegal strings in the net name */
		90	for (i = 0; i < l; i++)
		91	{
		92	for (j = 0; j < sizeof (illegal); j++)
		93	if (buffer[i] == illegal[j])
		94	buffer[i] = replace[j];
		95	}
		96
		97	i = l - 1;
		98	/* convert pin indices back from Altera form if we are looking at FIT files */
		99	if (l)
		100	{
		101	/* name ends in underscore, this forces mapping name_nn_ --> name(nn) */
		102	if (buffer[i] == '_')
		103	{
		104	buffer[i--] = ']';
		105	while (i >= 0 && buffer[i] != '_')
		106	i--;
		107	if (i >= 0)
		108	buffer[i] = '[';
		109	}
		110	}
		111	return buffer;
		112	}
		113
		114	/* ********************************************************************** */
		115	/* decodes the 'vector' part of a bus , if known */
		116	int decode_UCF_bus (FILE f, vhdl_t vhdl)
		117	{
		118	if (!vhdl)
		119	vhdl = default_vhdl_datatype;
		120
		121	if (vhdl->is_vector)
		122	{
		123	int bus_high, bus_low;
		124	bus_high = 0;
		125	bus_low = 0;
		126	eval_vhdl_expression (vhdl->expr, &bus_high, &bus_low);
		127	if (bus_high == bus_low)
		128	return fprintf (f, "[%d]", bus_high);
		129	else
		130	return fprintf (f, "[%d:%d]", bus_high, bus_low);
		131	}
		132	return 0;
		133	}
		134
		135	/* ********************************************************************** */
		136	/* Printout an instance of a component */
		137	/* ********************************************************************** */
		138	void print_UCF_instance (FILE f, socket_t dev, int All)
		139	{
		140	node_t *n;
		141	int pass;
		142	char nam[MAXIDLEN], id[MAXIDLEN];
		143	/* generic_info_t * g_list= dev->generics;*/
		144	make_UCF_name (nam, check_null_str (dev->type));
		145	make_UCF_name (id, check_null_str (dev->identifier));
		146
		147	fprintf (f, "\n\n# Component instance\n");
		148	fprintf (f, "# device name = %s\n# device identifier =%s\n\n", nam, id);
		149
		150	sort_nodes (dev, NO_EXTRACT_XY);
		151
		152	/* do this in 2 passes, the second lists unused pins together */
		153	for (pass = 0; pass < 1; pass++)
		154	{
		155	n = dev->nodes;
		156	while (n)
		157	{
		158	char nam1[MAXIDLEN], nam2[MAXIDLEN];
		159	/* is there need to add a buffer signal prefix */
		160	/* routable case is checked here */
		161	if (n->net && IS_ROUTABLE (n->net->how_routed))
		162	{
		163	if (n->net_assigned /&& n->in_use/ &&
		164	!ISNULLSTR (n->identifier))
		165	{
		166	if (pass == 0)
		167	{
		168	fprintf (
		169	f,
		170	" NET \"%s",
		171	make_UCF_name (
		172	nam2,
		173	check_null_str (n->net->name))); /* was
		174	identifier
		175	*/
		176	decode_UCF_bus (f, n->vhdltype);
		177	fprintf (
		178	f,
		179	"\" LOC = \"%s\"; # Named net used \n",
		180	make_UCF_name (
		181	nam1, check_null_str (n->identifier)));
		182	}
		183	}
		184	else
		185	{
		186	/* No assigned net : pin exists */
		187	if (pass == 1)
		188	{
		189	fprintf (
		190	f,
		191	"# NET \"%s",
		192	make_UCF_name (
		193	nam2,
		194	check_null_str (
		195	n->net->identifier))); /* was
		196	identifier
		197	*/
		198	decode_UCF_bus (f, n->vhdltype);
		199	fprintf (
		200	f,
		201	"\" LOC = \"%s\"; # Unnamed net used \n",
		202	make_UCF_name (
		203	nam1, check_null_str (n->identifier)));
		204	}
		205	}
		206	}
		207	n = n->sktnext; /* traverse to next pin on socket */
		208	};
		209	}
		210	fprintf (f, "\n\n");
		211	}

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