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11 mjames 1
/*
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 * $Id: print_ucf.c,v 1.1.1.1 2003/11/04 23:34:57 mjames Exp $
2 mjames 3
 *
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 * $Log: print_ucf.c,v $
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 * Revision 1.1.1.1  2003/11/04 23:34:57  mjames
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 * Imported into local repositrory
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 *
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 * Revision 1.5  2003/01/02 21:37:16  mjames
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 * Experiment on creating NOT_ROUTABLE_H and NOT_ROUTABLE_L
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 * properties on the nets so that pin jumpers can be made without a problem.
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 *
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 * Still need to sort out pin assignments made to these not_routable nets
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 * which will become legal in some cases so that pullups and pulldown
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 * pins can be used on the FPGA.
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 *
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 * Revision 1.4  2002/10/02 18:38:26  MJAMES
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 * Added semicolons to strings
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 *
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 * Revision 1.3  2002/09/16 11:03:31  mjames
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 * Made the output compatible with Xilinx expectation, after testing with
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 * Xilinx Alliance
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 *
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 * Revision 1.2  2002/09/09 10:12:02  mjames
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 * Moved pin remapping function to pin ident editing function from
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 * sorting pin name routine.
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 *
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 * Revision 1.1  2002/08/19 14:30:03  mjames
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 * Added the 'write UCF' command for
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 * listing pin assignments in Xilinx UCF file format
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 *
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 *
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 *
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 * This file contains routines for listing UCF files out for Xilinx Virtex
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 * (and CoolRunner!)
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 *
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 * **********************************************************************
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 * this file generates a list like this
2 mjames 38
 
11 mjames 39
#Pin location constraints for sheet X1, X2, X3 & X13                                                                           
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        NET "IOdata_out(1051)" LOC = "AW22";                                                                   
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        NET "IOdata_out(1052)" LOC = "AW24";                                                                   
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        NET "IOdata_out(1053)" LOC = "AW23";                                                                   
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        NET "IOdata_out(1054)" LOC = "AL21";                                                                   
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 */
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <ctype.h>
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#include <time.h>
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#include <regex.h>
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#include "vertcl_main.h" 
2 mjames 57
#include "expression.h"
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#include "generic.h"
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#include "database.h"
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#include "printout.h"
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#include "print_ucf.h"
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#include "sorting.h"
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#include "cmdparse.h"
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#include "cmdlog.h"
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#define MAXWIDTH 60
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#ident "$RCSId$"
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/* ********************************************************************** */
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/* VHDL output of the entities                                            */
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/* ********************************************************************** */
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static char illegal[]="-+:|/.\\$ ";
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static char replace[]="NPCxxxxS_";
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char * make_UCF_name(char * buffer,char * str)
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{
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  int i,l,j;
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  l=strlen(str);
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  if (isdigit(str[0]))
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    {
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    l += 1;
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    sprintf(buffer,"\%s",str);   /* might as well use the verilog quotation method in this case */
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    }
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  else
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    strcpy(buffer,str);
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/* spot illegal strings in the net name */
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  for(i=0;i<l;i++){
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    for(j=0;j<sizeof(illegal);j++)
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      if (buffer[i]==illegal[j])
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        buffer[i]=replace[j];
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    }
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  i=l-1;
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  /* convert pin indices back from Altera form if we are looking at FIT files */
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  if(l){
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    /* name ends in underscore, this forces mapping name_nn_ --> name(nn) */
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    if(buffer[i] =='_'){
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      buffer[i--]=']';
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      while(i>=0 && buffer[i] != '_')
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        i--;
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      if(i>=0)
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        buffer[i] = '[';
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      }
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  }
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  return buffer;
2 mjames 112
}
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/* ********************************************************************** */
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/* decodes the 'vector' part of a bus , if known                           */
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int decode_UCF_bus(FILE * f,vhdl_t * vhdl) {
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  if(!vhdl)
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     vhdl=default_vhdl_datatype;
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  if(vhdl->is_vector) {
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    int bus_high,bus_low;
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    bus_high=0;
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    bus_low =0;
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    eval_vhdl_expression(vhdl->expr,&bus_high,&bus_low);
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    if(bus_high==bus_low)
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      return fprintf(f,"[%d]",           bus_high);
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    else
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      return fprintf(f,"[%d:%d]", bus_high, bus_low);
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    }
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  return 0;
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  }
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/* ********************************************************************** */
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/* Printout an instance of a component */
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/* ********************************************************************** */
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void print_UCF_instance(FILE * f,socket_t * dev, int All)
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{
11 mjames 142
  node_t * n;
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  int pass;
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  char nam[MAXIDLEN],id[MAXIDLEN];
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/*  generic_info_t * g_list= dev->generics;*/
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  make_UCF_name(nam,check_null_str(dev->type));
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  make_UCF_name(id ,check_null_str(dev->identifier));
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  fprintf(f,"\n\n# Component instance\n");
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  fprintf(f,"# device name = %s\n# device identifier =%s\n\n",nam,id);
2 mjames 151
 
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  sort_nodes(dev,NO_EXTRACT_XY);
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11 mjames 155
/* do this in 2 passes, the second lists unused pins together */
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  for(pass=0;pass<1;pass++)
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    {
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    n=dev->nodes;
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    while(n)
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      {
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      char nam1[MAXIDLEN] , nam2[MAXIDLEN];
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        /* is there need to add a buffer signal prefix */
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  /* routable case is checked here */
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      if(n->net && IS_ROUTABLE(n->net->how_routed)  ){
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        if(n->net_assigned /*&& n->in_use*/ && !ISNULLSTR(n->identifier) )  {
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          if(pass==0)
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            {
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            fprintf(f,"  NET  \"%s",
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                   make_UCF_name(nam2,check_null_str(n->net->name))); /* was identifier */
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            decode_UCF_bus(f,n->vhdltype);
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            fprintf(f,"\" LOC = \"%s\";  # Named net used \n",make_UCF_name(nam1,check_null_str(n->identifier)));
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            }
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          }
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        else
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          {
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          /* No assigned net : pin exists  */
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          if(pass==1)
180
            {
181
            fprintf(f,"# NET  \"%s",
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                   make_UCF_name(nam2,check_null_str(n->net->identifier))); /* was identifier */
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            decode_UCF_bus(f,n->vhdltype);
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            fprintf(f,"\" LOC = \"%s\";  # Unnamed net used \n",make_UCF_name(nam1,check_null_str(n->identifier)));
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            }
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           }
2 mjames 187
        }
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      n=n->sktnext; /* traverse to next pin on socket */
189
      };
190
    }
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    fprintf(f,"\n\n");
2 mjames 192
}
11 mjames 193