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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | -- Altera EPLD / PCB / VHDL tools -- |
| 2 | -- (c) Philips Semiconductors Southampton 1996-2001 -- |
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| 3 | |||
| 4 | -- by: Mike James (Mike.D.James@philips.com) |
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| 5 | |||
| 6 | -- package version:12.02 Verilog compiled: May 21 2001-- |
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| 7 | |||
| 8 | -- Produced by 'VERTICAL 12.02 Verilog': WRITE ACF (PC-CygWin) |
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| 9 | -- at 16:13:32 on 21/05/2001 |
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| 10 | |||
| 11 | COMPONENTS |
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| 12 | BEGIN |
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| 13 | END; |
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| 14 | |||
| 15 | WIRED_NETS |
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| 16 | BEGIN |
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| 17 | -- Routed & Named nets follow -- |
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| 18 | |||
| 19 | NAMED |
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| 20 | |||
| 21 | -- Routed & unused nets follow -- |
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| 22 | |||
| 23 | ROUTED |
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| 24 | |||
| 25 | -- Unrouted nets follow -- |
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| 26 | |||
| 27 | UNROUTED |
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| 28 | |||
| 29 | --Top Level |
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| 30 | CONNECTION "A" "" FREE_NAME; -- 0 nodes |
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| 31 | -- partition port=0 in=0 need_buff=0 |
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| 32 | END_CONN; |
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| 33 | --Top Level |
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| 34 | CONNECTION "B" "" FREE_NAME; -- 0 nodes |
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| 35 | -- partition port=0 in=0 need_buff=0 |
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| 36 | END_CONN; |
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| 37 | --Top Level |
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| 38 | CONNECTION "SUM" "" FREE_NAME; -- 0 nodes |
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| 39 | -- partition port=0 in=0 need_buff=0 |
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| 40 | END_CONN; |
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| 41 | END; |
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| 42 | |||
| 43 | -- Jumper list here -- |
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| 44 | JOINED_NETS |
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| 45 | BEGIN |
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| 46 | END; |
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| 47 | |||
| 48 | GENERIC -- Generic constants |
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| 49 | VERTICAL_INIT : env_string := "./vertical.ini" |
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| 50 | END; |
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| 51 | |||
| 52 | -- Alias list here -- |
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| 53 | JOINED_NETS |
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| 54 | BEGIN |
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| 55 | END; |
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| 56 | |||
| 57 | -- pin renames on unrouted list follow -- |
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| 58 | -- pin renames on routed list follow -- |
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| 59 | -- pin renames on named list follow -- |