Subversion Repositories dashGPS

Rev

Rev 19 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
20 mjames 1 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 1
16 mjames 2 
 
3 
 
4 
   1              		.cpu cortex-m3
5 
   2              		.eabi_attribute 20, 1
6 
   3              		.eabi_attribute 21, 1
7 
   4              		.eabi_attribute 23, 3
8 
   5              		.eabi_attribute 24, 1
9 
   6              		.eabi_attribute 25, 1
10 
   7              		.eabi_attribute 26, 1
11 
   8              		.eabi_attribute 30, 1
12 
   9              		.eabi_attribute 34, 1
13 
  10              		.eabi_attribute 18, 4
14 
  11              		.file	"system_stm32f1xx.c"
15 
  12              		.text
16 
  13              	.Ltext0:
17 
  14              		.cfi_sections	.debug_frame
18 
  15              		.section	.text.SystemInit,"ax",%progbits
19 
  16              		.align	1
20 
  17              		.global	SystemInit
21 
  18              		.arch armv7-m
22 
  19              		.syntax unified
23 
  20              		.thumb
24 
  21              		.thumb_func
25 
  22              		.fpu softvfp
26 
  24              	SystemInit:
27 
  25              	.LFB65:
28 
  26              		.file 1 "Core/Src/system_stm32f1xx.c"
29 
   1:Core/Src/system_stm32f1xx.c **** /**
30 
   2:Core/Src/system_stm32f1xx.c ****   ******************************************************************************
31 
   3:Core/Src/system_stm32f1xx.c ****   * @file    system_stm32f1xx.c
32 
   4:Core/Src/system_stm32f1xx.c ****   * @author  MCD Application Team
33 
   5:Core/Src/system_stm32f1xx.c ****   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
34 
   6:Core/Src/system_stm32f1xx.c ****   *
35 
   7:Core/Src/system_stm32f1xx.c ****   * 1.  This file provides two functions and one global variable to be called from
36 
   8:Core/Src/system_stm32f1xx.c ****   *     user application:
37 
   9:Core/Src/system_stm32f1xx.c ****   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
38 
  10:Core/Src/system_stm32f1xx.c ****   *                      factors, AHB/APBx prescalers and Flash settings).
39 
  11:Core/Src/system_stm32f1xx.c ****   *                      This function is called at startup just after reset and
40 
  12:Core/Src/system_stm32f1xx.c ****   *                      before branch to main program. This call is made inside
41 
  13:Core/Src/system_stm32f1xx.c ****   *                      the "startup_stm32f1xx_xx.s" file.
42 
  14:Core/Src/system_stm32f1xx.c ****   *
43 
  15:Core/Src/system_stm32f1xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
44 
  16:Core/Src/system_stm32f1xx.c ****   *                                  by the user application to setup the SysTick
45 
  17:Core/Src/system_stm32f1xx.c ****   *                                  timer or configure other parameters.
46 
  18:Core/Src/system_stm32f1xx.c ****   *
47 
  19:Core/Src/system_stm32f1xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
48 
  20:Core/Src/system_stm32f1xx.c ****   *                                 be called whenever the core clock is changed
49 
  21:Core/Src/system_stm32f1xx.c ****   *                                 during program execution.
50 
  22:Core/Src/system_stm32f1xx.c ****   *
51 
  23:Core/Src/system_stm32f1xx.c ****   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
52 
  24:Core/Src/system_stm32f1xx.c ****   *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
53 
  25:Core/Src/system_stm32f1xx.c ****   *    configure the system clock before to branch to main program.
54 
  26:Core/Src/system_stm32f1xx.c ****   *
55 
  27:Core/Src/system_stm32f1xx.c ****   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
56 
  28:Core/Src/system_stm32f1xx.c ****   *    the product used), refer to "HSE_VALUE".
57 
  29:Core/Src/system_stm32f1xx.c ****   *    When HSE is used as system clock source, directly or through PLL, and you
58 
  30:Core/Src/system_stm32f1xx.c ****   *    are using different crystal you have to adapt the HSE value to your own
59 
  31:Core/Src/system_stm32f1xx.c ****   *    configuration.
60 
  32:Core/Src/system_stm32f1xx.c ****   *
20 mjames 61 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 2
16 mjames 62 
 
63 
 
64 
  33:Core/Src/system_stm32f1xx.c ****   ******************************************************************************
65 
  34:Core/Src/system_stm32f1xx.c ****   * @attention
66 
  35:Core/Src/system_stm32f1xx.c ****   *
67 
  36:Core/Src/system_stm32f1xx.c ****   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
68 
  37:Core/Src/system_stm32f1xx.c ****   * All rights reserved.</center></h2>
69 
  38:Core/Src/system_stm32f1xx.c ****   *
70 
  39:Core/Src/system_stm32f1xx.c ****   * This software component is licensed by ST under BSD 3-Clause license,
71 
  40:Core/Src/system_stm32f1xx.c ****   * the "License"; You may not use this file except in compliance with the
72 
  41:Core/Src/system_stm32f1xx.c ****   * License. You may obtain a copy of the License at:
73 
  42:Core/Src/system_stm32f1xx.c ****   *                        opensource.org/licenses/BSD-3-Clause
74 
  43:Core/Src/system_stm32f1xx.c ****   *
75 
  44:Core/Src/system_stm32f1xx.c ****   ******************************************************************************
76 
  45:Core/Src/system_stm32f1xx.c ****   */
77 
  46:Core/Src/system_stm32f1xx.c ****
78 
  47:Core/Src/system_stm32f1xx.c **** /** @addtogroup CMSIS
79 
  48:Core/Src/system_stm32f1xx.c ****   * @{
80 
  49:Core/Src/system_stm32f1xx.c ****   */
81 
  50:Core/Src/system_stm32f1xx.c ****
82 
  51:Core/Src/system_stm32f1xx.c **** /** @addtogroup stm32f1xx_system
83 
  52:Core/Src/system_stm32f1xx.c ****   * @{
84 
  53:Core/Src/system_stm32f1xx.c ****   */
85 
  54:Core/Src/system_stm32f1xx.c ****
86 
  55:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Includes
87 
  56:Core/Src/system_stm32f1xx.c ****   * @{
88 
  57:Core/Src/system_stm32f1xx.c ****   */
89 
  58:Core/Src/system_stm32f1xx.c ****
90 
  59:Core/Src/system_stm32f1xx.c **** #include "stm32f1xx.h"
91 
  60:Core/Src/system_stm32f1xx.c ****
92 
  61:Core/Src/system_stm32f1xx.c **** /**
93 
  62:Core/Src/system_stm32f1xx.c ****   * @}
94 
  63:Core/Src/system_stm32f1xx.c ****   */
95 
  64:Core/Src/system_stm32f1xx.c ****
96 
  65:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
97 
  66:Core/Src/system_stm32f1xx.c ****   * @{
98 
  67:Core/Src/system_stm32f1xx.c ****   */
99 
  68:Core/Src/system_stm32f1xx.c ****
100 
  69:Core/Src/system_stm32f1xx.c **** /**
101 
  70:Core/Src/system_stm32f1xx.c ****   * @}
102 
  71:Core/Src/system_stm32f1xx.c ****   */
103 
  72:Core/Src/system_stm32f1xx.c ****
104 
  73:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Defines
105 
  74:Core/Src/system_stm32f1xx.c ****   * @{
106 
  75:Core/Src/system_stm32f1xx.c ****   */
107 
  76:Core/Src/system_stm32f1xx.c ****
108 
  77:Core/Src/system_stm32f1xx.c **** #if !defined  (HSE_VALUE)
109 
  78:Core/Src/system_stm32f1xx.c ****   #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
110 
  79:Core/Src/system_stm32f1xx.c ****                                                 This value can be provided and adapted by the user
111 
  80:Core/Src/system_stm32f1xx.c **** #endif /* HSE_VALUE */
112 
  81:Core/Src/system_stm32f1xx.c ****
113 
  82:Core/Src/system_stm32f1xx.c **** #if !defined  (HSI_VALUE)
114 
  83:Core/Src/system_stm32f1xx.c ****   #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
115 
  84:Core/Src/system_stm32f1xx.c ****                                                 This value can be provided and adapted by the user
116 
  85:Core/Src/system_stm32f1xx.c **** #endif /* HSI_VALUE */
117 
  86:Core/Src/system_stm32f1xx.c ****
118 
  87:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to use external SRAM  */
119 
  88:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
120 
  89:Core/Src/system_stm32f1xx.c **** /* #define DATA_IN_ExtSRAM */
20 mjames 121 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 3
16 mjames 122 
 
123 
 
124 
  90:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
125 
  91:Core/Src/system_stm32f1xx.c ****
126 
  92:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in
127 
  93:Core/Src/system_stm32f1xx.c ****      Internal SRAM. */
128 
  94:Core/Src/system_stm32f1xx.c **** /* #define VECT_TAB_SRAM */
129 
  95:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field.
130 
  96:Core/Src/system_stm32f1xx.c ****                                   This value must be a multiple of 0x200. */
131 
  97:Core/Src/system_stm32f1xx.c ****
132 
  98:Core/Src/system_stm32f1xx.c ****
133 
  99:Core/Src/system_stm32f1xx.c **** /**
134 
 100:Core/Src/system_stm32f1xx.c ****   * @}
135 
 101:Core/Src/system_stm32f1xx.c ****   */
136 
 102:Core/Src/system_stm32f1xx.c ****
137 
 103:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Macros
138 
 104:Core/Src/system_stm32f1xx.c ****   * @{
139 
 105:Core/Src/system_stm32f1xx.c ****   */
140 
 106:Core/Src/system_stm32f1xx.c ****
141 
 107:Core/Src/system_stm32f1xx.c **** /**
142 
 108:Core/Src/system_stm32f1xx.c ****   * @}
143 
 109:Core/Src/system_stm32f1xx.c ****   */
144 
 110:Core/Src/system_stm32f1xx.c ****
145 
 111:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Variables
146 
 112:Core/Src/system_stm32f1xx.c ****   * @{
147 
 113:Core/Src/system_stm32f1xx.c ****   */
148 
 114:Core/Src/system_stm32f1xx.c ****
149 
 115:Core/Src/system_stm32f1xx.c ****   /* This variable is updated in three ways:
150 
 116:Core/Src/system_stm32f1xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
151 
 117:Core/Src/system_stm32f1xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
152 
 118:Core/Src/system_stm32f1xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
153 
 119:Core/Src/system_stm32f1xx.c ****          Note: If you use this function to configure the system clock; then there
154 
 120:Core/Src/system_stm32f1xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
155 
 121:Core/Src/system_stm32f1xx.c ****                variable is updated automatically.
156 
 122:Core/Src/system_stm32f1xx.c ****   */
157 
 123:Core/Src/system_stm32f1xx.c **** uint32_t SystemCoreClock = 16000000;
158 
 124:Core/Src/system_stm32f1xx.c **** const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
159 
 125:Core/Src/system_stm32f1xx.c **** const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
160 
 126:Core/Src/system_stm32f1xx.c ****
161 
 127:Core/Src/system_stm32f1xx.c **** /**
162 
 128:Core/Src/system_stm32f1xx.c ****   * @}
163 
 129:Core/Src/system_stm32f1xx.c ****   */
164 
 130:Core/Src/system_stm32f1xx.c ****
165 
 131:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
166 
 132:Core/Src/system_stm32f1xx.c ****   * @{
167 
 133:Core/Src/system_stm32f1xx.c ****   */
168 
 134:Core/Src/system_stm32f1xx.c ****
169 
 135:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
170 
 136:Core/Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM
171 
 137:Core/Src/system_stm32f1xx.c ****   static void SystemInit_ExtMemCtl(void);
172 
 138:Core/Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */
173 
 139:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
174 
 140:Core/Src/system_stm32f1xx.c ****
175 
 141:Core/Src/system_stm32f1xx.c **** /**
176 
 142:Core/Src/system_stm32f1xx.c ****   * @}
177 
 143:Core/Src/system_stm32f1xx.c ****   */
178 
 144:Core/Src/system_stm32f1xx.c ****
179 
 145:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Functions
180 
 146:Core/Src/system_stm32f1xx.c ****   * @{
20 mjames 181 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 4
16 mjames 182 
 
183 
 
184 
 147:Core/Src/system_stm32f1xx.c ****   */
185 
 148:Core/Src/system_stm32f1xx.c ****
186 
 149:Core/Src/system_stm32f1xx.c **** /**
187 
 150:Core/Src/system_stm32f1xx.c ****   * @brief  Setup the microcontroller system
188 
 151:Core/Src/system_stm32f1xx.c ****   *         Initialize the Embedded Flash Interface, the PLL and update the
189 
 152:Core/Src/system_stm32f1xx.c ****   *         SystemCoreClock variable.
190 
 153:Core/Src/system_stm32f1xx.c ****   * @note   This function should be used only after reset.
191 
 154:Core/Src/system_stm32f1xx.c ****   * @param  None
192 
 155:Core/Src/system_stm32f1xx.c ****   * @retval None
193 
 156:Core/Src/system_stm32f1xx.c ****   */
194 
 157:Core/Src/system_stm32f1xx.c **** void SystemInit (void)
195 
 158:Core/Src/system_stm32f1xx.c **** {
196 
  27              		.loc 1 158 1 view -0
197 
  28              		.cfi_startproc
198 
  29              		@ args = 0, pretend = 0, frame = 0
199 
  30              		@ frame_needed = 0, uses_anonymous_args = 0
200 
  31              		@ link register save eliminated.
201 
 159:Core/Src/system_stm32f1xx.c ****   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
202 
 160:Core/Src/system_stm32f1xx.c ****   /* Set HSION bit */
203 
 161:Core/Src/system_stm32f1xx.c ****   RCC->CR |= 0x00000001U;
204 
  32              		.loc 1 161 3 view .LVU1
205 
  33              		.loc 1 161 11 is_stmt 0 view .LVU2
206 
  34 0000 0F4B     		ldr	r3, .L2
207 
  35 0002 1A68     		ldr	r2, [r3]
208 
  36 0004 42F00102 		orr	r2, r2, #1
209 
  37 0008 1A60     		str	r2, [r3]
210 
 162:Core/Src/system_stm32f1xx.c ****
211 
 163:Core/Src/system_stm32f1xx.c ****   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
212 
 164:Core/Src/system_stm32f1xx.c **** #if !defined(STM32F105xC) && !defined(STM32F107xC)
213 
 165:Core/Src/system_stm32f1xx.c ****   RCC->CFGR &= 0xF8FF0000U;
214 
  38              		.loc 1 165 3 is_stmt 1 view .LVU3
215 
  39              		.loc 1 165 13 is_stmt 0 view .LVU4
216 
  40 000a 5968     		ldr	r1, [r3, #4]
217 
  41 000c 0D4A     		ldr	r2, .L2+4
218 
  42 000e 0A40     		ands	r2, r2, r1
219 
  43 0010 5A60     		str	r2, [r3, #4]
220 
 166:Core/Src/system_stm32f1xx.c **** #else
221 
 167:Core/Src/system_stm32f1xx.c ****   RCC->CFGR &= 0xF0FF0000U;
222 
 168:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
223 
 169:Core/Src/system_stm32f1xx.c ****
224 
 170:Core/Src/system_stm32f1xx.c ****   /* Reset HSEON, CSSON and PLLON bits */
225 
 171:Core/Src/system_stm32f1xx.c ****   RCC->CR &= 0xFEF6FFFFU;
226 
  44              		.loc 1 171 3 is_stmt 1 view .LVU5
227 
  45              		.loc 1 171 11 is_stmt 0 view .LVU6
228 
  46 0012 1A68     		ldr	r2, [r3]
229 
  47 0014 22F08472 		bic	r2, r2, #17301504
230 
  48 0018 22F48032 		bic	r2, r2, #65536
231 
  49 001c 1A60     		str	r2, [r3]
232 
 172:Core/Src/system_stm32f1xx.c ****
233 
 173:Core/Src/system_stm32f1xx.c ****   /* Reset HSEBYP bit */
234 
 174:Core/Src/system_stm32f1xx.c ****   RCC->CR &= 0xFFFBFFFFU;
235 
  50              		.loc 1 174 3 is_stmt 1 view .LVU7
236 
  51              		.loc 1 174 11 is_stmt 0 view .LVU8
237 
  52 001e 1A68     		ldr	r2, [r3]
238 
  53 0020 22F48022 		bic	r2, r2, #262144
239 
  54 0024 1A60     		str	r2, [r3]
240 
 175:Core/Src/system_stm32f1xx.c ****
20 mjames 241 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 5
16 mjames 242 
 
243 
 
244 
 176:Core/Src/system_stm32f1xx.c ****   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
245 
 177:Core/Src/system_stm32f1xx.c ****   RCC->CFGR &= 0xFF80FFFFU;
246 
  55              		.loc 1 177 3 is_stmt 1 view .LVU9
247 
  56              		.loc 1 177 13 is_stmt 0 view .LVU10
248 
  57 0026 5A68     		ldr	r2, [r3, #4]
249 
  58 0028 22F4FE02 		bic	r2, r2, #8323072
250 
  59 002c 5A60     		str	r2, [r3, #4]
251 
 178:Core/Src/system_stm32f1xx.c ****
252 
 179:Core/Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
253 
 180:Core/Src/system_stm32f1xx.c ****   /* Reset PLL2ON and PLL3ON bits */
254 
 181:Core/Src/system_stm32f1xx.c ****   RCC->CR &= 0xEBFFFFFFU;
255 
 182:Core/Src/system_stm32f1xx.c ****
256 
 183:Core/Src/system_stm32f1xx.c ****   /* Disable all interrupts and clear pending bits  */
257 
 184:Core/Src/system_stm32f1xx.c ****   RCC->CIR = 0x00FF0000U;
258 
 185:Core/Src/system_stm32f1xx.c ****
259 
 186:Core/Src/system_stm32f1xx.c ****   /* Reset CFGR2 register */
260 
 187:Core/Src/system_stm32f1xx.c ****   RCC->CFGR2 = 0x00000000U;
261 
 188:Core/Src/system_stm32f1xx.c **** #elif defined(STM32F100xB) || defined(STM32F100xE)
262 
 189:Core/Src/system_stm32f1xx.c ****   /* Disable all interrupts and clear pending bits  */
263 
 190:Core/Src/system_stm32f1xx.c ****   RCC->CIR = 0x009F0000U;
264 
 191:Core/Src/system_stm32f1xx.c ****
265 
 192:Core/Src/system_stm32f1xx.c ****   /* Reset CFGR2 register */
266 
 193:Core/Src/system_stm32f1xx.c ****   RCC->CFGR2 = 0x00000000U;
267 
 194:Core/Src/system_stm32f1xx.c **** #else
268 
 195:Core/Src/system_stm32f1xx.c ****   /* Disable all interrupts and clear pending bits  */
269 
 196:Core/Src/system_stm32f1xx.c ****   RCC->CIR = 0x009F0000U;
270 
  60              		.loc 1 196 3 is_stmt 1 view .LVU11
271 
  61              		.loc 1 196 12 is_stmt 0 view .LVU12
272 
  62 002e 4FF41F02 		mov	r2, #10420224
273 
  63 0032 9A60     		str	r2, [r3, #8]
274 
 197:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
275 
 198:Core/Src/system_stm32f1xx.c ****
276 
 199:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
277 
 200:Core/Src/system_stm32f1xx.c ****   #ifdef DATA_IN_ExtSRAM
278 
 201:Core/Src/system_stm32f1xx.c ****     SystemInit_ExtMemCtl();
279 
 202:Core/Src/system_stm32f1xx.c ****   #endif /* DATA_IN_ExtSRAM */
280 
 203:Core/Src/system_stm32f1xx.c **** #endif
281 
 204:Core/Src/system_stm32f1xx.c ****
282 
 205:Core/Src/system_stm32f1xx.c **** #ifdef VECT_TAB_SRAM
283 
 206:Core/Src/system_stm32f1xx.c ****   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
284 
 207:Core/Src/system_stm32f1xx.c **** #else
285 
 208:Core/Src/system_stm32f1xx.c ****   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
286 
  64              		.loc 1 208 3 is_stmt 1 view .LVU13
287 
  65              		.loc 1 208 13 is_stmt 0 view .LVU14
288 
  66 0034 044B     		ldr	r3, .L2+8
289 
  67 0036 4FF00062 		mov	r2, #134217728
290 
  68 003a 9A60     		str	r2, [r3, #8]
291 
 209:Core/Src/system_stm32f1xx.c **** #endif
292 
 210:Core/Src/system_stm32f1xx.c **** }
293 
  69              		.loc 1 210 1 view .LVU15
294 
  70 003c 7047     		bx	lr
295 
  71              	.L3:
296 
  72 003e 00BF     		.align	2
297 
  73              	.L2:
298 
  74 0040 00100240 		.word	1073876992
299 
  75 0044 0000FFF8 		.word	-117506048
300 
  76 0048 00ED00E0 		.word	-536810240
20 mjames 301 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 6
16 mjames 302 
 
303 
 
304 
  77              		.cfi_endproc
305 
  78              	.LFE65:
306 
  80              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
307 
  81              		.align	1
308 
  82              		.global	SystemCoreClockUpdate
309 
  83              		.syntax unified
310 
  84              		.thumb
311 
  85              		.thumb_func
312 
  86              		.fpu softvfp
313 
  88              	SystemCoreClockUpdate:
314 
  89              	.LFB66:
315 
 211:Core/Src/system_stm32f1xx.c ****
316 
 212:Core/Src/system_stm32f1xx.c **** /**
317 
 213:Core/Src/system_stm32f1xx.c ****   * @brief  Update SystemCoreClock variable according to Clock Register Values.
318 
 214:Core/Src/system_stm32f1xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
319 
 215:Core/Src/system_stm32f1xx.c ****   *         be used by the user application to setup the SysTick timer or configure
320 
 216:Core/Src/system_stm32f1xx.c ****   *         other parameters.
321 
 217:Core/Src/system_stm32f1xx.c ****   *
322 
 218:Core/Src/system_stm32f1xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
323 
 219:Core/Src/system_stm32f1xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
324 
 220:Core/Src/system_stm32f1xx.c ****   *         based on this variable will be incorrect.
325 
 221:Core/Src/system_stm32f1xx.c ****   *
326 
 222:Core/Src/system_stm32f1xx.c ****   * @note   - The system frequency computed by this function is not the real
327 
 223:Core/Src/system_stm32f1xx.c ****   *           frequency in the chip. It is calculated based on the predefined
328 
 224:Core/Src/system_stm32f1xx.c ****   *           constant and the selected clock source:
329 
 225:Core/Src/system_stm32f1xx.c ****   *
330 
 226:Core/Src/system_stm32f1xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
331 
 227:Core/Src/system_stm32f1xx.c ****   *
332 
 228:Core/Src/system_stm32f1xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
333 
 229:Core/Src/system_stm32f1xx.c ****   *
334 
 230:Core/Src/system_stm32f1xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
335 
 231:Core/Src/system_stm32f1xx.c ****   *             or HSI_VALUE(*) multiplied by the PLL factors.
336 
 232:Core/Src/system_stm32f1xx.c ****   *
337 
 233:Core/Src/system_stm32f1xx.c ****   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
338 
 234:Core/Src/system_stm32f1xx.c ****   *             8 MHz) but the real value may vary depending on the variations
339 
 235:Core/Src/system_stm32f1xx.c ****   *             in voltage and temperature.
340 
 236:Core/Src/system_stm32f1xx.c ****   *
341 
 237:Core/Src/system_stm32f1xx.c ****   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
342 
 238:Core/Src/system_stm32f1xx.c ****   *              8 MHz or 25 MHz, depending on the product used), user has to ensure
343 
 239:Core/Src/system_stm32f1xx.c ****   *              that HSE_VALUE is same as the real frequency of the crystal used.
344 
 240:Core/Src/system_stm32f1xx.c ****   *              Otherwise, this function may have wrong result.
345 
 241:Core/Src/system_stm32f1xx.c ****   *
346 
 242:Core/Src/system_stm32f1xx.c ****   *         - The result of this function could be not correct when using fractional
347 
 243:Core/Src/system_stm32f1xx.c ****   *           value for HSE crystal.
348 
 244:Core/Src/system_stm32f1xx.c ****   * @param  None
349 
 245:Core/Src/system_stm32f1xx.c ****   * @retval None
350 
 246:Core/Src/system_stm32f1xx.c ****   */
351 
 247:Core/Src/system_stm32f1xx.c **** void SystemCoreClockUpdate (void)
352 
 248:Core/Src/system_stm32f1xx.c **** {
353 
  90              		.loc 1 248 1 is_stmt 1 view -0
354 
  91              		.cfi_startproc
355 
  92              		@ args = 0, pretend = 0, frame = 0
356 
  93              		@ frame_needed = 0, uses_anonymous_args = 0
357 
  94              		@ link register save eliminated.
358 
 249:Core/Src/system_stm32f1xx.c ****   uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
359 
  95              		.loc 1 249 3 view .LVU17
360 
  96              	.LVL0:
20 mjames 361 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 7
16 mjames 362 
 
363 
 
364 
 250:Core/Src/system_stm32f1xx.c ****
365 
 251:Core/Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
366 
 252:Core/Src/system_stm32f1xx.c ****   uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
367 
 253:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
368 
 254:Core/Src/system_stm32f1xx.c ****
369 
 255:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE)
370 
 256:Core/Src/system_stm32f1xx.c ****   uint32_t prediv1factor = 0U;
371 
 257:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xB or STM32F100xE */
372 
 258:Core/Src/system_stm32f1xx.c ****
373 
 259:Core/Src/system_stm32f1xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
374 
 260:Core/Src/system_stm32f1xx.c ****   tmp = RCC->CFGR & RCC_CFGR_SWS;
375 
  97              		.loc 1 260 3 view .LVU18
376 
  98              		.loc 1 260 12 is_stmt 0 view .LVU19
377 
  99 0000 1F4B     		ldr	r3, .L12
378 
 100 0002 5B68     		ldr	r3, [r3, #4]
379 
 101              		.loc 1 260 7 view .LVU20
380 
 102 0004 03F00C03 		and	r3, r3, #12
381 
 103              	.LVL1:
382 
 261:Core/Src/system_stm32f1xx.c ****
383 
 262:Core/Src/system_stm32f1xx.c ****   switch (tmp)
384 
 104              		.loc 1 262 3 is_stmt 1 view .LVU21
385 
 105 0008 042B     		cmp	r3, #4
386 
 106 000a 14D0     		beq	.L5
387 
 107 000c 082B     		cmp	r3, #8
388 
 108 000e 16D0     		beq	.L6
389 
 109 0010 1BB1     		cbz	r3, .L11
390 
 263:Core/Src/system_stm32f1xx.c ****   {
391 
 264:Core/Src/system_stm32f1xx.c ****     case 0x00U:  /* HSI used as system clock */
392 
 265:Core/Src/system_stm32f1xx.c ****       SystemCoreClock = HSI_VALUE;
393 
 266:Core/Src/system_stm32f1xx.c ****       break;
394 
 267:Core/Src/system_stm32f1xx.c ****     case 0x04U:  /* HSE used as system clock */
395 
 268:Core/Src/system_stm32f1xx.c ****       SystemCoreClock = HSE_VALUE;
396 
 269:Core/Src/system_stm32f1xx.c ****       break;
397 
 270:Core/Src/system_stm32f1xx.c ****     case 0x08U:  /* PLL used as system clock */
398 
 271:Core/Src/system_stm32f1xx.c ****
399 
 272:Core/Src/system_stm32f1xx.c ****       /* Get PLL clock source and multiplication factor ----------------------*/
400 
 273:Core/Src/system_stm32f1xx.c ****       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
401 
 274:Core/Src/system_stm32f1xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
402 
 275:Core/Src/system_stm32f1xx.c ****
403 
 276:Core/Src/system_stm32f1xx.c **** #if !defined(STM32F105xC) && !defined(STM32F107xC)
404 
 277:Core/Src/system_stm32f1xx.c ****       pllmull = ( pllmull >> 18U) + 2U;
405 
 278:Core/Src/system_stm32f1xx.c ****
406 
 279:Core/Src/system_stm32f1xx.c ****       if (pllsource == 0x00U)
407 
 280:Core/Src/system_stm32f1xx.c ****       {
408 
 281:Core/Src/system_stm32f1xx.c ****         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
409 
 282:Core/Src/system_stm32f1xx.c ****         SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
410 
 283:Core/Src/system_stm32f1xx.c ****       }
411 
 284:Core/Src/system_stm32f1xx.c ****       else
412 
 285:Core/Src/system_stm32f1xx.c ****       {
413 
 286:Core/Src/system_stm32f1xx.c ****  #if defined(STM32F100xB) || defined(STM32F100xE)
414 
 287:Core/Src/system_stm32f1xx.c ****        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
415 
 288:Core/Src/system_stm32f1xx.c ****        /* HSE oscillator clock selected as PREDIV1 clock entry */
416 
 289:Core/Src/system_stm32f1xx.c ****        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
417 
 290:Core/Src/system_stm32f1xx.c ****  #else
418 
 291:Core/Src/system_stm32f1xx.c ****         /* HSE selected as PLL clock entry */
419 
 292:Core/Src/system_stm32f1xx.c ****         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
420 
 293:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
20 mjames 421 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 8
16 mjames 422 
 
423 
 
424 
 294:Core/Src/system_stm32f1xx.c ****           SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
425 
 295:Core/Src/system_stm32f1xx.c ****         }
426 
 296:Core/Src/system_stm32f1xx.c ****         else
427 
 297:Core/Src/system_stm32f1xx.c ****         {
428 
 298:Core/Src/system_stm32f1xx.c ****           SystemCoreClock = HSE_VALUE * pllmull;
429 
 299:Core/Src/system_stm32f1xx.c ****         }
430 
 300:Core/Src/system_stm32f1xx.c ****  #endif
431 
 301:Core/Src/system_stm32f1xx.c ****       }
432 
 302:Core/Src/system_stm32f1xx.c **** #else
433 
 303:Core/Src/system_stm32f1xx.c ****       pllmull = pllmull >> 18U;
434 
 304:Core/Src/system_stm32f1xx.c ****
435 
 305:Core/Src/system_stm32f1xx.c ****       if (pllmull != 0x0DU)
436 
 306:Core/Src/system_stm32f1xx.c ****       {
437 
 307:Core/Src/system_stm32f1xx.c ****          pllmull += 2U;
438 
 308:Core/Src/system_stm32f1xx.c ****       }
439 
 309:Core/Src/system_stm32f1xx.c ****       else
440 
 310:Core/Src/system_stm32f1xx.c ****       { /* PLL multiplication factor = PLL input clock * 6.5 */
441 
 311:Core/Src/system_stm32f1xx.c ****         pllmull = 13U / 2U;
442 
 312:Core/Src/system_stm32f1xx.c ****       }
443 
 313:Core/Src/system_stm32f1xx.c ****
444 
 314:Core/Src/system_stm32f1xx.c ****       if (pllsource == 0x00U)
445 
 315:Core/Src/system_stm32f1xx.c ****       {
446 
 316:Core/Src/system_stm32f1xx.c ****         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
447 
 317:Core/Src/system_stm32f1xx.c ****         SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
448 
 318:Core/Src/system_stm32f1xx.c ****       }
449 
 319:Core/Src/system_stm32f1xx.c ****       else
450 
 320:Core/Src/system_stm32f1xx.c ****       {/* PREDIV1 selected as PLL clock entry */
451 
 321:Core/Src/system_stm32f1xx.c ****
452 
 322:Core/Src/system_stm32f1xx.c ****         /* Get PREDIV1 clock source and division factor */
453 
 323:Core/Src/system_stm32f1xx.c ****         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
454 
 324:Core/Src/system_stm32f1xx.c ****         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
455 
 325:Core/Src/system_stm32f1xx.c ****
456 
 326:Core/Src/system_stm32f1xx.c ****         if (prediv1source == 0U)
457 
 327:Core/Src/system_stm32f1xx.c ****         {
458 
 328:Core/Src/system_stm32f1xx.c ****           /* HSE oscillator clock selected as PREDIV1 clock entry */
459 
 329:Core/Src/system_stm32f1xx.c ****           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
460 
 330:Core/Src/system_stm32f1xx.c ****         }
461 
 331:Core/Src/system_stm32f1xx.c ****         else
462 
 332:Core/Src/system_stm32f1xx.c ****         {/* PLL2 clock selected as PREDIV1 clock entry */
463 
 333:Core/Src/system_stm32f1xx.c ****
464 
 334:Core/Src/system_stm32f1xx.c ****           /* Get PREDIV2 division factor and PLL2 multiplication factor */
465 
 335:Core/Src/system_stm32f1xx.c ****           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
466 
 336:Core/Src/system_stm32f1xx.c ****           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
467 
 337:Core/Src/system_stm32f1xx.c ****           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
468 
 338:Core/Src/system_stm32f1xx.c ****         }
469 
 339:Core/Src/system_stm32f1xx.c ****       }
470 
 340:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
471 
 341:Core/Src/system_stm32f1xx.c ****       break;
472 
 342:Core/Src/system_stm32f1xx.c ****
473 
 343:Core/Src/system_stm32f1xx.c ****     default:
474 
 344:Core/Src/system_stm32f1xx.c ****       SystemCoreClock = HSI_VALUE;
475 
 110              		.loc 1 344 7 view .LVU22
476 
 111              		.loc 1 344 23 is_stmt 0 view .LVU23
477 
 112 0012 1C4B     		ldr	r3, .L12+4
478 
 113              	.LVL2:
479 
 114              		.loc 1 344 23 view .LVU24
480 
 115 0014 1C4A     		ldr	r2, .L12+8
20 mjames 481 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 9
16 mjames 482 
 
483 
 
484 
 116 0016 1A60     		str	r2, [r3]
485 
 345:Core/Src/system_stm32f1xx.c ****       break;
486 
 117              		.loc 1 345 7 is_stmt 1 view .LVU25
487 
 118 0018 02E0     		b	.L8
488 
 119              	.LVL3:
489 
 120              	.L11:
490 
 265:Core/Src/system_stm32f1xx.c ****       break;
491 
 121              		.loc 1 265 7 view .LVU26
492 
 265:Core/Src/system_stm32f1xx.c ****       break;
493 
 122              		.loc 1 265 23 is_stmt 0 view .LVU27
494 
 123 001a 1A4B     		ldr	r3, .L12+4
495 
 124              	.LVL4:
496 
 265:Core/Src/system_stm32f1xx.c ****       break;
497 
 125              		.loc 1 265 23 view .LVU28
498 
 126 001c 1A4A     		ldr	r2, .L12+8
499 
 127 001e 1A60     		str	r2, [r3]
500 
 266:Core/Src/system_stm32f1xx.c ****     case 0x04U:  /* HSE used as system clock */
501 
 128              		.loc 1 266 7 is_stmt 1 view .LVU29
502 
 129              	.LVL5:
503 
 130              	.L8:
504 
 346:Core/Src/system_stm32f1xx.c ****   }
505 
 347:Core/Src/system_stm32f1xx.c ****
506 
 348:Core/Src/system_stm32f1xx.c ****   /* Compute HCLK clock frequency ----------------*/
507 
 349:Core/Src/system_stm32f1xx.c ****   /* Get HCLK prescaler */
508 
 350:Core/Src/system_stm32f1xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
509 
 131              		.loc 1 350 3 view .LVU30
510 
 132              		.loc 1 350 28 is_stmt 0 view .LVU31
511 
 133 0020 174B     		ldr	r3, .L12
512 
 134 0022 5B68     		ldr	r3, [r3, #4]
513 
 135              		.loc 1 350 52 view .LVU32
514 
 136 0024 C3F30313 		ubfx	r3, r3, #4, #4
515 
 137              		.loc 1 350 22 view .LVU33
516 
 138 0028 184A     		ldr	r2, .L12+12
517 
 139 002a D15C     		ldrb	r1, [r2, r3]	@ zero_extendqisi2
518 
 140              	.LVL6:
519 
 351:Core/Src/system_stm32f1xx.c ****   /* HCLK clock frequency */
520 
 352:Core/Src/system_stm32f1xx.c ****   SystemCoreClock >>= tmp;
521 
 141              		.loc 1 352 3 is_stmt 1 view .LVU34
522 
 142              		.loc 1 352 19 is_stmt 0 view .LVU35
523 
 143 002c 154A     		ldr	r2, .L12+4
524 
 144 002e 1368     		ldr	r3, [r2]
525 
 145 0030 CB40     		lsrs	r3, r3, r1
526 
 146 0032 1360     		str	r3, [r2]
527 
 353:Core/Src/system_stm32f1xx.c **** }
528 
 147              		.loc 1 353 1 view .LVU36
529 
 148 0034 7047     		bx	lr
530 
 149              	.LVL7:
531 
 150              	.L5:
532 
 268:Core/Src/system_stm32f1xx.c ****       break;
533 
 151              		.loc 1 268 7 is_stmt 1 view .LVU37
534 
 268:Core/Src/system_stm32f1xx.c ****       break;
535 
 152              		.loc 1 268 23 is_stmt 0 view .LVU38
536 
 153 0036 134B     		ldr	r3, .L12+4
537 
 154              	.LVL8:
538 
 268:Core/Src/system_stm32f1xx.c ****       break;
539 
 155              		.loc 1 268 23 view .LVU39
540 
 156 0038 134A     		ldr	r2, .L12+8
20 mjames 541 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 10
16 mjames 542 
 
543 
 
544 
 157 003a 1A60     		str	r2, [r3]
545 
 269:Core/Src/system_stm32f1xx.c ****     case 0x08U:  /* PLL used as system clock */
546 
 158              		.loc 1 269 7 is_stmt 1 view .LVU40
547 
 159 003c F0E7     		b	.L8
548 
 160              	.LVL9:
549 
 161              	.L6:
550 
 273:Core/Src/system_stm32f1xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
551 
 162              		.loc 1 273 7 view .LVU41
552 
 273:Core/Src/system_stm32f1xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
553 
 163              		.loc 1 273 20 is_stmt 0 view .LVU42
554 
 164 003e 104A     		ldr	r2, .L12
555 
 165 0040 5368     		ldr	r3, [r2, #4]
556 
 166              	.LVL10:
557 
 274:Core/Src/system_stm32f1xx.c ****
558 
 167              		.loc 1 274 7 is_stmt 1 view .LVU43
559 
 274:Core/Src/system_stm32f1xx.c ****
560 
 168              		.loc 1 274 22 is_stmt 0 view .LVU44
561 
 169 0042 5268     		ldr	r2, [r2, #4]
562 
 170              	.LVL11:
563 
 277:Core/Src/system_stm32f1xx.c ****
564 
 171              		.loc 1 277 7 is_stmt 1 view .LVU45
565 
 277:Core/Src/system_stm32f1xx.c ****
566 
 172              		.loc 1 277 27 is_stmt 0 view .LVU46
567 
 173 0044 C3F38343 		ubfx	r3, r3, #18, #4
568 
 174              	.LVL12:
569 
 277:Core/Src/system_stm32f1xx.c ****
570 
 175              		.loc 1 277 15 view .LVU47
571 
 176 0048 0233     		adds	r3, r3, #2
572 
 177              	.LVL13:
573 
 279:Core/Src/system_stm32f1xx.c ****       {
574 
 178              		.loc 1 279 7 is_stmt 1 view .LVU48
575 
 279:Core/Src/system_stm32f1xx.c ****       {
576 
 179              		.loc 1 279 10 is_stmt 0 view .LVU49
577 
 180 004a 12F4803F 		tst	r2, #65536
578 
 181 004e 05D1     		bne	.L9
579 
 282:Core/Src/system_stm32f1xx.c ****       }
580 
 182              		.loc 1 282 9 is_stmt 1 view .LVU50
581 
 282:Core/Src/system_stm32f1xx.c ****       }
582 
 183              		.loc 1 282 45 is_stmt 0 view .LVU51
583 
 184 0050 0F4A     		ldr	r2, .L12+16
584 
 185              	.LVL14:
585 
 282:Core/Src/system_stm32f1xx.c ****       }
586 
 186              		.loc 1 282 45 view .LVU52
587 
 187 0052 02FB03F3 		mul	r3, r2, r3
588 
 188              	.LVL15:
589 
 282:Core/Src/system_stm32f1xx.c ****       }
590 
 189              		.loc 1 282 25 view .LVU53
591 
 190 0056 0B4A     		ldr	r2, .L12+4
592 
 191 0058 1360     		str	r3, [r2]
593 
 192 005a E1E7     		b	.L8
594 
 193              	.LVL16:
595 
 194              	.L9:
596 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
597 
 195              		.loc 1 292 9 is_stmt 1 view .LVU54
598 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
599 
 196              		.loc 1 292 17 is_stmt 0 view .LVU55
600 
 197 005c 084A     		ldr	r2, .L12
20 mjames 601 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 11
16 mjames 602 
 
603 
 
604 
 198              	.LVL17:
605 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
606 
 199              		.loc 1 292 17 view .LVU56
607 
 200 005e 5268     		ldr	r2, [r2, #4]
608 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
609 
 201              		.loc 1 292 12 view .LVU57
610 
 202 0060 12F4003F 		tst	r2, #131072
611 
 203 0064 05D0     		beq	.L10
612 
 294:Core/Src/system_stm32f1xx.c ****         }
613 
 204              		.loc 1 294 11 is_stmt 1 view .LVU58
614 
 294:Core/Src/system_stm32f1xx.c ****         }
615 
 205              		.loc 1 294 47 is_stmt 0 view .LVU59
616 
 206 0066 0A4A     		ldr	r2, .L12+16
617 
 207 0068 02FB03F3 		mul	r3, r2, r3
618 
 208              	.LVL18:
619 
 294:Core/Src/system_stm32f1xx.c ****         }
620 
 209              		.loc 1 294 27 view .LVU60
621 
 210 006c 054A     		ldr	r2, .L12+4
622 
 211 006e 1360     		str	r3, [r2]
623 
 212 0070 D6E7     		b	.L8
624 
 213              	.LVL19:
625 
 214              	.L10:
626 
 298:Core/Src/system_stm32f1xx.c ****         }
627 
 215              		.loc 1 298 11 is_stmt 1 view .LVU61
628 
 298:Core/Src/system_stm32f1xx.c ****         }
629 
 216              		.loc 1 298 39 is_stmt 0 view .LVU62
630 
 217 0072 054A     		ldr	r2, .L12+8
631 
 218 0074 02FB03F3 		mul	r3, r2, r3
632 
 219              	.LVL20:
633 
 298:Core/Src/system_stm32f1xx.c ****         }
634 
 220              		.loc 1 298 27 view .LVU63
635 
 221 0078 024A     		ldr	r2, .L12+4
636 
 222 007a 1360     		str	r3, [r2]
637 
 223 007c D0E7     		b	.L8
638 
 224              	.L13:
639 
 225 007e 00BF     		.align	2
640 
 226              	.L12:
641 
 227 0080 00100240 		.word	1073876992
642 
 228 0084 00000000 		.word	.LANCHOR0
643 
 229 0088 00127A00 		.word	8000000
644 
 230 008c 00000000 		.word	.LANCHOR1
645 
 231 0090 00093D00 		.word	4000000
646 
 232              		.cfi_endproc
647 
 233              	.LFE66:
648 
 235              		.global	APBPrescTable
649 
 236              		.global	AHBPrescTable
650 
 237              		.global	SystemCoreClock
651 
 238              		.section	.data.SystemCoreClock,"aw"
652 
 239              		.align	2
653 
 240              		.set	.LANCHOR0,. + 0
654 
 243              	SystemCoreClock:
655 
 244 0000 0024F400 		.word	16000000
656 
 245              		.section	.rodata.AHBPrescTable,"a"
657 
 246              		.align	2
658 
 247              		.set	.LANCHOR1,. + 0
659 
 250              	AHBPrescTable:
660 
 251 0000 00       		.byte	0
20 mjames 661 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 12
16 mjames 662 
 
663 
 
664 
 252 0001 00       		.byte	0
665 
 253 0002 00       		.byte	0
666 
 254 0003 00       		.byte	0
667 
 255 0004 00       		.byte	0
668 
 256 0005 00       		.byte	0
669 
 257 0006 00       		.byte	0
670 
 258 0007 00       		.byte	0
671 
 259 0008 01       		.byte	1
672 
 260 0009 02       		.byte	2
673 
 261 000a 03       		.byte	3
674 
 262 000b 04       		.byte	4
675 
 263 000c 06       		.byte	6
676 
 264 000d 07       		.byte	7
677 
 265 000e 08       		.byte	8
678 
 266 000f 09       		.byte	9
679 
 267              		.section	.rodata.APBPrescTable,"a"
680 
 268              		.align	2
681 
 271              	APBPrescTable:
682 
 272 0000 00       		.byte	0
683 
 273 0001 00       		.byte	0
684 
 274 0002 00       		.byte	0
685 
 275 0003 00       		.byte	0
686 
 276 0004 01       		.byte	1
687 
 277 0005 02       		.byte	2
688 
 278 0006 03       		.byte	3
689 
 279 0007 04       		.byte	4
690 
 280              		.text
691 
 281              	.Letext0:
692 
 282              		.file 2 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7
693 
 283              		.file 3 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7
694 
 284              		.file 4 "Drivers/CMSIS/Include/core_cm3.h"
695 
 285              		.file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
696 
 286              		.file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
697 
 287              		.file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
698 
 288              		.file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
20 mjames 699 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 13
16 mjames 700 
 
701 
 
702 
DEFINED SYMBOLS
703 
                            *ABS*:0000000000000000 system_stm32f1xx.c
20 mjames 704 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:16     .text.SystemInit:0000000000000000 $t
705 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:24     .text.SystemInit:0000000000000000 SystemInit
706 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:74     .text.SystemInit:0000000000000040 $d
707 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:81     .text.SystemCoreClockUpdate:0000000000000000 $t
708 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:88     .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
709 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:227    .text.SystemCoreClockUpdate:0000000000000080 $d
710 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:271    .rodata.APBPrescTable:0000000000000000 APBPrescTable
711 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:250    .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
712 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:243    .data.SystemCoreClock:0000000000000000 SystemCoreClock
713 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:239    .data.SystemCoreClock:0000000000000000 $d
714 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:246    .rodata.AHBPrescTable:0000000000000000 $d
715 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:268    .rodata.APBPrescTable:0000000000000000 $d
16 mjames 716 
 
717 
NO UNDEFINED SYMBOLS