Rev 18 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 19 | mjames | 1 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 1 |
| 16 | mjames | 2 | |
| 3 | |||
| 4 | 1 .cpu cortex-m3 |
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| 5 | 2 .eabi_attribute 20, 1 |
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| 6 | 3 .eabi_attribute 21, 1 |
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| 7 | 4 .eabi_attribute 23, 3 |
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| 8 | 5 .eabi_attribute 24, 1 |
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| 9 | 6 .eabi_attribute 25, 1 |
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| 10 | 7 .eabi_attribute 26, 1 |
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| 11 | 8 .eabi_attribute 30, 1 |
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| 12 | 9 .eabi_attribute 34, 1 |
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| 13 | 10 .eabi_attribute 18, 4 |
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| 14 | 11 .file "stm32f1xx_hal_pwr.c" |
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| 15 | 12 .text |
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| 16 | 13 .Ltext0: |
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| 17 | 14 .cfi_sections .debug_frame |
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| 18 | 15 .section .text.PWR_OverloadWfe,"ax",%progbits |
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| 19 | 16 .align 1 |
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| 20 | 17 .arch armv7-m |
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| 21 | 18 .syntax unified |
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| 22 | 19 .thumb |
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| 23 | 20 .thumb_func |
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| 24 | 21 .fpu softvfp |
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| 25 | 23 PWR_OverloadWfe: |
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| 26 | 24 .LFB65: |
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| 27 | 25 .file 1 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" |
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| 28 | 1:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
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| 29 | 2:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ****************************************************************************** |
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| 30 | 3:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @file stm32f1xx_hal_pwr.c |
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| 31 | 4:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @author MCD Application Team |
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| 32 | 5:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief PWR HAL module driver. |
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| 33 | 6:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * |
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| 34 | 7:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This file provides firmware functions to manage the following |
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| 35 | 8:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: |
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| 36 | 9:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * + Initialization/de-initialization functions |
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| 37 | 10:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * + Peripheral Control functions |
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| 38 | 11:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * |
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| 39 | 12:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ****************************************************************************** |
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| 40 | 13:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @attention |
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| 41 | 14:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * |
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| 42 | 15:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 43 | 16:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * All rights reserved.</center></h2> |
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| 44 | 17:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * |
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| 45 | 18:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license, |
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| 46 | 19:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * the "License"; You may not use this file except in compliance with the |
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| 47 | 20:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * License. You may obtain a copy of the License at: |
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| 48 | 21:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * opensource.org/licenses/BSD-3-Clause |
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| 49 | 22:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * |
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| 50 | 23:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ****************************************************************************** |
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| 51 | 24:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 52 | 25:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 53 | 26:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ |
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| 54 | 27:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #include "stm32f1xx_hal.h" |
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| 55 | 28:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 56 | 29:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @addtogroup STM32F1xx_HAL_Driver |
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| 57 | 30:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
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| 58 | 31:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 59 | 32:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 60 | 33:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR PWR |
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| 19 | mjames | 61 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 2 |
| 16 | mjames | 62 | |
| 63 | |||
| 64 | 34:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief PWR HAL module driver |
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| 65 | 35:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
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| 66 | 36:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 67 | 37:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 68 | 38:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED |
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| 69 | 39:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 70 | 40:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ |
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| 71 | 41:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ |
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| 72 | 42:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 73 | 43:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Private_Constants PWR Private Constants |
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| 74 | 44:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
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| 75 | 45:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 76 | 46:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 77 | 47:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask |
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| 78 | 48:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
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| 79 | 49:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 80 | 50:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVD_MODE_IT 0x00010000U |
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| 81 | 51:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVD_MODE_EVT 0x00020000U |
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| 82 | 52:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVD_RISING_EDGE 0x00000001U |
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| 83 | 53:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVD_FALLING_EDGE 0x00000002U |
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| 84 | 54:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
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| 85 | 55:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @} |
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| 86 | 56:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 87 | 57:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 88 | 58:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 89 | 59:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_register_alias_address PWR Register alias address |
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| 90 | 60:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
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| 91 | 61:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 92 | 62:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* ------------- PWR registers bit address in the alias region ---------------*/ |
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| 93 | 63:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
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| 94 | 64:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_CR_OFFSET 0x00U |
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| 95 | 65:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_CSR_OFFSET 0x04U |
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| 96 | 66:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) |
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| 97 | 67:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) |
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| 98 | 68:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
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| 99 | 69:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @} |
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| 100 | 70:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 101 | 71:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 102 | 72:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_CR_register_alias PWR CR Register alias address |
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| 103 | 73:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
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| 104 | 74:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 105 | 75:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* --- CR Register ---*/ |
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| 106 | 76:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Alias word address of LPSDSR bit */ |
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| 107 | 77:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos |
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| 108 | 78:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BI |
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| 109 | 79:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 110 | 80:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Alias word address of DBP bit */ |
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| 111 | 81:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define DBP_BIT_NUMBER PWR_CR_DBP_Pos |
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| 112 | 82:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_N |
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| 113 | 83:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 114 | 84:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Alias word address of PVDE bit */ |
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| 115 | 85:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos |
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| 116 | 86:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_ |
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| 117 | 87:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 118 | 88:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
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| 119 | 89:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @} |
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| 120 | 90:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 19 | mjames | 121 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 3 |
| 16 | mjames | 122 | |
| 123 | |||
| 124 | 91:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 125 | 92:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address |
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| 126 | 93:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
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| 127 | 94:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 128 | 95:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 129 | 96:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* --- CSR Register ---*/ |
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| 130 | 97:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Alias word address of EWUP1 bit */ |
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| 131 | 98:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION |
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| 132 | 99:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
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| 133 | 100:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @} |
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| 134 | 101:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 135 | 102:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 136 | 103:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
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| 137 | 104:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @} |
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| 138 | 105:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 139 | 106:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 140 | 107:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ |
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| 141 | 108:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ |
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| 142 | 109:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Private_Functions PWR Private Functions |
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| 143 | 110:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround secti |
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| 144 | 111:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
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| 145 | 112:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 146 | 113:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** static void PWR_OverloadWfe(void); |
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| 147 | 114:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 148 | 115:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/ |
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| 149 | 116:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __NOINLINE |
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| 150 | 117:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** static void PWR_OverloadWfe(void) |
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| 151 | 118:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
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| 152 | 26 .loc 1 118 1 view -0 |
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| 153 | 27 .cfi_startproc |
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| 154 | 28 @ args = 0, pretend = 0, frame = 0 |
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| 155 | 29 @ frame_needed = 0, uses_anonymous_args = 0 |
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| 156 | 30 @ link register save eliminated. |
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| 157 | 119:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __asm volatile( "wfe" ); |
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| 158 | 31 .loc 1 119 3 view .LVU1 |
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| 159 | 32 .syntax unified |
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| 160 | 33 @ 119 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1 |
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| 161 | 34 0000 20BF wfe |
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| 162 | 35 @ 0 "" 2 |
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| 163 | 120:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __asm volatile( "nop" ); |
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| 164 | 36 .loc 1 120 3 view .LVU2 |
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| 165 | 37 @ 120 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1 |
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| 166 | 38 0002 00BF nop |
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| 167 | 39 @ 0 "" 2 |
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| 168 | 121:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
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| 169 | 40 .loc 1 121 1 is_stmt 0 view .LVU3 |
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| 170 | 41 .thumb |
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| 171 | 42 .syntax unified |
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| 172 | 43 0004 7047 bx lr |
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| 173 | 44 .cfi_endproc |
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| 174 | 45 .LFE65: |
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| 175 | 47 .section .text.HAL_PWR_DeInit,"ax",%progbits |
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| 176 | 48 .align 1 |
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| 177 | 49 .global HAL_PWR_DeInit |
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| 178 | 50 .syntax unified |
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| 179 | 51 .thumb |
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| 180 | 52 .thumb_func |
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| 19 | mjames | 181 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 4 |
| 16 | mjames | 182 | |
| 183 | |||
| 184 | 53 .fpu softvfp |
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| 185 | 55 HAL_PWR_DeInit: |
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| 186 | 56 .LFB66: |
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| 187 | 122:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 188 | 123:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
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| 189 | 124:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @} |
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| 190 | 125:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 191 | 126:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 192 | 127:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 193 | 128:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions |
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| 194 | 129:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
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| 195 | 130:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
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| 196 | 131:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 197 | 132:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 198 | 133:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Initialization and de-initialization functions |
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| 199 | 134:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * |
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| 200 | 135:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** @verbatim |
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| 201 | 136:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** =============================================================================== |
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| 202 | 137:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### |
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| 203 | 138:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** =============================================================================== |
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| 204 | 139:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
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| 205 | 140:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data |
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| 206 | 141:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** registers) is protected against possible unwanted |
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| 207 | 142:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** write accesses. |
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| 208 | 143:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows: |
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| 209 | 144:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the |
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| 210 | 145:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro. |
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| 211 | 146:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
||
| 212 | 147:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 213 | 148:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** @endverbatim |
||
| 214 | 149:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
||
| 215 | 150:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 216 | 151:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 217 | 152:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 218 | 153:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values. |
||
| 219 | 154:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 220 | 155:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 221 | 156:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DeInit(void) |
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| 222 | 157:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 223 | 57 .loc 1 157 1 is_stmt 1 view -0 |
||
| 224 | 58 .cfi_startproc |
||
| 225 | 59 @ args = 0, pretend = 0, frame = 0 |
||
| 226 | 60 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 227 | 61 @ link register save eliminated. |
||
| 228 | 158:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); |
||
| 229 | 62 .loc 1 158 3 view .LVU5 |
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| 230 | 63 0000 044B ldr r3, .L3 |
||
| 231 | 64 0002 1A69 ldr r2, [r3, #16] |
||
| 232 | 65 0004 42F08052 orr r2, r2, #268435456 |
||
| 233 | 66 0008 1A61 str r2, [r3, #16] |
||
| 234 | 159:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); |
||
| 235 | 67 .loc 1 159 3 view .LVU6 |
||
| 236 | 68 000a 1A69 ldr r2, [r3, #16] |
||
| 237 | 69 000c 22F08052 bic r2, r2, #268435456 |
||
| 238 | 70 0010 1A61 str r2, [r3, #16] |
||
| 239 | 160:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 240 | 71 .loc 1 160 1 is_stmt 0 view .LVU7 |
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| 19 | mjames | 241 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 5 |
| 16 | mjames | 242 | |
| 243 | |||
| 244 | 72 0012 7047 bx lr |
||
| 245 | 73 .L4: |
||
| 246 | 74 .align 2 |
||
| 247 | 75 .L3: |
||
| 248 | 76 0014 00100240 .word 1073876992 |
||
| 249 | 77 .cfi_endproc |
||
| 250 | 78 .LFE66: |
||
| 251 | 80 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits |
||
| 252 | 81 .align 1 |
||
| 253 | 82 .global HAL_PWR_EnableBkUpAccess |
||
| 254 | 83 .syntax unified |
||
| 255 | 84 .thumb |
||
| 256 | 85 .thumb_func |
||
| 257 | 86 .fpu softvfp |
||
| 258 | 88 HAL_PWR_EnableBkUpAccess: |
||
| 259 | 89 .LFB67: |
||
| 260 | 161:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 261 | 162:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 262 | 163:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC |
||
| 263 | 164:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * backup data registers ). |
||
| 264 | 165:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note If the HSE divided by 128 is used as the RTC clock, the |
||
| 265 | 166:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. |
||
| 266 | 167:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 267 | 168:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 268 | 169:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) |
||
| 269 | 170:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 270 | 90 .loc 1 170 1 is_stmt 1 view -0 |
||
| 271 | 91 .cfi_startproc |
||
| 272 | 92 @ args = 0, pretend = 0, frame = 0 |
||
| 273 | 93 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 274 | 94 @ link register save eliminated. |
||
| 275 | 171:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Enable access to RTC and backup registers */ |
||
| 276 | 172:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; |
||
| 277 | 95 .loc 1 172 3 view .LVU9 |
||
| 278 | 96 .loc 1 172 32 is_stmt 0 view .LVU10 |
||
| 279 | 97 0000 014B ldr r3, .L6 |
||
| 280 | 98 0002 0122 movs r2, #1 |
||
| 281 | 99 0004 1A60 str r2, [r3] |
||
| 282 | 173:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 283 | 100 .loc 1 173 1 view .LVU11 |
||
| 284 | 101 0006 7047 bx lr |
||
| 285 | 102 .L7: |
||
| 286 | 103 .align 2 |
||
| 287 | 104 .L6: |
||
| 288 | 105 0008 20000E42 .word 1108213792 |
||
| 289 | 106 .cfi_endproc |
||
| 290 | 107 .LFE67: |
||
| 291 | 109 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits |
||
| 292 | 110 .align 1 |
||
| 293 | 111 .global HAL_PWR_DisableBkUpAccess |
||
| 294 | 112 .syntax unified |
||
| 295 | 113 .thumb |
||
| 296 | 114 .thumb_func |
||
| 297 | 115 .fpu softvfp |
||
| 298 | 117 HAL_PWR_DisableBkUpAccess: |
||
| 299 | 118 .LFB68: |
||
| 300 | 174:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 19 | mjames | 301 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 6 |
| 16 | mjames | 302 | |
| 303 | |||
| 304 | 175:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 305 | 176:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC |
||
| 306 | 177:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * backup data registers). |
||
| 307 | 178:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note If the HSE divided by 128 is used as the RTC clock, the |
||
| 308 | 179:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. |
||
| 309 | 180:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 310 | 181:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 311 | 182:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) |
||
| 312 | 183:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 313 | 119 .loc 1 183 1 is_stmt 1 view -0 |
||
| 314 | 120 .cfi_startproc |
||
| 315 | 121 @ args = 0, pretend = 0, frame = 0 |
||
| 316 | 122 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 317 | 123 @ link register save eliminated. |
||
| 318 | 184:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Disable access to RTC and backup registers */ |
||
| 319 | 185:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; |
||
| 320 | 124 .loc 1 185 3 view .LVU13 |
||
| 321 | 125 .loc 1 185 32 is_stmt 0 view .LVU14 |
||
| 322 | 126 0000 014B ldr r3, .L9 |
||
| 323 | 127 0002 0022 movs r2, #0 |
||
| 324 | 128 0004 1A60 str r2, [r3] |
||
| 325 | 186:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 326 | 129 .loc 1 186 1 view .LVU15 |
||
| 327 | 130 0006 7047 bx lr |
||
| 328 | 131 .L10: |
||
| 329 | 132 .align 2 |
||
| 330 | 133 .L9: |
||
| 331 | 134 0008 20000E42 .word 1108213792 |
||
| 332 | 135 .cfi_endproc |
||
| 333 | 136 .LFE68: |
||
| 334 | 138 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits |
||
| 335 | 139 .align 1 |
||
| 336 | 140 .global HAL_PWR_ConfigPVD |
||
| 337 | 141 .syntax unified |
||
| 338 | 142 .thumb |
||
| 339 | 143 .thumb_func |
||
| 340 | 144 .fpu softvfp |
||
| 341 | 146 HAL_PWR_ConfigPVD: |
||
| 342 | 147 .LVL0: |
||
| 343 | 148 .LFB69: |
||
| 344 | 187:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 345 | 188:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 346 | 189:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @} |
||
| 347 | 190:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 348 | 191:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 349 | 192:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions |
||
| 350 | 193:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Low Power modes configuration functions |
||
| 351 | 194:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * |
||
| 352 | 195:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** @verbatim |
||
| 353 | 196:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** =============================================================================== |
||
| 354 | 197:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ##### Peripheral Control functions ##### |
||
| 355 | 198:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** =============================================================================== |
||
| 356 | 199:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 357 | 200:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** PVD configuration *** |
||
| 358 | 201:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ========================= |
||
| 359 | 202:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
||
| 360 | 203:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a |
||
| 19 | mjames | 361 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 7 |
| 16 | mjames | 362 | |
| 363 | |||
| 364 | 204:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). |
||
| 365 | 205:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 366 | 206:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower |
||
| 367 | 207:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI |
||
| 368 | 208:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through |
||
| 369 | 209:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PVD_EXTI_ENABLE_IT() macro. |
||
| 370 | 210:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode. |
||
| 371 | 211:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 372 | 212:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** WakeUp pin configuration *** |
||
| 373 | 213:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ================================ |
||
| 374 | 214:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
||
| 375 | 215:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) WakeUp pin is used to wake up the system from Standby mode. This pin is |
||
| 376 | 216:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** forced in input pull-down configuration and is active on rising edges. |
||
| 377 | 217:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) There is one WakeUp pin: |
||
| 378 | 218:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** WakeUp Pin 1 on PA.00. |
||
| 379 | 219:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 380 | 220:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
||
| 381 | 221:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 382 | 222:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Low Power modes configuration *** |
||
| 383 | 223:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ===================================== |
||
| 384 | 224:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
||
| 385 | 225:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The device features 3 low-power modes: |
||
| 386 | 226:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like |
||
| 387 | 227:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** NVIC, SysTick, etc. are kept running |
||
| 388 | 228:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Stop mode: All clocks are stopped |
||
| 389 | 229:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Standby mode: 1.8V domain powered off |
||
| 390 | 230:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 391 | 231:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 392 | 232:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Sleep mode *** |
||
| 393 | 233:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ================== |
||
| 394 | 234:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
||
| 395 | 235:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Entry: |
||
| 396 | 236:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S |
||
| 397 | 237:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** functions with |
||
| 398 | 238:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
||
| 399 | 239:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
||
| 400 | 240:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 401 | 241:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Exit: |
||
| 402 | 242:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt |
||
| 403 | 243:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. |
||
| 404 | 244:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. |
||
| 405 | 245:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex |
||
| 406 | 246:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+++) Any EXTI Line (Internal or External) configured in Event mode |
||
| 407 | 247:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 408 | 248:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Stop mode *** |
||
| 409 | 249:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ================= |
||
| 410 | 250:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
||
| 411 | 251:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral |
||
| 412 | 252:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** clock gating. The voltage regulator can be configured either in normal or low-power mode. |
||
| 413 | 253:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC |
||
| 414 | 254:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** oscillators are disabled. SRAM and register contents are preserved. |
||
| 415 | 255:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** In Stop mode, all I/O pins keep the same state as in Run mode. |
||
| 416 | 256:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 417 | 257:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Entry: |
||
| 418 | 258:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPE |
||
| 419 | 259:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** function with: |
||
| 420 | 260:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. |
||
| 19 | mjames | 421 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 8 |
| 16 | mjames | 422 | |
| 423 | |||
| 424 | 261:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. |
||
| 425 | 262:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction |
||
| 426 | 263:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction |
||
| 427 | 264:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Exit: |
||
| 428 | 265:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode wi |
||
| 429 | 266:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. |
||
| 430 | 267:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 431 | 268:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Standby mode *** |
||
| 432 | 269:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ==================== |
||
| 433 | 270:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
||
| 434 | 271:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based on the |
||
| 435 | 272:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is |
||
| 436 | 273:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also |
||
| 437 | 274:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** switched off. SRAM and register contents are lost except for registers in the Backup domain |
||
| 438 | 275:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** and Standby circuitry |
||
| 439 | 276:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 440 | 277:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Entry: |
||
| 441 | 278:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
||
| 442 | 279:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) Exit: |
||
| 443 | 280:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in |
||
| 444 | 281:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** NRSTpin, IWDG Reset |
||
| 445 | 282:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 446 | 283:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode *** |
||
| 447 | 284:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ============================================= |
||
| 448 | 285:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
||
| 449 | 286:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 450 | 287:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) The MCU can be woken up from low-power mode by an RTC Alarm event, |
||
| 451 | 288:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode). |
||
| 452 | 289:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 453 | 290:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes |
||
| 454 | 291:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 455 | 292:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to |
||
| 456 | 293:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() functio |
||
| 457 | 294:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 458 | 295:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *** PWR Workarounds linked to Silicon Limitation *** |
||
| 459 | 296:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** ==================================================== |
||
| 460 | 297:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** [..] |
||
| 461 | 298:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** Below the list of all silicon limitations known on STM32F1xx prouct. |
||
| 462 | 299:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 463 | 300:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (#)Workarounds Implemented inside PWR HAL Driver |
||
| 464 | 301:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function |
||
| 465 | 302:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 466 | 303:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** @endverbatim |
||
| 467 | 304:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @{ |
||
| 468 | 305:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 469 | 306:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 470 | 307:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 471 | 308:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). |
||
| 472 | 309:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration |
||
| 473 | 310:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * information for the PVD. |
||
| 474 | 311:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for |
||
| 475 | 312:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each |
||
| 476 | 313:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * detection level. |
||
| 477 | 314:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 478 | 315:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 479 | 316:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) |
||
| 480 | 317:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 19 | mjames | 481 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 9 |
| 16 | mjames | 482 | |
| 483 | |||
| 484 | 149 .loc 1 317 1 is_stmt 1 view -0 |
||
| 485 | 150 .cfi_startproc |
||
| 486 | 151 @ args = 0, pretend = 0, frame = 0 |
||
| 487 | 152 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 488 | 153 @ link register save eliminated. |
||
| 489 | 318:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameters */ |
||
| 490 | 319:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); |
||
| 491 | 154 .loc 1 319 3 view .LVU17 |
||
| 492 | 320:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); |
||
| 493 | 155 .loc 1 320 3 view .LVU18 |
||
| 494 | 321:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 495 | 322:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */ |
||
| 496 | 323:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); |
||
| 497 | 156 .loc 1 323 3 view .LVU19 |
||
| 498 | 157 0000 1E4A ldr r2, .L16 |
||
| 499 | 158 0002 1368 ldr r3, [r2] |
||
| 500 | 159 0004 23F0E003 bic r3, r3, #224 |
||
| 501 | 160 0008 0168 ldr r1, [r0] |
||
| 502 | 161 000a 0B43 orrs r3, r3, r1 |
||
| 503 | 162 000c 1360 str r3, [r2] |
||
| 504 | 324:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 505 | 325:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
||
| 506 | 326:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); |
||
| 507 | 163 .loc 1 326 3 view .LVU20 |
||
| 508 | 164 000e 1C4B ldr r3, .L16+4 |
||
| 509 | 165 0010 5A68 ldr r2, [r3, #4] |
||
| 510 | 166 0012 22F48032 bic r2, r2, #65536 |
||
| 511 | 167 0016 5A60 str r2, [r3, #4] |
||
| 512 | 327:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); |
||
| 513 | 168 .loc 1 327 3 view .LVU21 |
||
| 514 | 169 0018 1A68 ldr r2, [r3] |
||
| 515 | 170 001a 22F48032 bic r2, r2, #65536 |
||
| 516 | 171 001e 1A60 str r2, [r3] |
||
| 517 | 328:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); |
||
| 518 | 172 .loc 1 328 3 view .LVU22 |
||
| 519 | 173 0020 DA68 ldr r2, [r3, #12] |
||
| 520 | 174 0022 22F48032 bic r2, r2, #65536 |
||
| 521 | 175 0026 DA60 str r2, [r3, #12] |
||
| 522 | 329:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); |
||
| 523 | 176 .loc 1 329 3 view .LVU23 |
||
| 524 | 177 0028 9A68 ldr r2, [r3, #8] |
||
| 525 | 178 002a 22F48032 bic r2, r2, #65536 |
||
| 526 | 179 002e 9A60 str r2, [r3, #8] |
||
| 527 | 330:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 528 | 331:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Configure interrupt mode */ |
||
| 529 | 332:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) |
||
| 530 | 180 .loc 1 332 3 view .LVU24 |
||
| 531 | 181 .loc 1 332 17 is_stmt 0 view .LVU25 |
||
| 532 | 182 0030 4368 ldr r3, [r0, #4] |
||
| 533 | 183 .loc 1 332 5 view .LVU26 |
||
| 534 | 184 0032 13F4803F tst r3, #65536 |
||
| 535 | 185 0036 04D0 beq .L12 |
||
| 536 | 333:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 537 | 334:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); |
||
| 538 | 186 .loc 1 334 5 is_stmt 1 view .LVU27 |
||
| 539 | 187 0038 114A ldr r2, .L16+4 |
||
| 540 | 188 003a 1368 ldr r3, [r2] |
||
| 19 | mjames | 541 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 10 |
| 16 | mjames | 542 | |
| 543 | |||
| 544 | 189 003c 43F48033 orr r3, r3, #65536 |
||
| 545 | 190 0040 1360 str r3, [r2] |
||
| 546 | 191 .L12: |
||
| 547 | 335:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 548 | 336:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 549 | 337:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Configure event mode */ |
||
| 550 | 338:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) |
||
| 551 | 192 .loc 1 338 3 view .LVU28 |
||
| 552 | 193 .loc 1 338 17 is_stmt 0 view .LVU29 |
||
| 553 | 194 0042 4368 ldr r3, [r0, #4] |
||
| 554 | 195 .loc 1 338 5 view .LVU30 |
||
| 555 | 196 0044 13F4003F tst r3, #131072 |
||
| 556 | 197 0048 04D0 beq .L13 |
||
| 557 | 339:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 558 | 340:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); |
||
| 559 | 198 .loc 1 340 5 is_stmt 1 view .LVU31 |
||
| 560 | 199 004a 0D4A ldr r2, .L16+4 |
||
| 561 | 200 004c 5368 ldr r3, [r2, #4] |
||
| 562 | 201 004e 43F48033 orr r3, r3, #65536 |
||
| 563 | 202 0052 5360 str r3, [r2, #4] |
||
| 564 | 203 .L13: |
||
| 565 | 341:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 566 | 342:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 567 | 343:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Configure the edge */ |
||
| 568 | 344:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) |
||
| 569 | 204 .loc 1 344 3 view .LVU32 |
||
| 570 | 205 .loc 1 344 17 is_stmt 0 view .LVU33 |
||
| 571 | 206 0054 4368 ldr r3, [r0, #4] |
||
| 572 | 207 .loc 1 344 5 view .LVU34 |
||
| 573 | 208 0056 13F0010F tst r3, #1 |
||
| 574 | 209 005a 04D0 beq .L14 |
||
| 575 | 345:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 576 | 346:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); |
||
| 577 | 210 .loc 1 346 5 is_stmt 1 view .LVU35 |
||
| 578 | 211 005c 084A ldr r2, .L16+4 |
||
| 579 | 212 005e 9368 ldr r3, [r2, #8] |
||
| 580 | 213 0060 43F48033 orr r3, r3, #65536 |
||
| 581 | 214 0064 9360 str r3, [r2, #8] |
||
| 582 | 215 .L14: |
||
| 583 | 347:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 584 | 348:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 585 | 349:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) |
||
| 586 | 216 .loc 1 349 3 view .LVU36 |
||
| 587 | 217 .loc 1 349 17 is_stmt 0 view .LVU37 |
||
| 588 | 218 0066 4368 ldr r3, [r0, #4] |
||
| 589 | 219 .loc 1 349 5 view .LVU38 |
||
| 590 | 220 0068 13F0020F tst r3, #2 |
||
| 591 | 221 006c 04D0 beq .L11 |
||
| 592 | 350:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 593 | 351:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
||
| 594 | 222 .loc 1 351 5 is_stmt 1 view .LVU39 |
||
| 595 | 223 006e 044A ldr r2, .L16+4 |
||
| 596 | 224 0070 D368 ldr r3, [r2, #12] |
||
| 597 | 225 0072 43F48033 orr r3, r3, #65536 |
||
| 598 | 226 0076 D360 str r3, [r2, #12] |
||
| 599 | 227 .L11: |
||
| 600 | 352:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 19 | mjames | 601 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 11 |
| 16 | mjames | 602 | |
| 603 | |||
| 604 | 353:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 605 | 228 .loc 1 353 1 is_stmt 0 view .LVU40 |
||
| 606 | 229 0078 7047 bx lr |
||
| 607 | 230 .L17: |
||
| 608 | 231 007a 00BF .align 2 |
||
| 609 | 232 .L16: |
||
| 610 | 233 007c 00700040 .word 1073770496 |
||
| 611 | 234 0080 00040140 .word 1073808384 |
||
| 612 | 235 .cfi_endproc |
||
| 613 | 236 .LFE69: |
||
| 614 | 238 .section .text.HAL_PWR_EnablePVD,"ax",%progbits |
||
| 615 | 239 .align 1 |
||
| 616 | 240 .global HAL_PWR_EnablePVD |
||
| 617 | 241 .syntax unified |
||
| 618 | 242 .thumb |
||
| 619 | 243 .thumb_func |
||
| 620 | 244 .fpu softvfp |
||
| 621 | 246 HAL_PWR_EnablePVD: |
||
| 622 | 247 .LFB70: |
||
| 623 | 354:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 624 | 355:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 625 | 356:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enables the Power Voltage Detector(PVD). |
||
| 626 | 357:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 627 | 358:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 628 | 359:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void) |
||
| 629 | 360:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 630 | 248 .loc 1 360 1 is_stmt 1 view -0 |
||
| 631 | 249 .cfi_startproc |
||
| 632 | 250 @ args = 0, pretend = 0, frame = 0 |
||
| 633 | 251 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 634 | 252 @ link register save eliminated. |
||
| 635 | 361:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Enable the power voltage detector */ |
||
| 636 | 362:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; |
||
| 637 | 253 .loc 1 362 3 view .LVU42 |
||
| 638 | 254 .loc 1 362 33 is_stmt 0 view .LVU43 |
||
| 639 | 255 0000 014B ldr r3, .L19 |
||
| 640 | 256 0002 0122 movs r2, #1 |
||
| 641 | 257 0004 1A60 str r2, [r3] |
||
| 642 | 363:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 643 | 258 .loc 1 363 1 view .LVU44 |
||
| 644 | 259 0006 7047 bx lr |
||
| 645 | 260 .L20: |
||
| 646 | 261 .align 2 |
||
| 647 | 262 .L19: |
||
| 648 | 263 0008 10000E42 .word 1108213776 |
||
| 649 | 264 .cfi_endproc |
||
| 650 | 265 .LFE70: |
||
| 651 | 267 .section .text.HAL_PWR_DisablePVD,"ax",%progbits |
||
| 652 | 268 .align 1 |
||
| 653 | 269 .global HAL_PWR_DisablePVD |
||
| 654 | 270 .syntax unified |
||
| 655 | 271 .thumb |
||
| 656 | 272 .thumb_func |
||
| 657 | 273 .fpu softvfp |
||
| 658 | 275 HAL_PWR_DisablePVD: |
||
| 659 | 276 .LFB71: |
||
| 660 | 364:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 19 | mjames | 661 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 12 |
| 16 | mjames | 662 | |
| 663 | |||
| 664 | 365:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 665 | 366:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables the Power Voltage Detector(PVD). |
||
| 666 | 367:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 667 | 368:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 668 | 369:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void) |
||
| 669 | 370:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 670 | 277 .loc 1 370 1 is_stmt 1 view -0 |
||
| 671 | 278 .cfi_startproc |
||
| 672 | 279 @ args = 0, pretend = 0, frame = 0 |
||
| 673 | 280 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 674 | 281 @ link register save eliminated. |
||
| 675 | 371:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Disable the power voltage detector */ |
||
| 676 | 372:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; |
||
| 677 | 282 .loc 1 372 3 view .LVU46 |
||
| 678 | 283 .loc 1 372 33 is_stmt 0 view .LVU47 |
||
| 679 | 284 0000 014B ldr r3, .L22 |
||
| 680 | 285 0002 0022 movs r2, #0 |
||
| 681 | 286 0004 1A60 str r2, [r3] |
||
| 682 | 373:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 683 | 287 .loc 1 373 1 view .LVU48 |
||
| 684 | 288 0006 7047 bx lr |
||
| 685 | 289 .L23: |
||
| 686 | 290 .align 2 |
||
| 687 | 291 .L22: |
||
| 688 | 292 0008 10000E42 .word 1108213776 |
||
| 689 | 293 .cfi_endproc |
||
| 690 | 294 .LFE71: |
||
| 691 | 296 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits |
||
| 692 | 297 .align 1 |
||
| 693 | 298 .global HAL_PWR_EnableWakeUpPin |
||
| 694 | 299 .syntax unified |
||
| 695 | 300 .thumb |
||
| 696 | 301 .thumb_func |
||
| 697 | 302 .fpu softvfp |
||
| 698 | 304 HAL_PWR_EnableWakeUpPin: |
||
| 699 | 305 .LVL1: |
||
| 700 | 306 .LFB72: |
||
| 701 | 374:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 702 | 375:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 703 | 376:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality. |
||
| 704 | 377:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. |
||
| 705 | 378:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values: |
||
| 706 | 379:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 |
||
| 707 | 380:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 708 | 381:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 709 | 382:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
||
| 710 | 383:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 711 | 307 .loc 1 383 1 is_stmt 1 view -0 |
||
| 712 | 308 .cfi_startproc |
||
| 713 | 309 @ args = 0, pretend = 0, frame = 0 |
||
| 714 | 310 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 715 | 311 @ link register save eliminated. |
||
| 716 | 384:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameter */ |
||
| 717 | 385:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
||
| 718 | 312 .loc 1 385 3 view .LVU50 |
||
| 719 | 386:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Enable the EWUPx pin */ |
||
| 720 | 387:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; |
||
| 19 | mjames | 721 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 13 |
| 16 | mjames | 722 | |
| 723 | |||
| 724 | 313 .loc 1 387 3 view .LVU51 |
||
| 725 | 314 .LBB6: |
||
| 726 | 315 .LBI6: |
||
| 727 | 316 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" |
||
| 728 | 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** |
||
| 729 | 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h |
||
| 730 | 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file |
||
| 731 | 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 |
||
| 732 | 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 |
||
| 733 | 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ |
||
| 734 | 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* |
||
| 735 | 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
||
| 736 | 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * |
||
| 737 | 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 |
||
| 738 | 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * |
||
| 739 | 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may |
||
| 740 | 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. |
||
| 741 | 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at |
||
| 742 | 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * |
||
| 743 | 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 |
||
| 744 | 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * |
||
| 745 | 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software |
||
| 746 | 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||
| 747 | 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||
| 748 | 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and |
||
| 749 | 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. |
||
| 750 | 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 751 | 24:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 752 | 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H |
||
| 753 | 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H |
||
| 754 | 27:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 755 | 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ |
||
| 756 | 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 757 | 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" |
||
| 758 | 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" |
||
| 759 | 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" |
||
| 760 | 33:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 761 | 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ |
||
| 762 | 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin |
||
| 763 | 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) |
||
| 764 | 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 765 | 38:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 766 | 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ |
||
| 767 | 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM |
||
| 768 | 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm |
||
| 769 | 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 770 | 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE |
||
| 771 | 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline |
||
| 772 | 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 773 | 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE |
||
| 774 | 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline |
||
| 775 | 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 776 | 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE |
||
| 777 | 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline |
||
| 778 | 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 779 | 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN |
||
| 780 | 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) |
||
| 19 | mjames | 781 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 14 |
| 16 | mjames | 782 | |
| 783 | |||
| 784 | 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 785 | 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED |
||
| 786 | 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) |
||
| 787 | 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 788 | 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK |
||
| 789 | 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) |
||
| 790 | 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 791 | 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED |
||
| 792 | 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) |
||
| 793 | 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 794 | 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT |
||
| 795 | 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) |
||
| 796 | 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 797 | 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION |
||
| 798 | 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) |
||
| 799 | 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 800 | 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ |
||
| 801 | 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 802 | 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 803 | 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 804 | 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; |
||
| 805 | 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 806 | 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
||
| 807 | 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 808 | 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE |
||
| 809 | 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 810 | 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 811 | 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 812 | 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; |
||
| 813 | 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 814 | 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- |
||
| 815 | 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 816 | 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ |
||
| 817 | 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 818 | 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 819 | 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 820 | 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; |
||
| 821 | 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 822 | 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add |
||
| 823 | 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 824 | 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE |
||
| 825 | 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 826 | 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 827 | 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 828 | 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; |
||
| 829 | 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 830 | 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- |
||
| 831 | 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 832 | 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ |
||
| 833 | 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 834 | 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 835 | 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 836 | 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; |
||
| 837 | 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 838 | 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add |
||
| 839 | 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 840 | 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED |
||
| 19 | mjames | 841 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 15 |
| 16 | mjames | 842 | |
| 843 | |||
| 844 | 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) |
||
| 845 | 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 846 | 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT |
||
| 847 | 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict |
||
| 848 | 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 849 | 116:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 850 | 117:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 851 | 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ |
||
| 852 | 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface |
||
| 853 | 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
||
| 854 | 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ |
||
| 855 | 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 856 | 123:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 857 | 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 858 | 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts |
||
| 859 | 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. |
||
| 860 | 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. |
||
| 861 | 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 862 | 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) |
||
| 863 | 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 864 | 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); |
||
| 865 | 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 866 | 133:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 867 | 134:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 868 | 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 869 | 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts |
||
| 870 | 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. |
||
| 871 | 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. |
||
| 872 | 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 873 | 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) |
||
| 874 | 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 875 | 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); |
||
| 876 | 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 877 | 144:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 878 | 145:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 879 | 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 880 | 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register |
||
| 881 | 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. |
||
| 882 | 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value |
||
| 883 | 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 884 | 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) |
||
| 885 | 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 886 | 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 887 | 154:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 888 | 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); |
||
| 889 | 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 890 | 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 891 | 158:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 892 | 159:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 893 | 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 894 | 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 895 | 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) |
||
| 896 | 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. |
||
| 897 | 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value |
||
| 898 | 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 899 | 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) |
||
| 900 | 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 19 | mjames | 901 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 16 |
| 16 | mjames | 902 | |
| 903 | |||
| 904 | 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 905 | 169:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 906 | 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); |
||
| 907 | 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 908 | 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 909 | 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 910 | 174:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 911 | 175:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 912 | 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 913 | 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register |
||
| 914 | 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. |
||
| 915 | 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set |
||
| 916 | 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 917 | 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) |
||
| 918 | 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 919 | 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); |
||
| 920 | 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 921 | 185:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 922 | 186:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 923 | 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 924 | 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 925 | 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) |
||
| 926 | 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. |
||
| 927 | 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set |
||
| 928 | 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 929 | 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) |
||
| 930 | 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 931 | 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); |
||
| 932 | 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 933 | 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 934 | 198:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 935 | 199:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 936 | 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 937 | 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register |
||
| 938 | 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. |
||
| 939 | 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value |
||
| 940 | 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 941 | 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) |
||
| 942 | 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 943 | 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 944 | 208:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 945 | 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); |
||
| 946 | 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 947 | 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 948 | 212:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 949 | 213:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 950 | 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 951 | 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register |
||
| 952 | 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. |
||
| 953 | 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value |
||
| 954 | 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 955 | 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) |
||
| 956 | 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 957 | 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 958 | 222:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 959 | 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); |
||
| 960 | 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 19 | mjames | 961 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 17 |
| 16 | mjames | 962 | |
| 963 | |||
| 964 | 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 965 | 226:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 966 | 227:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 967 | 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 968 | 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register |
||
| 969 | 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. |
||
| 970 | 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value |
||
| 971 | 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 972 | 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) |
||
| 973 | 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 974 | 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 975 | 236:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 976 | 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); |
||
| 977 | 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 978 | 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 979 | 240:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 980 | 241:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 981 | 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 982 | 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer |
||
| 983 | 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). |
||
| 984 | 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value |
||
| 985 | 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 986 | 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) |
||
| 987 | 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 988 | 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 989 | 250:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 990 | 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); |
||
| 991 | 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 992 | 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 993 | 254:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 994 | 255:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 995 | 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 996 | 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 997 | 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) |
||
| 998 | 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s |
||
| 999 | 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value |
||
| 1000 | 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1001 | 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) |
||
| 1002 | 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1003 | 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1004 | 265:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1005 | 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); |
||
| 1006 | 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1007 | 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1008 | 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1009 | 270:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1010 | 271:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1011 | 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1012 | 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer |
||
| 1013 | 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). |
||
| 1014 | 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set |
||
| 1015 | 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1016 | 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) |
||
| 1017 | 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1018 | 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); |
||
| 1019 | 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1020 | 281:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 19 | mjames | 1021 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 18 |
| 16 | mjames | 1022 | |
| 1023 | |||
| 1024 | 282:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1025 | 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1026 | 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1027 | 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) |
||
| 1028 | 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta |
||
| 1029 | 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set |
||
| 1030 | 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1031 | 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) |
||
| 1032 | 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1033 | 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); |
||
| 1034 | 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1035 | 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1036 | 294:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1037 | 295:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1038 | 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1039 | 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer |
||
| 1040 | 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). |
||
| 1041 | 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value |
||
| 1042 | 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1043 | 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) |
||
| 1044 | 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1045 | 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1046 | 304:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1047 | 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); |
||
| 1048 | 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1049 | 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1050 | 308:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1051 | 309:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1052 | 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1053 | 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1054 | 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) |
||
| 1055 | 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat |
||
| 1056 | 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value |
||
| 1057 | 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1058 | 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) |
||
| 1059 | 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1060 | 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1061 | 319:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1062 | 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); |
||
| 1063 | 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1064 | 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1065 | 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1066 | 324:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1067 | 325:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1068 | 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1069 | 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer |
||
| 1070 | 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). |
||
| 1071 | 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set |
||
| 1072 | 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1073 | 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) |
||
| 1074 | 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1075 | 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); |
||
| 1076 | 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1077 | 335:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1078 | 336:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1079 | 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1080 | 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 19 | mjames | 1081 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 19 |
| 16 | mjames | 1082 | |
| 1083 | |||
| 1084 | 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) |
||
| 1085 | 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. |
||
| 1086 | 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set |
||
| 1087 | 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1088 | 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) |
||
| 1089 | 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1090 | 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); |
||
| 1091 | 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1092 | 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1093 | 348:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1094 | 349:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1095 | 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1096 | 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1097 | 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) |
||
| 1098 | 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. |
||
| 1099 | 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value |
||
| 1100 | 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1101 | 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) |
||
| 1102 | 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1103 | 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1104 | 359:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1105 | 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); |
||
| 1106 | 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1107 | 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1108 | 363:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1109 | 364:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1110 | 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1111 | 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) |
||
| 1112 | 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. |
||
| 1113 | 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set |
||
| 1114 | 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1115 | 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) |
||
| 1116 | 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1117 | 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); |
||
| 1118 | 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1119 | 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1120 | 375:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1121 | 376:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1122 | 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1123 | 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask |
||
| 1124 | 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. |
||
| 1125 | 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value |
||
| 1126 | 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1127 | 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) |
||
| 1128 | 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1129 | 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1130 | 385:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1131 | 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); |
||
| 1132 | 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1133 | 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1134 | 389:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1135 | 390:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1136 | 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1137 | 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1138 | 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) |
||
| 1139 | 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg |
||
| 1140 | 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value |
||
| 19 | mjames | 1141 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 20 |
| 16 | mjames | 1142 | |
| 1143 | |||
| 1144 | 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1145 | 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) |
||
| 1146 | 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1147 | 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1148 | 400:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1149 | 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); |
||
| 1150 | 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1151 | 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1152 | 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1153 | 405:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1154 | 406:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1155 | 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1156 | 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask |
||
| 1157 | 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. |
||
| 1158 | 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask |
||
| 1159 | 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1160 | 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) |
||
| 1161 | 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1162 | 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); |
||
| 1163 | 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1164 | 416:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1165 | 417:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1166 | 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1167 | 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1168 | 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) |
||
| 1169 | 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. |
||
| 1170 | 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask |
||
| 1171 | 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1172 | 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) |
||
| 1173 | 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1174 | 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); |
||
| 1175 | 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1176 | 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1177 | 429:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1178 | 430:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1179 | 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||
| 1180 | 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
||
| 1181 | 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
||
| 1182 | 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1183 | 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ |
||
| 1184 | 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. |
||
| 1185 | 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. |
||
| 1186 | 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1187 | 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) |
||
| 1188 | 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1189 | 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); |
||
| 1190 | 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1191 | 443:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1192 | 444:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1193 | 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1194 | 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ |
||
| 1195 | 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. |
||
| 1196 | 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. |
||
| 1197 | 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1198 | 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) |
||
| 1199 | 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1200 | 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); |
||
| 19 | mjames | 1201 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 21 |
| 16 | mjames | 1202 | |
| 1203 | |||
| 1204 | 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1205 | 454:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1206 | 455:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1207 | 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1208 | 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority |
||
| 1209 | 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. |
||
| 1210 | 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value |
||
| 1211 | 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1212 | 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) |
||
| 1213 | 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1214 | 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1215 | 464:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1216 | 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); |
||
| 1217 | 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1218 | 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1219 | 468:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1220 | 469:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1221 | 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1222 | 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1223 | 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) |
||
| 1224 | 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. |
||
| 1225 | 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value |
||
| 1226 | 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1227 | 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) |
||
| 1228 | 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1229 | 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1230 | 479:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1231 | 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); |
||
| 1232 | 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1233 | 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1234 | 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1235 | 484:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1236 | 485:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1237 | 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1238 | 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority |
||
| 1239 | 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. |
||
| 1240 | 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set |
||
| 1241 | 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1242 | 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) |
||
| 1243 | 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1244 | 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); |
||
| 1245 | 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1246 | 495:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1247 | 496:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1248 | 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1249 | 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1250 | 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) |
||
| 1251 | 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. |
||
| 1252 | 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set |
||
| 1253 | 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1254 | 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) |
||
| 1255 | 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1256 | 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); |
||
| 1257 | 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1258 | 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1259 | 508:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1260 | 509:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 19 | mjames | 1261 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 22 |
| 16 | mjames | 1262 | |
| 1263 | |||
| 1264 | 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1265 | 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition |
||
| 1266 | 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable |
||
| 1267 | 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. |
||
| 1268 | 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set |
||
| 1269 | 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1270 | 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) |
||
| 1271 | 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1272 | 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); |
||
| 1273 | 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1274 | 520:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1275 | 521:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1276 | 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1277 | 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask |
||
| 1278 | 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. |
||
| 1279 | 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value |
||
| 1280 | 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1281 | 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) |
||
| 1282 | 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1283 | 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1284 | 530:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1285 | 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
||
| 1286 | 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1287 | 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1288 | 534:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1289 | 535:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1290 | 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1291 | 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1292 | 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) |
||
| 1293 | 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. |
||
| 1294 | 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value |
||
| 1295 | 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1296 | 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) |
||
| 1297 | 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1298 | 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1299 | 545:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1300 | 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); |
||
| 1301 | 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1302 | 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1303 | 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1304 | 550:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1305 | 551:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1306 | 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1307 | 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask |
||
| 1308 | 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. |
||
| 1309 | 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set |
||
| 1310 | 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1311 | 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) |
||
| 1312 | 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1313 | 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); |
||
| 1314 | 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1315 | 561:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1316 | 562:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1317 | 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1318 | 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1319 | 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) |
||
| 1320 | 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. |
||
| 19 | mjames | 1321 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 23 |
| 16 | mjames | 1322 | |
| 1323 | |||
| 1324 | 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set |
||
| 1325 | 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1326 | 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) |
||
| 1327 | 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1328 | 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); |
||
| 1329 | 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1330 | 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1331 | 574:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1332 | 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||
| 1333 | 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
||
| 1334 | 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ |
||
| 1335 | 578:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1336 | 579:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1337 | 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
||
| 1338 | 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
||
| 1339 | 582:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1340 | 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1341 | 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit |
||
| 1342 | 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 1343 | 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure |
||
| 1344 | 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. |
||
| 1345 | 588:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1346 | 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). |
||
| 1347 | 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value |
||
| 1348 | 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1349 | 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) |
||
| 1350 | 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1351 | 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||
| 1352 | 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||
| 1353 | 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI |
||
| 1354 | 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; |
||
| 1355 | 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1356 | 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1357 | 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); |
||
| 1358 | 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 1359 | 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1360 | 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1361 | 604:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1362 | 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1363 | 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1364 | 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) |
||
| 1365 | 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 1366 | 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. |
||
| 1367 | 610:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1368 | 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in |
||
| 1369 | 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value |
||
| 1370 | 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1371 | 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) |
||
| 1372 | 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1373 | 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) |
||
| 1374 | 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI |
||
| 1375 | 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; |
||
| 1376 | 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1377 | 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1378 | 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); |
||
| 1379 | 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 1380 | 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 19 | mjames | 1381 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 24 |
| 16 | mjames | 1382 | |
| 1383 | |||
| 1384 | 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1385 | 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1386 | 626:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1387 | 627:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1388 | 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1389 | 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit |
||
| 1390 | 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 1391 | 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure |
||
| 1392 | 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. |
||
| 1393 | 633:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1394 | 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). |
||
| 1395 | 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set |
||
| 1396 | 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1397 | 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) |
||
| 1398 | 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1399 | 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||
| 1400 | 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||
| 1401 | 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI |
||
| 1402 | 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; |
||
| 1403 | 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1404 | 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); |
||
| 1405 | 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1406 | 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1407 | 647:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1408 | 648:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1409 | 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1410 | 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1411 | 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) |
||
| 1412 | 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 1413 | 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. |
||
| 1414 | 654:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1415 | 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s |
||
| 1416 | 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set |
||
| 1417 | 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1418 | 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) |
||
| 1419 | 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1420 | 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) |
||
| 1421 | 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI |
||
| 1422 | 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; |
||
| 1423 | 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1424 | 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); |
||
| 1425 | 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1426 | 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1427 | 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1428 | 668:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1429 | 669:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1430 | 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1431 | 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit |
||
| 1432 | 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 1433 | 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure |
||
| 1434 | 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. |
||
| 1435 | 675:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1436 | 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). |
||
| 1437 | 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value |
||
| 1438 | 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1439 | 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) |
||
| 1440 | 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 19 | mjames | 1441 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 25 |
| 16 | mjames | 1442 | |
| 1443 | |||
| 1444 | 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||
| 1445 | 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||
| 1446 | 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI |
||
| 1447 | 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; |
||
| 1448 | 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1449 | 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1450 | 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); |
||
| 1451 | 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 1452 | 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1453 | 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1454 | 691:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1455 | 692:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1456 | 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 1457 | 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1458 | 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) |
||
| 1459 | 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 1460 | 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. |
||
| 1461 | 698:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1462 | 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec |
||
| 1463 | 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value |
||
| 1464 | 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1465 | 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) |
||
| 1466 | 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1467 | 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) |
||
| 1468 | 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI |
||
| 1469 | 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; |
||
| 1470 | 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1471 | 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1472 | 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); |
||
| 1473 | 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 1474 | 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1475 | 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1476 | 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1477 | 714:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1478 | 715:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1479 | 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1480 | 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit |
||
| 1481 | 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 1482 | 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure |
||
| 1483 | 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. |
||
| 1484 | 721:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1485 | 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). |
||
| 1486 | 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set |
||
| 1487 | 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1488 | 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) |
||
| 1489 | 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1490 | 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||
| 1491 | 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||
| 1492 | 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI |
||
| 1493 | 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; |
||
| 1494 | 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1495 | 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); |
||
| 1496 | 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1497 | 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1498 | 735:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1499 | 736:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1500 | 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 19 | mjames | 1501 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 26 |
| 16 | mjames | 1502 | |
| 1503 | |||
| 1504 | 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1505 | 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) |
||
| 1506 | 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 1507 | 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. |
||
| 1508 | 742:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1509 | 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu |
||
| 1510 | 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set |
||
| 1511 | 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1512 | 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) |
||
| 1513 | 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1514 | 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) |
||
| 1515 | 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI |
||
| 1516 | 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; |
||
| 1517 | 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1518 | 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); |
||
| 1519 | 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1520 | 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1521 | 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1522 | 756:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1523 | 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
||
| 1524 | 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ |
||
| 1525 | 759:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1526 | 760:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1527 | 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1528 | 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR |
||
| 1529 | 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. |
||
| 1530 | 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value |
||
| 1531 | 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1532 | 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) |
||
| 1533 | 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1534 | 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||
| 1535 | 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
||
| 1536 | 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) |
||
| 1537 | 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed |
||
| 1538 | 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) |
||
| 1539 | 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ |
||
| 1540 | 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); |
||
| 1541 | 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1542 | 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1543 | 777:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1544 | 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); |
||
| 1545 | 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 1546 | 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1547 | 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1548 | 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); |
||
| 1549 | 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1550 | 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1551 | 785:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1552 | 786:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1553 | 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1554 | 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR |
||
| 1555 | 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. |
||
| 1556 | 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set |
||
| 1557 | 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1558 | 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) |
||
| 1559 | 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1560 | 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||
| 19 | mjames | 1561 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 27 |
| 16 | mjames | 1562 | |
| 1563 | |||
| 1564 | 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
||
| 1565 | 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) |
||
| 1566 | 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed |
||
| 1567 | 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) |
||
| 1568 | 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ |
||
| 1569 | 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); |
||
| 1570 | 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1571 | 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); |
||
| 1572 | 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1573 | 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1574 | 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; |
||
| 1575 | 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1576 | 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1577 | 808:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1578 | 809:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1579 | 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ |
||
| 1580 | 811:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1581 | 812:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1582 | 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ |
||
| 1583 | 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface |
||
| 1584 | 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions |
||
| 1585 | 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ |
||
| 1586 | 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1587 | 818:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1588 | 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. |
||
| 1589 | 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" |
||
| 1590 | 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ |
||
| 1591 | 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) |
||
| 1592 | 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) |
||
| 1593 | 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) |
||
| 1594 | 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) |
||
| 1595 | 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1596 | 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) |
||
| 1597 | 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) |
||
| 1598 | 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) |
||
| 1599 | 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1600 | 831:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1601 | 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1602 | 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation |
||
| 1603 | 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. |
||
| 1604 | 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1605 | 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") |
||
| 1606 | 837:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1607 | 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1608 | 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt |
||
| 1609 | 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o |
||
| 1610 | 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1611 | 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") |
||
| 1612 | 843:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1613 | 844:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1614 | 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1615 | 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event |
||
| 1616 | 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter |
||
| 1617 | 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. |
||
| 1618 | 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1619 | 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") |
||
| 1620 | 851:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 19 | mjames | 1621 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 28 |
| 16 | mjames | 1622 | |
| 1623 | |||
| 1624 | 852:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1625 | 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1626 | 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event |
||
| 1627 | 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
||
| 1628 | 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1629 | 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") |
||
| 1630 | 858:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1631 | 859:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1632 | 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1633 | 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier |
||
| 1634 | 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, |
||
| 1635 | 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, |
||
| 1636 | 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. |
||
| 1637 | 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1638 | 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) |
||
| 1639 | 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1640 | 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); |
||
| 1641 | 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1642 | 870:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1643 | 871:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1644 | 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1645 | 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier |
||
| 1646 | 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. |
||
| 1647 | 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. |
||
| 1648 | 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1649 | 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) |
||
| 1650 | 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1651 | 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); |
||
| 1652 | 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1653 | 881:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1654 | 882:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1655 | 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1656 | 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier |
||
| 1657 | 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before |
||
| 1658 | 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. |
||
| 1659 | 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1660 | 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) |
||
| 1661 | 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1662 | 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); |
||
| 1663 | 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1664 | 892:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1665 | 893:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1666 | 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1667 | 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) |
||
| 1668 | 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 |
||
| 1669 | 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse |
||
| 1670 | 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value |
||
| 1671 | 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1672 | 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) |
||
| 1673 | 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1674 | 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) |
||
| 1675 | 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); |
||
| 1676 | 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1677 | 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1678 | 906:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1679 | 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
||
| 1680 | 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 19 | mjames | 1681 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 29 |
| 16 | mjames | 1682 | |
| 1683 | |||
| 1684 | 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1685 | 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1686 | 911:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1687 | 912:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1688 | 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1689 | 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) |
||
| 1690 | 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes |
||
| 1691 | 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse |
||
| 1692 | 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value |
||
| 1693 | 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1694 | 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) |
||
| 1695 | 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1696 | 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1697 | 922:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1698 | 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
||
| 1699 | 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 1700 | 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1701 | 926:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1702 | 927:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1703 | 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1704 | 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) |
||
| 1705 | 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam |
||
| 1706 | 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse |
||
| 1707 | 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value |
||
| 1708 | 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1709 | 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) |
||
| 1710 | 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1711 | 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
||
| 1712 | 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); |
||
| 1713 | 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1714 | 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; |
||
| 1715 | 940:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1716 | 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
||
| 1717 | 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 1718 | 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1719 | 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1720 | 945:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1721 | 946:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1722 | 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1723 | 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) |
||
| 1724 | 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v |
||
| 1725 | 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate |
||
| 1726 | 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate |
||
| 1727 | 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value |
||
| 1728 | 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1729 | 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) |
||
| 1730 | 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1731 | 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; |
||
| 1732 | 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) |
||
| 1733 | 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1734 | 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; |
||
| 1735 | 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1736 | 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); |
||
| 1737 | 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1738 | 963:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1739 | 964:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1740 | 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 19 | mjames | 1741 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 30 |
| 16 | mjames | 1742 | |
| 1743 | |||
| 1744 | 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint |
||
| 1745 | 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. |
||
| 1746 | 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula |
||
| 1747 | 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. |
||
| 1748 | 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break |
||
| 1749 | 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1750 | 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) |
||
| 1751 | 973:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1752 | 974:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1753 | 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 1754 | 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value |
||
| 1755 | 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. |
||
| 1756 | 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse |
||
| 1757 | 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value |
||
| 1758 | 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 1759 | 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) |
||
| 1760 | 317 .loc 2 981 31 view .LVU52 |
||
| 1761 | 318 .LBB7: |
||
| 1762 | 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1763 | 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 1764 | 319 .loc 2 983 3 view .LVU53 |
||
| 1765 | 984:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1766 | 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||
| 1767 | 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
||
| 1768 | 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
||
| 1769 | 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
||
| 1770 | 320 .loc 2 988 4 view .LVU54 |
||
| 1771 | 321 .syntax unified |
||
| 1772 | 322 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 |
||
| 1773 | 323 0000 90FAA0F0 rbit r0, r0 |
||
| 1774 | 324 @ 0 "" 2 |
||
| 1775 | 325 .LVL2: |
||
| 1776 | 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1777 | 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ |
||
| 1778 | 991:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1779 | 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ |
||
| 1780 | 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) |
||
| 1781 | 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1782 | 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; |
||
| 1783 | 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; |
||
| 1784 | 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; |
||
| 1785 | 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 1786 | 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ |
||
| 1787 | 1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 1788 | 1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 1789 | 326 .loc 2 1001 3 view .LVU55 |
||
| 1790 | 327 .loc 2 1001 3 is_stmt 0 view .LVU56 |
||
| 1791 | 328 .thumb |
||
| 1792 | 329 .syntax unified |
||
| 1793 | 330 .LBE7: |
||
| 1794 | 331 .LBE6: |
||
| 1795 | 332 .loc 1 387 22 view .LVU57 |
||
| 1796 | 333 0004 B0FA80F0 clz r0, r0 |
||
| 1797 | 334 0008 024B ldr r3, .L25 |
||
| 1798 | 335 000a 0344 add r3, r3, r0 |
||
| 1799 | 336 000c 9B00 lsls r3, r3, #2 |
||
| 1800 | 337 .loc 1 387 46 view .LVU58 |
||
| 19 | mjames | 1801 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 31 |
| 16 | mjames | 1802 | |
| 1803 | |||
| 1804 | 338 000e 0122 movs r2, #1 |
||
| 1805 | 339 0010 1A60 str r2, [r3] |
||
| 1806 | 388:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 1807 | 340 .loc 1 388 1 view .LVU59 |
||
| 1808 | 341 0012 7047 bx lr |
||
| 1809 | 342 .L26: |
||
| 1810 | 343 .align 2 |
||
| 1811 | 344 .L25: |
||
| 1812 | 345 0014 20808310 .word 277053472 |
||
| 1813 | 346 .cfi_endproc |
||
| 1814 | 347 .LFE72: |
||
| 1815 | 349 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits |
||
| 1816 | 350 .align 1 |
||
| 1817 | 351 .global HAL_PWR_DisableWakeUpPin |
||
| 1818 | 352 .syntax unified |
||
| 1819 | 353 .thumb |
||
| 1820 | 354 .thumb_func |
||
| 1821 | 355 .fpu softvfp |
||
| 1822 | 357 HAL_PWR_DisableWakeUpPin: |
||
| 1823 | 358 .LVL3: |
||
| 1824 | 359 .LFB73: |
||
| 1825 | 389:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 1826 | 390:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 1827 | 391:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality. |
||
| 1828 | 392:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. |
||
| 1829 | 393:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values: |
||
| 1830 | 394:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 |
||
| 1831 | 395:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 1832 | 396:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 1833 | 397:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
||
| 1834 | 398:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 1835 | 360 .loc 1 398 1 is_stmt 1 view -0 |
||
| 1836 | 361 .cfi_startproc |
||
| 1837 | 362 @ args = 0, pretend = 0, frame = 0 |
||
| 1838 | 363 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 1839 | 364 @ link register save eliminated. |
||
| 1840 | 399:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameter */ |
||
| 1841 | 400:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
||
| 1842 | 365 .loc 1 400 3 view .LVU61 |
||
| 1843 | 401:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Disable the EWUPx pin */ |
||
| 1844 | 402:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; |
||
| 1845 | 366 .loc 1 402 3 view .LVU62 |
||
| 1846 | 367 .LBB8: |
||
| 1847 | 368 .LBI8: |
||
| 1848 | 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 1849 | 369 .loc 2 981 31 view .LVU63 |
||
| 1850 | 370 .LBB9: |
||
| 1851 | 983:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 1852 | 371 .loc 2 983 3 view .LVU64 |
||
| 1853 | 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 1854 | 372 .loc 2 988 4 view .LVU65 |
||
| 1855 | 373 .syntax unified |
||
| 1856 | 374 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 |
||
| 1857 | 375 0000 90FAA0F0 rbit r0, r0 |
||
| 1858 | 376 @ 0 "" 2 |
||
| 1859 | 377 .LVL4: |
||
| 1860 | 378 .loc 2 1001 3 view .LVU66 |
||
| 19 | mjames | 1861 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 32 |
| 16 | mjames | 1862 | |
| 1863 | |||
| 1864 | 379 .loc 2 1001 3 is_stmt 0 view .LVU67 |
||
| 1865 | 380 .thumb |
||
| 1866 | 381 .syntax unified |
||
| 1867 | 382 .LBE9: |
||
| 1868 | 383 .LBE8: |
||
| 1869 | 384 .loc 1 402 22 view .LVU68 |
||
| 1870 | 385 0004 B0FA80F0 clz r0, r0 |
||
| 1871 | 386 0008 024B ldr r3, .L28 |
||
| 1872 | 387 000a 0344 add r3, r3, r0 |
||
| 1873 | 388 000c 9B00 lsls r3, r3, #2 |
||
| 1874 | 389 .loc 1 402 46 view .LVU69 |
||
| 1875 | 390 000e 0022 movs r2, #0 |
||
| 1876 | 391 0010 1A60 str r2, [r3] |
||
| 1877 | 403:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 1878 | 392 .loc 1 403 1 view .LVU70 |
||
| 1879 | 393 0012 7047 bx lr |
||
| 1880 | 394 .L29: |
||
| 1881 | 395 .align 2 |
||
| 1882 | 396 .L28: |
||
| 1883 | 397 0014 20808310 .word 277053472 |
||
| 1884 | 398 .cfi_endproc |
||
| 1885 | 399 .LFE73: |
||
| 1886 | 401 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits |
||
| 1887 | 402 .align 1 |
||
| 1888 | 403 .global HAL_PWR_EnterSLEEPMode |
||
| 1889 | 404 .syntax unified |
||
| 1890 | 405 .thumb |
||
| 1891 | 406 .thumb_func |
||
| 1892 | 407 .fpu softvfp |
||
| 1893 | 409 HAL_PWR_EnterSLEEPMode: |
||
| 1894 | 410 .LVL5: |
||
| 1895 | 411 .LFB74: |
||
| 1896 | 404:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 1897 | 405:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 1898 | 406:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enters Sleep mode. |
||
| 1899 | 407:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
||
| 1900 | 408:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability f |
||
| 1901 | 409:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. |
||
| 1902 | 410:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as |
||
| 1903 | 411:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * the interrupt wake up source. |
||
| 1904 | 412:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values: |
||
| 1905 | 413:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
||
| 1906 | 414:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
||
| 1907 | 415:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 1908 | 416:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 1909 | 417:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
||
| 1910 | 418:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 1911 | 412 .loc 1 418 1 is_stmt 1 view -0 |
||
| 1912 | 413 .cfi_startproc |
||
| 1913 | 414 @ args = 0, pretend = 0, frame = 0 |
||
| 1914 | 415 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 1915 | 416 @ link register save eliminated. |
||
| 1916 | 419:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameters */ |
||
| 1917 | 420:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* No check on Regulator because parameter not used in SLEEP mode */ |
||
| 1918 | 421:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Prevent unused argument(s) compilation warning */ |
||
| 1919 | 422:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** UNUSED(Regulator); |
||
| 1920 | 417 .loc 1 422 3 view .LVU72 |
||
| 19 | mjames | 1921 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 33 |
| 16 | mjames | 1922 | |
| 1923 | |||
| 1924 | 423:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 1925 | 424:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
||
| 1926 | 418 .loc 1 424 3 view .LVU73 |
||
| 1927 | 425:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 1928 | 426:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
||
| 1929 | 427:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
||
| 1930 | 419 .loc 1 427 3 view .LVU74 |
||
| 1931 | 420 0000 064A ldr r2, .L34 |
||
| 1932 | 421 0002 1369 ldr r3, [r2, #16] |
||
| 1933 | 422 0004 23F00403 bic r3, r3, #4 |
||
| 1934 | 423 0008 1361 str r3, [r2, #16] |
||
| 1935 | 428:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 1936 | 429:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ |
||
| 1937 | 430:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
||
| 1938 | 424 .loc 1 430 3 view .LVU75 |
||
| 1939 | 425 .loc 1 430 5 is_stmt 0 view .LVU76 |
||
| 1940 | 426 000a 0129 cmp r1, #1 |
||
| 1941 | 427 000c 03D0 beq .L33 |
||
| 1942 | 431:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 1943 | 432:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Interrupt */ |
||
| 1944 | 433:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFI(); |
||
| 1945 | 434:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 1946 | 435:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** else |
||
| 1947 | 436:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 1948 | 437:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Event */ |
||
| 1949 | 438:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __SEV(); |
||
| 1950 | 428 .loc 1 438 5 is_stmt 1 view .LVU77 |
||
| 1951 | 429 .syntax unified |
||
| 1952 | 430 @ 438 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1 |
||
| 1953 | 431 000e 40BF sev |
||
| 1954 | 432 @ 0 "" 2 |
||
| 1955 | 439:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFE(); |
||
| 1956 | 433 .loc 1 439 5 view .LVU78 |
||
| 1957 | 434 @ 439 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1 |
||
| 1958 | 435 0010 20BF wfe |
||
| 1959 | 436 @ 0 "" 2 |
||
| 1960 | 440:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFE(); |
||
| 1961 | 437 .loc 1 440 5 view .LVU79 |
||
| 1962 | 438 @ 440 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1 |
||
| 1963 | 439 0012 20BF wfe |
||
| 1964 | 440 @ 0 "" 2 |
||
| 1965 | 441:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 1966 | 442:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 1967 | 441 .loc 1 442 1 is_stmt 0 view .LVU80 |
||
| 1968 | 442 .thumb |
||
| 1969 | 443 .syntax unified |
||
| 1970 | 444 0014 7047 bx lr |
||
| 1971 | 445 .L33: |
||
| 1972 | 433:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 1973 | 446 .loc 1 433 5 is_stmt 1 view .LVU81 |
||
| 1974 | 447 .syntax unified |
||
| 1975 | 448 @ 433 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1 |
||
| 1976 | 449 0016 30BF wfi |
||
| 1977 | 450 @ 0 "" 2 |
||
| 1978 | 451 .thumb |
||
| 1979 | 452 .syntax unified |
||
| 1980 | 453 0018 7047 bx lr |
||
| 19 | mjames | 1981 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 34 |
| 16 | mjames | 1982 | |
| 1983 | |||
| 1984 | 454 .L35: |
||
| 1985 | 455 001a 00BF .align 2 |
||
| 1986 | 456 .L34: |
||
| 1987 | 457 001c 00ED00E0 .word -536810240 |
||
| 1988 | 458 .cfi_endproc |
||
| 1989 | 459 .LFE74: |
||
| 1990 | 461 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits |
||
| 1991 | 462 .align 1 |
||
| 1992 | 463 .global HAL_PWR_EnterSTOPMode |
||
| 1993 | 464 .syntax unified |
||
| 1994 | 465 .thumb |
||
| 1995 | 466 .thumb_func |
||
| 1996 | 467 .fpu softvfp |
||
| 1997 | 469 HAL_PWR_EnterSTOPMode: |
||
| 1998 | 470 .LVL6: |
||
| 1999 | 471 .LFB75: |
||
| 2000 | 443:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2001 | 444:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 2002 | 445:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enters Stop mode. |
||
| 2003 | 446:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. |
||
| 2004 | 447:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note When exiting Stop mode by using an interrupt or a wakeup event, |
||
| 2005 | 448:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * HSI RC oscillator is selected as system clock. |
||
| 2006 | 449:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional |
||
| 2007 | 450:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode. |
||
| 2008 | 451:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption |
||
| 2009 | 452:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * is higher although the startup time is reduced. |
||
| 2010 | 453:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in Stop mode. |
||
| 2011 | 454:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values: |
||
| 2012 | 455:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON |
||
| 2013 | 456:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON |
||
| 2014 | 457:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. |
||
| 2015 | 458:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * This parameter can be one of the following values: |
||
| 2016 | 459:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction |
||
| 2017 | 460:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction |
||
| 2018 | 461:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 2019 | 462:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 2020 | 463:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
||
| 2021 | 464:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2022 | 472 .loc 1 464 1 view -0 |
||
| 2023 | 473 .cfi_startproc |
||
| 2024 | 474 @ args = 0, pretend = 0, frame = 0 |
||
| 2025 | 475 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2026 | 476 .loc 1 464 1 is_stmt 0 view .LVU83 |
||
| 2027 | 477 0000 08B5 push {r3, lr} |
||
| 2028 | 478 .LCFI0: |
||
| 2029 | 479 .cfi_def_cfa_offset 8 |
||
| 2030 | 480 .cfi_offset 3, -8 |
||
| 2031 | 481 .cfi_offset 14, -4 |
||
| 2032 | 465:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check the parameters */ |
||
| 2033 | 466:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); |
||
| 2034 | 482 .loc 1 466 3 is_stmt 1 view .LVU84 |
||
| 2035 | 467:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
||
| 2036 | 483 .loc 1 467 3 view .LVU85 |
||
| 2037 | 468:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2038 | 469:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ |
||
| 2039 | 470:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_PDDS); |
||
| 2040 | 484 .loc 1 470 3 view .LVU86 |
||
| 19 | mjames | 2041 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 35 |
| 16 | mjames | 2042 | |
| 2043 | |||
| 2044 | 485 0002 0F4A ldr r2, .L40 |
||
| 2045 | 486 0004 1368 ldr r3, [r2] |
||
| 2046 | 487 0006 23F00203 bic r3, r3, #2 |
||
| 2047 | 488 000a 1360 str r3, [r2] |
||
| 2048 | 471:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2049 | 472:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator p |
||
| 2050 | 473:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); |
||
| 2051 | 489 .loc 1 473 3 view .LVU87 |
||
| 2052 | 490 000c 1368 ldr r3, [r2] |
||
| 2053 | 491 000e 23F00103 bic r3, r3, #1 |
||
| 2054 | 492 0012 1843 orrs r0, r0, r3 |
||
| 2055 | 493 .LVL7: |
||
| 2056 | 494 .loc 1 473 3 is_stmt 0 view .LVU88 |
||
| 2057 | 495 0014 1060 str r0, [r2] |
||
| 2058 | 474:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2059 | 475:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ |
||
| 2060 | 476:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
||
| 2061 | 496 .loc 1 476 3 is_stmt 1 view .LVU89 |
||
| 2062 | 497 0016 0B4A ldr r2, .L40+4 |
||
| 2063 | 498 0018 1369 ldr r3, [r2, #16] |
||
| 2064 | 499 001a 43F00403 orr r3, r3, #4 |
||
| 2065 | 500 001e 1361 str r3, [r2, #16] |
||
| 2066 | 477:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2067 | 478:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/ |
||
| 2068 | 479:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI) |
||
| 2069 | 501 .loc 1 479 3 view .LVU90 |
||
| 2070 | 502 .loc 1 479 5 is_stmt 0 view .LVU91 |
||
| 2071 | 503 0020 0129 cmp r1, #1 |
||
| 2072 | 504 0022 06D1 bne .L37 |
||
| 2073 | 480:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2074 | 481:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Interrupt */ |
||
| 2075 | 482:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFI(); |
||
| 2076 | 505 .loc 1 482 5 is_stmt 1 view .LVU92 |
||
| 2077 | 506 .syntax unified |
||
| 2078 | 507 @ 482 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1 |
||
| 2079 | 508 0024 30BF wfi |
||
| 2080 | 509 @ 0 "" 2 |
||
| 2081 | 510 .LVL8: |
||
| 2082 | 511 .thumb |
||
| 2083 | 512 .syntax unified |
||
| 2084 | 513 .L38: |
||
| 2085 | 483:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2086 | 484:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** else |
||
| 2087 | 485:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2088 | 486:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Event */ |
||
| 2089 | 487:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __SEV(); |
||
| 2090 | 488:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** PWR_OverloadWfe(); /* WFE redefine locally */ |
||
| 2091 | 489:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** PWR_OverloadWfe(); /* WFE redefine locally */ |
||
| 2092 | 490:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2093 | 491:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
||
| 2094 | 492:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
||
| 2095 | 514 .loc 1 492 3 view .LVU93 |
||
| 2096 | 515 0026 074A ldr r2, .L40+4 |
||
| 2097 | 516 0028 1369 ldr r3, [r2, #16] |
||
| 2098 | 517 002a 23F00403 bic r3, r3, #4 |
||
| 2099 | 518 002e 1361 str r3, [r2, #16] |
||
| 2100 | 493:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 19 | mjames | 2101 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 36 |
| 16 | mjames | 2102 | |
| 2103 | |||
| 2104 | 519 .loc 1 493 1 is_stmt 0 view .LVU94 |
||
| 2105 | 520 0030 08BD pop {r3, pc} |
||
| 2106 | 521 .LVL9: |
||
| 2107 | 522 .L37: |
||
| 2108 | 487:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** PWR_OverloadWfe(); /* WFE redefine locally */ |
||
| 2109 | 523 .loc 1 487 5 is_stmt 1 view .LVU95 |
||
| 2110 | 524 .syntax unified |
||
| 2111 | 525 @ 487 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1 |
||
| 2112 | 526 0032 40BF sev |
||
| 2113 | 527 @ 0 "" 2 |
||
| 2114 | 488:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** PWR_OverloadWfe(); /* WFE redefine locally */ |
||
| 2115 | 528 .loc 1 488 5 view .LVU96 |
||
| 2116 | 529 .thumb |
||
| 2117 | 530 .syntax unified |
||
| 2118 | 531 0034 FFF7FEFF bl PWR_OverloadWfe |
||
| 2119 | 532 .LVL10: |
||
| 2120 | 489:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2121 | 533 .loc 1 489 5 view .LVU97 |
||
| 2122 | 534 0038 FFF7FEFF bl PWR_OverloadWfe |
||
| 2123 | 535 .LVL11: |
||
| 2124 | 536 003c F3E7 b .L38 |
||
| 2125 | 537 .L41: |
||
| 2126 | 538 003e 00BF .align 2 |
||
| 2127 | 539 .L40: |
||
| 2128 | 540 0040 00700040 .word 1073770496 |
||
| 2129 | 541 0044 00ED00E0 .word -536810240 |
||
| 2130 | 542 .cfi_endproc |
||
| 2131 | 543 .LFE75: |
||
| 2132 | 545 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits |
||
| 2133 | 546 .align 1 |
||
| 2134 | 547 .global HAL_PWR_EnterSTANDBYMode |
||
| 2135 | 548 .syntax unified |
||
| 2136 | 549 .thumb |
||
| 2137 | 550 .thumb_func |
||
| 2138 | 551 .fpu softvfp |
||
| 2139 | 553 HAL_PWR_EnterSTANDBYMode: |
||
| 2140 | 554 .LFB76: |
||
| 2141 | 494:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2142 | 495:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 2143 | 496:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enters Standby mode. |
||
| 2144 | 497:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for: |
||
| 2145 | 498:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * - Reset pad (still available) |
||
| 2146 | 499:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * - TAMPER pin if configured for tamper or calibration out. |
||
| 2147 | 500:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * - WKUP pin (PA0) if enabled. |
||
| 2148 | 501:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 2149 | 502:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 2150 | 503:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) |
||
| 2151 | 504:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2152 | 555 .loc 1 504 1 view -0 |
||
| 2153 | 556 .cfi_startproc |
||
| 2154 | 557 @ args = 0, pretend = 0, frame = 0 |
||
| 2155 | 558 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2156 | 559 @ link register save eliminated. |
||
| 2157 | 505:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Select Standby mode */ |
||
| 2158 | 506:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PDDS); |
||
| 2159 | 560 .loc 1 506 3 view .LVU99 |
||
| 2160 | 561 0000 054A ldr r2, .L43 |
||
| 19 | mjames | 2161 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 37 |
| 16 | mjames | 2162 | |
| 2163 | |||
| 2164 | 562 0002 1368 ldr r3, [r2] |
||
| 2165 | 563 0004 43F00203 orr r3, r3, #2 |
||
| 2166 | 564 0008 1360 str r3, [r2] |
||
| 2167 | 507:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2168 | 508:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ |
||
| 2169 | 509:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
||
| 2170 | 565 .loc 1 509 3 view .LVU100 |
||
| 2171 | 566 000a 044A ldr r2, .L43+4 |
||
| 2172 | 567 000c 1369 ldr r3, [r2, #16] |
||
| 2173 | 568 000e 43F00403 orr r3, r3, #4 |
||
| 2174 | 569 0012 1361 str r3, [r2, #16] |
||
| 2175 | 510:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2176 | 511:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ |
||
| 2177 | 512:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #if defined ( __CC_ARM) |
||
| 2178 | 513:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __force_stores(); |
||
| 2179 | 514:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #endif |
||
| 2180 | 515:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Request Wait For Interrupt */ |
||
| 2181 | 516:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __WFI(); |
||
| 2182 | 570 .loc 1 516 3 view .LVU101 |
||
| 2183 | 571 .syntax unified |
||
| 2184 | 572 @ 516 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c" 1 |
||
| 2185 | 573 0014 30BF wfi |
||
| 2186 | 574 @ 0 "" 2 |
||
| 2187 | 517:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2188 | 575 .loc 1 517 1 is_stmt 0 view .LVU102 |
||
| 2189 | 576 .thumb |
||
| 2190 | 577 .syntax unified |
||
| 2191 | 578 0016 7047 bx lr |
||
| 2192 | 579 .L44: |
||
| 2193 | 580 .align 2 |
||
| 2194 | 581 .L43: |
||
| 2195 | 582 0018 00700040 .word 1073770496 |
||
| 2196 | 583 001c 00ED00E0 .word -536810240 |
||
| 2197 | 584 .cfi_endproc |
||
| 2198 | 585 .LFE76: |
||
| 2199 | 587 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits |
||
| 2200 | 588 .align 1 |
||
| 2201 | 589 .global HAL_PWR_EnableSleepOnExit |
||
| 2202 | 590 .syntax unified |
||
| 2203 | 591 .thumb |
||
| 2204 | 592 .thumb_func |
||
| 2205 | 593 .fpu softvfp |
||
| 2206 | 595 HAL_PWR_EnableSleepOnExit: |
||
| 2207 | 596 .LFB77: |
||
| 2208 | 518:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2209 | 519:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2210 | 520:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 2211 | 521:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. |
||
| 2212 | 522:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
||
| 2213 | 523:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. |
||
| 2214 | 524:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on |
||
| 2215 | 525:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * interruptions handling. |
||
| 2216 | 526:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 2217 | 527:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 2218 | 528:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) |
||
| 2219 | 529:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2220 | 597 .loc 1 529 1 is_stmt 1 view -0 |
||
| 19 | mjames | 2221 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 38 |
| 16 | mjames | 2222 | |
| 2223 | |||
| 2224 | 598 .cfi_startproc |
||
| 2225 | 599 @ args = 0, pretend = 0, frame = 0 |
||
| 2226 | 600 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2227 | 601 @ link register save eliminated. |
||
| 2228 | 530:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
||
| 2229 | 531:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
||
| 2230 | 602 .loc 1 531 3 view .LVU104 |
||
| 2231 | 603 0000 024A ldr r2, .L46 |
||
| 2232 | 604 0002 1369 ldr r3, [r2, #16] |
||
| 2233 | 605 0004 43F00203 orr r3, r3, #2 |
||
| 2234 | 606 0008 1361 str r3, [r2, #16] |
||
| 2235 | 532:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2236 | 607 .loc 1 532 1 is_stmt 0 view .LVU105 |
||
| 2237 | 608 000a 7047 bx lr |
||
| 2238 | 609 .L47: |
||
| 2239 | 610 .align 2 |
||
| 2240 | 611 .L46: |
||
| 2241 | 612 000c 00ED00E0 .word -536810240 |
||
| 2242 | 613 .cfi_endproc |
||
| 2243 | 614 .LFE77: |
||
| 2244 | 616 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits |
||
| 2245 | 617 .align 1 |
||
| 2246 | 618 .global HAL_PWR_DisableSleepOnExit |
||
| 2247 | 619 .syntax unified |
||
| 2248 | 620 .thumb |
||
| 2249 | 621 .thumb_func |
||
| 2250 | 622 .fpu softvfp |
||
| 2251 | 624 HAL_PWR_DisableSleepOnExit: |
||
| 2252 | 625 .LFB78: |
||
| 2253 | 533:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2254 | 534:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2255 | 535:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 2256 | 536:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. |
||
| 2257 | 537:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
||
| 2258 | 538:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. |
||
| 2259 | 539:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 2260 | 540:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 2261 | 541:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) |
||
| 2262 | 542:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2263 | 626 .loc 1 542 1 is_stmt 1 view -0 |
||
| 2264 | 627 .cfi_startproc |
||
| 2265 | 628 @ args = 0, pretend = 0, frame = 0 |
||
| 2266 | 629 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2267 | 630 @ link register save eliminated. |
||
| 2268 | 543:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
||
| 2269 | 544:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
||
| 2270 | 631 .loc 1 544 3 view .LVU107 |
||
| 2271 | 632 0000 024A ldr r2, .L49 |
||
| 2272 | 633 0002 1369 ldr r3, [r2, #16] |
||
| 2273 | 634 0004 23F00203 bic r3, r3, #2 |
||
| 2274 | 635 0008 1361 str r3, [r2, #16] |
||
| 2275 | 545:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2276 | 636 .loc 1 545 1 is_stmt 0 view .LVU108 |
||
| 2277 | 637 000a 7047 bx lr |
||
| 2278 | 638 .L50: |
||
| 2279 | 639 .align 2 |
||
| 2280 | 640 .L49: |
||
| 19 | mjames | 2281 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 39 |
| 16 | mjames | 2282 | |
| 2283 | |||
| 2284 | 641 000c 00ED00E0 .word -536810240 |
||
| 2285 | 642 .cfi_endproc |
||
| 2286 | 643 .LFE78: |
||
| 2287 | 645 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits |
||
| 2288 | 646 .align 1 |
||
| 2289 | 647 .global HAL_PWR_EnableSEVOnPend |
||
| 2290 | 648 .syntax unified |
||
| 2291 | 649 .thumb |
||
| 2292 | 650 .thumb_func |
||
| 2293 | 651 .fpu softvfp |
||
| 2294 | 653 HAL_PWR_EnableSEVOnPend: |
||
| 2295 | 654 .LFB79: |
||
| 2296 | 546:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2297 | 547:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2298 | 548:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 2299 | 549:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Enables CORTEX M3 SEVONPEND bit. |
||
| 2300 | 550:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes |
||
| 2301 | 551:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. |
||
| 2302 | 552:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 2303 | 553:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 2304 | 554:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) |
||
| 2305 | 555:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2306 | 655 .loc 1 555 1 is_stmt 1 view -0 |
||
| 2307 | 656 .cfi_startproc |
||
| 2308 | 657 @ args = 0, pretend = 0, frame = 0 |
||
| 2309 | 658 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2310 | 659 @ link register save eliminated. |
||
| 2311 | 556:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ |
||
| 2312 | 557:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
||
| 2313 | 660 .loc 1 557 3 view .LVU110 |
||
| 2314 | 661 0000 024A ldr r2, .L52 |
||
| 2315 | 662 0002 1369 ldr r3, [r2, #16] |
||
| 2316 | 663 0004 43F01003 orr r3, r3, #16 |
||
| 2317 | 664 0008 1361 str r3, [r2, #16] |
||
| 2318 | 558:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2319 | 665 .loc 1 558 1 is_stmt 0 view .LVU111 |
||
| 2320 | 666 000a 7047 bx lr |
||
| 2321 | 667 .L53: |
||
| 2322 | 668 .align 2 |
||
| 2323 | 669 .L52: |
||
| 2324 | 670 000c 00ED00E0 .word -536810240 |
||
| 2325 | 671 .cfi_endproc |
||
| 2326 | 672 .LFE79: |
||
| 2327 | 674 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits |
||
| 2328 | 675 .align 1 |
||
| 2329 | 676 .global HAL_PWR_DisableSEVOnPend |
||
| 2330 | 677 .syntax unified |
||
| 2331 | 678 .thumb |
||
| 2332 | 679 .thumb_func |
||
| 2333 | 680 .fpu softvfp |
||
| 2334 | 682 HAL_PWR_DisableSEVOnPend: |
||
| 2335 | 683 .LFB80: |
||
| 2336 | 559:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2337 | 560:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2338 | 561:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 2339 | 562:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief Disables CORTEX M3 SEVONPEND bit. |
||
| 2340 | 563:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes |
||
| 19 | mjames | 2341 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 40 |
| 16 | mjames | 2342 | |
| 2343 | |||
| 2344 | 564:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. |
||
| 2345 | 565:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 2346 | 566:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 2347 | 567:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) |
||
| 2348 | 568:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2349 | 684 .loc 1 568 1 is_stmt 1 view -0 |
||
| 2350 | 685 .cfi_startproc |
||
| 2351 | 686 @ args = 0, pretend = 0, frame = 0 |
||
| 2352 | 687 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2353 | 688 @ link register save eliminated. |
||
| 2354 | 569:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ |
||
| 2355 | 570:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
||
| 2356 | 689 .loc 1 570 3 view .LVU113 |
||
| 2357 | 690 0000 024A ldr r2, .L55 |
||
| 2358 | 691 0002 1369 ldr r3, [r2, #16] |
||
| 2359 | 692 0004 23F01003 bic r3, r3, #16 |
||
| 2360 | 693 0008 1361 str r3, [r2, #16] |
||
| 2361 | 571:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2362 | 694 .loc 1 571 1 is_stmt 0 view .LVU114 |
||
| 2363 | 695 000a 7047 bx lr |
||
| 2364 | 696 .L56: |
||
| 2365 | 697 .align 2 |
||
| 2366 | 698 .L55: |
||
| 2367 | 699 000c 00ED00E0 .word -536810240 |
||
| 2368 | 700 .cfi_endproc |
||
| 2369 | 701 .LFE80: |
||
| 2370 | 703 .section .text.HAL_PWR_PVDCallback,"ax",%progbits |
||
| 2371 | 704 .align 1 |
||
| 2372 | 705 .weak HAL_PWR_PVDCallback |
||
| 2373 | 706 .syntax unified |
||
| 2374 | 707 .thumb |
||
| 2375 | 708 .thumb_func |
||
| 2376 | 709 .fpu softvfp |
||
| 2377 | 711 HAL_PWR_PVDCallback: |
||
| 2378 | 712 .LFB82: |
||
| 2379 | 572:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2380 | 573:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2381 | 574:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2382 | 575:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 2383 | 576:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request. |
||
| 2384 | 577:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @note This API should be called under the PVD_IRQHandler(). |
||
| 2385 | 578:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 2386 | 579:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 2387 | 580:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void) |
||
| 2388 | 581:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2389 | 582:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check PWR exti flag */ |
||
| 2390 | 583:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) |
||
| 2391 | 584:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2392 | 585:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ |
||
| 2393 | 586:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** HAL_PWR_PVDCallback(); |
||
| 2394 | 587:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2395 | 588:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Clear PWR Exti pending bit */ |
||
| 2396 | 589:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); |
||
| 2397 | 590:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2398 | 591:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2399 | 592:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2400 | 593:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** |
||
| 19 | mjames | 2401 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 41 |
| 16 | mjames | 2402 | |
| 2403 | |||
| 2404 | 594:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @brief PWR PVD interrupt callback |
||
| 2405 | 595:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** * @retval None |
||
| 2406 | 596:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 2407 | 597:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void) |
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| 2408 | 598:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2409 | 713 .loc 1 598 1 is_stmt 1 view -0 |
||
| 2410 | 714 .cfi_startproc |
||
| 2411 | 715 @ args = 0, pretend = 0, frame = 0 |
||
| 2412 | 716 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2413 | 717 @ link register save eliminated. |
||
| 2414 | 599:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* NOTE : This function Should not be modified, when the callback is needed, |
||
| 2415 | 600:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** the HAL_PWR_PVDCallback could be implemented in the user file |
||
| 2416 | 601:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** */ |
||
| 2417 | 602:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
||
| 2418 | 718 .loc 1 602 1 view .LVU116 |
||
| 2419 | 719 0000 7047 bx lr |
||
| 2420 | 720 .cfi_endproc |
||
| 2421 | 721 .LFE82: |
||
| 2422 | 723 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits |
||
| 2423 | 724 .align 1 |
||
| 2424 | 725 .global HAL_PWR_PVD_IRQHandler |
||
| 2425 | 726 .syntax unified |
||
| 2426 | 727 .thumb |
||
| 2427 | 728 .thumb_func |
||
| 2428 | 729 .fpu softvfp |
||
| 2429 | 731 HAL_PWR_PVD_IRQHandler: |
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| 2430 | 732 .LFB81: |
||
| 2431 | 581:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /* Check PWR exti flag */ |
||
| 2432 | 733 .loc 1 581 1 view -0 |
||
| 2433 | 734 .cfi_startproc |
||
| 2434 | 735 @ args = 0, pretend = 0, frame = 0 |
||
| 2435 | 736 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2436 | 737 0000 08B5 push {r3, lr} |
||
| 2437 | 738 .LCFI1: |
||
| 2438 | 739 .cfi_def_cfa_offset 8 |
||
| 2439 | 740 .cfi_offset 3, -8 |
||
| 2440 | 741 .cfi_offset 14, -4 |
||
| 2441 | 583:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2442 | 742 .loc 1 583 3 view .LVU118 |
||
| 2443 | 583:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2444 | 743 .loc 1 583 6 is_stmt 0 view .LVU119 |
||
| 2445 | 744 0002 064B ldr r3, .L62 |
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| 2446 | 745 0004 5B69 ldr r3, [r3, #20] |
||
| 2447 | 583:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** { |
||
| 2448 | 746 .loc 1 583 5 view .LVU120 |
||
| 2449 | 747 0006 13F4803F tst r3, #65536 |
||
| 2450 | 748 000a 00D1 bne .L61 |
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| 2451 | 749 .L58: |
||
| 2452 | 591:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 2453 | 750 .loc 1 591 1 view .LVU121 |
||
| 2454 | 751 000c 08BD pop {r3, pc} |
||
| 2455 | 752 .L61: |
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| 2456 | 586:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
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| 2457 | 753 .loc 1 586 5 is_stmt 1 view .LVU122 |
||
| 2458 | 754 000e FFF7FEFF bl HAL_PWR_PVDCallback |
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| 2459 | 755 .LVL12: |
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| 2460 | 589:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** } |
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| 19 | mjames | 2461 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 42 |
| 16 | mjames | 2462 | |
| 2463 | |||
| 2464 | 756 .loc 1 589 5 view .LVU123 |
||
| 2465 | 757 0012 024B ldr r3, .L62 |
||
| 2466 | 758 0014 4FF48032 mov r2, #65536 |
||
| 2467 | 759 0018 5A61 str r2, [r3, #20] |
||
| 2468 | 591:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** |
||
| 2469 | 760 .loc 1 591 1 is_stmt 0 view .LVU124 |
||
| 2470 | 761 001a F7E7 b .L58 |
||
| 2471 | 762 .L63: |
||
| 2472 | 763 .align 2 |
||
| 2473 | 764 .L62: |
||
| 2474 | 765 001c 00040140 .word 1073808384 |
||
| 2475 | 766 .cfi_endproc |
||
| 2476 | 767 .LFE81: |
||
| 2477 | 769 .text |
||
| 2478 | 770 .Letext0: |
||
| 2479 | 771 .file 3 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7 |
||
| 2480 | 772 .file 4 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7 |
||
| 2481 | 773 .file 5 "Drivers/CMSIS/Include/core_cm3.h" |
||
| 2482 | 774 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" |
||
| 2483 | 775 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h" |
||
| 2484 | 776 .file 8 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" |
||
| 2485 | 777 .file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h" |
||
| 2486 | 778 .file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h" |
||
| 19 | mjames | 2487 | ARM GAS C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s page 43 |
| 16 | mjames | 2488 | |
| 2489 | |||
| 2490 | DEFINED SYMBOLS |
||
| 2491 | *ABS*:0000000000000000 stm32f1xx_hal_pwr.c |
||
| 19 | mjames | 2492 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:16 .text.PWR_OverloadWfe:0000000000000000 $t |
| 2493 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:23 .text.PWR_OverloadWfe:0000000000000000 PWR_OverloadWfe |
||
| 2494 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:48 .text.HAL_PWR_DeInit:0000000000000000 $t |
||
| 2495 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:55 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit |
||
| 2496 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:76 .text.HAL_PWR_DeInit:0000000000000014 $d |
||
| 2497 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:81 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t |
||
| 2498 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:88 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess |
||
| 2499 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:105 .text.HAL_PWR_EnableBkUpAccess:0000000000000008 $d |
||
| 2500 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:110 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t |
||
| 2501 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:117 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess |
||
| 2502 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:134 .text.HAL_PWR_DisableBkUpAccess:0000000000000008 $d |
||
| 2503 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:139 .text.HAL_PWR_ConfigPVD:0000000000000000 $t |
||
| 2504 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:146 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD |
||
| 2505 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:233 .text.HAL_PWR_ConfigPVD:000000000000007c $d |
||
| 2506 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:239 .text.HAL_PWR_EnablePVD:0000000000000000 $t |
||
| 2507 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:246 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD |
||
| 2508 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:263 .text.HAL_PWR_EnablePVD:0000000000000008 $d |
||
| 2509 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:268 .text.HAL_PWR_DisablePVD:0000000000000000 $t |
||
| 2510 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:275 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD |
||
| 2511 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:292 .text.HAL_PWR_DisablePVD:0000000000000008 $d |
||
| 2512 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:297 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t |
||
| 2513 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:304 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin |
||
| 2514 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:345 .text.HAL_PWR_EnableWakeUpPin:0000000000000014 $d |
||
| 2515 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:350 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t |
||
| 2516 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:357 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin |
||
| 2517 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:397 .text.HAL_PWR_DisableWakeUpPin:0000000000000014 $d |
||
| 2518 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:402 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t |
||
| 2519 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:409 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode |
||
| 2520 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:457 .text.HAL_PWR_EnterSLEEPMode:000000000000001c $d |
||
| 2521 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:462 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t |
||
| 2522 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:469 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode |
||
| 2523 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:540 .text.HAL_PWR_EnterSTOPMode:0000000000000040 $d |
||
| 2524 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:546 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t |
||
| 2525 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:553 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode |
||
| 2526 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:582 .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d |
||
| 2527 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:588 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t |
||
| 2528 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:595 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit |
||
| 2529 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:612 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d |
||
| 2530 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:617 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t |
||
| 2531 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:624 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit |
||
| 2532 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:641 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d |
||
| 2533 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:646 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t |
||
| 2534 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:653 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend |
||
| 2535 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:670 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d |
||
| 2536 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:675 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t |
||
| 2537 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:682 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend |
||
| 2538 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:699 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d |
||
| 2539 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:704 .text.HAL_PWR_PVDCallback:0000000000000000 $t |
||
| 2540 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:711 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback |
||
| 2541 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:724 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t |
||
| 2542 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:731 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler |
||
| 2543 | C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:765 .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d |
||
| 16 | mjames | 2544 | |
| 2545 | NO UNDEFINED SYMBOLS |