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20 mjames 1 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 1
16 mjames 2 
 
3 
 
4 
   1              		.cpu cortex-m3
5 
   2              		.eabi_attribute 20, 1
6 
   3              		.eabi_attribute 21, 1
7 
   4              		.eabi_attribute 23, 3
8 
   5              		.eabi_attribute 24, 1
9 
   6              		.eabi_attribute 25, 1
10 
   7              		.eabi_attribute 26, 1
11 
   8              		.eabi_attribute 30, 1
12 
   9              		.eabi_attribute 34, 1
13 
  10              		.eabi_attribute 18, 4
14 
  11              		.file	"stm32f1xx_hal_msp.c"
15 
  12              		.text
16 
  13              	.Ltext0:
17 
  14              		.cfi_sections	.debug_frame
18 
  15              		.section	.text.HAL_MspInit,"ax",%progbits
19 
  16              		.align	1
20 
  17              		.global	HAL_MspInit
21 
  18              		.arch armv7-m
22 
  19              		.syntax unified
23 
  20              		.thumb
24 
  21              		.thumb_func
25 
  22              		.fpu softvfp
26 
  24              	HAL_MspInit:
27 
  25              	.LFB65:
28 
  26              		.file 1 "Core/Src/stm32f1xx_hal_msp.c"
29 
   1:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Header */
30 
   2:Core/Src/stm32f1xx_hal_msp.c **** /**
31 
   3:Core/Src/stm32f1xx_hal_msp.c ****   ******************************************************************************
32 
   4:Core/Src/stm32f1xx_hal_msp.c ****   * File Name          : stm32f1xx_hal_msp.c
33 
   5:Core/Src/stm32f1xx_hal_msp.c ****   * Description        : This file provides code for the MSP Initialization
34 
   6:Core/Src/stm32f1xx_hal_msp.c ****   *                      and de-Initialization codes.
35 
   7:Core/Src/stm32f1xx_hal_msp.c ****   ******************************************************************************
36 
   8:Core/Src/stm32f1xx_hal_msp.c ****   * @attention
37 
   9:Core/Src/stm32f1xx_hal_msp.c ****   *
38 
  10:Core/Src/stm32f1xx_hal_msp.c ****   * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
39 
  11:Core/Src/stm32f1xx_hal_msp.c ****   * All rights reserved.</center></h2>
40 
  12:Core/Src/stm32f1xx_hal_msp.c ****   *
41 
  13:Core/Src/stm32f1xx_hal_msp.c ****   * This software component is licensed by ST under BSD 3-Clause license,
42 
  14:Core/Src/stm32f1xx_hal_msp.c ****   * the "License"; You may not use this file except in compliance with the
43 
  15:Core/Src/stm32f1xx_hal_msp.c ****   * License. You may obtain a copy of the License at:
44 
  16:Core/Src/stm32f1xx_hal_msp.c ****   *                        opensource.org/licenses/BSD-3-Clause
45 
  17:Core/Src/stm32f1xx_hal_msp.c ****   *
46 
  18:Core/Src/stm32f1xx_hal_msp.c ****   ******************************************************************************
47 
  19:Core/Src/stm32f1xx_hal_msp.c ****   */
48 
  20:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Header */
49 
  21:Core/Src/stm32f1xx_hal_msp.c ****
50 
  22:Core/Src/stm32f1xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
51 
  23:Core/Src/stm32f1xx_hal_msp.c **** #include "main.h"
52 
  24:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Includes */
53 
  25:Core/Src/stm32f1xx_hal_msp.c ****
54 
  26:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Includes */
55 
  27:Core/Src/stm32f1xx_hal_msp.c ****
56 
  28:Core/Src/stm32f1xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
57 
  29:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TD */
58 
  30:Core/Src/stm32f1xx_hal_msp.c ****
59 
  31:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TD */
60 
  32:Core/Src/stm32f1xx_hal_msp.c ****
20 mjames 61 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 2
16 mjames 62 
 
63 
 
64 
  33:Core/Src/stm32f1xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
65 
  34:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Define */
66 
  35:Core/Src/stm32f1xx_hal_msp.c ****
67 
  36:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Define */
68 
  37:Core/Src/stm32f1xx_hal_msp.c ****
69 
  38:Core/Src/stm32f1xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
70 
  39:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Macro */
71 
  40:Core/Src/stm32f1xx_hal_msp.c ****
72 
  41:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Macro */
73 
  42:Core/Src/stm32f1xx_hal_msp.c ****
74 
  43:Core/Src/stm32f1xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
75 
  44:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PV */
76 
  45:Core/Src/stm32f1xx_hal_msp.c ****
77 
  46:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PV */
78 
  47:Core/Src/stm32f1xx_hal_msp.c ****
79 
  48:Core/Src/stm32f1xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
80 
  49:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PFP */
81 
  50:Core/Src/stm32f1xx_hal_msp.c ****
82 
  51:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PFP */
83 
  52:Core/Src/stm32f1xx_hal_msp.c ****
84 
  53:Core/Src/stm32f1xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
85 
  54:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
86 
  55:Core/Src/stm32f1xx_hal_msp.c ****
87 
  56:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
88 
  57:Core/Src/stm32f1xx_hal_msp.c ****
89 
  58:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN 0 */
90 
  59:Core/Src/stm32f1xx_hal_msp.c ****
91 
  60:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END 0 */
92 
  61:Core/Src/stm32f1xx_hal_msp.c **** /**
93 
  62:Core/Src/stm32f1xx_hal_msp.c ****   * Initializes the Global MSP.
94 
  63:Core/Src/stm32f1xx_hal_msp.c ****   */
95 
  64:Core/Src/stm32f1xx_hal_msp.c **** void HAL_MspInit(void)
96 
  65:Core/Src/stm32f1xx_hal_msp.c **** {
97 
  27              		.loc 1 65 1 view -0
98 
  28              		.cfi_startproc
99 
  29              		@ args = 0, pretend = 0, frame = 8
100 
  30              		@ frame_needed = 0, uses_anonymous_args = 0
101 
  31              		@ link register save eliminated.
102 
  32 0000 82B0     		sub	sp, sp, #8
103 
  33              	.LCFI0:
104 
  34              		.cfi_def_cfa_offset 8
105 
  66:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN MspInit 0 */
106 
  67:Core/Src/stm32f1xx_hal_msp.c ****
107 
  68:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END MspInit 0 */
108 
  69:Core/Src/stm32f1xx_hal_msp.c ****
109 
  70:Core/Src/stm32f1xx_hal_msp.c ****   __HAL_RCC_AFIO_CLK_ENABLE();
110 
  35              		.loc 1 70 3 view .LVU1
111 
  36              	.LBB2:
112 
  37              		.loc 1 70 3 view .LVU2
113 
  38              		.loc 1 70 3 view .LVU3
114 
  39 0002 0E4B     		ldr	r3, .L3
115 
  40 0004 9A69     		ldr	r2, [r3, #24]
116 
  41 0006 42F00102 		orr	r2, r2, #1
117 
  42 000a 9A61     		str	r2, [r3, #24]
118 
  43              		.loc 1 70 3 view .LVU4
119 
  44 000c 9A69     		ldr	r2, [r3, #24]
120 
  45 000e 02F00102 		and	r2, r2, #1
20 mjames 121 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 3
16 mjames 122 
 
123 
 
124 
  46 0012 0092     		str	r2, [sp]
125 
  47              		.loc 1 70 3 view .LVU5
126 
  48 0014 009A     		ldr	r2, [sp]
127 
  49              	.LBE2:
128 
  71:Core/Src/stm32f1xx_hal_msp.c ****   __HAL_RCC_PWR_CLK_ENABLE();
129 
  50              		.loc 1 71 3 view .LVU6
130 
  51              	.LBB3:
131 
  52              		.loc 1 71 3 view .LVU7
132 
  53              		.loc 1 71 3 view .LVU8
133 
  54 0016 DA69     		ldr	r2, [r3, #28]
134 
  55 0018 42F08052 		orr	r2, r2, #268435456
135 
  56 001c DA61     		str	r2, [r3, #28]
136 
  57              		.loc 1 71 3 view .LVU9
137 
  58 001e DB69     		ldr	r3, [r3, #28]
138 
  59 0020 03F08053 		and	r3, r3, #268435456
139 
  60 0024 0193     		str	r3, [sp, #4]
140 
  61              		.loc 1 71 3 view .LVU10
141 
  62 0026 019B     		ldr	r3, [sp, #4]
142 
  63              	.LBE3:
143 
  72:Core/Src/stm32f1xx_hal_msp.c ****
144 
  73:Core/Src/stm32f1xx_hal_msp.c ****   /* System interrupt init*/
145 
  74:Core/Src/stm32f1xx_hal_msp.c ****
146 
  75:Core/Src/stm32f1xx_hal_msp.c ****   /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
147 
  76:Core/Src/stm32f1xx_hal_msp.c ****   */
148 
  77:Core/Src/stm32f1xx_hal_msp.c ****   __HAL_AFIO_REMAP_SWJ_NOJTAG();
149 
  64              		.loc 1 77 3 view .LVU11
150 
  65              	.LBB4:
151 
  66              		.loc 1 77 3 view .LVU12
152 
  67 0028 054A     		ldr	r2, .L3+4
153 
  68 002a 5368     		ldr	r3, [r2, #4]
154 
  69              	.LVL0:
155 
  70              		.loc 1 77 3 view .LVU13
156 
  71 002c 23F0E063 		bic	r3, r3, #117440512
157 
  72              	.LVL1:
158 
  73              		.loc 1 77 3 view .LVU14
159 
  74 0030 43F00073 		orr	r3, r3, #33554432
160 
  75              	.LVL2:
161 
  76              		.loc 1 77 3 view .LVU15
162 
  77 0034 5360     		str	r3, [r2, #4]
163 
  78              	.LBE4:
164 
  78:Core/Src/stm32f1xx_hal_msp.c ****
165 
  79:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN MspInit 1 */
166 
  80:Core/Src/stm32f1xx_hal_msp.c ****
167 
  81:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END MspInit 1 */
168 
  82:Core/Src/stm32f1xx_hal_msp.c **** }
169 
  79              		.loc 1 82 1 is_stmt 0 view .LVU16
170 
  80 0036 02B0     		add	sp, sp, #8
171 
  81              	.LCFI1:
172 
  82              		.cfi_def_cfa_offset 0
173 
  83              		@ sp needed
174 
  84 0038 7047     		bx	lr
175 
  85              	.L4:
176 
  86 003a 00BF     		.align	2
177 
  87              	.L3:
178 
  88 003c 00100240 		.word	1073876992
179 
  89 0040 00000140 		.word	1073807360
180 
  90              		.cfi_endproc
20 mjames 181 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 4
16 mjames 182 
 
183 
 
184 
  91              	.LFE65:
185 
  93              		.section	.text.HAL_I2C_MspInit,"ax",%progbits
186 
  94              		.align	1
187 
  95              		.global	HAL_I2C_MspInit
188 
  96              		.syntax unified
189 
  97              		.thumb
190 
  98              		.thumb_func
191 
  99              		.fpu softvfp
192 
 101              	HAL_I2C_MspInit:
193 
 102              	.LVL3:
194 
 103              	.LFB66:
195 
  83:Core/Src/stm32f1xx_hal_msp.c ****
196 
  84:Core/Src/stm32f1xx_hal_msp.c **** /**
197 
  85:Core/Src/stm32f1xx_hal_msp.c **** * @brief I2C MSP Initialization
198 
  86:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
199 
  87:Core/Src/stm32f1xx_hal_msp.c **** * @param hi2c: I2C handle pointer
200 
  88:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
201 
  89:Core/Src/stm32f1xx_hal_msp.c **** */
202 
  90:Core/Src/stm32f1xx_hal_msp.c **** void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
203 
  91:Core/Src/stm32f1xx_hal_msp.c **** {
204 
 104              		.loc 1 91 1 is_stmt 1 view -0
205 
 105              		.cfi_startproc
206 
 106              		@ args = 0, pretend = 0, frame = 32
207 
 107              		@ frame_needed = 0, uses_anonymous_args = 0
208 
 108              		.loc 1 91 1 is_stmt 0 view .LVU18
209 
 109 0000 10B5     		push	{r4, lr}
210 
 110              	.LCFI2:
211 
 111              		.cfi_def_cfa_offset 8
212 
 112              		.cfi_offset 4, -8
213 
 113              		.cfi_offset 14, -4
214 
 114 0002 88B0     		sub	sp, sp, #32
215 
 115              	.LCFI3:
216 
 116              		.cfi_def_cfa_offset 40
217 
  92:Core/Src/stm32f1xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
218 
 117              		.loc 1 92 3 is_stmt 1 view .LVU19
219 
 118              		.loc 1 92 20 is_stmt 0 view .LVU20
220 
 119 0004 0023     		movs	r3, #0
221 
 120 0006 0493     		str	r3, [sp, #16]
222 
 121 0008 0593     		str	r3, [sp, #20]
223 
 122 000a 0693     		str	r3, [sp, #24]
224 
 123 000c 0793     		str	r3, [sp, #28]
225 
  93:Core/Src/stm32f1xx_hal_msp.c ****   if(hi2c->Instance==I2C2)
226 
 124              		.loc 1 93 3 is_stmt 1 view .LVU21
227 
 125              		.loc 1 93 10 is_stmt 0 view .LVU22
228 
 126 000e 0268     		ldr	r2, [r0]
229 
 127              		.loc 1 93 5 view .LVU23
230 
 128 0010 164B     		ldr	r3, .L9
231 
 129 0012 9A42     		cmp	r2, r3
232 
 130 0014 01D0     		beq	.L8
233 
 131              	.LVL4:
234 
 132              	.L5:
235 
  94:Core/Src/stm32f1xx_hal_msp.c ****   {
236 
  95:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN I2C2_MspInit 0 */
237 
  96:Core/Src/stm32f1xx_hal_msp.c ****       __HAL_RCC_I2C2_CLK_ENABLE();
238 
  97:Core/Src/stm32f1xx_hal_msp.c ****
239 
  98:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END I2C2_MspInit 0 */
240 
  99:Core/Src/stm32f1xx_hal_msp.c ****
20 mjames 241 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 5
16 mjames 242 
 
243 
 
244 
 100:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
245 
 101:Core/Src/stm32f1xx_hal_msp.c ****     /**I2C2 GPIO Configuration
246 
 102:Core/Src/stm32f1xx_hal_msp.c ****     PB10     ------> I2C2_SCL
247 
 103:Core/Src/stm32f1xx_hal_msp.c ****     PB11     ------> I2C2_SDA
248 
 104:Core/Src/stm32f1xx_hal_msp.c ****     */
249 
 105:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
250 
 106:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
251 
 107:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
252 
 108:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
253 
 109:Core/Src/stm32f1xx_hal_msp.c ****
254 
 110:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock enable */
255 
 111:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_I2C2_CLK_ENABLE();
256 
 112:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN I2C2_MspInit 1 */
257 
 113:Core/Src/stm32f1xx_hal_msp.c ****
258 
 114:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END I2C2_MspInit 1 */
259 
 115:Core/Src/stm32f1xx_hal_msp.c ****   }
260 
 116:Core/Src/stm32f1xx_hal_msp.c ****
261 
 117:Core/Src/stm32f1xx_hal_msp.c **** }
262 
 133              		.loc 1 117 1 view .LVU24
263 
 134 0016 08B0     		add	sp, sp, #32
264 
 135              	.LCFI4:
265 
 136              		.cfi_remember_state
266 
 137              		.cfi_def_cfa_offset 8
267 
 138              		@ sp needed
268 
 139 0018 10BD     		pop	{r4, pc}
269 
 140              	.LVL5:
270 
 141              	.L8:
271 
 142              	.LCFI5:
272 
 143              		.cfi_restore_state
273 
  96:Core/Src/stm32f1xx_hal_msp.c ****
274 
 144              		.loc 1 96 7 is_stmt 1 view .LVU25
275 
 145              	.LBB5:
276 
  96:Core/Src/stm32f1xx_hal_msp.c ****
277 
 146              		.loc 1 96 7 view .LVU26
278 
  96:Core/Src/stm32f1xx_hal_msp.c ****
279 
 147              		.loc 1 96 7 view .LVU27
280 
 148 001a 154C     		ldr	r4, .L9+4
281 
 149 001c E369     		ldr	r3, [r4, #28]
282 
 150 001e 43F48003 		orr	r3, r3, #4194304
283 
 151 0022 E361     		str	r3, [r4, #28]
284 
  96:Core/Src/stm32f1xx_hal_msp.c ****
285 
 152              		.loc 1 96 7 view .LVU28
286 
 153 0024 E369     		ldr	r3, [r4, #28]
287 
 154 0026 03F48003 		and	r3, r3, #4194304
288 
 155 002a 0193     		str	r3, [sp, #4]
289 
  96:Core/Src/stm32f1xx_hal_msp.c ****
290 
 156              		.loc 1 96 7 view .LVU29
291 
 157 002c 019B     		ldr	r3, [sp, #4]
292 
 158              	.LBE5:
293 
 100:Core/Src/stm32f1xx_hal_msp.c ****     /**I2C2 GPIO Configuration
294 
 159              		.loc 1 100 5 view .LVU30
295 
 160              	.LBB6:
296 
 100:Core/Src/stm32f1xx_hal_msp.c ****     /**I2C2 GPIO Configuration
297 
 161              		.loc 1 100 5 view .LVU31
298 
 100:Core/Src/stm32f1xx_hal_msp.c ****     /**I2C2 GPIO Configuration
299 
 162              		.loc 1 100 5 view .LVU32
300 
 163 002e A369     		ldr	r3, [r4, #24]
20 mjames 301 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 6
16 mjames 302 
 
303 
 
304 
 164 0030 43F00803 		orr	r3, r3, #8
305 
 165 0034 A361     		str	r3, [r4, #24]
306 
 100:Core/Src/stm32f1xx_hal_msp.c ****     /**I2C2 GPIO Configuration
307 
 166              		.loc 1 100 5 view .LVU33
308 
 167 0036 A369     		ldr	r3, [r4, #24]
309 
 168 0038 03F00803 		and	r3, r3, #8
310 
 169 003c 0293     		str	r3, [sp, #8]
311 
 100:Core/Src/stm32f1xx_hal_msp.c ****     /**I2C2 GPIO Configuration
312 
 170              		.loc 1 100 5 view .LVU34
313 
 171 003e 029B     		ldr	r3, [sp, #8]
314 
 172              	.LBE6:
315 
 105:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
316 
 173              		.loc 1 105 5 view .LVU35
317 
 105:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
318 
 174              		.loc 1 105 25 is_stmt 0 view .LVU36
319 
 175 0040 4FF44063 		mov	r3, #3072
320 
 176 0044 0493     		str	r3, [sp, #16]
321 
 106:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
322 
 177              		.loc 1 106 5 is_stmt 1 view .LVU37
323 
 106:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
324 
 178              		.loc 1 106 26 is_stmt 0 view .LVU38
325 
 179 0046 1223     		movs	r3, #18
326 
 180 0048 0593     		str	r3, [sp, #20]
327 
 107:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
328 
 181              		.loc 1 107 5 is_stmt 1 view .LVU39
329 
 107:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
330 
 182              		.loc 1 107 27 is_stmt 0 view .LVU40
331 
 183 004a 0323     		movs	r3, #3
332 
 184 004c 0793     		str	r3, [sp, #28]
333 
 108:Core/Src/stm32f1xx_hal_msp.c ****
334 
 185              		.loc 1 108 5 is_stmt 1 view .LVU41
335 
 186 004e 04A9     		add	r1, sp, #16
336 
 187 0050 0848     		ldr	r0, .L9+8
337 
 188              	.LVL6:
338 
 108:Core/Src/stm32f1xx_hal_msp.c ****
339 
 189              		.loc 1 108 5 is_stmt 0 view .LVU42
340 
 190 0052 FFF7FEFF 		bl	HAL_GPIO_Init
341 
 191              	.LVL7:
342 
 111:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN I2C2_MspInit 1 */
343 
 192              		.loc 1 111 5 is_stmt 1 view .LVU43
344 
 193              	.LBB7:
345 
 111:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN I2C2_MspInit 1 */
346 
 194              		.loc 1 111 5 view .LVU44
347 
 111:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN I2C2_MspInit 1 */
348 
 195              		.loc 1 111 5 view .LVU45
349 
 196 0056 E369     		ldr	r3, [r4, #28]
350 
 197 0058 43F48003 		orr	r3, r3, #4194304
351 
 198 005c E361     		str	r3, [r4, #28]
352 
 111:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN I2C2_MspInit 1 */
353 
 199              		.loc 1 111 5 view .LVU46
354 
 200 005e E369     		ldr	r3, [r4, #28]
355 
 201 0060 03F48003 		and	r3, r3, #4194304
356 
 202 0064 0393     		str	r3, [sp, #12]
357 
 111:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN I2C2_MspInit 1 */
358 
 203              		.loc 1 111 5 view .LVU47
359 
 204 0066 039B     		ldr	r3, [sp, #12]
360 
 205              	.LBE7:
20 mjames 361 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 7
16 mjames 362 
 
363 
 
364 
 206              		.loc 1 117 1 is_stmt 0 view .LVU48
365 
 207 0068 D5E7     		b	.L5
366 
 208              	.L10:
367 
 209 006a 00BF     		.align	2
368 
 210              	.L9:
369 
 211 006c 00580040 		.word	1073764352
370 
 212 0070 00100240 		.word	1073876992
371 
 213 0074 000C0140 		.word	1073810432
372 
 214              		.cfi_endproc
373 
 215              	.LFE66:
374 
 217              		.section	.text.HAL_I2C_MspDeInit,"ax",%progbits
375 
 218              		.align	1
376 
 219              		.global	HAL_I2C_MspDeInit
377 
 220              		.syntax unified
378 
 221              		.thumb
379 
 222              		.thumb_func
380 
 223              		.fpu softvfp
381 
 225              	HAL_I2C_MspDeInit:
382 
 226              	.LVL8:
383 
 227              	.LFB67:
384 
 118:Core/Src/stm32f1xx_hal_msp.c ****
385 
 119:Core/Src/stm32f1xx_hal_msp.c **** /**
386 
 120:Core/Src/stm32f1xx_hal_msp.c **** * @brief I2C MSP De-Initialization
387 
 121:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
388 
 122:Core/Src/stm32f1xx_hal_msp.c **** * @param hi2c: I2C handle pointer
389 
 123:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
390 
 124:Core/Src/stm32f1xx_hal_msp.c **** */
391 
 125:Core/Src/stm32f1xx_hal_msp.c **** void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
392 
 126:Core/Src/stm32f1xx_hal_msp.c **** {
393 
 228              		.loc 1 126 1 is_stmt 1 view -0
394 
 229              		.cfi_startproc
395 
 230              		@ args = 0, pretend = 0, frame = 0
396 
 231              		@ frame_needed = 0, uses_anonymous_args = 0
397 
 127:Core/Src/stm32f1xx_hal_msp.c ****   if(hi2c->Instance==I2C2)
398 
 232              		.loc 1 127 3 view .LVU50
399 
 233              		.loc 1 127 10 is_stmt 0 view .LVU51
400 
 234 0000 0268     		ldr	r2, [r0]
401 
 235              		.loc 1 127 5 view .LVU52
402 
 236 0002 0B4B     		ldr	r3, .L18
403 
 237 0004 9A42     		cmp	r2, r3
404 
 238 0006 00D0     		beq	.L17
405 
 239 0008 7047     		bx	lr
406 
 240              	.L17:
407 
 126:Core/Src/stm32f1xx_hal_msp.c ****   if(hi2c->Instance==I2C2)
408 
 241              		.loc 1 126 1 view .LVU53
409 
 242 000a 10B5     		push	{r4, lr}
410 
 243              	.LCFI6:
411 
 244              		.cfi_def_cfa_offset 8
412 
 245              		.cfi_offset 4, -8
413 
 246              		.cfi_offset 14, -4
414 
 128:Core/Src/stm32f1xx_hal_msp.c ****   {
415 
 129:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN I2C2_MspDeInit 0 */
416 
 130:Core/Src/stm32f1xx_hal_msp.c ****
417 
 131:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END I2C2_MspDeInit 0 */
418 
 132:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock disable */
419 
 133:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_I2C2_CLK_DISABLE();
420 
 247              		.loc 1 133 5 is_stmt 1 view .LVU54
20 mjames 421 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 8
16 mjames 422 
 
423 
 
424 
 248 000c 094A     		ldr	r2, .L18+4
425 
 249 000e D369     		ldr	r3, [r2, #28]
426 
 250 0010 23F48003 		bic	r3, r3, #4194304
427 
 251 0014 D361     		str	r3, [r2, #28]
428 
 134:Core/Src/stm32f1xx_hal_msp.c ****
429 
 135:Core/Src/stm32f1xx_hal_msp.c ****     /**I2C2 GPIO Configuration
430 
 136:Core/Src/stm32f1xx_hal_msp.c ****     PB10     ------> I2C2_SCL
431 
 137:Core/Src/stm32f1xx_hal_msp.c ****     PB11     ------> I2C2_SDA
432 
 138:Core/Src/stm32f1xx_hal_msp.c ****     */
433 
 139:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10);
434 
 252              		.loc 1 139 5 view .LVU55
435 
 253 0016 084C     		ldr	r4, .L18+8
436 
 254 0018 4FF48061 		mov	r1, #1024
437 
 255 001c 2046     		mov	r0, r4
438 
 256              	.LVL9:
439 
 257              		.loc 1 139 5 is_stmt 0 view .LVU56
440 
 258 001e FFF7FEFF 		bl	HAL_GPIO_DeInit
441 
 259              	.LVL10:
442 
 140:Core/Src/stm32f1xx_hal_msp.c ****
443 
 141:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11);
444 
 260              		.loc 1 141 5 is_stmt 1 view .LVU57
445 
 261 0022 4FF40061 		mov	r1, #2048
446 
 262 0026 2046     		mov	r0, r4
447 
 263 0028 FFF7FEFF 		bl	HAL_GPIO_DeInit
448 
 264              	.LVL11:
449 
 142:Core/Src/stm32f1xx_hal_msp.c ****
450 
 143:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN I2C2_MspDeInit 1 */
451 
 144:Core/Src/stm32f1xx_hal_msp.c ****
452 
 145:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END I2C2_MspDeInit 1 */
453 
 146:Core/Src/stm32f1xx_hal_msp.c ****   }
454 
 147:Core/Src/stm32f1xx_hal_msp.c ****
455 
 148:Core/Src/stm32f1xx_hal_msp.c **** }
456 
 265              		.loc 1 148 1 is_stmt 0 view .LVU58
457 
 266 002c 10BD     		pop	{r4, pc}
458 
 267              	.L19:
459 
 268 002e 00BF     		.align	2
460 
 269              	.L18:
461 
 270 0030 00580040 		.word	1073764352
462 
 271 0034 00100240 		.word	1073876992
463 
 272 0038 000C0140 		.word	1073810432
464 
 273              		.cfi_endproc
465 
 274              	.LFE67:
466 
 276              		.section	.text.HAL_RTC_MspInit,"ax",%progbits
467 
 277              		.align	1
468 
 278              		.global	HAL_RTC_MspInit
469 
 279              		.syntax unified
470 
 280              		.thumb
471 
 281              		.thumb_func
472 
 282              		.fpu softvfp
473 
 284              	HAL_RTC_MspInit:
474 
 285              	.LVL12:
475 
 286              	.LFB68:
476 
 149:Core/Src/stm32f1xx_hal_msp.c ****
477 
 150:Core/Src/stm32f1xx_hal_msp.c **** /**
478 
 151:Core/Src/stm32f1xx_hal_msp.c **** * @brief RTC MSP Initialization
479 
 152:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
480 
 153:Core/Src/stm32f1xx_hal_msp.c **** * @param hrtc: RTC handle pointer
20 mjames 481 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 9
16 mjames 482 
 
483 
 
484 
 154:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
485 
 155:Core/Src/stm32f1xx_hal_msp.c **** */
486 
 156:Core/Src/stm32f1xx_hal_msp.c **** void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
487 
 157:Core/Src/stm32f1xx_hal_msp.c **** {
488 
 287              		.loc 1 157 1 is_stmt 1 view -0
489 
 288              		.cfi_startproc
490 
 289              		@ args = 0, pretend = 0, frame = 8
491 
 290              		@ frame_needed = 0, uses_anonymous_args = 0
492 
 158:Core/Src/stm32f1xx_hal_msp.c ****   if(hrtc->Instance==RTC)
493 
 291              		.loc 1 158 3 view .LVU60
494 
 292              		.loc 1 158 10 is_stmt 0 view .LVU61
495 
 293 0000 0268     		ldr	r2, [r0]
496 
 294              		.loc 1 158 5 view .LVU62
497 
 295 0002 0C4B     		ldr	r3, .L27
498 
 296 0004 9A42     		cmp	r2, r3
499 
 297 0006 00D0     		beq	.L26
500 
 298 0008 7047     		bx	lr
501 
 299              	.L26:
502 
 157:Core/Src/stm32f1xx_hal_msp.c ****   if(hrtc->Instance==RTC)
503 
 300              		.loc 1 157 1 view .LVU63
504 
 301 000a 00B5     		push	{lr}
505 
 302              	.LCFI7:
506 
 303              		.cfi_def_cfa_offset 4
507 
 304              		.cfi_offset 14, -4
508 
 305 000c 83B0     		sub	sp, sp, #12
509 
 306              	.LCFI8:
510 
 307              		.cfi_def_cfa_offset 16
511 
 159:Core/Src/stm32f1xx_hal_msp.c ****   {
512 
 160:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN RTC_MspInit 0 */
513 
 161:Core/Src/stm32f1xx_hal_msp.c ****
514 
 162:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END RTC_MspInit 0 */
515 
 163:Core/Src/stm32f1xx_hal_msp.c ****     HAL_PWR_EnableBkUpAccess();
516 
 308              		.loc 1 163 5 is_stmt 1 view .LVU64
517 
 309 000e FFF7FEFF 		bl	HAL_PWR_EnableBkUpAccess
518 
 310              	.LVL13:
519 
 164:Core/Src/stm32f1xx_hal_msp.c ****     /* Enable BKP CLK enable for backup registers */
520 
 165:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_BKP_CLK_ENABLE();
521 
 311              		.loc 1 165 5 view .LVU65
522 
 312              	.LBB8:
523 
 313              		.loc 1 165 5 view .LVU66
524 
 314              		.loc 1 165 5 view .LVU67
525 
 315 0012 094B     		ldr	r3, .L27+4
526 
 316 0014 DA69     		ldr	r2, [r3, #28]
527 
 317 0016 42F00062 		orr	r2, r2, #134217728
528 
 318 001a DA61     		str	r2, [r3, #28]
529 
 319              		.loc 1 165 5 view .LVU68
530 
 320 001c DB69     		ldr	r3, [r3, #28]
531 
 321 001e 03F00063 		and	r3, r3, #134217728
532 
 322 0022 0193     		str	r3, [sp, #4]
533 
 323              		.loc 1 165 5 view .LVU69
534 
 324 0024 019B     		ldr	r3, [sp, #4]
535 
 325              	.LBE8:
536 
 166:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock enable */
537 
 167:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_RTC_ENABLE();
538 
 326              		.loc 1 167 5 view .LVU70
539 
 327 0026 054B     		ldr	r3, .L27+8
540 
 328 0028 0122     		movs	r2, #1
20 mjames 541 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 10
16 mjames 542 
 
543 
 
544 
 329 002a 1A60     		str	r2, [r3]
545 
 168:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN RTC_MspInit 1 */
546 
 169:Core/Src/stm32f1xx_hal_msp.c ****
547 
 170:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END RTC_MspInit 1 */
548 
 171:Core/Src/stm32f1xx_hal_msp.c ****   }
549 
 172:Core/Src/stm32f1xx_hal_msp.c ****
550 
 173:Core/Src/stm32f1xx_hal_msp.c **** }
551 
 330              		.loc 1 173 1 is_stmt 0 view .LVU71
552 
 331 002c 03B0     		add	sp, sp, #12
553 
 332              	.LCFI9:
554 
 333              		.cfi_def_cfa_offset 4
555 
 334              		@ sp needed
556 
 335 002e 5DF804FB 		ldr	pc, [sp], #4
557 
 336              	.L28:
558 
 337 0032 00BF     		.align	2
559 
 338              	.L27:
560 
 339 0034 00280040 		.word	1073752064
561 
 340 0038 00100240 		.word	1073876992
562 
 341 003c 3C044242 		.word	1111622716
563 
 342              		.cfi_endproc
564 
 343              	.LFE68:
565 
 345              		.section	.text.HAL_RTC_MspDeInit,"ax",%progbits
566 
 346              		.align	1
567 
 347              		.global	HAL_RTC_MspDeInit
568 
 348              		.syntax unified
569 
 349              		.thumb
570 
 350              		.thumb_func
571 
 351              		.fpu softvfp
572 
 353              	HAL_RTC_MspDeInit:
573 
 354              	.LVL14:
574 
 355              	.LFB69:
575 
 174:Core/Src/stm32f1xx_hal_msp.c ****
576 
 175:Core/Src/stm32f1xx_hal_msp.c **** /**
577 
 176:Core/Src/stm32f1xx_hal_msp.c **** * @brief RTC MSP De-Initialization
578 
 177:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
579 
 178:Core/Src/stm32f1xx_hal_msp.c **** * @param hrtc: RTC handle pointer
580 
 179:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
581 
 180:Core/Src/stm32f1xx_hal_msp.c **** */
582 
 181:Core/Src/stm32f1xx_hal_msp.c **** void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
583 
 182:Core/Src/stm32f1xx_hal_msp.c **** {
584 
 356              		.loc 1 182 1 is_stmt 1 view -0
585 
 357              		.cfi_startproc
586 
 358              		@ args = 0, pretend = 0, frame = 0
587 
 359              		@ frame_needed = 0, uses_anonymous_args = 0
588 
 360              		@ link register save eliminated.
589 
 183:Core/Src/stm32f1xx_hal_msp.c ****   if(hrtc->Instance==RTC)
590 
 361              		.loc 1 183 3 view .LVU73
591 
 362              		.loc 1 183 10 is_stmt 0 view .LVU74
592 
 363 0000 0268     		ldr	r2, [r0]
593 
 364              		.loc 1 183 5 view .LVU75
594 
 365 0002 044B     		ldr	r3, .L32
595 
 366 0004 9A42     		cmp	r2, r3
596 
 367 0006 00D0     		beq	.L31
597 
 368              	.L29:
598 
 184:Core/Src/stm32f1xx_hal_msp.c ****   {
599 
 185:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN RTC_MspDeInit 0 */
600 
 186:Core/Src/stm32f1xx_hal_msp.c ****
20 mjames 601 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 11
16 mjames 602 
 
603 
 
604 
 187:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END RTC_MspDeInit 0 */
605 
 188:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock disable */
606 
 189:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_RTC_DISABLE();
607 
 190:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN RTC_MspDeInit 1 */
608 
 191:Core/Src/stm32f1xx_hal_msp.c ****
609 
 192:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END RTC_MspDeInit 1 */
610 
 193:Core/Src/stm32f1xx_hal_msp.c ****   }
611 
 194:Core/Src/stm32f1xx_hal_msp.c ****
612 
 195:Core/Src/stm32f1xx_hal_msp.c **** }
613 
 369              		.loc 1 195 1 view .LVU76
614 
 370 0008 7047     		bx	lr
615 
 371              	.L31:
616 
 189:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN RTC_MspDeInit 1 */
617 
 372              		.loc 1 189 5 is_stmt 1 view .LVU77
618 
 373 000a 034B     		ldr	r3, .L32+4
619 
 374 000c 0022     		movs	r2, #0
620 
 375 000e 1A60     		str	r2, [r3]
621 
 376              		.loc 1 195 1 is_stmt 0 view .LVU78
622 
 377 0010 FAE7     		b	.L29
623 
 378              	.L33:
624 
 379 0012 00BF     		.align	2
625 
 380              	.L32:
626 
 381 0014 00280040 		.word	1073752064
627 
 382 0018 3C044242 		.word	1111622716
628 
 383              		.cfi_endproc
629 
 384              	.LFE69:
630 
 386              		.section	.text.HAL_SPI_MspInit,"ax",%progbits
631 
 387              		.align	1
632 
 388              		.global	HAL_SPI_MspInit
633 
 389              		.syntax unified
634 
 390              		.thumb
635 
 391              		.thumb_func
636 
 392              		.fpu softvfp
637 
 394              	HAL_SPI_MspInit:
638 
 395              	.LVL15:
639 
 396              	.LFB70:
640 
 196:Core/Src/stm32f1xx_hal_msp.c ****
641 
 197:Core/Src/stm32f1xx_hal_msp.c **** /**
642 
 198:Core/Src/stm32f1xx_hal_msp.c **** * @brief SPI MSP Initialization
643 
 199:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
644 
 200:Core/Src/stm32f1xx_hal_msp.c **** * @param hspi: SPI handle pointer
645 
 201:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
646 
 202:Core/Src/stm32f1xx_hal_msp.c **** */
647 
 203:Core/Src/stm32f1xx_hal_msp.c **** void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
648 
 204:Core/Src/stm32f1xx_hal_msp.c **** {
649 
 397              		.loc 1 204 1 is_stmt 1 view -0
650 
 398              		.cfi_startproc
651 
 399              		@ args = 0, pretend = 0, frame = 24
652 
 400              		@ frame_needed = 0, uses_anonymous_args = 0
653 
 401              		.loc 1 204 1 is_stmt 0 view .LVU80
654 
 402 0000 00B5     		push	{lr}
655 
 403              	.LCFI10:
656 
 404              		.cfi_def_cfa_offset 4
657 
 405              		.cfi_offset 14, -4
658 
 406 0002 87B0     		sub	sp, sp, #28
659 
 407              	.LCFI11:
660 
 408              		.cfi_def_cfa_offset 32
20 mjames 661 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 12
16 mjames 662 
 
663 
 
664 
 205:Core/Src/stm32f1xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
665 
 409              		.loc 1 205 3 is_stmt 1 view .LVU81
666 
 410              		.loc 1 205 20 is_stmt 0 view .LVU82
667 
 411 0004 0023     		movs	r3, #0
668 
 412 0006 0293     		str	r3, [sp, #8]
669 
 413 0008 0393     		str	r3, [sp, #12]
670 
 414 000a 0493     		str	r3, [sp, #16]
671 
 415 000c 0593     		str	r3, [sp, #20]
672 
 206:Core/Src/stm32f1xx_hal_msp.c ****   if(hspi->Instance==SPI1)
673 
 416              		.loc 1 206 3 is_stmt 1 view .LVU83
674 
 417              		.loc 1 206 10 is_stmt 0 view .LVU84
675 
 418 000e 0268     		ldr	r2, [r0]
676 
 419              		.loc 1 206 5 view .LVU85
677 
 420 0010 124B     		ldr	r3, .L38
678 
 421 0012 9A42     		cmp	r2, r3
679 
 422 0014 02D0     		beq	.L37
680 
 423              	.LVL16:
681 
 424              	.L34:
682 
 207:Core/Src/stm32f1xx_hal_msp.c ****   {
683 
 208:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN SPI1_MspInit 0 */
684 
 209:Core/Src/stm32f1xx_hal_msp.c ****
685 
 210:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END SPI1_MspInit 0 */
686 
 211:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock enable */
687 
 212:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_SPI1_CLK_ENABLE();
688 
 213:Core/Src/stm32f1xx_hal_msp.c ****
689 
 214:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
690 
 215:Core/Src/stm32f1xx_hal_msp.c ****     /**SPI1 GPIO Configuration
691 
 216:Core/Src/stm32f1xx_hal_msp.c ****     PA5     ------> SPI1_SCK
692 
 217:Core/Src/stm32f1xx_hal_msp.c ****     PA7     ------> SPI1_MOSI
693 
 218:Core/Src/stm32f1xx_hal_msp.c ****     */
694 
 219:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pin = SPI_SCK_Pin|SPI_MOSI_Pin;
695 
 220:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
696 
 221:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
697 
 222:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
698 
 223:Core/Src/stm32f1xx_hal_msp.c ****
699 
 224:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN SPI1_MspInit 1 */
700 
 225:Core/Src/stm32f1xx_hal_msp.c ****
701 
 226:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END SPI1_MspInit 1 */
702 
 227:Core/Src/stm32f1xx_hal_msp.c ****   }
703 
 228:Core/Src/stm32f1xx_hal_msp.c ****
704 
 229:Core/Src/stm32f1xx_hal_msp.c **** }
705 
 425              		.loc 1 229 1 view .LVU86
706 
 426 0016 07B0     		add	sp, sp, #28
707 
 427              	.LCFI12:
708 
 428              		.cfi_remember_state
709 
 429              		.cfi_def_cfa_offset 4
710 
 430              		@ sp needed
711 
 431 0018 5DF804FB 		ldr	pc, [sp], #4
712 
 432              	.LVL17:
713 
 433              	.L37:
714 
 434              	.LCFI13:
715 
 435              		.cfi_restore_state
716 
 212:Core/Src/stm32f1xx_hal_msp.c ****
717 
 436              		.loc 1 212 5 is_stmt 1 view .LVU87
718 
 437              	.LBB9:
719 
 212:Core/Src/stm32f1xx_hal_msp.c ****
720 
 438              		.loc 1 212 5 view .LVU88
20 mjames 721 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 13
16 mjames 722 
 
723 
 
724 
 212:Core/Src/stm32f1xx_hal_msp.c ****
725 
 439              		.loc 1 212 5 view .LVU89
726 
 440 001c 03F56043 		add	r3, r3, #57344
727 
 441 0020 9A69     		ldr	r2, [r3, #24]
728 
 442 0022 42F48052 		orr	r2, r2, #4096
729 
 443 0026 9A61     		str	r2, [r3, #24]
730 
 212:Core/Src/stm32f1xx_hal_msp.c ****
731 
 444              		.loc 1 212 5 view .LVU90
732 
 445 0028 9A69     		ldr	r2, [r3, #24]
733 
 446 002a 02F48052 		and	r2, r2, #4096
734 
 447 002e 0092     		str	r2, [sp]
735 
 212:Core/Src/stm32f1xx_hal_msp.c ****
736 
 448              		.loc 1 212 5 view .LVU91
737 
 449 0030 009A     		ldr	r2, [sp]
738 
 450              	.LBE9:
739 
 214:Core/Src/stm32f1xx_hal_msp.c ****     /**SPI1 GPIO Configuration
740 
 451              		.loc 1 214 5 view .LVU92
741 
 452              	.LBB10:
742 
 214:Core/Src/stm32f1xx_hal_msp.c ****     /**SPI1 GPIO Configuration
743 
 453              		.loc 1 214 5 view .LVU93
744 
 214:Core/Src/stm32f1xx_hal_msp.c ****     /**SPI1 GPIO Configuration
745 
 454              		.loc 1 214 5 view .LVU94
746 
 455 0032 9A69     		ldr	r2, [r3, #24]
747 
 456 0034 42F00402 		orr	r2, r2, #4
748 
 457 0038 9A61     		str	r2, [r3, #24]
749 
 214:Core/Src/stm32f1xx_hal_msp.c ****     /**SPI1 GPIO Configuration
750 
 458              		.loc 1 214 5 view .LVU95
751 
 459 003a 9B69     		ldr	r3, [r3, #24]
752 
 460 003c 03F00403 		and	r3, r3, #4
753 
 461 0040 0193     		str	r3, [sp, #4]
754 
 214:Core/Src/stm32f1xx_hal_msp.c ****     /**SPI1 GPIO Configuration
755 
 462              		.loc 1 214 5 view .LVU96
756 
 463 0042 019B     		ldr	r3, [sp, #4]
757 
 464              	.LBE10:
758 
 219:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
759 
 465              		.loc 1 219 5 view .LVU97
760 
 219:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
761 
 466              		.loc 1 219 25 is_stmt 0 view .LVU98
762 
 467 0044 A023     		movs	r3, #160
763 
 468 0046 0293     		str	r3, [sp, #8]
764 
 220:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
765 
 469              		.loc 1 220 5 is_stmt 1 view .LVU99
766 
 220:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
767 
 470              		.loc 1 220 26 is_stmt 0 view .LVU100
768 
 471 0048 0223     		movs	r3, #2
769 
 472 004a 0393     		str	r3, [sp, #12]
770 
 221:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
771 
 473              		.loc 1 221 5 is_stmt 1 view .LVU101
772 
 221:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
773 
 474              		.loc 1 221 27 is_stmt 0 view .LVU102
774 
 475 004c 0323     		movs	r3, #3
775 
 476 004e 0593     		str	r3, [sp, #20]
776 
 222:Core/Src/stm32f1xx_hal_msp.c ****
777 
 477              		.loc 1 222 5 is_stmt 1 view .LVU103
778 
 478 0050 02A9     		add	r1, sp, #8
779 
 479 0052 0348     		ldr	r0, .L38+4
780 
 480              	.LVL18:
20 mjames 781 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 14
16 mjames 782 
 
783 
 
784 
 222:Core/Src/stm32f1xx_hal_msp.c ****
785 
 481              		.loc 1 222 5 is_stmt 0 view .LVU104
786 
 482 0054 FFF7FEFF 		bl	HAL_GPIO_Init
787 
 483              	.LVL19:
788 
 484              		.loc 1 229 1 view .LVU105
789 
 485 0058 DDE7     		b	.L34
790 
 486              	.L39:
791 
 487 005a 00BF     		.align	2
792 
 488              	.L38:
793 
 489 005c 00300140 		.word	1073819648
794 
 490 0060 00080140 		.word	1073809408
795 
 491              		.cfi_endproc
796 
 492              	.LFE70:
797 
 494              		.section	.text.HAL_SPI_MspDeInit,"ax",%progbits
798 
 495              		.align	1
799 
 496              		.global	HAL_SPI_MspDeInit
800 
 497              		.syntax unified
801 
 498              		.thumb
802 
 499              		.thumb_func
803 
 500              		.fpu softvfp
804 
 502              	HAL_SPI_MspDeInit:
805 
 503              	.LVL20:
806 
 504              	.LFB71:
807 
 230:Core/Src/stm32f1xx_hal_msp.c ****
808 
 231:Core/Src/stm32f1xx_hal_msp.c **** /**
809 
 232:Core/Src/stm32f1xx_hal_msp.c **** * @brief SPI MSP De-Initialization
810 
 233:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
811 
 234:Core/Src/stm32f1xx_hal_msp.c **** * @param hspi: SPI handle pointer
812 
 235:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
813 
 236:Core/Src/stm32f1xx_hal_msp.c **** */
814 
 237:Core/Src/stm32f1xx_hal_msp.c **** void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
815 
 238:Core/Src/stm32f1xx_hal_msp.c **** {
816 
 505              		.loc 1 238 1 is_stmt 1 view -0
817 
 506              		.cfi_startproc
818 
 507              		@ args = 0, pretend = 0, frame = 0
819 
 508              		@ frame_needed = 0, uses_anonymous_args = 0
820 
 509              		.loc 1 238 1 is_stmt 0 view .LVU107
821 
 510 0000 08B5     		push	{r3, lr}
822 
 511              	.LCFI14:
823 
 512              		.cfi_def_cfa_offset 8
824 
 513              		.cfi_offset 3, -8
825 
 514              		.cfi_offset 14, -4
826 
 239:Core/Src/stm32f1xx_hal_msp.c ****   if(hspi->Instance==SPI1)
827 
 515              		.loc 1 239 3 is_stmt 1 view .LVU108
828 
 516              		.loc 1 239 10 is_stmt 0 view .LVU109
829 
 517 0002 0268     		ldr	r2, [r0]
830 
 518              		.loc 1 239 5 view .LVU110
831 
 519 0004 064B     		ldr	r3, .L44
832 
 520 0006 9A42     		cmp	r2, r3
833 
 521 0008 00D0     		beq	.L43
834 
 522              	.LVL21:
835 
 523              	.L40:
836 
 240:Core/Src/stm32f1xx_hal_msp.c ****   {
837 
 241:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN SPI1_MspDeInit 0 */
838 
 242:Core/Src/stm32f1xx_hal_msp.c ****
839 
 243:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END SPI1_MspDeInit 0 */
840 
 244:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock disable */
20 mjames 841 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 15
16 mjames 842 
 
843 
 
844 
 245:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_SPI1_CLK_DISABLE();
845 
 246:Core/Src/stm32f1xx_hal_msp.c ****
846 
 247:Core/Src/stm32f1xx_hal_msp.c ****     /**SPI1 GPIO Configuration
847 
 248:Core/Src/stm32f1xx_hal_msp.c ****     PA5     ------> SPI1_SCK
848 
 249:Core/Src/stm32f1xx_hal_msp.c ****     PA7     ------> SPI1_MOSI
849 
 250:Core/Src/stm32f1xx_hal_msp.c ****     */
850 
 251:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOA, SPI_SCK_Pin|SPI_MOSI_Pin);
851 
 252:Core/Src/stm32f1xx_hal_msp.c ****
852 
 253:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN SPI1_MspDeInit 1 */
853 
 254:Core/Src/stm32f1xx_hal_msp.c ****
854 
 255:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END SPI1_MspDeInit 1 */
855 
 256:Core/Src/stm32f1xx_hal_msp.c ****   }
856 
 257:Core/Src/stm32f1xx_hal_msp.c ****
857 
 258:Core/Src/stm32f1xx_hal_msp.c **** }
858 
 524              		.loc 1 258 1 view .LVU111
859 
 525 000a 08BD     		pop	{r3, pc}
860 
 526              	.LVL22:
861 
 527              	.L43:
862 
 245:Core/Src/stm32f1xx_hal_msp.c ****
863 
 528              		.loc 1 245 5 is_stmt 1 view .LVU112
864 
 529 000c 054A     		ldr	r2, .L44+4
865 
 530 000e 9369     		ldr	r3, [r2, #24]
866 
 531 0010 23F48053 		bic	r3, r3, #4096
867 
 532 0014 9361     		str	r3, [r2, #24]
868 
 251:Core/Src/stm32f1xx_hal_msp.c ****
869 
 533              		.loc 1 251 5 view .LVU113
870 
 534 0016 A021     		movs	r1, #160
871 
 535 0018 0348     		ldr	r0, .L44+8
872 
 536              	.LVL23:
873 
 251:Core/Src/stm32f1xx_hal_msp.c ****
874 
 537              		.loc 1 251 5 is_stmt 0 view .LVU114
875 
 538 001a FFF7FEFF 		bl	HAL_GPIO_DeInit
876 
 539              	.LVL24:
877 
 540              		.loc 1 258 1 view .LVU115
878 
 541 001e F4E7     		b	.L40
879 
 542              	.L45:
880 
 543              		.align	2
881 
 544              	.L44:
882 
 545 0020 00300140 		.word	1073819648
883 
 546 0024 00100240 		.word	1073876992
884 
 547 0028 00080140 		.word	1073809408
885 
 548              		.cfi_endproc
886 
 549              	.LFE71:
887 
 551              		.section	.text.HAL_TIM_OC_MspInit,"ax",%progbits
888 
 552              		.align	1
889 
 553              		.global	HAL_TIM_OC_MspInit
890 
 554              		.syntax unified
891 
 555              		.thumb
892 
 556              		.thumb_func
893 
 557              		.fpu softvfp
894 
 559              	HAL_TIM_OC_MspInit:
895 
 560              	.LVL25:
896 
 561              	.LFB72:
897 
 259:Core/Src/stm32f1xx_hal_msp.c ****
898 
 260:Core/Src/stm32f1xx_hal_msp.c **** /**
899 
 261:Core/Src/stm32f1xx_hal_msp.c **** * @brief TIM_OC MSP Initialization
900 
 262:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
20 mjames 901 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 16
16 mjames 902 
 
903 
 
904 
 263:Core/Src/stm32f1xx_hal_msp.c **** * @param htim_oc: TIM_OC handle pointer
905 
 264:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
906 
 265:Core/Src/stm32f1xx_hal_msp.c **** */
907 
 266:Core/Src/stm32f1xx_hal_msp.c **** void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* htim_oc)
908 
 267:Core/Src/stm32f1xx_hal_msp.c **** {
909 
 562              		.loc 1 267 1 is_stmt 1 view -0
910 
 563              		.cfi_startproc
911 
 564              		@ args = 0, pretend = 0, frame = 8
912 
 565              		@ frame_needed = 0, uses_anonymous_args = 0
913 
 566              		@ link register save eliminated.
914 
 268:Core/Src/stm32f1xx_hal_msp.c ****   if(htim_oc->Instance==TIM3)
915 
 567              		.loc 1 268 3 view .LVU117
916 
 568              		.loc 1 268 13 is_stmt 0 view .LVU118
917 
 569 0000 0268     		ldr	r2, [r0]
918 
 570              		.loc 1 268 5 view .LVU119
919 
 571 0002 094B     		ldr	r3, .L53
920 
 572 0004 9A42     		cmp	r2, r3
921 
 573 0006 00D0     		beq	.L52
922 
 574 0008 7047     		bx	lr
923 
 575              	.L52:
924 
 267:Core/Src/stm32f1xx_hal_msp.c ****   if(htim_oc->Instance==TIM3)
925 
 576              		.loc 1 267 1 view .LVU120
926 
 577 000a 82B0     		sub	sp, sp, #8
927 
 578              	.LCFI15:
928 
 579              		.cfi_def_cfa_offset 8
929 
 269:Core/Src/stm32f1xx_hal_msp.c ****   {
930 
 270:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspInit 0 */
931 
 271:Core/Src/stm32f1xx_hal_msp.c ****
932 
 272:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END TIM3_MspInit 0 */
933 
 273:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock enable */
934 
 274:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_TIM3_CLK_ENABLE();
935 
 580              		.loc 1 274 5 is_stmt 1 view .LVU121
936 
 581              	.LBB11:
937 
 582              		.loc 1 274 5 view .LVU122
938 
 583              		.loc 1 274 5 view .LVU123
939 
 584 000c 03F50333 		add	r3, r3, #134144
940 
 585 0010 DA69     		ldr	r2, [r3, #28]
941 
 586 0012 42F00202 		orr	r2, r2, #2
942 
 587 0016 DA61     		str	r2, [r3, #28]
943 
 588              		.loc 1 274 5 view .LVU124
944 
 589 0018 DB69     		ldr	r3, [r3, #28]
945 
 590 001a 03F00203 		and	r3, r3, #2
946 
 591 001e 0193     		str	r3, [sp, #4]
947 
 592              		.loc 1 274 5 view .LVU125
948 
 593 0020 019B     		ldr	r3, [sp, #4]
949 
 594              	.LBE11:
950 
 275:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspInit 1 */
951 
 276:Core/Src/stm32f1xx_hal_msp.c ****
952 
 277:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END TIM3_MspInit 1 */
953 
 278:Core/Src/stm32f1xx_hal_msp.c ****   }
954 
 279:Core/Src/stm32f1xx_hal_msp.c ****
955 
 280:Core/Src/stm32f1xx_hal_msp.c **** }
956 
 595              		.loc 1 280 1 is_stmt 0 view .LVU126
957 
 596 0022 02B0     		add	sp, sp, #8
958 
 597              	.LCFI16:
959 
 598              		.cfi_def_cfa_offset 0
960 
 599              		@ sp needed
20 mjames 961 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 17
16 mjames 962 
 
963 
 
964 
 600 0024 7047     		bx	lr
965 
 601              	.L54:
966 
 602 0026 00BF     		.align	2
967 
 603              	.L53:
968 
 604 0028 00040040 		.word	1073742848
969 
 605              		.cfi_endproc
970 
 606              	.LFE72:
971 
 608              		.section	.text.HAL_TIM_Encoder_MspInit,"ax",%progbits
972 
 609              		.align	1
973 
 610              		.global	HAL_TIM_Encoder_MspInit
974 
 611              		.syntax unified
975 
 612              		.thumb
976 
 613              		.thumb_func
977 
 614              		.fpu softvfp
978 
 616              	HAL_TIM_Encoder_MspInit:
979 
 617              	.LVL26:
980 
 618              	.LFB73:
981 
 281:Core/Src/stm32f1xx_hal_msp.c ****
982 
 282:Core/Src/stm32f1xx_hal_msp.c **** /**
983 
 283:Core/Src/stm32f1xx_hal_msp.c **** * @brief TIM_Encoder MSP Initialization
984 
 284:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
985 
 285:Core/Src/stm32f1xx_hal_msp.c **** * @param htim_encoder: TIM_Encoder handle pointer
986 
 286:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
987 
 287:Core/Src/stm32f1xx_hal_msp.c **** */
988 
 288:Core/Src/stm32f1xx_hal_msp.c **** void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
989 
 289:Core/Src/stm32f1xx_hal_msp.c **** {
990 
 619              		.loc 1 289 1 is_stmt 1 view -0
991 
 620              		.cfi_startproc
992 
 621              		@ args = 0, pretend = 0, frame = 24
993 
 622              		@ frame_needed = 0, uses_anonymous_args = 0
994 
 623              		.loc 1 289 1 is_stmt 0 view .LVU128
995 
 624 0000 00B5     		push	{lr}
996 
 625              	.LCFI17:
997 
 626              		.cfi_def_cfa_offset 4
998 
 627              		.cfi_offset 14, -4
999 
 628 0002 87B0     		sub	sp, sp, #28
1000 
 629              	.LCFI18:
1001 
 630              		.cfi_def_cfa_offset 32
1002 
 290:Core/Src/stm32f1xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
1003 
 631              		.loc 1 290 3 is_stmt 1 view .LVU129
1004 
 632              		.loc 1 290 20 is_stmt 0 view .LVU130
1005 
 633 0004 0023     		movs	r3, #0
1006 
 634 0006 0293     		str	r3, [sp, #8]
1007 
 635 0008 0393     		str	r3, [sp, #12]
1008 
 636 000a 0493     		str	r3, [sp, #16]
1009 
 637 000c 0593     		str	r3, [sp, #20]
1010 
 291:Core/Src/stm32f1xx_hal_msp.c ****   if(htim_encoder->Instance==TIM4)
1011 
 638              		.loc 1 291 3 is_stmt 1 view .LVU131
1012 
 639              		.loc 1 291 18 is_stmt 0 view .LVU132
1013 
 640 000e 0268     		ldr	r2, [r0]
1014 
 641              		.loc 1 291 5 view .LVU133
1015 
 642 0010 114B     		ldr	r3, .L59
1016 
 643 0012 9A42     		cmp	r2, r3
1017 
 644 0014 02D0     		beq	.L58
1018 
 645              	.LVL27:
1019 
 646              	.L55:
1020 
 292:Core/Src/stm32f1xx_hal_msp.c ****   {
20 mjames 1021 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 18
16 mjames 1022 
 
1023 
 
1024 
 293:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN TIM4_MspInit 0 */
1025 
 294:Core/Src/stm32f1xx_hal_msp.c ****
1026 
 295:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END TIM4_MspInit 0 */
1027 
 296:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock enable */
1028 
 297:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_TIM4_CLK_ENABLE();
1029 
 298:Core/Src/stm32f1xx_hal_msp.c ****
1030 
 299:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_GPIOB_CLK_ENABLE();
1031 
 300:Core/Src/stm32f1xx_hal_msp.c ****     /**TIM4 GPIO Configuration
1032 
 301:Core/Src/stm32f1xx_hal_msp.c ****     PB6     ------> TIM4_CH1
1033 
 302:Core/Src/stm32f1xx_hal_msp.c ****     PB7     ------> TIM4_CH2
1034 
 303:Core/Src/stm32f1xx_hal_msp.c ****     */
1035 
 304:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
1036 
 305:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
1037 
 306:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_PULLUP;
1038 
 307:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
1039 
 308:Core/Src/stm32f1xx_hal_msp.c ****
1040 
 309:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN TIM4_MspInit 1 */
1041 
 310:Core/Src/stm32f1xx_hal_msp.c ****
1042 
 311:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END TIM4_MspInit 1 */
1043 
 312:Core/Src/stm32f1xx_hal_msp.c ****   }
1044 
 313:Core/Src/stm32f1xx_hal_msp.c ****
1045 
 314:Core/Src/stm32f1xx_hal_msp.c **** }
1046 
 647              		.loc 1 314 1 view .LVU134
1047 
 648 0016 07B0     		add	sp, sp, #28
1048 
 649              	.LCFI19:
1049 
 650              		.cfi_remember_state
1050 
 651              		.cfi_def_cfa_offset 4
1051 
 652              		@ sp needed
1052 
 653 0018 5DF804FB 		ldr	pc, [sp], #4
1053 
 654              	.LVL28:
1054 
 655              	.L58:
1055 
 656              	.LCFI20:
1056 
 657              		.cfi_restore_state
1057 
 297:Core/Src/stm32f1xx_hal_msp.c ****
1058 
 658              		.loc 1 297 5 is_stmt 1 view .LVU135
1059 
 659              	.LBB12:
1060 
 297:Core/Src/stm32f1xx_hal_msp.c ****
1061 
 660              		.loc 1 297 5 view .LVU136
1062 
 297:Core/Src/stm32f1xx_hal_msp.c ****
1063 
 661              		.loc 1 297 5 view .LVU137
1064 
 662 001c 03F50233 		add	r3, r3, #133120
1065 
 663 0020 DA69     		ldr	r2, [r3, #28]
1066 
 664 0022 42F00402 		orr	r2, r2, #4
1067 
 665 0026 DA61     		str	r2, [r3, #28]
1068 
 297:Core/Src/stm32f1xx_hal_msp.c ****
1069 
 666              		.loc 1 297 5 view .LVU138
1070 
 667 0028 DA69     		ldr	r2, [r3, #28]
1071 
 668 002a 02F00402 		and	r2, r2, #4
1072 
 669 002e 0092     		str	r2, [sp]
1073 
 297:Core/Src/stm32f1xx_hal_msp.c ****
1074 
 670              		.loc 1 297 5 view .LVU139
1075 
 671 0030 009A     		ldr	r2, [sp]
1076 
 672              	.LBE12:
1077 
 299:Core/Src/stm32f1xx_hal_msp.c ****     /**TIM4 GPIO Configuration
1078 
 673              		.loc 1 299 5 view .LVU140
1079 
 674              	.LBB13:
1080 
 299:Core/Src/stm32f1xx_hal_msp.c ****     /**TIM4 GPIO Configuration
20 mjames 1081 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 19
16 mjames 1082 
 
1083 
 
1084 
 675              		.loc 1 299 5 view .LVU141
1085 
 299:Core/Src/stm32f1xx_hal_msp.c ****     /**TIM4 GPIO Configuration
1086 
 676              		.loc 1 299 5 view .LVU142
1087 
 677 0032 9A69     		ldr	r2, [r3, #24]
1088 
 678 0034 42F00802 		orr	r2, r2, #8
1089 
 679 0038 9A61     		str	r2, [r3, #24]
1090 
 299:Core/Src/stm32f1xx_hal_msp.c ****     /**TIM4 GPIO Configuration
1091 
 680              		.loc 1 299 5 view .LVU143
1092 
 681 003a 9B69     		ldr	r3, [r3, #24]
1093 
 682 003c 03F00803 		and	r3, r3, #8
1094 
 683 0040 0193     		str	r3, [sp, #4]
1095 
 299:Core/Src/stm32f1xx_hal_msp.c ****     /**TIM4 GPIO Configuration
1096 
 684              		.loc 1 299 5 view .LVU144
1097 
 685 0042 019B     		ldr	r3, [sp, #4]
1098 
 686              	.LBE13:
1099 
 304:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
1100 
 687              		.loc 1 304 5 view .LVU145
1101 
 304:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
1102 
 688              		.loc 1 304 25 is_stmt 0 view .LVU146
1103 
 689 0044 C023     		movs	r3, #192
1104 
 690 0046 0293     		str	r3, [sp, #8]
1105 
 305:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_PULLUP;
1106 
 691              		.loc 1 305 5 is_stmt 1 view .LVU147
1107 
 306:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
1108 
 692              		.loc 1 306 5 view .LVU148
1109 
 306:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
1110 
 693              		.loc 1 306 26 is_stmt 0 view .LVU149
1111 
 694 0048 0123     		movs	r3, #1
1112 
 695 004a 0493     		str	r3, [sp, #16]
1113 
 307:Core/Src/stm32f1xx_hal_msp.c ****
1114 
 696              		.loc 1 307 5 is_stmt 1 view .LVU150
1115 
 697 004c 02A9     		add	r1, sp, #8
1116 
 698 004e 0348     		ldr	r0, .L59+4
1117 
 699              	.LVL29:
1118 
 307:Core/Src/stm32f1xx_hal_msp.c ****
1119 
 700              		.loc 1 307 5 is_stmt 0 view .LVU151
1120 
 701 0050 FFF7FEFF 		bl	HAL_GPIO_Init
1121 
 702              	.LVL30:
1122 
 703              		.loc 1 314 1 view .LVU152
1123 
 704 0054 DFE7     		b	.L55
1124 
 705              	.L60:
1125 
 706 0056 00BF     		.align	2
1126 
 707              	.L59:
1127 
 708 0058 00080040 		.word	1073743872
1128 
 709 005c 000C0140 		.word	1073810432
1129 
 710              		.cfi_endproc
1130 
 711              	.LFE73:
1131 
 713              		.section	.text.HAL_TIM_OC_MspDeInit,"ax",%progbits
1132 
 714              		.align	1
1133 
 715              		.global	HAL_TIM_OC_MspDeInit
1134 
 716              		.syntax unified
1135 
 717              		.thumb
1136 
 718              		.thumb_func
1137 
 719              		.fpu softvfp
1138 
 721              	HAL_TIM_OC_MspDeInit:
1139 
 722              	.LVL31:
1140 
 723              	.LFB74:
20 mjames 1141 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 20
16 mjames 1142 
 
1143 
 
1144 
 315:Core/Src/stm32f1xx_hal_msp.c ****
1145 
 316:Core/Src/stm32f1xx_hal_msp.c **** /**
1146 
 317:Core/Src/stm32f1xx_hal_msp.c **** * @brief TIM_OC MSP De-Initialization
1147 
 318:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
1148 
 319:Core/Src/stm32f1xx_hal_msp.c **** * @param htim_oc: TIM_OC handle pointer
1149 
 320:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
1150 
 321:Core/Src/stm32f1xx_hal_msp.c **** */
1151 
 322:Core/Src/stm32f1xx_hal_msp.c **** void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef* htim_oc)
1152 
 323:Core/Src/stm32f1xx_hal_msp.c **** {
1153 
 724              		.loc 1 323 1 is_stmt 1 view -0
1154 
 725              		.cfi_startproc
1155 
 726              		@ args = 0, pretend = 0, frame = 0
1156 
 727              		@ frame_needed = 0, uses_anonymous_args = 0
1157 
 728              		@ link register save eliminated.
1158 
 324:Core/Src/stm32f1xx_hal_msp.c ****   if(htim_oc->Instance==TIM3)
1159 
 729              		.loc 1 324 3 view .LVU154
1160 
 730              		.loc 1 324 13 is_stmt 0 view .LVU155
1161 
 731 0000 0268     		ldr	r2, [r0]
1162 
 732              		.loc 1 324 5 view .LVU156
1163 
 733 0002 054B     		ldr	r3, .L64
1164 
 734 0004 9A42     		cmp	r2, r3
1165 
 735 0006 00D0     		beq	.L63
1166 
 736              	.L61:
1167 
 325:Core/Src/stm32f1xx_hal_msp.c ****   {
1168 
 326:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspDeInit 0 */
1169 
 327:Core/Src/stm32f1xx_hal_msp.c ****
1170 
 328:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END TIM3_MspDeInit 0 */
1171 
 329:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock disable */
1172 
 330:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_TIM3_CLK_DISABLE();
1173 
 331:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspDeInit 1 */
1174 
 332:Core/Src/stm32f1xx_hal_msp.c ****
1175 
 333:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END TIM3_MspDeInit 1 */
1176 
 334:Core/Src/stm32f1xx_hal_msp.c ****   }
1177 
 335:Core/Src/stm32f1xx_hal_msp.c ****
1178 
 336:Core/Src/stm32f1xx_hal_msp.c **** }
1179 
 737              		.loc 1 336 1 view .LVU157
1180 
 738 0008 7047     		bx	lr
1181 
 739              	.L63:
1182 
 330:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN TIM3_MspDeInit 1 */
1183 
 740              		.loc 1 330 5 is_stmt 1 view .LVU158
1184 
 741 000a 044A     		ldr	r2, .L64+4
1185 
 742 000c D369     		ldr	r3, [r2, #28]
1186 
 743 000e 23F00203 		bic	r3, r3, #2
1187 
 744 0012 D361     		str	r3, [r2, #28]
1188 
 745              		.loc 1 336 1 is_stmt 0 view .LVU159
1189 
 746 0014 F8E7     		b	.L61
1190 
 747              	.L65:
1191 
 748 0016 00BF     		.align	2
1192 
 749              	.L64:
1193 
 750 0018 00040040 		.word	1073742848
1194 
 751 001c 00100240 		.word	1073876992
1195 
 752              		.cfi_endproc
1196 
 753              	.LFE74:
1197 
 755              		.section	.text.HAL_TIM_Encoder_MspDeInit,"ax",%progbits
1198 
 756              		.align	1
1199 
 757              		.global	HAL_TIM_Encoder_MspDeInit
1200 
 758              		.syntax unified
20 mjames 1201 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 21
16 mjames 1202 
 
1203 
 
1204 
 759              		.thumb
1205 
 760              		.thumb_func
1206 
 761              		.fpu softvfp
1207 
 763              	HAL_TIM_Encoder_MspDeInit:
1208 
 764              	.LVL32:
1209 
 765              	.LFB75:
1210 
 337:Core/Src/stm32f1xx_hal_msp.c ****
1211 
 338:Core/Src/stm32f1xx_hal_msp.c **** /**
1212 
 339:Core/Src/stm32f1xx_hal_msp.c **** * @brief TIM_Encoder MSP De-Initialization
1213 
 340:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
1214 
 341:Core/Src/stm32f1xx_hal_msp.c **** * @param htim_encoder: TIM_Encoder handle pointer
1215 
 342:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
1216 
 343:Core/Src/stm32f1xx_hal_msp.c **** */
1217 
 344:Core/Src/stm32f1xx_hal_msp.c **** void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder)
1218 
 345:Core/Src/stm32f1xx_hal_msp.c **** {
1219 
 766              		.loc 1 345 1 is_stmt 1 view -0
1220 
 767              		.cfi_startproc
1221 
 768              		@ args = 0, pretend = 0, frame = 0
1222 
 769              		@ frame_needed = 0, uses_anonymous_args = 0
1223 
 770              		.loc 1 345 1 is_stmt 0 view .LVU161
1224 
 771 0000 08B5     		push	{r3, lr}
1225 
 772              	.LCFI21:
1226 
 773              		.cfi_def_cfa_offset 8
1227 
 774              		.cfi_offset 3, -8
1228 
 775              		.cfi_offset 14, -4
1229 
 346:Core/Src/stm32f1xx_hal_msp.c ****   if(htim_encoder->Instance==TIM4)
1230 
 776              		.loc 1 346 3 is_stmt 1 view .LVU162
1231 
 777              		.loc 1 346 18 is_stmt 0 view .LVU163
1232 
 778 0002 0268     		ldr	r2, [r0]
1233 
 779              		.loc 1 346 5 view .LVU164
1234 
 780 0004 064B     		ldr	r3, .L70
1235 
 781 0006 9A42     		cmp	r2, r3
1236 
 782 0008 00D0     		beq	.L69
1237 
 783              	.LVL33:
1238 
 784              	.L66:
1239 
 347:Core/Src/stm32f1xx_hal_msp.c ****   {
1240 
 348:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN TIM4_MspDeInit 0 */
1241 
 349:Core/Src/stm32f1xx_hal_msp.c ****
1242 
 350:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END TIM4_MspDeInit 0 */
1243 
 351:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock disable */
1244 
 352:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_TIM4_CLK_DISABLE();
1245 
 353:Core/Src/stm32f1xx_hal_msp.c ****
1246 
 354:Core/Src/stm32f1xx_hal_msp.c ****     /**TIM4 GPIO Configuration
1247 
 355:Core/Src/stm32f1xx_hal_msp.c ****     PB6     ------> TIM4_CH1
1248 
 356:Core/Src/stm32f1xx_hal_msp.c ****     PB7     ------> TIM4_CH2
1249 
 357:Core/Src/stm32f1xx_hal_msp.c ****     */
1250 
 358:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
1251 
 359:Core/Src/stm32f1xx_hal_msp.c ****
1252 
 360:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN TIM4_MspDeInit 1 */
1253 
 361:Core/Src/stm32f1xx_hal_msp.c ****
1254 
 362:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END TIM4_MspDeInit 1 */
1255 
 363:Core/Src/stm32f1xx_hal_msp.c ****   }
1256 
 364:Core/Src/stm32f1xx_hal_msp.c ****
1257 
 365:Core/Src/stm32f1xx_hal_msp.c **** }
1258 
 785              		.loc 1 365 1 view .LVU165
1259 
 786 000a 08BD     		pop	{r3, pc}
1260 
 787              	.LVL34:
20 mjames 1261 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 22
16 mjames 1262 
 
1263 
 
1264 
 788              	.L69:
1265 
 352:Core/Src/stm32f1xx_hal_msp.c ****
1266 
 789              		.loc 1 352 5 is_stmt 1 view .LVU166
1267 
 790 000c 054A     		ldr	r2, .L70+4
1268 
 791 000e D369     		ldr	r3, [r2, #28]
1269 
 792 0010 23F00403 		bic	r3, r3, #4
1270 
 793 0014 D361     		str	r3, [r2, #28]
1271 
 358:Core/Src/stm32f1xx_hal_msp.c ****
1272 
 794              		.loc 1 358 5 view .LVU167
1273 
 795 0016 C021     		movs	r1, #192
1274 
 796 0018 0348     		ldr	r0, .L70+8
1275 
 797              	.LVL35:
1276 
 358:Core/Src/stm32f1xx_hal_msp.c ****
1277 
 798              		.loc 1 358 5 is_stmt 0 view .LVU168
1278 
 799 001a FFF7FEFF 		bl	HAL_GPIO_DeInit
1279 
 800              	.LVL36:
1280 
 801              		.loc 1 365 1 view .LVU169
1281 
 802 001e F4E7     		b	.L66
1282 
 803              	.L71:
1283 
 804              		.align	2
1284 
 805              	.L70:
1285 
 806 0020 00080040 		.word	1073743872
1286 
 807 0024 00100240 		.word	1073876992
1287 
 808 0028 000C0140 		.word	1073810432
1288 
 809              		.cfi_endproc
1289 
 810              	.LFE75:
1290 
 812              		.section	.text.HAL_UART_MspInit,"ax",%progbits
1291 
 813              		.align	1
1292 
 814              		.global	HAL_UART_MspInit
1293 
 815              		.syntax unified
1294 
 816              		.thumb
1295 
 817              		.thumb_func
1296 
 818              		.fpu softvfp
1297 
 820              	HAL_UART_MspInit:
1298 
 821              	.LVL37:
1299 
 822              	.LFB76:
1300 
 366:Core/Src/stm32f1xx_hal_msp.c ****
1301 
 367:Core/Src/stm32f1xx_hal_msp.c **** /**
1302 
 368:Core/Src/stm32f1xx_hal_msp.c **** * @brief UART MSP Initialization
1303 
 369:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
1304 
 370:Core/Src/stm32f1xx_hal_msp.c **** * @param huart: UART handle pointer
1305 
 371:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
1306 
 372:Core/Src/stm32f1xx_hal_msp.c **** */
1307 
 373:Core/Src/stm32f1xx_hal_msp.c **** void HAL_UART_MspInit(UART_HandleTypeDef* huart)
1308 
 374:Core/Src/stm32f1xx_hal_msp.c **** {
1309 
 823              		.loc 1 374 1 is_stmt 1 view -0
1310 
 824              		.cfi_startproc
1311 
 825              		@ args = 0, pretend = 0, frame = 24
1312 
 826              		@ frame_needed = 0, uses_anonymous_args = 0
1313 
 827              		.loc 1 374 1 is_stmt 0 view .LVU171
1314 
 828 0000 30B5     		push	{r4, r5, lr}
1315 
 829              	.LCFI22:
1316 
 830              		.cfi_def_cfa_offset 12
1317 
 831              		.cfi_offset 4, -12
1318 
 832              		.cfi_offset 5, -8
1319 
 833              		.cfi_offset 14, -4
1320 
 834 0002 87B0     		sub	sp, sp, #28
20 mjames 1321 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 23
16 mjames 1322 
 
1323 
 
1324 
 835              	.LCFI23:
1325 
 836              		.cfi_def_cfa_offset 40
1326 
 375:Core/Src/stm32f1xx_hal_msp.c ****   GPIO_InitTypeDef GPIO_InitStruct = {0};
1327 
 837              		.loc 1 375 3 is_stmt 1 view .LVU172
1328 
 838              		.loc 1 375 20 is_stmt 0 view .LVU173
1329 
 839 0004 0023     		movs	r3, #0
1330 
 840 0006 0293     		str	r3, [sp, #8]
1331 
 841 0008 0393     		str	r3, [sp, #12]
1332 
 842 000a 0493     		str	r3, [sp, #16]
1333 
 843 000c 0593     		str	r3, [sp, #20]
1334 
 376:Core/Src/stm32f1xx_hal_msp.c ****   if(huart->Instance==USART1)
1335 
 844              		.loc 1 376 3 is_stmt 1 view .LVU174
1336 
 845              		.loc 1 376 11 is_stmt 0 view .LVU175
1337 
 846 000e 0268     		ldr	r2, [r0]
1338 
 847              		.loc 1 376 5 view .LVU176
1339 
 848 0010 1B4B     		ldr	r3, .L76
1340 
 849 0012 9A42     		cmp	r2, r3
1341 
 850 0014 01D0     		beq	.L75
1342 
 851              	.LVL38:
1343 
 852              	.L72:
1344 
 377:Core/Src/stm32f1xx_hal_msp.c ****   {
1345 
 378:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspInit 0 */
1346 
 379:Core/Src/stm32f1xx_hal_msp.c ****
1347 
 380:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END USART1_MspInit 0 */
1348 
 381:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock enable */
1349 
 382:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_USART1_CLK_ENABLE();
1350 
 383:Core/Src/stm32f1xx_hal_msp.c ****
1351 
 384:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_GPIOA_CLK_ENABLE();
1352 
 385:Core/Src/stm32f1xx_hal_msp.c ****     /**USART1 GPIO Configuration
1353 
 386:Core/Src/stm32f1xx_hal_msp.c ****     PA9     ------> USART1_TX
1354 
 387:Core/Src/stm32f1xx_hal_msp.c ****     PA10     ------> USART1_RX
1355 
 388:Core/Src/stm32f1xx_hal_msp.c ****     */
1356 
 389:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_9;
1357 
 390:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1358 
 391:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
1359 
 392:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
1360 
 393:Core/Src/stm32f1xx_hal_msp.c ****
1361 
 394:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pin = GPIO_PIN_10;
1362 
 395:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
1363 
 396:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
1364 
 397:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
1365 
 398:Core/Src/stm32f1xx_hal_msp.c ****
1366 
 399:Core/Src/stm32f1xx_hal_msp.c ****     /* USART1 interrupt Init */
1367 
 400:Core/Src/stm32f1xx_hal_msp.c ****     HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
1368 
 401:Core/Src/stm32f1xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(USART1_IRQn);
1369 
 402:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspInit 1 */
1370 
 403:Core/Src/stm32f1xx_hal_msp.c ****
1371 
 404:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END USART1_MspInit 1 */
1372 
 405:Core/Src/stm32f1xx_hal_msp.c ****   }
1373 
 406:Core/Src/stm32f1xx_hal_msp.c ****
1374 
 407:Core/Src/stm32f1xx_hal_msp.c **** }
1375 
 853              		.loc 1 407 1 view .LVU177
1376 
 854 0016 07B0     		add	sp, sp, #28
1377 
 855              	.LCFI24:
1378 
 856              		.cfi_remember_state
1379 
 857              		.cfi_def_cfa_offset 12
1380 
 858              		@ sp needed
20 mjames 1381 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 24
16 mjames 1382 
 
1383 
 
1384 
 859 0018 30BD     		pop	{r4, r5, pc}
1385 
 860              	.LVL39:
1386 
 861              	.L75:
1387 
 862              	.LCFI25:
1388 
 863              		.cfi_restore_state
1389 
 382:Core/Src/stm32f1xx_hal_msp.c ****
1390 
 864              		.loc 1 382 5 is_stmt 1 view .LVU178
1391 
 865              	.LBB14:
1392 
 382:Core/Src/stm32f1xx_hal_msp.c ****
1393 
 866              		.loc 1 382 5 view .LVU179
1394 
 382:Core/Src/stm32f1xx_hal_msp.c ****
1395 
 867              		.loc 1 382 5 view .LVU180
1396 
 868 001a 03F55843 		add	r3, r3, #55296
1397 
 869 001e 9A69     		ldr	r2, [r3, #24]
1398 
 870 0020 42F48042 		orr	r2, r2, #16384
1399 
 871 0024 9A61     		str	r2, [r3, #24]
1400 
 382:Core/Src/stm32f1xx_hal_msp.c ****
1401 
 872              		.loc 1 382 5 view .LVU181
1402 
 873 0026 9A69     		ldr	r2, [r3, #24]
1403 
 874 0028 02F48042 		and	r2, r2, #16384
1404 
 875 002c 0092     		str	r2, [sp]
1405 
 382:Core/Src/stm32f1xx_hal_msp.c ****
1406 
 876              		.loc 1 382 5 view .LVU182
1407 
 877 002e 009A     		ldr	r2, [sp]
1408 
 878              	.LBE14:
1409 
 384:Core/Src/stm32f1xx_hal_msp.c ****     /**USART1 GPIO Configuration
1410 
 879              		.loc 1 384 5 view .LVU183
1411 
 880              	.LBB15:
1412 
 384:Core/Src/stm32f1xx_hal_msp.c ****     /**USART1 GPIO Configuration
1413 
 881              		.loc 1 384 5 view .LVU184
1414 
 384:Core/Src/stm32f1xx_hal_msp.c ****     /**USART1 GPIO Configuration
1415 
 882              		.loc 1 384 5 view .LVU185
1416 
 883 0030 9A69     		ldr	r2, [r3, #24]
1417 
 884 0032 42F00402 		orr	r2, r2, #4
1418 
 885 0036 9A61     		str	r2, [r3, #24]
1419 
 384:Core/Src/stm32f1xx_hal_msp.c ****     /**USART1 GPIO Configuration
1420 
 886              		.loc 1 384 5 view .LVU186
1421 
 887 0038 9B69     		ldr	r3, [r3, #24]
1422 
 888 003a 03F00403 		and	r3, r3, #4
1423 
 889 003e 0193     		str	r3, [sp, #4]
1424 
 384:Core/Src/stm32f1xx_hal_msp.c ****     /**USART1 GPIO Configuration
1425 
 890              		.loc 1 384 5 view .LVU187
1426 
 891 0040 019B     		ldr	r3, [sp, #4]
1427 
 892              	.LBE15:
1428 
 389:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1429 
 893              		.loc 1 389 5 view .LVU188
1430 
 389:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1431 
 894              		.loc 1 389 25 is_stmt 0 view .LVU189
1432 
 895 0042 4FF40073 		mov	r3, #512
1433 
 896 0046 0293     		str	r3, [sp, #8]
1434 
 390:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
1435 
 897              		.loc 1 390 5 is_stmt 1 view .LVU190
1436 
 390:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
1437 
 898              		.loc 1 390 26 is_stmt 0 view .LVU191
1438 
 899 0048 0223     		movs	r3, #2
1439 
 900 004a 0393     		str	r3, [sp, #12]
1440 
 391:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
20 mjames 1441 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 25
16 mjames 1442 
 
1443 
 
1444 
 901              		.loc 1 391 5 is_stmt 1 view .LVU192
1445 
 391:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
1446 
 902              		.loc 1 391 27 is_stmt 0 view .LVU193
1447 
 903 004c 0323     		movs	r3, #3
1448 
 904 004e 0593     		str	r3, [sp, #20]
1449 
 392:Core/Src/stm32f1xx_hal_msp.c ****
1450 
 905              		.loc 1 392 5 is_stmt 1 view .LVU194
1451 
 906 0050 0C4D     		ldr	r5, .L76+4
1452 
 907 0052 02A9     		add	r1, sp, #8
1453 
 908 0054 2846     		mov	r0, r5
1454 
 909              	.LVL40:
1455 
 392:Core/Src/stm32f1xx_hal_msp.c ****
1456 
 910              		.loc 1 392 5 is_stmt 0 view .LVU195
1457 
 911 0056 FFF7FEFF 		bl	HAL_GPIO_Init
1458 
 912              	.LVL41:
1459 
 394:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
1460 
 913              		.loc 1 394 5 is_stmt 1 view .LVU196
1461 
 394:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
1462 
 914              		.loc 1 394 25 is_stmt 0 view .LVU197
1463 
 915 005a 4FF48063 		mov	r3, #1024
1464 
 916 005e 0293     		str	r3, [sp, #8]
1465 
 395:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
1466 
 917              		.loc 1 395 5 is_stmt 1 view .LVU198
1467 
 395:Core/Src/stm32f1xx_hal_msp.c ****     GPIO_InitStruct.Pull = GPIO_NOPULL;
1468 
 918              		.loc 1 395 26 is_stmt 0 view .LVU199
1469 
 919 0060 0024     		movs	r4, #0
1470 
 920 0062 0394     		str	r4, [sp, #12]
1471 
 396:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
1472 
 921              		.loc 1 396 5 is_stmt 1 view .LVU200
1473 
 396:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
1474 
 922              		.loc 1 396 26 is_stmt 0 view .LVU201
1475 
 923 0064 0494     		str	r4, [sp, #16]
1476 
 397:Core/Src/stm32f1xx_hal_msp.c ****
1477 
 924              		.loc 1 397 5 is_stmt 1 view .LVU202
1478 
 925 0066 02A9     		add	r1, sp, #8
1479 
 926 0068 2846     		mov	r0, r5
1480 
 927 006a FFF7FEFF 		bl	HAL_GPIO_Init
1481 
 928              	.LVL42:
1482 
 400:Core/Src/stm32f1xx_hal_msp.c ****     HAL_NVIC_EnableIRQ(USART1_IRQn);
1483 
 929              		.loc 1 400 5 view .LVU203
1484 
 930 006e 2246     		mov	r2, r4
1485 
 931 0070 2146     		mov	r1, r4
1486 
 932 0072 2520     		movs	r0, #37
1487 
 933 0074 FFF7FEFF 		bl	HAL_NVIC_SetPriority
1488 
 934              	.LVL43:
1489 
 401:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspInit 1 */
1490 
 935              		.loc 1 401 5 view .LVU204
1491 
 936 0078 2520     		movs	r0, #37
1492 
 937 007a FFF7FEFF 		bl	HAL_NVIC_EnableIRQ
1493 
 938              	.LVL44:
1494 
 939              		.loc 1 407 1 is_stmt 0 view .LVU205
1495 
 940 007e CAE7     		b	.L72
1496 
 941              	.L77:
1497 
 942              		.align	2
1498 
 943              	.L76:
1499 
 944 0080 00380140 		.word	1073821696
1500 
 945 0084 00080140 		.word	1073809408
20 mjames 1501 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 26
16 mjames 1502 
 
1503 
 
1504 
 946              		.cfi_endproc
1505 
 947              	.LFE76:
1506 
 949              		.section	.text.HAL_UART_MspDeInit,"ax",%progbits
1507 
 950              		.align	1
1508 
 951              		.global	HAL_UART_MspDeInit
1509 
 952              		.syntax unified
1510 
 953              		.thumb
1511 
 954              		.thumb_func
1512 
 955              		.fpu softvfp
1513 
 957              	HAL_UART_MspDeInit:
1514 
 958              	.LVL45:
1515 
 959              	.LFB77:
1516 
 408:Core/Src/stm32f1xx_hal_msp.c ****
1517 
 409:Core/Src/stm32f1xx_hal_msp.c **** /**
1518 
 410:Core/Src/stm32f1xx_hal_msp.c **** * @brief UART MSP De-Initialization
1519 
 411:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
1520 
 412:Core/Src/stm32f1xx_hal_msp.c **** * @param huart: UART handle pointer
1521 
 413:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
1522 
 414:Core/Src/stm32f1xx_hal_msp.c **** */
1523 
 415:Core/Src/stm32f1xx_hal_msp.c **** void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
1524 
 416:Core/Src/stm32f1xx_hal_msp.c **** {
1525 
 960              		.loc 1 416 1 is_stmt 1 view -0
1526 
 961              		.cfi_startproc
1527 
 962              		@ args = 0, pretend = 0, frame = 0
1528 
 963              		@ frame_needed = 0, uses_anonymous_args = 0
1529 
 964              		.loc 1 416 1 is_stmt 0 view .LVU207
1530 
 965 0000 08B5     		push	{r3, lr}
1531 
 966              	.LCFI26:
1532 
 967              		.cfi_def_cfa_offset 8
1533 
 968              		.cfi_offset 3, -8
1534 
 969              		.cfi_offset 14, -4
1535 
 417:Core/Src/stm32f1xx_hal_msp.c ****   if(huart->Instance==USART1)
1536 
 970              		.loc 1 417 3 is_stmt 1 view .LVU208
1537 
 971              		.loc 1 417 11 is_stmt 0 view .LVU209
1538 
 972 0002 0268     		ldr	r2, [r0]
1539 
 973              		.loc 1 417 5 view .LVU210
1540 
 974 0004 084B     		ldr	r3, .L82
1541 
 975 0006 9A42     		cmp	r2, r3
1542 
 976 0008 00D0     		beq	.L81
1543 
 977              	.LVL46:
1544 
 978              	.L78:
1545 
 418:Core/Src/stm32f1xx_hal_msp.c ****   {
1546 
 419:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspDeInit 0 */
1547 
 420:Core/Src/stm32f1xx_hal_msp.c ****
1548 
 421:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END USART1_MspDeInit 0 */
1549 
 422:Core/Src/stm32f1xx_hal_msp.c ****     /* Peripheral clock disable */
1550 
 423:Core/Src/stm32f1xx_hal_msp.c ****     __HAL_RCC_USART1_CLK_DISABLE();
1551 
 424:Core/Src/stm32f1xx_hal_msp.c ****
1552 
 425:Core/Src/stm32f1xx_hal_msp.c ****     /**USART1 GPIO Configuration
1553 
 426:Core/Src/stm32f1xx_hal_msp.c ****     PA9     ------> USART1_TX
1554 
 427:Core/Src/stm32f1xx_hal_msp.c ****     PA10     ------> USART1_RX
1555 
 428:Core/Src/stm32f1xx_hal_msp.c ****     */
1556 
 429:Core/Src/stm32f1xx_hal_msp.c ****     HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
1557 
 430:Core/Src/stm32f1xx_hal_msp.c ****
1558 
 431:Core/Src/stm32f1xx_hal_msp.c ****     /* USART1 interrupt DeInit */
1559 
 432:Core/Src/stm32f1xx_hal_msp.c ****     HAL_NVIC_DisableIRQ(USART1_IRQn);
1560 
 433:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspDeInit 1 */
20 mjames 1561 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 27
16 mjames 1562 
 
1563 
 
1564 
 434:Core/Src/stm32f1xx_hal_msp.c ****
1565 
 435:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE END USART1_MspDeInit 1 */
1566 
 436:Core/Src/stm32f1xx_hal_msp.c ****   }
1567 
 437:Core/Src/stm32f1xx_hal_msp.c ****
1568 
 438:Core/Src/stm32f1xx_hal_msp.c **** }
1569 
 979              		.loc 1 438 1 view .LVU211
1570 
 980 000a 08BD     		pop	{r3, pc}
1571 
 981              	.LVL47:
1572 
 982              	.L81:
1573 
 423:Core/Src/stm32f1xx_hal_msp.c ****
1574 
 983              		.loc 1 423 5 is_stmt 1 view .LVU212
1575 
 984 000c 074A     		ldr	r2, .L82+4
1576 
 985 000e 9369     		ldr	r3, [r2, #24]
1577 
 986 0010 23F48043 		bic	r3, r3, #16384
1578 
 987 0014 9361     		str	r3, [r2, #24]
1579 
 429:Core/Src/stm32f1xx_hal_msp.c ****
1580 
 988              		.loc 1 429 5 view .LVU213
1581 
 989 0016 4FF4C061 		mov	r1, #1536
1582 
 990 001a 0548     		ldr	r0, .L82+8
1583 
 991              	.LVL48:
1584 
 429:Core/Src/stm32f1xx_hal_msp.c ****
1585 
 992              		.loc 1 429 5 is_stmt 0 view .LVU214
1586 
 993 001c FFF7FEFF 		bl	HAL_GPIO_DeInit
1587 
 994              	.LVL49:
1588 
 432:Core/Src/stm32f1xx_hal_msp.c ****   /* USER CODE BEGIN USART1_MspDeInit 1 */
1589 
 995              		.loc 1 432 5 is_stmt 1 view .LVU215
1590 
 996 0020 2520     		movs	r0, #37
1591 
 997 0022 FFF7FEFF 		bl	HAL_NVIC_DisableIRQ
1592 
 998              	.LVL50:
1593 
 999              		.loc 1 438 1 is_stmt 0 view .LVU216
1594 
 1000 0026 F0E7     		b	.L78
1595 
 1001              	.L83:
1596 
 1002              		.align	2
1597 
 1003              	.L82:
1598 
 1004 0028 00380140 		.word	1073821696
1599 
 1005 002c 00100240 		.word	1073876992
1600 
 1006 0030 00080140 		.word	1073809408
1601 
 1007              		.cfi_endproc
1602 
 1008              	.LFE77:
1603 
 1010              		.text
1604 
 1011              	.Letext0:
1605 
 1012              		.file 2 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7
1606 
 1013              		.file 3 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7
1607 
 1014              		.file 4 "Drivers/CMSIS/Include/core_cm3.h"
1608 
 1015              		.file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
1609 
 1016              		.file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
1610 
 1017              		.file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
1611 
 1018              		.file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h"
1612 
 1019              		.file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h"
1613 
 1020              		.file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h"
1614 
 1021              		.file 11 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h"
1615 
 1022              		.file 12 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h"
1616 
 1023              		.file 13 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h"
1617 
 1024              		.file 14 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h"
1618 
 1025              		.file 15 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h"
1619 
 1026              		.file 16 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
1620 
 1027              		.file 17 "Core/Inc/main.h"
20 mjames 1621 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 28
16 mjames 1622 
 
1623 
 
1624 
 1028              		.file 18 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h"
1625 
 1029              		.file 19 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h"
20 mjames 1626 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccpexaTP.s 			page 29
16 mjames 1627 
 
1628 
 
1629 
DEFINED SYMBOLS
1630 
                            *ABS*:0000000000000000 stm32f1xx_hal_msp.c
20 mjames 1631 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:16     .text.HAL_MspInit:0000000000000000 $t
1632 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:24     .text.HAL_MspInit:0000000000000000 HAL_MspInit
1633 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:88     .text.HAL_MspInit:000000000000003c $d
1634 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:94     .text.HAL_I2C_MspInit:0000000000000000 $t
1635 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:101    .text.HAL_I2C_MspInit:0000000000000000 HAL_I2C_MspInit
1636 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:211    .text.HAL_I2C_MspInit:000000000000006c $d
1637 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:218    .text.HAL_I2C_MspDeInit:0000000000000000 $t
1638 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:225    .text.HAL_I2C_MspDeInit:0000000000000000 HAL_I2C_MspDeInit
1639 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:270    .text.HAL_I2C_MspDeInit:0000000000000030 $d
1640 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:277    .text.HAL_RTC_MspInit:0000000000000000 $t
1641 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:284    .text.HAL_RTC_MspInit:0000000000000000 HAL_RTC_MspInit
1642 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:339    .text.HAL_RTC_MspInit:0000000000000034 $d
1643 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:346    .text.HAL_RTC_MspDeInit:0000000000000000 $t
1644 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:353    .text.HAL_RTC_MspDeInit:0000000000000000 HAL_RTC_MspDeInit
1645 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:381    .text.HAL_RTC_MspDeInit:0000000000000014 $d
1646 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:387    .text.HAL_SPI_MspInit:0000000000000000 $t
1647 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:394    .text.HAL_SPI_MspInit:0000000000000000 HAL_SPI_MspInit
1648 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:489    .text.HAL_SPI_MspInit:000000000000005c $d
1649 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:495    .text.HAL_SPI_MspDeInit:0000000000000000 $t
1650 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:502    .text.HAL_SPI_MspDeInit:0000000000000000 HAL_SPI_MspDeInit
1651 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:545    .text.HAL_SPI_MspDeInit:0000000000000020 $d
1652 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:552    .text.HAL_TIM_OC_MspInit:0000000000000000 $t
1653 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:559    .text.HAL_TIM_OC_MspInit:0000000000000000 HAL_TIM_OC_MspInit
1654 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:604    .text.HAL_TIM_OC_MspInit:0000000000000028 $d
1655 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:609    .text.HAL_TIM_Encoder_MspInit:0000000000000000 $t
1656 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:616    .text.HAL_TIM_Encoder_MspInit:0000000000000000 HAL_TIM_Encoder_MspInit
1657 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:708    .text.HAL_TIM_Encoder_MspInit:0000000000000058 $d
1658 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:714    .text.HAL_TIM_OC_MspDeInit:0000000000000000 $t
1659 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:721    .text.HAL_TIM_OC_MspDeInit:0000000000000000 HAL_TIM_OC_MspDeInit
1660 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:750    .text.HAL_TIM_OC_MspDeInit:0000000000000018 $d
1661 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:756    .text.HAL_TIM_Encoder_MspDeInit:0000000000000000 $t
1662 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:763    .text.HAL_TIM_Encoder_MspDeInit:0000000000000000 HAL_TIM_Encoder_MspDeInit
1663 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:806    .text.HAL_TIM_Encoder_MspDeInit:0000000000000020 $d
1664 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:813    .text.HAL_UART_MspInit:0000000000000000 $t
1665 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:820    .text.HAL_UART_MspInit:0000000000000000 HAL_UART_MspInit
1666 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:944    .text.HAL_UART_MspInit:0000000000000080 $d
1667 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:950    .text.HAL_UART_MspDeInit:0000000000000000 $t
1668 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:957    .text.HAL_UART_MspDeInit:0000000000000000 HAL_UART_MspDeInit
1669 
C:\Users\mike\AppData\Local\Temp\ccpexaTP.s:1004   .text.HAL_UART_MspDeInit:0000000000000028 $d
16 mjames 1670 
 
1671 
UNDEFINED SYMBOLS
1672 
HAL_GPIO_Init
1673 
HAL_GPIO_DeInit
1674 
HAL_PWR_EnableBkUpAccess
1675 
HAL_NVIC_SetPriority
1676 
HAL_NVIC_EnableIRQ
1677 
HAL_NVIC_DisableIRQ