Rev 19 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 20 | mjames | 1 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 1 |
| 16 | mjames | 2 | |
| 3 | |||
| 4 | 1 .cpu cortex-m3 |
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| 5 | 2 .eabi_attribute 20, 1 |
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| 6 | 3 .eabi_attribute 21, 1 |
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| 7 | 4 .eabi_attribute 23, 3 |
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| 8 | 5 .eabi_attribute 24, 1 |
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| 9 | 6 .eabi_attribute 25, 1 |
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| 10 | 7 .eabi_attribute 26, 1 |
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| 11 | 8 .eabi_attribute 30, 1 |
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| 12 | 9 .eabi_attribute 34, 1 |
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| 13 | 10 .eabi_attribute 18, 4 |
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| 14 | 11 .file "stm32f1xx_hal_cortex.c" |
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| 15 | 12 .text |
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| 16 | 13 .Ltext0: |
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| 17 | 14 .cfi_sections .debug_frame |
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| 18 | 15 .section .text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits |
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| 19 | 16 .align 1 |
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| 20 | 17 .global HAL_NVIC_SetPriorityGrouping |
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| 21 | 18 .arch armv7-m |
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| 22 | 19 .syntax unified |
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| 23 | 20 .thumb |
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| 24 | 21 .thumb_func |
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| 25 | 22 .fpu softvfp |
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| 26 | 24 HAL_NVIC_SetPriorityGrouping: |
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| 27 | 25 .LVL0: |
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| 28 | 26 .LFB65: |
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| 29 | 27 .file 1 "Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c" |
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| 30 | 1:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
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| 31 | 2:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ****************************************************************************** |
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| 32 | 3:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @file stm32f1xx_hal_cortex.c |
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| 33 | 4:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @author MCD Application Team |
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| 34 | 5:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief CORTEX HAL module driver. |
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| 35 | 6:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This file provides firmware functions to manage the following |
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| 36 | 7:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * functionalities of the CORTEX: |
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| 37 | 8:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * + Initialization and de-initialization functions |
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| 38 | 9:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * + Peripheral Control functions |
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| 39 | 10:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * |
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| 40 | 11:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @verbatim |
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| 41 | 12:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ============================================================================== |
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| 42 | 13:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ##### How to use this driver ##### |
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| 43 | 14:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ============================================================================== |
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| 44 | 15:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 45 | 16:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** [..] |
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| 46 | 17:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** |
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| 47 | 18:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** =========================================================== |
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| 48 | 19:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** [..] |
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| 49 | 20:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ). |
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| 50 | 21:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** The Cortex-M3 exceptions are managed by CMSIS functions. |
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| 51 | 22:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 52 | 23:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() |
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| 53 | 24:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** function according to the following table. |
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| 54 | 25:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). |
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| 55 | 26:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). |
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| 56 | 27:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (#) please refer to programming manual for details in how to configure priority. |
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| 57 | 28:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 58 | 29:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. |
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| 59 | 30:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority. |
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| 60 | 31:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 20 | mjames | 61 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 2 |
| 16 | mjames | 62 | |
| 63 | |||
| 64 | 32:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority): |
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| 65 | 33:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (+@) Lowest preemption priority |
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| 66 | 34:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (+@) Lowest sub priority |
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| 67 | 35:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (+@) Lowest hardware priority (IRQ number) |
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| 68 | 36:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 69 | 37:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** [..] |
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| 70 | 38:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver *** |
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| 71 | 39:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ======================================================== |
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| 72 | 40:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** [..] |
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| 73 | 41:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** Setup SysTick Timer for time base. |
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| 74 | 42:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 75 | 43:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which |
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| 76 | 44:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** is a CMSIS function that: |
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| 77 | 45:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. |
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| 78 | 46:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value 0x0F. |
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| 79 | 47:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (++) Resets the SysTick Counter register. |
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| 80 | 48:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). |
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| 81 | 49:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. |
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| 82 | 50:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (++) Starts the SysTick Counter. |
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| 83 | 51:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 84 | 52:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro |
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| 85 | 53:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the |
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| 86 | 54:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined |
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| 87 | 55:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** inside the stm32f1xx_hal_cortex.h file. |
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| 88 | 56:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 89 | 57:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the |
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| 90 | 58:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function |
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| 91 | 59:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct |
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| 92 | 60:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 93 | 61:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: |
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| 94 | 62:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 95 | 63:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) |
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| 96 | 64:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function |
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| 97 | 65:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF |
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| 98 | 66:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 99 | 67:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @endverbatim |
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| 100 | 68:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ****************************************************************************** |
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| 101 | 69:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @attention |
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| 102 | 70:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * |
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| 103 | 71:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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| 104 | 72:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * All rights reserved.</center></h2> |
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| 105 | 73:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * |
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| 106 | 74:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This software component is licensed by ST under BSD 3-Clause license, |
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| 107 | 75:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * the "License"; You may not use this file except in compliance with the |
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| 108 | 76:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * License. You may obtain a copy of the License at: |
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| 109 | 77:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * opensource.org/licenses/BSD-3-Clause |
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| 110 | 78:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * |
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| 111 | 79:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ****************************************************************************** |
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| 112 | 80:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
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| 113 | 81:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 114 | 82:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ |
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| 115 | 83:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** #include "stm32f1xx_hal.h" |
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| 116 | 84:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 117 | 85:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @addtogroup STM32F1xx_HAL_Driver |
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| 118 | 86:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @{ |
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| 119 | 87:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
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| 120 | 88:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 20 | mjames | 121 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 3 |
| 16 | mjames | 122 | |
| 123 | |||
| 124 | 89:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX |
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| 125 | 90:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief CORTEX HAL module driver |
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| 126 | 91:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @{ |
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| 127 | 92:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
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| 128 | 93:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 129 | 94:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED |
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| 130 | 95:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 131 | 96:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/ |
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| 132 | 97:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ |
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| 133 | 98:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/ |
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| 134 | 99:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/ |
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| 135 | 100:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/ |
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| 136 | 101:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/ |
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| 137 | 102:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 138 | 103:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions |
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| 139 | 104:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @{ |
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| 140 | 105:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
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| 141 | 106:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 142 | 107:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 143 | 108:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 144 | 109:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Initialization and Configuration functions |
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| 145 | 110:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * |
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| 146 | 111:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @verbatim |
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| 147 | 112:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ============================================================================== |
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| 148 | 113:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ##### Initialization and de-initialization functions ##### |
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| 149 | 114:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ============================================================================== |
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| 150 | 115:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** [..] |
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| 151 | 116:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts |
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| 152 | 117:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** Systick functionalities |
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| 153 | 118:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 154 | 119:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @endverbatim |
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| 155 | 120:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @{ |
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| 156 | 121:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
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| 157 | 122:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 158 | 123:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 159 | 124:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
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| 160 | 125:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Sets the priority grouping field (preemption priority and subpriority) |
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| 161 | 126:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * using the required unlock sequence. |
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| 162 | 127:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param PriorityGroup: The priority grouping bits length. |
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| 163 | 128:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be one of the following values: |
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| 164 | 129:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
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| 165 | 130:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 4 bits for subpriority |
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| 166 | 131:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
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| 167 | 132:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 3 bits for subpriority |
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| 168 | 133:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
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| 169 | 134:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 2 bits for subpriority |
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| 170 | 135:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
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| 171 | 136:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 1 bits for subpriority |
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| 172 | 137:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
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| 173 | 138:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 0 bits for subpriority |
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| 174 | 139:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. |
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| 175 | 140:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * The pending IRQ priority will be managed only by the subpriority. |
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| 176 | 141:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
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| 177 | 142:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
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| 178 | 143:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
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| 179 | 144:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
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| 180 | 28 .loc 1 144 1 view -0 |
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| 20 | mjames | 181 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 4 |
| 16 | mjames | 182 | |
| 183 | |||
| 184 | 29 .cfi_startproc |
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| 185 | 30 @ args = 0, pretend = 0, frame = 0 |
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| 186 | 31 @ frame_needed = 0, uses_anonymous_args = 0 |
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| 187 | 32 @ link register save eliminated. |
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| 188 | 145:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
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| 189 | 146:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
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| 190 | 33 .loc 1 146 3 view .LVU1 |
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| 191 | 147:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
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| 192 | 148:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ |
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| 193 | 149:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** NVIC_SetPriorityGrouping(PriorityGroup); |
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| 194 | 34 .loc 1 149 3 view .LVU2 |
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| 195 | 35 .LBB46: |
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| 196 | 36 .LBI46: |
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| 197 | 37 .file 2 "Drivers/CMSIS/Include/core_cm3.h" |
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| 198 | 1:Drivers/CMSIS/Include/core_cm3.h **** /**************************************************************************//** |
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| 199 | 2:Drivers/CMSIS/Include/core_cm3.h **** * @file core_cm3.h |
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| 200 | 3:Drivers/CMSIS/Include/core_cm3.h **** * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File |
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| 201 | 4:Drivers/CMSIS/Include/core_cm3.h **** * @version V5.0.8 |
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| 202 | 5:Drivers/CMSIS/Include/core_cm3.h **** * @date 04. June 2018 |
||
| 203 | 6:Drivers/CMSIS/Include/core_cm3.h **** ******************************************************************************/ |
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| 204 | 7:Drivers/CMSIS/Include/core_cm3.h **** /* |
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| 205 | 8:Drivers/CMSIS/Include/core_cm3.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
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| 206 | 9:Drivers/CMSIS/Include/core_cm3.h **** * |
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| 207 | 10:Drivers/CMSIS/Include/core_cm3.h **** * SPDX-License-Identifier: Apache-2.0 |
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| 208 | 11:Drivers/CMSIS/Include/core_cm3.h **** * |
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| 209 | 12:Drivers/CMSIS/Include/core_cm3.h **** * Licensed under the Apache License, Version 2.0 (the License); you may |
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| 210 | 13:Drivers/CMSIS/Include/core_cm3.h **** * not use this file except in compliance with the License. |
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| 211 | 14:Drivers/CMSIS/Include/core_cm3.h **** * You may obtain a copy of the License at |
||
| 212 | 15:Drivers/CMSIS/Include/core_cm3.h **** * |
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| 213 | 16:Drivers/CMSIS/Include/core_cm3.h **** * www.apache.org/licenses/LICENSE-2.0 |
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| 214 | 17:Drivers/CMSIS/Include/core_cm3.h **** * |
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| 215 | 18:Drivers/CMSIS/Include/core_cm3.h **** * Unless required by applicable law or agreed to in writing, software |
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| 216 | 19:Drivers/CMSIS/Include/core_cm3.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
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| 217 | 20:Drivers/CMSIS/Include/core_cm3.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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| 218 | 21:Drivers/CMSIS/Include/core_cm3.h **** * See the License for the specific language governing permissions and |
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| 219 | 22:Drivers/CMSIS/Include/core_cm3.h **** * limitations under the License. |
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| 220 | 23:Drivers/CMSIS/Include/core_cm3.h **** */ |
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| 221 | 24:Drivers/CMSIS/Include/core_cm3.h **** |
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| 222 | 25:Drivers/CMSIS/Include/core_cm3.h **** #if defined ( __ICCARM__ ) |
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| 223 | 26:Drivers/CMSIS/Include/core_cm3.h **** #pragma system_include /* treat file as system include file for MISRA check */ |
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| 224 | 27:Drivers/CMSIS/Include/core_cm3.h **** #elif defined (__clang__) |
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| 225 | 28:Drivers/CMSIS/Include/core_cm3.h **** #pragma clang system_header /* treat file as system include file */ |
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| 226 | 29:Drivers/CMSIS/Include/core_cm3.h **** #endif |
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| 227 | 30:Drivers/CMSIS/Include/core_cm3.h **** |
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| 228 | 31:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CORE_CM3_H_GENERIC |
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| 229 | 32:Drivers/CMSIS/Include/core_cm3.h **** #define __CORE_CM3_H_GENERIC |
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| 230 | 33:Drivers/CMSIS/Include/core_cm3.h **** |
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| 231 | 34:Drivers/CMSIS/Include/core_cm3.h **** #include <stdint.h> |
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| 232 | 35:Drivers/CMSIS/Include/core_cm3.h **** |
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| 233 | 36:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus |
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| 234 | 37:Drivers/CMSIS/Include/core_cm3.h **** extern "C" { |
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| 235 | 38:Drivers/CMSIS/Include/core_cm3.h **** #endif |
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| 236 | 39:Drivers/CMSIS/Include/core_cm3.h **** |
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| 237 | 40:Drivers/CMSIS/Include/core_cm3.h **** /** |
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| 238 | 41:Drivers/CMSIS/Include/core_cm3.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
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| 239 | 42:Drivers/CMSIS/Include/core_cm3.h **** CMSIS violates the following MISRA-C:2004 rules: |
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| 240 | 43:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 20 | mjames | 241 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 5 |
| 16 | mjames | 242 | |
| 243 | |||
| 244 | 44:Drivers/CMSIS/Include/core_cm3.h **** \li Required Rule 8.5, object/function definition in header file.<br> |
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| 245 | 45:Drivers/CMSIS/Include/core_cm3.h **** Function definitions in header files are used to allow 'inlining'. |
||
| 246 | 46:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 247 | 47:Drivers/CMSIS/Include/core_cm3.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
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| 248 | 48:Drivers/CMSIS/Include/core_cm3.h **** Unions are used for effective representation of core registers. |
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| 249 | 49:Drivers/CMSIS/Include/core_cm3.h **** |
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| 250 | 50:Drivers/CMSIS/Include/core_cm3.h **** \li Advisory Rule 19.7, Function-like macro defined.<br> |
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| 251 | 51:Drivers/CMSIS/Include/core_cm3.h **** Function-like macros are used to allow more efficient code. |
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| 252 | 52:Drivers/CMSIS/Include/core_cm3.h **** */ |
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| 253 | 53:Drivers/CMSIS/Include/core_cm3.h **** |
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| 254 | 54:Drivers/CMSIS/Include/core_cm3.h **** |
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| 255 | 55:Drivers/CMSIS/Include/core_cm3.h **** /******************************************************************************* |
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| 256 | 56:Drivers/CMSIS/Include/core_cm3.h **** * CMSIS definitions |
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| 257 | 57:Drivers/CMSIS/Include/core_cm3.h **** ******************************************************************************/ |
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| 258 | 58:Drivers/CMSIS/Include/core_cm3.h **** /** |
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| 259 | 59:Drivers/CMSIS/Include/core_cm3.h **** \ingroup Cortex_M3 |
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| 260 | 60:Drivers/CMSIS/Include/core_cm3.h **** @{ |
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| 261 | 61:Drivers/CMSIS/Include/core_cm3.h **** */ |
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| 262 | 62:Drivers/CMSIS/Include/core_cm3.h **** |
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| 263 | 63:Drivers/CMSIS/Include/core_cm3.h **** #include "cmsis_version.h" |
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| 264 | 64:Drivers/CMSIS/Include/core_cm3.h **** |
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| 265 | 65:Drivers/CMSIS/Include/core_cm3.h **** /* CMSIS CM3 definitions */ |
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| 266 | 66:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] C |
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| 267 | 67:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] C |
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| 268 | 68:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ |
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| 269 | 69:Drivers/CMSIS/Include/core_cm3.h **** __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL |
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| 270 | 70:Drivers/CMSIS/Include/core_cm3.h **** |
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| 271 | 71:Drivers/CMSIS/Include/core_cm3.h **** #define __CORTEX_M (3U) /*!< Cortex-M Core */ |
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| 272 | 72:Drivers/CMSIS/Include/core_cm3.h **** |
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| 273 | 73:Drivers/CMSIS/Include/core_cm3.h **** /** __FPU_USED indicates whether an FPU is used or not. |
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| 274 | 74:Drivers/CMSIS/Include/core_cm3.h **** This core does not support an FPU at all |
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| 275 | 75:Drivers/CMSIS/Include/core_cm3.h **** */ |
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| 276 | 76:Drivers/CMSIS/Include/core_cm3.h **** #define __FPU_USED 0U |
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| 277 | 77:Drivers/CMSIS/Include/core_cm3.h **** |
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| 278 | 78:Drivers/CMSIS/Include/core_cm3.h **** #if defined ( __CC_ARM ) |
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| 279 | 79:Drivers/CMSIS/Include/core_cm3.h **** #if defined __TARGET_FPU_VFP |
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| 280 | 80:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 281 | 81:Drivers/CMSIS/Include/core_cm3.h **** #endif |
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| 282 | 82:Drivers/CMSIS/Include/core_cm3.h **** |
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| 283 | 83:Drivers/CMSIS/Include/core_cm3.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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| 284 | 84:Drivers/CMSIS/Include/core_cm3.h **** #if defined __ARM_PCS_VFP |
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| 285 | 85:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 286 | 86:Drivers/CMSIS/Include/core_cm3.h **** #endif |
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| 287 | 87:Drivers/CMSIS/Include/core_cm3.h **** |
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| 288 | 88:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __GNUC__ ) |
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| 289 | 89:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
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| 290 | 90:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 291 | 91:Drivers/CMSIS/Include/core_cm3.h **** #endif |
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| 292 | 92:Drivers/CMSIS/Include/core_cm3.h **** |
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| 293 | 93:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __ICCARM__ ) |
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| 294 | 94:Drivers/CMSIS/Include/core_cm3.h **** #if defined __ARMVFP__ |
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| 295 | 95:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 296 | 96:Drivers/CMSIS/Include/core_cm3.h **** #endif |
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| 297 | 97:Drivers/CMSIS/Include/core_cm3.h **** |
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| 298 | 98:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __TI_ARM__ ) |
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| 299 | 99:Drivers/CMSIS/Include/core_cm3.h **** #if defined __TI_VFP_SUPPORT__ |
||
| 300 | 100:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||
| 20 | mjames | 301 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 6 |
| 16 | mjames | 302 | |
| 303 | |||
| 304 | 101:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 305 | 102:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 306 | 103:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __TASKING__ ) |
||
| 307 | 104:Drivers/CMSIS/Include/core_cm3.h **** #if defined __FPU_VFP__ |
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| 308 | 105:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 309 | 106:Drivers/CMSIS/Include/core_cm3.h **** #endif |
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| 310 | 107:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 311 | 108:Drivers/CMSIS/Include/core_cm3.h **** #elif defined ( __CSMC__ ) |
||
| 312 | 109:Drivers/CMSIS/Include/core_cm3.h **** #if ( __CSMC__ & 0x400U) |
||
| 313 | 110:Drivers/CMSIS/Include/core_cm3.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||
| 314 | 111:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 315 | 112:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 316 | 113:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 317 | 114:Drivers/CMSIS/Include/core_cm3.h **** |
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| 318 | 115:Drivers/CMSIS/Include/core_cm3.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
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| 319 | 116:Drivers/CMSIS/Include/core_cm3.h **** |
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| 320 | 117:Drivers/CMSIS/Include/core_cm3.h **** |
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| 321 | 118:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus |
||
| 322 | 119:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 323 | 120:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 324 | 121:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 325 | 122:Drivers/CMSIS/Include/core_cm3.h **** #endif /* __CORE_CM3_H_GENERIC */ |
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| 326 | 123:Drivers/CMSIS/Include/core_cm3.h **** |
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| 327 | 124:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CMSIS_GENERIC |
||
| 328 | 125:Drivers/CMSIS/Include/core_cm3.h **** |
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| 329 | 126:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CORE_CM3_H_DEPENDANT |
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| 330 | 127:Drivers/CMSIS/Include/core_cm3.h **** #define __CORE_CM3_H_DEPENDANT |
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| 331 | 128:Drivers/CMSIS/Include/core_cm3.h **** |
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| 332 | 129:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus |
||
| 333 | 130:Drivers/CMSIS/Include/core_cm3.h **** extern "C" { |
||
| 334 | 131:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 335 | 132:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 336 | 133:Drivers/CMSIS/Include/core_cm3.h **** /* check device defines and use defaults */ |
||
| 337 | 134:Drivers/CMSIS/Include/core_cm3.h **** #if defined __CHECK_DEVICE_DEFINES |
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| 338 | 135:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __CM3_REV |
||
| 339 | 136:Drivers/CMSIS/Include/core_cm3.h **** #define __CM3_REV 0x0200U |
||
| 340 | 137:Drivers/CMSIS/Include/core_cm3.h **** #warning "__CM3_REV not defined in device header file; using default!" |
||
| 341 | 138:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 342 | 139:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 343 | 140:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __MPU_PRESENT |
||
| 344 | 141:Drivers/CMSIS/Include/core_cm3.h **** #define __MPU_PRESENT 0U |
||
| 345 | 142:Drivers/CMSIS/Include/core_cm3.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" |
||
| 346 | 143:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 347 | 144:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 348 | 145:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __NVIC_PRIO_BITS |
||
| 349 | 146:Drivers/CMSIS/Include/core_cm3.h **** #define __NVIC_PRIO_BITS 3U |
||
| 350 | 147:Drivers/CMSIS/Include/core_cm3.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||
| 351 | 148:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 352 | 149:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 353 | 150:Drivers/CMSIS/Include/core_cm3.h **** #ifndef __Vendor_SysTickConfig |
||
| 354 | 151:Drivers/CMSIS/Include/core_cm3.h **** #define __Vendor_SysTickConfig 0U |
||
| 355 | 152:Drivers/CMSIS/Include/core_cm3.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||
| 356 | 153:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 357 | 154:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 358 | 155:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 359 | 156:Drivers/CMSIS/Include/core_cm3.h **** /* IO definitions (access restrictions to peripheral registers) */ |
||
| 360 | 157:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 20 | mjames | 361 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 7 |
| 16 | mjames | 362 | |
| 363 | |||
| 364 | 158:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines |
||
| 365 | 159:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 366 | 160:Drivers/CMSIS/Include/core_cm3.h **** <strong>IO Type Qualifiers</strong> are used |
||
| 367 | 161:Drivers/CMSIS/Include/core_cm3.h **** \li to specify the access to peripheral variables. |
||
| 368 | 162:Drivers/CMSIS/Include/core_cm3.h **** \li for automatic generation of peripheral register debug information. |
||
| 369 | 163:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 370 | 164:Drivers/CMSIS/Include/core_cm3.h **** #ifdef __cplusplus |
||
| 371 | 165:Drivers/CMSIS/Include/core_cm3.h **** #define __I volatile /*!< Defines 'read only' permissions */ |
||
| 372 | 166:Drivers/CMSIS/Include/core_cm3.h **** #else |
||
| 373 | 167:Drivers/CMSIS/Include/core_cm3.h **** #define __I volatile const /*!< Defines 'read only' permissions */ |
||
| 374 | 168:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 375 | 169:Drivers/CMSIS/Include/core_cm3.h **** #define __O volatile /*!< Defines 'write only' permissions */ |
||
| 376 | 170:Drivers/CMSIS/Include/core_cm3.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ |
||
| 377 | 171:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 378 | 172:Drivers/CMSIS/Include/core_cm3.h **** /* following defines should be used for structure members */ |
||
| 379 | 173:Drivers/CMSIS/Include/core_cm3.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||
| 380 | 174:Drivers/CMSIS/Include/core_cm3.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ |
||
| 381 | 175:Drivers/CMSIS/Include/core_cm3.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||
| 382 | 176:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 383 | 177:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group Cortex_M3 */ |
||
| 384 | 178:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 385 | 179:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 386 | 180:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 387 | 181:Drivers/CMSIS/Include/core_cm3.h **** /******************************************************************************* |
||
| 388 | 182:Drivers/CMSIS/Include/core_cm3.h **** * Register Abstraction |
||
| 389 | 183:Drivers/CMSIS/Include/core_cm3.h **** Core Register contain: |
||
| 390 | 184:Drivers/CMSIS/Include/core_cm3.h **** - Core Register |
||
| 391 | 185:Drivers/CMSIS/Include/core_cm3.h **** - Core NVIC Register |
||
| 392 | 186:Drivers/CMSIS/Include/core_cm3.h **** - Core SCB Register |
||
| 393 | 187:Drivers/CMSIS/Include/core_cm3.h **** - Core SysTick Register |
||
| 394 | 188:Drivers/CMSIS/Include/core_cm3.h **** - Core Debug Register |
||
| 395 | 189:Drivers/CMSIS/Include/core_cm3.h **** - Core MPU Register |
||
| 396 | 190:Drivers/CMSIS/Include/core_cm3.h **** ******************************************************************************/ |
||
| 397 | 191:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 398 | 192:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_core_register Defines and Type Definitions |
||
| 399 | 193:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions and defines for Cortex-M processor based devices. |
||
| 400 | 194:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 401 | 195:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 402 | 196:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 403 | 197:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 404 | 198:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_CORE Status and Control Registers |
||
| 405 | 199:Drivers/CMSIS/Include/core_cm3.h **** \brief Core Register type definitions. |
||
| 406 | 200:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 407 | 201:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 408 | 202:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 409 | 203:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 410 | 204:Drivers/CMSIS/Include/core_cm3.h **** \brief Union type to access the Application Program Status Register (APSR). |
||
| 411 | 205:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 412 | 206:Drivers/CMSIS/Include/core_cm3.h **** typedef union |
||
| 413 | 207:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 414 | 208:Drivers/CMSIS/Include/core_cm3.h **** struct |
||
| 415 | 209:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 416 | 210:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ |
||
| 417 | 211:Drivers/CMSIS/Include/core_cm3.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
||
| 418 | 212:Drivers/CMSIS/Include/core_cm3.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||
| 419 | 213:Drivers/CMSIS/Include/core_cm3.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||
| 420 | 214:Drivers/CMSIS/Include/core_cm3.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||
| 20 | mjames | 421 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 8 |
| 16 | mjames | 422 | |
| 423 | |||
| 424 | 215:Drivers/CMSIS/Include/core_cm3.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||
| 425 | 216:Drivers/CMSIS/Include/core_cm3.h **** } b; /*!< Structure used for bit access */ |
||
| 426 | 217:Drivers/CMSIS/Include/core_cm3.h **** uint32_t w; /*!< Type used for word access */ |
||
| 427 | 218:Drivers/CMSIS/Include/core_cm3.h **** } APSR_Type; |
||
| 428 | 219:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 429 | 220:Drivers/CMSIS/Include/core_cm3.h **** /* APSR Register Definitions */ |
||
| 430 | 221:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_N_Pos 31U /*!< APSR |
||
| 431 | 222:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR |
||
| 432 | 223:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 433 | 224:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Z_Pos 30U /*!< APSR |
||
| 434 | 225:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR |
||
| 435 | 226:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 436 | 227:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_C_Pos 29U /*!< APSR |
||
| 437 | 228:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR |
||
| 438 | 229:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 439 | 230:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_V_Pos 28U /*!< APSR |
||
| 440 | 231:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR |
||
| 441 | 232:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 442 | 233:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Q_Pos 27U /*!< APSR |
||
| 443 | 234:Drivers/CMSIS/Include/core_cm3.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR |
||
| 444 | 235:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 445 | 236:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 446 | 237:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 447 | 238:Drivers/CMSIS/Include/core_cm3.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). |
||
| 448 | 239:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 449 | 240:Drivers/CMSIS/Include/core_cm3.h **** typedef union |
||
| 450 | 241:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 451 | 242:Drivers/CMSIS/Include/core_cm3.h **** struct |
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| 452 | 243:Drivers/CMSIS/Include/core_cm3.h **** { |
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| 453 | 244:Drivers/CMSIS/Include/core_cm3.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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| 454 | 245:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
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| 455 | 246:Drivers/CMSIS/Include/core_cm3.h **** } b; /*!< Structure used for bit access */ |
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| 456 | 247:Drivers/CMSIS/Include/core_cm3.h **** uint32_t w; /*!< Type used for word access */ |
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| 457 | 248:Drivers/CMSIS/Include/core_cm3.h **** } IPSR_Type; |
||
| 458 | 249:Drivers/CMSIS/Include/core_cm3.h **** |
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| 459 | 250:Drivers/CMSIS/Include/core_cm3.h **** /* IPSR Register Definitions */ |
||
| 460 | 251:Drivers/CMSIS/Include/core_cm3.h **** #define IPSR_ISR_Pos 0U /*!< IPSR |
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| 461 | 252:Drivers/CMSIS/Include/core_cm3.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR |
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| 462 | 253:Drivers/CMSIS/Include/core_cm3.h **** |
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| 463 | 254:Drivers/CMSIS/Include/core_cm3.h **** |
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| 464 | 255:Drivers/CMSIS/Include/core_cm3.h **** /** |
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| 465 | 256:Drivers/CMSIS/Include/core_cm3.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
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| 466 | 257:Drivers/CMSIS/Include/core_cm3.h **** */ |
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| 467 | 258:Drivers/CMSIS/Include/core_cm3.h **** typedef union |
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| 468 | 259:Drivers/CMSIS/Include/core_cm3.h **** { |
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| 469 | 260:Drivers/CMSIS/Include/core_cm3.h **** struct |
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| 470 | 261:Drivers/CMSIS/Include/core_cm3.h **** { |
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| 471 | 262:Drivers/CMSIS/Include/core_cm3.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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| 472 | 263:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ |
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| 473 | 264:Drivers/CMSIS/Include/core_cm3.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ |
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| 474 | 265:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ |
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| 475 | 266:Drivers/CMSIS/Include/core_cm3.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ |
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| 476 | 267:Drivers/CMSIS/Include/core_cm3.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ |
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| 477 | 268:Drivers/CMSIS/Include/core_cm3.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
||
| 478 | 269:Drivers/CMSIS/Include/core_cm3.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||
| 479 | 270:Drivers/CMSIS/Include/core_cm3.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||
| 480 | 271:Drivers/CMSIS/Include/core_cm3.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||
| 20 | mjames | 481 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 9 |
| 16 | mjames | 482 | |
| 483 | |||
| 484 | 272:Drivers/CMSIS/Include/core_cm3.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||
| 485 | 273:Drivers/CMSIS/Include/core_cm3.h **** } b; /*!< Structure used for bit access */ |
||
| 486 | 274:Drivers/CMSIS/Include/core_cm3.h **** uint32_t w; /*!< Type used for word access */ |
||
| 487 | 275:Drivers/CMSIS/Include/core_cm3.h **** } xPSR_Type; |
||
| 488 | 276:Drivers/CMSIS/Include/core_cm3.h **** |
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| 489 | 277:Drivers/CMSIS/Include/core_cm3.h **** /* xPSR Register Definitions */ |
||
| 490 | 278:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_N_Pos 31U /*!< xPSR |
||
| 491 | 279:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR |
||
| 492 | 280:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 493 | 281:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Z_Pos 30U /*!< xPSR |
||
| 494 | 282:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR |
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| 495 | 283:Drivers/CMSIS/Include/core_cm3.h **** |
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| 496 | 284:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_C_Pos 29U /*!< xPSR |
||
| 497 | 285:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR |
||
| 498 | 286:Drivers/CMSIS/Include/core_cm3.h **** |
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| 499 | 287:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_V_Pos 28U /*!< xPSR |
||
| 500 | 288:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR |
||
| 501 | 289:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 502 | 290:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Q_Pos 27U /*!< xPSR |
||
| 503 | 291:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR |
||
| 504 | 292:Drivers/CMSIS/Include/core_cm3.h **** |
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| 505 | 293:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR |
||
| 506 | 294:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR |
||
| 507 | 295:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 508 | 296:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_T_Pos 24U /*!< xPSR |
||
| 509 | 297:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR |
||
| 510 | 298:Drivers/CMSIS/Include/core_cm3.h **** |
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| 511 | 299:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR |
||
| 512 | 300:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR |
||
| 513 | 301:Drivers/CMSIS/Include/core_cm3.h **** |
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| 514 | 302:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ISR_Pos 0U /*!< xPSR |
||
| 515 | 303:Drivers/CMSIS/Include/core_cm3.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR |
||
| 516 | 304:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 517 | 305:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 518 | 306:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 519 | 307:Drivers/CMSIS/Include/core_cm3.h **** \brief Union type to access the Control Registers (CONTROL). |
||
| 520 | 308:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 521 | 309:Drivers/CMSIS/Include/core_cm3.h **** typedef union |
||
| 522 | 310:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 523 | 311:Drivers/CMSIS/Include/core_cm3.h **** struct |
||
| 524 | 312:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 525 | 313:Drivers/CMSIS/Include/core_cm3.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
||
| 526 | 314:Drivers/CMSIS/Include/core_cm3.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||
| 527 | 315:Drivers/CMSIS/Include/core_cm3.h **** uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||
| 528 | 316:Drivers/CMSIS/Include/core_cm3.h **** } b; /*!< Structure used for bit access */ |
||
| 529 | 317:Drivers/CMSIS/Include/core_cm3.h **** uint32_t w; /*!< Type used for word access */ |
||
| 530 | 318:Drivers/CMSIS/Include/core_cm3.h **** } CONTROL_Type; |
||
| 531 | 319:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 532 | 320:Drivers/CMSIS/Include/core_cm3.h **** /* CONTROL Register Definitions */ |
||
| 533 | 321:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT |
||
| 534 | 322:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT |
||
| 535 | 323:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 536 | 324:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT |
||
| 537 | 325:Drivers/CMSIS/Include/core_cm3.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT |
||
| 538 | 326:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 539 | 327:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_CORE */ |
||
| 540 | 328:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 20 | mjames | 541 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 10 |
| 16 | mjames | 542 | |
| 543 | |||
| 544 | 329:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 545 | 330:Drivers/CMSIS/Include/core_cm3.h **** /** |
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| 546 | 331:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 547 | 332:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||
| 548 | 333:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the NVIC Registers |
||
| 549 | 334:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 550 | 335:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 551 | 336:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 552 | 337:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 553 | 338:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||
| 554 | 339:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 555 | 340:Drivers/CMSIS/Include/core_cm3.h **** typedef struct |
||
| 556 | 341:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 557 | 342:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||
| 558 | 343:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[24U]; |
||
| 559 | 344:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register |
||
| 560 | 345:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RSERVED1[24U]; |
||
| 561 | 346:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * |
||
| 562 | 347:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED2[24U]; |
||
| 563 | 348:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register |
||
| 564 | 349:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED3[24U]; |
||
| 565 | 350:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
||
| 566 | 351:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED4[56U]; |
||
| 567 | 352:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi |
||
| 568 | 353:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED5[644U]; |
||
| 569 | 354:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis |
||
| 570 | 355:Drivers/CMSIS/Include/core_cm3.h **** } NVIC_Type; |
||
| 571 | 356:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 572 | 357:Drivers/CMSIS/Include/core_cm3.h **** /* Software Triggered Interrupt Register Definitions */ |
||
| 573 | 358:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I |
||
| 574 | 359:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I |
||
| 575 | 360:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 576 | 361:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_NVIC */ |
||
| 577 | 362:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 578 | 363:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 579 | 364:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 580 | 365:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 581 | 366:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_SCB System Control Block (SCB) |
||
| 582 | 367:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the System Control Block Registers |
||
| 583 | 368:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 584 | 369:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 585 | 370:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 586 | 371:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 587 | 372:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the System Control Block (SCB). |
||
| 588 | 373:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 589 | 374:Drivers/CMSIS/Include/core_cm3.h **** typedef struct |
||
| 590 | 375:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 591 | 376:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||
| 592 | 377:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi |
||
| 593 | 378:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
||
| 594 | 379:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset |
||
| 595 | 380:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||
| 596 | 381:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * |
||
| 597 | 382:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe |
||
| 598 | 383:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State |
||
| 599 | 384:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist |
||
| 600 | 385:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
||
| 20 | mjames | 601 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 11 |
| 16 | mjames | 602 | |
| 603 | |||
| 604 | 386:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
||
| 605 | 387:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register |
||
| 606 | 388:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
||
| 607 | 389:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register |
||
| 608 | 390:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
||
| 609 | 391:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
||
| 610 | 392:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
||
| 611 | 393:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
||
| 612 | 394:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis |
||
| 613 | 395:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[5U]; |
||
| 614 | 396:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis |
||
| 615 | 397:Drivers/CMSIS/Include/core_cm3.h **** } SCB_Type; |
||
| 616 | 398:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 617 | 399:Drivers/CMSIS/Include/core_cm3.h **** /* SCB CPUID Register Definitions */ |
||
| 618 | 400:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB |
||
| 619 | 401:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB |
||
| 620 | 402:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 621 | 403:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB |
||
| 622 | 404:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB |
||
| 623 | 405:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 624 | 406:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB |
||
| 625 | 407:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB |
||
| 626 | 408:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 627 | 409:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB |
||
| 628 | 410:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB |
||
| 629 | 411:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 630 | 412:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB |
||
| 631 | 413:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB |
||
| 632 | 414:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 633 | 415:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Interrupt Control State Register Definitions */ |
||
| 634 | 416:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB |
||
| 635 | 417:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB |
||
| 636 | 418:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 637 | 419:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB |
||
| 638 | 420:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB |
||
| 639 | 421:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 640 | 422:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB |
||
| 641 | 423:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB |
||
| 642 | 424:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 643 | 425:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB |
||
| 644 | 426:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB |
||
| 645 | 427:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 646 | 428:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB |
||
| 647 | 429:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB |
||
| 648 | 430:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 649 | 431:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB |
||
| 650 | 432:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB |
||
| 651 | 433:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 652 | 434:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB |
||
| 653 | 435:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB |
||
| 654 | 436:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 655 | 437:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB |
||
| 656 | 438:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB |
||
| 657 | 439:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 658 | 440:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB |
||
| 659 | 441:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB |
||
| 660 | 442:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 20 | mjames | 661 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 12 |
| 16 | mjames | 662 | |
| 663 | |||
| 664 | 443:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB |
||
| 665 | 444:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB |
||
| 666 | 445:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 667 | 446:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Vector Table Offset Register Definitions */ |
||
| 668 | 447:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ |
||
| 669 | 448:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB |
||
| 670 | 449:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB |
||
| 671 | 450:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 672 | 451:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB |
||
| 673 | 452:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB |
||
| 674 | 453:Drivers/CMSIS/Include/core_cm3.h **** #else |
||
| 675 | 454:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB |
||
| 676 | 455:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB |
||
| 677 | 456:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 678 | 457:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 679 | 458:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ |
||
| 680 | 459:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB |
||
| 681 | 460:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB |
||
| 682 | 461:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 683 | 462:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB |
||
| 684 | 463:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB |
||
| 685 | 464:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 686 | 465:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB |
||
| 687 | 466:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB |
||
| 688 | 467:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 689 | 468:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB |
||
| 690 | 469:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB |
||
| 691 | 470:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 692 | 471:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB |
||
| 693 | 472:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB |
||
| 694 | 473:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 695 | 474:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB |
||
| 696 | 475:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB |
||
| 697 | 476:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 698 | 477:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB |
||
| 699 | 478:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB |
||
| 700 | 479:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 701 | 480:Drivers/CMSIS/Include/core_cm3.h **** /* SCB System Control Register Definitions */ |
||
| 702 | 481:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB |
||
| 703 | 482:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB |
||
| 704 | 483:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 705 | 484:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB |
||
| 706 | 485:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB |
||
| 707 | 486:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 708 | 487:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB |
||
| 709 | 488:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB |
||
| 710 | 489:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 711 | 490:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Configuration Control Register Definitions */ |
||
| 712 | 491:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB |
||
| 713 | 492:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB |
||
| 714 | 493:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 715 | 494:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB |
||
| 716 | 495:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB |
||
| 717 | 496:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 718 | 497:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB |
||
| 719 | 498:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB |
||
| 720 | 499:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 20 | mjames | 721 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 13 |
| 16 | mjames | 722 | |
| 723 | |||
| 724 | 500:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB |
||
| 725 | 501:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB |
||
| 726 | 502:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 727 | 503:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB |
||
| 728 | 504:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB |
||
| 729 | 505:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 730 | 506:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB |
||
| 731 | 507:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB |
||
| 732 | 508:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 733 | 509:Drivers/CMSIS/Include/core_cm3.h **** /* SCB System Handler Control and State Register Definitions */ |
||
| 734 | 510:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB |
||
| 735 | 511:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB |
||
| 736 | 512:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 737 | 513:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB |
||
| 738 | 514:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB |
||
| 739 | 515:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 740 | 516:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB |
||
| 741 | 517:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB |
||
| 742 | 518:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 743 | 519:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB |
||
| 744 | 520:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB |
||
| 745 | 521:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 746 | 522:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB |
||
| 747 | 523:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB |
||
| 748 | 524:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 749 | 525:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB |
||
| 750 | 526:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB |
||
| 751 | 527:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 752 | 528:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB |
||
| 753 | 529:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB |
||
| 754 | 530:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 755 | 531:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB |
||
| 756 | 532:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB |
||
| 757 | 533:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 758 | 534:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB |
||
| 759 | 535:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB |
||
| 760 | 536:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 761 | 537:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB |
||
| 762 | 538:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB |
||
| 763 | 539:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 764 | 540:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB |
||
| 765 | 541:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB |
||
| 766 | 542:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 767 | 543:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB |
||
| 768 | 544:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB |
||
| 769 | 545:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 770 | 546:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB |
||
| 771 | 547:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB |
||
| 772 | 548:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 773 | 549:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB |
||
| 774 | 550:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB |
||
| 775 | 551:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 776 | 552:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Configurable Fault Status Register Definitions */ |
||
| 777 | 553:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB |
||
| 778 | 554:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB |
||
| 779 | 555:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 780 | 556:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB |
||
| 20 | mjames | 781 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 14 |
| 16 | mjames | 782 | |
| 783 | |||
| 784 | 557:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB |
||
| 785 | 558:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 786 | 559:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB |
||
| 787 | 560:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB |
||
| 788 | 561:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 789 | 562:Drivers/CMSIS/Include/core_cm3.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ |
||
| 790 | 563:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB |
||
| 791 | 564:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB |
||
| 792 | 565:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 793 | 566:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB |
||
| 794 | 567:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB |
||
| 795 | 568:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 796 | 569:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB |
||
| 797 | 570:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB |
||
| 798 | 571:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 799 | 572:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB |
||
| 800 | 573:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB |
||
| 801 | 574:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 802 | 575:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB |
||
| 803 | 576:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB |
||
| 804 | 577:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 805 | 578:Drivers/CMSIS/Include/core_cm3.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ |
||
| 806 | 579:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB |
||
| 807 | 580:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB |
||
| 808 | 581:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 809 | 582:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB |
||
| 810 | 583:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB |
||
| 811 | 584:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 812 | 585:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB |
||
| 813 | 586:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB |
||
| 814 | 587:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 815 | 588:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB |
||
| 816 | 589:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB |
||
| 817 | 590:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 818 | 591:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB |
||
| 819 | 592:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB |
||
| 820 | 593:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 821 | 594:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB |
||
| 822 | 595:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB |
||
| 823 | 596:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 824 | 597:Drivers/CMSIS/Include/core_cm3.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ |
||
| 825 | 598:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB |
||
| 826 | 599:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB |
||
| 827 | 600:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 828 | 601:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB |
||
| 829 | 602:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB |
||
| 830 | 603:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 831 | 604:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB |
||
| 832 | 605:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB |
||
| 833 | 606:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 834 | 607:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB |
||
| 835 | 608:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB |
||
| 836 | 609:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 837 | 610:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB |
||
| 838 | 611:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB |
||
| 839 | 612:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 840 | 613:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB |
||
| 20 | mjames | 841 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 15 |
| 16 | mjames | 842 | |
| 843 | |||
| 844 | 614:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB |
||
| 845 | 615:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 846 | 616:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Hard Fault Status Register Definitions */ |
||
| 847 | 617:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB |
||
| 848 | 618:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB |
||
| 849 | 619:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 850 | 620:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB |
||
| 851 | 621:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB |
||
| 852 | 622:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 853 | 623:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB |
||
| 854 | 624:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB |
||
| 855 | 625:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 856 | 626:Drivers/CMSIS/Include/core_cm3.h **** /* SCB Debug Fault Status Register Definitions */ |
||
| 857 | 627:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB |
||
| 858 | 628:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB |
||
| 859 | 629:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 860 | 630:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB |
||
| 861 | 631:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB |
||
| 862 | 632:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 863 | 633:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB |
||
| 864 | 634:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB |
||
| 865 | 635:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 866 | 636:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB |
||
| 867 | 637:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB |
||
| 868 | 638:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 869 | 639:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB |
||
| 870 | 640:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB |
||
| 871 | 641:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 872 | 642:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_SCB */ |
||
| 873 | 643:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 874 | 644:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 875 | 645:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 876 | 646:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 877 | 647:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
||
| 878 | 648:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the System Control and ID Register not in the SCB |
||
| 879 | 649:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 880 | 650:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 881 | 651:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 882 | 652:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 883 | 653:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the System Control and ID Register not in the SCB. |
||
| 884 | 654:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 885 | 655:Drivers/CMSIS/Include/core_cm3.h **** typedef struct |
||
| 886 | 656:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 887 | 657:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[1U]; |
||
| 888 | 658:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist |
||
| 889 | 659:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) |
||
| 890 | 660:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
||
| 891 | 661:Drivers/CMSIS/Include/core_cm3.h **** #else |
||
| 892 | 662:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED1[1U]; |
||
| 893 | 663:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 894 | 664:Drivers/CMSIS/Include/core_cm3.h **** } SCnSCB_Type; |
||
| 895 | 665:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 896 | 666:Drivers/CMSIS/Include/core_cm3.h **** /* Interrupt Controller Type Register Definitions */ |
||
| 897 | 667:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I |
||
| 898 | 668:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I |
||
| 899 | 669:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 900 | 670:Drivers/CMSIS/Include/core_cm3.h **** /* Auxiliary Control Register Definitions */ |
||
| 20 | mjames | 901 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 16 |
| 16 | mjames | 902 | |
| 903 | |||
| 904 | 671:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 905 | 672:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: |
||
| 906 | 673:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: |
||
| 907 | 674:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 908 | 675:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: |
||
| 909 | 676:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: |
||
| 910 | 677:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 911 | 678:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: |
||
| 912 | 679:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: |
||
| 913 | 680:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 914 | 681:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_SCnotSCB */ |
||
| 915 | 682:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 916 | 683:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 917 | 684:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 918 | 685:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 919 | 686:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||
| 920 | 687:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the System Timer Registers. |
||
| 921 | 688:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 922 | 689:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 923 | 690:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 924 | 691:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 925 | 692:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the System Timer (SysTick). |
||
| 926 | 693:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 927 | 694:Drivers/CMSIS/Include/core_cm3.h **** typedef struct |
||
| 928 | 695:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 929 | 696:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis |
||
| 930 | 697:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||
| 931 | 698:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * |
||
| 932 | 699:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||
| 933 | 700:Drivers/CMSIS/Include/core_cm3.h **** } SysTick_Type; |
||
| 934 | 701:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 935 | 702:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Control / Status Register Definitions */ |
||
| 936 | 703:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT |
||
| 937 | 704:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT |
||
| 938 | 705:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 939 | 706:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT |
||
| 940 | 707:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT |
||
| 941 | 708:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 942 | 709:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT |
||
| 943 | 710:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT |
||
| 944 | 711:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 945 | 712:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT |
||
| 946 | 713:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT |
||
| 947 | 714:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 948 | 715:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Reload Register Definitions */ |
||
| 949 | 716:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT |
||
| 950 | 717:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT |
||
| 951 | 718:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 952 | 719:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Current Register Definitions */ |
||
| 953 | 720:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT |
||
| 954 | 721:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT |
||
| 955 | 722:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 956 | 723:Drivers/CMSIS/Include/core_cm3.h **** /* SysTick Calibration Register Definitions */ |
||
| 957 | 724:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT |
||
| 958 | 725:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT |
||
| 959 | 726:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 960 | 727:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT |
||
| 20 | mjames | 961 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 17 |
| 16 | mjames | 962 | |
| 963 | |||
| 964 | 728:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT |
||
| 965 | 729:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 966 | 730:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT |
||
| 967 | 731:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT |
||
| 968 | 732:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 969 | 733:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_SysTick */ |
||
| 970 | 734:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 971 | 735:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 972 | 736:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 973 | 737:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 974 | 738:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
||
| 975 | 739:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
||
| 976 | 740:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 977 | 741:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 978 | 742:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 979 | 743:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 980 | 744:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
||
| 981 | 745:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 982 | 746:Drivers/CMSIS/Include/core_cm3.h **** typedef struct |
||
| 983 | 747:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 984 | 748:Drivers/CMSIS/Include/core_cm3.h **** __OM union |
||
| 985 | 749:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 986 | 750:Drivers/CMSIS/Include/core_cm3.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
||
| 987 | 751:Drivers/CMSIS/Include/core_cm3.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
||
| 988 | 752:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
||
| 989 | 753:Drivers/CMSIS/Include/core_cm3.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
||
| 990 | 754:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[864U]; |
||
| 991 | 755:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
||
| 992 | 756:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED1[15U]; |
||
| 993 | 757:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
||
| 994 | 758:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED2[15U]; |
||
| 995 | 759:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
||
| 996 | 760:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED3[29U]; |
||
| 997 | 761:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * |
||
| 998 | 762:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ |
||
| 999 | 763:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg |
||
| 1000 | 764:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED4[43U]; |
||
| 1001 | 765:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ |
||
| 1002 | 766:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ |
||
| 1003 | 767:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED5[6U]; |
||
| 1004 | 768:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re |
||
| 1005 | 769:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re |
||
| 1006 | 770:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re |
||
| 1007 | 771:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re |
||
| 1008 | 772:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re |
||
| 1009 | 773:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re |
||
| 1010 | 774:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re |
||
| 1011 | 775:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re |
||
| 1012 | 776:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re |
||
| 1013 | 777:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re |
||
| 1014 | 778:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re |
||
| 1015 | 779:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re |
||
| 1016 | 780:Drivers/CMSIS/Include/core_cm3.h **** } ITM_Type; |
||
| 1017 | 781:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1018 | 782:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Trace Privilege Register Definitions */ |
||
| 1019 | 783:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM |
||
| 1020 | 784:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM |
||
| 20 | mjames | 1021 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 18 |
| 16 | mjames | 1022 | |
| 1023 | |||
| 1024 | 785:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1025 | 786:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Trace Control Register Definitions */ |
||
| 1026 | 787:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM |
||
| 1027 | 788:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM |
||
| 1028 | 789:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1029 | 790:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM |
||
| 1030 | 791:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM |
||
| 1031 | 792:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1032 | 793:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM |
||
| 1033 | 794:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM |
||
| 1034 | 795:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1035 | 796:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM |
||
| 1036 | 797:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM |
||
| 1037 | 798:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1038 | 799:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM |
||
| 1039 | 800:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM |
||
| 1040 | 801:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1041 | 802:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM |
||
| 1042 | 803:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM |
||
| 1043 | 804:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1044 | 805:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM |
||
| 1045 | 806:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM |
||
| 1046 | 807:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1047 | 808:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM |
||
| 1048 | 809:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM |
||
| 1049 | 810:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1050 | 811:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM |
||
| 1051 | 812:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM |
||
| 1052 | 813:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1053 | 814:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Integration Write Register Definitions */ |
||
| 1054 | 815:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM |
||
| 1055 | 816:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM |
||
| 1056 | 817:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1057 | 818:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Integration Read Register Definitions */ |
||
| 1058 | 819:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM |
||
| 1059 | 820:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM |
||
| 1060 | 821:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1061 | 822:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Integration Mode Control Register Definitions */ |
||
| 1062 | 823:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM |
||
| 1063 | 824:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM |
||
| 1064 | 825:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1065 | 826:Drivers/CMSIS/Include/core_cm3.h **** /* ITM Lock Status Register Definitions */ |
||
| 1066 | 827:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM |
||
| 1067 | 828:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM |
||
| 1068 | 829:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1069 | 830:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM |
||
| 1070 | 831:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM |
||
| 1071 | 832:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1072 | 833:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM |
||
| 1073 | 834:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM |
||
| 1074 | 835:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1075 | 836:Drivers/CMSIS/Include/core_cm3.h **** /*@}*/ /* end of group CMSIS_ITM */ |
||
| 1076 | 837:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1077 | 838:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1078 | 839:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1079 | 840:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 1080 | 841:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
||
| 20 | mjames | 1081 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 19 |
| 16 | mjames | 1082 | |
| 1083 | |||
| 1084 | 842:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) |
||
| 1085 | 843:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 1086 | 844:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1087 | 845:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1088 | 846:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1089 | 847:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
||
| 1090 | 848:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1091 | 849:Drivers/CMSIS/Include/core_cm3.h **** typedef struct |
||
| 1092 | 850:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1093 | 851:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
||
| 1094 | 852:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
||
| 1095 | 853:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
||
| 1096 | 854:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe |
||
| 1097 | 855:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
||
| 1098 | 856:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
||
| 1099 | 857:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe |
||
| 1100 | 858:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register |
||
| 1101 | 859:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
||
| 1102 | 860:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ |
||
| 1103 | 861:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
||
| 1104 | 862:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[1U]; |
||
| 1105 | 863:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
||
| 1106 | 864:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ |
||
| 1107 | 865:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
||
| 1108 | 866:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED1[1U]; |
||
| 1109 | 867:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
||
| 1110 | 868:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ |
||
| 1111 | 869:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
||
| 1112 | 870:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED2[1U]; |
||
| 1113 | 871:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
||
| 1114 | 872:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ |
||
| 1115 | 873:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
||
| 1116 | 874:Drivers/CMSIS/Include/core_cm3.h **** } DWT_Type; |
||
| 1117 | 875:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1118 | 876:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Control Register Definitions */ |
||
| 1119 | 877:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR |
||
| 1120 | 878:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR |
||
| 1121 | 879:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1122 | 880:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR |
||
| 1123 | 881:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR |
||
| 1124 | 882:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1125 | 883:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR |
||
| 1126 | 884:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR |
||
| 1127 | 885:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1128 | 886:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR |
||
| 1129 | 887:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR |
||
| 1130 | 888:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1131 | 889:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR |
||
| 1132 | 890:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR |
||
| 1133 | 891:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1134 | 892:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR |
||
| 1135 | 893:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR |
||
| 1136 | 894:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1137 | 895:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR |
||
| 1138 | 896:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR |
||
| 1139 | 897:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1140 | 898:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR |
||
| 20 | mjames | 1141 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 20 |
| 16 | mjames | 1142 | |
| 1143 | |||
| 1144 | 899:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR |
||
| 1145 | 900:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1146 | 901:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR |
||
| 1147 | 902:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR |
||
| 1148 | 903:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1149 | 904:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR |
||
| 1150 | 905:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR |
||
| 1151 | 906:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1152 | 907:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR |
||
| 1153 | 908:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR |
||
| 1154 | 909:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1155 | 910:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR |
||
| 1156 | 911:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR |
||
| 1157 | 912:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1158 | 913:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR |
||
| 1159 | 914:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR |
||
| 1160 | 915:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1161 | 916:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR |
||
| 1162 | 917:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR |
||
| 1163 | 918:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1164 | 919:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR |
||
| 1165 | 920:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR |
||
| 1166 | 921:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1167 | 922:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR |
||
| 1168 | 923:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR |
||
| 1169 | 924:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1170 | 925:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR |
||
| 1171 | 926:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR |
||
| 1172 | 927:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1173 | 928:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR |
||
| 1174 | 929:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR |
||
| 1175 | 930:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1176 | 931:Drivers/CMSIS/Include/core_cm3.h **** /* DWT CPI Count Register Definitions */ |
||
| 1177 | 932:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI |
||
| 1178 | 933:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI |
||
| 1179 | 934:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1180 | 935:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Exception Overhead Count Register Definitions */ |
||
| 1181 | 936:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC |
||
| 1182 | 937:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC |
||
| 1183 | 938:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1184 | 939:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Sleep Count Register Definitions */ |
||
| 1185 | 940:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE |
||
| 1186 | 941:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE |
||
| 1187 | 942:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1188 | 943:Drivers/CMSIS/Include/core_cm3.h **** /* DWT LSU Count Register Definitions */ |
||
| 1189 | 944:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU |
||
| 1190 | 945:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU |
||
| 1191 | 946:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1192 | 947:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Folded-instruction Count Register Definitions */ |
||
| 1193 | 948:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL |
||
| 1194 | 949:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL |
||
| 1195 | 950:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1196 | 951:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Comparator Mask Register Definitions */ |
||
| 1197 | 952:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS |
||
| 1198 | 953:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS |
||
| 1199 | 954:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1200 | 955:Drivers/CMSIS/Include/core_cm3.h **** /* DWT Comparator Function Register Definitions */ |
||
| 20 | mjames | 1201 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 21 |
| 16 | mjames | 1202 | |
| 1203 | |||
| 1204 | 956:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN |
||
| 1205 | 957:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN |
||
| 1206 | 958:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1207 | 959:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN |
||
| 1208 | 960:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN |
||
| 1209 | 961:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1210 | 962:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN |
||
| 1211 | 963:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN |
||
| 1212 | 964:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1213 | 965:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN |
||
| 1214 | 966:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN |
||
| 1215 | 967:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1216 | 968:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN |
||
| 1217 | 969:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN |
||
| 1218 | 970:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1219 | 971:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN |
||
| 1220 | 972:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN |
||
| 1221 | 973:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1222 | 974:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN |
||
| 1223 | 975:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN |
||
| 1224 | 976:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1225 | 977:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN |
||
| 1226 | 978:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN |
||
| 1227 | 979:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1228 | 980:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN |
||
| 1229 | 981:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN |
||
| 1230 | 982:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1231 | 983:Drivers/CMSIS/Include/core_cm3.h **** /*@}*/ /* end of group CMSIS_DWT */ |
||
| 1232 | 984:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1233 | 985:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1234 | 986:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1235 | 987:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 1236 | 988:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) |
||
| 1237 | 989:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Trace Port Interface (TPI) |
||
| 1238 | 990:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 1239 | 991:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1240 | 992:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1241 | 993:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1242 | 994:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Trace Port Interface Register (TPI). |
||
| 1243 | 995:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1244 | 996:Drivers/CMSIS/Include/core_cm3.h **** typedef struct |
||
| 1245 | 997:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1246 | 998:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg |
||
| 1247 | 999:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis |
||
| 1248 | 1000:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED0[2U]; |
||
| 1249 | 1001:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg |
||
| 1250 | 1002:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED1[55U]; |
||
| 1251 | 1003:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * |
||
| 1252 | 1004:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED2[131U]; |
||
| 1253 | 1005:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis |
||
| 1254 | 1006:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi |
||
| 1255 | 1007:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte |
||
| 1256 | 1008:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED3[759U]; |
||
| 1257 | 1009:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ |
||
| 1258 | 1010:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
||
| 1259 | 1011:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
||
| 1260 | 1012:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED4[1U]; |
||
| 20 | mjames | 1261 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 22 |
| 16 | mjames | 1262 | |
| 1263 | |||
| 1264 | 1013:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
||
| 1265 | 1014:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
||
| 1266 | 1015:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
||
| 1267 | 1016:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED5[39U]; |
||
| 1268 | 1017:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
||
| 1269 | 1018:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
||
| 1270 | 1019:Drivers/CMSIS/Include/core_cm3.h **** uint32_t RESERVED7[8U]; |
||
| 1271 | 1020:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
||
| 1272 | 1021:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
||
| 1273 | 1022:Drivers/CMSIS/Include/core_cm3.h **** } TPI_Type; |
||
| 1274 | 1023:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1275 | 1024:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ |
||
| 1276 | 1025:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP |
||
| 1277 | 1026:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP |
||
| 1278 | 1027:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1279 | 1028:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Selected Pin Protocol Register Definitions */ |
||
| 1280 | 1029:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP |
||
| 1281 | 1030:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP |
||
| 1282 | 1031:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1283 | 1032:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Formatter and Flush Status Register Definitions */ |
||
| 1284 | 1033:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS |
||
| 1285 | 1034:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS |
||
| 1286 | 1035:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1287 | 1036:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS |
||
| 1288 | 1037:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS |
||
| 1289 | 1038:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1290 | 1039:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS |
||
| 1291 | 1040:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS |
||
| 1292 | 1041:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1293 | 1042:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS |
||
| 1294 | 1043:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS |
||
| 1295 | 1044:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1296 | 1045:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Formatter and Flush Control Register Definitions */ |
||
| 1297 | 1046:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC |
||
| 1298 | 1047:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC |
||
| 1299 | 1048:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1300 | 1049:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC |
||
| 1301 | 1050:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC |
||
| 1302 | 1051:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1303 | 1052:Drivers/CMSIS/Include/core_cm3.h **** /* TPI TRIGGER Register Definitions */ |
||
| 1304 | 1053:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI |
||
| 1305 | 1054:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI |
||
| 1306 | 1055:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1307 | 1056:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
||
| 1308 | 1057:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF |
||
| 1309 | 1058:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF |
||
| 1310 | 1059:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1311 | 1060:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF |
||
| 1312 | 1061:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF |
||
| 1313 | 1062:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1314 | 1063:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF |
||
| 1315 | 1064:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF |
||
| 1316 | 1065:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1317 | 1066:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF |
||
| 1318 | 1067:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF |
||
| 1319 | 1068:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1320 | 1069:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF |
||
| 20 | mjames | 1321 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 23 |
| 16 | mjames | 1322 | |
| 1323 | |||
| 1324 | 1070:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF |
||
| 1325 | 1071:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1326 | 1072:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF |
||
| 1327 | 1073:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF |
||
| 1328 | 1074:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1329 | 1075:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF |
||
| 1330 | 1076:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF |
||
| 1331 | 1077:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1332 | 1078:Drivers/CMSIS/Include/core_cm3.h **** /* TPI ITATBCTR2 Register Definitions */ |
||
| 1333 | 1079:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA |
||
| 1334 | 1080:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA |
||
| 1335 | 1081:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1336 | 1082:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA |
||
| 1337 | 1083:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA |
||
| 1338 | 1084:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1339 | 1085:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
||
| 1340 | 1086:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF |
||
| 1341 | 1087:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF |
||
| 1342 | 1088:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1343 | 1089:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF |
||
| 1344 | 1090:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF |
||
| 1345 | 1091:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1346 | 1092:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF |
||
| 1347 | 1093:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF |
||
| 1348 | 1094:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1349 | 1095:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF |
||
| 1350 | 1096:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF |
||
| 1351 | 1097:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1352 | 1098:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF |
||
| 1353 | 1099:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF |
||
| 1354 | 1100:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1355 | 1101:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF |
||
| 1356 | 1102:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF |
||
| 1357 | 1103:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1358 | 1104:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF |
||
| 1359 | 1105:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF |
||
| 1360 | 1106:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1361 | 1107:Drivers/CMSIS/Include/core_cm3.h **** /* TPI ITATBCTR0 Register Definitions */ |
||
| 1362 | 1108:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA |
||
| 1363 | 1109:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA |
||
| 1364 | 1110:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1365 | 1111:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA |
||
| 1366 | 1112:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA |
||
| 1367 | 1113:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1368 | 1114:Drivers/CMSIS/Include/core_cm3.h **** /* TPI Integration Mode Control Register Definitions */ |
||
| 1369 | 1115:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC |
||
| 1370 | 1116:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC |
||
| 1371 | 1117:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1372 | 1118:Drivers/CMSIS/Include/core_cm3.h **** /* TPI DEVID Register Definitions */ |
||
| 1373 | 1119:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV |
||
| 1374 | 1120:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV |
||
| 1375 | 1121:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1376 | 1122:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV |
||
| 1377 | 1123:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV |
||
| 1378 | 1124:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1379 | 1125:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV |
||
| 1380 | 1126:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV |
||
| 20 | mjames | 1381 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 24 |
| 16 | mjames | 1382 | |
| 1383 | |||
| 1384 | 1127:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1385 | 1128:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV |
||
| 1386 | 1129:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV |
||
| 1387 | 1130:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1388 | 1131:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV |
||
| 1389 | 1132:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV |
||
| 1390 | 1133:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1391 | 1134:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV |
||
| 1392 | 1135:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV |
||
| 1393 | 1136:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1394 | 1137:Drivers/CMSIS/Include/core_cm3.h **** /* TPI DEVTYPE Register Definitions */ |
||
| 1395 | 1138:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV |
||
| 1396 | 1139:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV |
||
| 1397 | 1140:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1398 | 1141:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV |
||
| 1399 | 1142:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV |
||
| 1400 | 1143:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1401 | 1144:Drivers/CMSIS/Include/core_cm3.h **** /*@}*/ /* end of group CMSIS_TPI */ |
||
| 1402 | 1145:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1403 | 1146:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1404 | 1147:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
||
| 1405 | 1148:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1406 | 1149:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 1407 | 1150:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
||
| 1408 | 1151:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Memory Protection Unit (MPU) |
||
| 1409 | 1152:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 1410 | 1153:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1411 | 1154:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1412 | 1155:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1413 | 1156:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Memory Protection Unit (MPU). |
||
| 1414 | 1157:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1415 | 1158:Drivers/CMSIS/Include/core_cm3.h **** typedef struct |
||
| 1416 | 1159:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1417 | 1160:Drivers/CMSIS/Include/core_cm3.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
||
| 1418 | 1161:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
||
| 1419 | 1162:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
||
| 1420 | 1163:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register |
||
| 1421 | 1164:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re |
||
| 1422 | 1165:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address |
||
| 1423 | 1166:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and |
||
| 1424 | 1167:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address |
||
| 1425 | 1168:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and |
||
| 1426 | 1169:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address |
||
| 1427 | 1170:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and |
||
| 1428 | 1171:Drivers/CMSIS/Include/core_cm3.h **** } MPU_Type; |
||
| 1429 | 1172:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1430 | 1173:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_RALIASES 4U |
||
| 1431 | 1174:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1432 | 1175:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Type Register Definitions */ |
||
| 1433 | 1176:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU |
||
| 1434 | 1177:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU |
||
| 1435 | 1178:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1436 | 1179:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU |
||
| 1437 | 1180:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU |
||
| 1438 | 1181:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1439 | 1182:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU |
||
| 1440 | 1183:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU |
||
| 20 | mjames | 1441 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 25 |
| 16 | mjames | 1442 | |
| 1443 | |||
| 1444 | 1184:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1445 | 1185:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Control Register Definitions */ |
||
| 1446 | 1186:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU |
||
| 1447 | 1187:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU |
||
| 1448 | 1188:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1449 | 1189:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU |
||
| 1450 | 1190:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU |
||
| 1451 | 1191:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1452 | 1192:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU |
||
| 1453 | 1193:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU |
||
| 1454 | 1194:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1455 | 1195:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Region Number Register Definitions */ |
||
| 1456 | 1196:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU |
||
| 1457 | 1197:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU |
||
| 1458 | 1198:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1459 | 1199:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Region Base Address Register Definitions */ |
||
| 1460 | 1200:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU |
||
| 1461 | 1201:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU |
||
| 1462 | 1202:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1463 | 1203:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU |
||
| 1464 | 1204:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU |
||
| 1465 | 1205:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1466 | 1206:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU |
||
| 1467 | 1207:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU |
||
| 1468 | 1208:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1469 | 1209:Drivers/CMSIS/Include/core_cm3.h **** /* MPU Region Attribute and Size Register Definitions */ |
||
| 1470 | 1210:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU |
||
| 1471 | 1211:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU |
||
| 1472 | 1212:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1473 | 1213:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU |
||
| 1474 | 1214:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU |
||
| 1475 | 1215:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1476 | 1216:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU |
||
| 1477 | 1217:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU |
||
| 1478 | 1218:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1479 | 1219:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU |
||
| 1480 | 1220:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU |
||
| 1481 | 1221:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1482 | 1222:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_S_Pos 18U /*!< MPU |
||
| 1483 | 1223:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU |
||
| 1484 | 1224:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1485 | 1225:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_C_Pos 17U /*!< MPU |
||
| 1486 | 1226:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU |
||
| 1487 | 1227:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1488 | 1228:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_B_Pos 16U /*!< MPU |
||
| 1489 | 1229:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU |
||
| 1490 | 1230:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1491 | 1231:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU |
||
| 1492 | 1232:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU |
||
| 1493 | 1233:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1494 | 1234:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU |
||
| 1495 | 1235:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU |
||
| 1496 | 1236:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1497 | 1237:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU |
||
| 1498 | 1238:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU |
||
| 1499 | 1239:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1500 | 1240:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_MPU */ |
||
| 20 | mjames | 1501 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 26 |
| 16 | mjames | 1502 | |
| 1503 | |||
| 1504 | 1241:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 1505 | 1242:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1506 | 1243:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1507 | 1244:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1508 | 1245:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 1509 | 1246:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||
| 1510 | 1247:Drivers/CMSIS/Include/core_cm3.h **** \brief Type definitions for the Core Debug Registers |
||
| 1511 | 1248:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 1512 | 1249:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1513 | 1250:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1514 | 1251:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1515 | 1252:Drivers/CMSIS/Include/core_cm3.h **** \brief Structure type to access the Core Debug Register (CoreDebug). |
||
| 1516 | 1253:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1517 | 1254:Drivers/CMSIS/Include/core_cm3.h **** typedef struct |
||
| 1518 | 1255:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1519 | 1256:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status |
||
| 1520 | 1257:Drivers/CMSIS/Include/core_cm3.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg |
||
| 1521 | 1258:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe |
||
| 1522 | 1259:Drivers/CMSIS/Include/core_cm3.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont |
||
| 1523 | 1260:Drivers/CMSIS/Include/core_cm3.h **** } CoreDebug_Type; |
||
| 1524 | 1261:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1525 | 1262:Drivers/CMSIS/Include/core_cm3.h **** /* Debug Halting Control and Status Register Definitions */ |
||
| 1526 | 1263:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core |
||
| 1527 | 1264:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core |
||
| 1528 | 1265:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1529 | 1266:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core |
||
| 1530 | 1267:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core |
||
| 1531 | 1268:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1532 | 1269:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core |
||
| 1533 | 1270:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core |
||
| 1534 | 1271:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1535 | 1272:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core |
||
| 1536 | 1273:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core |
||
| 1537 | 1274:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1538 | 1275:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core |
||
| 1539 | 1276:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core |
||
| 1540 | 1277:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1541 | 1278:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core |
||
| 1542 | 1279:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core |
||
| 1543 | 1280:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1544 | 1281:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core |
||
| 1545 | 1282:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core |
||
| 1546 | 1283:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1547 | 1284:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core |
||
| 1548 | 1285:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core |
||
| 1549 | 1286:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1550 | 1287:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core |
||
| 1551 | 1288:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core |
||
| 1552 | 1289:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1553 | 1290:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core |
||
| 1554 | 1291:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core |
||
| 1555 | 1292:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1556 | 1293:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core |
||
| 1557 | 1294:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core |
||
| 1558 | 1295:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1559 | 1296:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core |
||
| 1560 | 1297:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core |
||
| 20 | mjames | 1561 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 27 |
| 16 | mjames | 1562 | |
| 1563 | |||
| 1564 | 1298:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1565 | 1299:Drivers/CMSIS/Include/core_cm3.h **** /* Debug Core Register Selector Register Definitions */ |
||
| 1566 | 1300:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core |
||
| 1567 | 1301:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core |
||
| 1568 | 1302:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1569 | 1303:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core |
||
| 1570 | 1304:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core |
||
| 1571 | 1305:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1572 | 1306:Drivers/CMSIS/Include/core_cm3.h **** /* Debug Exception and Monitor Control Register Definitions */ |
||
| 1573 | 1307:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core |
||
| 1574 | 1308:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core |
||
| 1575 | 1309:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1576 | 1310:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core |
||
| 1577 | 1311:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core |
||
| 1578 | 1312:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1579 | 1313:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core |
||
| 1580 | 1314:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core |
||
| 1581 | 1315:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1582 | 1316:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core |
||
| 1583 | 1317:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core |
||
| 1584 | 1318:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1585 | 1319:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core |
||
| 1586 | 1320:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core |
||
| 1587 | 1321:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1588 | 1322:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core |
||
| 1589 | 1323:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core |
||
| 1590 | 1324:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1591 | 1325:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core |
||
| 1592 | 1326:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core |
||
| 1593 | 1327:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1594 | 1328:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core |
||
| 1595 | 1329:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core |
||
| 1596 | 1330:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1597 | 1331:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core |
||
| 1598 | 1332:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core |
||
| 1599 | 1333:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1600 | 1334:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core |
||
| 1601 | 1335:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core |
||
| 1602 | 1336:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1603 | 1337:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core |
||
| 1604 | 1338:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core |
||
| 1605 | 1339:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1606 | 1340:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core |
||
| 1607 | 1341:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core |
||
| 1608 | 1342:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1609 | 1343:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core |
||
| 1610 | 1344:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core |
||
| 1611 | 1345:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1612 | 1346:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_CoreDebug */ |
||
| 1613 | 1347:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1614 | 1348:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1615 | 1349:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1616 | 1350:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 1617 | 1351:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_core_bitfield Core register bit field macros |
||
| 1618 | 1352:Drivers/CMSIS/Include/core_cm3.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||
| 1619 | 1353:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 1620 | 1354:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 20 | mjames | 1621 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 28 |
| 16 | mjames | 1622 | |
| 1623 | |||
| 1624 | 1355:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1625 | 1356:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1626 | 1357:Drivers/CMSIS/Include/core_cm3.h **** \brief Mask and shift a bit field value for use in a register bit range. |
||
| 1627 | 1358:Drivers/CMSIS/Include/core_cm3.h **** \param[in] field Name of the register bit field. |
||
| 1628 | 1359:Drivers/CMSIS/Include/core_cm3.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
||
| 1629 | 1360:Drivers/CMSIS/Include/core_cm3.h **** \return Masked and shifted value. |
||
| 1630 | 1361:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1631 | 1362:Drivers/CMSIS/Include/core_cm3.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
||
| 1632 | 1363:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1633 | 1364:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1634 | 1365:Drivers/CMSIS/Include/core_cm3.h **** \brief Mask and shift a register value to extract a bit filed value. |
||
| 1635 | 1366:Drivers/CMSIS/Include/core_cm3.h **** \param[in] field Name of the register bit field. |
||
| 1636 | 1367:Drivers/CMSIS/Include/core_cm3.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
||
| 1637 | 1368:Drivers/CMSIS/Include/core_cm3.h **** \return Masked and shifted bit field value. |
||
| 1638 | 1369:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1639 | 1370:Drivers/CMSIS/Include/core_cm3.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
||
| 1640 | 1371:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1641 | 1372:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of group CMSIS_core_bitfield */ |
||
| 1642 | 1373:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1643 | 1374:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1644 | 1375:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1645 | 1376:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_core_register |
||
| 1646 | 1377:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_core_base Core Definitions |
||
| 1647 | 1378:Drivers/CMSIS/Include/core_cm3.h **** \brief Definitions for base addresses, unions, and structures. |
||
| 1648 | 1379:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 1649 | 1380:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1650 | 1381:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1651 | 1382:Drivers/CMSIS/Include/core_cm3.h **** /* Memory mapping of Core Hardware */ |
||
| 1652 | 1383:Drivers/CMSIS/Include/core_cm3.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas |
||
| 1653 | 1384:Drivers/CMSIS/Include/core_cm3.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
||
| 1654 | 1385:Drivers/CMSIS/Include/core_cm3.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
||
| 1655 | 1386:Drivers/CMSIS/Include/core_cm3.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
||
| 1656 | 1387:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address |
||
| 1657 | 1388:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||
| 1658 | 1389:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||
| 1659 | 1390:Drivers/CMSIS/Include/core_cm3.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas |
||
| 1660 | 1391:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1661 | 1392:Drivers/CMSIS/Include/core_cm3.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register |
||
| 1662 | 1393:Drivers/CMSIS/Include/core_cm3.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct |
||
| 1663 | 1394:Drivers/CMSIS/Include/core_cm3.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st |
||
| 1664 | 1395:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc |
||
| 1665 | 1396:Drivers/CMSIS/Include/core_cm3.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct |
||
| 1666 | 1397:Drivers/CMSIS/Include/core_cm3.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct |
||
| 1667 | 1398:Drivers/CMSIS/Include/core_cm3.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct |
||
| 1668 | 1399:Drivers/CMSIS/Include/core_cm3.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration |
||
| 1669 | 1400:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1670 | 1401:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
||
| 1671 | 1402:Drivers/CMSIS/Include/core_cm3.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * |
||
| 1672 | 1403:Drivers/CMSIS/Include/core_cm3.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * |
||
| 1673 | 1404:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 1674 | 1405:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1675 | 1406:Drivers/CMSIS/Include/core_cm3.h **** /*@} */ |
||
| 1676 | 1407:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1677 | 1408:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1678 | 1409:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1679 | 1410:Drivers/CMSIS/Include/core_cm3.h **** /******************************************************************************* |
||
| 1680 | 1411:Drivers/CMSIS/Include/core_cm3.h **** * Hardware Abstraction Layer |
||
| 20 | mjames | 1681 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 29 |
| 16 | mjames | 1682 | |
| 1683 | |||
| 1684 | 1412:Drivers/CMSIS/Include/core_cm3.h **** Core Function Interface contains: |
||
| 1685 | 1413:Drivers/CMSIS/Include/core_cm3.h **** - Core NVIC Functions |
||
| 1686 | 1414:Drivers/CMSIS/Include/core_cm3.h **** - Core SysTick Functions |
||
| 1687 | 1415:Drivers/CMSIS/Include/core_cm3.h **** - Core Debug Functions |
||
| 1688 | 1416:Drivers/CMSIS/Include/core_cm3.h **** - Core Register Access Functions |
||
| 1689 | 1417:Drivers/CMSIS/Include/core_cm3.h **** ******************************************************************************/ |
||
| 1690 | 1418:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1691 | 1419:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||
| 1692 | 1420:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1693 | 1421:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1694 | 1422:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1695 | 1423:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1696 | 1424:Drivers/CMSIS/Include/core_cm3.h **** /* ########################## NVIC functions #################################### */ |
||
| 1697 | 1425:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1698 | 1426:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_Core_FunctionInterface |
||
| 1699 | 1427:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||
| 1700 | 1428:Drivers/CMSIS/Include/core_cm3.h **** \brief Functions that manage interrupts and exceptions via the NVIC. |
||
| 1701 | 1429:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 1702 | 1430:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1703 | 1431:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1704 | 1432:Drivers/CMSIS/Include/core_cm3.h **** #ifdef CMSIS_NVIC_VIRTUAL |
||
| 1705 | 1433:Drivers/CMSIS/Include/core_cm3.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||
| 1706 | 1434:Drivers/CMSIS/Include/core_cm3.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
||
| 1707 | 1435:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 1708 | 1436:Drivers/CMSIS/Include/core_cm3.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||
| 1709 | 1437:Drivers/CMSIS/Include/core_cm3.h **** #else |
||
| 1710 | 1438:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
||
| 1711 | 1439:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
||
| 1712 | 1440:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ |
||
| 1713 | 1441:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
||
| 1714 | 1442:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ |
||
| 1715 | 1443:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
||
| 1716 | 1444:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
||
| 1717 | 1445:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
||
| 1718 | 1446:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetActive __NVIC_GetActive |
||
| 1719 | 1447:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SetPriority __NVIC_SetPriority |
||
| 1720 | 1448:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetPriority __NVIC_GetPriority |
||
| 1721 | 1449:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SystemReset __NVIC_SystemReset |
||
| 1722 | 1450:Drivers/CMSIS/Include/core_cm3.h **** #endif /* CMSIS_NVIC_VIRTUAL */ |
||
| 1723 | 1451:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1724 | 1452:Drivers/CMSIS/Include/core_cm3.h **** #ifdef CMSIS_VECTAB_VIRTUAL |
||
| 1725 | 1453:Drivers/CMSIS/Include/core_cm3.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||
| 1726 | 1454:Drivers/CMSIS/Include/core_cm3.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
||
| 1727 | 1455:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 1728 | 1456:Drivers/CMSIS/Include/core_cm3.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||
| 1729 | 1457:Drivers/CMSIS/Include/core_cm3.h **** #else |
||
| 1730 | 1458:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_SetVector __NVIC_SetVector |
||
| 1731 | 1459:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_GetVector __NVIC_GetVector |
||
| 1732 | 1460:Drivers/CMSIS/Include/core_cm3.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
||
| 1733 | 1461:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1734 | 1462:Drivers/CMSIS/Include/core_cm3.h **** #define NVIC_USER_IRQ_OFFSET 16 |
||
| 1735 | 1463:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1736 | 1464:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1737 | 1465:Drivers/CMSIS/Include/core_cm3.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ |
||
| 1738 | 1466:Drivers/CMSIS/Include/core_cm3.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret |
||
| 1739 | 1467:Drivers/CMSIS/Include/core_cm3.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu |
||
| 1740 | 1468:Drivers/CMSIS/Include/core_cm3.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu |
||
| 20 | mjames | 1741 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 30 |
| 16 | mjames | 1742 | |
| 1743 | |||
| 1744 | 1469:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1745 | 1470:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1746 | 1471:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1747 | 1472:Drivers/CMSIS/Include/core_cm3.h **** \brief Set Priority Grouping |
||
| 1748 | 1473:Drivers/CMSIS/Include/core_cm3.h **** \details Sets the priority grouping field using the required unlock sequence. |
||
| 1749 | 1474:Drivers/CMSIS/Include/core_cm3.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
||
| 1750 | 1475:Drivers/CMSIS/Include/core_cm3.h **** Only values from 0..7 are used. |
||
| 1751 | 1476:Drivers/CMSIS/Include/core_cm3.h **** In case of a conflict between priority grouping and available |
||
| 1752 | 1477:Drivers/CMSIS/Include/core_cm3.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
||
| 1753 | 1478:Drivers/CMSIS/Include/core_cm3.h **** \param [in] PriorityGroup Priority grouping field. |
||
| 1754 | 1479:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1755 | 1480:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
||
| 1756 | 38 .loc 2 1480 22 view .LVU3 |
||
| 1757 | 39 .LBB47: |
||
| 1758 | 1481:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1759 | 1482:Drivers/CMSIS/Include/core_cm3.h **** uint32_t reg_value; |
||
| 1760 | 40 .loc 2 1482 3 view .LVU4 |
||
| 1761 | 1483:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a |
||
| 1762 | 41 .loc 2 1483 3 view .LVU5 |
||
| 1763 | 1484:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1764 | 1485:Drivers/CMSIS/Include/core_cm3.h **** reg_value = SCB->AIRCR; /* read old register |
||
| 1765 | 42 .loc 2 1485 3 view .LVU6 |
||
| 1766 | 43 .loc 2 1485 14 is_stmt 0 view .LVU7 |
||
| 1767 | 44 0000 074A ldr r2, .L2 |
||
| 1768 | 45 0002 D368 ldr r3, [r2, #12] |
||
| 1769 | 46 .LVL1: |
||
| 1770 | 1486:Drivers/CMSIS/Include/core_cm3.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan |
||
| 1771 | 47 .loc 2 1486 3 is_stmt 1 view .LVU8 |
||
| 1772 | 48 .loc 2 1486 13 is_stmt 0 view .LVU9 |
||
| 1773 | 49 0004 23F4E063 bic r3, r3, #1792 |
||
| 1774 | 50 .LVL2: |
||
| 1775 | 51 .loc 2 1486 13 view .LVU10 |
||
| 1776 | 52 0008 1B04 lsls r3, r3, #16 |
||
| 1777 | 53 000a 1B0C lsrs r3, r3, #16 |
||
| 1778 | 54 .LVL3: |
||
| 1779 | 1487:Drivers/CMSIS/Include/core_cm3.h **** reg_value = (reg_value | |
||
| 1780 | 55 .loc 2 1487 3 is_stmt 1 view .LVU11 |
||
| 1781 | 1488:Drivers/CMSIS/Include/core_cm3.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||
| 1782 | 1489:Drivers/CMSIS/Include/core_cm3.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a |
||
| 1783 | 56 .loc 2 1489 35 is_stmt 0 view .LVU12 |
||
| 1784 | 57 000c 0002 lsls r0, r0, #8 |
||
| 1785 | 58 .LVL4: |
||
| 1786 | 59 .loc 2 1489 35 view .LVU13 |
||
| 1787 | 60 000e 00F4E060 and r0, r0, #1792 |
||
| 1788 | 1488:Drivers/CMSIS/Include/core_cm3.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||
| 1789 | 61 .loc 2 1488 62 view .LVU14 |
||
| 1790 | 62 0012 1843 orrs r0, r0, r3 |
||
| 1791 | 1487:Drivers/CMSIS/Include/core_cm3.h **** reg_value = (reg_value | |
||
| 1792 | 63 .loc 2 1487 14 view .LVU15 |
||
| 1793 | 64 0014 40F0BF60 orr r0, r0, #100139008 |
||
| 1794 | 65 0018 40F40030 orr r0, r0, #131072 |
||
| 1795 | 66 .LVL5: |
||
| 1796 | 1490:Drivers/CMSIS/Include/core_cm3.h **** SCB->AIRCR = reg_value; |
||
| 1797 | 67 .loc 2 1490 3 is_stmt 1 view .LVU16 |
||
| 1798 | 68 .loc 2 1490 14 is_stmt 0 view .LVU17 |
||
| 1799 | 69 001c D060 str r0, [r2, #12] |
||
| 1800 | 70 .LVL6: |
||
| 20 | mjames | 1801 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 31 |
| 16 | mjames | 1802 | |
| 1803 | |||
| 1804 | 71 .loc 2 1490 14 view .LVU18 |
||
| 1805 | 72 .LBE47: |
||
| 1806 | 73 .LBE46: |
||
| 1807 | 150:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 1808 | 74 .loc 1 150 1 view .LVU19 |
||
| 1809 | 75 001e 7047 bx lr |
||
| 1810 | 76 .L3: |
||
| 1811 | 77 .align 2 |
||
| 1812 | 78 .L2: |
||
| 1813 | 79 0020 00ED00E0 .word -536810240 |
||
| 1814 | 80 .cfi_endproc |
||
| 1815 | 81 .LFE65: |
||
| 1816 | 83 .section .text.HAL_NVIC_SetPriority,"ax",%progbits |
||
| 1817 | 84 .align 1 |
||
| 1818 | 85 .global HAL_NVIC_SetPriority |
||
| 1819 | 86 .syntax unified |
||
| 1820 | 87 .thumb |
||
| 1821 | 88 .thumb_func |
||
| 1822 | 89 .fpu softvfp |
||
| 1823 | 91 HAL_NVIC_SetPriority: |
||
| 1824 | 92 .LVL7: |
||
| 1825 | 93 .LFB66: |
||
| 1826 | 151:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 1827 | 152:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 1828 | 153:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Sets the priority of an interrupt. |
||
| 1829 | 154:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param IRQn: External interrupt number. |
||
| 1830 | 155:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration |
||
| 1831 | 156:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI |
||
| 1832 | 157:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param PreemptPriority: The preemption priority for the IRQn channel. |
||
| 1833 | 158:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 |
||
| 1834 | 159:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * A lower priority value indicates a higher priority |
||
| 1835 | 160:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param SubPriority: the subpriority level for the IRQ channel. |
||
| 1836 | 161:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 |
||
| 1837 | 162:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * A lower priority value indicates a higher priority. |
||
| 1838 | 163:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 1839 | 164:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 1840 | 165:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) |
||
| 1841 | 166:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 1842 | 94 .loc 1 166 1 is_stmt 1 view -0 |
||
| 1843 | 95 .cfi_startproc |
||
| 1844 | 96 @ args = 0, pretend = 0, frame = 0 |
||
| 1845 | 97 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 1846 | 98 @ link register save eliminated. |
||
| 1847 | 99 .loc 1 166 1 is_stmt 0 view .LVU21 |
||
| 1848 | 100 0000 30B4 push {r4, r5} |
||
| 1849 | 101 .LCFI0: |
||
| 1850 | 102 .cfi_def_cfa_offset 8 |
||
| 1851 | 103 .cfi_offset 4, -8 |
||
| 1852 | 104 .cfi_offset 5, -4 |
||
| 1853 | 167:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** uint32_t prioritygroup = 0x00U; |
||
| 1854 | 105 .loc 1 167 3 is_stmt 1 view .LVU22 |
||
| 1855 | 106 .LVL8: |
||
| 1856 | 168:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 1857 | 169:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 1858 | 170:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); |
||
| 1859 | 107 .loc 1 170 3 view .LVU23 |
||
| 1860 | 171:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); |
||
| 20 | mjames | 1861 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 32 |
| 16 | mjames | 1862 | |
| 1863 | |||
| 1864 | 108 .loc 1 171 3 view .LVU24 |
||
| 1865 | 172:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 1866 | 173:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** prioritygroup = NVIC_GetPriorityGrouping(); |
||
| 1867 | 109 .loc 1 173 3 view .LVU25 |
||
| 1868 | 110 .LBB48: |
||
| 1869 | 111 .LBI48: |
||
| 1870 | 1491:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1871 | 1492:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1872 | 1493:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1873 | 1494:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1874 | 1495:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Priority Grouping |
||
| 1875 | 1496:Drivers/CMSIS/Include/core_cm3.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. |
||
| 1876 | 1497:Drivers/CMSIS/Include/core_cm3.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
||
| 1877 | 1498:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1878 | 1499:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) |
||
| 1879 | 112 .loc 2 1499 26 view .LVU26 |
||
| 1880 | 113 .LBB49: |
||
| 1881 | 1500:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1882 | 1501:Drivers/CMSIS/Include/core_cm3.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); |
||
| 1883 | 114 .loc 2 1501 3 view .LVU27 |
||
| 1884 | 115 .loc 2 1501 26 is_stmt 0 view .LVU28 |
||
| 1885 | 116 0002 174B ldr r3, .L10 |
||
| 1886 | 117 0004 DB68 ldr r3, [r3, #12] |
||
| 1887 | 118 .loc 2 1501 11 view .LVU29 |
||
| 1888 | 119 0006 C3F30223 ubfx r3, r3, #8, #3 |
||
| 1889 | 120 .LVL9: |
||
| 1890 | 121 .loc 2 1501 11 view .LVU30 |
||
| 1891 | 122 .LBE49: |
||
| 1892 | 123 .LBE48: |
||
| 1893 | 174:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 1894 | 175:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); |
||
| 1895 | 124 .loc 1 175 3 is_stmt 1 view .LVU31 |
||
| 1896 | 125 .LBB50: |
||
| 1897 | 126 .LBI50: |
||
| 1898 | 1502:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1899 | 1503:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1900 | 1504:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1901 | 1505:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1902 | 1506:Drivers/CMSIS/Include/core_cm3.h **** \brief Enable Interrupt |
||
| 1903 | 1507:Drivers/CMSIS/Include/core_cm3.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. |
||
| 1904 | 1508:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number. |
||
| 1905 | 1509:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative. |
||
| 1906 | 1510:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1907 | 1511:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
||
| 1908 | 1512:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1909 | 1513:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0) |
||
| 1910 | 1514:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1911 | 1515:Drivers/CMSIS/Include/core_cm3.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||
| 1912 | 1516:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1913 | 1517:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1914 | 1518:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1915 | 1519:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1916 | 1520:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1917 | 1521:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Interrupt Enable status |
||
| 1918 | 1522:Drivers/CMSIS/Include/core_cm3.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
||
| 1919 | 1523:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number. |
||
| 1920 | 1524:Drivers/CMSIS/Include/core_cm3.h **** \return 0 Interrupt is not enabled. |
||
| 20 | mjames | 1921 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 33 |
| 16 | mjames | 1922 | |
| 1923 | |||
| 1924 | 1525:Drivers/CMSIS/Include/core_cm3.h **** \return 1 Interrupt is enabled. |
||
| 1925 | 1526:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative. |
||
| 1926 | 1527:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1927 | 1528:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
||
| 1928 | 1529:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1929 | 1530:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0) |
||
| 1930 | 1531:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1931 | 1532:Drivers/CMSIS/Include/core_cm3.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) |
||
| 1932 | 1533:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1933 | 1534:Drivers/CMSIS/Include/core_cm3.h **** else |
||
| 1934 | 1535:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1935 | 1536:Drivers/CMSIS/Include/core_cm3.h **** return(0U); |
||
| 1936 | 1537:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1937 | 1538:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1938 | 1539:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1939 | 1540:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1940 | 1541:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1941 | 1542:Drivers/CMSIS/Include/core_cm3.h **** \brief Disable Interrupt |
||
| 1942 | 1543:Drivers/CMSIS/Include/core_cm3.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. |
||
| 1943 | 1544:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number. |
||
| 1944 | 1545:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative. |
||
| 1945 | 1546:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1946 | 1547:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
||
| 1947 | 1548:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1948 | 1549:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0) |
||
| 1949 | 1550:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1950 | 1551:Drivers/CMSIS/Include/core_cm3.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||
| 1951 | 1552:Drivers/CMSIS/Include/core_cm3.h **** __DSB(); |
||
| 1952 | 1553:Drivers/CMSIS/Include/core_cm3.h **** __ISB(); |
||
| 1953 | 1554:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1954 | 1555:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1955 | 1556:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1956 | 1557:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1957 | 1558:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1958 | 1559:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Pending Interrupt |
||
| 1959 | 1560:Drivers/CMSIS/Include/core_cm3.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe |
||
| 1960 | 1561:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number. |
||
| 1961 | 1562:Drivers/CMSIS/Include/core_cm3.h **** \return 0 Interrupt status is not pending. |
||
| 1962 | 1563:Drivers/CMSIS/Include/core_cm3.h **** \return 1 Interrupt status is pending. |
||
| 1963 | 1564:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative. |
||
| 1964 | 1565:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1965 | 1566:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||
| 1966 | 1567:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1967 | 1568:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0) |
||
| 1968 | 1569:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1969 | 1570:Drivers/CMSIS/Include/core_cm3.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) |
||
| 1970 | 1571:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1971 | 1572:Drivers/CMSIS/Include/core_cm3.h **** else |
||
| 1972 | 1573:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1973 | 1574:Drivers/CMSIS/Include/core_cm3.h **** return(0U); |
||
| 1974 | 1575:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1975 | 1576:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1976 | 1577:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1977 | 1578:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1978 | 1579:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1979 | 1580:Drivers/CMSIS/Include/core_cm3.h **** \brief Set Pending Interrupt |
||
| 1980 | 1581:Drivers/CMSIS/Include/core_cm3.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
||
| 20 | mjames | 1981 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 34 |
| 16 | mjames | 1982 | |
| 1983 | |||
| 1984 | 1582:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number. |
||
| 1985 | 1583:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative. |
||
| 1986 | 1584:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 1987 | 1585:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||
| 1988 | 1586:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1989 | 1587:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0) |
||
| 1990 | 1588:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 1991 | 1589:Drivers/CMSIS/Include/core_cm3.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||
| 1992 | 1590:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1993 | 1591:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 1994 | 1592:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1995 | 1593:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 1996 | 1594:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 1997 | 1595:Drivers/CMSIS/Include/core_cm3.h **** \brief Clear Pending Interrupt |
||
| 1998 | 1596:Drivers/CMSIS/Include/core_cm3.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
||
| 1999 | 1597:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number. |
||
| 2000 | 1598:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative. |
||
| 2001 | 1599:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 2002 | 1600:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||
| 2003 | 1601:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2004 | 1602:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0) |
||
| 2005 | 1603:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2006 | 1604:Drivers/CMSIS/Include/core_cm3.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||
| 2007 | 1605:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2008 | 1606:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2009 | 1607:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2010 | 1608:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2011 | 1609:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 2012 | 1610:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Active Interrupt |
||
| 2013 | 1611:Drivers/CMSIS/Include/core_cm3.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific |
||
| 2014 | 1612:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Device specific interrupt number. |
||
| 2015 | 1613:Drivers/CMSIS/Include/core_cm3.h **** \return 0 Interrupt status is not active. |
||
| 2016 | 1614:Drivers/CMSIS/Include/core_cm3.h **** \return 1 Interrupt status is active. |
||
| 2017 | 1615:Drivers/CMSIS/Include/core_cm3.h **** \note IRQn must not be negative. |
||
| 2018 | 1616:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 2019 | 1617:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) |
||
| 2020 | 1618:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2021 | 1619:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0) |
||
| 2022 | 1620:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2023 | 1621:Drivers/CMSIS/Include/core_cm3.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) |
||
| 2024 | 1622:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2025 | 1623:Drivers/CMSIS/Include/core_cm3.h **** else |
||
| 2026 | 1624:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2027 | 1625:Drivers/CMSIS/Include/core_cm3.h **** return(0U); |
||
| 2028 | 1626:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2029 | 1627:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2030 | 1628:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2031 | 1629:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2032 | 1630:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 2033 | 1631:Drivers/CMSIS/Include/core_cm3.h **** \brief Set Interrupt Priority |
||
| 2034 | 1632:Drivers/CMSIS/Include/core_cm3.h **** \details Sets the priority of a device specific interrupt or a processor exception. |
||
| 2035 | 1633:Drivers/CMSIS/Include/core_cm3.h **** The interrupt number can be positive to specify a device specific interrupt, |
||
| 2036 | 1634:Drivers/CMSIS/Include/core_cm3.h **** or negative to specify a processor exception. |
||
| 2037 | 1635:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Interrupt number. |
||
| 2038 | 1636:Drivers/CMSIS/Include/core_cm3.h **** \param [in] priority Priority to set. |
||
| 2039 | 1637:Drivers/CMSIS/Include/core_cm3.h **** \note The priority cannot be set for every processor exception. |
||
| 2040 | 1638:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 20 | mjames | 2041 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 35 |
| 16 | mjames | 2042 | |
| 2043 | |||
| 2044 | 1639:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||
| 2045 | 1640:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2046 | 1641:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0) |
||
| 2047 | 1642:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2048 | 1643:Drivers/CMSIS/Include/core_cm3.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u |
||
| 2049 | 1644:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2050 | 1645:Drivers/CMSIS/Include/core_cm3.h **** else |
||
| 2051 | 1646:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2052 | 1647:Drivers/CMSIS/Include/core_cm3.h **** SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u |
||
| 2053 | 1648:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2054 | 1649:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2055 | 1650:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2056 | 1651:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2057 | 1652:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 2058 | 1653:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Interrupt Priority |
||
| 2059 | 1654:Drivers/CMSIS/Include/core_cm3.h **** \details Reads the priority of a device specific interrupt or a processor exception. |
||
| 2060 | 1655:Drivers/CMSIS/Include/core_cm3.h **** The interrupt number can be positive to specify a device specific interrupt, |
||
| 2061 | 1656:Drivers/CMSIS/Include/core_cm3.h **** or negative to specify a processor exception. |
||
| 2062 | 1657:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Interrupt number. |
||
| 2063 | 1658:Drivers/CMSIS/Include/core_cm3.h **** \return Interrupt Priority. |
||
| 2064 | 1659:Drivers/CMSIS/Include/core_cm3.h **** Value is aligned automatically to the implemented priority bits of the microc |
||
| 2065 | 1660:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 2066 | 1661:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
||
| 2067 | 1662:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2068 | 1663:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2069 | 1664:Drivers/CMSIS/Include/core_cm3.h **** if ((int32_t)(IRQn) >= 0) |
||
| 2070 | 1665:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2071 | 1666:Drivers/CMSIS/Include/core_cm3.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); |
||
| 2072 | 1667:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2073 | 1668:Drivers/CMSIS/Include/core_cm3.h **** else |
||
| 2074 | 1669:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2075 | 1670:Drivers/CMSIS/Include/core_cm3.h **** return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); |
||
| 2076 | 1671:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2077 | 1672:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2078 | 1673:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2079 | 1674:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2080 | 1675:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 2081 | 1676:Drivers/CMSIS/Include/core_cm3.h **** \brief Encode Priority |
||
| 2082 | 1677:Drivers/CMSIS/Include/core_cm3.h **** \details Encodes the priority for an interrupt with the given priority group, |
||
| 2083 | 1678:Drivers/CMSIS/Include/core_cm3.h **** preemptive priority value, and subpriority value. |
||
| 2084 | 1679:Drivers/CMSIS/Include/core_cm3.h **** In case of a conflict between priority grouping and available |
||
| 2085 | 1680:Drivers/CMSIS/Include/core_cm3.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
||
| 2086 | 1681:Drivers/CMSIS/Include/core_cm3.h **** \param [in] PriorityGroup Used priority group. |
||
| 2087 | 1682:Drivers/CMSIS/Include/core_cm3.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). |
||
| 2088 | 1683:Drivers/CMSIS/Include/core_cm3.h **** \param [in] SubPriority Subpriority value (starting from 0). |
||
| 2089 | 1684:Drivers/CMSIS/Include/core_cm3.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP |
||
| 2090 | 1685:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 2091 | 1686:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin |
||
| 2092 | 127 .loc 2 1686 26 view .LVU32 |
||
| 2093 | 128 .LBB51: |
||
| 2094 | 1687:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2095 | 1688:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used |
||
| 2096 | 129 .loc 2 1688 3 view .LVU33 |
||
| 2097 | 1689:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PreemptPriorityBits; |
||
| 2098 | 130 .loc 2 1689 3 view .LVU34 |
||
| 2099 | 1690:Drivers/CMSIS/Include/core_cm3.h **** uint32_t SubPriorityBits; |
||
| 2100 | 131 .loc 2 1690 3 view .LVU35 |
||
| 20 | mjames | 2101 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 36 |
| 16 | mjames | 2102 | |
| 2103 | |||
| 2104 | 1691:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2105 | 1692:Drivers/CMSIS/Include/core_cm3.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV |
||
| 2106 | 132 .loc 2 1692 3 view .LVU36 |
||
| 2107 | 133 .loc 2 1692 31 is_stmt 0 view .LVU37 |
||
| 2108 | 134 000a C3F10704 rsb r4, r3, #7 |
||
| 2109 | 135 .loc 2 1692 23 view .LVU38 |
||
| 2110 | 136 000e 042C cmp r4, #4 |
||
| 2111 | 137 0010 28BF it cs |
||
| 2112 | 138 0012 0424 movcs r4, #4 |
||
| 2113 | 139 .LVL10: |
||
| 2114 | 1693:Drivers/CMSIS/Include/core_cm3.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint |
||
| 2115 | 140 .loc 2 1693 3 is_stmt 1 view .LVU39 |
||
| 2116 | 141 .loc 2 1693 44 is_stmt 0 view .LVU40 |
||
| 2117 | 142 0014 1D1D adds r5, r3, #4 |
||
| 2118 | 143 .loc 2 1693 109 view .LVU41 |
||
| 2119 | 144 0016 062D cmp r5, #6 |
||
| 2120 | 145 0018 01D9 bls .L8 |
||
| 2121 | 146 001a 033B subs r3, r3, #3 |
||
| 2122 | 147 .LVL11: |
||
| 2123 | 148 .loc 2 1693 109 view .LVU42 |
||
| 2124 | 149 001c 00E0 b .L5 |
||
| 2125 | 150 .LVL12: |
||
| 2126 | 151 .L8: |
||
| 2127 | 152 .loc 2 1693 109 view .LVU43 |
||
| 2128 | 153 001e 0023 movs r3, #0 |
||
| 2129 | 154 .LVL13: |
||
| 2130 | 155 .L5: |
||
| 2131 | 1694:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 2132 | 1695:Drivers/CMSIS/Include/core_cm3.h **** return ( |
||
| 2133 | 156 .loc 2 1695 3 is_stmt 1 view .LVU44 |
||
| 2134 | 1696:Drivers/CMSIS/Include/core_cm3.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits |
||
| 2135 | 157 .loc 2 1696 30 is_stmt 0 view .LVU45 |
||
| 2136 | 158 0020 4FF0FF35 mov r5, #-1 |
||
| 2137 | 159 .LVL14: |
||
| 2138 | 160 .loc 2 1696 30 view .LVU46 |
||
| 2139 | 161 0024 05FA04F4 lsl r4, r5, r4 |
||
| 2140 | 162 .LVL15: |
||
| 2141 | 163 .loc 2 1696 30 view .LVU47 |
||
| 2142 | 164 0028 21EA0401 bic r1, r1, r4 |
||
| 2143 | 165 .LVL16: |
||
| 2144 | 166 .loc 2 1696 82 view .LVU48 |
||
| 2145 | 167 002c 9940 lsls r1, r1, r3 |
||
| 2146 | 1697:Drivers/CMSIS/Include/core_cm3.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
||
| 2147 | 168 .loc 2 1697 30 view .LVU49 |
||
| 2148 | 169 002e 05FA03F3 lsl r3, r5, r3 |
||
| 2149 | 170 .LVL17: |
||
| 2150 | 171 .loc 2 1697 30 view .LVU50 |
||
| 2151 | 172 0032 22EA0303 bic r3, r2, r3 |
||
| 2152 | 1696:Drivers/CMSIS/Include/core_cm3.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits |
||
| 2153 | 173 .loc 2 1696 102 view .LVU51 |
||
| 2154 | 174 0036 1943 orrs r1, r1, r3 |
||
| 2155 | 175 .LVL18: |
||
| 2156 | 1696:Drivers/CMSIS/Include/core_cm3.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits |
||
| 2157 | 176 .loc 2 1696 102 view .LVU52 |
||
| 2158 | 177 .LBE51: |
||
| 2159 | 178 .LBE50: |
||
| 2160 | 179 .LBB52: |
||
| 20 | mjames | 2161 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 37 |
| 16 | mjames | 2162 | |
| 2163 | |||
| 2164 | 180 .LBI52: |
||
| 2165 | 1639:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2166 | 181 .loc 2 1639 22 is_stmt 1 view .LVU53 |
||
| 2167 | 182 .LBB53: |
||
| 2168 | 1641:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2169 | 183 .loc 2 1641 3 view .LVU54 |
||
| 2170 | 1641:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2171 | 184 .loc 2 1641 6 is_stmt 0 view .LVU55 |
||
| 2172 | 185 0038 0028 cmp r0, #0 |
||
| 2173 | 186 003a 09DB blt .L6 |
||
| 2174 | 1643:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2175 | 187 .loc 2 1643 5 is_stmt 1 view .LVU56 |
||
| 2176 | 1643:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2177 | 188 .loc 2 1643 48 is_stmt 0 view .LVU57 |
||
| 2178 | 189 003c 0901 lsls r1, r1, #4 |
||
| 2179 | 190 .LVL19: |
||
| 2180 | 1643:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2181 | 191 .loc 2 1643 48 view .LVU58 |
||
| 2182 | 192 003e C9B2 uxtb r1, r1 |
||
| 2183 | 1643:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2184 | 193 .loc 2 1643 46 view .LVU59 |
||
| 2185 | 194 0040 00F16040 add r0, r0, #-536870912 |
||
| 2186 | 195 .LVL20: |
||
| 2187 | 1643:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2188 | 196 .loc 2 1643 46 view .LVU60 |
||
| 2189 | 197 0044 00F56140 add r0, r0, #57600 |
||
| 2190 | 198 0048 80F80013 strb r1, [r0, #768] |
||
| 2191 | 199 .LVL21: |
||
| 2192 | 200 .L4: |
||
| 2193 | 1643:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2194 | 201 .loc 2 1643 46 view .LVU61 |
||
| 2195 | 202 .LBE53: |
||
| 2196 | 203 .LBE52: |
||
| 2197 | 176:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 2198 | 204 .loc 1 176 1 view .LVU62 |
||
| 2199 | 205 004c 30BC pop {r4, r5} |
||
| 2200 | 206 .LCFI1: |
||
| 2201 | 207 .cfi_remember_state |
||
| 2202 | 208 .cfi_restore 5 |
||
| 2203 | 209 .cfi_restore 4 |
||
| 2204 | 210 .cfi_def_cfa_offset 0 |
||
| 2205 | 211 004e 7047 bx lr |
||
| 2206 | 212 .LVL22: |
||
| 2207 | 213 .L6: |
||
| 2208 | 214 .LCFI2: |
||
| 2209 | 215 .cfi_restore_state |
||
| 2210 | 216 .LBB55: |
||
| 2211 | 217 .LBB54: |
||
| 2212 | 1647:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2213 | 218 .loc 2 1647 5 is_stmt 1 view .LVU63 |
||
| 2214 | 1647:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2215 | 219 .loc 2 1647 32 is_stmt 0 view .LVU64 |
||
| 2216 | 220 0050 00F00F00 and r0, r0, #15 |
||
| 2217 | 221 .LVL23: |
||
| 2218 | 1647:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2219 | 222 .loc 2 1647 48 view .LVU65 |
||
| 2220 | 223 0054 0901 lsls r1, r1, #4 |
||
| 20 | mjames | 2221 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 38 |
| 16 | mjames | 2222 | |
| 2223 | |||
| 2224 | 224 .LVL24: |
||
| 2225 | 1647:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2226 | 225 .loc 2 1647 48 view .LVU66 |
||
| 2227 | 226 0056 C9B2 uxtb r1, r1 |
||
| 2228 | 1647:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2229 | 227 .loc 2 1647 46 view .LVU67 |
||
| 2230 | 228 0058 024B ldr r3, .L10+4 |
||
| 2231 | 229 005a 1954 strb r1, [r3, r0] |
||
| 2232 | 230 .LVL25: |
||
| 2233 | 1647:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2234 | 231 .loc 2 1647 46 view .LVU68 |
||
| 2235 | 232 .LBE54: |
||
| 2236 | 233 .LBE55: |
||
| 2237 | 234 .loc 1 176 1 view .LVU69 |
||
| 2238 | 235 005c F6E7 b .L4 |
||
| 2239 | 236 .L11: |
||
| 2240 | 237 005e 00BF .align 2 |
||
| 2241 | 238 .L10: |
||
| 2242 | 239 0060 00ED00E0 .word -536810240 |
||
| 2243 | 240 0064 14ED00E0 .word -536810220 |
||
| 2244 | 241 .cfi_endproc |
||
| 2245 | 242 .LFE66: |
||
| 2246 | 244 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits |
||
| 2247 | 245 .align 1 |
||
| 2248 | 246 .global HAL_NVIC_EnableIRQ |
||
| 2249 | 247 .syntax unified |
||
| 2250 | 248 .thumb |
||
| 2251 | 249 .thumb_func |
||
| 2252 | 250 .fpu softvfp |
||
| 2253 | 252 HAL_NVIC_EnableIRQ: |
||
| 2254 | 253 .LVL26: |
||
| 2255 | 254 .LFB67: |
||
| 2256 | 177:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 2257 | 178:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 2258 | 179:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller. |
||
| 2259 | 180:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() |
||
| 2260 | 181:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * function should be called before. |
||
| 2261 | 182:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param IRQn External interrupt number. |
||
| 2262 | 183:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration |
||
| 2263 | 184:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI |
||
| 2264 | 185:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 2265 | 186:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 2266 | 187:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) |
||
| 2267 | 188:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 2268 | 255 .loc 1 188 1 is_stmt 1 view -0 |
||
| 2269 | 256 .cfi_startproc |
||
| 2270 | 257 @ args = 0, pretend = 0, frame = 0 |
||
| 2271 | 258 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2272 | 259 @ link register save eliminated. |
||
| 2273 | 189:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 2274 | 190:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||
| 2275 | 260 .loc 1 190 3 view .LVU71 |
||
| 2276 | 191:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 2277 | 192:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Enable interrupt */ |
||
| 2278 | 193:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); |
||
| 2279 | 261 .loc 1 193 3 view .LVU72 |
||
| 2280 | 262 .LBB56: |
||
| 20 | mjames | 2281 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 39 |
| 16 | mjames | 2282 | |
| 2283 | |||
| 2284 | 263 .LBI56: |
||
| 2285 | 1511:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2286 | 264 .loc 2 1511 22 view .LVU73 |
||
| 2287 | 265 .LBB57: |
||
| 2288 | 1513:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2289 | 266 .loc 2 1513 3 view .LVU74 |
||
| 2290 | 1513:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2291 | 267 .loc 2 1513 6 is_stmt 0 view .LVU75 |
||
| 2292 | 268 0000 0028 cmp r0, #0 |
||
| 2293 | 269 .LVL27: |
||
| 2294 | 1513:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2295 | 270 .loc 2 1513 6 view .LVU76 |
||
| 2296 | 271 0002 07DB blt .L12 |
||
| 2297 | 1515:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2298 | 272 .loc 2 1515 5 is_stmt 1 view .LVU77 |
||
| 2299 | 1515:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2300 | 273 .loc 2 1515 81 is_stmt 0 view .LVU78 |
||
| 2301 | 274 0004 00F01F02 and r2, r0, #31 |
||
| 2302 | 1515:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2303 | 275 .loc 2 1515 34 view .LVU79 |
||
| 2304 | 276 0008 4009 lsrs r0, r0, #5 |
||
| 2305 | 1515:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2306 | 277 .loc 2 1515 45 view .LVU80 |
||
| 2307 | 278 000a 0123 movs r3, #1 |
||
| 2308 | 279 000c 9340 lsls r3, r3, r2 |
||
| 2309 | 1515:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2310 | 280 .loc 2 1515 43 view .LVU81 |
||
| 2311 | 281 000e 024A ldr r2, .L14 |
||
| 2312 | 282 0010 42F82030 str r3, [r2, r0, lsl #2] |
||
| 2313 | 283 .LVL28: |
||
| 2314 | 284 .L12: |
||
| 2315 | 1515:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 2316 | 285 .loc 2 1515 43 view .LVU82 |
||
| 2317 | 286 .LBE57: |
||
| 2318 | 287 .LBE56: |
||
| 2319 | 194:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 2320 | 288 .loc 1 194 1 view .LVU83 |
||
| 2321 | 289 0014 7047 bx lr |
||
| 2322 | 290 .L15: |
||
| 2323 | 291 0016 00BF .align 2 |
||
| 2324 | 292 .L14: |
||
| 2325 | 293 0018 00E100E0 .word -536813312 |
||
| 2326 | 294 .cfi_endproc |
||
| 2327 | 295 .LFE67: |
||
| 2328 | 297 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits |
||
| 2329 | 298 .align 1 |
||
| 2330 | 299 .global HAL_NVIC_DisableIRQ |
||
| 2331 | 300 .syntax unified |
||
| 2332 | 301 .thumb |
||
| 2333 | 302 .thumb_func |
||
| 2334 | 303 .fpu softvfp |
||
| 2335 | 305 HAL_NVIC_DisableIRQ: |
||
| 2336 | 306 .LVL29: |
||
| 2337 | 307 .LFB68: |
||
| 2338 | 195:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 2339 | 196:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 2340 | 197:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller. |
||
| 20 | mjames | 2341 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 40 |
| 16 | mjames | 2342 | |
| 2343 | |||
| 2344 | 198:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param IRQn External interrupt number. |
||
| 2345 | 199:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration |
||
| 2346 | 200:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI |
||
| 2347 | 201:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 2348 | 202:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 2349 | 203:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) |
||
| 2350 | 204:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 2351 | 308 .loc 1 204 1 is_stmt 1 view -0 |
||
| 2352 | 309 .cfi_startproc |
||
| 2353 | 310 @ args = 0, pretend = 0, frame = 0 |
||
| 2354 | 311 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 2355 | 312 @ link register save eliminated. |
||
| 2356 | 205:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 2357 | 206:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||
| 2358 | 313 .loc 1 206 3 view .LVU85 |
||
| 2359 | 207:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 2360 | 208:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Disable interrupt */ |
||
| 2361 | 209:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); |
||
| 2362 | 314 .loc 1 209 3 view .LVU86 |
||
| 2363 | 315 .LBB58: |
||
| 2364 | 316 .LBI58: |
||
| 2365 | 1547:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2366 | 317 .loc 2 1547 22 view .LVU87 |
||
| 2367 | 318 .LBB59: |
||
| 2368 | 1549:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2369 | 319 .loc 2 1549 3 view .LVU88 |
||
| 2370 | 1549:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2371 | 320 .loc 2 1549 6 is_stmt 0 view .LVU89 |
||
| 2372 | 321 0000 0028 cmp r0, #0 |
||
| 2373 | 322 .LVL30: |
||
| 2374 | 1549:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 2375 | 323 .loc 2 1549 6 view .LVU90 |
||
| 2376 | 324 0002 0CDB blt .L16 |
||
| 2377 | 1551:Drivers/CMSIS/Include/core_cm3.h **** __DSB(); |
||
| 2378 | 325 .loc 2 1551 5 is_stmt 1 view .LVU91 |
||
| 2379 | 1551:Drivers/CMSIS/Include/core_cm3.h **** __DSB(); |
||
| 2380 | 326 .loc 2 1551 81 is_stmt 0 view .LVU92 |
||
| 2381 | 327 0004 00F01F02 and r2, r0, #31 |
||
| 2382 | 1551:Drivers/CMSIS/Include/core_cm3.h **** __DSB(); |
||
| 2383 | 328 .loc 2 1551 34 view .LVU93 |
||
| 2384 | 329 0008 4009 lsrs r0, r0, #5 |
||
| 2385 | 1551:Drivers/CMSIS/Include/core_cm3.h **** __DSB(); |
||
| 2386 | 330 .loc 2 1551 45 view .LVU94 |
||
| 2387 | 331 000a 0123 movs r3, #1 |
||
| 2388 | 332 000c 9340 lsls r3, r3, r2 |
||
| 2389 | 1551:Drivers/CMSIS/Include/core_cm3.h **** __DSB(); |
||
| 2390 | 333 .loc 2 1551 43 view .LVU95 |
||
| 2391 | 334 000e 2030 adds r0, r0, #32 |
||
| 2392 | 335 0010 034A ldr r2, .L18 |
||
| 2393 | 336 0012 42F82030 str r3, [r2, r0, lsl #2] |
||
| 2394 | 1552:Drivers/CMSIS/Include/core_cm3.h **** __ISB(); |
||
| 2395 | 337 .loc 2 1552 5 is_stmt 1 view .LVU96 |
||
| 2396 | 338 .LBB60: |
||
| 2397 | 339 .LBI60: |
||
| 2398 | 340 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" |
||
| 2399 | 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** |
||
| 2400 | 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h |
||
| 20 | mjames | 2401 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 41 |
| 16 | mjames | 2402 | |
| 2403 | |||
| 2404 | 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file |
||
| 2405 | 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 |
||
| 2406 | 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 |
||
| 2407 | 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ |
||
| 2408 | 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* |
||
| 2409 | 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
||
| 2410 | 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * |
||
| 2411 | 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 |
||
| 2412 | 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * |
||
| 2413 | 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may |
||
| 2414 | 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. |
||
| 2415 | 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at |
||
| 2416 | 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * |
||
| 2417 | 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 |
||
| 2418 | 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * |
||
| 2419 | 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software |
||
| 2420 | 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||
| 2421 | 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||
| 2422 | 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and |
||
| 2423 | 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. |
||
| 2424 | 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2425 | 24:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2426 | 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H |
||
| 2427 | 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H |
||
| 2428 | 27:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2429 | 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ |
||
| 2430 | 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 2431 | 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" |
||
| 2432 | 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" |
||
| 2433 | 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" |
||
| 2434 | 33:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2435 | 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ |
||
| 2436 | 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin |
||
| 2437 | 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) |
||
| 2438 | 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2439 | 38:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2440 | 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ |
||
| 2441 | 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM |
||
| 2442 | 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm |
||
| 2443 | 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2444 | 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE |
||
| 2445 | 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline |
||
| 2446 | 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2447 | 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE |
||
| 2448 | 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline |
||
| 2449 | 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2450 | 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE |
||
| 2451 | 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline |
||
| 2452 | 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2453 | 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN |
||
| 2454 | 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) |
||
| 2455 | 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2456 | 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED |
||
| 2457 | 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) |
||
| 2458 | 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2459 | 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK |
||
| 2460 | 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) |
||
| 20 | mjames | 2461 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 42 |
| 16 | mjames | 2462 | |
| 2463 | |||
| 2464 | 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2465 | 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED |
||
| 2466 | 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) |
||
| 2467 | 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2468 | 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT |
||
| 2469 | 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) |
||
| 2470 | 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2471 | 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION |
||
| 2472 | 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) |
||
| 2473 | 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2474 | 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ |
||
| 2475 | 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 2476 | 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 2477 | 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 2478 | 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; |
||
| 2479 | 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 2480 | 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
||
| 2481 | 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2482 | 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE |
||
| 2483 | 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 2484 | 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 2485 | 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 2486 | 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; |
||
| 2487 | 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 2488 | 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- |
||
| 2489 | 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2490 | 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ |
||
| 2491 | 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 2492 | 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 2493 | 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 2494 | 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; |
||
| 2495 | 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 2496 | 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add |
||
| 2497 | 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2498 | 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE |
||
| 2499 | 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 2500 | 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 2501 | 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 2502 | 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; |
||
| 2503 | 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 2504 | 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- |
||
| 2505 | 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2506 | 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ |
||
| 2507 | 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push |
||
| 2508 | 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" |
||
| 2509 | 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" |
||
| 2510 | 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; |
||
| 2511 | 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop |
||
| 2512 | 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add |
||
| 2513 | 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2514 | 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED |
||
| 2515 | 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) |
||
| 2516 | 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2517 | 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT |
||
| 2518 | 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict |
||
| 2519 | 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2520 | 116:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 20 | mjames | 2521 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 43 |
| 16 | mjames | 2522 | |
| 2523 | |||
| 2524 | 117:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2525 | 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ |
||
| 2526 | 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface |
||
| 2527 | 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
||
| 2528 | 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ |
||
| 2529 | 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2530 | 123:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2531 | 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2532 | 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts |
||
| 2533 | 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. |
||
| 2534 | 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. |
||
| 2535 | 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2536 | 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) |
||
| 2537 | 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2538 | 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); |
||
| 2539 | 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2540 | 133:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2541 | 134:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2542 | 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2543 | 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts |
||
| 2544 | 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. |
||
| 2545 | 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. |
||
| 2546 | 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2547 | 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) |
||
| 2548 | 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2549 | 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); |
||
| 2550 | 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2551 | 144:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2552 | 145:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2553 | 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2554 | 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register |
||
| 2555 | 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. |
||
| 2556 | 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value |
||
| 2557 | 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2558 | 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) |
||
| 2559 | 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2560 | 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2561 | 154:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2562 | 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); |
||
| 2563 | 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2564 | 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2565 | 158:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2566 | 159:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2567 | 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2568 | 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2569 | 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) |
||
| 2570 | 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. |
||
| 2571 | 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value |
||
| 2572 | 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2573 | 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) |
||
| 2574 | 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2575 | 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2576 | 169:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2577 | 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); |
||
| 2578 | 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2579 | 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2580 | 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 20 | mjames | 2581 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 44 |
| 16 | mjames | 2582 | |
| 2583 | |||
| 2584 | 174:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2585 | 175:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2586 | 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2587 | 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register |
||
| 2588 | 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. |
||
| 2589 | 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set |
||
| 2590 | 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2591 | 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) |
||
| 2592 | 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2593 | 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); |
||
| 2594 | 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2595 | 185:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2596 | 186:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2597 | 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2598 | 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2599 | 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) |
||
| 2600 | 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. |
||
| 2601 | 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set |
||
| 2602 | 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2603 | 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) |
||
| 2604 | 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2605 | 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); |
||
| 2606 | 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2607 | 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2608 | 198:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2609 | 199:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2610 | 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2611 | 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register |
||
| 2612 | 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. |
||
| 2613 | 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value |
||
| 2614 | 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2615 | 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) |
||
| 2616 | 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2617 | 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2618 | 208:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2619 | 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); |
||
| 2620 | 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2621 | 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2622 | 212:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2623 | 213:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2624 | 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2625 | 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register |
||
| 2626 | 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. |
||
| 2627 | 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value |
||
| 2628 | 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2629 | 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) |
||
| 2630 | 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2631 | 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2632 | 222:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2633 | 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); |
||
| 2634 | 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2635 | 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2636 | 226:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2637 | 227:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2638 | 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2639 | 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register |
||
| 2640 | 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. |
||
| 20 | mjames | 2641 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 45 |
| 16 | mjames | 2642 | |
| 2643 | |||
| 2644 | 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value |
||
| 2645 | 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2646 | 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) |
||
| 2647 | 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2648 | 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2649 | 236:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2650 | 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); |
||
| 2651 | 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2652 | 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2653 | 240:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2654 | 241:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2655 | 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2656 | 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer |
||
| 2657 | 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). |
||
| 2658 | 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value |
||
| 2659 | 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2660 | 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) |
||
| 2661 | 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2662 | 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2663 | 250:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2664 | 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); |
||
| 2665 | 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2666 | 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2667 | 254:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2668 | 255:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2669 | 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2670 | 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2671 | 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) |
||
| 2672 | 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s |
||
| 2673 | 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value |
||
| 2674 | 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2675 | 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) |
||
| 2676 | 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2677 | 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2678 | 265:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2679 | 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); |
||
| 2680 | 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2681 | 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2682 | 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2683 | 270:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2684 | 271:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2685 | 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2686 | 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer |
||
| 2687 | 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). |
||
| 2688 | 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set |
||
| 2689 | 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2690 | 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) |
||
| 2691 | 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2692 | 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); |
||
| 2693 | 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2694 | 281:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2695 | 282:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2696 | 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2697 | 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2698 | 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) |
||
| 2699 | 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta |
||
| 2700 | 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set |
||
| 20 | mjames | 2701 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 46 |
| 16 | mjames | 2702 | |
| 2703 | |||
| 2704 | 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2705 | 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) |
||
| 2706 | 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2707 | 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); |
||
| 2708 | 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2709 | 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2710 | 294:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2711 | 295:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2712 | 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2713 | 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer |
||
| 2714 | 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). |
||
| 2715 | 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value |
||
| 2716 | 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2717 | 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) |
||
| 2718 | 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2719 | 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2720 | 304:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2721 | 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); |
||
| 2722 | 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2723 | 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2724 | 308:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2725 | 309:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2726 | 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2727 | 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2728 | 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) |
||
| 2729 | 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat |
||
| 2730 | 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value |
||
| 2731 | 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2732 | 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) |
||
| 2733 | 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2734 | 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2735 | 319:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2736 | 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); |
||
| 2737 | 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2738 | 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2739 | 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2740 | 324:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2741 | 325:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2742 | 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2743 | 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer |
||
| 2744 | 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). |
||
| 2745 | 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set |
||
| 2746 | 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2747 | 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) |
||
| 2748 | 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2749 | 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); |
||
| 2750 | 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2751 | 335:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2752 | 336:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2753 | 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2754 | 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2755 | 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) |
||
| 2756 | 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. |
||
| 2757 | 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set |
||
| 2758 | 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2759 | 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) |
||
| 2760 | 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 20 | mjames | 2761 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 47 |
| 16 | mjames | 2762 | |
| 2763 | |||
| 2764 | 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); |
||
| 2765 | 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2766 | 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2767 | 348:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2768 | 349:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2769 | 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2770 | 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2771 | 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) |
||
| 2772 | 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. |
||
| 2773 | 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value |
||
| 2774 | 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2775 | 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) |
||
| 2776 | 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2777 | 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2778 | 359:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2779 | 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); |
||
| 2780 | 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2781 | 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2782 | 363:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2783 | 364:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2784 | 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2785 | 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) |
||
| 2786 | 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. |
||
| 2787 | 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set |
||
| 2788 | 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2789 | 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) |
||
| 2790 | 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2791 | 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); |
||
| 2792 | 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2793 | 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2794 | 375:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2795 | 376:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2796 | 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2797 | 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask |
||
| 2798 | 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. |
||
| 2799 | 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value |
||
| 2800 | 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2801 | 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) |
||
| 2802 | 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2803 | 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2804 | 385:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2805 | 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); |
||
| 2806 | 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2807 | 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2808 | 389:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2809 | 390:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2810 | 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2811 | 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2812 | 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) |
||
| 2813 | 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg |
||
| 2814 | 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value |
||
| 2815 | 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2816 | 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) |
||
| 2817 | 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2818 | 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2819 | 400:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2820 | 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); |
||
| 20 | mjames | 2821 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 48 |
| 16 | mjames | 2822 | |
| 2823 | |||
| 2824 | 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2825 | 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2826 | 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2827 | 405:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2828 | 406:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2829 | 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2830 | 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask |
||
| 2831 | 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. |
||
| 2832 | 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask |
||
| 2833 | 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2834 | 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) |
||
| 2835 | 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2836 | 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); |
||
| 2837 | 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2838 | 416:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2839 | 417:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2840 | 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2841 | 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2842 | 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) |
||
| 2843 | 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. |
||
| 2844 | 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask |
||
| 2845 | 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2846 | 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) |
||
| 2847 | 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2848 | 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); |
||
| 2849 | 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2850 | 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2851 | 429:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2852 | 430:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2853 | 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||
| 2854 | 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
||
| 2855 | 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
||
| 2856 | 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2857 | 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ |
||
| 2858 | 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. |
||
| 2859 | 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. |
||
| 2860 | 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2861 | 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) |
||
| 2862 | 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2863 | 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); |
||
| 2864 | 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2865 | 443:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2866 | 444:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2867 | 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2868 | 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ |
||
| 2869 | 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. |
||
| 2870 | 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. |
||
| 2871 | 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2872 | 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) |
||
| 2873 | 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2874 | 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); |
||
| 2875 | 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2876 | 454:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2877 | 455:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2878 | 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2879 | 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority |
||
| 2880 | 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. |
||
| 20 | mjames | 2881 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 49 |
| 16 | mjames | 2882 | |
| 2883 | |||
| 2884 | 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value |
||
| 2885 | 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2886 | 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) |
||
| 2887 | 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2888 | 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2889 | 464:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2890 | 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); |
||
| 2891 | 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2892 | 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2893 | 468:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2894 | 469:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2895 | 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2896 | 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2897 | 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) |
||
| 2898 | 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. |
||
| 2899 | 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value |
||
| 2900 | 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2901 | 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) |
||
| 2902 | 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2903 | 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2904 | 479:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2905 | 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); |
||
| 2906 | 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2907 | 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2908 | 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2909 | 484:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2910 | 485:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2911 | 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2912 | 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority |
||
| 2913 | 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. |
||
| 2914 | 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set |
||
| 2915 | 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2916 | 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) |
||
| 2917 | 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2918 | 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); |
||
| 2919 | 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2920 | 495:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2921 | 496:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2922 | 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2923 | 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2924 | 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) |
||
| 2925 | 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. |
||
| 2926 | 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set |
||
| 2927 | 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2928 | 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) |
||
| 2929 | 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2930 | 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); |
||
| 2931 | 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2932 | 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2933 | 508:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2934 | 509:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2935 | 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2936 | 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition |
||
| 2937 | 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable |
||
| 2938 | 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. |
||
| 2939 | 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set |
||
| 2940 | 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 20 | mjames | 2941 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 50 |
| 16 | mjames | 2942 | |
| 2943 | |||
| 2944 | 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) |
||
| 2945 | 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2946 | 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); |
||
| 2947 | 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2948 | 520:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2949 | 521:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2950 | 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2951 | 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask |
||
| 2952 | 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. |
||
| 2953 | 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value |
||
| 2954 | 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2955 | 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) |
||
| 2956 | 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2957 | 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2958 | 530:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2959 | 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
||
| 2960 | 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2961 | 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2962 | 534:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2963 | 535:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2964 | 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2965 | 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2966 | 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) |
||
| 2967 | 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. |
||
| 2968 | 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value |
||
| 2969 | 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2970 | 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) |
||
| 2971 | 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2972 | 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 2973 | 545:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2974 | 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); |
||
| 2975 | 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 2976 | 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2977 | 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 2978 | 550:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2979 | 551:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2980 | 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2981 | 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask |
||
| 2982 | 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. |
||
| 2983 | 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set |
||
| 2984 | 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2985 | 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) |
||
| 2986 | 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2987 | 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); |
||
| 2988 | 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 2989 | 561:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2990 | 562:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 2991 | 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 2992 | 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 2993 | 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) |
||
| 2994 | 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. |
||
| 2995 | 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set |
||
| 2996 | 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 2997 | 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) |
||
| 2998 | 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 2999 | 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); |
||
| 3000 | 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 20 | mjames | 3001 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 51 |
| 16 | mjames | 3002 | |
| 3003 | |||
| 3004 | 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3005 | 574:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3006 | 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||
| 3007 | 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
||
| 3008 | 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ |
||
| 3009 | 578:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3010 | 579:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3011 | 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
||
| 3012 | 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
||
| 3013 | 582:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3014 | 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3015 | 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit |
||
| 3016 | 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 3017 | 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure |
||
| 3018 | 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. |
||
| 3019 | 588:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3020 | 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). |
||
| 3021 | 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value |
||
| 3022 | 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3023 | 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) |
||
| 3024 | 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3025 | 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||
| 3026 | 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||
| 3027 | 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI |
||
| 3028 | 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; |
||
| 3029 | 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3030 | 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 3031 | 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); |
||
| 3032 | 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 3033 | 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3034 | 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3035 | 604:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3036 | 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) |
||
| 3037 | 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3038 | 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) |
||
| 3039 | 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 3040 | 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. |
||
| 3041 | 610:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3042 | 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in |
||
| 3043 | 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value |
||
| 3044 | 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3045 | 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) |
||
| 3046 | 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3047 | 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) |
||
| 3048 | 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI |
||
| 3049 | 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; |
||
| 3050 | 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3051 | 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 3052 | 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); |
||
| 3053 | 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 3054 | 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3055 | 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3056 | 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3057 | 626:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3058 | 627:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3059 | 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3060 | 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit |
||
| 20 | mjames | 3061 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 52 |
| 16 | mjames | 3062 | |
| 3063 | |||
| 3064 | 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 3065 | 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure |
||
| 3066 | 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. |
||
| 3067 | 633:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3068 | 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). |
||
| 3069 | 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set |
||
| 3070 | 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3071 | 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) |
||
| 3072 | 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3073 | 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||
| 3074 | 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||
| 3075 | 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI |
||
| 3076 | 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; |
||
| 3077 | 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3078 | 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); |
||
| 3079 | 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3080 | 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3081 | 647:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3082 | 648:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3083 | 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 3084 | 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3085 | 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) |
||
| 3086 | 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 3087 | 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. |
||
| 3088 | 654:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3089 | 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s |
||
| 3090 | 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set |
||
| 3091 | 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3092 | 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) |
||
| 3093 | 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3094 | 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) |
||
| 3095 | 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI |
||
| 3096 | 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; |
||
| 3097 | 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3098 | 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); |
||
| 3099 | 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3100 | 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3101 | 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3102 | 668:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3103 | 669:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3104 | 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3105 | 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit |
||
| 3106 | 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 3107 | 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure |
||
| 3108 | 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. |
||
| 3109 | 675:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3110 | 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). |
||
| 3111 | 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value |
||
| 3112 | 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3113 | 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) |
||
| 3114 | 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3115 | 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||
| 3116 | 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||
| 3117 | 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI |
||
| 3118 | 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; |
||
| 3119 | 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3120 | 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 20 | mjames | 3121 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 53 |
| 16 | mjames | 3122 | |
| 3123 | |||
| 3124 | 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); |
||
| 3125 | 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 3126 | 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3127 | 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3128 | 691:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3129 | 692:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3130 | 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 3131 | 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3132 | 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) |
||
| 3133 | 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 3134 | 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. |
||
| 3135 | 698:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3136 | 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec |
||
| 3137 | 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value |
||
| 3138 | 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3139 | 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) |
||
| 3140 | 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3141 | 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) |
||
| 3142 | 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI |
||
| 3143 | 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; |
||
| 3144 | 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3145 | 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 3146 | 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); |
||
| 3147 | 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; |
||
| 3148 | 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3149 | 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3150 | 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3151 | 714:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3152 | 715:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3153 | 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3154 | 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit |
||
| 3155 | 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 3156 | 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure |
||
| 3157 | 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. |
||
| 3158 | 721:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3159 | 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). |
||
| 3160 | 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set |
||
| 3161 | 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3162 | 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) |
||
| 3163 | 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3164 | 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||
| 3165 | 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||
| 3166 | 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI |
||
| 3167 | 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; |
||
| 3168 | 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3169 | 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); |
||
| 3170 | 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3171 | 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3172 | 735:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3173 | 736:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3174 | 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
||
| 3175 | 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3176 | 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) |
||
| 3177 | 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure |
||
| 3178 | 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. |
||
| 3179 | 742:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3180 | 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu |
||
| 20 | mjames | 3181 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 54 |
| 16 | mjames | 3182 | |
| 3183 | |||
| 3184 | 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set |
||
| 3185 | 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3186 | 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) |
||
| 3187 | 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3188 | 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) |
||
| 3189 | 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI |
||
| 3190 | 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; |
||
| 3191 | 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3192 | 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); |
||
| 3193 | 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3194 | 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3195 | 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3196 | 756:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3197 | 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
||
| 3198 | 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ |
||
| 3199 | 759:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3200 | 760:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3201 | 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3202 | 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR |
||
| 3203 | 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. |
||
| 3204 | 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value |
||
| 3205 | 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3206 | 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) |
||
| 3207 | 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3208 | 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||
| 3209 | 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
||
| 3210 | 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) |
||
| 3211 | 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed |
||
| 3212 | 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) |
||
| 3213 | 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ |
||
| 3214 | 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); |
||
| 3215 | 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3216 | 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; |
||
| 3217 | 777:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3218 | 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); |
||
| 3219 | 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); |
||
| 3220 | 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3221 | 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3222 | 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); |
||
| 3223 | 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3224 | 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3225 | 785:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3226 | 786:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3227 | 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3228 | 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR |
||
| 3229 | 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. |
||
| 3230 | 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set |
||
| 3231 | 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3232 | 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) |
||
| 3233 | 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3234 | 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||
| 3235 | 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
||
| 3236 | 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) |
||
| 3237 | 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed |
||
| 3238 | 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) |
||
| 3239 | 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ |
||
| 3240 | 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); |
||
| 20 | mjames | 3241 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 55 |
| 16 | mjames | 3242 | |
| 3243 | |||
| 3244 | 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3245 | 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); |
||
| 3246 | 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3247 | 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3248 | 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; |
||
| 3249 | 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3250 | 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3251 | 808:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3252 | 809:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3253 | 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ |
||
| 3254 | 811:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3255 | 812:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3256 | 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ |
||
| 3257 | 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface |
||
| 3258 | 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions |
||
| 3259 | 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ |
||
| 3260 | 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3261 | 818:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3262 | 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. |
||
| 3263 | 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" |
||
| 3264 | 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ |
||
| 3265 | 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) |
||
| 3266 | 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) |
||
| 3267 | 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) |
||
| 3268 | 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) |
||
| 3269 | 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else |
||
| 3270 | 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) |
||
| 3271 | 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) |
||
| 3272 | 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) |
||
| 3273 | 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif |
||
| 3274 | 831:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3275 | 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3276 | 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation |
||
| 3277 | 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. |
||
| 3278 | 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3279 | 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") |
||
| 3280 | 837:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3281 | 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3282 | 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt |
||
| 3283 | 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o |
||
| 3284 | 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3285 | 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") |
||
| 3286 | 843:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3287 | 844:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3288 | 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3289 | 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event |
||
| 3290 | 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter |
||
| 3291 | 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. |
||
| 3292 | 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3293 | 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") |
||
| 3294 | 851:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3295 | 852:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3296 | 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3297 | 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event |
||
| 3298 | 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
||
| 3299 | 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3300 | 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") |
||
| 20 | mjames | 3301 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 56 |
| 16 | mjames | 3302 | |
| 3303 | |||
| 3304 | 858:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3305 | 859:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3306 | 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3307 | 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier |
||
| 3308 | 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, |
||
| 3309 | 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, |
||
| 3310 | 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. |
||
| 3311 | 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3312 | 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) |
||
| 3313 | 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3314 | 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); |
||
| 3315 | 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3316 | 870:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3317 | 871:Drivers/CMSIS/Include/cmsis_gcc.h **** |
||
| 3318 | 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** |
||
| 3319 | 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier |
||
| 3320 | 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. |
||
| 3321 | 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. |
||
| 3322 | 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ |
||
| 3323 | 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) |
||
| 3324 | 341 .loc 3 877 27 view .LVU97 |
||
| 3325 | 342 .LBB61: |
||
| 3326 | 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3327 | 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); |
||
| 3328 | 343 .loc 3 879 3 view .LVU98 |
||
| 3329 | 344 .syntax unified |
||
| 3330 | 345 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 |
||
| 3331 | 346 0016 BFF34F8F dsb 0xF |
||
| 3332 | 347 @ 0 "" 2 |
||
| 3333 | 348 .thumb |
||
| 3334 | 349 .syntax unified |
||
| 3335 | 350 .LBE61: |
||
| 3336 | 351 .LBE60: |
||
| 3337 | 1553:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3338 | 352 .loc 2 1553 5 view .LVU99 |
||
| 3339 | 353 .LBB62: |
||
| 3340 | 354 .LBI62: |
||
| 3341 | 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3342 | 355 .loc 3 866 27 view .LVU100 |
||
| 3343 | 356 .LBB63: |
||
| 3344 | 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3345 | 357 .loc 3 868 3 view .LVU101 |
||
| 3346 | 358 .syntax unified |
||
| 3347 | 359 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 |
||
| 3348 | 360 001a BFF36F8F isb 0xF |
||
| 3349 | 361 @ 0 "" 2 |
||
| 3350 | 362 .LVL31: |
||
| 3351 | 363 .thumb |
||
| 3352 | 364 .syntax unified |
||
| 3353 | 365 .L16: |
||
| 3354 | 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } |
||
| 3355 | 366 .loc 3 868 3 is_stmt 0 view .LVU102 |
||
| 3356 | 367 .LBE63: |
||
| 3357 | 368 .LBE62: |
||
| 3358 | 369 .LBE59: |
||
| 3359 | 370 .LBE58: |
||
| 3360 | 210:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 20 | mjames | 3361 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 57 |
| 16 | mjames | 3362 | |
| 3363 | |||
| 3364 | 371 .loc 1 210 1 view .LVU103 |
||
| 3365 | 372 001e 7047 bx lr |
||
| 3366 | 373 .L19: |
||
| 3367 | 374 .align 2 |
||
| 3368 | 375 .L18: |
||
| 3369 | 376 0020 00E100E0 .word -536813312 |
||
| 3370 | 377 .cfi_endproc |
||
| 3371 | 378 .LFE68: |
||
| 3372 | 380 .section .text.HAL_NVIC_SystemReset,"ax",%progbits |
||
| 3373 | 381 .align 1 |
||
| 3374 | 382 .global HAL_NVIC_SystemReset |
||
| 3375 | 383 .syntax unified |
||
| 3376 | 384 .thumb |
||
| 3377 | 385 .thumb_func |
||
| 3378 | 386 .fpu softvfp |
||
| 3379 | 388 HAL_NVIC_SystemReset: |
||
| 3380 | 389 .LFB69: |
||
| 3381 | 211:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3382 | 212:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 3383 | 213:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU. |
||
| 3384 | 214:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 3385 | 215:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 3386 | 216:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) |
||
| 3387 | 217:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 3388 | 390 .loc 1 217 1 is_stmt 1 view -0 |
||
| 3389 | 391 .cfi_startproc |
||
| 3390 | 392 @ Volatile: function does not return. |
||
| 3391 | 393 @ args = 0, pretend = 0, frame = 0 |
||
| 3392 | 394 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 3393 | 395 @ link register save eliminated. |
||
| 3394 | 218:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* System Reset */ |
||
| 3395 | 219:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** NVIC_SystemReset(); |
||
| 3396 | 396 .loc 1 219 3 view .LVU105 |
||
| 3397 | 397 .LBB70: |
||
| 3398 | 398 .LBI70: |
||
| 3399 | 1698:Drivers/CMSIS/Include/core_cm3.h **** ); |
||
| 3400 | 1699:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3401 | 1700:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3402 | 1701:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3403 | 1702:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 3404 | 1703:Drivers/CMSIS/Include/core_cm3.h **** \brief Decode Priority |
||
| 3405 | 1704:Drivers/CMSIS/Include/core_cm3.h **** \details Decodes an interrupt priority value with a given priority group to |
||
| 3406 | 1705:Drivers/CMSIS/Include/core_cm3.h **** preemptive priority value and subpriority value. |
||
| 3407 | 1706:Drivers/CMSIS/Include/core_cm3.h **** In case of a conflict between priority grouping and available |
||
| 3408 | 1707:Drivers/CMSIS/Include/core_cm3.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
||
| 3409 | 1708:Drivers/CMSIS/Include/core_cm3.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC |
||
| 3410 | 1709:Drivers/CMSIS/Include/core_cm3.h **** \param [in] PriorityGroup Used priority group. |
||
| 3411 | 1710:Drivers/CMSIS/Include/core_cm3.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
||
| 3412 | 1711:Drivers/CMSIS/Include/core_cm3.h **** \param [out] pSubPriority Subpriority value (starting from 0). |
||
| 3413 | 1712:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 3414 | 1713:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons |
||
| 3415 | 1714:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3416 | 1715:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used |
||
| 3417 | 1716:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PreemptPriorityBits; |
||
| 3418 | 1717:Drivers/CMSIS/Include/core_cm3.h **** uint32_t SubPriorityBits; |
||
| 3419 | 1718:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3420 | 1719:Drivers/CMSIS/Include/core_cm3.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV |
||
| 20 | mjames | 3421 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 58 |
| 16 | mjames | 3422 | |
| 3423 | |||
| 3424 | 1720:Drivers/CMSIS/Include/core_cm3.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint |
||
| 3425 | 1721:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3426 | 1722:Drivers/CMSIS/Include/core_cm3.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 |
||
| 3427 | 1723:Drivers/CMSIS/Include/core_cm3.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 |
||
| 3428 | 1724:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3429 | 1725:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3430 | 1726:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3431 | 1727:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 3432 | 1728:Drivers/CMSIS/Include/core_cm3.h **** \brief Set Interrupt Vector |
||
| 3433 | 1729:Drivers/CMSIS/Include/core_cm3.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. |
||
| 3434 | 1730:Drivers/CMSIS/Include/core_cm3.h **** The interrupt number can be positive to specify a device specific interrupt, |
||
| 3435 | 1731:Drivers/CMSIS/Include/core_cm3.h **** or negative to specify a processor exception. |
||
| 3436 | 1732:Drivers/CMSIS/Include/core_cm3.h **** VTOR must been relocated to SRAM before. |
||
| 3437 | 1733:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Interrupt number |
||
| 3438 | 1734:Drivers/CMSIS/Include/core_cm3.h **** \param [in] vector Address of interrupt handler function |
||
| 3439 | 1735:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 3440 | 1736:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
||
| 3441 | 1737:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3442 | 1738:Drivers/CMSIS/Include/core_cm3.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; |
||
| 3443 | 1739:Drivers/CMSIS/Include/core_cm3.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
||
| 3444 | 1740:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3445 | 1741:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3446 | 1742:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3447 | 1743:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 3448 | 1744:Drivers/CMSIS/Include/core_cm3.h **** \brief Get Interrupt Vector |
||
| 3449 | 1745:Drivers/CMSIS/Include/core_cm3.h **** \details Reads an interrupt vector from interrupt vector table. |
||
| 3450 | 1746:Drivers/CMSIS/Include/core_cm3.h **** The interrupt number can be positive to specify a device specific interrupt, |
||
| 3451 | 1747:Drivers/CMSIS/Include/core_cm3.h **** or negative to specify a processor exception. |
||
| 3452 | 1748:Drivers/CMSIS/Include/core_cm3.h **** \param [in] IRQn Interrupt number. |
||
| 3453 | 1749:Drivers/CMSIS/Include/core_cm3.h **** \return Address of interrupt handler function |
||
| 3454 | 1750:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 3455 | 1751:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
||
| 3456 | 1752:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3457 | 1753:Drivers/CMSIS/Include/core_cm3.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; |
||
| 3458 | 1754:Drivers/CMSIS/Include/core_cm3.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
||
| 3459 | 1755:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3460 | 1756:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3461 | 1757:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3462 | 1758:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 3463 | 1759:Drivers/CMSIS/Include/core_cm3.h **** \brief System Reset |
||
| 3464 | 1760:Drivers/CMSIS/Include/core_cm3.h **** \details Initiates a system reset request to reset the MCU. |
||
| 3465 | 1761:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 3466 | 1762:Drivers/CMSIS/Include/core_cm3.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) |
||
| 3467 | 399 .loc 2 1762 34 view .LVU106 |
||
| 3468 | 400 .LBB71: |
||
| 3469 | 1763:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3470 | 1764:Drivers/CMSIS/Include/core_cm3.h **** __DSB(); /* Ensure all outstanding memor |
||
| 3471 | 401 .loc 2 1764 3 view .LVU107 |
||
| 3472 | 402 .LBB72: |
||
| 3473 | 403 .LBI72: |
||
| 3474 | 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3475 | 404 .loc 3 877 27 view .LVU108 |
||
| 3476 | 405 .LBB73: |
||
| 3477 | 406 .loc 3 879 3 view .LVU109 |
||
| 3478 | 407 .syntax unified |
||
| 3479 | 408 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 |
||
| 3480 | 409 0000 BFF34F8F dsb 0xF |
||
| 20 | mjames | 3481 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 59 |
| 16 | mjames | 3482 | |
| 3483 | |||
| 3484 | 410 @ 0 "" 2 |
||
| 3485 | 411 .thumb |
||
| 3486 | 412 .syntax unified |
||
| 3487 | 413 .LBE73: |
||
| 3488 | 414 .LBE72: |
||
| 3489 | 1765:Drivers/CMSIS/Include/core_cm3.h **** buffered write are completed |
||
| 3490 | 1766:Drivers/CMSIS/Include/core_cm3.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||
| 3491 | 415 .loc 2 1766 3 view .LVU110 |
||
| 3492 | 1767:Drivers/CMSIS/Include/core_cm3.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
||
| 3493 | 416 .loc 2 1767 32 is_stmt 0 view .LVU111 |
||
| 3494 | 417 0004 0549 ldr r1, .L22 |
||
| 3495 | 418 0006 CA68 ldr r2, [r1, #12] |
||
| 3496 | 419 .loc 2 1767 40 view .LVU112 |
||
| 3497 | 420 0008 02F4E062 and r2, r2, #1792 |
||
| 3498 | 1766:Drivers/CMSIS/Include/core_cm3.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
||
| 3499 | 421 .loc 2 1766 17 view .LVU113 |
||
| 3500 | 422 000c 044B ldr r3, .L22+4 |
||
| 3501 | 423 000e 1343 orrs r3, r3, r2 |
||
| 3502 | 1766:Drivers/CMSIS/Include/core_cm3.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
||
| 3503 | 424 .loc 2 1766 15 view .LVU114 |
||
| 3504 | 425 0010 CB60 str r3, [r1, #12] |
||
| 3505 | 1768:Drivers/CMSIS/Include/core_cm3.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange |
||
| 3506 | 1769:Drivers/CMSIS/Include/core_cm3.h **** __DSB(); /* Ensure completion of memory |
||
| 3507 | 426 .loc 2 1769 3 is_stmt 1 view .LVU115 |
||
| 3508 | 427 .LBB74: |
||
| 3509 | 428 .LBI74: |
||
| 3510 | 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { |
||
| 3511 | 429 .loc 3 877 27 view .LVU116 |
||
| 3512 | 430 .LBB75: |
||
| 3513 | 431 .loc 3 879 3 view .LVU117 |
||
| 3514 | 432 .syntax unified |
||
| 3515 | 433 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 |
||
| 3516 | 434 0012 BFF34F8F dsb 0xF |
||
| 3517 | 435 @ 0 "" 2 |
||
| 3518 | 436 .thumb |
||
| 3519 | 437 .syntax unified |
||
| 3520 | 438 .L21: |
||
| 3521 | 439 .LBE75: |
||
| 3522 | 440 .LBE74: |
||
| 3523 | 1770:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3524 | 1771:Drivers/CMSIS/Include/core_cm3.h **** for(;;) /* wait until reset */ |
||
| 3525 | 441 .loc 2 1771 3 view .LVU118 |
||
| 3526 | 1772:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3527 | 1773:Drivers/CMSIS/Include/core_cm3.h **** __NOP(); |
||
| 3528 | 442 .loc 2 1773 5 view .LVU119 |
||
| 3529 | 443 .syntax unified |
||
| 3530 | 444 @ 1773 "Drivers/CMSIS/Include/core_cm3.h" 1 |
||
| 3531 | 445 0016 00BF nop |
||
| 3532 | 446 @ 0 "" 2 |
||
| 3533 | 447 .thumb |
||
| 3534 | 448 .syntax unified |
||
| 3535 | 449 0018 FDE7 b .L21 |
||
| 3536 | 450 .L23: |
||
| 3537 | 451 001a 00BF .align 2 |
||
| 3538 | 452 .L22: |
||
| 3539 | 453 001c 00ED00E0 .word -536810240 |
||
| 3540 | 454 0020 0400FA05 .word 100270084 |
||
| 20 | mjames | 3541 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 60 |
| 16 | mjames | 3542 | |
| 3543 | |||
| 3544 | 455 .LBE71: |
||
| 3545 | 456 .LBE70: |
||
| 3546 | 457 .cfi_endproc |
||
| 3547 | 458 .LFE69: |
||
| 3548 | 460 .section .text.HAL_SYSTICK_Config,"ax",%progbits |
||
| 3549 | 461 .align 1 |
||
| 3550 | 462 .global HAL_SYSTICK_Config |
||
| 3551 | 463 .syntax unified |
||
| 3552 | 464 .thumb |
||
| 3553 | 465 .thumb_func |
||
| 3554 | 466 .fpu softvfp |
||
| 3555 | 468 HAL_SYSTICK_Config: |
||
| 3556 | 469 .LVL32: |
||
| 3557 | 470 .LFB70: |
||
| 3558 | 220:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 3559 | 221:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3560 | 222:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 3561 | 223:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||
| 3562 | 224:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. |
||
| 3563 | 225:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. |
||
| 3564 | 226:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval status: - 0 Function succeeded. |
||
| 3565 | 227:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * - 1 Function failed. |
||
| 3566 | 228:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 3567 | 229:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) |
||
| 3568 | 230:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 3569 | 471 .loc 1 230 1 view -0 |
||
| 3570 | 472 .cfi_startproc |
||
| 3571 | 473 @ args = 0, pretend = 0, frame = 0 |
||
| 3572 | 474 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 3573 | 475 @ link register save eliminated. |
||
| 3574 | 231:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** return SysTick_Config(TicksNumb); |
||
| 3575 | 476 .loc 1 231 4 view .LVU121 |
||
| 3576 | 477 .LBB76: |
||
| 3577 | 478 .LBI76: |
||
| 3578 | 1774:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3579 | 1775:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3580 | 1776:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3581 | 1777:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of CMSIS_Core_NVICFunctions */ |
||
| 3582 | 1778:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3583 | 1779:Drivers/CMSIS/Include/core_cm3.h **** /* ########################## MPU functions #################################### */ |
||
| 3584 | 1780:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3585 | 1781:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
||
| 3586 | 1782:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3587 | 1783:Drivers/CMSIS/Include/core_cm3.h **** #include "mpu_armv7.h" |
||
| 3588 | 1784:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3589 | 1785:Drivers/CMSIS/Include/core_cm3.h **** #endif |
||
| 3590 | 1786:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3591 | 1787:Drivers/CMSIS/Include/core_cm3.h **** /* ########################## FPU functions #################################### */ |
||
| 3592 | 1788:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 3593 | 1789:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_Core_FunctionInterface |
||
| 3594 | 1790:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions |
||
| 3595 | 1791:Drivers/CMSIS/Include/core_cm3.h **** \brief Function that provides FPU type. |
||
| 3596 | 1792:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 3597 | 1793:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 3598 | 1794:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3599 | 1795:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 3600 | 1796:Drivers/CMSIS/Include/core_cm3.h **** \brief get FPU type |
||
| 20 | mjames | 3601 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 61 |
| 16 | mjames | 3602 | |
| 3603 | |||
| 3604 | 1797:Drivers/CMSIS/Include/core_cm3.h **** \details returns the FPU type |
||
| 3605 | 1798:Drivers/CMSIS/Include/core_cm3.h **** \returns |
||
| 3606 | 1799:Drivers/CMSIS/Include/core_cm3.h **** - \b 0: No FPU |
||
| 3607 | 1800:Drivers/CMSIS/Include/core_cm3.h **** - \b 1: Single precision FPU |
||
| 3608 | 1801:Drivers/CMSIS/Include/core_cm3.h **** - \b 2: Double + Single precision FPU |
||
| 3609 | 1802:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 3610 | 1803:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
||
| 3611 | 1804:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3612 | 1805:Drivers/CMSIS/Include/core_cm3.h **** return 0U; /* No FPU */ |
||
| 3613 | 1806:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3614 | 1807:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3615 | 1808:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3616 | 1809:Drivers/CMSIS/Include/core_cm3.h **** /*@} end of CMSIS_Core_FpuFunctions */ |
||
| 3617 | 1810:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3618 | 1811:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3619 | 1812:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3620 | 1813:Drivers/CMSIS/Include/core_cm3.h **** /* ################################## SysTick function ######################################## |
||
| 3621 | 1814:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 3622 | 1815:Drivers/CMSIS/Include/core_cm3.h **** \ingroup CMSIS_Core_FunctionInterface |
||
| 3623 | 1816:Drivers/CMSIS/Include/core_cm3.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||
| 3624 | 1817:Drivers/CMSIS/Include/core_cm3.h **** \brief Functions that configure the System. |
||
| 3625 | 1818:Drivers/CMSIS/Include/core_cm3.h **** @{ |
||
| 3626 | 1819:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 3627 | 1820:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3628 | 1821:Drivers/CMSIS/Include/core_cm3.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
||
| 3629 | 1822:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3630 | 1823:Drivers/CMSIS/Include/core_cm3.h **** /** |
||
| 3631 | 1824:Drivers/CMSIS/Include/core_cm3.h **** \brief System Tick Configuration |
||
| 3632 | 1825:Drivers/CMSIS/Include/core_cm3.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||
| 3633 | 1826:Drivers/CMSIS/Include/core_cm3.h **** Counter is in free running mode to generate periodic interrupts. |
||
| 3634 | 1827:Drivers/CMSIS/Include/core_cm3.h **** \param [in] ticks Number of ticks between two interrupts. |
||
| 3635 | 1828:Drivers/CMSIS/Include/core_cm3.h **** \return 0 Function succeeded. |
||
| 3636 | 1829:Drivers/CMSIS/Include/core_cm3.h **** \return 1 Function failed. |
||
| 3637 | 1830:Drivers/CMSIS/Include/core_cm3.h **** \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||
| 3638 | 1831:Drivers/CMSIS/Include/core_cm3.h **** function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>. |
||
| 3639 | 1832:Drivers/CMSIS/Include/core_cm3.h **** must contain a vendor-specific implementation of this function. |
||
| 3640 | 1833:Drivers/CMSIS/Include/core_cm3.h **** */ |
||
| 3641 | 1834:Drivers/CMSIS/Include/core_cm3.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||
| 3642 | 479 .loc 2 1834 26 view .LVU122 |
||
| 3643 | 480 .LBB77: |
||
| 3644 | 1835:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3645 | 1836:Drivers/CMSIS/Include/core_cm3.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||
| 3646 | 481 .loc 2 1836 3 view .LVU123 |
||
| 3647 | 482 .loc 2 1836 14 is_stmt 0 view .LVU124 |
||
| 3648 | 483 0000 0138 subs r0, r0, #1 |
||
| 3649 | 484 .LVL33: |
||
| 3650 | 485 .loc 2 1836 6 view .LVU125 |
||
| 3651 | 486 0002 B0F1807F cmp r0, #16777216 |
||
| 3652 | 487 0006 0AD2 bcs .L26 |
||
| 3653 | 1837:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3654 | 1838:Drivers/CMSIS/Include/core_cm3.h **** return (1UL); /* Reload value impossible */ |
||
| 3655 | 1839:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3656 | 1840:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3657 | 1841:Drivers/CMSIS/Include/core_cm3.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||
| 3658 | 488 .loc 2 1841 3 is_stmt 1 view .LVU126 |
||
| 3659 | 489 .loc 2 1841 18 is_stmt 0 view .LVU127 |
||
| 3660 | 490 0008 064B ldr r3, .L27 |
||
| 20 | mjames | 3661 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 62 |
| 16 | mjames | 3662 | |
| 3663 | |||
| 3664 | 491 000a 5860 str r0, [r3, #4] |
||
| 3665 | 1842:Drivers/CMSIS/Include/core_cm3.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int |
||
| 3666 | 492 .loc 2 1842 3 is_stmt 1 view .LVU128 |
||
| 3667 | 493 .LVL34: |
||
| 3668 | 494 .LBB78: |
||
| 3669 | 495 .LBI78: |
||
| 3670 | 1639:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3671 | 496 .loc 2 1639 22 view .LVU129 |
||
| 3672 | 497 .LBB79: |
||
| 3673 | 1641:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3674 | 498 .loc 2 1641 3 view .LVU130 |
||
| 3675 | 1647:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3676 | 499 .loc 2 1647 5 view .LVU131 |
||
| 3677 | 1647:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3678 | 500 .loc 2 1647 46 is_stmt 0 view .LVU132 |
||
| 3679 | 501 000c 064A ldr r2, .L27+4 |
||
| 3680 | 502 000e F021 movs r1, #240 |
||
| 3681 | 503 0010 82F82310 strb r1, [r2, #35] |
||
| 3682 | 504 .LVL35: |
||
| 3683 | 1647:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3684 | 505 .loc 2 1647 46 view .LVU133 |
||
| 3685 | 506 .LBE79: |
||
| 3686 | 507 .LBE78: |
||
| 3687 | 1843:Drivers/CMSIS/Include/core_cm3.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val |
||
| 3688 | 508 .loc 2 1843 3 is_stmt 1 view .LVU134 |
||
| 3689 | 509 .loc 2 1843 18 is_stmt 0 view .LVU135 |
||
| 3690 | 510 0014 0020 movs r0, #0 |
||
| 3691 | 511 .LVL36: |
||
| 3692 | 512 .loc 2 1843 18 view .LVU136 |
||
| 3693 | 513 0016 9860 str r0, [r3, #8] |
||
| 3694 | 1844:Drivers/CMSIS/Include/core_cm3.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||
| 3695 | 514 .loc 2 1844 3 is_stmt 1 view .LVU137 |
||
| 3696 | 515 .loc 2 1844 18 is_stmt 0 view .LVU138 |
||
| 3697 | 516 0018 0722 movs r2, #7 |
||
| 3698 | 517 001a 1A60 str r2, [r3] |
||
| 3699 | 1845:Drivers/CMSIS/Include/core_cm3.h **** SysTick_CTRL_TICKINT_Msk | |
||
| 3700 | 1846:Drivers/CMSIS/Include/core_cm3.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi |
||
| 3701 | 1847:Drivers/CMSIS/Include/core_cm3.h **** return (0UL); /* Function successful */ |
||
| 3702 | 518 .loc 2 1847 3 is_stmt 1 view .LVU139 |
||
| 3703 | 519 001c 7047 bx lr |
||
| 3704 | 520 .L26: |
||
| 3705 | 1838:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3706 | 521 .loc 2 1838 12 is_stmt 0 view .LVU140 |
||
| 3707 | 522 001e 0120 movs r0, #1 |
||
| 3708 | 523 .LVL37: |
||
| 3709 | 1838:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3710 | 524 .loc 2 1838 12 view .LVU141 |
||
| 3711 | 525 .LBE77: |
||
| 3712 | 526 .LBE76: |
||
| 3713 | 232:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 3714 | 527 .loc 1 232 1 view .LVU142 |
||
| 3715 | 528 0020 7047 bx lr |
||
| 3716 | 529 .L28: |
||
| 3717 | 530 0022 00BF .align 2 |
||
| 3718 | 531 .L27: |
||
| 3719 | 532 0024 10E000E0 .word -536813552 |
||
| 3720 | 533 0028 00ED00E0 .word -536810240 |
||
| 20 | mjames | 3721 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 63 |
| 16 | mjames | 3722 | |
| 3723 | |||
| 3724 | 534 .cfi_endproc |
||
| 3725 | 535 .LFE70: |
||
| 3726 | 537 .section .text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits |
||
| 3727 | 538 .align 1 |
||
| 3728 | 539 .global HAL_NVIC_GetPriorityGrouping |
||
| 3729 | 540 .syntax unified |
||
| 3730 | 541 .thumb |
||
| 3731 | 542 .thumb_func |
||
| 3732 | 543 .fpu softvfp |
||
| 3733 | 545 HAL_NVIC_GetPriorityGrouping: |
||
| 3734 | 546 .LFB71: |
||
| 3735 | 233:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 3736 | 234:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @} |
||
| 3737 | 235:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 3738 | 236:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3739 | 237:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions |
||
| 3740 | 238:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Cortex control functions |
||
| 3741 | 239:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * |
||
| 3742 | 240:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @verbatim |
||
| 3743 | 241:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ============================================================================== |
||
| 3744 | 242:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ##### Peripheral Control functions ##### |
||
| 3745 | 243:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ============================================================================== |
||
| 3746 | 244:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** [..] |
||
| 3747 | 245:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX |
||
| 3748 | 246:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities. |
||
| 3749 | 247:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3750 | 248:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3751 | 249:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** @endverbatim |
||
| 3752 | 250:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @{ |
||
| 3753 | 251:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 3754 | 252:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3755 | 253:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** #if (__MPU_PRESENT == 1U) |
||
| 3756 | 254:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 3757 | 255:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Disables the MPU |
||
| 3758 | 256:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 3759 | 257:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 3760 | 258:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_MPU_Disable(void) |
||
| 3761 | 259:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 3762 | 260:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Make sure outstanding transfers are done */ |
||
| 3763 | 261:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** __DMB(); |
||
| 3764 | 262:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3765 | 263:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Disable fault exceptions */ |
||
| 3766 | 264:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
||
| 3767 | 265:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3768 | 266:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Disable the MPU and clear the control register*/ |
||
| 3769 | 267:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** MPU->CTRL = 0U; |
||
| 3770 | 268:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 3771 | 269:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3772 | 270:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 3773 | 271:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Enable the MPU. |
||
| 3774 | 272:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param MPU_Control: Specifies the control mode of the MPU during hard fault, |
||
| 3775 | 273:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * NMI, FAULTMASK and privileged access to the default memory |
||
| 3776 | 274:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be one of the following values: |
||
| 3777 | 275:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE |
||
| 3778 | 276:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI |
||
| 3779 | 277:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT |
||
| 3780 | 278:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF |
||
| 20 | mjames | 3781 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 64 |
| 16 | mjames | 3782 | |
| 3783 | |||
| 3784 | 279:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 3785 | 280:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 3786 | 281:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control) |
||
| 3787 | 282:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 3788 | 283:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Enable the MPU */ |
||
| 3789 | 284:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||
| 3790 | 285:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3791 | 286:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Enable fault exceptions */ |
||
| 3792 | 287:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
||
| 3793 | 288:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3794 | 289:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Ensure MPU setting take effects */ |
||
| 3795 | 290:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** __DSB(); |
||
| 3796 | 291:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** __ISB(); |
||
| 3797 | 292:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 3798 | 293:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3799 | 294:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 3800 | 295:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Initializes and configures the Region and the memory to be protected. |
||
| 3801 | 296:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains |
||
| 3802 | 297:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * the initialization and configuration information. |
||
| 3803 | 298:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 3804 | 299:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 3805 | 300:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) |
||
| 3806 | 301:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 3807 | 302:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 3808 | 303:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); |
||
| 3809 | 304:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); |
||
| 3810 | 305:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3811 | 306:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Set the Region number */ |
||
| 3812 | 307:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number; |
||
| 3813 | 308:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3814 | 309:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** if ((MPU_Init->Enable) != RESET) |
||
| 3815 | 310:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 3816 | 311:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 3817 | 312:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); |
||
| 3818 | 313:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); |
||
| 3819 | 314:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); |
||
| 3820 | 315:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); |
||
| 3821 | 316:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); |
||
| 3822 | 317:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); |
||
| 3823 | 318:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); |
||
| 3824 | 319:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); |
||
| 3825 | 320:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3826 | 321:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress; |
||
| 3827 | 322:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | |
||
| 3828 | 323:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | |
||
| 3829 | 324:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | |
||
| 3830 | 325:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | |
||
| 3831 | 326:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | |
||
| 3832 | 327:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | |
||
| 3833 | 328:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | |
||
| 3834 | 329:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | |
||
| 3835 | 330:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); |
||
| 3836 | 331:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 3837 | 332:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** else |
||
| 3838 | 333:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 3839 | 334:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** MPU->RBAR = 0x00U; |
||
| 3840 | 335:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** MPU->RASR = 0x00U; |
||
| 20 | mjames | 3841 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 65 |
| 16 | mjames | 3842 | |
| 3843 | |||
| 3844 | 336:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 3845 | 337:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 3846 | 338:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** #endif /* __MPU_PRESENT */ |
||
| 3847 | 339:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3848 | 340:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 3849 | 341:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. |
||
| 3850 | 342:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) |
||
| 3851 | 343:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 3852 | 344:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void) |
||
| 3853 | 345:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 3854 | 547 .loc 1 345 1 is_stmt 1 view -0 |
||
| 3855 | 548 .cfi_startproc |
||
| 3856 | 549 @ args = 0, pretend = 0, frame = 0 |
||
| 3857 | 550 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 3858 | 551 @ link register save eliminated. |
||
| 3859 | 346:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Get the PRIGROUP[10:8] field value */ |
||
| 3860 | 347:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** return NVIC_GetPriorityGrouping(); |
||
| 3861 | 552 .loc 1 347 3 view .LVU144 |
||
| 3862 | 553 .LBB80: |
||
| 3863 | 554 .LBI80: |
||
| 3864 | 1499:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3865 | 555 .loc 2 1499 26 view .LVU145 |
||
| 3866 | 556 .LBB81: |
||
| 3867 | 1501:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3868 | 557 .loc 2 1501 3 view .LVU146 |
||
| 3869 | 1501:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3870 | 558 .loc 2 1501 26 is_stmt 0 view .LVU147 |
||
| 3871 | 559 0000 024B ldr r3, .L30 |
||
| 3872 | 560 0002 D868 ldr r0, [r3, #12] |
||
| 3873 | 561 .LBE81: |
||
| 3874 | 562 .LBE80: |
||
| 3875 | 348:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 3876 | 563 .loc 1 348 1 view .LVU148 |
||
| 3877 | 564 0004 C0F30220 ubfx r0, r0, #8, #3 |
||
| 3878 | 565 0008 7047 bx lr |
||
| 3879 | 566 .L31: |
||
| 3880 | 567 000a 00BF .align 2 |
||
| 3881 | 568 .L30: |
||
| 3882 | 569 000c 00ED00E0 .word -536810240 |
||
| 3883 | 570 .cfi_endproc |
||
| 3884 | 571 .LFE71: |
||
| 3885 | 573 .section .text.HAL_NVIC_GetPriority,"ax",%progbits |
||
| 3886 | 574 .align 1 |
||
| 3887 | 575 .global HAL_NVIC_GetPriority |
||
| 3888 | 576 .syntax unified |
||
| 3889 | 577 .thumb |
||
| 3890 | 578 .thumb_func |
||
| 3891 | 579 .fpu softvfp |
||
| 3892 | 581 HAL_NVIC_GetPriority: |
||
| 3893 | 582 .LVL38: |
||
| 3894 | 583 .LFB72: |
||
| 3895 | 349:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 3896 | 350:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 3897 | 351:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Gets the priority of an interrupt. |
||
| 3898 | 352:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param IRQn: External interrupt number. |
||
| 3899 | 353:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration |
||
| 3900 | 354:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI |
||
| 20 | mjames | 3901 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 66 |
| 16 | mjames | 3902 | |
| 3903 | |||
| 3904 | 355:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param PriorityGroup: the priority grouping bits length. |
||
| 3905 | 356:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be one of the following values: |
||
| 3906 | 357:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
||
| 3907 | 358:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 4 bits for subpriority |
||
| 3908 | 359:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
||
| 3909 | 360:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 3 bits for subpriority |
||
| 3910 | 361:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
||
| 3911 | 362:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 2 bits for subpriority |
||
| 3912 | 363:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
||
| 3913 | 364:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 1 bits for subpriority |
||
| 3914 | 365:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
||
| 3915 | 366:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * 0 bits for subpriority |
||
| 3916 | 367:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). |
||
| 3917 | 368:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param pSubPriority: Pointer on the Subpriority value (starting from 0). |
||
| 3918 | 369:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 3919 | 370:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 3920 | 371:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3 |
||
| 3921 | 372:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 3922 | 584 .loc 1 372 1 is_stmt 1 view -0 |
||
| 3923 | 585 .cfi_startproc |
||
| 3924 | 586 @ args = 0, pretend = 0, frame = 0 |
||
| 3925 | 587 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 3926 | 588 @ link register save eliminated. |
||
| 3927 | 589 .loc 1 372 1 is_stmt 0 view .LVU150 |
||
| 3928 | 590 0000 70B4 push {r4, r5, r6} |
||
| 3929 | 591 .LCFI3: |
||
| 3930 | 592 .cfi_def_cfa_offset 12 |
||
| 3931 | 593 .cfi_offset 4, -12 |
||
| 3932 | 594 .cfi_offset 5, -8 |
||
| 3933 | 595 .cfi_offset 6, -4 |
||
| 3934 | 373:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 3935 | 374:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
||
| 3936 | 596 .loc 1 374 3 is_stmt 1 view .LVU151 |
||
| 3937 | 375:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ |
||
| 3938 | 376:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); |
||
| 3939 | 597 .loc 1 376 3 view .LVU152 |
||
| 3940 | 598 .LVL39: |
||
| 3941 | 599 .LBB82: |
||
| 3942 | 600 .LBI82: |
||
| 3943 | 1661:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3944 | 601 .loc 2 1661 26 view .LVU153 |
||
| 3945 | 602 .LBB83: |
||
| 3946 | 1664:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3947 | 603 .loc 2 1664 3 view .LVU154 |
||
| 3948 | 1664:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3949 | 604 .loc 2 1664 6 is_stmt 0 view .LVU155 |
||
| 3950 | 605 0002 0028 cmp r0, #0 |
||
| 3951 | 606 .LVL40: |
||
| 3952 | 1664:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3953 | 607 .loc 2 1664 6 view .LVU156 |
||
| 3954 | 608 0004 21DB blt .L33 |
||
| 3955 | 1666:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3956 | 609 .loc 2 1666 5 is_stmt 1 view .LVU157 |
||
| 3957 | 1666:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3958 | 610 .loc 2 1666 31 is_stmt 0 view .LVU158 |
||
| 3959 | 611 0006 00F16040 add r0, r0, #-536870912 |
||
| 3960 | 612 000a 00F56140 add r0, r0, #57600 |
||
| 20 | mjames | 3961 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 67 |
| 16 | mjames | 3962 | |
| 3963 | |||
| 3964 | 613 000e 90F80003 ldrb r0, [r0, #768] @ zero_extendqisi2 |
||
| 3965 | 1666:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3966 | 614 .loc 2 1666 64 view .LVU159 |
||
| 3967 | 615 0012 0009 lsrs r0, r0, #4 |
||
| 3968 | 616 .L34: |
||
| 3969 | 617 .LVL41: |
||
| 3970 | 1666:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 3971 | 618 .loc 2 1666 64 view .LVU160 |
||
| 3972 | 619 .LBE83: |
||
| 3973 | 620 .LBE82: |
||
| 3974 | 621 .LBB85: |
||
| 3975 | 622 .LBI85: |
||
| 3976 | 1713:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 3977 | 623 .loc 2 1713 22 is_stmt 1 view .LVU161 |
||
| 3978 | 624 .LBB86: |
||
| 3979 | 1715:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PreemptPriorityBits; |
||
| 3980 | 625 .loc 2 1715 3 view .LVU162 |
||
| 3981 | 1715:Drivers/CMSIS/Include/core_cm3.h **** uint32_t PreemptPriorityBits; |
||
| 3982 | 626 .loc 2 1715 12 is_stmt 0 view .LVU163 |
||
| 3983 | 627 0014 01F00701 and r1, r1, #7 |
||
| 3984 | 628 .LVL42: |
||
| 3985 | 1716:Drivers/CMSIS/Include/core_cm3.h **** uint32_t SubPriorityBits; |
||
| 3986 | 629 .loc 2 1716 3 is_stmt 1 view .LVU164 |
||
| 3987 | 1717:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 3988 | 630 .loc 2 1717 3 view .LVU165 |
||
| 3989 | 1719:Drivers/CMSIS/Include/core_cm3.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint |
||
| 3990 | 631 .loc 2 1719 3 view .LVU166 |
||
| 3991 | 1719:Drivers/CMSIS/Include/core_cm3.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint |
||
| 3992 | 632 .loc 2 1719 31 is_stmt 0 view .LVU167 |
||
| 3993 | 633 0018 C1F10704 rsb r4, r1, #7 |
||
| 3994 | 1719:Drivers/CMSIS/Include/core_cm3.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint |
||
| 3995 | 634 .loc 2 1719 23 view .LVU168 |
||
| 3996 | 635 001c 042C cmp r4, #4 |
||
| 3997 | 636 001e 28BF it cs |
||
| 3998 | 637 0020 0424 movcs r4, #4 |
||
| 3999 | 638 .LVL43: |
||
| 4000 | 1720:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 4001 | 639 .loc 2 1720 3 is_stmt 1 view .LVU169 |
||
| 4002 | 1720:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 4003 | 640 .loc 2 1720 44 is_stmt 0 view .LVU170 |
||
| 4004 | 641 0022 0D1D adds r5, r1, #4 |
||
| 4005 | 1720:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 4006 | 642 .loc 2 1720 109 view .LVU171 |
||
| 4007 | 643 0024 062D cmp r5, #6 |
||
| 4008 | 644 0026 16D9 bls .L36 |
||
| 4009 | 645 0028 0339 subs r1, r1, #3 |
||
| 4010 | 646 .LVL44: |
||
| 4011 | 647 .L35: |
||
| 4012 | 1722:Drivers/CMSIS/Include/core_cm3.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 |
||
| 4013 | 648 .loc 2 1722 3 is_stmt 1 view .LVU172 |
||
| 4014 | 1722:Drivers/CMSIS/Include/core_cm3.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 |
||
| 4015 | 649 .loc 2 1722 33 is_stmt 0 view .LVU173 |
||
| 4016 | 650 002a 20FA01F6 lsr r6, r0, r1 |
||
| 4017 | 1722:Drivers/CMSIS/Include/core_cm3.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 |
||
| 4018 | 651 .loc 2 1722 53 view .LVU174 |
||
| 4019 | 652 002e 4FF0FF35 mov r5, #-1 |
||
| 4020 | 653 .LVL45: |
||
| 20 | mjames | 4021 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 68 |
| 16 | mjames | 4022 | |
| 4023 | |||
| 4024 | 1722:Drivers/CMSIS/Include/core_cm3.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 |
||
| 4025 | 654 .loc 2 1722 53 view .LVU175 |
||
| 4026 | 655 0032 05FA04F4 lsl r4, r5, r4 |
||
| 4027 | 656 .LVL46: |
||
| 4028 | 1722:Drivers/CMSIS/Include/core_cm3.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 |
||
| 4029 | 657 .loc 2 1722 53 view .LVU176 |
||
| 4030 | 658 0036 26EA0404 bic r4, r6, r4 |
||
| 4031 | 1722:Drivers/CMSIS/Include/core_cm3.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 |
||
| 4032 | 659 .loc 2 1722 21 view .LVU177 |
||
| 4033 | 660 003a 1460 str r4, [r2] |
||
| 4034 | 1723:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4035 | 661 .loc 2 1723 3 is_stmt 1 view .LVU178 |
||
| 4036 | 1723:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4037 | 662 .loc 2 1723 53 is_stmt 0 view .LVU179 |
||
| 4038 | 663 003c 05FA01F1 lsl r1, r5, r1 |
||
| 4039 | 664 .LVL47: |
||
| 4040 | 1723:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4041 | 665 .loc 2 1723 53 view .LVU180 |
||
| 4042 | 666 0040 20EA0100 bic r0, r0, r1 |
||
| 4043 | 667 .LVL48: |
||
| 4044 | 1723:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4045 | 668 .loc 2 1723 21 view .LVU181 |
||
| 4046 | 669 0044 1860 str r0, [r3] |
||
| 4047 | 670 .LVL49: |
||
| 4048 | 1723:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4049 | 671 .loc 2 1723 21 view .LVU182 |
||
| 4050 | 672 .LBE86: |
||
| 4051 | 673 .LBE85: |
||
| 4052 | 377:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4053 | 674 .loc 1 377 1 view .LVU183 |
||
| 4054 | 675 0046 70BC pop {r4, r5, r6} |
||
| 4055 | 676 .LCFI4: |
||
| 4056 | 677 .cfi_remember_state |
||
| 4057 | 678 .cfi_restore 6 |
||
| 4058 | 679 .cfi_restore 5 |
||
| 4059 | 680 .cfi_restore 4 |
||
| 4060 | 681 .cfi_def_cfa_offset 0 |
||
| 4061 | 682 0048 7047 bx lr |
||
| 4062 | 683 .LVL50: |
||
| 4063 | 684 .L33: |
||
| 4064 | 685 .LCFI5: |
||
| 4065 | 686 .cfi_restore_state |
||
| 4066 | 687 .LBB88: |
||
| 4067 | 688 .LBB84: |
||
| 4068 | 1670:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4069 | 689 .loc 2 1670 5 is_stmt 1 view .LVU184 |
||
| 4070 | 1670:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4071 | 690 .loc 2 1670 50 is_stmt 0 view .LVU185 |
||
| 4072 | 691 004a 00F00F00 and r0, r0, #15 |
||
| 4073 | 1670:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4074 | 692 .loc 2 1670 31 view .LVU186 |
||
| 4075 | 693 004e 034C ldr r4, .L38 |
||
| 4076 | 694 0050 205C ldrb r0, [r4, r0] @ zero_extendqisi2 |
||
| 4077 | 1670:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4078 | 695 .loc 2 1670 64 view .LVU187 |
||
| 4079 | 696 0052 0009 lsrs r0, r0, #4 |
||
| 4080 | 697 0054 DEE7 b .L34 |
||
| 20 | mjames | 4081 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 69 |
| 16 | mjames | 4082 | |
| 4083 | |||
| 4084 | 698 .LVL51: |
||
| 4085 | 699 .L36: |
||
| 4086 | 1670:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4087 | 700 .loc 2 1670 64 view .LVU188 |
||
| 4088 | 701 .LBE84: |
||
| 4089 | 702 .LBE88: |
||
| 4090 | 703 .LBB89: |
||
| 4091 | 704 .LBB87: |
||
| 4092 | 1720:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 4093 | 705 .loc 2 1720 109 view .LVU189 |
||
| 4094 | 706 0056 0021 movs r1, #0 |
||
| 4095 | 707 .LVL52: |
||
| 4096 | 1720:Drivers/CMSIS/Include/core_cm3.h **** |
||
| 4097 | 708 .loc 2 1720 109 view .LVU190 |
||
| 4098 | 709 0058 E7E7 b .L35 |
||
| 4099 | 710 .L39: |
||
| 4100 | 711 005a 00BF .align 2 |
||
| 4101 | 712 .L38: |
||
| 4102 | 713 005c 14ED00E0 .word -536810220 |
||
| 4103 | 714 .LBE87: |
||
| 4104 | 715 .LBE89: |
||
| 4105 | 716 .cfi_endproc |
||
| 4106 | 717 .LFE72: |
||
| 4107 | 719 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits |
||
| 4108 | 720 .align 1 |
||
| 4109 | 721 .global HAL_NVIC_SetPendingIRQ |
||
| 4110 | 722 .syntax unified |
||
| 4111 | 723 .thumb |
||
| 4112 | 724 .thumb_func |
||
| 4113 | 725 .fpu softvfp |
||
| 4114 | 727 HAL_NVIC_SetPendingIRQ: |
||
| 4115 | 728 .LVL53: |
||
| 4116 | 729 .LFB73: |
||
| 4117 | 378:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4118 | 379:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 4119 | 380:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt. |
||
| 4120 | 381:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param IRQn External interrupt number |
||
| 4121 | 382:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration |
||
| 4122 | 383:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI |
||
| 4123 | 384:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 4124 | 385:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 4125 | 386:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||
| 4126 | 387:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 4127 | 730 .loc 1 387 1 is_stmt 1 view -0 |
||
| 4128 | 731 .cfi_startproc |
||
| 4129 | 732 @ args = 0, pretend = 0, frame = 0 |
||
| 4130 | 733 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 4131 | 734 @ link register save eliminated. |
||
| 4132 | 388:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 4133 | 389:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||
| 4134 | 735 .loc 1 389 3 view .LVU192 |
||
| 4135 | 390:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4136 | 391:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Set interrupt pending */ |
||
| 4137 | 392:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); |
||
| 4138 | 736 .loc 1 392 3 view .LVU193 |
||
| 4139 | 737 .LBB90: |
||
| 4140 | 738 .LBI90: |
||
| 20 | mjames | 4141 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 70 |
| 16 | mjames | 4142 | |
| 4143 | |||
| 4144 | 1585:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4145 | 739 .loc 2 1585 22 view .LVU194 |
||
| 4146 | 740 .LBB91: |
||
| 4147 | 1587:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4148 | 741 .loc 2 1587 3 view .LVU195 |
||
| 4149 | 1587:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4150 | 742 .loc 2 1587 6 is_stmt 0 view .LVU196 |
||
| 4151 | 743 0000 0028 cmp r0, #0 |
||
| 4152 | 744 .LVL54: |
||
| 4153 | 1587:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4154 | 745 .loc 2 1587 6 view .LVU197 |
||
| 4155 | 746 0002 08DB blt .L40 |
||
| 4156 | 1589:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4157 | 747 .loc 2 1589 5 is_stmt 1 view .LVU198 |
||
| 4158 | 1589:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4159 | 748 .loc 2 1589 81 is_stmt 0 view .LVU199 |
||
| 4160 | 749 0004 00F01F02 and r2, r0, #31 |
||
| 4161 | 1589:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4162 | 750 .loc 2 1589 34 view .LVU200 |
||
| 4163 | 751 0008 4009 lsrs r0, r0, #5 |
||
| 4164 | 1589:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4165 | 752 .loc 2 1589 45 view .LVU201 |
||
| 4166 | 753 000a 0123 movs r3, #1 |
||
| 4167 | 754 000c 9340 lsls r3, r3, r2 |
||
| 4168 | 1589:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4169 | 755 .loc 2 1589 43 view .LVU202 |
||
| 4170 | 756 000e 4030 adds r0, r0, #64 |
||
| 4171 | 757 0010 014A ldr r2, .L42 |
||
| 4172 | 758 0012 42F82030 str r3, [r2, r0, lsl #2] |
||
| 4173 | 759 .LVL55: |
||
| 4174 | 760 .L40: |
||
| 4175 | 1589:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4176 | 761 .loc 2 1589 43 view .LVU203 |
||
| 4177 | 762 .LBE91: |
||
| 4178 | 763 .LBE90: |
||
| 4179 | 393:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4180 | 764 .loc 1 393 1 view .LVU204 |
||
| 4181 | 765 0016 7047 bx lr |
||
| 4182 | 766 .L43: |
||
| 4183 | 767 .align 2 |
||
| 4184 | 768 .L42: |
||
| 4185 | 769 0018 00E100E0 .word -536813312 |
||
| 4186 | 770 .cfi_endproc |
||
| 4187 | 771 .LFE73: |
||
| 4188 | 773 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits |
||
| 4189 | 774 .align 1 |
||
| 4190 | 775 .global HAL_NVIC_GetPendingIRQ |
||
| 4191 | 776 .syntax unified |
||
| 4192 | 777 .thumb |
||
| 4193 | 778 .thumb_func |
||
| 4194 | 779 .fpu softvfp |
||
| 4195 | 781 HAL_NVIC_GetPendingIRQ: |
||
| 4196 | 782 .LVL56: |
||
| 4197 | 783 .LFB74: |
||
| 4198 | 394:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4199 | 395:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 4200 | 396:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC |
||
| 20 | mjames | 4201 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 71 |
| 16 | mjames | 4202 | |
| 4203 | |||
| 4204 | 397:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt). |
||
| 4205 | 398:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param IRQn External interrupt number. |
||
| 4206 | 399:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration |
||
| 4207 | 400:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI |
||
| 4208 | 401:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. |
||
| 4209 | 402:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * - 1 Interrupt status is pending. |
||
| 4210 | 403:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 4211 | 404:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||
| 4212 | 405:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 4213 | 784 .loc 1 405 1 is_stmt 1 view -0 |
||
| 4214 | 785 .cfi_startproc |
||
| 4215 | 786 @ args = 0, pretend = 0, frame = 0 |
||
| 4216 | 787 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 4217 | 788 @ link register save eliminated. |
||
| 4218 | 406:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 4219 | 407:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||
| 4220 | 789 .loc 1 407 3 view .LVU206 |
||
| 4221 | 408:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4222 | 409:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Return 1 if pending else 0 */ |
||
| 4223 | 410:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); |
||
| 4224 | 790 .loc 1 410 3 view .LVU207 |
||
| 4225 | 791 .LBB92: |
||
| 4226 | 792 .LBI92: |
||
| 4227 | 1566:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4228 | 793 .loc 2 1566 26 view .LVU208 |
||
| 4229 | 794 .LBB93: |
||
| 4230 | 1568:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4231 | 795 .loc 2 1568 3 view .LVU209 |
||
| 4232 | 1568:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4233 | 796 .loc 2 1568 6 is_stmt 0 view .LVU210 |
||
| 4234 | 797 0000 0028 cmp r0, #0 |
||
| 4235 | 798 .LVL57: |
||
| 4236 | 1568:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4237 | 799 .loc 2 1568 6 view .LVU211 |
||
| 4238 | 800 0002 0BDB blt .L46 |
||
| 4239 | 1570:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4240 | 801 .loc 2 1570 5 is_stmt 1 view .LVU212 |
||
| 4241 | 1570:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4242 | 802 .loc 2 1570 54 is_stmt 0 view .LVU213 |
||
| 4243 | 803 0004 4309 lsrs r3, r0, #5 |
||
| 4244 | 1570:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4245 | 804 .loc 2 1570 35 view .LVU214 |
||
| 4246 | 805 0006 4033 adds r3, r3, #64 |
||
| 4247 | 806 0008 054A ldr r2, .L47 |
||
| 4248 | 807 000a 52F82330 ldr r3, [r2, r3, lsl #2] |
||
| 4249 | 1570:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4250 | 808 .loc 2 1570 91 view .LVU215 |
||
| 4251 | 809 000e 00F01F00 and r0, r0, #31 |
||
| 4252 | 1570:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4253 | 810 .loc 2 1570 103 view .LVU216 |
||
| 4254 | 811 0012 23FA00F0 lsr r0, r3, r0 |
||
| 4255 | 1570:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4256 | 812 .loc 2 1570 12 view .LVU217 |
||
| 4257 | 813 0016 00F00100 and r0, r0, #1 |
||
| 4258 | 814 001a 7047 bx lr |
||
| 4259 | 815 .L46: |
||
| 4260 | 1574:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 20 | mjames | 4261 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 72 |
| 16 | mjames | 4262 | |
| 4263 | |||
| 4264 | 816 .loc 2 1574 11 view .LVU218 |
||
| 4265 | 817 001c 0020 movs r0, #0 |
||
| 4266 | 818 .LVL58: |
||
| 4267 | 1574:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4268 | 819 .loc 2 1574 11 view .LVU219 |
||
| 4269 | 820 .LBE93: |
||
| 4270 | 821 .LBE92: |
||
| 4271 | 411:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4272 | 822 .loc 1 411 1 view .LVU220 |
||
| 4273 | 823 001e 7047 bx lr |
||
| 4274 | 824 .L48: |
||
| 4275 | 825 .align 2 |
||
| 4276 | 826 .L47: |
||
| 4277 | 827 0020 00E100E0 .word -536813312 |
||
| 4278 | 828 .cfi_endproc |
||
| 4279 | 829 .LFE74: |
||
| 4280 | 831 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits |
||
| 4281 | 832 .align 1 |
||
| 4282 | 833 .global HAL_NVIC_ClearPendingIRQ |
||
| 4283 | 834 .syntax unified |
||
| 4284 | 835 .thumb |
||
| 4285 | 836 .thumb_func |
||
| 4286 | 837 .fpu softvfp |
||
| 4287 | 839 HAL_NVIC_ClearPendingIRQ: |
||
| 4288 | 840 .LVL59: |
||
| 4289 | 841 .LFB75: |
||
| 4290 | 412:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4291 | 413:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 4292 | 414:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt. |
||
| 4293 | 415:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param IRQn External interrupt number. |
||
| 4294 | 416:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration |
||
| 4295 | 417:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI |
||
| 4296 | 418:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 4297 | 419:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 4298 | 420:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||
| 4299 | 421:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 4300 | 842 .loc 1 421 1 is_stmt 1 view -0 |
||
| 4301 | 843 .cfi_startproc |
||
| 4302 | 844 @ args = 0, pretend = 0, frame = 0 |
||
| 4303 | 845 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 4304 | 846 @ link register save eliminated. |
||
| 4305 | 422:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 4306 | 423:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||
| 4307 | 847 .loc 1 423 3 view .LVU222 |
||
| 4308 | 424:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4309 | 425:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Clear pending interrupt */ |
||
| 4310 | 426:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); |
||
| 4311 | 848 .loc 1 426 3 view .LVU223 |
||
| 4312 | 849 .LBB94: |
||
| 4313 | 850 .LBI94: |
||
| 4314 | 1600:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4315 | 851 .loc 2 1600 22 view .LVU224 |
||
| 4316 | 852 .LBB95: |
||
| 4317 | 1602:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4318 | 853 .loc 2 1602 3 view .LVU225 |
||
| 4319 | 1602:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4320 | 854 .loc 2 1602 6 is_stmt 0 view .LVU226 |
||
| 20 | mjames | 4321 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 73 |
| 16 | mjames | 4322 | |
| 4323 | |||
| 4324 | 855 0000 0028 cmp r0, #0 |
||
| 4325 | 856 .LVL60: |
||
| 4326 | 1602:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4327 | 857 .loc 2 1602 6 view .LVU227 |
||
| 4328 | 858 0002 08DB blt .L49 |
||
| 4329 | 1604:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4330 | 859 .loc 2 1604 5 is_stmt 1 view .LVU228 |
||
| 4331 | 1604:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4332 | 860 .loc 2 1604 81 is_stmt 0 view .LVU229 |
||
| 4333 | 861 0004 00F01F02 and r2, r0, #31 |
||
| 4334 | 1604:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4335 | 862 .loc 2 1604 34 view .LVU230 |
||
| 4336 | 863 0008 4009 lsrs r0, r0, #5 |
||
| 4337 | 1604:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4338 | 864 .loc 2 1604 45 view .LVU231 |
||
| 4339 | 865 000a 0123 movs r3, #1 |
||
| 4340 | 866 000c 9340 lsls r3, r3, r2 |
||
| 4341 | 1604:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4342 | 867 .loc 2 1604 43 view .LVU232 |
||
| 4343 | 868 000e 6030 adds r0, r0, #96 |
||
| 4344 | 869 0010 014A ldr r2, .L51 |
||
| 4345 | 870 0012 42F82030 str r3, [r2, r0, lsl #2] |
||
| 4346 | 871 .LVL61: |
||
| 4347 | 872 .L49: |
||
| 4348 | 1604:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4349 | 873 .loc 2 1604 43 view .LVU233 |
||
| 4350 | 874 .LBE95: |
||
| 4351 | 875 .LBE94: |
||
| 4352 | 427:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4353 | 876 .loc 1 427 1 view .LVU234 |
||
| 4354 | 877 0016 7047 bx lr |
||
| 4355 | 878 .L52: |
||
| 4356 | 879 .align 2 |
||
| 4357 | 880 .L51: |
||
| 4358 | 881 0018 00E100E0 .word -536813312 |
||
| 4359 | 882 .cfi_endproc |
||
| 4360 | 883 .LFE75: |
||
| 4361 | 885 .section .text.HAL_NVIC_GetActive,"ax",%progbits |
||
| 4362 | 886 .align 1 |
||
| 4363 | 887 .global HAL_NVIC_GetActive |
||
| 4364 | 888 .syntax unified |
||
| 4365 | 889 .thumb |
||
| 4366 | 890 .thumb_func |
||
| 4367 | 891 .fpu softvfp |
||
| 4368 | 893 HAL_NVIC_GetActive: |
||
| 4369 | 894 .LVL62: |
||
| 4370 | 895 .LFB76: |
||
| 4371 | 428:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4372 | 429:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 4373 | 430:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). |
||
| 4374 | 431:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param IRQn External interrupt number |
||
| 4375 | 432:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration |
||
| 4376 | 433:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI |
||
| 4377 | 434:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. |
||
| 4378 | 435:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * - 1 Interrupt status is pending. |
||
| 4379 | 436:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 4380 | 437:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) |
||
| 20 | mjames | 4381 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 74 |
| 16 | mjames | 4382 | |
| 4383 | |||
| 4384 | 438:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 4385 | 896 .loc 1 438 1 is_stmt 1 view -0 |
||
| 4386 | 897 .cfi_startproc |
||
| 4387 | 898 @ args = 0, pretend = 0, frame = 0 |
||
| 4388 | 899 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 4389 | 900 @ link register save eliminated. |
||
| 4390 | 439:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 4391 | 440:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||
| 4392 | 901 .loc 1 440 3 view .LVU236 |
||
| 4393 | 441:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4394 | 442:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Return 1 if active else 0 */ |
||
| 4395 | 443:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** return NVIC_GetActive(IRQn); |
||
| 4396 | 902 .loc 1 443 3 view .LVU237 |
||
| 4397 | 903 .LBB96: |
||
| 4398 | 904 .LBI96: |
||
| 4399 | 1617:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4400 | 905 .loc 2 1617 26 view .LVU238 |
||
| 4401 | 906 .LBB97: |
||
| 4402 | 1619:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4403 | 907 .loc 2 1619 3 view .LVU239 |
||
| 4404 | 1619:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4405 | 908 .loc 2 1619 6 is_stmt 0 view .LVU240 |
||
| 4406 | 909 0000 0028 cmp r0, #0 |
||
| 4407 | 910 .LVL63: |
||
| 4408 | 1619:Drivers/CMSIS/Include/core_cm3.h **** { |
||
| 4409 | 911 .loc 2 1619 6 view .LVU241 |
||
| 4410 | 912 0002 0BDB blt .L55 |
||
| 4411 | 1621:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4412 | 913 .loc 2 1621 5 is_stmt 1 view .LVU242 |
||
| 4413 | 1621:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4414 | 914 .loc 2 1621 54 is_stmt 0 view .LVU243 |
||
| 4415 | 915 0004 4309 lsrs r3, r0, #5 |
||
| 4416 | 1621:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4417 | 916 .loc 2 1621 35 view .LVU244 |
||
| 4418 | 917 0006 8033 adds r3, r3, #128 |
||
| 4419 | 918 0008 054A ldr r2, .L56 |
||
| 4420 | 919 000a 52F82330 ldr r3, [r2, r3, lsl #2] |
||
| 4421 | 1621:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4422 | 920 .loc 2 1621 91 view .LVU245 |
||
| 4423 | 921 000e 00F01F00 and r0, r0, #31 |
||
| 4424 | 1621:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4425 | 922 .loc 2 1621 103 view .LVU246 |
||
| 4426 | 923 0012 23FA00F0 lsr r0, r3, r0 |
||
| 4427 | 1621:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4428 | 924 .loc 2 1621 12 view .LVU247 |
||
| 4429 | 925 0016 00F00100 and r0, r0, #1 |
||
| 4430 | 926 001a 7047 bx lr |
||
| 4431 | 927 .L55: |
||
| 4432 | 1625:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4433 | 928 .loc 2 1625 11 view .LVU248 |
||
| 4434 | 929 001c 0020 movs r0, #0 |
||
| 4435 | 930 .LVL64: |
||
| 4436 | 1625:Drivers/CMSIS/Include/core_cm3.h **** } |
||
| 4437 | 931 .loc 2 1625 11 view .LVU249 |
||
| 4438 | 932 .LBE97: |
||
| 4439 | 933 .LBE96: |
||
| 4440 | 444:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 20 | mjames | 4441 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 75 |
| 16 | mjames | 4442 | |
| 4443 | |||
| 4444 | 934 .loc 1 444 1 view .LVU250 |
||
| 4445 | 935 001e 7047 bx lr |
||
| 4446 | 936 .L57: |
||
| 4447 | 937 .align 2 |
||
| 4448 | 938 .L56: |
||
| 4449 | 939 0020 00E100E0 .word -536813312 |
||
| 4450 | 940 .cfi_endproc |
||
| 4451 | 941 .LFE76: |
||
| 4452 | 943 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits |
||
| 4453 | 944 .align 1 |
||
| 4454 | 945 .global HAL_SYSTICK_CLKSourceConfig |
||
| 4455 | 946 .syntax unified |
||
| 4456 | 947 .thumb |
||
| 4457 | 948 .thumb_func |
||
| 4458 | 949 .fpu softvfp |
||
| 4459 | 951 HAL_SYSTICK_CLKSourceConfig: |
||
| 4460 | 952 .LVL65: |
||
| 4461 | 953 .LFB77: |
||
| 4462 | 445:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4463 | 446:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 4464 | 447:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief Configures the SysTick clock source. |
||
| 4465 | 448:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @param CLKSource: specifies the SysTick clock source. |
||
| 4466 | 449:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * This parameter can be one of the following values: |
||
| 4467 | 450:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock |
||
| 4468 | 451:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. |
||
| 4469 | 452:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 4470 | 453:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 4471 | 454:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) |
||
| 4472 | 455:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 4473 | 954 .loc 1 455 1 is_stmt 1 view -0 |
||
| 4474 | 955 .cfi_startproc |
||
| 4475 | 956 @ args = 0, pretend = 0, frame = 0 |
||
| 4476 | 957 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 4477 | 958 @ link register save eliminated. |
||
| 4478 | 456:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* Check the parameters */ |
||
| 4479 | 457:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); |
||
| 4480 | 959 .loc 1 457 3 view .LVU252 |
||
| 4481 | 458:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) |
||
| 4482 | 960 .loc 1 458 3 view .LVU253 |
||
| 4483 | 961 .loc 1 458 6 is_stmt 0 view .LVU254 |
||
| 4484 | 962 0000 0428 cmp r0, #4 |
||
| 4485 | 963 0002 05D0 beq .L61 |
||
| 4486 | 459:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 4487 | 460:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; |
||
| 4488 | 461:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4489 | 462:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** else |
||
| 4490 | 463:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 4491 | 464:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; |
||
| 4492 | 964 .loc 1 464 5 is_stmt 1 view .LVU255 |
||
| 4493 | 965 .loc 1 464 19 is_stmt 0 view .LVU256 |
||
| 4494 | 966 0004 054A ldr r2, .L62 |
||
| 4495 | 967 0006 1368 ldr r3, [r2] |
||
| 4496 | 968 0008 23F00403 bic r3, r3, #4 |
||
| 4497 | 969 000c 1360 str r3, [r2] |
||
| 4498 | 465:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4499 | 466:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4500 | 970 .loc 1 466 1 view .LVU257 |
||
| 20 | mjames | 4501 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 76 |
| 16 | mjames | 4502 | |
| 4503 | |||
| 4504 | 971 000e 7047 bx lr |
||
| 4505 | 972 .L61: |
||
| 4506 | 460:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4507 | 973 .loc 1 460 5 is_stmt 1 view .LVU258 |
||
| 4508 | 460:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4509 | 974 .loc 1 460 19 is_stmt 0 view .LVU259 |
||
| 4510 | 975 0010 024A ldr r2, .L62 |
||
| 4511 | 976 0012 1368 ldr r3, [r2] |
||
| 4512 | 977 0014 43F00403 orr r3, r3, #4 |
||
| 4513 | 978 0018 1360 str r3, [r2] |
||
| 4514 | 979 001a 7047 bx lr |
||
| 4515 | 980 .L63: |
||
| 4516 | 981 .align 2 |
||
| 4517 | 982 .L62: |
||
| 4518 | 983 001c 10E000E0 .word -536813552 |
||
| 4519 | 984 .cfi_endproc |
||
| 4520 | 985 .LFE77: |
||
| 4521 | 987 .section .text.HAL_SYSTICK_Callback,"ax",%progbits |
||
| 4522 | 988 .align 1 |
||
| 4523 | 989 .weak HAL_SYSTICK_Callback |
||
| 4524 | 990 .syntax unified |
||
| 4525 | 991 .thumb |
||
| 4526 | 992 .thumb_func |
||
| 4527 | 993 .fpu softvfp |
||
| 4528 | 995 HAL_SYSTICK_Callback: |
||
| 4529 | 996 .LFB79: |
||
| 4530 | 467:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4531 | 468:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 4532 | 469:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request. |
||
| 4533 | 470:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 4534 | 471:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 4535 | 472:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) |
||
| 4536 | 473:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 4537 | 474:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** HAL_SYSTICK_Callback(); |
||
| 4538 | 475:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4539 | 476:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4540 | 477:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /** |
||
| 4541 | 478:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @brief SYSTICK callback. |
||
| 4542 | 479:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** * @retval None |
||
| 4543 | 480:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 4544 | 481:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) |
||
| 4545 | 482:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** { |
||
| 4546 | 997 .loc 1 482 1 is_stmt 1 view -0 |
||
| 4547 | 998 .cfi_startproc |
||
| 4548 | 999 @ args = 0, pretend = 0, frame = 0 |
||
| 4549 | 1000 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 4550 | 1001 @ link register save eliminated. |
||
| 4551 | 483:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed, |
||
| 4552 | 484:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file |
||
| 4553 | 485:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** */ |
||
| 4554 | 486:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4555 | 1002 .loc 1 486 1 view .LVU261 |
||
| 4556 | 1003 0000 7047 bx lr |
||
| 4557 | 1004 .cfi_endproc |
||
| 4558 | 1005 .LFE79: |
||
| 4559 | 1007 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits |
||
| 4560 | 1008 .align 1 |
||
| 20 | mjames | 4561 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 77 |
| 16 | mjames | 4562 | |
| 4563 | |||
| 4564 | 1009 .global HAL_SYSTICK_IRQHandler |
||
| 4565 | 1010 .syntax unified |
||
| 4566 | 1011 .thumb |
||
| 4567 | 1012 .thumb_func |
||
| 4568 | 1013 .fpu softvfp |
||
| 4569 | 1015 HAL_SYSTICK_IRQHandler: |
||
| 4570 | 1016 .LFB78: |
||
| 4571 | 473:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** HAL_SYSTICK_Callback(); |
||
| 4572 | 1017 .loc 1 473 1 view -0 |
||
| 4573 | 1018 .cfi_startproc |
||
| 4574 | 1019 @ args = 0, pretend = 0, frame = 0 |
||
| 4575 | 1020 @ frame_needed = 0, uses_anonymous_args = 0 |
||
| 4576 | 1021 0000 08B5 push {r3, lr} |
||
| 4577 | 1022 .LCFI6: |
||
| 4578 | 1023 .cfi_def_cfa_offset 8 |
||
| 4579 | 1024 .cfi_offset 3, -8 |
||
| 4580 | 1025 .cfi_offset 14, -4 |
||
| 4581 | 474:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** } |
||
| 4582 | 1026 .loc 1 474 3 view .LVU263 |
||
| 4583 | 1027 0002 FFF7FEFF bl HAL_SYSTICK_Callback |
||
| 4584 | 1028 .LVL66: |
||
| 4585 | 475:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c **** |
||
| 4586 | 1029 .loc 1 475 1 is_stmt 0 view .LVU264 |
||
| 4587 | 1030 0006 08BD pop {r3, pc} |
||
| 4588 | 1031 .cfi_endproc |
||
| 4589 | 1032 .LFE78: |
||
| 4590 | 1034 .text |
||
| 4591 | 1035 .Letext0: |
||
| 4592 | 1036 .file 4 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h" |
||
| 4593 | 1037 .file 5 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7 |
||
| 4594 | 1038 .file 6 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7 |
||
| 4595 | 1039 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" |
||
| 4596 | 1040 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h" |
||
| 20 | mjames | 4597 | ARM GAS C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s page 78 |
| 16 | mjames | 4598 | |
| 4599 | |||
| 4600 | DEFINED SYMBOLS |
||
| 4601 | *ABS*:0000000000000000 stm32f1xx_hal_cortex.c |
||
| 20 | mjames | 4602 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:16 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 $t |
| 4603 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:24 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 HAL_NVIC_SetPriorityGrouping |
||
| 4604 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:79 .text.HAL_NVIC_SetPriorityGrouping:0000000000000020 $d |
||
| 4605 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:84 .text.HAL_NVIC_SetPriority:0000000000000000 $t |
||
| 4606 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:91 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority |
||
| 4607 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:239 .text.HAL_NVIC_SetPriority:0000000000000060 $d |
||
| 4608 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:245 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t |
||
| 4609 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:252 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ |
||
| 4610 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:293 .text.HAL_NVIC_EnableIRQ:0000000000000018 $d |
||
| 4611 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:298 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t |
||
| 4612 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:305 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ |
||
| 4613 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:376 .text.HAL_NVIC_DisableIRQ:0000000000000020 $d |
||
| 4614 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:381 .text.HAL_NVIC_SystemReset:0000000000000000 $t |
||
| 4615 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:388 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset |
||
| 4616 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:453 .text.HAL_NVIC_SystemReset:000000000000001c $d |
||
| 4617 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:461 .text.HAL_SYSTICK_Config:0000000000000000 $t |
||
| 4618 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:468 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config |
||
| 4619 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:532 .text.HAL_SYSTICK_Config:0000000000000024 $d |
||
| 4620 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:538 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 $t |
||
| 4621 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:545 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 HAL_NVIC_GetPriorityGrouping |
||
| 4622 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:569 .text.HAL_NVIC_GetPriorityGrouping:000000000000000c $d |
||
| 4623 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:574 .text.HAL_NVIC_GetPriority:0000000000000000 $t |
||
| 4624 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:581 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority |
||
| 4625 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:713 .text.HAL_NVIC_GetPriority:000000000000005c $d |
||
| 4626 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:720 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t |
||
| 4627 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:727 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ |
||
| 4628 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:769 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d |
||
| 4629 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:774 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t |
||
| 4630 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:781 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ |
||
| 4631 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:827 .text.HAL_NVIC_GetPendingIRQ:0000000000000020 $d |
||
| 4632 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:832 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t |
||
| 4633 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:839 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ |
||
| 4634 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:881 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d |
||
| 4635 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:886 .text.HAL_NVIC_GetActive:0000000000000000 $t |
||
| 4636 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:893 .text.HAL_NVIC_GetActive:0000000000000000 HAL_NVIC_GetActive |
||
| 4637 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:939 .text.HAL_NVIC_GetActive:0000000000000020 $d |
||
| 4638 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:944 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t |
||
| 4639 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:951 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig |
||
| 4640 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:983 .text.HAL_SYSTICK_CLKSourceConfig:000000000000001c $d |
||
| 4641 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:988 .text.HAL_SYSTICK_Callback:0000000000000000 $t |
||
| 4642 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:995 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback |
||
| 4643 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:1008 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t |
||
| 4644 | C:\Users\mike\AppData\Local\Temp\cc4oRr9x.s:1015 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler |
||
| 16 | mjames | 4645 | |
| 4646 | NO UNDEFINED SYMBOLS |