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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_adc.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief ADC LL module driver |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | #if defined(USE_FULL_LL_DRIVER) |
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| 21 | |||
| 22 | /* Includes ------------------------------------------------------------------*/ |
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| 23 | #include "stm32f1xx_ll_adc.h" |
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| 24 | #include "stm32f1xx_ll_bus.h" |
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| 25 | |||
| 26 | #ifdef USE_FULL_ASSERT |
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| 27 | #include "stm32_assert.h" |
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| 28 | #else |
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| 29 | #define assert_param(expr) ((void)0U) |
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| 30 | #endif |
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| 31 | |||
| 32 | /** @addtogroup STM32F1xx_LL_Driver |
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| 33 | * @{ |
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| 34 | */ |
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| 35 | |||
| 36 | #if defined (ADC1) || defined (ADC2) || defined (ADC3) |
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| 37 | |||
| 38 | /** @addtogroup ADC_LL ADC |
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| 39 | * @{ |
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| 40 | */ |
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| 41 | |||
| 42 | /* Private types -------------------------------------------------------------*/ |
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| 43 | /* Private variables ---------------------------------------------------------*/ |
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| 44 | /* Private constants ---------------------------------------------------------*/ |
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| 45 | /* Private macros ------------------------------------------------------------*/ |
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| 46 | |||
| 47 | /** @addtogroup ADC_LL_Private_Macros |
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| 48 | * @{ |
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| 49 | */ |
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| 50 | |||
| 51 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 52 | /* common to several ADC instances. */ |
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| 53 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 54 | /* ADC instance. */ |
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| 55 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
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| 56 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
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| 57 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
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| 58 | ) |
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| 59 | |||
| 60 | #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
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| 61 | ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
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| 62 | || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
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| 63 | ) |
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| 64 | |||
| 65 | #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
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| 66 | ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
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| 67 | || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
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| 68 | ) |
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| 69 | |||
| 70 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 71 | /* ADC group regular */ |
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| 72 | #if defined(ADC3) |
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| 73 | #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ |
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| 74 | ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ |
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| 75 | ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
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| 76 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
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| 77 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
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| 78 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
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| 79 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
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| 80 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
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| 81 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
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| 82 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
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| 83 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ |
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| 84 | ) \ |
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| 85 | : \ |
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| 86 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
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| 87 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
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| 88 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
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| 89 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
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| 90 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ |
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| 91 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \ |
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| 92 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ |
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| 93 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ |
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| 94 | ) \ |
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| 95 | ) |
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| 96 | #else |
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| 97 | #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC) |
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| 98 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
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| 99 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
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| 100 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
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| 101 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
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| 102 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
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| 103 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
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| 104 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
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| 105 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
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| 106 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
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| 107 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ |
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| 108 | ) |
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| 109 | #else |
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| 110 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
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| 111 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
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| 112 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
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| 113 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
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| 114 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
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| 115 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
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| 116 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
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| 117 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
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| 118 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
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| 119 | ) |
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| 120 | #endif |
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| 121 | #endif |
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| 122 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
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| 123 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
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| 124 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
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| 125 | ) |
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| 126 | |||
| 127 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
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| 128 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
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| 129 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
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| 130 | ) |
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| 131 | |||
| 132 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
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| 133 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
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| 134 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
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| 135 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
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| 136 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
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| 137 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
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| 138 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
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| 139 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
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| 140 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
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| 141 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
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| 142 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
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| 143 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
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| 144 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
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| 145 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
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| 146 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
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| 147 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
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| 148 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
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| 149 | ) |
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| 150 | |||
| 151 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
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| 152 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
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| 153 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
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| 154 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
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| 155 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
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| 156 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
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| 157 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
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| 158 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
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| 159 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
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| 160 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
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| 161 | ) |
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| 162 | |||
| 163 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 164 | /* ADC group injected */ |
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| 165 | #if defined(ADC3) |
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| 166 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ |
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| 167 | ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ |
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| 168 | ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
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| 169 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
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| 170 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
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| 171 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
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| 172 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
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| 173 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
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| 174 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
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| 175 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
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| 176 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ |
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| 177 | ) \ |
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| 178 | : \ |
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| 179 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
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| 180 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
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| 181 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
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| 182 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
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| 183 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ |
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| 184 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \ |
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| 185 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ |
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| 186 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ |
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| 187 | ) \ |
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| 188 | ) |
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| 189 | #else |
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| 190 | #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC) |
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| 191 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
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| 192 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
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| 193 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
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| 194 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
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| 195 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
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| 196 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
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| 197 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
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| 198 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
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| 199 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
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| 200 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ |
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| 201 | ) |
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| 202 | #else |
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| 203 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
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| 204 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
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| 205 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
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| 206 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
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| 207 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
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| 208 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
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| 209 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
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| 210 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
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| 211 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
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| 212 | ) |
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| 213 | #endif |
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| 214 | #endif |
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| 215 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
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| 216 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
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| 217 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
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| 218 | ) |
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| 219 | |||
| 220 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
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| 221 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
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| 222 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
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| 223 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
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| 224 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
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| 225 | ) |
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| 226 | |||
| 227 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
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| 228 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
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| 229 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
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| 230 | ) |
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| 231 | |||
| 232 | #if defined(ADC_MULTIMODE_SUPPORT) |
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| 233 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 234 | /* multimode. */ |
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| 235 | #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ |
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| 236 | ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ |
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| 237 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ |
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| 238 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \ |
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| 239 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \ |
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| 240 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ |
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| 241 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ |
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| 242 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ |
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| 243 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ |
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| 244 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \ |
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| 245 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \ |
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| 246 | ) |
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| 247 | |||
| 248 | #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ |
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| 249 | ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ |
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| 250 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ |
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| 251 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ |
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| 252 | ) |
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| 253 | |||
| 254 | #endif /* ADC_MULTIMODE_SUPPORT */ |
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| 255 | /** |
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| 256 | * @} |
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| 257 | */ |
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| 258 | |||
| 259 | |||
| 260 | /* Private function prototypes -----------------------------------------------*/ |
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| 261 | |||
| 262 | /* Exported functions --------------------------------------------------------*/ |
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| 263 | /** @addtogroup ADC_LL_Exported_Functions |
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| 264 | * @{ |
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| 265 | */ |
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| 266 | |||
| 267 | /** @addtogroup ADC_LL_EF_Init |
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| 268 | * @{ |
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| 269 | */ |
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| 270 | |||
| 271 | /** |
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| 272 | * @brief De-initialize registers of all ADC instances belonging to |
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| 273 | * the same ADC common instance to their default reset values. |
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| 274 | * @param ADCxy_COMMON ADC common instance |
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| 275 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
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| 276 | * @retval An ErrorStatus enumeration value: |
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| 277 | * - SUCCESS: ADC common registers are de-initialized |
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| 278 | * - ERROR: not applicable |
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| 279 | */ |
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| 280 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
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| 281 | { |
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| 282 | /* Check the parameters */ |
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| 283 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
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| 284 | |||
| 285 | /* Force reset of ADC clock (core clock) */ |
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| 286 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); |
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| 287 | |||
| 288 | /* Release reset of ADC clock (core clock) */ |
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| 289 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); |
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| 290 | |||
| 291 | return SUCCESS; |
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| 292 | } |
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| 293 | |||
| 294 | /** |
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| 295 | * @brief Initialize some features of ADC common parameters |
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| 296 | * (all ADC instances belonging to the same ADC common instance) |
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| 297 | * and multimode (for devices with several ADC instances available). |
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| 298 | * @note The setting of ADC common parameters is conditioned to |
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| 299 | * ADC instances state: |
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| 300 | * All ADC instances belonging to the same ADC common instance |
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| 301 | * must be disabled. |
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| 302 | * @param ADCxy_COMMON ADC common instance |
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| 303 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
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| 304 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
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| 305 | * @retval An ErrorStatus enumeration value: |
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| 306 | * - SUCCESS: ADC common registers are initialized |
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| 307 | * - ERROR: ADC common registers are not initialized |
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| 308 | */ |
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| 309 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
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| 310 | { |
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| 311 | ErrorStatus status = SUCCESS; |
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| 312 | |||
| 313 | /* Check the parameters */ |
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| 314 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
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| 315 | #if defined(ADC_MULTIMODE_SUPPORT) |
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| 316 | assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); |
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| 317 | #endif /* ADC_MULTIMODE_SUPPORT */ |
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| 318 | |||
| 319 | /* Note: Hardware constraint (refer to description of functions */ |
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| 320 | /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ |
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| 321 | /* On this STM32 serie, setting of these features is conditioned to */ |
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| 322 | /* ADC state: */ |
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| 323 | /* All ADC instances of the ADC common group must be disabled. */ |
||
| 324 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
||
| 325 | { |
||
| 326 | /* Configuration of ADC hierarchical scope: */ |
||
| 327 | /* - common to several ADC */ |
||
| 328 | /* (all ADC instances belonging to the same ADC common instance) */ |
||
| 329 | /* - multimode (if several ADC instances available on the */ |
||
| 330 | /* selected device) */ |
||
| 331 | /* - Set ADC multimode configuration */ |
||
| 332 | /* - Set ADC multimode DMA transfer */ |
||
| 333 | /* - Set ADC multimode: delay between 2 sampling phases */ |
||
| 334 | #if defined(ADC_MULTIMODE_SUPPORT) |
||
| 335 | if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) |
||
| 336 | { |
||
| 337 | MODIFY_REG(ADCxy_COMMON->CR1, |
||
| 338 | ADC_CR1_DUALMOD, |
||
| 339 | ADC_CommonInitStruct->Multimode |
||
| 340 | ); |
||
| 341 | } |
||
| 342 | else |
||
| 343 | { |
||
| 344 | MODIFY_REG(ADCxy_COMMON->CR1, |
||
| 345 | ADC_CR1_DUALMOD, |
||
| 346 | LL_ADC_MULTI_INDEPENDENT |
||
| 347 | ); |
||
| 348 | } |
||
| 349 | #endif |
||
| 350 | } |
||
| 351 | else |
||
| 352 | { |
||
| 353 | /* Initialization error: One or several ADC instances belonging to */ |
||
| 354 | /* the same ADC common instance are not disabled. */ |
||
| 355 | status = ERROR; |
||
| 356 | } |
||
| 357 | |||
| 358 | return status; |
||
| 359 | } |
||
| 360 | |||
| 361 | /** |
||
| 362 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
||
| 363 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
||
| 364 | * whose fields will be set to default values. |
||
| 365 | * @retval None |
||
| 366 | */ |
||
| 367 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
||
| 368 | { |
||
| 369 | /* Set ADC_CommonInitStruct fields to default values */ |
||
| 370 | /* Set fields of ADC common */ |
||
| 371 | /* (all ADC instances belonging to the same ADC common instance) */ |
||
| 372 | |||
| 373 | #if defined(ADC_MULTIMODE_SUPPORT) |
||
| 374 | /* Set fields of ADC multimode */ |
||
| 375 | ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; |
||
| 376 | #endif /* ADC_MULTIMODE_SUPPORT */ |
||
| 377 | } |
||
| 378 | |||
| 379 | /** |
||
| 380 | * @brief De-initialize registers of the selected ADC instance |
||
| 381 | * to their default reset values. |
||
| 382 | * @note To reset all ADC instances quickly (perform a hard reset), |
||
| 383 | * use function @ref LL_ADC_CommonDeInit(). |
||
| 384 | * @param ADCx ADC instance |
||
| 385 | * @retval An ErrorStatus enumeration value: |
||
| 386 | * - SUCCESS: ADC registers are de-initialized |
||
| 387 | * - ERROR: ADC registers are not de-initialized |
||
| 388 | */ |
||
| 389 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
||
| 390 | { |
||
| 391 | ErrorStatus status = SUCCESS; |
||
| 392 | |||
| 393 | /* Check the parameters */ |
||
| 394 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
||
| 395 | |||
| 396 | /* Disable ADC instance if not already disabled. */ |
||
| 397 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
||
| 398 | { |
||
| 399 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
||
| 400 | /* have an external trigger event occurring during the conversion stop */ |
||
| 401 | /* ADC disable process. */ |
||
| 402 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
||
| 403 | |||
| 404 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
||
| 405 | /* have an external trigger event occurring during the conversion stop */ |
||
| 406 | /* ADC disable process. */ |
||
| 407 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
||
| 408 | |||
| 409 | /* Disable the ADC instance */ |
||
| 410 | LL_ADC_Disable(ADCx); |
||
| 411 | } |
||
| 412 | |||
| 413 | /* Check whether ADC state is compliant with expected state */ |
||
| 414 | /* (hardware requirements of bits state to reset registers below) */ |
||
| 415 | if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) |
||
| 416 | { |
||
| 417 | /* ========== Reset ADC registers ========== */ |
||
| 418 | /* Reset register SR */ |
||
| 419 | CLEAR_BIT(ADCx->SR, |
||
| 420 | ( LL_ADC_FLAG_STRT |
||
| 421 | | LL_ADC_FLAG_JSTRT |
||
| 422 | | LL_ADC_FLAG_EOS |
||
| 423 | | LL_ADC_FLAG_JEOS |
||
| 424 | | LL_ADC_FLAG_AWD1 ) |
||
| 425 | ); |
||
| 426 | |||
| 427 | /* Reset register CR1 */ |
||
| 428 | #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||
| 429 | |||
| 430 | CLEAR_BIT(ADCx->CR1, |
||
| 431 | ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DUALMOD |
||
| 432 | | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
||
| 433 | | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
||
| 434 | | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
||
| 435 | | ADC_CR1_AWDCH ) |
||
| 436 | ); |
||
| 437 | #else |
||
| 438 | |||
| 439 | CLEAR_BIT(ADCx->CR1, |
||
| 440 | ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
||
| 441 | | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
||
| 442 | | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
||
| 443 | | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ) |
||
| 444 | ); |
||
| 445 | #endif |
||
| 446 | |||
| 447 | /* Reset register CR2 */ |
||
| 448 | CLEAR_BIT(ADCx->CR2, |
||
| 449 | ( ADC_CR2_TSVREFE |
||
| 450 | | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL |
||
| 451 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
||
| 452 | | ADC_CR2_ALIGN | ADC_CR2_DMA |
||
| 453 | | ADC_CR2_RSTCAL | ADC_CR2_CAL |
||
| 454 | | ADC_CR2_CONT | ADC_CR2_ADON ) |
||
| 455 | ); |
||
| 456 | |||
| 457 | /* Reset register SMPR1 */ |
||
| 458 | CLEAR_BIT(ADCx->SMPR1, |
||
| 459 | ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 |
||
| 460 | | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
||
| 461 | | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) |
||
| 462 | ); |
||
| 463 | |||
| 464 | /* Reset register SMPR2 */ |
||
| 465 | CLEAR_BIT(ADCx->SMPR2, |
||
| 466 | ( ADC_SMPR2_SMP9 |
||
| 467 | | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 |
||
| 468 | | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 |
||
| 469 | | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) |
||
| 470 | ); |
||
| 471 | |||
| 472 | /* Reset register JOFR1 */ |
||
| 473 | CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
||
| 474 | /* Reset register JOFR2 */ |
||
| 475 | CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
||
| 476 | /* Reset register JOFR3 */ |
||
| 477 | CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
||
| 478 | /* Reset register JOFR4 */ |
||
| 479 | CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
||
| 480 | |||
| 481 | /* Reset register HTR */ |
||
| 482 | SET_BIT(ADCx->HTR, ADC_HTR_HT); |
||
| 483 | /* Reset register LTR */ |
||
| 484 | CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
||
| 485 | |||
| 486 | /* Reset register SQR1 */ |
||
| 487 | CLEAR_BIT(ADCx->SQR1, |
||
| 488 | ( ADC_SQR1_L |
||
| 489 | | ADC_SQR1_SQ16 |
||
| 490 | | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) |
||
| 491 | ); |
||
| 492 | |||
| 493 | /* Reset register SQR2 */ |
||
| 494 | CLEAR_BIT(ADCx->SQR2, |
||
| 495 | ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
||
| 496 | | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) |
||
| 497 | ); |
||
| 498 | |||
| 499 | |||
| 500 | /* Reset register JSQR */ |
||
| 501 | CLEAR_BIT(ADCx->JSQR, |
||
| 502 | ( ADC_JSQR_JL |
||
| 503 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
||
| 504 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
||
| 505 | ); |
||
| 506 | |||
| 507 | /* Reset register DR */ |
||
| 508 | /* bits in access mode read only, no direct reset applicable */ |
||
| 509 | |||
| 510 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
||
| 511 | /* bits in access mode read only, no direct reset applicable */ |
||
| 512 | |||
| 513 | } |
||
| 514 | |||
| 515 | return status; |
||
| 516 | } |
||
| 517 | |||
| 518 | /** |
||
| 519 | * @brief Initialize some features of ADC instance. |
||
| 520 | * @note These parameters have an impact on ADC scope: ADC instance. |
||
| 521 | * Affects both group regular and group injected (availability |
||
| 522 | * of ADC group injected depends on STM32 families). |
||
| 523 | * Refer to corresponding unitary functions into |
||
| 524 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
||
| 525 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
||
| 526 | * is conditioned to ADC state: |
||
| 527 | * ADC instance must be disabled. |
||
| 528 | * This condition is applied to all ADC features, for efficiency |
||
| 529 | * and compatibility over all STM32 families. However, the different |
||
| 530 | * features can be set under different ADC state conditions |
||
| 531 | * (setting possible with ADC enabled without conversion on going, |
||
| 532 | * ADC enabled with conversion on going, ...) |
||
| 533 | * Each feature can be updated afterwards with a unitary function |
||
| 534 | * and potentially with ADC in a different state than disabled, |
||
| 535 | * refer to description of each function for setting |
||
| 536 | * conditioned to ADC state. |
||
| 537 | * @note After using this function, some other features must be configured |
||
| 538 | * using LL unitary functions. |
||
| 539 | * The minimum configuration remaining to be done is: |
||
| 540 | * - Set ADC group regular or group injected sequencer: |
||
| 541 | * map channel on the selected sequencer rank. |
||
| 542 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
||
| 543 | * - Set ADC channel sampling time |
||
| 544 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
||
| 545 | * @param ADCx ADC instance |
||
| 546 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
||
| 547 | * @retval An ErrorStatus enumeration value: |
||
| 548 | * - SUCCESS: ADC registers are initialized |
||
| 549 | * - ERROR: ADC registers are not initialized |
||
| 550 | */ |
||
| 551 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
||
| 552 | { |
||
| 553 | ErrorStatus status = SUCCESS; |
||
| 554 | |||
| 555 | /* Check the parameters */ |
||
| 556 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
||
| 557 | |||
| 558 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
||
| 559 | assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
||
| 560 | |||
| 561 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 562 | /* ADC instance must be disabled. */ |
||
| 563 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
||
| 564 | { |
||
| 565 | /* Configuration of ADC hierarchical scope: */ |
||
| 566 | /* - ADC instance */ |
||
| 567 | /* - Set ADC conversion data alignment */ |
||
| 568 | MODIFY_REG(ADCx->CR1, |
||
| 569 | ADC_CR1_SCAN |
||
| 570 | , |
||
| 571 | ADC_InitStruct->SequencersScanMode |
||
| 572 | ); |
||
| 573 | |||
| 574 | MODIFY_REG(ADCx->CR2, |
||
| 575 | ADC_CR2_ALIGN |
||
| 576 | , |
||
| 577 | ADC_InitStruct->DataAlignment |
||
| 578 | ); |
||
| 579 | |||
| 580 | } |
||
| 581 | else |
||
| 582 | { |
||
| 583 | /* Initialization error: ADC instance is not disabled. */ |
||
| 584 | status = ERROR; |
||
| 585 | } |
||
| 586 | return status; |
||
| 587 | } |
||
| 588 | |||
| 589 | /** |
||
| 590 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
||
| 591 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
||
| 592 | * whose fields will be set to default values. |
||
| 593 | * @retval None |
||
| 594 | */ |
||
| 595 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
||
| 596 | { |
||
| 597 | /* Set ADC_InitStruct fields to default values */ |
||
| 598 | /* Set fields of ADC instance */ |
||
| 599 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
||
| 600 | |||
| 601 | /* Enable scan mode to have a generic behavior with ADC of other */ |
||
| 602 | /* STM32 families, without this setting available: */ |
||
| 603 | /* ADC group regular sequencer and ADC group injected sequencer depend */ |
||
| 604 | /* only of their own configuration. */ |
||
| 605 | ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
||
| 606 | |||
| 607 | } |
||
| 608 | |||
| 609 | /** |
||
| 610 | * @brief Initialize some features of ADC group regular. |
||
| 611 | * @note These parameters have an impact on ADC scope: ADC group regular. |
||
| 612 | * Refer to corresponding unitary functions into |
||
| 613 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
||
| 614 | * (functions with prefix "REG"). |
||
| 615 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
||
| 616 | * is conditioned to ADC state: |
||
| 617 | * ADC instance must be disabled. |
||
| 618 | * This condition is applied to all ADC features, for efficiency |
||
| 619 | * and compatibility over all STM32 families. However, the different |
||
| 620 | * features can be set under different ADC state conditions |
||
| 621 | * (setting possible with ADC enabled without conversion on going, |
||
| 622 | * ADC enabled with conversion on going, ...) |
||
| 623 | * Each feature can be updated afterwards with a unitary function |
||
| 624 | * and potentially with ADC in a different state than disabled, |
||
| 625 | * refer to description of each function for setting |
||
| 626 | * conditioned to ADC state. |
||
| 627 | * @note After using this function, other features must be configured |
||
| 628 | * using LL unitary functions. |
||
| 629 | * The minimum configuration remaining to be done is: |
||
| 630 | * - Set ADC group regular or group injected sequencer: |
||
| 631 | * map channel on the selected sequencer rank. |
||
| 632 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
||
| 633 | * - Set ADC channel sampling time |
||
| 634 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
||
| 635 | * @param ADCx ADC instance |
||
| 636 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
||
| 637 | * @retval An ErrorStatus enumeration value: |
||
| 638 | * - SUCCESS: ADC registers are initialized |
||
| 639 | * - ERROR: ADC registers are not initialized |
||
| 640 | */ |
||
| 641 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
||
| 642 | { |
||
| 643 | ErrorStatus status = SUCCESS; |
||
| 644 | |||
| 645 | /* Check the parameters */ |
||
| 646 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
||
| 647 | #if defined(ADC3) |
||
| 648 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource)); |
||
| 649 | #else |
||
| 650 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
||
| 651 | #endif |
||
| 652 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
||
| 653 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
||
| 654 | { |
||
| 655 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
||
| 656 | } |
||
| 657 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
||
| 658 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
||
| 659 | |||
| 660 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 661 | /* ADC instance must be disabled. */ |
||
| 662 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
||
| 663 | { |
||
| 664 | /* Configuration of ADC hierarchical scope: */ |
||
| 665 | /* - ADC group regular */ |
||
| 666 | /* - Set ADC group regular trigger source */ |
||
| 667 | /* - Set ADC group regular sequencer length */ |
||
| 668 | /* - Set ADC group regular sequencer discontinuous mode */ |
||
| 669 | /* - Set ADC group regular continuous mode */ |
||
| 670 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
||
| 671 | /* transfer by DMA, and DMA requests mode */ |
||
| 672 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
||
| 673 | /* ADC conversion. */ |
||
| 674 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
||
| 675 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
||
| 676 | { |
||
| 677 | MODIFY_REG(ADCx->CR1, |
||
| 678 | ADC_CR1_DISCEN |
||
| 679 | | ADC_CR1_DISCNUM |
||
| 680 | , |
||
| 681 | ADC_REG_InitStruct->SequencerLength |
||
| 682 | | ADC_REG_InitStruct->SequencerDiscont |
||
| 683 | ); |
||
| 684 | } |
||
| 685 | else |
||
| 686 | { |
||
| 687 | MODIFY_REG(ADCx->CR1, |
||
| 688 | ADC_CR1_DISCEN |
||
| 689 | | ADC_CR1_DISCNUM |
||
| 690 | , |
||
| 691 | ADC_REG_InitStruct->SequencerLength |
||
| 692 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
||
| 693 | ); |
||
| 694 | } |
||
| 695 | |||
| 696 | MODIFY_REG(ADCx->CR2, |
||
| 697 | ADC_CR2_EXTSEL |
||
| 698 | | ADC_CR2_CONT |
||
| 699 | | ADC_CR2_DMA |
||
| 700 | , |
||
| 701 | ADC_REG_InitStruct->TriggerSource |
||
| 702 | | ADC_REG_InitStruct->ContinuousMode |
||
| 703 | | ADC_REG_InitStruct->DMATransfer |
||
| 704 | ); |
||
| 705 | |||
| 706 | /* Set ADC group regular sequencer length and scan direction */ |
||
| 707 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 708 | /* Note: If ADC instance feature scan mode is disabled */ |
||
| 709 | /* (refer to ADC instance initialization structure */ |
||
| 710 | /* parameter @ref SequencersScanMode */ |
||
| 711 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
||
| 712 | /* this parameter is discarded. */ |
||
| 713 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
||
| 714 | } |
||
| 715 | else |
||
| 716 | { |
||
| 717 | /* Initialization error: ADC instance is not disabled. */ |
||
| 718 | status = ERROR; |
||
| 719 | } |
||
| 720 | return status; |
||
| 721 | } |
||
| 722 | |||
| 723 | /** |
||
| 724 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
||
| 725 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
||
| 726 | * whose fields will be set to default values. |
||
| 727 | * @retval None |
||
| 728 | */ |
||
| 729 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
||
| 730 | { |
||
| 731 | /* Set ADC_REG_InitStruct fields to default values */ |
||
| 732 | /* Set fields of ADC group regular */ |
||
| 733 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
||
| 734 | /* ADC conversion. */ |
||
| 735 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
||
| 736 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
||
| 737 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
||
| 738 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
||
| 739 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
||
| 740 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
||
| 741 | } |
||
| 742 | |||
| 743 | /** |
||
| 744 | * @brief Initialize some features of ADC group injected. |
||
| 745 | * @note These parameters have an impact on ADC scope: ADC group injected. |
||
| 746 | * Refer to corresponding unitary functions into |
||
| 747 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
||
| 748 | * (functions with prefix "INJ"). |
||
| 749 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
||
| 750 | * is conditioned to ADC state: |
||
| 751 | * ADC instance must be disabled. |
||
| 752 | * This condition is applied to all ADC features, for efficiency |
||
| 753 | * and compatibility over all STM32 families. However, the different |
||
| 754 | * features can be set under different ADC state conditions |
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| 755 | * (setting possible with ADC enabled without conversion on going, |
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| 756 | * ADC enabled with conversion on going, ...) |
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| 757 | * Each feature can be updated afterwards with a unitary function |
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| 758 | * and potentially with ADC in a different state than disabled, |
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| 759 | * refer to description of each function for setting |
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| 760 | * conditioned to ADC state. |
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| 761 | * @note After using this function, other features must be configured |
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| 762 | * using LL unitary functions. |
||
| 763 | * The minimum configuration remaining to be done is: |
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| 764 | * - Set ADC group injected sequencer: |
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| 765 | * map channel on the selected sequencer rank. |
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| 766 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
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| 767 | * - Set ADC channel sampling time |
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| 768 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
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| 769 | * @param ADCx ADC instance |
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| 770 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
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| 771 | * @retval An ErrorStatus enumeration value: |
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| 772 | * - SUCCESS: ADC registers are initialized |
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| 773 | * - ERROR: ADC registers are not initialized |
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| 774 | */ |
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| 775 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
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| 776 | { |
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| 777 | ErrorStatus status = SUCCESS; |
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| 778 | |||
| 779 | /* Check the parameters */ |
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| 780 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
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| 781 | #if defined(ADC3) |
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| 782 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource)); |
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| 783 | #else |
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| 784 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
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| 785 | #endif |
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| 786 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
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| 787 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
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| 788 | { |
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| 789 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
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| 790 | } |
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| 791 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
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| 792 | |||
| 793 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 794 | /* ADC instance must be disabled. */ |
||
| 795 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
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| 796 | { |
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| 797 | /* Configuration of ADC hierarchical scope: */ |
||
| 798 | /* - ADC group injected */ |
||
| 799 | /* - Set ADC group injected trigger source */ |
||
| 800 | /* - Set ADC group injected sequencer length */ |
||
| 801 | /* - Set ADC group injected sequencer discontinuous mode */ |
||
| 802 | /* - Set ADC group injected conversion trigger: independent or */ |
||
| 803 | /* from ADC group regular */ |
||
| 804 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
||
| 805 | /* ADC conversion. */ |
||
| 806 | /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
||
| 807 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
||
| 808 | { |
||
| 809 | MODIFY_REG(ADCx->CR1, |
||
| 810 | ADC_CR1_JDISCEN |
||
| 811 | | ADC_CR1_JAUTO |
||
| 812 | , |
||
| 813 | ADC_INJ_InitStruct->SequencerDiscont |
||
| 814 | | ADC_INJ_InitStruct->TrigAuto |
||
| 815 | ); |
||
| 816 | } |
||
| 817 | else |
||
| 818 | { |
||
| 819 | MODIFY_REG(ADCx->CR1, |
||
| 820 | ADC_CR1_JDISCEN |
||
| 821 | | ADC_CR1_JAUTO |
||
| 822 | , |
||
| 823 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
||
| 824 | | ADC_INJ_InitStruct->TrigAuto |
||
| 825 | ); |
||
| 826 | } |
||
| 827 | |||
| 828 | MODIFY_REG(ADCx->CR2, |
||
| 829 | ADC_CR2_JEXTSEL |
||
| 830 | , |
||
| 831 | ADC_INJ_InitStruct->TriggerSource |
||
| 832 | ); |
||
| 833 | |||
| 834 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 835 | /* Note: If ADC instance feature scan mode is disabled */ |
||
| 836 | /* (refer to ADC instance initialization structure */ |
||
| 837 | /* parameter @ref SequencersScanMode */ |
||
| 838 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
||
| 839 | /* this parameter is discarded. */ |
||
| 840 | LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
||
| 841 | } |
||
| 842 | else |
||
| 843 | { |
||
| 844 | /* Initialization error: ADC instance is not disabled. */ |
||
| 845 | status = ERROR; |
||
| 846 | } |
||
| 847 | return status; |
||
| 848 | } |
||
| 849 | |||
| 850 | /** |
||
| 851 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
||
| 852 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
||
| 853 | * whose fields will be set to default values. |
||
| 854 | * @retval None |
||
| 855 | */ |
||
| 856 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
||
| 857 | { |
||
| 858 | /* Set ADC_INJ_InitStruct fields to default values */ |
||
| 859 | /* Set fields of ADC group injected */ |
||
| 860 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
||
| 861 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
||
| 862 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
||
| 863 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
||
| 864 | } |
||
| 865 | |||
| 866 | /** |
||
| 867 | * @} |
||
| 868 | */ |
||
| 869 | |||
| 870 | /** |
||
| 871 | * @} |
||
| 872 | */ |
||
| 873 | |||
| 874 | /** |
||
| 875 | * @} |
||
| 876 | */ |
||
| 877 | |||
| 878 | #endif /* ADC1 || ADC2 || ADC3 */ |
||
| 879 | |||
| 880 | /** |
||
| 881 | * @} |
||
| 882 | */ |
||
| 883 | |||
| 884 | #endif /* USE_FULL_LL_DRIVER */ |
||
| 885 | |||
| 886 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |