WebSVN – dashGPS – Blame – /branches/dashGPS-bmp/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_nor.c
		4	* @author MCD Application Team
		5	* @brief NOR HAL module driver.
		6	* This file provides a generic firmware to drive NOR memories mounted
		7	* as external device.
		8	*
		9	@verbatim
		10	==============================================================================
		11	##### How to use this driver #####
		12	==============================================================================
		13	[..]
		14	This driver is a generic layered driver which contains a set of APIs used to
		15	control NOR flash memories. It uses the FSMC layer functions to interface
		16	with NOR devices. This driver is used as follows:
		17
		18	(+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
		19	with control and timing parameters for both normal and extended mode.
		20
		21	(+) Read NOR flash memory manufacturer code and device IDs using the function
		22	HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
		23	structure declared by the function caller.
		24
		25	(+) Access NOR flash memory by read/write data unit operations using the functions
		26	HAL_NOR_Read(), HAL_NOR_Program().
		27
		28	(+) Perform NOR flash erase block/chip operations using the functions
		29	HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
		30
		31	(+) Read the NOR flash CFI (common flash interface) IDs using the function
		32	HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
		33	structure declared by the function caller.
		34
		35	(+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
		36	HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
		37
		38	(+) You can monitor the NOR device HAL state by calling the function
		39	HAL_NOR_GetState()
		40	[..]
		41	(@) This driver is a set of generic APIs which handle standard NOR flash operations.
		42	If a NOR flash device contains different operations and/or implementations,
		43	it should be implemented separately.
		44
		45	* NOR HAL driver macros list *
		46	=============================================
		47	[..]
		48	Below the list of most used macros in NOR HAL driver.
		49
		50	(+) NOR_WRITE : NOR memory write data to specified address
		51
		52	* Callback registration *
		53	=============================================
		54	[..]
		55	The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
		56	allows the user to configure dynamically the driver callbacks.
		57
		58	Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
		59	it allows to register following callbacks:
		60	(+) MspInitCallback : NOR MspInit.
		61	(+) MspDeInitCallback : NOR MspDeInit.
		62	This function takes as parameters the HAL peripheral handle, the Callback ID
		63	and a pointer to the user callback function.
		64
		65	Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
		66	weak (surcharged) function. It allows to reset following callbacks:
		67	(+) MspInitCallback : NOR MspInit.
		68	(+) MspDeInitCallback : NOR MspDeInit.
		69	This function) takes as parameters the HAL peripheral handle and the Callback ID.
		70
		71	By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
		72	all callbacks are reset to the corresponding legacy weak (surcharged) functions.
		73	Exception done for MspInit and MspDeInit callbacks that are respectively
		74	reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
		75	and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
		76	If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
		77	keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
		78
		79	Callbacks can be registered/unregistered in READY state only.
		80	Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
		81	in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
		82	during the Init/DeInit.
		83	In that case first register the MspInit/MspDeInit user callbacks
		84	using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
		85	or @ref HAL_NOR_Init function.
		86
		87	When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
		88	not defined, the callback registering feature is not available
		89	and weak (surcharged) callbacks are used.
		90
		91	@endverbatim
		92	******************************************************************************
		93	* @attention
		94	*
		95	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		96	* All rights reserved.</center></h2>
		97	*
		98	* This software component is licensed by ST under BSD 3-Clause license,
		99	* the "License"; You may not use this file except in compliance with the
		100	* License. You may obtain a copy of the License at:
		101	* opensource.org/licenses/BSD-3-Clause
		102	*
		103	******************************************************************************
		104	*/
		105
		106	/* Includes ------------------------------------------------------------------*/
		107	#include "stm32f1xx_hal.h"
		108
		109	#if defined FSMC_BANK1
		110
		111	/** @addtogroup STM32F1xx_HAL_Driver
		112	* @{
		113	*/
		114
		115	#ifdef HAL_NOR_MODULE_ENABLED
		116
		117	/** @defgroup NOR NOR
		118	* @brief NOR driver modules
		119	* @{
		120	*/
		121
		122	/* Private typedef -----------------------------------------------------------*/
		123	/* Private define ------------------------------------------------------------*/
		124
		125	/** @defgroup NOR_Private_Defines NOR Private Defines
		126	* @{
		127	*/
		128
		129	/* Constants to define address to set to write a command */
		130	#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
		131	#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
		132	#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
		133	#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
		134	#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
		135	#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
		136	#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
		137
		138	/* Constants to define data to program a command */
		139	#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
		140	#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
		141	#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
		142	#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
		143	#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
		144	#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
		145	#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
		146	#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
		147	#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
		148	#define NOR_CMD_DATA_CFI (uint16_t)0x0098
		149
		150	#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
		151	#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
		152	#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
		153
		154	/* Mask on NOR STATUS REGISTER */
		155	#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
		156	#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
		157
		158	/**
		159	* @}
		160	*/
		161
		162	/* Private macro -------------------------------------------------------------*/
		163	/* Private variables ---------------------------------------------------------*/
		164	/** @defgroup NOR_Private_Variables NOR Private Variables
		165	* @{
		166	*/
		167
		168	static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
		169
		170	/**
		171	* @}
		172	*/
		173
		174	/* Private functions ---------------------------------------------------------*/
		175	/* Exported functions --------------------------------------------------------*/
		176	/** @defgroup NOR_Exported_Functions NOR Exported Functions
		177	* @{
		178	*/
		179
		180	/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
		181	* @brief Initialization and Configuration functions
		182	*
		183	@verbatim
		184	==============================================================================
		185	##### NOR Initialization and de_initialization functions #####
		186	==============================================================================
		187	[..]
		188	This section provides functions allowing to initialize/de-initialize
		189	the NOR memory
		190
		191	@endverbatim
		192	* @{
		193	*/
		194
		195	/**
		196	* @brief Perform the NOR memory Initialization sequence
		197	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		198	* the configuration information for NOR module.
		199	* @param Timing pointer to NOR control timing structure
		200	* @param ExtTiming pointer to NOR extended mode timing structure
		201	* @retval HAL status
		202	*/
		203	HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef hnor, FSMC_NORSRAM_TimingTypeDef Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
		204	{
		205	/* Check the NOR handle parameter */
		206	if (hnor == NULL)
		207	{
		208	return HAL_ERROR;
		209	}
		210
		211	if (hnor->State == HAL_NOR_STATE_RESET)
		212	{
		213	/* Allocate lock resource and initialize it */
		214	hnor->Lock = HAL_UNLOCKED;
		215
		216	#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
		217	if(hnor->MspInitCallback == NULL)
		218	{
		219	hnor->MspInitCallback = HAL_NOR_MspInit;
		220	}
		221
		222	/* Init the low level hardware */
		223	hnor->MspInitCallback(hnor);
		224	#else
		225	/* Initialize the low level hardware (MSP) */
		226	HAL_NOR_MspInit(hnor);
		227	#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
		228	}
		229
		230	/* Initialize NOR control Interface */
		231	(void)FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
		232
		233	/* Initialize NOR timing Interface */
		234	(void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
		235
		236	/* Initialize NOR extended mode timing Interface */
		237	(void)FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
		238
		239	/* Enable the NORSRAM device */
		240	__FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
		241
		242	/* Initialize NOR Memory Data Width*/
		243	if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
		244	{
		245	uwNORMemoryDataWidth = NOR_MEMORY_8B;
		246	}
		247	else
		248	{
		249	uwNORMemoryDataWidth = NOR_MEMORY_16B;
		250	}
		251
		252	/* Initialize the NOR controller state */
		253	hnor->State = HAL_NOR_STATE_READY;
		254
		255	return HAL_OK;
		256	}
		257
		258	/**
		259	* @brief Perform NOR memory De-Initialization sequence
		260	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		261	* the configuration information for NOR module.
		262	* @retval HAL status
		263	*/
		264	HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
		265	{
		266	#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
		267	if(hnor->MspDeInitCallback == NULL)
		268	{
		269	hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
		270	}
		271
		272	/* DeInit the low level hardware */
		273	hnor->MspDeInitCallback(hnor);
		274	#else
		275	/* De-Initialize the low level hardware (MSP) */
		276	HAL_NOR_MspDeInit(hnor);
		277	#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
		278
		279	/* Configure the NOR registers with their reset values */
		280	(void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
		281
		282	/* Reset the NOR controller state */
		283	hnor->State = HAL_NOR_STATE_RESET;
		284
		285	/* Release Lock */
		286	__HAL_UNLOCK(hnor);
		287
		288	return HAL_OK;
		289	}
		290
		291	/**
		292	* @brief NOR MSP Init
		293	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		294	* the configuration information for NOR module.
		295	* @retval None
		296	*/
		297	__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
		298	{
		299	/* Prevent unused argument(s) compilation warning */
		300	UNUSED(hnor);
		301
		302	/* NOTE : This function Should not be modified, when the callback is needed,
		303	the HAL_NOR_MspInit could be implemented in the user file
		304	*/
		305	}
		306
		307	/**
		308	* @brief NOR MSP DeInit
		309	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		310	* the configuration information for NOR module.
		311	* @retval None
		312	*/
		313	__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
		314	{
		315	/* Prevent unused argument(s) compilation warning */
		316	UNUSED(hnor);
		317
		318	/* NOTE : This function Should not be modified, when the callback is needed,
		319	the HAL_NOR_MspDeInit could be implemented in the user file
		320	*/
		321	}
		322
		323	/**
		324	* @brief NOR MSP Wait for Ready/Busy signal
		325	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		326	* the configuration information for NOR module.
		327	* @param Timeout Maximum timeout value
		328	* @retval None
		329	*/
		330	__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
		331	{
		332	/* Prevent unused argument(s) compilation warning */
		333	UNUSED(hnor);
		334	UNUSED(Timeout);
		335
		336	/* NOTE : This function Should not be modified, when the callback is needed,
		337	the HAL_NOR_MspWait could be implemented in the user file
		338	*/
		339	}
		340
		341	/**
		342	* @}
		343	*/
		344
		345	/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
		346	* @brief Input Output and memory control functions
		347	*
		348	@verbatim
		349	==============================================================================
		350	##### NOR Input and Output functions #####
		351	==============================================================================
		352	[..]
		353	This section provides functions allowing to use and control the NOR memory
		354
		355	@endverbatim
		356	* @{
		357	*/
		358
		359	/**
		360	* @brief Read NOR flash IDs
		361	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		362	* the configuration information for NOR module.
		363	* @param pNOR_ID pointer to NOR ID structure
		364	* @retval HAL status
		365	*/
		366	HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef hnor, NOR_IDTypeDef pNOR_ID)
		367	{
		368	uint32_t deviceaddress;
		369	HAL_NOR_StateTypeDef state;
		370
		371	/* Check the NOR controller state */
		372	state = hnor->State;
		373	if (state == HAL_NOR_STATE_BUSY)
		374	{
		375	return HAL_BUSY;
		376	}
		377	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
		378	{
		379	/* Process Locked */
		380	__HAL_LOCK(hnor);
		381
		382	/* Update the NOR controller state */
		383	hnor->State = HAL_NOR_STATE_BUSY;
		384
		385	/* Select the NOR device address */
		386	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		387	{
		388	deviceaddress = NOR_MEMORY_ADRESS1;
		389	}
		390	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		391	{
		392	deviceaddress = NOR_MEMORY_ADRESS2;
		393	}
		394	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		395	{
		396	deviceaddress = NOR_MEMORY_ADRESS3;
		397	}
		398	else /* FSMC_NORSRAM_BANK4 */
		399	{
		400	deviceaddress = NOR_MEMORY_ADRESS4;
		401	}
		402
		403	/* Send read ID command */
		404	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		405	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		406	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
		407
		408	/* Read the NOR IDs */
		409	pNOR_ID->Manufacturer_Code = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
		410	pNOR_ID->Device_Code1 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
		411	pNOR_ID->Device_Code2 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
		412	pNOR_ID->Device_Code3 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
		413
		414	/* Check the NOR controller state */
		415	hnor->State = state;
		416
		417	/* Process unlocked */
		418	__HAL_UNLOCK(hnor);
		419	}
		420	else
		421	{
		422	return HAL_ERROR;
		423	}
		424
		425	return HAL_OK;
		426	}
		427
		428	/**
		429	* @brief Returns the NOR memory to Read mode.
		430	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		431	* the configuration information for NOR module.
		432	* @retval HAL status
		433	*/
		434	HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
		435	{
		436	uint32_t deviceaddress;
		437	HAL_NOR_StateTypeDef state;
		438
		439	/* Check the NOR controller state */
		440	state = hnor->State;
		441	if (state == HAL_NOR_STATE_BUSY)
		442	{
		443	return HAL_BUSY;
		444	}
		445	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
		446	{
		447	/* Process Locked */
		448	__HAL_LOCK(hnor);
		449
		450	/* Update the NOR controller state */
		451	hnor->State = HAL_NOR_STATE_BUSY;
		452
		453	/* Select the NOR device address */
		454	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		455	{
		456	deviceaddress = NOR_MEMORY_ADRESS1;
		457	}
		458	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		459	{
		460	deviceaddress = NOR_MEMORY_ADRESS2;
		461	}
		462	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		463	{
		464	deviceaddress = NOR_MEMORY_ADRESS3;
		465	}
		466	else /* FSMC_NORSRAM_BANK4 */
		467	{
		468	deviceaddress = NOR_MEMORY_ADRESS4;
		469	}
		470
		471	NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
		472
		473	/* Check the NOR controller state */
		474	hnor->State = state;
		475
		476	/* Process unlocked */
		477	__HAL_UNLOCK(hnor);
		478	}
		479	else
		480	{
		481	return HAL_ERROR;
		482	}
		483
		484	return HAL_OK;
		485	}
		486
		487	/**
		488	* @brief Read data from NOR memory
		489	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		490	* the configuration information for NOR module.
		491	* @param pAddress pointer to Device address
		492	* @param pData pointer to read data
		493	* @retval HAL status
		494	*/
		495	HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef hnor, uint32_t pAddress, uint16_t *pData)
		496	{
		497	uint32_t deviceaddress;
		498	HAL_NOR_StateTypeDef state;
		499
		500	/* Check the NOR controller state */
		501	state = hnor->State;
		502	if (state == HAL_NOR_STATE_BUSY)
		503	{
		504	return HAL_BUSY;
		505	}
		506	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
		507	{
		508	/* Process Locked */
		509	__HAL_LOCK(hnor);
		510
		511	/* Update the NOR controller state */
		512	hnor->State = HAL_NOR_STATE_BUSY;
		513
		514	/* Select the NOR device address */
		515	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		516	{
		517	deviceaddress = NOR_MEMORY_ADRESS1;
		518	}
		519	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		520	{
		521	deviceaddress = NOR_MEMORY_ADRESS2;
		522	}
		523	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		524	{
		525	deviceaddress = NOR_MEMORY_ADRESS3;
		526	}
		527	else /* FSMC_NORSRAM_BANK4 */
		528	{
		529	deviceaddress = NOR_MEMORY_ADRESS4;
		530	}
		531
		532	/* Send read data command */
		533	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		534	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		535	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
		536
		537	/* Read the data */
		538	pData = (uint16_t)((__IO uint32_t *)pAddress);
		539
		540	/* Check the NOR controller state */
		541	hnor->State = state;
		542
		543	/* Process unlocked */
		544	__HAL_UNLOCK(hnor);
		545	}
		546	else
		547	{
		548	return HAL_ERROR;
		549	}
		550
		551	return HAL_OK;
		552	}
		553
		554	/**
		555	* @brief Program data to NOR memory
		556	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		557	* the configuration information for NOR module.
		558	* @param pAddress Device address
		559	* @param pData pointer to the data to write
		560	* @retval HAL status
		561	*/
		562	HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef hnor, uint32_t pAddress, uint16_t *pData)
		563	{
		564	uint32_t deviceaddress;
		565
		566	/* Check the NOR controller state */
		567	if (hnor->State == HAL_NOR_STATE_BUSY)
		568	{
		569	return HAL_BUSY;
		570	}
		571	else if (hnor->State == HAL_NOR_STATE_READY)
		572	{
		573	/* Process Locked */
		574	__HAL_LOCK(hnor);
		575
		576	/* Update the NOR controller state */
		577	hnor->State = HAL_NOR_STATE_BUSY;
		578
		579	/* Select the NOR device address */
		580	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		581	{
		582	deviceaddress = NOR_MEMORY_ADRESS1;
		583	}
		584	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		585	{
		586	deviceaddress = NOR_MEMORY_ADRESS2;
		587	}
		588	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		589	{
		590	deviceaddress = NOR_MEMORY_ADRESS3;
		591	}
		592	else /* FSMC_NORSRAM_BANK4 */
		593	{
		594	deviceaddress = NOR_MEMORY_ADRESS4;
		595	}
		596
		597	/* Send program data command */
		598	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		599	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		600	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
		601
		602	/* Write the data */
		603	NOR_WRITE(pAddress, *pData);
		604
		605	/* Check the NOR controller state */
		606	hnor->State = HAL_NOR_STATE_READY;
		607
		608	/* Process unlocked */
		609	__HAL_UNLOCK(hnor);
		610	}
		611	else
		612	{
		613	return HAL_ERROR;
		614	}
		615
		616	return HAL_OK;
		617	}
		618
		619	/**
		620	* @brief Reads a half-word buffer from the NOR memory.
		621	* @param hnor pointer to the NOR handle
		622	* @param uwAddress NOR memory internal address to read from.
		623	* @param pData pointer to the buffer that receives the data read from the
		624	* NOR memory.
		625	* @param uwBufferSize number of Half word to read.
		626	* @retval HAL status
		627	*/
		628	HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef hnor, uint32_t uwAddress, uint16_t pData, uint32_t uwBufferSize)
		629	{
		630	uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
		631	uint16_t *data = pData;
		632	HAL_NOR_StateTypeDef state;
		633
		634	/* Check the NOR controller state */
		635	state = hnor->State;
		636	if (state == HAL_NOR_STATE_BUSY)
		637	{
		638	return HAL_BUSY;
		639	}
		640	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
		641	{
		642	/* Process Locked */
		643	__HAL_LOCK(hnor);
		644
		645	/* Update the NOR controller state */
		646	hnor->State = HAL_NOR_STATE_BUSY;
		647
		648	/* Select the NOR device address */
		649	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		650	{
		651	deviceaddress = NOR_MEMORY_ADRESS1;
		652	}
		653	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		654	{
		655	deviceaddress = NOR_MEMORY_ADRESS2;
		656	}
		657	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		658	{
		659	deviceaddress = NOR_MEMORY_ADRESS3;
		660	}
		661	else /* FSMC_NORSRAM_BANK4 */
		662	{
		663	deviceaddress = NOR_MEMORY_ADRESS4;
		664	}
		665
		666	/* Send read data command */
		667	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		668	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		669	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
		670
		671	/* Read buffer */
		672	while (size > 0U)
		673	{
		674	data = (__IO uint16_t *)address;
		675	data++;
		676	address += 2U;
		677	size--;
		678	}
		679
		680	/* Check the NOR controller state */
		681	hnor->State = state;
		682
		683	/* Process unlocked */
		684	__HAL_UNLOCK(hnor);
		685	}
		686	else
		687	{
		688	return HAL_ERROR;
		689	}
		690
		691	return HAL_OK;
		692	}
		693
		694	/**
		695	* @brief Writes a half-word buffer to the NOR memory. This function must be used
		696	only with S29GL128P NOR memory.
		697	* @param hnor pointer to the NOR handle
		698	* @param uwAddress NOR memory internal start write address
		699	* @param pData pointer to source data buffer.
		700	* @param uwBufferSize Size of the buffer to write
		701	* @retval HAL status
		702	*/
		703	HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef hnor, uint32_t uwAddress, uint16_t pData, uint32_t uwBufferSize)
		704	{
		705	uint16_t *p_currentaddress;
		706	const uint16_t *p_endaddress;
		707	uint16_t *data = pData;
		708	uint32_t lastloadedaddress, deviceaddress;
		709
		710	/* Check the NOR controller state */
		711	if (hnor->State == HAL_NOR_STATE_BUSY)
		712	{
		713	return HAL_BUSY;
		714	}
		715	else if (hnor->State == HAL_NOR_STATE_READY)
		716	{
		717	/* Process Locked */
		718	__HAL_LOCK(hnor);
		719
		720	/* Update the NOR controller state */
		721	hnor->State = HAL_NOR_STATE_BUSY;
		722
		723	/* Select the NOR device address */
		724	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		725	{
		726	deviceaddress = NOR_MEMORY_ADRESS1;
		727	}
		728	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		729	{
		730	deviceaddress = NOR_MEMORY_ADRESS2;
		731	}
		732	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		733	{
		734	deviceaddress = NOR_MEMORY_ADRESS3;
		735	}
		736	else /* FSMC_NORSRAM_BANK4 */
		737	{
		738	deviceaddress = NOR_MEMORY_ADRESS4;
		739	}
		740
		741	/* Initialize variables */
		742	p_currentaddress = (uint16_t *)(uwAddress);
		743	p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U));
		744	lastloadedaddress = uwAddress;
		745
		746	/* Issue unlock command sequence */
		747	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		748	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		749
		750	/* Write Buffer Load Command */
		751	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
		752	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U));
		753
		754	/* Load Data into NOR Buffer */
		755	while (p_currentaddress <= p_endaddress)
		756	{
		757	/* Store last loaded address & data value (for polling) */
		758	lastloadedaddress = (uint32_t)p_currentaddress;
		759
		760	NOR_WRITE(p_currentaddress, *data);
		761
		762	data++;
		763	p_currentaddress ++;
		764	}
		765
		766	NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
		767
		768	/* Check the NOR controller state */
		769	hnor->State = HAL_NOR_STATE_READY;
		770
		771	/* Process unlocked */
		772	__HAL_UNLOCK(hnor);
		773	}
		774	else
		775	{
		776	return HAL_ERROR;
		777	}
		778
		779	return HAL_OK;
		780
		781	}
		782
		783	/**
		784	* @brief Erase the specified block of the NOR memory
		785	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		786	* the configuration information for NOR module.
		787	* @param BlockAddress Block to erase address
		788	* @param Address Device address
		789	* @retval HAL status
		790	*/
		791	HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
		792	{
		793	uint32_t deviceaddress;
		794
		795	/* Check the NOR controller state */
		796	if (hnor->State == HAL_NOR_STATE_BUSY)
		797	{
		798	return HAL_BUSY;
		799	}
		800	else if (hnor->State == HAL_NOR_STATE_READY)
		801	{
		802	/* Process Locked */
		803	__HAL_LOCK(hnor);
		804
		805	/* Update the NOR controller state */
		806	hnor->State = HAL_NOR_STATE_BUSY;
		807
		808	/* Select the NOR device address */
		809	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		810	{
		811	deviceaddress = NOR_MEMORY_ADRESS1;
		812	}
		813	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		814	{
		815	deviceaddress = NOR_MEMORY_ADRESS2;
		816	}
		817	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		818	{
		819	deviceaddress = NOR_MEMORY_ADRESS3;
		820	}
		821	else /* FSMC_NORSRAM_BANK4 */
		822	{
		823	deviceaddress = NOR_MEMORY_ADRESS4;
		824	}
		825
		826	/* Send block erase command sequence */
		827	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		828	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		829	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
		830	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
		831	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
		832	NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
		833
		834	/* Check the NOR memory status and update the controller state */
		835	hnor->State = HAL_NOR_STATE_READY;
		836
		837	/* Process unlocked */
		838	__HAL_UNLOCK(hnor);
		839	}
		840	else
		841	{
		842	return HAL_ERROR;
		843	}
		844
		845	return HAL_OK;
		846
		847	}
		848
		849	/**
		850	* @brief Erase the entire NOR chip.
		851	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		852	* the configuration information for NOR module.
		853	* @param Address Device address
		854	* @retval HAL status
		855	*/
		856	HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
		857	{
		858	uint32_t deviceaddress;
		859	UNUSED(Address);
		860
		861	/* Check the NOR controller state */
		862	if (hnor->State == HAL_NOR_STATE_BUSY)
		863	{
		864	return HAL_BUSY;
		865	}
		866	else if (hnor->State == HAL_NOR_STATE_READY)
		867	{
		868	/* Process Locked */
		869	__HAL_LOCK(hnor);
		870
		871	/* Update the NOR controller state */
		872	hnor->State = HAL_NOR_STATE_BUSY;
		873
		874	/* Select the NOR device address */
		875	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		876	{
		877	deviceaddress = NOR_MEMORY_ADRESS1;
		878	}
		879	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		880	{
		881	deviceaddress = NOR_MEMORY_ADRESS2;
		882	}
		883	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		884	{
		885	deviceaddress = NOR_MEMORY_ADRESS3;
		886	}
		887	else /* FSMC_NORSRAM_BANK4 */
		888	{
		889	deviceaddress = NOR_MEMORY_ADRESS4;
		890	}
		891
		892	/* Send NOR chip erase command sequence */
		893	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
		894	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
		895	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
		896	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
		897	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
		898	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
		899
		900	/* Check the NOR memory status and update the controller state */
		901	hnor->State = HAL_NOR_STATE_READY;
		902
		903	/* Process unlocked */
		904	__HAL_UNLOCK(hnor);
		905	}
		906	else
		907	{
		908	return HAL_ERROR;
		909	}
		910
		911	return HAL_OK;
		912	}
		913
		914	/**
		915	* @brief Read NOR flash CFI IDs
		916	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		917	* the configuration information for NOR module.
		918	* @param pNOR_CFI pointer to NOR CFI IDs structure
		919	* @retval HAL status
		920	*/
		921	HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef hnor, NOR_CFITypeDef pNOR_CFI)
		922	{
		923	uint32_t deviceaddress;
		924	HAL_NOR_StateTypeDef state;
		925
		926	/* Check the NOR controller state */
		927	state = hnor->State;
		928	if (state == HAL_NOR_STATE_BUSY)
		929	{
		930	return HAL_BUSY;
		931	}
		932	else if ((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_PROTECTED))
		933	{
		934	/* Process Locked */
		935	__HAL_LOCK(hnor);
		936
		937	/* Update the NOR controller state */
		938	hnor->State = HAL_NOR_STATE_BUSY;
		939
		940	/* Select the NOR device address */
		941	if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
		942	{
		943	deviceaddress = NOR_MEMORY_ADRESS1;
		944	}
		945	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
		946	{
		947	deviceaddress = NOR_MEMORY_ADRESS2;
		948	}
		949	else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
		950	{
		951	deviceaddress = NOR_MEMORY_ADRESS3;
		952	}
		953	else /* FSMC_NORSRAM_BANK4 */
		954	{
		955	deviceaddress = NOR_MEMORY_ADRESS4;
		956	}
		957
		958	/* Send read CFI query command */
		959	NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
		960
		961	/* read the NOR CFI information */
		962	pNOR_CFI->CFI_1 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
		963	pNOR_CFI->CFI_2 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
		964	pNOR_CFI->CFI_3 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
		965	pNOR_CFI->CFI_4 = (__IO uint16_t ) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
		966
		967	/* Check the NOR controller state */
		968	hnor->State = state;
		969
		970	/* Process unlocked */
		971	__HAL_UNLOCK(hnor);
		972	}
		973	else
		974	{
		975	return HAL_ERROR;
		976	}
		977
		978	return HAL_OK;
		979	}
		980
		981	#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
		982	/**
		983	* @brief Register a User NOR Callback
		984	* To be used instead of the weak (surcharged) predefined callback
		985	* @param hnor : NOR handle
		986	* @param CallbackId : ID of the callback to be registered
		987	* This parameter can be one of the following values:
		988	* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
		989	* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
		990	* @param pCallback : pointer to the Callback function
		991	* @retval status
		992	*/
		993	HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
		994	{
		995	HAL_StatusTypeDef status = HAL_OK;
		996	HAL_NOR_StateTypeDef state;
		997
		998	if(pCallback == NULL)
		999	{
		1000	return HAL_ERROR;
		1001	}
		1002
		1003	/* Process locked */
		1004	__HAL_LOCK(hnor);
		1005
		1006	state = hnor->State;
		1007	if((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_RESET) \|\| (state == HAL_NOR_STATE_PROTECTED))
		1008	{
		1009	switch (CallbackId)
		1010	{
		1011	case HAL_NOR_MSP_INIT_CB_ID :
		1012	hnor->MspInitCallback = pCallback;
		1013	break;
		1014	case HAL_NOR_MSP_DEINIT_CB_ID :
		1015	hnor->MspDeInitCallback = pCallback;
		1016	break;
		1017	default :
		1018	/* update return status */
		1019	status = HAL_ERROR;
		1020	break;
		1021	}
		1022	}
		1023	else
		1024	{
		1025	/* update return status */
		1026	status = HAL_ERROR;
		1027	}
		1028
		1029	/* Release Lock */
		1030	__HAL_UNLOCK(hnor);
		1031	return status;
		1032	}
		1033
		1034	/**
		1035	* @brief Unregister a User NOR Callback
		1036	* NOR Callback is redirected to the weak (surcharged) predefined callback
		1037	* @param hnor : NOR handle
		1038	* @param CallbackId : ID of the callback to be unregistered
		1039	* This parameter can be one of the following values:
		1040	* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
		1041	* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
		1042	* @retval status
		1043	*/
		1044	HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
		1045	{
		1046	HAL_StatusTypeDef status = HAL_OK;
		1047	HAL_NOR_StateTypeDef state;
		1048
		1049	/* Process locked */
		1050	__HAL_LOCK(hnor);
		1051
		1052	state = hnor->State;
		1053	if((state == HAL_NOR_STATE_READY) \|\| (state == HAL_NOR_STATE_RESET) \|\| (state == HAL_NOR_STATE_PROTECTED))
		1054	{
		1055	switch (CallbackId)
		1056	{
		1057	case HAL_NOR_MSP_INIT_CB_ID :
		1058	hnor->MspInitCallback = HAL_NOR_MspInit;
		1059	break;
		1060	case HAL_NOR_MSP_DEINIT_CB_ID :
		1061	hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
		1062	break;
		1063	default :
		1064	/* update return status */
		1065	status = HAL_ERROR;
		1066	break;
		1067	}
		1068	}
		1069	else
		1070	{
		1071	/* update return status */
		1072	status = HAL_ERROR;
		1073	}
		1074
		1075	/* Release Lock */
		1076	__HAL_UNLOCK(hnor);
		1077	return status;
		1078	}
		1079	#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
		1080
		1081	/**
		1082	* @}
		1083	*/
		1084
		1085	/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
		1086	* @brief management functions
		1087	*
		1088	@verbatim
		1089	==============================================================================
		1090	##### NOR Control functions #####
		1091	==============================================================================
		1092	[..]
		1093	This subsection provides a set of functions allowing to control dynamically
		1094	the NOR interface.
		1095
		1096	@endverbatim
		1097	* @{
		1098	*/
		1099
		1100	/**
		1101	* @brief Enables dynamically NOR write operation.
		1102	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1103	* the configuration information for NOR module.
		1104	* @retval HAL status
		1105	*/
		1106	HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
		1107	{
		1108	/* Check the NOR controller state */
		1109	if(hnor->State == HAL_NOR_STATE_PROTECTED)
		1110	{
		1111	/* Process Locked */
		1112	__HAL_LOCK(hnor);
		1113
		1114	/* Update the NOR controller state */
		1115	hnor->State = HAL_NOR_STATE_BUSY;
		1116
		1117	/* Enable write operation */
		1118	(void)FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
		1119
		1120	/* Update the NOR controller state */
		1121	hnor->State = HAL_NOR_STATE_READY;
		1122
		1123	/* Process unlocked */
		1124	__HAL_UNLOCK(hnor);
		1125	}
		1126	else
		1127	{
		1128	return HAL_ERROR;
		1129	}
		1130
		1131	return HAL_OK;
		1132	}
		1133
		1134	/**
		1135	* @brief Disables dynamically NOR write operation.
		1136	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1137	* the configuration information for NOR module.
		1138	* @retval HAL status
		1139	*/
		1140	HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
		1141	{
		1142	/* Check the NOR controller state */
		1143	if(hnor->State == HAL_NOR_STATE_READY)
		1144	{
		1145	/* Process Locked */
		1146	__HAL_LOCK(hnor);
		1147
		1148	/* Update the NOR controller state */
		1149	hnor->State = HAL_NOR_STATE_BUSY;
		1150
		1151	/* Disable write operation */
		1152	(void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
		1153
		1154	/* Update the NOR controller state */
		1155	hnor->State = HAL_NOR_STATE_PROTECTED;
		1156
		1157	/* Process unlocked */
		1158	__HAL_UNLOCK(hnor);
		1159	}
		1160	else
		1161	{
		1162	return HAL_ERROR;
		1163	}
		1164
		1165	return HAL_OK;
		1166	}
		1167
		1168	/**
		1169	* @}
		1170	*/
		1171
		1172	/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
		1173	* @brief Peripheral State functions
		1174	*
		1175	@verbatim
		1176	==============================================================================
		1177	##### NOR State functions #####
		1178	==============================================================================
		1179	[..]
		1180	This subsection permits to get in run-time the status of the NOR controller
		1181	and the data flow.
		1182
		1183	@endverbatim
		1184	* @{
		1185	*/
		1186
		1187	/**
		1188	* @brief return the NOR controller state
		1189	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1190	* the configuration information for NOR module.
		1191	* @retval NOR controller state
		1192	*/
		1193	HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
		1194	{
		1195	return hnor->State;
		1196	}
		1197
		1198	/**
		1199	* @brief Returns the NOR operation status.
		1200	* @param hnor pointer to a NOR_HandleTypeDef structure that contains
		1201	* the configuration information for NOR module.
		1202	* @param Address Device address
		1203	* @param Timeout NOR programming Timeout
		1204	* @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
		1205	* or HAL_NOR_STATUS_TIMEOUT
		1206	*/
		1207	HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
		1208	{
		1209	HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
		1210	uint16_t tmpSR1, tmpSR2;
		1211	uint32_t tickstart;
		1212
		1213	/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
		1214	HAL_NOR_MspWait(hnor, Timeout);
		1215
		1216	/* Get the NOR memory operation status -------------------------------------*/
		1217
		1218	/* Get tick */
		1219	tickstart = HAL_GetTick();
		1220	while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
		1221	{
		1222	/* Check for the Timeout */
		1223	if (Timeout != HAL_MAX_DELAY)
		1224	{
		1225	if (((HAL_GetTick() - tickstart) > Timeout) \|\| (Timeout == 0U))
		1226	{
		1227	status = HAL_NOR_STATUS_TIMEOUT;
		1228	}
		1229	}
		1230
		1231	/* Read NOR status register (DQ6 and DQ5) */
		1232	tmpSR1 = (__IO uint16_t )Address;
		1233	tmpSR2 = (__IO uint16_t )Address;
		1234
		1235	/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
		1236	if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
		1237	{
		1238	return HAL_NOR_STATUS_SUCCESS ;
		1239	}
		1240
		1241	if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
		1242	{
		1243	status = HAL_NOR_STATUS_ONGOING;
		1244	}
		1245
		1246	tmpSR1 = (__IO uint16_t )Address;
		1247	tmpSR2 = (__IO uint16_t )Address;
		1248
		1249	/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
		1250	if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
		1251	{
		1252	return HAL_NOR_STATUS_SUCCESS;
		1253	}
		1254	if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
		1255	{
		1256	return HAL_NOR_STATUS_ERROR;
		1257	}
		1258	}
		1259
		1260	/* Return the operation status */
		1261	return status;
		1262	}
		1263
		1264	/**
		1265	* @}
		1266	*/
		1267
		1268	/**
		1269	* @}
		1270	*/
		1271
		1272	/**
		1273	* @}
		1274	*/
		1275
		1276	#endif /* HAL_NOR_MODULE_ENABLED */
		1277
		1278	/**
		1279	* @}
		1280	*/
		1281
		1282	#endif /* FSMC_BANK1 */
		1283
		1284	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories dashGPS

(root)/branches/dashGPS-bmp/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c – Rev 18