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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f1xx_hal_dma.c |
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4 | * @author MCD Application Team |
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5 | * @brief DMA HAL module driver. |
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6 | * This file provides firmware functions to manage the following |
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7 | * functionalities of the Direct Memory Access (DMA) peripheral: |
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8 | * + Initialization and de-initialization functions |
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9 | * + IO operation functions |
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10 | * + Peripheral State and errors functions |
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11 | @verbatim |
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12 | ============================================================================== |
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13 | ##### How to use this driver ##### |
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14 | ============================================================================== |
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15 | [..] |
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16 | (#) Enable and configure the peripheral to be connected to the DMA Channel |
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17 | (except for internal SRAM / FLASH memories: no initialization is |
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18 | necessary). Please refer to the Reference manual for connection between peripherals |
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19 | and DMA requests. |
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20 | |||
21 | (#) For a given Channel, program the required configuration through the following parameters: |
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22 | Channel request, Transfer Direction, Source and Destination data formats, |
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23 | Circular or Normal mode, Channel Priority level, Source and Destination Increment mode |
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24 | using HAL_DMA_Init() function. |
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25 | |||
26 | (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error |
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27 | detection. |
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28 | |||
29 | (#) Use HAL_DMA_Abort() function to abort the current transfer |
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30 | |||
31 | -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. |
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32 | *** Polling mode IO operation *** |
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33 | ================================= |
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34 | [..] |
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35 | (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source |
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36 | address and destination address and the Length of data to be transferred |
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37 | (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this |
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38 | case a fixed Timeout can be configured by User depending from his application. |
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39 | |||
40 | *** Interrupt mode IO operation *** |
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41 | =================================== |
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42 | [..] |
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43 | (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() |
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44 | (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() |
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45 | (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of |
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46 | Source address and destination address and the Length of data to be transferred. |
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47 | In this case the DMA interrupt is configured |
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48 | (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine |
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49 | (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can |
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50 | add his own function by customization of function pointer XferCpltCallback and |
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51 | XferErrorCallback (i.e. a member of DMA handle structure). |
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52 | |||
53 | *** DMA HAL driver macros list *** |
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54 | ============================================= |
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55 | [..] |
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56 | Below the list of most used macros in DMA HAL driver. |
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57 | |||
58 | (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. |
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59 | (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. |
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60 | (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. |
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61 | (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. |
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62 | (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. |
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63 | (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. |
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64 | (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. |
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65 | |||
66 | [..] |
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67 | (@) You can refer to the DMA HAL driver header file for more useful macros |
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68 | |||
69 | @endverbatim |
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70 | ****************************************************************************** |
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71 | * @attention |
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72 | * |
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73 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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74 | * All rights reserved.</center></h2> |
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75 | * |
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76 | * This software component is licensed by ST under BSD 3-Clause license, |
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77 | * the "License"; You may not use this file except in compliance with the |
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78 | * License. You may obtain a copy of the License at: |
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79 | * opensource.org/licenses/BSD-3-Clause |
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80 | * |
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81 | ****************************************************************************** |
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82 | */ |
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83 | |||
84 | /* Includes ------------------------------------------------------------------*/ |
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85 | #include "stm32f1xx_hal.h" |
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86 | |||
87 | /** @addtogroup STM32F1xx_HAL_Driver |
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88 | * @{ |
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89 | */ |
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90 | |||
91 | /** @defgroup DMA DMA |
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92 | * @brief DMA HAL module driver |
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93 | * @{ |
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94 | */ |
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95 | |||
96 | #ifdef HAL_DMA_MODULE_ENABLED |
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97 | |||
98 | /* Private typedef -----------------------------------------------------------*/ |
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99 | /* Private define ------------------------------------------------------------*/ |
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100 | /* Private macro -------------------------------------------------------------*/ |
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101 | /* Private variables ---------------------------------------------------------*/ |
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102 | /* Private function prototypes -----------------------------------------------*/ |
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103 | /** @defgroup DMA_Private_Functions DMA Private Functions |
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104 | * @{ |
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105 | */ |
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106 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
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107 | /** |
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108 | * @} |
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109 | */ |
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110 | |||
111 | /* Exported functions ---------------------------------------------------------*/ |
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112 | |||
113 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
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114 | * @{ |
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115 | */ |
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116 | |||
117 | /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
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118 | * @brief Initialization and de-initialization functions |
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119 | * |
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120 | @verbatim |
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121 | =============================================================================== |
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122 | ##### Initialization and de-initialization functions ##### |
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123 | =============================================================================== |
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124 | [..] |
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125 | This section provides functions allowing to initialize the DMA Channel source |
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126 | and destination addresses, incrementation and data sizes, transfer direction, |
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127 | circular/normal mode selection, memory-to-memory mode selection and Channel priority value. |
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128 | [..] |
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129 | The HAL_DMA_Init() function follows the DMA configuration procedures as described in |
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130 | reference manual. |
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131 | |||
132 | @endverbatim |
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133 | * @{ |
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134 | */ |
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135 | |||
136 | /** |
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137 | * @brief Initialize the DMA according to the specified |
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138 | * parameters in the DMA_InitTypeDef and initialize the associated handle. |
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139 | * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains |
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140 | * the configuration information for the specified DMA Channel. |
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141 | * @retval HAL status |
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142 | */ |
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143 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) |
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144 | { |
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145 | uint32_t tmp = 0U; |
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146 | |||
147 | /* Check the DMA handle allocation */ |
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148 | if(hdma == NULL) |
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149 | { |
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150 | return HAL_ERROR; |
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151 | } |
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152 | |||
153 | /* Check the parameters */ |
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154 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
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155 | assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); |
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156 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); |
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157 | assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); |
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158 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
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159 | assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
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160 | assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
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161 | assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
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162 | |||
163 | #if defined (DMA2) |
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164 | /* calculation of the channel index */ |
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165 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
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166 | { |
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167 | /* DMA1 */ |
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168 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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169 | hdma->DmaBaseAddress = DMA1; |
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170 | } |
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171 | else |
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172 | { |
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173 | /* DMA2 */ |
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174 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
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175 | hdma->DmaBaseAddress = DMA2; |
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176 | } |
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177 | #else |
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178 | /* DMA1 */ |
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179 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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180 | hdma->DmaBaseAddress = DMA1; |
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181 | #endif /* DMA2 */ |
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182 | |||
183 | /* Change DMA peripheral state */ |
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184 | hdma->State = HAL_DMA_STATE_BUSY; |
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185 | |||
186 | /* Get the CR register value */ |
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187 | tmp = hdma->Instance->CCR; |
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188 | |||
189 | /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ |
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190 | tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ |
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191 | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ |
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192 | DMA_CCR_DIR)); |
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193 | |||
194 | /* Prepare the DMA Channel configuration */ |
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195 | tmp |= hdma->Init.Direction | |
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196 | hdma->Init.PeriphInc | hdma->Init.MemInc | |
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197 | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | |
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198 | hdma->Init.Mode | hdma->Init.Priority; |
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199 | |||
200 | /* Write to DMA Channel CR register */ |
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201 | hdma->Instance->CCR = tmp; |
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202 | |||
203 | /* Initialise the error code */ |
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204 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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205 | |||
206 | /* Initialize the DMA state*/ |
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207 | hdma->State = HAL_DMA_STATE_READY; |
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208 | /* Allocate lock resource and initialize it */ |
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209 | hdma->Lock = HAL_UNLOCKED; |
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210 | |||
211 | return HAL_OK; |
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212 | } |
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213 | |||
214 | /** |
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215 | * @brief DeInitialize the DMA peripheral. |
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216 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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217 | * the configuration information for the specified DMA Channel. |
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218 | * @retval HAL status |
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219 | */ |
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220 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) |
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221 | { |
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222 | /* Check the DMA handle allocation */ |
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223 | if(hdma == NULL) |
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224 | { |
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225 | return HAL_ERROR; |
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226 | } |
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227 | |||
228 | /* Check the parameters */ |
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229 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
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230 | |||
231 | /* Disable the selected DMA Channelx */ |
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232 | __HAL_DMA_DISABLE(hdma); |
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233 | |||
234 | /* Reset DMA Channel control register */ |
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235 | hdma->Instance->CCR = 0U; |
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236 | |||
237 | /* Reset DMA Channel Number of Data to Transfer register */ |
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238 | hdma->Instance->CNDTR = 0U; |
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239 | |||
240 | /* Reset DMA Channel peripheral address register */ |
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241 | hdma->Instance->CPAR = 0U; |
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242 | |||
243 | /* Reset DMA Channel memory address register */ |
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244 | hdma->Instance->CMAR = 0U; |
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245 | |||
246 | #if defined (DMA2) |
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247 | /* calculation of the channel index */ |
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248 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
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249 | { |
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250 | /* DMA1 */ |
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251 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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252 | hdma->DmaBaseAddress = DMA1; |
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253 | } |
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254 | else |
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255 | { |
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256 | /* DMA2 */ |
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257 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
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258 | hdma->DmaBaseAddress = DMA2; |
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259 | } |
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260 | #else |
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261 | /* DMA1 */ |
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262 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
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263 | hdma->DmaBaseAddress = DMA1; |
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264 | #endif /* DMA2 */ |
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265 | |||
266 | /* Clear all flags */ |
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267 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); |
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268 | |||
269 | /* Clean all callbacks */ |
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270 | hdma->XferCpltCallback = NULL; |
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271 | hdma->XferHalfCpltCallback = NULL; |
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272 | hdma->XferErrorCallback = NULL; |
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273 | hdma->XferAbortCallback = NULL; |
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274 | |||
275 | /* Reset the error code */ |
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276 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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277 | |||
278 | /* Reset the DMA state */ |
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279 | hdma->State = HAL_DMA_STATE_RESET; |
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280 | |||
281 | /* Release Lock */ |
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282 | __HAL_UNLOCK(hdma); |
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283 | |||
284 | return HAL_OK; |
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285 | } |
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286 | |||
287 | /** |
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288 | * @} |
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289 | */ |
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290 | |||
291 | /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions |
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292 | * @brief Input and Output operation functions |
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293 | * |
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294 | @verbatim |
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295 | =============================================================================== |
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296 | ##### IO operation functions ##### |
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297 | =============================================================================== |
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298 | [..] This section provides functions allowing to: |
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299 | (+) Configure the source, destination address and data length and Start DMA transfer |
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300 | (+) Configure the source, destination address and data length and |
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301 | Start DMA transfer with interrupt |
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302 | (+) Abort DMA transfer |
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303 | (+) Poll for transfer complete |
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304 | (+) Handle DMA interrupt request |
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305 | |||
306 | @endverbatim |
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307 | * @{ |
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308 | */ |
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309 | |||
310 | /** |
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311 | * @brief Start the DMA Transfer. |
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312 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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313 | * the configuration information for the specified DMA Channel. |
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314 | * @param SrcAddress: The source memory Buffer address |
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315 | * @param DstAddress: The destination memory Buffer address |
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316 | * @param DataLength: The length of data to be transferred from source to destination |
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317 | * @retval HAL status |
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318 | */ |
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319 | HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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320 | { |
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321 | HAL_StatusTypeDef status = HAL_OK; |
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322 | |||
323 | /* Check the parameters */ |
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324 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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325 | |||
326 | /* Process locked */ |
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327 | __HAL_LOCK(hdma); |
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328 | |||
329 | if(HAL_DMA_STATE_READY == hdma->State) |
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330 | { |
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331 | /* Change DMA peripheral state */ |
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332 | hdma->State = HAL_DMA_STATE_BUSY; |
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333 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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334 | |||
335 | /* Disable the peripheral */ |
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336 | __HAL_DMA_DISABLE(hdma); |
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337 | |||
338 | /* Configure the source, destination address and the data length & clear flags*/ |
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339 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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340 | |||
341 | /* Enable the Peripheral */ |
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342 | __HAL_DMA_ENABLE(hdma); |
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343 | } |
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344 | else |
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345 | { |
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346 | /* Process Unlocked */ |
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347 | __HAL_UNLOCK(hdma); |
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348 | status = HAL_BUSY; |
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349 | } |
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350 | return status; |
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351 | } |
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352 | |||
353 | /** |
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354 | * @brief Start the DMA Transfer with interrupt enabled. |
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355 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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356 | * the configuration information for the specified DMA Channel. |
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357 | * @param SrcAddress: The source memory Buffer address |
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358 | * @param DstAddress: The destination memory Buffer address |
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359 | * @param DataLength: The length of data to be transferred from source to destination |
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360 | * @retval HAL status |
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361 | */ |
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362 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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363 | { |
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364 | HAL_StatusTypeDef status = HAL_OK; |
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365 | |||
366 | /* Check the parameters */ |
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367 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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368 | |||
369 | /* Process locked */ |
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370 | __HAL_LOCK(hdma); |
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371 | |||
372 | if(HAL_DMA_STATE_READY == hdma->State) |
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373 | { |
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374 | /* Change DMA peripheral state */ |
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375 | hdma->State = HAL_DMA_STATE_BUSY; |
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376 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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377 | |||
378 | /* Disable the peripheral */ |
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379 | __HAL_DMA_DISABLE(hdma); |
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380 | |||
381 | /* Configure the source, destination address and the data length & clear flags*/ |
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382 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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383 | |||
384 | /* Enable the transfer complete interrupt */ |
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385 | /* Enable the transfer Error interrupt */ |
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386 | if(NULL != hdma->XferHalfCpltCallback) |
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387 | { |
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388 | /* Enable the Half transfer complete interrupt as well */ |
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389 | __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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390 | } |
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391 | else |
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392 | { |
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393 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
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394 | __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); |
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395 | } |
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396 | /* Enable the Peripheral */ |
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397 | __HAL_DMA_ENABLE(hdma); |
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398 | } |
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399 | else |
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400 | { |
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401 | /* Process Unlocked */ |
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402 | __HAL_UNLOCK(hdma); |
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403 | |||
404 | /* Remain BUSY */ |
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405 | status = HAL_BUSY; |
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406 | } |
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407 | return status; |
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408 | } |
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409 | |||
410 | /** |
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411 | * @brief Abort the DMA Transfer. |
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412 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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413 | * the configuration information for the specified DMA Channel. |
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414 | * @retval HAL status |
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415 | */ |
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416 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
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417 | { |
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418 | HAL_StatusTypeDef status = HAL_OK; |
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419 | |||
420 | if(hdma->State != HAL_DMA_STATE_BUSY) |
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421 | { |
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422 | /* no transfer ongoing */ |
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423 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
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424 | |||
425 | /* Process Unlocked */ |
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426 | __HAL_UNLOCK(hdma); |
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427 | |||
428 | return HAL_ERROR; |
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429 | } |
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430 | else |
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431 | |||
432 | { |
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433 | /* Disable DMA IT */ |
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434 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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435 | |||
436 | /* Disable the channel */ |
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437 | __HAL_DMA_DISABLE(hdma); |
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438 | |||
439 | /* Clear all flags */ |
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440 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
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441 | } |
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442 | /* Change the DMA state */ |
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443 | hdma->State = HAL_DMA_STATE_READY; |
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444 | |||
445 | /* Process Unlocked */ |
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446 | __HAL_UNLOCK(hdma); |
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447 | |||
448 | return status; |
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449 | } |
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450 | |||
451 | /** |
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452 | * @brief Aborts the DMA Transfer in Interrupt mode. |
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453 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
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454 | * the configuration information for the specified DMA Channel. |
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455 | * @retval HAL status |
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456 | */ |
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457 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) |
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458 | { |
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459 | HAL_StatusTypeDef status = HAL_OK; |
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460 | |||
461 | if(HAL_DMA_STATE_BUSY != hdma->State) |
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462 | { |
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463 | /* no transfer ongoing */ |
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464 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
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465 | |||
466 | status = HAL_ERROR; |
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467 | } |
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468 | else |
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469 | { |
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470 | /* Disable DMA IT */ |
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471 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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472 | |||
473 | /* Disable the channel */ |
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474 | __HAL_DMA_DISABLE(hdma); |
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475 | |||
476 | /* Clear all flags */ |
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477 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); |
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478 | |||
479 | /* Change the DMA state */ |
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480 | hdma->State = HAL_DMA_STATE_READY; |
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481 | |||
482 | /* Process Unlocked */ |
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483 | __HAL_UNLOCK(hdma); |
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484 | |||
485 | /* Call User Abort callback */ |
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486 | if(hdma->XferAbortCallback != NULL) |
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487 | { |
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488 | hdma->XferAbortCallback(hdma); |
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489 | } |
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490 | } |
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491 | return status; |
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492 | } |
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493 | |||
494 | /** |
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495 | * @brief Polling for transfer complete. |
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496 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
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497 | * the configuration information for the specified DMA Channel. |
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498 | * @param CompleteLevel: Specifies the DMA level complete. |
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499 | * @param Timeout: Timeout duration. |
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500 | * @retval HAL status |
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501 | */ |
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502 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) |
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503 | { |
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504 | uint32_t temp; |
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505 | uint32_t tickstart = 0U; |
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506 | |||
507 | if(HAL_DMA_STATE_BUSY != hdma->State) |
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508 | { |
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509 | /* no transfer ongoing */ |
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510 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
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511 | __HAL_UNLOCK(hdma); |
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512 | return HAL_ERROR; |
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513 | } |
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514 | |||
515 | /* Polling mode not supported in circular mode */ |
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516 | if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) |
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517 | { |
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518 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; |
||
519 | return HAL_ERROR; |
||
520 | } |
||
521 | |||
522 | /* Get the level transfer complete flag */ |
||
523 | if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
||
524 | { |
||
525 | /* Transfer Complete flag */ |
||
526 | temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); |
||
527 | } |
||
528 | else |
||
529 | { |
||
530 | /* Half Transfer Complete flag */ |
||
531 | temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); |
||
532 | } |
||
533 | |||
534 | /* Get tick */ |
||
535 | tickstart = HAL_GetTick(); |
||
536 | |||
537 | while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) |
||
538 | { |
||
539 | if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) |
||
540 | { |
||
541 | /* When a DMA transfer error occurs */ |
||
542 | /* A hardware clear of its EN bits is performed */ |
||
543 | /* Clear all flags */ |
||
544 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||
545 | |||
546 | /* Update error code */ |
||
547 | SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); |
||
548 | |||
549 | /* Change the DMA state */ |
||
550 | hdma->State= HAL_DMA_STATE_READY; |
||
551 | |||
552 | /* Process Unlocked */ |
||
553 | __HAL_UNLOCK(hdma); |
||
554 | |||
555 | return HAL_ERROR; |
||
556 | } |
||
557 | /* Check for the Timeout */ |
||
558 | if(Timeout != HAL_MAX_DELAY) |
||
559 | { |
||
560 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) |
||
561 | { |
||
562 | /* Update error code */ |
||
563 | SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); |
||
564 | |||
565 | /* Change the DMA state */ |
||
566 | hdma->State = HAL_DMA_STATE_READY; |
||
567 | |||
568 | /* Process Unlocked */ |
||
569 | __HAL_UNLOCK(hdma); |
||
570 | |||
571 | return HAL_ERROR; |
||
572 | } |
||
573 | } |
||
574 | } |
||
575 | |||
576 | if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
||
577 | { |
||
578 | /* Clear the transfer complete flag */ |
||
579 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
||
580 | |||
581 | /* The selected Channelx EN bit is cleared (DMA is disabled and |
||
582 | all transfers are complete) */ |
||
583 | hdma->State = HAL_DMA_STATE_READY; |
||
584 | } |
||
585 | else |
||
586 | { |
||
587 | /* Clear the half transfer complete flag */ |
||
588 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
||
589 | } |
||
590 | |||
591 | /* Process unlocked */ |
||
592 | __HAL_UNLOCK(hdma); |
||
593 | |||
594 | return HAL_OK; |
||
595 | } |
||
596 | |||
597 | /** |
||
598 | * @brief Handles DMA interrupt request. |
||
599 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
600 | * the configuration information for the specified DMA Channel. |
||
601 | * @retval None |
||
602 | */ |
||
603 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) |
||
604 | { |
||
605 | uint32_t flag_it = hdma->DmaBaseAddress->ISR; |
||
606 | uint32_t source_it = hdma->Instance->CCR; |
||
607 | |||
608 | /* Half Transfer Complete Interrupt management ******************************/ |
||
609 | if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) |
||
610 | { |
||
611 | /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ |
||
612 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||
613 | { |
||
614 | /* Disable the half transfer interrupt */ |
||
615 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
||
616 | } |
||
617 | /* Clear the half transfer complete flag */ |
||
618 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
||
619 | |||
620 | /* DMA peripheral state is not updated in Half Transfer */ |
||
621 | /* but in Transfer Complete case */ |
||
622 | |||
623 | if(hdma->XferHalfCpltCallback != NULL) |
||
624 | { |
||
625 | /* Half transfer callback */ |
||
626 | hdma->XferHalfCpltCallback(hdma); |
||
627 | } |
||
628 | } |
||
629 | |||
630 | /* Transfer Complete Interrupt management ***********************************/ |
||
631 | else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) |
||
632 | { |
||
633 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||
634 | { |
||
635 | /* Disable the transfer complete and error interrupt */ |
||
636 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); |
||
637 | |||
638 | /* Change the DMA state */ |
||
639 | hdma->State = HAL_DMA_STATE_READY; |
||
640 | } |
||
641 | /* Clear the transfer complete flag */ |
||
642 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
||
643 | |||
644 | /* Process Unlocked */ |
||
645 | __HAL_UNLOCK(hdma); |
||
646 | |||
647 | if(hdma->XferCpltCallback != NULL) |
||
648 | { |
||
649 | /* Transfer complete callback */ |
||
650 | hdma->XferCpltCallback(hdma); |
||
651 | } |
||
652 | } |
||
653 | |||
654 | /* Transfer Error Interrupt management **************************************/ |
||
655 | else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) |
||
656 | { |
||
657 | /* When a DMA transfer error occurs */ |
||
658 | /* A hardware clear of its EN bits is performed */ |
||
659 | /* Disable ALL DMA IT */ |
||
660 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
||
661 | |||
662 | /* Clear all flags */ |
||
663 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||
664 | |||
665 | /* Update error code */ |
||
666 | hdma->ErrorCode = HAL_DMA_ERROR_TE; |
||
667 | |||
668 | /* Change the DMA state */ |
||
669 | hdma->State = HAL_DMA_STATE_READY; |
||
670 | |||
671 | /* Process Unlocked */ |
||
672 | __HAL_UNLOCK(hdma); |
||
673 | |||
674 | if (hdma->XferErrorCallback != NULL) |
||
675 | { |
||
676 | /* Transfer error callback */ |
||
677 | hdma->XferErrorCallback(hdma); |
||
678 | } |
||
679 | } |
||
680 | return; |
||
681 | } |
||
682 | |||
683 | /** |
||
684 | * @brief Register callbacks |
||
685 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
686 | * the configuration information for the specified DMA Channel. |
||
687 | * @param CallbackID: User Callback identifer |
||
688 | * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||
689 | * @param pCallback: pointer to private callbacsk function which has pointer to |
||
690 | * a DMA_HandleTypeDef structure as parameter. |
||
691 | * @retval HAL status |
||
692 | */ |
||
693 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) |
||
694 | { |
||
695 | HAL_StatusTypeDef status = HAL_OK; |
||
696 | |||
697 | /* Process locked */ |
||
698 | __HAL_LOCK(hdma); |
||
699 | |||
700 | if(HAL_DMA_STATE_READY == hdma->State) |
||
701 | { |
||
702 | switch (CallbackID) |
||
703 | { |
||
704 | case HAL_DMA_XFER_CPLT_CB_ID: |
||
705 | hdma->XferCpltCallback = pCallback; |
||
706 | break; |
||
707 | |||
708 | case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||
709 | hdma->XferHalfCpltCallback = pCallback; |
||
710 | break; |
||
711 | |||
712 | case HAL_DMA_XFER_ERROR_CB_ID: |
||
713 | hdma->XferErrorCallback = pCallback; |
||
714 | break; |
||
715 | |||
716 | case HAL_DMA_XFER_ABORT_CB_ID: |
||
717 | hdma->XferAbortCallback = pCallback; |
||
718 | break; |
||
719 | |||
720 | default: |
||
721 | status = HAL_ERROR; |
||
722 | break; |
||
723 | } |
||
724 | } |
||
725 | else |
||
726 | { |
||
727 | status = HAL_ERROR; |
||
728 | } |
||
729 | |||
730 | /* Release Lock */ |
||
731 | __HAL_UNLOCK(hdma); |
||
732 | |||
733 | return status; |
||
734 | } |
||
735 | |||
736 | /** |
||
737 | * @brief UnRegister callbacks |
||
738 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
739 | * the configuration information for the specified DMA Channel. |
||
740 | * @param CallbackID: User Callback identifer |
||
741 | * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||
742 | * @retval HAL status |
||
743 | */ |
||
744 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) |
||
745 | { |
||
746 | HAL_StatusTypeDef status = HAL_OK; |
||
747 | |||
748 | /* Process locked */ |
||
749 | __HAL_LOCK(hdma); |
||
750 | |||
751 | if(HAL_DMA_STATE_READY == hdma->State) |
||
752 | { |
||
753 | switch (CallbackID) |
||
754 | { |
||
755 | case HAL_DMA_XFER_CPLT_CB_ID: |
||
756 | hdma->XferCpltCallback = NULL; |
||
757 | break; |
||
758 | |||
759 | case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||
760 | hdma->XferHalfCpltCallback = NULL; |
||
761 | break; |
||
762 | |||
763 | case HAL_DMA_XFER_ERROR_CB_ID: |
||
764 | hdma->XferErrorCallback = NULL; |
||
765 | break; |
||
766 | |||
767 | case HAL_DMA_XFER_ABORT_CB_ID: |
||
768 | hdma->XferAbortCallback = NULL; |
||
769 | break; |
||
770 | |||
771 | case HAL_DMA_XFER_ALL_CB_ID: |
||
772 | hdma->XferCpltCallback = NULL; |
||
773 | hdma->XferHalfCpltCallback = NULL; |
||
774 | hdma->XferErrorCallback = NULL; |
||
775 | hdma->XferAbortCallback = NULL; |
||
776 | break; |
||
777 | |||
778 | default: |
||
779 | status = HAL_ERROR; |
||
780 | break; |
||
781 | } |
||
782 | } |
||
783 | else |
||
784 | { |
||
785 | status = HAL_ERROR; |
||
786 | } |
||
787 | |||
788 | /* Release Lock */ |
||
789 | __HAL_UNLOCK(hdma); |
||
790 | |||
791 | return status; |
||
792 | } |
||
793 | |||
794 | /** |
||
795 | * @} |
||
796 | */ |
||
797 | |||
798 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions |
||
799 | * @brief Peripheral State and Errors functions |
||
800 | * |
||
801 | @verbatim |
||
802 | =============================================================================== |
||
803 | ##### Peripheral State and Errors functions ##### |
||
804 | =============================================================================== |
||
805 | [..] |
||
806 | This subsection provides functions allowing to |
||
807 | (+) Check the DMA state |
||
808 | (+) Get error code |
||
809 | |||
810 | @endverbatim |
||
811 | * @{ |
||
812 | */ |
||
813 | |||
814 | /** |
||
815 | * @brief Return the DMA hande state. |
||
816 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
817 | * the configuration information for the specified DMA Channel. |
||
818 | * @retval HAL state |
||
819 | */ |
||
820 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) |
||
821 | { |
||
822 | /* Return DMA handle state */ |
||
823 | return hdma->State; |
||
824 | } |
||
825 | |||
826 | /** |
||
827 | * @brief Return the DMA error code. |
||
828 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
||
829 | * the configuration information for the specified DMA Channel. |
||
830 | * @retval DMA Error Code |
||
831 | */ |
||
832 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) |
||
833 | { |
||
834 | return hdma->ErrorCode; |
||
835 | } |
||
836 | |||
837 | /** |
||
838 | * @} |
||
839 | */ |
||
840 | |||
841 | /** |
||
842 | * @} |
||
843 | */ |
||
844 | |||
845 | /** @addtogroup DMA_Private_Functions |
||
846 | * @{ |
||
847 | */ |
||
848 | |||
849 | /** |
||
850 | * @brief Sets the DMA Transfer parameter. |
||
851 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||
852 | * the configuration information for the specified DMA Channel. |
||
853 | * @param SrcAddress: The source memory Buffer address |
||
854 | * @param DstAddress: The destination memory Buffer address |
||
855 | * @param DataLength: The length of data to be transferred from source to destination |
||
856 | * @retval HAL status |
||
857 | */ |
||
858 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||
859 | { |
||
860 | /* Clear all flags */ |
||
861 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||
862 | |||
863 | /* Configure DMA Channel data length */ |
||
864 | hdma->Instance->CNDTR = DataLength; |
||
865 | |||
866 | /* Memory to Peripheral */ |
||
867 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) |
||
868 | { |
||
869 | /* Configure DMA Channel destination address */ |
||
870 | hdma->Instance->CPAR = DstAddress; |
||
871 | |||
872 | /* Configure DMA Channel source address */ |
||
873 | hdma->Instance->CMAR = SrcAddress; |
||
874 | } |
||
875 | /* Peripheral to Memory */ |
||
876 | else |
||
877 | { |
||
878 | /* Configure DMA Channel source address */ |
||
879 | hdma->Instance->CPAR = SrcAddress; |
||
880 | |||
881 | /* Configure DMA Channel destination address */ |
||
882 | hdma->Instance->CMAR = DstAddress; |
||
883 | } |
||
884 | } |
||
885 | |||
886 | /** |
||
887 | * @} |
||
888 | */ |
||
889 | |||
890 | #endif /* HAL_DMA_MODULE_ENABLED */ |
||
891 | /** |
||
892 | * @} |
||
893 | */ |
||
894 | |||
895 | /** |
||
896 | * @} |
||
897 | */ |
||
898 | |||
899 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |