Rev 2 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
||
| 3 | * @file stm32f1xx_hal_adc.c |
||
| 4 | * @author MCD Application Team |
||
| 5 | * @brief This file provides firmware functions to manage the following |
||
| 6 | * functionalities of the Analog to Digital Convertor (ADC) |
||
| 7 | * peripheral: |
||
| 8 | * + Initialization and de-initialization functions |
||
| 9 | * ++ Initialization and Configuration of ADC |
||
| 10 | * + Operation functions |
||
| 11 | * ++ Start, stop, get result of conversions of regular |
||
| 12 | * group, using 3 possible modes: polling, interruption or DMA. |
||
| 13 | * + Control functions |
||
| 14 | * ++ Channels configuration on regular group |
||
| 15 | * ++ Channels configuration on injected group |
||
| 16 | * ++ Analog Watchdog configuration |
||
| 17 | * + State functions |
||
| 18 | * ++ ADC state machine management |
||
| 19 | * ++ Interrupts and flags management |
||
| 20 | * Other functions (extended functions) are available in file |
||
| 21 | * "stm32f1xx_hal_adc_ex.c". |
||
| 22 | * |
||
| 23 | @verbatim |
||
| 24 | ============================================================================== |
||
| 25 | ##### ADC peripheral features ##### |
||
| 26 | ============================================================================== |
||
| 27 | [..] |
||
| 28 | (+) 12-bit resolution |
||
| 29 | |||
| 30 | (+) Interrupt generation at the end of regular conversion, end of injected |
||
| 31 | conversion, and in case of analog watchdog or overrun events. |
||
| 32 | |||
| 33 | (+) Single and continuous conversion modes. |
||
| 34 | |||
| 35 | (+) Scan mode for conversion of several channels sequentially. |
||
| 36 | |||
| 37 | (+) Data alignment with in-built data coherency. |
||
| 38 | |||
| 39 | (+) Programmable sampling time (channel wise) |
||
| 40 | |||
| 41 | (+) ADC conversion of regular group and injected group. |
||
| 42 | |||
| 43 | (+) External trigger (timer or EXTI) |
||
| 44 | for both regular and injected groups. |
||
| 45 | |||
| 46 | (+) DMA request generation for transfer of conversions data of regular group. |
||
| 47 | |||
| 48 | (+) Multimode Dual mode (available on devices with 2 ADCs or more). |
||
| 49 | |||
| 50 | (+) Configurable DMA data storage in Multimode Dual mode (available on devices |
||
| 51 | with 2 DCs or more). |
||
| 52 | |||
| 53 | (+) Configurable delay between conversions in Dual interleaved mode (available |
||
| 54 | on devices with 2 DCs or more). |
||
| 55 | |||
| 56 | (+) ADC calibration |
||
| 57 | |||
| 58 | (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
||
| 59 | slower speed. |
||
| 60 | |||
| 61 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
||
| 62 | Vdda or to an external voltage reference). |
||
| 63 | |||
| 64 | |||
| 65 | ##### How to use this driver ##### |
||
| 66 | ============================================================================== |
||
| 67 | [..] |
||
| 68 | |||
| 69 | *** Configuration of top level parameters related to ADC *** |
||
| 70 | ============================================================ |
||
| 71 | [..] |
||
| 72 | |||
| 73 | (#) Enable the ADC interface |
||
| 74 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
||
| 75 | Caution: On STM32F1, ADC clock frequency max is 14MHz (refer |
||
| 76 | to device datasheet). |
||
| 77 | Therefore, ADC clock prescaler must be configured in |
||
| 78 | function of ADC clock source frequency to remain below |
||
| 79 | this maximum frequency. |
||
| 80 | (++) One clock setting is mandatory: |
||
| 81 | ADC clock (core clock, also possibly conversion clock). |
||
| 82 | (+++) Example: |
||
| 83 | Into HAL_ADC_MspInit() (recommended code location) or with |
||
| 84 | other device clock parameters configuration: |
||
| 85 | (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit; |
||
| 86 | (+++) __ADC1_CLK_ENABLE(); |
||
| 87 | (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; |
||
| 88 | (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; |
||
| 89 | (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); |
||
| 90 | |||
| 91 | (#) ADC pins configuration |
||
| 92 | (++) Enable the clock for the ADC GPIOs |
||
| 93 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
||
| 94 | (++) Configure these ADC pins in analog mode |
||
| 95 | using function HAL_GPIO_Init() |
||
| 96 | |||
| 97 | (#) Optionally, in case of usage of ADC with interruptions: |
||
| 98 | (++) Configure the NVIC for ADC |
||
| 99 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
||
| 100 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
||
| 101 | into the function of corresponding ADC interruption vector |
||
| 102 | ADCx_IRQHandler(). |
||
| 103 | |||
| 104 | (#) Optionally, in case of usage of DMA: |
||
| 105 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
||
| 106 | using function HAL_DMA_Init(). |
||
| 107 | (++) Configure the NVIC for DMA |
||
| 108 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
||
| 109 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
||
| 110 | into the function of corresponding DMA interruption vector |
||
| 111 | DMAx_Channelx_IRQHandler(). |
||
| 112 | |||
| 113 | *** Configuration of ADC, groups regular/injected, channels parameters *** |
||
| 114 | ========================================================================== |
||
| 115 | [..] |
||
| 116 | |||
| 117 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
||
| 118 | and regular group parameters (conversion trigger, sequencer, ...) |
||
| 119 | using function HAL_ADC_Init(). |
||
| 120 | |||
| 121 | (#) Configure the channels for regular group parameters (channel number, |
||
| 122 | channel rank into sequencer, ..., into regular group) |
||
| 123 | using function HAL_ADC_ConfigChannel(). |
||
| 124 | |||
| 125 | (#) Optionally, configure the injected group parameters (conversion trigger, |
||
| 126 | sequencer, ..., of injected group) |
||
| 127 | and the channels for injected group parameters (channel number, |
||
| 128 | channel rank into sequencer, ..., into injected group) |
||
| 129 | using function HAL_ADCEx_InjectedConfigChannel(). |
||
| 130 | |||
| 131 | (#) Optionally, configure the analog watchdog parameters (channels |
||
| 132 | monitored, thresholds, ...) |
||
| 133 | using function HAL_ADC_AnalogWDGConfig(). |
||
| 134 | |||
| 135 | (#) Optionally, for devices with several ADC instances: configure the |
||
| 136 | multimode parameters |
||
| 137 | using function HAL_ADCEx_MultiModeConfigChannel(). |
||
| 138 | |||
| 139 | *** Execution of ADC conversions *** |
||
| 140 | ==================================== |
||
| 141 | [..] |
||
| 142 | |||
| 143 | (#) Optionally, perform an automatic ADC calibration to improve the |
||
| 144 | conversion accuracy |
||
| 145 | using function HAL_ADCEx_Calibration_Start(). |
||
| 146 | |||
| 147 | (#) ADC driver can be used among three modes: polling, interruption, |
||
| 148 | transfer by DMA. |
||
| 149 | |||
| 150 | (++) ADC conversion by polling: |
||
| 151 | (+++) Activate the ADC peripheral and start conversions |
||
| 152 | using function HAL_ADC_Start() |
||
| 153 | (+++) Wait for ADC conversion completion |
||
| 154 | using function HAL_ADC_PollForConversion() |
||
| 155 | (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) |
||
| 156 | (+++) Retrieve conversion results |
||
| 157 | using function HAL_ADC_GetValue() |
||
| 158 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
||
| 159 | (+++) Stop conversion and disable the ADC peripheral |
||
| 160 | using function HAL_ADC_Stop() |
||
| 161 | |||
| 162 | (++) ADC conversion by interruption: |
||
| 163 | (+++) Activate the ADC peripheral and start conversions |
||
| 164 | using function HAL_ADC_Start_IT() |
||
| 165 | (+++) Wait for ADC conversion completion by call of function |
||
| 166 | HAL_ADC_ConvCpltCallback() |
||
| 167 | (this function must be implemented in user program) |
||
| 168 | (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) |
||
| 169 | (+++) Retrieve conversion results |
||
| 170 | using function HAL_ADC_GetValue() |
||
| 171 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
||
| 172 | (+++) Stop conversion and disable the ADC peripheral |
||
| 173 | using function HAL_ADC_Stop_IT() |
||
| 174 | |||
| 175 | (++) ADC conversion with transfer by DMA: |
||
| 176 | (+++) Activate the ADC peripheral and start conversions |
||
| 177 | using function HAL_ADC_Start_DMA() |
||
| 178 | (+++) Wait for ADC conversion completion by call of function |
||
| 179 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
||
| 180 | (these functions must be implemented in user program) |
||
| 181 | (+++) Conversion results are automatically transferred by DMA into |
||
| 182 | destination variable address. |
||
| 183 | (+++) Stop conversion and disable the ADC peripheral |
||
| 184 | using function HAL_ADC_Stop_DMA() |
||
| 185 | |||
| 186 | (++) For devices with several ADCs: ADC multimode conversion |
||
| 187 | with transfer by DMA: |
||
| 188 | (+++) Activate the ADC peripheral (slave) and start conversions |
||
| 189 | using function HAL_ADC_Start() |
||
| 190 | (+++) Activate the ADC peripheral (master) and start conversions |
||
| 191 | using function HAL_ADCEx_MultiModeStart_DMA() |
||
| 192 | (+++) Wait for ADC conversion completion by call of function |
||
| 193 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
||
| 194 | (these functions must be implemented in user program) |
||
| 195 | (+++) Conversion results are automatically transferred by DMA into |
||
| 196 | destination variable address. |
||
| 197 | (+++) Stop conversion and disable the ADC peripheral (master) |
||
| 198 | using function HAL_ADCEx_MultiModeStop_DMA() |
||
| 199 | (+++) Stop conversion and disable the ADC peripheral (slave) |
||
| 200 | using function HAL_ADC_Stop_IT() |
||
| 201 | |||
| 202 | [..] |
||
| 203 | |||
| 204 | (@) Callback functions must be implemented in user program: |
||
| 205 | (+@) HAL_ADC_ErrorCallback() |
||
| 206 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
||
| 207 | (+@) HAL_ADC_ConvCpltCallback() |
||
| 208 | (+@) HAL_ADC_ConvHalfCpltCallback |
||
| 209 | (+@) HAL_ADCEx_InjectedConvCpltCallback() |
||
| 210 | |||
| 211 | *** Deinitialization of ADC *** |
||
| 212 | ============================================================ |
||
| 213 | [..] |
||
| 214 | |||
| 215 | (#) Disable the ADC interface |
||
| 216 | (++) ADC clock can be hard reset and disabled at RCC top level. |
||
| 217 | (++) Hard reset of ADC peripherals |
||
| 218 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
||
| 219 | (++) ADC clock disable |
||
| 220 | using the equivalent macro/functions as configuration step. |
||
| 221 | (+++) Example: |
||
| 222 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
||
| 223 | other device clock parameters configuration: |
||
| 224 | (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC |
||
| 225 | (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF |
||
| 226 | (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) |
||
| 227 | |||
| 228 | (#) ADC pins configuration |
||
| 229 | (++) Disable the clock for the ADC GPIOs |
||
| 230 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
||
| 231 | |||
| 232 | (#) Optionally, in case of usage of ADC with interruptions: |
||
| 233 | (++) Disable the NVIC for ADC |
||
| 234 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
||
| 235 | |||
| 236 | (#) Optionally, in case of usage of DMA: |
||
| 237 | (++) Deinitialize the DMA |
||
| 238 | using function HAL_DMA_Init(). |
||
| 239 | (++) Disable the NVIC for DMA |
||
| 240 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
||
| 241 | |||
| 242 | [..] |
||
| 243 | |||
| 244 | *** Callback registration *** |
||
| 245 | ============================================= |
||
| 246 | [..] |
||
| 247 | |||
| 248 | The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, |
||
| 249 | allows the user to configure dynamically the driver callbacks. |
||
| 250 | Use Functions @ref HAL_ADC_RegisterCallback() |
||
| 251 | to register an interrupt callback. |
||
| 252 | [..] |
||
| 253 | |||
| 254 | Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: |
||
| 255 | (+) ConvCpltCallback : ADC conversion complete callback |
||
| 256 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
||
| 257 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
||
| 258 | (+) ErrorCallback : ADC error callback |
||
| 259 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
||
| 260 | (+) MspInitCallback : ADC Msp Init callback |
||
| 261 | (+) MspDeInitCallback : ADC Msp DeInit callback |
||
| 262 | This function takes as parameters the HAL peripheral handle, the Callback ID |
||
| 263 | and a pointer to the user callback function. |
||
| 264 | [..] |
||
| 265 | |||
| 266 | Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default |
||
| 267 | weak function. |
||
| 268 | [..] |
||
| 269 | |||
| 270 | @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, |
||
| 271 | and the Callback ID. |
||
| 272 | This function allows to reset following callbacks: |
||
| 273 | (+) ConvCpltCallback : ADC conversion complete callback |
||
| 274 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
||
| 275 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
||
| 276 | (+) ErrorCallback : ADC error callback |
||
| 277 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
||
| 278 | (+) MspInitCallback : ADC Msp Init callback |
||
| 279 | (+) MspDeInitCallback : ADC Msp DeInit callback |
||
| 280 | [..] |
||
| 281 | |||
| 282 | By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET |
||
| 283 | all callbacks are set to the corresponding weak functions: |
||
| 284 | examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). |
||
| 285 | Exception done for MspInit and MspDeInit functions that are |
||
| 286 | reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when |
||
| 287 | these callbacks are null (not registered beforehand). |
||
| 288 | [..] |
||
| 289 | |||
| 290 | If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() |
||
| 291 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
||
| 292 | [..] |
||
| 293 | |||
| 294 | Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. |
||
| 295 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
||
| 296 | in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, |
||
| 297 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
||
| 298 | [..] |
||
| 299 | |||
| 300 | Then, the user first registers the MspInit/MspDeInit user callbacks |
||
| 301 | using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() |
||
| 302 | or @ref HAL_ADC_Init() function. |
||
| 303 | [..] |
||
| 304 | |||
| 305 | When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or |
||
| 306 | not defined, the callback registration feature is not available and all callbacks |
||
| 307 | are set to the corresponding weak functions. |
||
| 308 | |||
| 309 | @endverbatim |
||
| 310 | ****************************************************************************** |
||
| 311 | * @attention |
||
| 312 | * |
||
| 313 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||
| 314 | * All rights reserved.</center></h2> |
||
| 315 | * |
||
| 316 | * This software component is licensed by ST under BSD 3-Clause license, |
||
| 317 | * the "License"; You may not use this file except in compliance with the |
||
| 318 | * License. You may obtain a copy of the License at: |
||
| 319 | * opensource.org/licenses/BSD-3-Clause |
||
| 320 | * |
||
| 321 | ****************************************************************************** |
||
| 322 | */ |
||
| 323 | |||
| 324 | /* Includes ------------------------------------------------------------------*/ |
||
| 325 | #include "stm32f1xx_hal.h" |
||
| 326 | |||
| 327 | /** @addtogroup STM32F1xx_HAL_Driver |
||
| 328 | * @{ |
||
| 329 | */ |
||
| 330 | |||
| 331 | /** @defgroup ADC ADC |
||
| 332 | * @brief ADC HAL module driver |
||
| 333 | * @{ |
||
| 334 | */ |
||
| 335 | |||
| 336 | #ifdef HAL_ADC_MODULE_ENABLED |
||
| 337 | |||
| 338 | /* Private typedef -----------------------------------------------------------*/ |
||
| 339 | /* Private define ------------------------------------------------------------*/ |
||
| 340 | /** @defgroup ADC_Private_Constants ADC Private Constants |
||
| 341 | * @{ |
||
| 342 | */ |
||
| 343 | |||
| 344 | /* Timeout values for ADC enable and disable settling time. */ |
||
| 345 | /* Values defined to be higher than worst cases: low clocks freq, */ |
||
| 346 | /* maximum prescaler. */ |
||
| 347 | /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ |
||
| 348 | /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ |
||
| 349 | /* Unit: ms */ |
||
| 350 | #define ADC_ENABLE_TIMEOUT 2U |
||
| 351 | #define ADC_DISABLE_TIMEOUT 2U |
||
| 352 | |||
| 353 | /* Delay for ADC stabilization time. */ |
||
| 354 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
||
| 355 | /* Unit: us */ |
||
| 356 | #define ADC_STAB_DELAY_US 1U |
||
| 357 | |||
| 358 | /* Delay for temperature sensor stabilization time. */ |
||
| 359 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
||
| 360 | /* Unit: us */ |
||
| 361 | #define ADC_TEMPSENSOR_DELAY_US 10U |
||
| 362 | |||
| 363 | /** |
||
| 364 | * @} |
||
| 365 | */ |
||
| 366 | |||
| 367 | /* Private macro -------------------------------------------------------------*/ |
||
| 368 | /* Private variables ---------------------------------------------------------*/ |
||
| 369 | /* Private function prototypes -----------------------------------------------*/ |
||
| 370 | /** @defgroup ADC_Private_Functions ADC Private Functions |
||
| 371 | * @{ |
||
| 372 | */ |
||
| 373 | /** |
||
| 374 | * @} |
||
| 375 | */ |
||
| 376 | |||
| 377 | /* Exported functions --------------------------------------------------------*/ |
||
| 378 | |||
| 379 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
||
| 380 | * @{ |
||
| 381 | */ |
||
| 382 | |||
| 383 | /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions |
||
| 384 | * @brief Initialization and Configuration functions |
||
| 385 | * |
||
| 386 | @verbatim |
||
| 387 | =============================================================================== |
||
| 388 | ##### Initialization and de-initialization functions ##### |
||
| 389 | =============================================================================== |
||
| 390 | [..] This section provides functions allowing to: |
||
| 391 | (+) Initialize and configure the ADC. |
||
| 392 | (+) De-initialize the ADC. |
||
| 393 | |||
| 394 | @endverbatim |
||
| 395 | * @{ |
||
| 396 | */ |
||
| 397 | |||
| 398 | /** |
||
| 399 | * @brief Initializes the ADC peripheral and regular group according to |
||
| 400 | * parameters specified in structure "ADC_InitTypeDef". |
||
| 401 | * @note As prerequisite, ADC clock must be configured at RCC top level |
||
| 402 | * (clock source APB2). |
||
| 403 | * See commented example code below that can be copied and uncommented |
||
| 404 | * into HAL_ADC_MspInit(). |
||
| 405 | * @note Possibility to update parameters on the fly: |
||
| 406 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
||
| 407 | * coming from ADC state reset. Following calls to this function can |
||
| 408 | * be used to reconfigure some parameters of ADC_InitTypeDef |
||
| 409 | * structure on the fly, without modifying MSP configuration. If ADC |
||
| 410 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
||
| 411 | * before HAL_ADC_Init(). |
||
| 412 | * The setting of these parameters is conditioned to ADC state. |
||
| 413 | * For parameters constraints, see comments of structure |
||
| 414 | * "ADC_InitTypeDef". |
||
| 415 | * @note This function configures the ADC within 2 scopes: scope of entire |
||
| 416 | * ADC and scope of regular group. For parameters details, see comments |
||
| 417 | * of structure "ADC_InitTypeDef". |
||
| 418 | * @param hadc: ADC handle |
||
| 419 | * @retval HAL status |
||
| 420 | */ |
||
| 421 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
||
| 422 | { |
||
| 423 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 424 | uint32_t tmp_cr1 = 0U; |
||
| 425 | uint32_t tmp_cr2 = 0U; |
||
| 426 | uint32_t tmp_sqr1 = 0U; |
||
| 427 | |||
| 428 | /* Check ADC handle */ |
||
| 429 | if(hadc == NULL) |
||
| 430 | { |
||
| 431 | return HAL_ERROR; |
||
| 432 | } |
||
| 433 | |||
| 434 | /* Check the parameters */ |
||
| 435 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 436 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
||
| 437 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
||
| 438 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
||
| 439 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
||
| 440 | |||
| 441 | if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) |
||
| 442 | { |
||
| 443 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
||
| 444 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
||
| 445 | if(hadc->Init.DiscontinuousConvMode != DISABLE) |
||
| 446 | { |
||
| 447 | assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); |
||
| 448 | } |
||
| 449 | } |
||
| 450 | |||
| 451 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
||
| 452 | /* at RCC top level. */ |
||
| 453 | /* Refer to header of this file for more details on clock enabling */ |
||
| 454 | /* procedure. */ |
||
| 455 | |||
| 456 | /* Actions performed only if ADC is coming from state reset: */ |
||
| 457 | /* - Initialization of ADC MSP */ |
||
| 458 | if (hadc->State == HAL_ADC_STATE_RESET) |
||
| 459 | { |
||
| 460 | /* Initialize ADC error code */ |
||
| 461 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 462 | |||
| 463 | /* Allocate lock resource and initialize it */ |
||
| 464 | hadc->Lock = HAL_UNLOCKED; |
||
| 465 | |||
| 466 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 467 | /* Init the ADC Callback settings */ |
||
| 468 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ |
||
| 469 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ |
||
| 470 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ |
||
| 471 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ |
||
| 472 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ |
||
| 473 | |||
| 474 | if (hadc->MspInitCallback == NULL) |
||
| 475 | { |
||
| 476 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
| 477 | } |
||
| 478 | |||
| 479 | /* Init the low level hardware */ |
||
| 480 | hadc->MspInitCallback(hadc); |
||
| 481 | #else |
||
| 482 | /* Init the low level hardware */ |
||
| 483 | HAL_ADC_MspInit(hadc); |
||
| 484 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 485 | } |
||
| 486 | |||
| 487 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 488 | /* Disable ADC peripheral */ |
||
| 489 | /* Note: In case of ADC already enabled, precaution to not launch an */ |
||
| 490 | /* unwanted conversion while modifying register CR2 by writing 1 to */ |
||
| 491 | /* bit ADON. */ |
||
| 492 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 493 | |||
| 494 | |||
| 495 | /* Configuration of ADC parameters if previous preliminary actions are */ |
||
| 496 | /* correctly completed. */ |
||
| 497 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && |
||
| 498 | (tmp_hal_status == HAL_OK) ) |
||
| 499 | { |
||
| 500 | /* Set ADC state */ |
||
| 501 | ADC_STATE_CLR_SET(hadc->State, |
||
| 502 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
| 503 | HAL_ADC_STATE_BUSY_INTERNAL); |
||
| 504 | |||
| 505 | /* Set ADC parameters */ |
||
| 506 | |||
| 507 | /* Configuration of ADC: */ |
||
| 508 | /* - data alignment */ |
||
| 509 | /* - external trigger to start conversion */ |
||
| 510 | /* - external trigger polarity (always set to 1, because needed for all */ |
||
| 511 | /* triggers: external trigger of SW start) */ |
||
| 512 | /* - continuous conversion mode */ |
||
| 513 | /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ |
||
| 514 | /* HAL_ADC_Start_xxx functions because if set in this function, */ |
||
| 515 | /* a conversion on injected group would start a conversion also on */ |
||
| 516 | /* regular group after ADC enabling. */ |
||
| 517 | tmp_cr2 |= (hadc->Init.DataAlign | |
||
| 518 | ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | |
||
| 519 | ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); |
||
| 520 | |||
| 521 | /* Configuration of ADC: */ |
||
| 522 | /* - scan mode */ |
||
| 523 | /* - discontinuous mode disable/enable */ |
||
| 524 | /* - discontinuous mode number of conversions */ |
||
| 525 | tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); |
||
| 526 | |||
| 527 | /* Enable discontinuous mode only if continuous mode is disabled */ |
||
| 528 | /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ |
||
| 529 | /* discontinuous is set anyway, but will have no effect on ADC HW. */ |
||
| 530 | if (hadc->Init.DiscontinuousConvMode == ENABLE) |
||
| 531 | { |
||
| 532 | if (hadc->Init.ContinuousConvMode == DISABLE) |
||
| 533 | { |
||
| 534 | /* Enable the selected ADC regular discontinuous mode */ |
||
| 535 | /* Set the number of channels to be converted in discontinuous mode */ |
||
| 536 | SET_BIT(tmp_cr1, ADC_CR1_DISCEN | |
||
| 537 | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); |
||
| 538 | } |
||
| 539 | else |
||
| 540 | { |
||
| 541 | /* ADC regular group settings continuous and sequencer discontinuous*/ |
||
| 542 | /* cannot be enabled simultaneously. */ |
||
| 543 | |||
| 544 | /* Update ADC state machine to error */ |
||
| 545 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
| 546 | |||
| 547 | /* Set ADC error code to ADC IP internal error */ |
||
| 548 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
| 549 | } |
||
| 550 | } |
||
| 551 | |||
| 552 | /* Update ADC configuration register CR1 with previous settings */ |
||
| 553 | MODIFY_REG(hadc->Instance->CR1, |
||
| 554 | ADC_CR1_SCAN | |
||
| 555 | ADC_CR1_DISCEN | |
||
| 556 | ADC_CR1_DISCNUM , |
||
| 557 | tmp_cr1 ); |
||
| 558 | |||
| 559 | /* Update ADC configuration register CR2 with previous settings */ |
||
| 560 | MODIFY_REG(hadc->Instance->CR2, |
||
| 561 | ADC_CR2_ALIGN | |
||
| 562 | ADC_CR2_EXTSEL | |
||
| 563 | ADC_CR2_EXTTRIG | |
||
| 564 | ADC_CR2_CONT , |
||
| 565 | tmp_cr2 ); |
||
| 566 | |||
| 567 | /* Configuration of regular group sequencer: */ |
||
| 568 | /* - if scan mode is disabled, regular channels sequence length is set to */ |
||
| 569 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
||
| 570 | /* Parameter "NbrOfConversion" is discarded. */ |
||
| 571 | /* Note: Scan mode is present by hardware on this device and, if */ |
||
| 572 | /* disabled, discards automatically nb of conversions. Anyway, nb of */ |
||
| 573 | /* conversions is forced to 0x00 for alignment over all STM32 devices. */ |
||
| 574 | /* - if scan mode is enabled, regular channels sequence length is set to */ |
||
| 575 | /* parameter "NbrOfConversion" */ |
||
| 576 | if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) |
||
| 577 | { |
||
| 578 | tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); |
||
| 579 | } |
||
| 580 | |||
| 581 | MODIFY_REG(hadc->Instance->SQR1, |
||
| 582 | ADC_SQR1_L , |
||
| 583 | tmp_sqr1 ); |
||
| 584 | |||
| 585 | /* Check back that ADC registers have effectively been configured to */ |
||
| 586 | /* ensure of no potential problem of ADC core IP clocking. */ |
||
| 587 | /* Check through register CR2 (excluding bits set in other functions: */ |
||
| 588 | /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ |
||
| 589 | /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ |
||
| 590 | /* measurement path bit (TSVREFE). */ |
||
| 591 | if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | |
||
| 592 | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | |
||
| 593 | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | |
||
| 594 | ADC_CR2_TSVREFE )) |
||
| 595 | == tmp_cr2) |
||
| 596 | { |
||
| 597 | /* Set ADC error code to none */ |
||
| 598 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 599 | |||
| 600 | /* Set the ADC state */ |
||
| 601 | ADC_STATE_CLR_SET(hadc->State, |
||
| 602 | HAL_ADC_STATE_BUSY_INTERNAL, |
||
| 603 | HAL_ADC_STATE_READY); |
||
| 604 | } |
||
| 605 | else |
||
| 606 | { |
||
| 607 | /* Update ADC state machine to error */ |
||
| 608 | ADC_STATE_CLR_SET(hadc->State, |
||
| 609 | HAL_ADC_STATE_BUSY_INTERNAL, |
||
| 610 | HAL_ADC_STATE_ERROR_INTERNAL); |
||
| 611 | |||
| 612 | /* Set ADC error code to ADC IP internal error */ |
||
| 613 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
| 614 | |||
| 615 | tmp_hal_status = HAL_ERROR; |
||
| 616 | } |
||
| 617 | |||
| 618 | } |
||
| 619 | else |
||
| 620 | { |
||
| 621 | /* Update ADC state machine to error */ |
||
| 622 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
| 623 | |||
| 624 | tmp_hal_status = HAL_ERROR; |
||
| 625 | } |
||
| 626 | |||
| 627 | /* Return function status */ |
||
| 628 | return tmp_hal_status; |
||
| 629 | } |
||
| 630 | |||
| 631 | /** |
||
| 632 | * @brief Deinitialize the ADC peripheral registers to their default reset |
||
| 633 | * values, with deinitialization of the ADC MSP. |
||
| 634 | * If needed, the example code can be copied and uncommented into |
||
| 635 | * function HAL_ADC_MspDeInit(). |
||
| 636 | * @param hadc: ADC handle |
||
| 637 | * @retval HAL status |
||
| 638 | */ |
||
| 639 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
||
| 640 | { |
||
| 641 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 642 | |||
| 643 | /* Check ADC handle */ |
||
| 644 | if(hadc == NULL) |
||
| 645 | { |
||
| 646 | return HAL_ERROR; |
||
| 647 | } |
||
| 648 | |||
| 649 | /* Check the parameters */ |
||
| 650 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 651 | |||
| 652 | /* Set ADC state */ |
||
| 653 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
||
| 654 | |||
| 655 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 656 | /* Disable ADC peripheral */ |
||
| 657 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 658 | |||
| 659 | |||
| 660 | /* Configuration of ADC parameters if previous preliminary actions are */ |
||
| 661 | /* correctly completed. */ |
||
| 662 | if (tmp_hal_status == HAL_OK) |
||
| 663 | { |
||
| 664 | /* ========== Reset ADC registers ========== */ |
||
| 665 | |||
| 666 | |||
| 667 | |||
| 668 | |||
| 669 | /* Reset register SR */ |
||
| 670 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | |
||
| 671 | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); |
||
| 672 | |||
| 673 | /* Reset register CR1 */ |
||
| 674 | CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | |
||
| 675 | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | |
||
| 676 | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | |
||
| 677 | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )); |
||
| 678 | |||
| 679 | /* Reset register CR2 */ |
||
| 680 | CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | |
||
| 681 | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | |
||
| 682 | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA | |
||
| 683 | ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | |
||
| 684 | ADC_CR2_ADON )); |
||
| 685 | |||
| 686 | /* Reset register SMPR1 */ |
||
| 687 | CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | |
||
| 688 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | |
||
| 689 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 )); |
||
| 690 | |||
| 691 | /* Reset register SMPR2 */ |
||
| 692 | CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | |
||
| 693 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | |
||
| 694 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | |
||
| 695 | ADC_SMPR2_SMP0 )); |
||
| 696 | |||
| 697 | /* Reset register JOFR1 */ |
||
| 698 | CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); |
||
| 699 | /* Reset register JOFR2 */ |
||
| 700 | CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); |
||
| 701 | /* Reset register JOFR3 */ |
||
| 702 | CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); |
||
| 703 | /* Reset register JOFR4 */ |
||
| 704 | CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); |
||
| 705 | |||
| 706 | /* Reset register HTR */ |
||
| 707 | CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); |
||
| 708 | /* Reset register LTR */ |
||
| 709 | CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); |
||
| 710 | |||
| 711 | /* Reset register SQR1 */ |
||
| 712 | CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | |
||
| 713 | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | |
||
| 714 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); |
||
| 715 | |||
| 716 | /* Reset register SQR1 */ |
||
| 717 | CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | |
||
| 718 | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | |
||
| 719 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); |
||
| 720 | |||
| 721 | /* Reset register SQR2 */ |
||
| 722 | CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | |
||
| 723 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 ); |
||
| 724 | |||
| 725 | /* Reset register SQR3 */ |
||
| 726 | CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | |
||
| 727 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 ); |
||
| 728 | |||
| 729 | /* Reset register JSQR */ |
||
| 730 | CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | |
||
| 731 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
||
| 732 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); |
||
| 733 | |||
| 734 | /* Reset register JSQR */ |
||
| 735 | CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | |
||
| 736 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
||
| 737 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); |
||
| 738 | |||
| 739 | /* Reset register DR */ |
||
| 740 | /* bits in access mode read only, no direct reset applicable*/ |
||
| 741 | |||
| 742 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
||
| 743 | /* bits in access mode read only, no direct reset applicable*/ |
||
| 744 | |||
| 745 | /* ========== Hard reset ADC peripheral ========== */ |
||
| 746 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
||
| 747 | /* forced to a similar state after device power-on. */ |
||
| 748 | /* If needed, copy-paste and uncomment the following reset code into */ |
||
| 749 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
||
| 750 | /* */ |
||
| 751 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
||
| 752 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
||
| 753 | |||
| 754 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 755 | if (hadc->MspDeInitCallback == NULL) |
||
| 756 | { |
||
| 757 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
| 758 | } |
||
| 759 | |||
| 760 | /* DeInit the low level hardware */ |
||
| 761 | hadc->MspDeInitCallback(hadc); |
||
| 762 | #else |
||
| 763 | /* DeInit the low level hardware */ |
||
| 764 | HAL_ADC_MspDeInit(hadc); |
||
| 765 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 766 | |||
| 767 | /* Set ADC error code to none */ |
||
| 768 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 769 | |||
| 770 | /* Set ADC state */ |
||
| 771 | hadc->State = HAL_ADC_STATE_RESET; |
||
| 772 | |||
| 773 | } |
||
| 774 | |||
| 775 | /* Process unlocked */ |
||
| 776 | __HAL_UNLOCK(hadc); |
||
| 777 | |||
| 778 | /* Return function status */ |
||
| 779 | return tmp_hal_status; |
||
| 780 | } |
||
| 781 | |||
| 782 | /** |
||
| 783 | * @brief Initializes the ADC MSP. |
||
| 784 | * @param hadc: ADC handle |
||
| 785 | * @retval None |
||
| 786 | */ |
||
| 787 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
||
| 788 | { |
||
| 789 | /* Prevent unused argument(s) compilation warning */ |
||
| 790 | UNUSED(hadc); |
||
| 791 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 792 | function HAL_ADC_MspInit must be implemented in the user file. |
||
| 793 | */ |
||
| 794 | } |
||
| 795 | |||
| 796 | /** |
||
| 797 | * @brief DeInitializes the ADC MSP. |
||
| 798 | * @param hadc: ADC handle |
||
| 799 | * @retval None |
||
| 800 | */ |
||
| 801 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
||
| 802 | { |
||
| 803 | /* Prevent unused argument(s) compilation warning */ |
||
| 804 | UNUSED(hadc); |
||
| 805 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 806 | function HAL_ADC_MspDeInit must be implemented in the user file. |
||
| 807 | */ |
||
| 808 | } |
||
| 809 | |||
| 810 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 811 | /** |
||
| 812 | * @brief Register a User ADC Callback |
||
| 813 | * To be used instead of the weak predefined callback |
||
| 814 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
||
| 815 | * the configuration information for the specified ADC. |
||
| 816 | * @param CallbackID ID of the callback to be registered |
||
| 817 | * This parameter can be one of the following values: |
||
| 818 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
||
| 819 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
||
| 820 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
||
| 821 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
||
| 822 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
||
| 823 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
||
| 824 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
||
| 825 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
||
| 826 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
||
| 827 | * @param pCallback pointer to the Callback function |
||
| 828 | * @retval HAL status |
||
| 829 | */ |
||
| 830 | HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) |
||
| 831 | { |
||
| 832 | HAL_StatusTypeDef status = HAL_OK; |
||
| 833 | |||
| 834 | if (pCallback == NULL) |
||
| 835 | { |
||
| 836 | /* Update the error code */ |
||
| 837 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 838 | |||
| 839 | return HAL_ERROR; |
||
| 840 | } |
||
| 841 | |||
| 842 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
||
| 843 | { |
||
| 844 | switch (CallbackID) |
||
| 845 | { |
||
| 846 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
||
| 847 | hadc->ConvCpltCallback = pCallback; |
||
| 848 | break; |
||
| 849 | |||
| 850 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
||
| 851 | hadc->ConvHalfCpltCallback = pCallback; |
||
| 852 | break; |
||
| 853 | |||
| 854 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
||
| 855 | hadc->LevelOutOfWindowCallback = pCallback; |
||
| 856 | break; |
||
| 857 | |||
| 858 | case HAL_ADC_ERROR_CB_ID : |
||
| 859 | hadc->ErrorCallback = pCallback; |
||
| 860 | break; |
||
| 861 | |||
| 862 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
||
| 863 | hadc->InjectedConvCpltCallback = pCallback; |
||
| 864 | break; |
||
| 865 | |||
| 866 | case HAL_ADC_MSPINIT_CB_ID : |
||
| 867 | hadc->MspInitCallback = pCallback; |
||
| 868 | break; |
||
| 869 | |||
| 870 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
| 871 | hadc->MspDeInitCallback = pCallback; |
||
| 872 | break; |
||
| 873 | |||
| 874 | default : |
||
| 875 | /* Update the error code */ |
||
| 876 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 877 | |||
| 878 | /* Return error status */ |
||
| 879 | status = HAL_ERROR; |
||
| 880 | break; |
||
| 881 | } |
||
| 882 | } |
||
| 883 | else if (HAL_ADC_STATE_RESET == hadc->State) |
||
| 884 | { |
||
| 885 | switch (CallbackID) |
||
| 886 | { |
||
| 887 | case HAL_ADC_MSPINIT_CB_ID : |
||
| 888 | hadc->MspInitCallback = pCallback; |
||
| 889 | break; |
||
| 890 | |||
| 891 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
| 892 | hadc->MspDeInitCallback = pCallback; |
||
| 893 | break; |
||
| 894 | |||
| 895 | default : |
||
| 896 | /* Update the error code */ |
||
| 897 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 898 | |||
| 899 | /* Return error status */ |
||
| 900 | status = HAL_ERROR; |
||
| 901 | break; |
||
| 902 | } |
||
| 903 | } |
||
| 904 | else |
||
| 905 | { |
||
| 906 | /* Update the error code */ |
||
| 907 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 908 | |||
| 909 | /* Return error status */ |
||
| 910 | status = HAL_ERROR; |
||
| 911 | } |
||
| 912 | |||
| 913 | return status; |
||
| 914 | } |
||
| 915 | |||
| 916 | /** |
||
| 917 | * @brief Unregister a ADC Callback |
||
| 918 | * ADC callback is redirected to the weak predefined callback |
||
| 919 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
||
| 920 | * the configuration information for the specified ADC. |
||
| 921 | * @param CallbackID ID of the callback to be unregistered |
||
| 922 | * This parameter can be one of the following values: |
||
| 923 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
||
| 924 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
||
| 925 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
||
| 926 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
||
| 927 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
||
| 928 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
||
| 929 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
||
| 930 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
||
| 931 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
||
| 932 | * @retval HAL status |
||
| 933 | */ |
||
| 934 | HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) |
||
| 935 | { |
||
| 936 | HAL_StatusTypeDef status = HAL_OK; |
||
| 937 | |||
| 938 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
||
| 939 | { |
||
| 940 | switch (CallbackID) |
||
| 941 | { |
||
| 942 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
||
| 943 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; |
||
| 944 | break; |
||
| 945 | |||
| 946 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
||
| 947 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; |
||
| 948 | break; |
||
| 949 | |||
| 950 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
||
| 951 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; |
||
| 952 | break; |
||
| 953 | |||
| 954 | case HAL_ADC_ERROR_CB_ID : |
||
| 955 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; |
||
| 956 | break; |
||
| 957 | |||
| 958 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
||
| 959 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; |
||
| 960 | break; |
||
| 961 | |||
| 962 | case HAL_ADC_MSPINIT_CB_ID : |
||
| 963 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
| 964 | break; |
||
| 965 | |||
| 966 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
| 967 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
| 968 | break; |
||
| 969 | |||
| 970 | default : |
||
| 971 | /* Update the error code */ |
||
| 972 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 973 | |||
| 974 | /* Return error status */ |
||
| 975 | status = HAL_ERROR; |
||
| 976 | break; |
||
| 977 | } |
||
| 978 | } |
||
| 979 | else if (HAL_ADC_STATE_RESET == hadc->State) |
||
| 980 | { |
||
| 981 | switch (CallbackID) |
||
| 982 | { |
||
| 983 | case HAL_ADC_MSPINIT_CB_ID : |
||
| 984 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
| 985 | break; |
||
| 986 | |||
| 987 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
| 988 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
| 989 | break; |
||
| 990 | |||
| 991 | default : |
||
| 992 | /* Update the error code */ |
||
| 993 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 994 | |||
| 995 | /* Return error status */ |
||
| 996 | status = HAL_ERROR; |
||
| 997 | break; |
||
| 998 | } |
||
| 999 | } |
||
| 1000 | else |
||
| 1001 | { |
||
| 1002 | /* Update the error code */ |
||
| 1003 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 1004 | |||
| 1005 | /* Return error status */ |
||
| 1006 | status = HAL_ERROR; |
||
| 1007 | } |
||
| 1008 | |||
| 1009 | return status; |
||
| 1010 | } |
||
| 1011 | |||
| 1012 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 1013 | |||
| 1014 | /** |
||
| 1015 | * @} |
||
| 1016 | */ |
||
| 1017 | |||
| 1018 | /** @defgroup ADC_Exported_Functions_Group2 IO operation functions |
||
| 1019 | * @brief Input and Output operation functions |
||
| 1020 | * |
||
| 1021 | @verbatim |
||
| 1022 | =============================================================================== |
||
| 1023 | ##### IO operation functions ##### |
||
| 1024 | =============================================================================== |
||
| 1025 | [..] This section provides functions allowing to: |
||
| 1026 | (+) Start conversion of regular group. |
||
| 1027 | (+) Stop conversion of regular group. |
||
| 1028 | (+) Poll for conversion complete on regular group. |
||
| 1029 | (+) Poll for conversion event. |
||
| 1030 | (+) Get result of regular channel conversion. |
||
| 1031 | (+) Start conversion of regular group and enable interruptions. |
||
| 1032 | (+) Stop conversion of regular group and disable interruptions. |
||
| 1033 | (+) Handle ADC interrupt request |
||
| 1034 | (+) Start conversion of regular group and enable DMA transfer. |
||
| 1035 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
||
| 1036 | @endverbatim |
||
| 1037 | * @{ |
||
| 1038 | */ |
||
| 1039 | |||
| 1040 | /** |
||
| 1041 | * @brief Enables ADC, starts conversion of regular group. |
||
| 1042 | * Interruptions enabled in this function: None. |
||
| 1043 | * @param hadc: ADC handle |
||
| 1044 | * @retval HAL status |
||
| 1045 | */ |
||
| 1046 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
||
| 1047 | { |
||
| 1048 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1049 | |||
| 1050 | /* Check the parameters */ |
||
| 1051 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1052 | |||
| 1053 | /* Process locked */ |
||
| 1054 | __HAL_LOCK(hadc); |
||
| 1055 | |||
| 1056 | /* Enable the ADC peripheral */ |
||
| 1057 | tmp_hal_status = ADC_Enable(hadc); |
||
| 1058 | |||
| 1059 | /* Start conversion if ADC is effectively enabled */ |
||
| 1060 | if (tmp_hal_status == HAL_OK) |
||
| 1061 | { |
||
| 1062 | /* Set ADC state */ |
||
| 1063 | /* - Clear state bitfield related to regular group conversion results */ |
||
| 1064 | /* - Set state bitfield related to regular operation */ |
||
| 1065 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1066 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, |
||
| 1067 | HAL_ADC_STATE_REG_BUSY); |
||
| 1068 | |||
| 1069 | /* Set group injected state (from auto-injection) and multimode state */ |
||
| 1070 | /* for all cases of multimode: independent mode, multimode ADC master */ |
||
| 1071 | /* or multimode ADC slave (for devices with several ADCs): */ |
||
| 1072 | if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) |
||
| 1073 | { |
||
| 1074 | /* Set ADC state (ADC independent or master) */ |
||
| 1075 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
||
| 1076 | |||
| 1077 | /* If conversions on group regular are also triggering group injected, */ |
||
| 1078 | /* update ADC state. */ |
||
| 1079 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
||
| 1080 | { |
||
| 1081 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
| 1082 | } |
||
| 1083 | } |
||
| 1084 | else |
||
| 1085 | { |
||
| 1086 | /* Set ADC state (ADC slave) */ |
||
| 1087 | SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
||
| 1088 | |||
| 1089 | /* If conversions on group regular are also triggering group injected, */ |
||
| 1090 | /* update ADC state. */ |
||
| 1091 | if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) |
||
| 1092 | { |
||
| 1093 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
| 1094 | } |
||
| 1095 | } |
||
| 1096 | |||
| 1097 | /* State machine update: Check if an injected conversion is ongoing */ |
||
| 1098 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1099 | { |
||
| 1100 | /* Reset ADC error code fields related to conversions on group regular */ |
||
| 1101 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
||
| 1102 | } |
||
| 1103 | else |
||
| 1104 | { |
||
| 1105 | /* Reset ADC all error code fields */ |
||
| 1106 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 1107 | } |
||
| 1108 | |||
| 1109 | /* Process unlocked */ |
||
| 1110 | /* Unlock before starting ADC conversions: in case of potential */ |
||
| 1111 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
| 1112 | __HAL_UNLOCK(hadc); |
||
| 1113 | |||
| 1114 | /* Clear regular group conversion flag */ |
||
| 1115 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
||
| 1116 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); |
||
| 1117 | |||
| 1118 | /* Enable conversion of regular group. */ |
||
| 1119 | /* If software start has been selected, conversion starts immediately. */ |
||
| 1120 | /* If external trigger has been selected, conversion will start at next */ |
||
| 1121 | /* trigger event. */ |
||
| 1122 | /* Case of multimode enabled: */ |
||
| 1123 | /* - if ADC is slave, ADC is enabled only (conversion is not started). */ |
||
| 1124 | /* - if ADC is master, ADC is enabled and conversion is started. */ |
||
| 1125 | /* If ADC is master, ADC is enabled and conversion is started. */ |
||
| 1126 | /* Note: Alternate trigger for single conversion could be to force an */ |
||
| 1127 | /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ |
||
| 1128 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 1129 | ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) |
||
| 1130 | { |
||
| 1131 | /* Start ADC conversion on regular group with SW start */ |
||
| 1132 | SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); |
||
| 1133 | } |
||
| 1134 | else |
||
| 1135 | { |
||
| 1136 | /* Start ADC conversion on regular group with external trigger */ |
||
| 1137 | SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); |
||
| 1138 | } |
||
| 1139 | } |
||
| 1140 | else |
||
| 1141 | { |
||
| 1142 | /* Process unlocked */ |
||
| 1143 | __HAL_UNLOCK(hadc); |
||
| 1144 | } |
||
| 1145 | |||
| 1146 | /* Return function status */ |
||
| 1147 | return tmp_hal_status; |
||
| 1148 | } |
||
| 1149 | |||
| 1150 | /** |
||
| 1151 | * @brief Stop ADC conversion of regular group (and injected channels in |
||
| 1152 | * case of auto_injection mode), disable ADC peripheral. |
||
| 1153 | * @note: ADC peripheral disable is forcing stop of potential |
||
| 1154 | * conversion on injected group. If injected group is under use, it |
||
| 1155 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
||
| 1156 | * @param hadc: ADC handle |
||
| 1157 | * @retval HAL status. |
||
| 1158 | */ |
||
| 1159 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
||
| 1160 | { |
||
| 1161 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1162 | |||
| 1163 | /* Check the parameters */ |
||
| 1164 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1165 | |||
| 1166 | /* Process locked */ |
||
| 1167 | __HAL_LOCK(hadc); |
||
| 1168 | |||
| 1169 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 1170 | /* Disable ADC peripheral */ |
||
| 1171 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 1172 | |||
| 1173 | /* Check if ADC is effectively disabled */ |
||
| 1174 | if (tmp_hal_status == HAL_OK) |
||
| 1175 | { |
||
| 1176 | /* Set ADC state */ |
||
| 1177 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1178 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
| 1179 | HAL_ADC_STATE_READY); |
||
| 1180 | } |
||
| 1181 | |||
| 1182 | /* Process unlocked */ |
||
| 1183 | __HAL_UNLOCK(hadc); |
||
| 1184 | |||
| 1185 | /* Return function status */ |
||
| 1186 | return tmp_hal_status; |
||
| 1187 | } |
||
| 1188 | |||
| 1189 | /** |
||
| 1190 | * @brief Wait for regular group conversion to be completed. |
||
| 1191 | * @note This function cannot be used in a particular setup: ADC configured |
||
| 1192 | * in DMA mode. |
||
| 1193 | * In this case, DMA resets the flag EOC and polling cannot be |
||
| 1194 | * performed on each conversion. |
||
| 1195 | * @note On STM32F1 devices, limitation in case of sequencer enabled |
||
| 1196 | * (several ranks selected): polling cannot be done on each |
||
| 1197 | * conversion inside the sequence. In this case, polling is replaced by |
||
| 1198 | * wait for maximum conversion time. |
||
| 1199 | * @param hadc: ADC handle |
||
| 1200 | * @param Timeout: Timeout value in millisecond. |
||
| 1201 | * @retval HAL status |
||
| 1202 | */ |
||
| 1203 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
||
| 1204 | { |
||
| 1205 | uint32_t tickstart = 0U; |
||
| 1206 | |||
| 1207 | /* Variables for polling in case of scan mode enabled and polling for each */ |
||
| 1208 | /* conversion. */ |
||
| 1209 | __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; |
||
| 1210 | uint32_t Conversion_Timeout_CPU_cycles_max = 0U; |
||
| 1211 | |||
| 1212 | /* Check the parameters */ |
||
| 1213 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1214 | |||
| 1215 | /* Get tick count */ |
||
| 1216 | tickstart = HAL_GetTick(); |
||
| 1217 | |||
| 1218 | /* Verification that ADC configuration is compliant with polling for */ |
||
| 1219 | /* each conversion: */ |
||
| 1220 | /* Particular case is ADC configured in DMA mode */ |
||
| 1221 | if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) |
||
| 1222 | { |
||
| 1223 | /* Update ADC state machine to error */ |
||
| 1224 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
| 1225 | |||
| 1226 | /* Process unlocked */ |
||
| 1227 | __HAL_UNLOCK(hadc); |
||
| 1228 | |||
| 1229 | return HAL_ERROR; |
||
| 1230 | } |
||
| 1231 | |||
| 1232 | /* Polling for end of conversion: differentiation if single/sequence */ |
||
| 1233 | /* conversion. */ |
||
| 1234 | /* - If single conversion for regular group (Scan mode disabled or enabled */ |
||
| 1235 | /* with NbrOfConversion =1), flag EOC is used to determine the */ |
||
| 1236 | /* conversion completion. */ |
||
| 1237 | /* - If sequence conversion for regular group (scan mode enabled and */ |
||
| 1238 | /* NbrOfConversion >=2), flag EOC is set only at the end of the */ |
||
| 1239 | /* sequence. */ |
||
| 1240 | /* To poll for each conversion, the maximum conversion time is computed */ |
||
| 1241 | /* from ADC conversion time (selected sampling time + conversion time of */ |
||
| 1242 | /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ |
||
| 1243 | /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ |
||
| 1244 | /* As flag EOC is not set after each conversion, no timeout status can */ |
||
| 1245 | /* be set. */ |
||
| 1246 | if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && |
||
| 1247 | HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) |
||
| 1248 | { |
||
| 1249 | /* Wait until End of Conversion flag is raised */ |
||
| 1250 | while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
||
| 1251 | { |
||
| 1252 | /* Check if timeout is disabled (set to infinite wait) */ |
||
| 1253 | if(Timeout != HAL_MAX_DELAY) |
||
| 1254 | { |
||
| 1255 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) |
||
| 1256 | { |
||
| 1257 | /* Update ADC state machine to timeout */ |
||
| 1258 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
||
| 1259 | |||
| 1260 | /* Process unlocked */ |
||
| 1261 | __HAL_UNLOCK(hadc); |
||
| 1262 | |||
| 1263 | return HAL_TIMEOUT; |
||
| 1264 | } |
||
| 1265 | } |
||
| 1266 | } |
||
| 1267 | } |
||
| 1268 | else |
||
| 1269 | { |
||
| 1270 | /* Replace polling by wait for maximum conversion time */ |
||
| 1271 | /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ |
||
| 1272 | /* and ADC maximum conversion cycles on all channels. */ |
||
| 1273 | /* - Wait for the expected ADC clock cycles delay */ |
||
| 1274 | Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock |
||
| 1275 | / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) |
||
| 1276 | * ADC_CONVCYCLES_MAX_RANGE(hadc) ); |
||
| 1277 | |||
| 1278 | while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) |
||
| 1279 | { |
||
| 1280 | /* Check if timeout is disabled (set to infinite wait) */ |
||
| 1281 | if(Timeout != HAL_MAX_DELAY) |
||
| 1282 | { |
||
| 1283 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) |
||
| 1284 | { |
||
| 1285 | /* Update ADC state machine to timeout */ |
||
| 1286 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
||
| 1287 | |||
| 1288 | /* Process unlocked */ |
||
| 1289 | __HAL_UNLOCK(hadc); |
||
| 1290 | |||
| 1291 | return HAL_TIMEOUT; |
||
| 1292 | } |
||
| 1293 | } |
||
| 1294 | Conversion_Timeout_CPU_cycles ++; |
||
| 1295 | } |
||
| 1296 | } |
||
| 1297 | |||
| 1298 | /* Clear regular group conversion flag */ |
||
| 1299 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
||
| 1300 | |||
| 1301 | /* Update ADC state machine */ |
||
| 1302 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
| 1303 | |||
| 1304 | /* Determine whether any further conversion upcoming on group regular */ |
||
| 1305 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
| 1306 | /* Note: On STM32F1 devices, in case of sequencer enabled */ |
||
| 1307 | /* (several ranks selected), end of conversion flag is raised */ |
||
| 1308 | /* at the end of the sequence. */ |
||
| 1309 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 1310 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
||
| 1311 | { |
||
| 1312 | /* Set ADC state */ |
||
| 1313 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
||
| 1314 | |||
| 1315 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1316 | { |
||
| 1317 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
| 1318 | } |
||
| 1319 | } |
||
| 1320 | |||
| 1321 | /* Return ADC state */ |
||
| 1322 | return HAL_OK; |
||
| 1323 | } |
||
| 1324 | |||
| 1325 | /** |
||
| 1326 | * @brief Poll for conversion event. |
||
| 1327 | * @param hadc: ADC handle |
||
| 1328 | * @param EventType: the ADC event type. |
||
| 1329 | * This parameter can be one of the following values: |
||
| 1330 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event. |
||
| 1331 | * @param Timeout: Timeout value in millisecond. |
||
| 1332 | * @retval HAL status |
||
| 1333 | */ |
||
| 1334 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
||
| 1335 | { |
||
| 1336 | uint32_t tickstart = 0U; |
||
| 1337 | |||
| 1338 | /* Check the parameters */ |
||
| 1339 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1340 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
||
| 1341 | |||
| 1342 | /* Get tick count */ |
||
| 1343 | tickstart = HAL_GetTick(); |
||
| 1344 | |||
| 1345 | /* Check selected event flag */ |
||
| 1346 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
||
| 1347 | { |
||
| 1348 | /* Check if timeout is disabled (set to infinite wait) */ |
||
| 1349 | if(Timeout != HAL_MAX_DELAY) |
||
| 1350 | { |
||
| 1351 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) |
||
| 1352 | { |
||
| 1353 | /* Update ADC state machine to timeout */ |
||
| 1354 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
||
| 1355 | |||
| 1356 | /* Process unlocked */ |
||
| 1357 | __HAL_UNLOCK(hadc); |
||
| 1358 | |||
| 1359 | return HAL_TIMEOUT; |
||
| 1360 | } |
||
| 1361 | } |
||
| 1362 | } |
||
| 1363 | |||
| 1364 | /* Analog watchdog (level out of window) event */ |
||
| 1365 | /* Set ADC state */ |
||
| 1366 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
||
| 1367 | |||
| 1368 | /* Clear ADC analog watchdog flag */ |
||
| 1369 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
||
| 1370 | |||
| 1371 | /* Return ADC state */ |
||
| 1372 | return HAL_OK; |
||
| 1373 | } |
||
| 1374 | |||
| 1375 | /** |
||
| 1376 | * @brief Enables ADC, starts conversion of regular group with interruption. |
||
| 1377 | * Interruptions enabled in this function: |
||
| 1378 | * - EOC (end of conversion of regular group) |
||
| 1379 | * Each of these interruptions has its dedicated callback function. |
||
| 1380 | * @param hadc: ADC handle |
||
| 1381 | * @retval HAL status |
||
| 1382 | */ |
||
| 1383 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
||
| 1384 | { |
||
| 1385 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1386 | |||
| 1387 | /* Check the parameters */ |
||
| 1388 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1389 | |||
| 1390 | /* Process locked */ |
||
| 1391 | __HAL_LOCK(hadc); |
||
| 1392 | |||
| 1393 | /* Enable the ADC peripheral */ |
||
| 1394 | tmp_hal_status = ADC_Enable(hadc); |
||
| 1395 | |||
| 1396 | /* Start conversion if ADC is effectively enabled */ |
||
| 1397 | if (tmp_hal_status == HAL_OK) |
||
| 1398 | { |
||
| 1399 | /* Set ADC state */ |
||
| 1400 | /* - Clear state bitfield related to regular group conversion results */ |
||
| 1401 | /* - Set state bitfield related to regular operation */ |
||
| 1402 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1403 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
||
| 1404 | HAL_ADC_STATE_REG_BUSY); |
||
| 1405 | |||
| 1406 | /* Set group injected state (from auto-injection) and multimode state */ |
||
| 1407 | /* for all cases of multimode: independent mode, multimode ADC master */ |
||
| 1408 | /* or multimode ADC slave (for devices with several ADCs): */ |
||
| 1409 | if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) |
||
| 1410 | { |
||
| 1411 | /* Set ADC state (ADC independent or master) */ |
||
| 1412 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
||
| 1413 | |||
| 1414 | /* If conversions on group regular are also triggering group injected, */ |
||
| 1415 | /* update ADC state. */ |
||
| 1416 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
||
| 1417 | { |
||
| 1418 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
| 1419 | } |
||
| 1420 | } |
||
| 1421 | else |
||
| 1422 | { |
||
| 1423 | /* Set ADC state (ADC slave) */ |
||
| 1424 | SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
||
| 1425 | |||
| 1426 | /* If conversions on group regular are also triggering group injected, */ |
||
| 1427 | /* update ADC state. */ |
||
| 1428 | if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) |
||
| 1429 | { |
||
| 1430 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
| 1431 | } |
||
| 1432 | } |
||
| 1433 | |||
| 1434 | /* State machine update: Check if an injected conversion is ongoing */ |
||
| 1435 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1436 | { |
||
| 1437 | /* Reset ADC error code fields related to conversions on group regular */ |
||
| 1438 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
||
| 1439 | } |
||
| 1440 | else |
||
| 1441 | { |
||
| 1442 | /* Reset ADC all error code fields */ |
||
| 1443 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 1444 | } |
||
| 1445 | |||
| 1446 | /* Process unlocked */ |
||
| 1447 | /* Unlock before starting ADC conversions: in case of potential */ |
||
| 1448 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
| 1449 | __HAL_UNLOCK(hadc); |
||
| 1450 | |||
| 1451 | /* Clear regular group conversion flag and overrun flag */ |
||
| 1452 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
||
| 1453 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); |
||
| 1454 | |||
| 1455 | /* Enable end of conversion interrupt for regular group */ |
||
| 1456 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); |
||
| 1457 | |||
| 1458 | /* Enable conversion of regular group. */ |
||
| 1459 | /* If software start has been selected, conversion starts immediately. */ |
||
| 1460 | /* If external trigger has been selected, conversion will start at next */ |
||
| 1461 | /* trigger event. */ |
||
| 1462 | /* Case of multimode enabled: */ |
||
| 1463 | /* - if ADC is slave, ADC is enabled only (conversion is not started). */ |
||
| 1464 | /* - if ADC is master, ADC is enabled and conversion is started. */ |
||
| 1465 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 1466 | ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) |
||
| 1467 | { |
||
| 1468 | /* Start ADC conversion on regular group with SW start */ |
||
| 1469 | SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); |
||
| 1470 | } |
||
| 1471 | else |
||
| 1472 | { |
||
| 1473 | /* Start ADC conversion on regular group with external trigger */ |
||
| 1474 | SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); |
||
| 1475 | } |
||
| 1476 | } |
||
| 1477 | else |
||
| 1478 | { |
||
| 1479 | /* Process unlocked */ |
||
| 1480 | __HAL_UNLOCK(hadc); |
||
| 1481 | } |
||
| 1482 | |||
| 1483 | /* Return function status */ |
||
| 1484 | return tmp_hal_status; |
||
| 1485 | } |
||
| 1486 | |||
| 1487 | /** |
||
| 1488 | * @brief Stop ADC conversion of regular group (and injected group in |
||
| 1489 | * case of auto_injection mode), disable interrution of |
||
| 1490 | * end-of-conversion, disable ADC peripheral. |
||
| 1491 | * @param hadc: ADC handle |
||
| 1492 | * @retval None |
||
| 1493 | */ |
||
| 1494 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
||
| 1495 | { |
||
| 1496 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1497 | |||
| 1498 | /* Check the parameters */ |
||
| 1499 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1500 | |||
| 1501 | /* Process locked */ |
||
| 1502 | __HAL_LOCK(hadc); |
||
| 1503 | |||
| 1504 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 1505 | /* Disable ADC peripheral */ |
||
| 1506 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 1507 | |||
| 1508 | /* Check if ADC is effectively disabled */ |
||
| 1509 | if (tmp_hal_status == HAL_OK) |
||
| 1510 | { |
||
| 1511 | /* Disable ADC end of conversion interrupt for regular group */ |
||
| 1512 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
||
| 1513 | |||
| 1514 | /* Set ADC state */ |
||
| 1515 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1516 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
| 1517 | HAL_ADC_STATE_READY); |
||
| 1518 | } |
||
| 1519 | |||
| 1520 | /* Process unlocked */ |
||
| 1521 | __HAL_UNLOCK(hadc); |
||
| 1522 | |||
| 1523 | /* Return function status */ |
||
| 1524 | return tmp_hal_status; |
||
| 1525 | } |
||
| 1526 | |||
| 1527 | /** |
||
| 1528 | * @brief Enables ADC, starts conversion of regular group and transfers result |
||
| 1529 | * through DMA. |
||
| 1530 | * Interruptions enabled in this function: |
||
| 1531 | * - DMA transfer complete |
||
| 1532 | * - DMA half transfer |
||
| 1533 | * Each of these interruptions has its dedicated callback function. |
||
| 1534 | * @note For devices with several ADCs: This function is for single-ADC mode |
||
| 1535 | * only. For multimode, use the dedicated MultimodeStart function. |
||
| 1536 | * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending |
||
| 1537 | * on devices) have DMA capability. |
||
| 1538 | * ADC2 converted data can be transferred in dual ADC mode using DMA |
||
| 1539 | * of ADC1 (ADC master in multimode). |
||
| 1540 | * In case of using ADC1 with DMA on a device featuring 2 ADC |
||
| 1541 | * instances: ADC1 conversion register DR contains ADC1 conversion |
||
| 1542 | * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last |
||
| 1543 | * conversion result (ADC1 register DR bits 16 to 27). Therefore, to |
||
| 1544 | * have DMA transferring the conversion results of ADC1 only, DMA must |
||
| 1545 | * be configured to transfer size: half word. |
||
| 1546 | * @param hadc: ADC handle |
||
| 1547 | * @param pData: The destination Buffer address. |
||
| 1548 | * @param Length: The length of data to be transferred from ADC peripheral to memory. |
||
| 1549 | * @retval None |
||
| 1550 | */ |
||
| 1551 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
||
| 1552 | { |
||
| 1553 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1554 | |||
| 1555 | /* Check the parameters */ |
||
| 1556 | assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); |
||
| 1557 | |||
| 1558 | /* Verification if multimode is disabled (for devices with several ADC) */ |
||
| 1559 | /* If multimode is enabled, dedicated function multimode conversion */ |
||
| 1560 | /* start DMA must be used. */ |
||
| 1561 | if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) |
||
| 1562 | { |
||
| 1563 | /* Process locked */ |
||
| 1564 | __HAL_LOCK(hadc); |
||
| 1565 | |||
| 1566 | /* Enable the ADC peripheral */ |
||
| 1567 | tmp_hal_status = ADC_Enable(hadc); |
||
| 1568 | |||
| 1569 | /* Start conversion if ADC is effectively enabled */ |
||
| 1570 | if (tmp_hal_status == HAL_OK) |
||
| 1571 | { |
||
| 1572 | /* Set ADC state */ |
||
| 1573 | /* - Clear state bitfield related to regular group conversion results */ |
||
| 1574 | /* - Set state bitfield related to regular operation */ |
||
| 1575 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1576 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
||
| 1577 | HAL_ADC_STATE_REG_BUSY); |
||
| 1578 | |||
| 1579 | /* Set group injected state (from auto-injection) and multimode state */ |
||
| 1580 | /* for all cases of multimode: independent mode, multimode ADC master */ |
||
| 1581 | /* or multimode ADC slave (for devices with several ADCs): */ |
||
| 1582 | if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) |
||
| 1583 | { |
||
| 1584 | /* Set ADC state (ADC independent or master) */ |
||
| 1585 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
||
| 1586 | |||
| 1587 | /* If conversions on group regular are also triggering group injected, */ |
||
| 1588 | /* update ADC state. */ |
||
| 1589 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
||
| 1590 | { |
||
| 1591 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
| 1592 | } |
||
| 1593 | } |
||
| 1594 | else |
||
| 1595 | { |
||
| 1596 | /* Set ADC state (ADC slave) */ |
||
| 1597 | SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
||
| 1598 | |||
| 1599 | /* If conversions on group regular are also triggering group injected, */ |
||
| 1600 | /* update ADC state. */ |
||
| 1601 | if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) |
||
| 1602 | { |
||
| 1603 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
| 1604 | } |
||
| 1605 | } |
||
| 1606 | |||
| 1607 | /* State machine update: Check if an injected conversion is ongoing */ |
||
| 1608 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1609 | { |
||
| 1610 | /* Reset ADC error code fields related to conversions on group regular */ |
||
| 1611 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
||
| 1612 | } |
||
| 1613 | else |
||
| 1614 | { |
||
| 1615 | /* Reset ADC all error code fields */ |
||
| 1616 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 1617 | } |
||
| 1618 | |||
| 1619 | /* Process unlocked */ |
||
| 1620 | /* Unlock before starting ADC conversions: in case of potential */ |
||
| 1621 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
| 1622 | __HAL_UNLOCK(hadc); |
||
| 1623 | |||
| 1624 | /* Set the DMA transfer complete callback */ |
||
| 1625 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
||
| 1626 | |||
| 1627 | /* Set the DMA half transfer complete callback */ |
||
| 1628 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
||
| 1629 | |||
| 1630 | /* Set the DMA error callback */ |
||
| 1631 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
||
| 1632 | |||
| 1633 | |||
| 1634 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
||
| 1635 | /* start (in case of SW start): */ |
||
| 1636 | |||
| 1637 | /* Clear regular group conversion flag and overrun flag */ |
||
| 1638 | /* (To ensure of no unknown state from potential previous ADC */ |
||
| 1639 | /* operations) */ |
||
| 1640 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); |
||
| 1641 | |||
| 1642 | /* Enable ADC DMA mode */ |
||
| 1643 | SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); |
||
| 1644 | |||
| 1645 | /* Start the DMA channel */ |
||
| 1646 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
||
| 1647 | |||
| 1648 | /* Enable conversion of regular group. */ |
||
| 1649 | /* If software start has been selected, conversion starts immediately. */ |
||
| 1650 | /* If external trigger has been selected, conversion will start at next */ |
||
| 1651 | /* trigger event. */ |
||
| 1652 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
||
| 1653 | { |
||
| 1654 | /* Start ADC conversion on regular group with SW start */ |
||
| 1655 | SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); |
||
| 1656 | } |
||
| 1657 | else |
||
| 1658 | { |
||
| 1659 | /* Start ADC conversion on regular group with external trigger */ |
||
| 1660 | SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); |
||
| 1661 | } |
||
| 1662 | } |
||
| 1663 | else |
||
| 1664 | { |
||
| 1665 | /* Process unlocked */ |
||
| 1666 | __HAL_UNLOCK(hadc); |
||
| 1667 | } |
||
| 1668 | } |
||
| 1669 | else |
||
| 1670 | { |
||
| 1671 | tmp_hal_status = HAL_ERROR; |
||
| 1672 | } |
||
| 1673 | |||
| 1674 | /* Return function status */ |
||
| 1675 | return tmp_hal_status; |
||
| 1676 | } |
||
| 1677 | |||
| 1678 | /** |
||
| 1679 | * @brief Stop ADC conversion of regular group (and injected group in |
||
| 1680 | * case of auto_injection mode), disable ADC DMA transfer, disable |
||
| 1681 | * ADC peripheral. |
||
| 1682 | * @note: ADC peripheral disable is forcing stop of potential |
||
| 1683 | * conversion on injected group. If injected group is under use, it |
||
| 1684 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
||
| 1685 | * @note For devices with several ADCs: This function is for single-ADC mode |
||
| 1686 | * only. For multimode, use the dedicated MultimodeStop function. |
||
| 1687 | * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending |
||
| 1688 | * on devices) have DMA capability. |
||
| 1689 | * @param hadc: ADC handle |
||
| 1690 | * @retval HAL status. |
||
| 1691 | */ |
||
| 1692 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
||
| 1693 | { |
||
| 1694 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1695 | |||
| 1696 | /* Check the parameters */ |
||
| 1697 | assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); |
||
| 1698 | |||
| 1699 | /* Process locked */ |
||
| 1700 | __HAL_LOCK(hadc); |
||
| 1701 | |||
| 1702 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 1703 | /* Disable ADC peripheral */ |
||
| 1704 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 1705 | |||
| 1706 | /* Check if ADC is effectively disabled */ |
||
| 1707 | if (tmp_hal_status == HAL_OK) |
||
| 1708 | { |
||
| 1709 | /* Disable ADC DMA mode */ |
||
| 1710 | CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); |
||
| 1711 | |||
| 1712 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
||
| 1713 | /* DMA transfer is on going) */ |
||
| 1714 | tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); |
||
| 1715 | |||
| 1716 | /* Check if DMA channel effectively disabled */ |
||
| 1717 | if (tmp_hal_status == HAL_OK) |
||
| 1718 | { |
||
| 1719 | /* Set ADC state */ |
||
| 1720 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1721 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
| 1722 | HAL_ADC_STATE_READY); |
||
| 1723 | } |
||
| 1724 | else |
||
| 1725 | { |
||
| 1726 | /* Update ADC state machine to error */ |
||
| 1727 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
||
| 1728 | } |
||
| 1729 | } |
||
| 1730 | |||
| 1731 | /* Process unlocked */ |
||
| 1732 | __HAL_UNLOCK(hadc); |
||
| 1733 | |||
| 1734 | /* Return function status */ |
||
| 1735 | return tmp_hal_status; |
||
| 1736 | } |
||
| 1737 | |||
| 1738 | /** |
||
| 1739 | * @brief Get ADC regular group conversion result. |
||
| 1740 | * @note Reading register DR automatically clears ADC flag EOC |
||
| 1741 | * (ADC group regular end of unitary conversion). |
||
| 1742 | * @note This function does not clear ADC flag EOS |
||
| 1743 | * (ADC group regular end of sequence conversion). |
||
| 1744 | * Occurrence of flag EOS rising: |
||
| 1745 | * - If sequencer is composed of 1 rank, flag EOS is equivalent |
||
| 1746 | * to flag EOC. |
||
| 1747 | * - If sequencer is composed of several ranks, during the scan |
||
| 1748 | * sequence flag EOC only is raised, at the end of the scan sequence |
||
| 1749 | * both flags EOC and EOS are raised. |
||
| 1750 | * To clear this flag, either use function: |
||
| 1751 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
||
| 1752 | * model polling: @ref HAL_ADC_PollForConversion() |
||
| 1753 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). |
||
| 1754 | * @param hadc: ADC handle |
||
| 1755 | * @retval ADC group regular conversion data |
||
| 1756 | */ |
||
| 1757 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
||
| 1758 | { |
||
| 1759 | /* Check the parameters */ |
||
| 1760 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1761 | |||
| 1762 | /* Note: EOC flag is not cleared here by software because automatically */ |
||
| 1763 | /* cleared by hardware when reading register DR. */ |
||
| 1764 | |||
| 1765 | /* Return ADC converted value */ |
||
| 1766 | return hadc->Instance->DR; |
||
| 1767 | } |
||
| 1768 | |||
| 1769 | /** |
||
| 1770 | * @brief Handles ADC interrupt request |
||
| 1771 | * @param hadc: ADC handle |
||
| 1772 | * @retval None |
||
| 1773 | */ |
||
| 1774 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
||
| 1775 | { |
||
| 1776 | /* Check the parameters */ |
||
| 1777 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1778 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
||
| 1779 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
||
| 1780 | |||
| 1781 | |||
| 1782 | /* ========== Check End of Conversion flag for regular group ========== */ |
||
| 1783 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) |
||
| 1784 | { |
||
| 1785 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) |
||
| 1786 | { |
||
| 1787 | /* Update state machine on conversion status if not in error state */ |
||
| 1788 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
||
| 1789 | { |
||
| 1790 | /* Set ADC state */ |
||
| 1791 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
| 1792 | } |
||
| 1793 | |||
| 1794 | /* Determine whether any further conversion upcoming on group regular */ |
||
| 1795 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
| 1796 | /* Note: On STM32F1 devices, in case of sequencer enabled */ |
||
| 1797 | /* (several ranks selected), end of conversion flag is raised */ |
||
| 1798 | /* at the end of the sequence. */ |
||
| 1799 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 1800 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
||
| 1801 | { |
||
| 1802 | /* Disable ADC end of conversion interrupt on group regular */ |
||
| 1803 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
||
| 1804 | |||
| 1805 | /* Set ADC state */ |
||
| 1806 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
||
| 1807 | |||
| 1808 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1809 | { |
||
| 1810 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
| 1811 | } |
||
| 1812 | } |
||
| 1813 | |||
| 1814 | /* Conversion complete callback */ |
||
| 1815 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 1816 | hadc->ConvCpltCallback(hadc); |
||
| 1817 | #else |
||
| 1818 | HAL_ADC_ConvCpltCallback(hadc); |
||
| 1819 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 1820 | |||
| 1821 | /* Clear regular group conversion flag */ |
||
| 1822 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
||
| 1823 | } |
||
| 1824 | } |
||
| 1825 | |||
| 1826 | /* ========== Check End of Conversion flag for injected group ========== */ |
||
| 1827 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) |
||
| 1828 | { |
||
| 1829 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) |
||
| 1830 | { |
||
| 1831 | /* Update state machine on conversion status if not in error state */ |
||
| 1832 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
||
| 1833 | { |
||
| 1834 | /* Set ADC state */ |
||
| 1835 | SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); |
||
| 1836 | } |
||
| 1837 | |||
| 1838 | /* Determine whether any further conversion upcoming on group injected */ |
||
| 1839 | /* by external trigger, scan sequence on going or by automatic injected */ |
||
| 1840 | /* conversion from group regular (same conditions as group regular */ |
||
| 1841 | /* interruption disabling above). */ |
||
| 1842 | /* Note: On STM32F1 devices, in case of sequencer enabled */ |
||
| 1843 | /* (several ranks selected), end of conversion flag is raised */ |
||
| 1844 | /* at the end of the sequence. */ |
||
| 1845 | if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || |
||
| 1846 | (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && |
||
| 1847 | (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 1848 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
||
| 1849 | { |
||
| 1850 | /* Disable ADC end of conversion interrupt on group injected */ |
||
| 1851 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
||
| 1852 | |||
| 1853 | /* Set ADC state */ |
||
| 1854 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); |
||
| 1855 | |||
| 1856 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
||
| 1857 | { |
||
| 1858 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
| 1859 | } |
||
| 1860 | } |
||
| 1861 | |||
| 1862 | /* Conversion complete callback */ |
||
| 1863 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 1864 | hadc->InjectedConvCpltCallback(hadc); |
||
| 1865 | #else |
||
| 1866 | HAL_ADCEx_InjectedConvCpltCallback(hadc); |
||
| 1867 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 1868 | |||
| 1869 | /* Clear injected group conversion flag */ |
||
| 1870 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); |
||
| 1871 | } |
||
| 1872 | } |
||
| 1873 | |||
| 1874 | /* ========== Check Analog watchdog flags ========== */ |
||
| 1875 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) |
||
| 1876 | { |
||
| 1877 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) |
||
| 1878 | { |
||
| 1879 | /* Set ADC state */ |
||
| 1880 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
||
| 1881 | |||
| 1882 | /* Level out of window callback */ |
||
| 1883 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 1884 | hadc->LevelOutOfWindowCallback(hadc); |
||
| 1885 | #else |
||
| 1886 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
||
| 1887 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 1888 | |||
| 1889 | /* Clear the ADC analog watchdog flag */ |
||
| 1890 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
||
| 1891 | } |
||
| 1892 | } |
||
| 1893 | |||
| 1894 | } |
||
| 1895 | |||
| 1896 | /** |
||
| 1897 | * @brief Conversion complete callback in non blocking mode |
||
| 1898 | * @param hadc: ADC handle |
||
| 1899 | * @retval None |
||
| 1900 | */ |
||
| 1901 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
||
| 1902 | { |
||
| 1903 | /* Prevent unused argument(s) compilation warning */ |
||
| 1904 | UNUSED(hadc); |
||
| 1905 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 1906 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
||
| 1907 | */ |
||
| 1908 | } |
||
| 1909 | |||
| 1910 | /** |
||
| 1911 | * @brief Conversion DMA half-transfer callback in non blocking mode |
||
| 1912 | * @param hadc: ADC handle |
||
| 1913 | * @retval None |
||
| 1914 | */ |
||
| 1915 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
||
| 1916 | { |
||
| 1917 | /* Prevent unused argument(s) compilation warning */ |
||
| 1918 | UNUSED(hadc); |
||
| 1919 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 1920 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
||
| 1921 | */ |
||
| 1922 | } |
||
| 1923 | |||
| 1924 | /** |
||
| 1925 | * @brief Analog watchdog callback in non blocking mode. |
||
| 1926 | * @param hadc: ADC handle |
||
| 1927 | * @retval None |
||
| 1928 | */ |
||
| 1929 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
||
| 1930 | { |
||
| 1931 | /* Prevent unused argument(s) compilation warning */ |
||
| 1932 | UNUSED(hadc); |
||
| 1933 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 1934 | function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. |
||
| 1935 | */ |
||
| 1936 | } |
||
| 1937 | |||
| 1938 | /** |
||
| 1939 | * @brief ADC error callback in non blocking mode |
||
| 1940 | * (ADC conversion with interruption or transfer by DMA) |
||
| 1941 | * @param hadc: ADC handle |
||
| 1942 | * @retval None |
||
| 1943 | */ |
||
| 1944 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
||
| 1945 | { |
||
| 1946 | /* Prevent unused argument(s) compilation warning */ |
||
| 1947 | UNUSED(hadc); |
||
| 1948 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 1949 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
||
| 1950 | */ |
||
| 1951 | } |
||
| 1952 | |||
| 1953 | |||
| 1954 | /** |
||
| 1955 | * @} |
||
| 1956 | */ |
||
| 1957 | |||
| 1958 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
||
| 1959 | * @brief Peripheral Control functions |
||
| 1960 | * |
||
| 1961 | @verbatim |
||
| 1962 | =============================================================================== |
||
| 1963 | ##### Peripheral Control functions ##### |
||
| 1964 | =============================================================================== |
||
| 1965 | [..] This section provides functions allowing to: |
||
| 1966 | (+) Configure channels on regular group |
||
| 1967 | (+) Configure the analog watchdog |
||
| 1968 | |||
| 1969 | @endverbatim |
||
| 1970 | * @{ |
||
| 1971 | */ |
||
| 1972 | |||
| 1973 | /** |
||
| 1974 | * @brief Configures the the selected channel to be linked to the regular |
||
| 1975 | * group. |
||
| 1976 | * @note In case of usage of internal measurement channels: |
||
| 1977 | * Vbat/VrefInt/TempSensor. |
||
| 1978 | * These internal paths can be be disabled using function |
||
| 1979 | * HAL_ADC_DeInit(). |
||
| 1980 | * @note Possibility to update parameters on the fly: |
||
| 1981 | * This function initializes channel into regular group, following |
||
| 1982 | * calls to this function can be used to reconfigure some parameters |
||
| 1983 | * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting |
||
| 1984 | * the ADC. |
||
| 1985 | * The setting of these parameters is conditioned to ADC state. |
||
| 1986 | * For parameters constraints, see comments of structure |
||
| 1987 | * "ADC_ChannelConfTypeDef". |
||
| 1988 | * @param hadc: ADC handle |
||
| 1989 | * @param sConfig: Structure of ADC channel for regular group. |
||
| 1990 | * @retval HAL status |
||
| 1991 | */ |
||
| 1992 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
||
| 1993 | { |
||
| 1994 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1995 | __IO uint32_t wait_loop_index = 0U; |
||
| 1996 | |||
| 1997 | /* Check the parameters */ |
||
| 1998 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1999 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
||
| 2000 | assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); |
||
| 2001 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
||
| 2002 | |||
| 2003 | /* Process locked */ |
||
| 2004 | __HAL_LOCK(hadc); |
||
| 2005 | |||
| 2006 | |||
| 2007 | /* Regular sequence configuration */ |
||
| 2008 | /* For Rank 1 to 6 */ |
||
| 2009 | if (sConfig->Rank < 7U) |
||
| 2010 | { |
||
| 2011 | MODIFY_REG(hadc->Instance->SQR3 , |
||
| 2012 | ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , |
||
| 2013 | ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); |
||
| 2014 | } |
||
| 2015 | /* For Rank 7 to 12 */ |
||
| 2016 | else if (sConfig->Rank < 13U) |
||
| 2017 | { |
||
| 2018 | MODIFY_REG(hadc->Instance->SQR2 , |
||
| 2019 | ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) , |
||
| 2020 | ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); |
||
| 2021 | } |
||
| 2022 | /* For Rank 13 to 16 */ |
||
| 2023 | else |
||
| 2024 | { |
||
| 2025 | MODIFY_REG(hadc->Instance->SQR1 , |
||
| 2026 | ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) , |
||
| 2027 | ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); |
||
| 2028 | } |
||
| 2029 | |||
| 2030 | |||
| 2031 | /* Channel sampling time configuration */ |
||
| 2032 | /* For channels 10 to 17 */ |
||
| 2033 | if (sConfig->Channel >= ADC_CHANNEL_10) |
||
| 2034 | { |
||
| 2035 | MODIFY_REG(hadc->Instance->SMPR1 , |
||
| 2036 | ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , |
||
| 2037 | ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); |
||
| 2038 | } |
||
| 2039 | else /* For channels 0 to 9 */ |
||
| 2040 | { |
||
| 2041 | MODIFY_REG(hadc->Instance->SMPR2 , |
||
| 2042 | ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) , |
||
| 2043 | ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); |
||
| 2044 | } |
||
| 2045 | |||
| 2046 | /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ |
||
| 2047 | /* and VREFINT measurement path. */ |
||
| 2048 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || |
||
| 2049 | (sConfig->Channel == ADC_CHANNEL_VREFINT) ) |
||
| 2050 | { |
||
| 2051 | /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ |
||
| 2052 | /* measurement channels (VrefInt/TempSensor). If these channels are */ |
||
| 2053 | /* intended to be set on other ADC instances, an error is reported. */ |
||
| 2054 | if (hadc->Instance == ADC1) |
||
| 2055 | { |
||
| 2056 | if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) |
||
| 2057 | { |
||
| 2058 | SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); |
||
| 2059 | |||
| 2060 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) |
||
| 2061 | { |
||
| 2062 | /* Delay for temperature sensor stabilization time */ |
||
| 2063 | /* Compute number of CPU cycles to wait for */ |
||
| 2064 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); |
||
| 2065 | while(wait_loop_index != 0U) |
||
| 2066 | { |
||
| 2067 | wait_loop_index--; |
||
| 2068 | } |
||
| 2069 | } |
||
| 2070 | } |
||
| 2071 | } |
||
| 2072 | else |
||
| 2073 | { |
||
| 2074 | /* Update ADC state machine to error */ |
||
| 2075 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
| 2076 | |||
| 2077 | tmp_hal_status = HAL_ERROR; |
||
| 2078 | } |
||
| 2079 | } |
||
| 2080 | |||
| 2081 | /* Process unlocked */ |
||
| 2082 | __HAL_UNLOCK(hadc); |
||
| 2083 | |||
| 2084 | /* Return function status */ |
||
| 2085 | return tmp_hal_status; |
||
| 2086 | } |
||
| 2087 | |||
| 2088 | /** |
||
| 2089 | * @brief Configures the analog watchdog. |
||
| 2090 | * @note Analog watchdog thresholds can be modified while ADC conversion |
||
| 2091 | * is on going. |
||
| 2092 | * In this case, some constraints must be taken into account: |
||
| 2093 | * the programmed threshold values are effective from the next |
||
| 2094 | * ADC EOC (end of unitary conversion). |
||
| 2095 | * Considering that registers write delay may happen due to |
||
| 2096 | * bus activity, this might cause an uncertainty on the |
||
| 2097 | * effective timing of the new programmed threshold values. |
||
| 2098 | * @param hadc: ADC handle |
||
| 2099 | * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration |
||
| 2100 | * @retval HAL status |
||
| 2101 | */ |
||
| 2102 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
||
| 2103 | { |
||
| 2104 | /* Check the parameters */ |
||
| 2105 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 2106 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
||
| 2107 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
||
| 2108 | assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); |
||
| 2109 | assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); |
||
| 2110 | |||
| 2111 | if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || |
||
| 2112 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || |
||
| 2113 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) |
||
| 2114 | { |
||
| 2115 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
||
| 2116 | } |
||
| 2117 | |||
| 2118 | /* Process locked */ |
||
| 2119 | __HAL_LOCK(hadc); |
||
| 2120 | |||
| 2121 | /* Analog watchdog configuration */ |
||
| 2122 | |||
| 2123 | /* Configure ADC Analog watchdog interrupt */ |
||
| 2124 | if(AnalogWDGConfig->ITMode == ENABLE) |
||
| 2125 | { |
||
| 2126 | /* Enable the ADC Analog watchdog interrupt */ |
||
| 2127 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
||
| 2128 | } |
||
| 2129 | else |
||
| 2130 | { |
||
| 2131 | /* Disable the ADC Analog watchdog interrupt */ |
||
| 2132 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
||
| 2133 | } |
||
| 2134 | |||
| 2135 | /* Configuration of analog watchdog: */ |
||
| 2136 | /* - Set the analog watchdog enable mode: regular and/or injected groups, */ |
||
| 2137 | /* one or all channels. */ |
||
| 2138 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
||
| 2139 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
||
| 2140 | MODIFY_REG(hadc->Instance->CR1 , |
||
| 2141 | ADC_CR1_AWDSGL | |
||
| 2142 | ADC_CR1_JAWDEN | |
||
| 2143 | ADC_CR1_AWDEN | |
||
| 2144 | ADC_CR1_AWDCH , |
||
| 2145 | AnalogWDGConfig->WatchdogMode | |
||
| 2146 | AnalogWDGConfig->Channel ); |
||
| 2147 | |||
| 2148 | /* Set the high threshold */ |
||
| 2149 | WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold); |
||
| 2150 | |||
| 2151 | /* Set the low threshold */ |
||
| 2152 | WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold); |
||
| 2153 | |||
| 2154 | /* Process unlocked */ |
||
| 2155 | __HAL_UNLOCK(hadc); |
||
| 2156 | |||
| 2157 | /* Return function status */ |
||
| 2158 | return HAL_OK; |
||
| 2159 | } |
||
| 2160 | |||
| 2161 | |||
| 2162 | /** |
||
| 2163 | * @} |
||
| 2164 | */ |
||
| 2165 | |||
| 2166 | |||
| 2167 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
||
| 2168 | * @brief Peripheral State functions |
||
| 2169 | * |
||
| 2170 | @verbatim |
||
| 2171 | =============================================================================== |
||
| 2172 | ##### Peripheral State and Errors functions ##### |
||
| 2173 | =============================================================================== |
||
| 2174 | [..] |
||
| 2175 | This subsection provides functions to get in run-time the status of the |
||
| 2176 | peripheral. |
||
| 2177 | (+) Check the ADC state |
||
| 2178 | (+) Check the ADC error code |
||
| 2179 | |||
| 2180 | @endverbatim |
||
| 2181 | * @{ |
||
| 2182 | */ |
||
| 2183 | |||
| 2184 | /** |
||
| 2185 | * @brief return the ADC state |
||
| 2186 | * @param hadc: ADC handle |
||
| 2187 | * @retval HAL state |
||
| 2188 | */ |
||
| 2189 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
||
| 2190 | { |
||
| 2191 | /* Return ADC state */ |
||
| 2192 | return hadc->State; |
||
| 2193 | } |
||
| 2194 | |||
| 2195 | /** |
||
| 2196 | * @brief Return the ADC error code |
||
| 2197 | * @param hadc: ADC handle |
||
| 2198 | * @retval ADC Error Code |
||
| 2199 | */ |
||
| 2200 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
||
| 2201 | { |
||
| 2202 | return hadc->ErrorCode; |
||
| 2203 | } |
||
| 2204 | |||
| 2205 | /** |
||
| 2206 | * @} |
||
| 2207 | */ |
||
| 2208 | |||
| 2209 | /** |
||
| 2210 | * @} |
||
| 2211 | */ |
||
| 2212 | |||
| 2213 | /** @defgroup ADC_Private_Functions ADC Private Functions |
||
| 2214 | * @{ |
||
| 2215 | */ |
||
| 2216 | |||
| 2217 | /** |
||
| 2218 | * @brief Enable the selected ADC. |
||
| 2219 | * @note Prerequisite condition to use this function: ADC must be disabled |
||
| 2220 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
||
| 2221 | * @param hadc: ADC handle |
||
| 2222 | * @retval HAL status. |
||
| 2223 | */ |
||
| 2224 | HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
||
| 2225 | { |
||
| 2226 | uint32_t tickstart = 0U; |
||
| 2227 | __IO uint32_t wait_loop_index = 0U; |
||
| 2228 | |||
| 2229 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
||
| 2230 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
||
| 2231 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
||
| 2232 | /* causes: ADC clock not running, ...). */ |
||
| 2233 | if (ADC_IS_ENABLE(hadc) == RESET) |
||
| 2234 | { |
||
| 2235 | /* Enable the Peripheral */ |
||
| 2236 | __HAL_ADC_ENABLE(hadc); |
||
| 2237 | |||
| 2238 | /* Delay for ADC stabilization time */ |
||
| 2239 | /* Compute number of CPU cycles to wait for */ |
||
| 2240 | wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); |
||
| 2241 | while(wait_loop_index != 0U) |
||
| 2242 | { |
||
| 2243 | wait_loop_index--; |
||
| 2244 | } |
||
| 2245 | |||
| 2246 | /* Get tick count */ |
||
| 2247 | tickstart = HAL_GetTick(); |
||
| 2248 | |||
| 2249 | /* Wait for ADC effectively enabled */ |
||
| 2250 | while(ADC_IS_ENABLE(hadc) == RESET) |
||
| 2251 | { |
||
| 2252 | if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) |
||
| 2253 | { |
||
| 2254 | /* Update ADC state machine to error */ |
||
| 2255 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
| 2256 | |||
| 2257 | /* Set ADC error code to ADC IP internal error */ |
||
| 2258 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
| 2259 | |||
| 2260 | /* Process unlocked */ |
||
| 2261 | __HAL_UNLOCK(hadc); |
||
| 2262 | |||
| 2263 | return HAL_ERROR; |
||
| 2264 | } |
||
| 2265 | } |
||
| 2266 | } |
||
| 2267 | |||
| 2268 | /* Return HAL status */ |
||
| 2269 | return HAL_OK; |
||
| 2270 | } |
||
| 2271 | |||
| 2272 | /** |
||
| 2273 | * @brief Stop ADC conversion and disable the selected ADC |
||
| 2274 | * @note Prerequisite condition to use this function: ADC conversions must be |
||
| 2275 | * stopped to disable the ADC. |
||
| 2276 | * @param hadc: ADC handle |
||
| 2277 | * @retval HAL status. |
||
| 2278 | */ |
||
| 2279 | HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) |
||
| 2280 | { |
||
| 2281 | uint32_t tickstart = 0U; |
||
| 2282 | |||
| 2283 | /* Verification if ADC is not already disabled */ |
||
| 2284 | if (ADC_IS_ENABLE(hadc) != RESET) |
||
| 2285 | { |
||
| 2286 | /* Disable the ADC peripheral */ |
||
| 2287 | __HAL_ADC_DISABLE(hadc); |
||
| 2288 | |||
| 2289 | /* Get tick count */ |
||
| 2290 | tickstart = HAL_GetTick(); |
||
| 2291 | |||
| 2292 | /* Wait for ADC effectively disabled */ |
||
| 2293 | while(ADC_IS_ENABLE(hadc) != RESET) |
||
| 2294 | { |
||
| 2295 | if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) |
||
| 2296 | { |
||
| 2297 | /* Update ADC state machine to error */ |
||
| 2298 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
| 2299 | |||
| 2300 | /* Set ADC error code to ADC IP internal error */ |
||
| 2301 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
| 2302 | |||
| 2303 | return HAL_ERROR; |
||
| 2304 | } |
||
| 2305 | } |
||
| 2306 | } |
||
| 2307 | |||
| 2308 | /* Return HAL status */ |
||
| 2309 | return HAL_OK; |
||
| 2310 | } |
||
| 2311 | |||
| 2312 | /** |
||
| 2313 | * @brief DMA transfer complete callback. |
||
| 2314 | * @param hdma: pointer to DMA handle. |
||
| 2315 | * @retval None |
||
| 2316 | */ |
||
| 2317 | void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
||
| 2318 | { |
||
| 2319 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
| 2320 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
| 2321 | |||
| 2322 | /* Update state machine on conversion status if not in error state */ |
||
| 2323 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
||
| 2324 | { |
||
| 2325 | /* Update ADC state machine */ |
||
| 2326 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
| 2327 | |||
| 2328 | /* Determine whether any further conversion upcoming on group regular */ |
||
| 2329 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
| 2330 | /* Note: On STM32F1 devices, in case of sequencer enabled */ |
||
| 2331 | /* (several ranks selected), end of conversion flag is raised */ |
||
| 2332 | /* at the end of the sequence. */ |
||
| 2333 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 2334 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
||
| 2335 | { |
||
| 2336 | /* Set ADC state */ |
||
| 2337 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
||
| 2338 | |||
| 2339 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 2340 | { |
||
| 2341 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
| 2342 | } |
||
| 2343 | } |
||
| 2344 | |||
| 2345 | /* Conversion complete callback */ |
||
| 2346 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 2347 | hadc->ConvCpltCallback(hadc); |
||
| 2348 | #else |
||
| 2349 | HAL_ADC_ConvCpltCallback(hadc); |
||
| 2350 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 2351 | } |
||
| 2352 | else |
||
| 2353 | { |
||
| 2354 | /* Call DMA error callback */ |
||
| 2355 | hadc->DMA_Handle->XferErrorCallback(hdma); |
||
| 2356 | } |
||
| 2357 | } |
||
| 2358 | |||
| 2359 | /** |
||
| 2360 | * @brief DMA half transfer complete callback. |
||
| 2361 | * @param hdma: pointer to DMA handle. |
||
| 2362 | * @retval None |
||
| 2363 | */ |
||
| 2364 | void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
||
| 2365 | { |
||
| 2366 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
| 2367 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
| 2368 | |||
| 2369 | /* Half conversion callback */ |
||
| 2370 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 2371 | hadc->ConvHalfCpltCallback(hadc); |
||
| 2372 | #else |
||
| 2373 | HAL_ADC_ConvHalfCpltCallback(hadc); |
||
| 2374 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 2375 | } |
||
| 2376 | |||
| 2377 | /** |
||
| 2378 | * @brief DMA error callback |
||
| 2379 | * @param hdma: pointer to DMA handle. |
||
| 2380 | * @retval None |
||
| 2381 | */ |
||
| 2382 | void ADC_DMAError(DMA_HandleTypeDef *hdma) |
||
| 2383 | { |
||
| 2384 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
| 2385 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
| 2386 | |||
| 2387 | /* Set ADC state */ |
||
| 2388 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
||
| 2389 | |||
| 2390 | /* Set ADC error code to DMA error */ |
||
| 2391 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
||
| 2392 | |||
| 2393 | /* Error callback */ |
||
| 2394 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 2395 | hadc->ErrorCallback(hadc); |
||
| 2396 | #else |
||
| 2397 | HAL_ADC_ErrorCallback(hadc); |
||
| 2398 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 2399 | } |
||
| 2400 | |||
| 2401 | /** |
||
| 2402 | * @} |
||
| 2403 | */ |
||
| 2404 | |||
| 2405 | #endif /* HAL_ADC_MODULE_ENABLED */ |
||
| 2406 | /** |
||
| 2407 | * @} |
||
| 2408 | */ |
||
| 2409 | |||
| 2410 | /** |
||
| 2411 | * @} |
||
| 2412 | */ |
||
| 2413 | |||
| 2414 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |