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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_system.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of SYSTEM LL module. |
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| 6 | @verbatim |
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| 7 | ============================================================================== |
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| 8 | ##### How to use this driver ##### |
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| 9 | ============================================================================== |
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| 10 | [..] |
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| 11 | The LL SYSTEM driver contains a set of generic APIs that can be |
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| 12 | used by user: |
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| 13 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
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| 14 | (+) Access to DBGCMU registers |
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| 15 | (+) Access to SYSCFG registers |
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| 16 | |||
| 17 | @endverbatim |
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| 18 | ****************************************************************************** |
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| 19 | * @attention |
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| 20 | * |
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| 21 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 22 | * All rights reserved.</center></h2> |
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| 23 | * |
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| 24 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 25 | * the "License"; You may not use this file except in compliance with the |
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| 26 | * License. You may obtain a copy of the License at: |
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| 27 | * opensource.org/licenses/BSD-3-Clause |
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| 28 | * |
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| 29 | ****************************************************************************** |
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| 30 | */ |
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| 31 | |||
| 32 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 33 | #ifndef __STM32F1xx_LL_SYSTEM_H |
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| 34 | #define __STM32F1xx_LL_SYSTEM_H |
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| 35 | |||
| 36 | #ifdef __cplusplus |
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| 37 | extern "C" { |
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| 38 | #endif |
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| 39 | |||
| 40 | /* Includes ------------------------------------------------------------------*/ |
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| 41 | #include "stm32f1xx.h" |
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| 42 | |||
| 43 | /** @addtogroup STM32F1xx_LL_Driver |
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| 44 | * @{ |
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| 45 | */ |
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| 46 | |||
| 47 | #if defined (FLASH) || defined (DBGMCU) |
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| 48 | |||
| 49 | /** @defgroup SYSTEM_LL SYSTEM |
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| 50 | * @{ |
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| 51 | */ |
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| 52 | |||
| 53 | /* Private types -------------------------------------------------------------*/ |
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| 54 | /* Private variables ---------------------------------------------------------*/ |
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| 55 | |||
| 56 | /* Private constants ---------------------------------------------------------*/ |
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| 57 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
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| 58 | * @{ |
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| 59 | */ |
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| 60 | |||
| 61 | /** |
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| 62 | * @} |
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| 63 | */ |
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| 64 | |||
| 65 | /* Private macros ------------------------------------------------------------*/ |
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| 66 | |||
| 67 | /* Exported types ------------------------------------------------------------*/ |
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| 68 | /* Exported constants --------------------------------------------------------*/ |
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| 69 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
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| 70 | * @{ |
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| 71 | */ |
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| 72 | |||
| 73 | |||
| 74 | |||
| 75 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
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| 76 | * @{ |
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| 77 | */ |
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| 78 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
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| 79 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
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| 80 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
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| 81 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
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| 82 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
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| 83 | /** |
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| 84 | * @} |
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| 85 | */ |
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| 86 | |||
| 87 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
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| 88 | * @{ |
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| 89 | */ |
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| 90 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ |
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| 91 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ |
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| 92 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ |
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| 93 | #if defined(DBGMCU_CR_DBG_TIM5_STOP) |
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| 94 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ |
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| 95 | #endif /* DBGMCU_CR_DBG_TIM5_STOP */ |
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| 96 | #if defined(DBGMCU_CR_DBG_TIM6_STOP) |
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| 97 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ |
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| 98 | #endif /* DBGMCU_CR_DBG_TIM6_STOP */ |
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| 99 | #if defined(DBGMCU_CR_DBG_TIM7_STOP) |
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| 100 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ |
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| 101 | #endif /* DBGMCU_CR_DBG_TIM7_STOP */ |
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| 102 | #if defined(DBGMCU_CR_DBG_TIM12_STOP) |
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| 103 | #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ |
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| 104 | #endif /* DBGMCU_CR_DBG_TIM12_STOP */ |
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| 105 | #if defined(DBGMCU_CR_DBG_TIM13_STOP) |
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| 106 | #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ |
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| 107 | #endif /* DBGMCU_CR_DBG_TIM13_STOP */ |
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| 108 | #if defined(DBGMCU_CR_DBG_TIM14_STOP) |
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| 109 | #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ |
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| 110 | #endif /* DBGMCU_CR_DBG_TIM14_STOP */ |
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| 111 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ |
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| 112 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ |
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| 113 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
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| 114 | #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
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| 115 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ |
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| 116 | #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */ |
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| 117 | #if defined(DBGMCU_CR_DBG_CAN1_STOP) |
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| 118 | #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ |
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| 119 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
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| 120 | #if defined(DBGMCU_CR_DBG_CAN2_STOP) |
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| 121 | #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ |
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| 122 | #endif /* DBGMCU_CR_DBG_CAN2_STOP */ |
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| 123 | /** |
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| 124 | * @} |
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| 125 | */ |
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| 126 | |||
| 127 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
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| 128 | * @{ |
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| 129 | */ |
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| 130 | #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ |
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| 131 | #if defined(DBGMCU_CR_DBG_TIM8_STOP) |
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| 132 | #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ |
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| 133 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
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| 134 | #if defined(DBGMCU_CR_DBG_TIM9_STOP) |
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| 135 | #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ |
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| 136 | #endif /* DBGMCU_CR_DBG_TIM9_STOP */ |
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| 137 | #if defined(DBGMCU_CR_DBG_TIM10_STOP) |
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| 138 | #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ |
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| 139 | #endif /* DBGMCU_CR_DBG_TIM10_STOP */ |
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| 140 | #if defined(DBGMCU_CR_DBG_TIM11_STOP) |
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| 141 | #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ |
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| 142 | #endif /* DBGMCU_CR_DBG_TIM11_STOP */ |
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| 143 | #if defined(DBGMCU_CR_DBG_TIM15_STOP) |
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| 144 | #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ |
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| 145 | #endif /* DBGMCU_CR_DBG_TIM15_STOP */ |
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| 146 | #if defined(DBGMCU_CR_DBG_TIM16_STOP) |
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| 147 | #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ |
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| 148 | #endif /* DBGMCU_CR_DBG_TIM16_STOP */ |
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| 149 | #if defined(DBGMCU_CR_DBG_TIM17_STOP) |
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| 150 | #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ |
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| 151 | #endif /* DBGMCU_CR_DBG_TIM17_STOP */ |
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| 152 | /** |
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| 153 | * @} |
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| 154 | */ |
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| 155 | |||
| 156 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
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| 157 | * @{ |
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| 158 | */ |
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| 159 | #if defined(FLASH_ACR_LATENCY) |
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| 160 | #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
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| 161 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ |
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| 162 | #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ |
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| 163 | #else |
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| 164 | #endif /* FLASH_ACR_LATENCY */ |
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| 165 | /** |
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| 166 | * @} |
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| 167 | */ |
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| 168 | |||
| 169 | /** |
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| 170 | * @} |
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| 171 | */ |
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| 172 | |||
| 173 | /* Exported macro ------------------------------------------------------------*/ |
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| 174 | |||
| 175 | /* Exported functions --------------------------------------------------------*/ |
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| 176 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
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| 177 | * @{ |
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| 178 | */ |
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| 179 | |||
| 180 | |||
| 181 | |||
| 182 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
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| 183 | * @{ |
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| 184 | */ |
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| 185 | |||
| 186 | /** |
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| 187 | * @brief Return the device identifier |
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| 188 | * @note For Low Density devices, the device ID is 0x412 |
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| 189 | * @note For Medium Density devices, the device ID is 0x410 |
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| 190 | * @note For High Density devices, the device ID is 0x414 |
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| 191 | * @note For XL Density devices, the device ID is 0x430 |
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| 192 | * @note For Connectivity Line devices, the device ID is 0x418 |
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| 193 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
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| 194 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFF |
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| 195 | */ |
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| 196 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
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| 197 | { |
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| 198 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
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| 199 | } |
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| 200 | |||
| 201 | /** |
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| 202 | * @brief Return the device revision identifier |
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| 203 | * @note This field indicates the revision of the device. |
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| 204 | For example, it is read as revA -> 0x1000,for Low Density devices |
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| 205 | For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices |
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| 206 | For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices |
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| 207 | For example, it is read as revA or 1 -> 0x1003,for XL Density devices |
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| 208 | For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices |
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| 209 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
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| 210 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
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| 211 | */ |
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| 212 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
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| 213 | { |
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| 214 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
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| 215 | } |
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| 216 | |||
| 217 | /** |
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| 218 | * @brief Enable the Debug Module during SLEEP mode |
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| 219 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
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| 220 | * @retval None |
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| 221 | */ |
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| 222 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
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| 223 | { |
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| 224 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
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| 225 | } |
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| 226 | |||
| 227 | /** |
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| 228 | * @brief Disable the Debug Module during SLEEP mode |
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| 229 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
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| 230 | * @retval None |
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| 231 | */ |
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| 232 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
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| 233 | { |
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| 234 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
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| 235 | } |
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| 236 | |||
| 237 | /** |
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| 238 | * @brief Enable the Debug Module during STOP mode |
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| 239 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
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| 240 | * @retval None |
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| 241 | */ |
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| 242 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
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| 243 | { |
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| 244 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
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| 245 | } |
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| 246 | |||
| 247 | /** |
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| 248 | * @brief Disable the Debug Module during STOP mode |
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| 249 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
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| 250 | * @retval None |
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| 251 | */ |
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| 252 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
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| 253 | { |
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| 254 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
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| 255 | } |
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| 256 | |||
| 257 | /** |
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| 258 | * @brief Enable the Debug Module during STANDBY mode |
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| 259 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
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| 260 | * @retval None |
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| 261 | */ |
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| 262 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
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| 263 | { |
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| 264 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
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| 265 | } |
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| 266 | |||
| 267 | /** |
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| 268 | * @brief Disable the Debug Module during STANDBY mode |
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| 269 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
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| 270 | * @retval None |
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| 271 | */ |
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| 272 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
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| 273 | { |
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| 274 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
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| 275 | } |
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| 276 | |||
| 277 | /** |
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| 278 | * @brief Set Trace pin assignment control |
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| 279 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
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| 280 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
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| 281 | * @param PinAssignment This parameter can be one of the following values: |
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| 282 | * @arg @ref LL_DBGMCU_TRACE_NONE |
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| 283 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
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| 284 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
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| 285 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
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| 286 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
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| 287 | * @retval None |
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| 288 | */ |
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| 289 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
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| 290 | { |
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| 291 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
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| 292 | } |
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| 293 | |||
| 294 | /** |
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| 295 | * @brief Get Trace pin assignment control |
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| 296 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
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| 297 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
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| 298 | * @retval Returned value can be one of the following values: |
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| 299 | * @arg @ref LL_DBGMCU_TRACE_NONE |
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| 300 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
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| 301 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
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| 302 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
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| 303 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
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| 304 | */ |
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| 305 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
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| 306 | { |
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| 307 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
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| 308 | } |
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| 309 | |||
| 310 | /** |
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| 311 | * @brief Freeze APB1 peripherals (group1 peripherals) |
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| 312 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 313 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 314 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 315 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 316 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 317 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 318 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 319 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 320 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 321 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 322 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 323 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 324 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 325 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 326 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
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| 327 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph |
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| 328 | * @param Periphs This parameter can be a combination of the following values: |
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| 329 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
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| 330 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
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| 331 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
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| 332 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
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| 333 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
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| 334 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
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| 335 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
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| 336 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
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| 337 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
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| 338 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
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| 339 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
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| 340 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
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| 341 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
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| 342 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
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| 343 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
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| 344 | * |
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| 345 | * (*) value not defined in all devices. |
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| 346 | * @retval None |
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| 347 | */ |
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| 348 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
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| 349 | { |
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| 350 | SET_BIT(DBGMCU->CR, Periphs); |
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| 351 | } |
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| 352 | |||
| 353 | /** |
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| 354 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
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| 355 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 356 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 357 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 358 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 359 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 360 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 361 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 362 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 363 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 364 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 365 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 366 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 367 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 368 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 369 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
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| 370 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
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| 371 | * @param Periphs This parameter can be a combination of the following values: |
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| 372 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
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| 373 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
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| 374 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
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| 375 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
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| 376 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
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| 377 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
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| 378 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
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| 379 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
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| 380 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
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| 381 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP |
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| 382 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
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| 383 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
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| 384 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
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| 385 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
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| 386 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
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| 387 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
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| 388 | * |
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| 389 | * (*) value not defined in all devices. |
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| 390 | * @retval None |
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| 391 | */ |
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| 392 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
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| 393 | { |
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| 394 | CLEAR_BIT(DBGMCU->CR, Periphs); |
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| 395 | } |
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| 396 | |||
| 397 | /** |
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| 398 | * @brief Freeze APB2 peripherals |
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| 399 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 400 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 401 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 402 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 403 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 404 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 405 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 406 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
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| 407 | * @param Periphs This parameter can be a combination of the following values: |
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| 408 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
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| 409 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
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| 410 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
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| 411 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
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| 412 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
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| 413 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
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| 414 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
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| 415 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
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| 416 | * |
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| 417 | * (*) value not defined in all devices. |
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| 418 | * @retval None |
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| 419 | */ |
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| 420 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
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| 421 | { |
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| 422 | SET_BIT(DBGMCU->CR, Periphs); |
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| 423 | } |
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| 424 | |||
| 425 | /** |
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| 426 | * @brief Unfreeze APB2 peripherals |
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| 427 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 428 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 429 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 430 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 431 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 432 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 433 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
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| 434 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
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| 435 | * @param Periphs This parameter can be a combination of the following values: |
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| 436 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
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| 437 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
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| 438 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
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| 439 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
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| 440 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
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| 441 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
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| 442 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
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| 443 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
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| 444 | * |
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| 445 | * (*) value not defined in all devices. |
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| 446 | * @retval None |
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| 447 | */ |
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| 448 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
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| 449 | { |
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| 450 | CLEAR_BIT(DBGMCU->CR, Periphs); |
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| 451 | } |
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| 452 | /** |
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| 453 | * @} |
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| 454 | */ |
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| 455 | |||
| 456 | #if defined(FLASH_ACR_LATENCY) |
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| 457 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
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| 458 | * @{ |
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| 459 | */ |
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| 460 | |||
| 461 | /** |
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| 462 | * @brief Set FLASH Latency |
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| 463 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
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| 464 | * @param Latency This parameter can be one of the following values: |
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| 465 | * @arg @ref LL_FLASH_LATENCY_0 |
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| 466 | * @arg @ref LL_FLASH_LATENCY_1 |
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| 467 | * @arg @ref LL_FLASH_LATENCY_2 |
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| 468 | * @retval None |
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| 469 | */ |
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| 470 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
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| 471 | { |
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| 472 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
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| 473 | } |
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| 474 | |||
| 475 | /** |
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| 476 | * @brief Get FLASH Latency |
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| 477 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
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| 478 | * @retval Returned value can be one of the following values: |
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| 479 | * @arg @ref LL_FLASH_LATENCY_0 |
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| 480 | * @arg @ref LL_FLASH_LATENCY_1 |
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| 481 | * @arg @ref LL_FLASH_LATENCY_2 |
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| 482 | */ |
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| 483 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
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| 484 | { |
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| 485 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
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| 486 | } |
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| 487 | |||
| 488 | /** |
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| 489 | * @brief Enable Prefetch |
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| 490 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch |
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| 491 | * @retval None |
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| 492 | */ |
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| 493 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
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| 494 | { |
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| 495 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
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| 496 | } |
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| 497 | |||
| 498 | /** |
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| 499 | * @brief Disable Prefetch |
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| 500 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch |
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| 501 | * @retval None |
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| 502 | */ |
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| 503 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
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| 504 | { |
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| 505 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
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| 506 | } |
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| 507 | |||
| 508 | /** |
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| 509 | * @brief Check if Prefetch buffer is enabled |
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| 510 | * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled |
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| 511 | * @retval State of bit (1 or 0). |
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| 512 | */ |
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| 513 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
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| 514 | { |
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| 515 | return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); |
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| 516 | } |
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| 517 | |||
| 518 | #endif /* FLASH_ACR_LATENCY */ |
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| 519 | /** |
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| 520 | * @brief Enable Flash Half Cycle Access |
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| 521 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess |
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| 522 | * @retval None |
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| 523 | */ |
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| 524 | __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) |
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| 525 | { |
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| 526 | SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
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| 527 | } |
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| 528 | |||
| 529 | /** |
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| 530 | * @brief Disable Flash Half Cycle Access |
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| 531 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess |
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| 532 | * @retval None |
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| 533 | */ |
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| 534 | __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) |
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| 535 | { |
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| 536 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
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| 537 | } |
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| 538 | |||
| 539 | /** |
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| 540 | * @brief Check if Flash Half Cycle Access is enabled or not |
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| 541 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled |
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| 542 | * @retval State of bit (1 or 0). |
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| 543 | */ |
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| 544 | __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) |
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| 545 | { |
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| 546 | return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); |
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| 547 | } |
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| 548 | |||
| 549 | |||
| 550 | /** |
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| 551 | * @} |
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| 552 | */ |
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| 553 | |||
| 554 | /** |
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| 555 | * @} |
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| 556 | */ |
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| 557 | |||
| 558 | /** |
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| 559 | * @} |
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| 560 | */ |
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| 561 | |||
| 562 | #endif /* defined (FLASH) || defined (DBGMCU) */ |
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| 563 | |||
| 564 | /** |
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| 565 | * @} |
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| 566 | */ |
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| 567 | |||
| 568 | #ifdef __cplusplus |
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| 569 | } |
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| 570 | #endif |
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| 571 | |||
| 572 | #endif /* __STM32F1xx_LL_SYSTEM_H */ |
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| 573 | |||
| 574 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |