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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_ll_dac.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of DAC LL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef STM32F1xx_LL_DAC_H |
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| 22 | #define STM32F1xx_LL_DAC_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f1xx.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F1xx_LL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | #if defined(DAC) |
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| 36 | |||
| 37 | /** @defgroup DAC_LL DAC |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Private types -------------------------------------------------------------*/ |
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| 42 | /* Private variables ---------------------------------------------------------*/ |
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| 43 | |||
| 44 | /* Private constants ---------------------------------------------------------*/ |
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| 45 | /** @defgroup DAC_LL_Private_Constants DAC Private Constants |
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| 46 | * @{ |
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| 47 | */ |
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| 48 | |||
| 49 | /* Internal masks for DAC channels definition */ |
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| 50 | /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ |
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| 51 | /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ |
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| 52 | /* - channel bits position into register SWTRIG */ |
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| 53 | /* - channel register offset of data holding register DHRx */ |
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| 54 | /* - channel register offset of data output register DORx */ |
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| 55 | #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
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| 56 | #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
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| 57 | #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) |
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| 58 | |||
| 59 | #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ |
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| 60 | #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ |
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| 61 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
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| 62 | |||
| 63 | #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ |
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| 64 | #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
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| 65 | #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
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| 66 | #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
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| 67 | #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
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| 68 | #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
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| 69 | #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U |
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| 70 | #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U |
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| 71 | #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U |
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| 72 | #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
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| 73 | |||
| 74 | #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ |
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| 75 | #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ |
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| 76 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) |
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| 77 | |||
| 78 | |||
| 79 | #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ |
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| 80 | #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */ |
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| 81 | #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */ |
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| 82 | |||
| 83 | #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
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| 84 | #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
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| 85 | #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
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| 86 | #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */ |
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| 87 | |||
| 88 | /* DAC registers bits positions */ |
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| 89 | #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos |
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| 90 | #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos |
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| 91 | #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos |
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| 92 | |||
| 93 | /* Miscellaneous data */ |
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| 94 | #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ |
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| 95 | |||
| 96 | /** |
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| 97 | * @} |
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| 98 | */ |
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| 99 | |||
| 100 | |||
| 101 | /* Private macros ------------------------------------------------------------*/ |
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| 102 | /** @defgroup DAC_LL_Private_Macros DAC Private Macros |
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| 103 | * @{ |
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| 104 | */ |
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| 105 | |||
| 106 | /** |
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| 107 | * @brief Driver macro reserved for internal use: set a pointer to |
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| 108 | * a register from a register basis from which an offset |
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| 109 | * is applied. |
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| 110 | * @param __REG__ Register basis from which the offset is applied. |
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| 111 | * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). |
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| 112 | * @retval Pointer to register address |
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| 113 | */ |
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| 114 | #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ |
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| 115 | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) |
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| 116 | |||
| 117 | /** |
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| 118 | * @} |
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| 119 | */ |
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| 120 | |||
| 121 | |||
| 122 | /* Exported types ------------------------------------------------------------*/ |
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| 123 | #if defined(USE_FULL_LL_DRIVER) |
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| 124 | /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure |
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| 125 | * @{ |
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| 126 | */ |
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| 127 | |||
| 128 | /** |
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| 129 | * @brief Structure definition of some features of DAC instance. |
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| 130 | */ |
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| 131 | typedef struct |
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| 132 | { |
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| 133 | uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). |
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| 134 | This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE |
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| 135 | |||
| 136 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ |
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| 137 | |||
| 138 | uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
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| 139 | This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE |
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| 140 | |||
| 141 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ |
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| 142 | |||
| 143 | uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
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| 144 | If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS |
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| 145 | If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE |
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| 146 | @note If waveform automatic generation mode is disabled, this parameter is discarded. |
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| 147 | |||
| 148 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude() |
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| 149 | depending on the wave automatic generation selected. */ |
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| 150 | |||
| 151 | uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. |
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| 152 | This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER |
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| 153 | |||
| 154 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ |
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| 155 | |||
| 156 | } LL_DAC_InitTypeDef; |
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| 157 | |||
| 158 | /** |
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| 159 | * @} |
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| 160 | */ |
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| 161 | #endif /* USE_FULL_LL_DRIVER */ |
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| 162 | |||
| 163 | /* Exported constants --------------------------------------------------------*/ |
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| 164 | /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants |
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| 165 | * @{ |
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| 166 | */ |
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| 167 | |||
| 168 | /** @defgroup DAC_LL_EC_GET_FLAG DAC flags |
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| 169 | * @brief Flags defines which can be used with LL_DAC_ReadReg function |
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| 170 | * @{ |
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| 171 | */ |
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| 172 | /* DAC channel 1 flags */ |
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| 173 | #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ |
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| 174 | |||
| 175 | /* DAC channel 2 flags */ |
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| 176 | #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ |
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| 177 | /** |
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| 178 | * @} |
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| 179 | */ |
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| 180 | |||
| 181 | /** @defgroup DAC_LL_EC_IT DAC interruptions |
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| 182 | * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions |
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| 183 | * @{ |
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| 184 | */ |
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| 185 | #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ |
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| 186 | #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ |
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| 187 | /** |
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| 188 | * @} |
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| 189 | */ |
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| 190 | |||
| 191 | /** @defgroup DAC_LL_EC_CHANNEL DAC channels |
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| 192 | * @{ |
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| 193 | */ |
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| 194 | #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ |
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| 195 | #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ |
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| 196 | /** |
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| 197 | * @} |
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| 198 | */ |
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| 199 | |||
| 200 | /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source |
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| 201 | * @{ |
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| 202 | */ |
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| 203 | #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ |
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| 204 | #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */ |
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| 205 | #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ |
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| 206 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ |
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| 207 | #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ |
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| 208 | #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ |
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| 209 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ |
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| 210 | #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ |
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| 211 | #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */ |
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| 212 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ |
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| 213 | /** |
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| 214 | * @} |
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| 215 | */ |
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| 216 | |||
| 217 | /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode |
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| 218 | * @{ |
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| 219 | */ |
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| 220 | #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ |
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| 221 | #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ |
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| 222 | #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ |
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| 223 | /** |
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| 224 | * @} |
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| 225 | */ |
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| 226 | |||
| 227 | /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits |
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| 228 | * @{ |
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| 229 | */ |
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| 230 | #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ |
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| 231 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ |
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| 232 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ |
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| 233 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ |
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| 234 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ |
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| 235 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ |
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| 236 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ |
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| 237 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ |
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| 238 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ |
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| 239 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ |
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| 240 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ |
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| 241 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ |
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| 242 | /** |
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| 243 | * @} |
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| 244 | */ |
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| 245 | |||
| 246 | /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude |
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| 247 | * @{ |
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| 248 | */ |
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| 249 | #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ |
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| 250 | #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ |
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| 251 | #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ |
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| 252 | #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ |
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| 253 | #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ |
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| 254 | #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ |
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| 255 | #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ |
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| 256 | #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ |
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| 257 | #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ |
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| 258 | #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ |
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| 259 | #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ |
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| 260 | #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ |
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| 261 | /** |
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| 262 | * @} |
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| 263 | */ |
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| 264 | |||
| 265 | /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer |
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| 266 | * @{ |
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| 267 | */ |
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| 268 | #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ |
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| 269 | #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ |
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| 270 | /** |
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| 271 | * @} |
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| 272 | */ |
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| 273 | |||
| 274 | /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution |
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| 275 | * @{ |
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| 276 | */ |
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| 277 | #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ |
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| 278 | #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ |
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| 279 | /** |
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| 280 | * @} |
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| 281 | */ |
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| 282 | |||
| 283 | /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose |
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| 284 | * @{ |
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| 285 | */ |
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| 286 | /* List of DAC registers intended to be used (most commonly) with */ |
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| 287 | /* DMA transfer. */ |
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| 288 | /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ |
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| 289 | #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ |
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| 290 | #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ |
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| 291 | #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ |
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| 292 | /** |
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| 293 | * @} |
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| 294 | */ |
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| 295 | |||
| 296 | /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays |
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| 297 | * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, |
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| 298 | * not timeout values. |
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| 299 | * For details on delays values, refer to descriptions in source code |
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| 300 | * above each literal definition. |
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| 301 | * @{ |
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| 302 | */ |
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| 303 | |||
| 304 | /* Delay for DAC channel voltage settling time from DAC channel startup */ |
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| 305 | /* (transition from disable to enable). */ |
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| 306 | /* Note: DAC channel startup time depends on board application environment: */ |
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| 307 | /* impedance connected to DAC channel output. */ |
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| 308 | /* The delay below is specified under conditions: */ |
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| 309 | /* - voltage maximum transition (lowest to highest value) */ |
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| 310 | /* - until voltage reaches final value +-1LSB */ |
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| 311 | /* - DAC channel output buffer enabled */ |
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| 312 | /* - load impedance of 5kOhm (min), 50pF (max) */ |
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| 313 | /* Literal set to maximum value (refer to device datasheet, */ |
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| 314 | /* parameter "tWAKEUP"). */ |
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| 315 | /* Unit: us */ |
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| 316 | #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ |
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| 317 | |||
| 318 | /* Delay for DAC channel voltage settling time. */ |
||
| 319 | /* Note: DAC channel startup time depends on board application environment: */ |
||
| 320 | /* impedance connected to DAC channel output. */ |
||
| 321 | /* The delay below is specified under conditions: */ |
||
| 322 | /* - voltage maximum transition (lowest to highest value) */ |
||
| 323 | /* - until voltage reaches final value +-1LSB */ |
||
| 324 | /* - DAC channel output buffer enabled */ |
||
| 325 | /* - load impedance of 5kOhm min, 50pF max */ |
||
| 326 | /* Literal set to maximum value (refer to device datasheet, */ |
||
| 327 | /* parameter "tSETTLING"). */ |
||
| 328 | /* Unit: us */ |
||
| 329 | #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ |
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| 330 | |||
| 331 | /** |
||
| 332 | * @} |
||
| 333 | */ |
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| 334 | |||
| 335 | /** |
||
| 336 | * @} |
||
| 337 | */ |
||
| 338 | |||
| 339 | /* Exported macro ------------------------------------------------------------*/ |
||
| 340 | /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros |
||
| 341 | * @{ |
||
| 342 | */ |
||
| 343 | |||
| 344 | /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros |
||
| 345 | * @{ |
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| 346 | */ |
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| 347 | |||
| 348 | /** |
||
| 349 | * @brief Write a value in DAC register |
||
| 350 | * @param __INSTANCE__ DAC Instance |
||
| 351 | * @param __REG__ Register to be written |
||
| 352 | * @param __VALUE__ Value to be written in the register |
||
| 353 | * @retval None |
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| 354 | */ |
||
| 355 | #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
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| 356 | |||
| 357 | /** |
||
| 358 | * @brief Read a value in DAC register |
||
| 359 | * @param __INSTANCE__ DAC Instance |
||
| 360 | * @param __REG__ Register to be read |
||
| 361 | * @retval Register value |
||
| 362 | */ |
||
| 363 | #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
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| 364 | |||
| 365 | /** |
||
| 366 | * @} |
||
| 367 | */ |
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| 368 | |||
| 369 | /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro |
||
| 370 | * @{ |
||
| 371 | */ |
||
| 372 | |||
| 373 | /** |
||
| 374 | * @brief Helper macro to get DAC channel number in decimal format |
||
| 375 | * from literals LL_DAC_CHANNEL_x. |
||
| 376 | * Example: |
||
| 377 | * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) |
||
| 378 | * will return decimal number "1". |
||
| 379 | * @note The input can be a value from functions where a channel |
||
| 380 | * number is returned. |
||
| 381 | * @param __CHANNEL__ This parameter can be one of the following values: |
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| 382 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 383 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 384 | * @retval 1...2 |
||
| 385 | */ |
||
| 386 | #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ |
||
| 387 | ((__CHANNEL__) & DAC_SWTR_CHX_MASK) |
||
| 388 | |||
| 389 | /** |
||
| 390 | * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x |
||
| 391 | * from number in decimal format. |
||
| 392 | * Example: |
||
| 393 | * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) |
||
| 394 | * will return a data equivalent to "LL_DAC_CHANNEL_1". |
||
| 395 | * @note If the input parameter does not correspond to a DAC channel, |
||
| 396 | * this macro returns value '0'. |
||
| 397 | * @param __DECIMAL_NB__ 1...2 |
||
| 398 | * @retval Returned value can be one of the following values: |
||
| 399 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 400 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 401 | */ |
||
| 402 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
||
| 403 | (((__DECIMAL_NB__) == 1U) \ |
||
| 404 | ? ( \ |
||
| 405 | LL_DAC_CHANNEL_1 \ |
||
| 406 | ) \ |
||
| 407 | : \ |
||
| 408 | (((__DECIMAL_NB__) == 2U) \ |
||
| 409 | ? ( \ |
||
| 410 | LL_DAC_CHANNEL_2 \ |
||
| 411 | ) \ |
||
| 412 | : \ |
||
| 413 | ( \ |
||
| 414 | 0U \ |
||
| 415 | ) \ |
||
| 416 | ) \ |
||
| 417 | ) |
||
| 418 | |||
| 419 | /** |
||
| 420 | * @brief Helper macro to define the DAC conversion data full-scale digital |
||
| 421 | * value corresponding to the selected DAC resolution. |
||
| 422 | * @note DAC conversion data full-scale corresponds to voltage range |
||
| 423 | * determined by analog voltage references Vref+ and Vref- |
||
| 424 | * (refer to reference manual). |
||
| 425 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
||
| 426 | * @arg @ref LL_DAC_RESOLUTION_12B |
||
| 427 | * @arg @ref LL_DAC_RESOLUTION_8B |
||
| 428 | * @retval ADC conversion data equivalent voltage value (unit: mVolt) |
||
| 429 | */ |
||
| 430 | #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
||
| 431 | ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) |
||
| 432 | |||
| 433 | /** |
||
| 434 | * @brief Helper macro to calculate the DAC conversion data (unit: digital |
||
| 435 | * value) corresponding to a voltage (unit: mVolt). |
||
| 436 | * @note This helper macro is intended to provide input data in voltage |
||
| 437 | * rather than digital value, |
||
| 438 | * to be used with LL DAC functions such as |
||
| 439 | * @ref LL_DAC_ConvertData12RightAligned(). |
||
| 440 | * @note Analog reference voltage (Vref+) must be either known from |
||
| 441 | * user board environment or can be calculated using ADC measurement |
||
| 442 | * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
||
| 443 | * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) |
||
| 444 | * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel |
||
| 445 | * (unit: mVolt). |
||
| 446 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
||
| 447 | * @arg @ref LL_DAC_RESOLUTION_12B |
||
| 448 | * @arg @ref LL_DAC_RESOLUTION_8B |
||
| 449 | * @retval DAC conversion data (unit: digital value) |
||
| 450 | */ |
||
| 451 | #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ |
||
| 452 | __DAC_VOLTAGE__,\ |
||
| 453 | __DAC_RESOLUTION__) \ |
||
| 454 | ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
||
| 455 | / (__VREFANALOG_VOLTAGE__) \ |
||
| 456 | ) |
||
| 457 | |||
| 458 | /** |
||
| 459 | * @} |
||
| 460 | */ |
||
| 461 | |||
| 462 | /** |
||
| 463 | * @} |
||
| 464 | */ |
||
| 465 | |||
| 466 | |||
| 467 | /* Exported functions --------------------------------------------------------*/ |
||
| 468 | /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions |
||
| 469 | * @{ |
||
| 470 | */ |
||
| 471 | /** |
||
| 472 | * @brief Set the conversion trigger source for the selected DAC channel. |
||
| 473 | * @note For conversion trigger source to be effective, DAC trigger |
||
| 474 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
||
| 475 | * @note To set conversion trigger source, DAC channel must be disabled. |
||
| 476 | * Otherwise, the setting is discarded. |
||
| 477 | * @note Availability of parameters of trigger sources from timer |
||
| 478 | * depends on timers availability on the selected device. |
||
| 479 | * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n |
||
| 480 | * CR TSEL2 LL_DAC_SetTriggerSource |
||
| 481 | * @param DACx DAC instance |
||
| 482 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 483 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 484 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 485 | * @param TriggerSource This parameter can be one of the following values: |
||
| 486 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
||
| 487 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
||
| 488 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO |
||
| 489 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
||
| 490 | * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO |
||
| 491 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
||
| 492 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
||
| 493 | * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO |
||
| 494 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
||
| 495 | * @retval None |
||
| 496 | */ |
||
| 497 | __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) |
||
| 498 | { |
||
| 499 | MODIFY_REG(DACx->CR, |
||
| 500 | DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
| 501 | TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 502 | } |
||
| 503 | |||
| 504 | /** |
||
| 505 | * @brief Get the conversion trigger source for the selected DAC channel. |
||
| 506 | * @note For conversion trigger source to be effective, DAC trigger |
||
| 507 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
||
| 508 | * @note Availability of parameters of trigger sources from timer |
||
| 509 | * depends on timers availability on the selected device. |
||
| 510 | * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n |
||
| 511 | * CR TSEL2 LL_DAC_GetTriggerSource |
||
| 512 | * @param DACx DAC instance |
||
| 513 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 514 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 515 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 516 | * @retval Returned value can be one of the following values: |
||
| 517 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
||
| 518 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
||
| 519 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO |
||
| 520 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
||
| 521 | * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO |
||
| 522 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
||
| 523 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
||
| 524 | * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO |
||
| 525 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
||
| 526 | */ |
||
| 527 | __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 528 | { |
||
| 529 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
| 530 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
| 531 | ); |
||
| 532 | } |
||
| 533 | |||
| 534 | /** |
||
| 535 | * @brief Set the waveform automatic generation mode |
||
| 536 | * for the selected DAC channel. |
||
| 537 | * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n |
||
| 538 | * CR WAVE2 LL_DAC_SetWaveAutoGeneration |
||
| 539 | * @param DACx DAC instance |
||
| 540 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 541 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 542 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 543 | * @param WaveAutoGeneration This parameter can be one of the following values: |
||
| 544 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
||
| 545 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
||
| 546 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
||
| 547 | * @retval None |
||
| 548 | */ |
||
| 549 | __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) |
||
| 550 | { |
||
| 551 | MODIFY_REG(DACx->CR, |
||
| 552 | DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
| 553 | WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 554 | } |
||
| 555 | |||
| 556 | /** |
||
| 557 | * @brief Get the waveform automatic generation mode |
||
| 558 | * for the selected DAC channel. |
||
| 559 | * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n |
||
| 560 | * CR WAVE2 LL_DAC_GetWaveAutoGeneration |
||
| 561 | * @param DACx DAC instance |
||
| 562 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 563 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 564 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 565 | * @retval Returned value can be one of the following values: |
||
| 566 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
||
| 567 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
||
| 568 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
||
| 569 | */ |
||
| 570 | __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 571 | { |
||
| 572 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
| 573 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
| 574 | ); |
||
| 575 | } |
||
| 576 | |||
| 577 | /** |
||
| 578 | * @brief Set the noise waveform generation for the selected DAC channel: |
||
| 579 | * Noise mode and parameters LFSR (linear feedback shift register). |
||
| 580 | * @note For wave generation to be effective, DAC channel |
||
| 581 | * wave generation mode must be enabled using |
||
| 582 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
||
| 583 | * @note This setting can be set when the selected DAC channel is disabled |
||
| 584 | * (otherwise, the setting operation is ignored). |
||
| 585 | * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n |
||
| 586 | * CR MAMP2 LL_DAC_SetWaveNoiseLFSR |
||
| 587 | * @param DACx DAC instance |
||
| 588 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 589 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 590 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 591 | * @param NoiseLFSRMask This parameter can be one of the following values: |
||
| 592 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
||
| 593 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
||
| 594 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
||
| 595 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
||
| 596 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
||
| 597 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
||
| 598 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
||
| 599 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
||
| 600 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
||
| 601 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
||
| 602 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
||
| 603 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
||
| 604 | * @retval None |
||
| 605 | */ |
||
| 606 | __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) |
||
| 607 | { |
||
| 608 | MODIFY_REG(DACx->CR, |
||
| 609 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
| 610 | NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 611 | } |
||
| 612 | |||
| 613 | /** |
||
| 614 | * @brief Get the noise waveform generation for the selected DAC channel: |
||
| 615 | * Noise mode and parameters LFSR (linear feedback shift register). |
||
| 616 | * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n |
||
| 617 | * CR MAMP2 LL_DAC_GetWaveNoiseLFSR |
||
| 618 | * @param DACx DAC instance |
||
| 619 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 620 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 621 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 622 | * @retval Returned value can be one of the following values: |
||
| 623 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
||
| 624 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
||
| 625 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
||
| 626 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
||
| 627 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
||
| 628 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
||
| 629 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
||
| 630 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
||
| 631 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
||
| 632 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
||
| 633 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
||
| 634 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
||
| 635 | */ |
||
| 636 | __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 637 | { |
||
| 638 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
| 639 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
| 640 | ); |
||
| 641 | } |
||
| 642 | |||
| 643 | /** |
||
| 644 | * @brief Set the triangle waveform generation for the selected DAC channel: |
||
| 645 | * triangle mode and amplitude. |
||
| 646 | * @note For wave generation to be effective, DAC channel |
||
| 647 | * wave generation mode must be enabled using |
||
| 648 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
||
| 649 | * @note This setting can be set when the selected DAC channel is disabled |
||
| 650 | * (otherwise, the setting operation is ignored). |
||
| 651 | * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n |
||
| 652 | * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude |
||
| 653 | * @param DACx DAC instance |
||
| 654 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 655 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 656 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 657 | * @param TriangleAmplitude This parameter can be one of the following values: |
||
| 658 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
||
| 659 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
||
| 660 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
||
| 661 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
||
| 662 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
||
| 663 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
||
| 664 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
||
| 665 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
||
| 666 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
||
| 667 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
||
| 668 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
||
| 669 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
||
| 670 | * @retval None |
||
| 671 | */ |
||
| 672 | __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, |
||
| 673 | uint32_t TriangleAmplitude) |
||
| 674 | { |
||
| 675 | MODIFY_REG(DACx->CR, |
||
| 676 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
| 677 | TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 678 | } |
||
| 679 | |||
| 680 | /** |
||
| 681 | * @brief Get the triangle waveform generation for the selected DAC channel: |
||
| 682 | * triangle mode and amplitude. |
||
| 683 | * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n |
||
| 684 | * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude |
||
| 685 | * @param DACx DAC instance |
||
| 686 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 687 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 688 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 689 | * @retval Returned value can be one of the following values: |
||
| 690 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
||
| 691 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
||
| 692 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
||
| 693 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
||
| 694 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
||
| 695 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
||
| 696 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
||
| 697 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
||
| 698 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
||
| 699 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
||
| 700 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
||
| 701 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
||
| 702 | */ |
||
| 703 | __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 704 | { |
||
| 705 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
| 706 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
| 707 | ); |
||
| 708 | } |
||
| 709 | |||
| 710 | /** |
||
| 711 | * @brief Set the output buffer for the selected DAC channel. |
||
| 712 | * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n |
||
| 713 | * CR BOFF2 LL_DAC_SetOutputBuffer |
||
| 714 | * @param DACx DAC instance |
||
| 715 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 716 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 717 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 718 | * @param OutputBuffer This parameter can be one of the following values: |
||
| 719 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
||
| 720 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
||
| 721 | * @retval None |
||
| 722 | */ |
||
| 723 | __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) |
||
| 724 | { |
||
| 725 | MODIFY_REG(DACx->CR, |
||
| 726 | DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
||
| 727 | OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 728 | } |
||
| 729 | |||
| 730 | /** |
||
| 731 | * @brief Get the output buffer state for the selected DAC channel. |
||
| 732 | * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n |
||
| 733 | * CR BOFF2 LL_DAC_GetOutputBuffer |
||
| 734 | * @param DACx DAC instance |
||
| 735 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 736 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 737 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 738 | * @retval Returned value can be one of the following values: |
||
| 739 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
||
| 740 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
||
| 741 | */ |
||
| 742 | __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 743 | { |
||
| 744 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
| 745 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
||
| 746 | ); |
||
| 747 | } |
||
| 748 | |||
| 749 | /** |
||
| 750 | * @} |
||
| 751 | */ |
||
| 752 | |||
| 753 | /** @defgroup DAC_LL_EF_DMA_Management DMA Management |
||
| 754 | * @{ |
||
| 755 | */ |
||
| 756 | |||
| 757 | /** |
||
| 758 | * @brief Enable DAC DMA transfer request of the selected channel. |
||
| 759 | * @note To configure DMA source address (peripheral address), |
||
| 760 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
||
| 761 | * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n |
||
| 762 | * CR DMAEN2 LL_DAC_EnableDMAReq |
||
| 763 | * @param DACx DAC instance |
||
| 764 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 765 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 766 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 767 | * @retval None |
||
| 768 | */ |
||
| 769 | __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 770 | { |
||
| 771 | SET_BIT(DACx->CR, |
||
| 772 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 773 | } |
||
| 774 | |||
| 775 | /** |
||
| 776 | * @brief Disable DAC DMA transfer request of the selected channel. |
||
| 777 | * @note To configure DMA source address (peripheral address), |
||
| 778 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
||
| 779 | * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n |
||
| 780 | * CR DMAEN2 LL_DAC_DisableDMAReq |
||
| 781 | * @param DACx DAC instance |
||
| 782 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 783 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 784 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 785 | * @retval None |
||
| 786 | */ |
||
| 787 | __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 788 | { |
||
| 789 | CLEAR_BIT(DACx->CR, |
||
| 790 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 791 | } |
||
| 792 | |||
| 793 | /** |
||
| 794 | * @brief Get DAC DMA transfer request state of the selected channel. |
||
| 795 | * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) |
||
| 796 | * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n |
||
| 797 | * CR DMAEN2 LL_DAC_IsDMAReqEnabled |
||
| 798 | * @param DACx DAC instance |
||
| 799 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 800 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 801 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 802 | * @retval State of bit (1 or 0). |
||
| 803 | */ |
||
| 804 | __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 805 | { |
||
| 806 | return ((READ_BIT(DACx->CR, |
||
| 807 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
| 808 | == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); |
||
| 809 | } |
||
| 810 | |||
| 811 | /** |
||
| 812 | * @brief Function to help to configure DMA transfer to DAC: retrieve the |
||
| 813 | * DAC register address from DAC instance and a list of DAC registers |
||
| 814 | * intended to be used (most commonly) with DMA transfer. |
||
| 815 | * @note These DAC registers are data holding registers: |
||
| 816 | * when DAC conversion is requested, DAC generates a DMA transfer |
||
| 817 | * request to have data available in DAC data holding registers. |
||
| 818 | * @note This macro is intended to be used with LL DMA driver, refer to |
||
| 819 | * function "LL_DMA_ConfigAddresses()". |
||
| 820 | * Example: |
||
| 821 | * LL_DMA_ConfigAddresses(DMA1, |
||
| 822 | * LL_DMA_CHANNEL_1, |
||
| 823 | * (uint32_t)&< array or variable >, |
||
| 824 | * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), |
||
| 825 | * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); |
||
| 826 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
||
| 827 | * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
||
| 828 | * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
||
| 829 | * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
||
| 830 | * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
||
| 831 | * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr |
||
| 832 | * @param DACx DAC instance |
||
| 833 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 834 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 835 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 836 | * @param Register This parameter can be one of the following values: |
||
| 837 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED |
||
| 838 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED |
||
| 839 | * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED |
||
| 840 | * @retval DAC register address |
||
| 841 | */ |
||
| 842 | __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) |
||
| 843 | { |
||
| 844 | /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ |
||
| 845 | /* DAC channel selected. */ |
||
| 846 | return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, |
||
| 847 | ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); |
||
| 848 | } |
||
| 849 | /** |
||
| 850 | * @} |
||
| 851 | */ |
||
| 852 | |||
| 853 | /** @defgroup DAC_LL_EF_Operation Operation on DAC channels |
||
| 854 | * @{ |
||
| 855 | */ |
||
| 856 | |||
| 857 | /** |
||
| 858 | * @brief Enable DAC selected channel. |
||
| 859 | * @rmtoll CR EN1 LL_DAC_Enable\n |
||
| 860 | * CR EN2 LL_DAC_Enable |
||
| 861 | * @note After enable from off state, DAC channel requires a delay |
||
| 862 | * for output voltage to reach accuracy +/- 1 LSB. |
||
| 863 | * Refer to device datasheet, parameter "tWAKEUP". |
||
| 864 | * @param DACx DAC instance |
||
| 865 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 866 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 867 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 868 | * @retval None |
||
| 869 | */ |
||
| 870 | __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 871 | { |
||
| 872 | SET_BIT(DACx->CR, |
||
| 873 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 874 | } |
||
| 875 | |||
| 876 | /** |
||
| 877 | * @brief Disable DAC selected channel. |
||
| 878 | * @rmtoll CR EN1 LL_DAC_Disable\n |
||
| 879 | * CR EN2 LL_DAC_Disable |
||
| 880 | * @param DACx DAC instance |
||
| 881 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 882 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 883 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 884 | * @retval None |
||
| 885 | */ |
||
| 886 | __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 887 | { |
||
| 888 | CLEAR_BIT(DACx->CR, |
||
| 889 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 890 | } |
||
| 891 | |||
| 892 | /** |
||
| 893 | * @brief Get DAC enable state of the selected channel. |
||
| 894 | * (0: DAC channel is disabled, 1: DAC channel is enabled) |
||
| 895 | * @rmtoll CR EN1 LL_DAC_IsEnabled\n |
||
| 896 | * CR EN2 LL_DAC_IsEnabled |
||
| 897 | * @param DACx DAC instance |
||
| 898 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 899 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 900 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 901 | * @retval State of bit (1 or 0). |
||
| 902 | */ |
||
| 903 | __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 904 | { |
||
| 905 | return ((READ_BIT(DACx->CR, |
||
| 906 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
| 907 | == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); |
||
| 908 | } |
||
| 909 | |||
| 910 | /** |
||
| 911 | * @brief Enable DAC trigger of the selected channel. |
||
| 912 | * @note - If DAC trigger is disabled, DAC conversion is performed |
||
| 913 | * automatically once the data holding register is updated, |
||
| 914 | * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
||
| 915 | * @ref LL_DAC_ConvertData12RightAligned(), ... |
||
| 916 | * - If DAC trigger is enabled, DAC conversion is performed |
||
| 917 | * only when a hardware of software trigger event is occurring. |
||
| 918 | * Select trigger source using |
||
| 919 | * function @ref LL_DAC_SetTriggerSource(). |
||
| 920 | * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n |
||
| 921 | * CR TEN2 LL_DAC_EnableTrigger |
||
| 922 | * @param DACx DAC instance |
||
| 923 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 924 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 925 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 926 | * @retval None |
||
| 927 | */ |
||
| 928 | __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 929 | { |
||
| 930 | SET_BIT(DACx->CR, |
||
| 931 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 932 | } |
||
| 933 | |||
| 934 | /** |
||
| 935 | * @brief Disable DAC trigger of the selected channel. |
||
| 936 | * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n |
||
| 937 | * CR TEN2 LL_DAC_DisableTrigger |
||
| 938 | * @param DACx DAC instance |
||
| 939 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 940 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 941 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 942 | * @retval None |
||
| 943 | */ |
||
| 944 | __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 945 | { |
||
| 946 | CLEAR_BIT(DACx->CR, |
||
| 947 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
||
| 948 | } |
||
| 949 | |||
| 950 | /** |
||
| 951 | * @brief Get DAC trigger state of the selected channel. |
||
| 952 | * (0: DAC trigger is disabled, 1: DAC trigger is enabled) |
||
| 953 | * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n |
||
| 954 | * CR TEN2 LL_DAC_IsTriggerEnabled |
||
| 955 | * @param DACx DAC instance |
||
| 956 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 957 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 958 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 959 | * @retval State of bit (1 or 0). |
||
| 960 | */ |
||
| 961 | __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 962 | { |
||
| 963 | return ((READ_BIT(DACx->CR, |
||
| 964 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
||
| 965 | == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); |
||
| 966 | } |
||
| 967 | |||
| 968 | /** |
||
| 969 | * @brief Trig DAC conversion by software for the selected DAC channel. |
||
| 970 | * @note Preliminarily, DAC trigger must be set to software trigger |
||
| 971 | * using function |
||
| 972 | * @ref LL_DAC_Init() |
||
| 973 | * @ref LL_DAC_SetTriggerSource() |
||
| 974 | * with parameter "LL_DAC_TRIGGER_SOFTWARE". |
||
| 975 | * and DAC trigger must be enabled using |
||
| 976 | * function @ref LL_DAC_EnableTrigger(). |
||
| 977 | * @note For devices featuring DAC with 2 channels: this function |
||
| 978 | * can perform a SW start of both DAC channels simultaneously. |
||
| 979 | * Two channels can be selected as parameter. |
||
| 980 | * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) |
||
| 981 | * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n |
||
| 982 | * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion |
||
| 983 | * @param DACx DAC instance |
||
| 984 | * @param DAC_Channel This parameter can a combination of the following values: |
||
| 985 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 986 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 987 | * @retval None |
||
| 988 | */ |
||
| 989 | __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 990 | { |
||
| 991 | SET_BIT(DACx->SWTRIGR, |
||
| 992 | (DAC_Channel & DAC_SWTR_CHX_MASK)); |
||
| 993 | } |
||
| 994 | |||
| 995 | /** |
||
| 996 | * @brief Set the data to be loaded in the data holding register |
||
| 997 | * in format 12 bits left alignment (LSB aligned on bit 0), |
||
| 998 | * for the selected DAC channel. |
||
| 999 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n |
||
| 1000 | * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned |
||
| 1001 | * @param DACx DAC instance |
||
| 1002 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 1003 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 1004 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 1005 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1006 | * @retval None |
||
| 1007 | */ |
||
| 1008 | __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
||
| 1009 | { |
||
| 1010 | __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); |
||
| 1011 | |||
| 1012 | MODIFY_REG(*preg, |
||
| 1013 | DAC_DHR12R1_DACC1DHR, |
||
| 1014 | Data); |
||
| 1015 | } |
||
| 1016 | |||
| 1017 | /** |
||
| 1018 | * @brief Set the data to be loaded in the data holding register |
||
| 1019 | * in format 12 bits left alignment (MSB aligned on bit 15), |
||
| 1020 | * for the selected DAC channel. |
||
| 1021 | * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n |
||
| 1022 | * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned |
||
| 1023 | * @param DACx DAC instance |
||
| 1024 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 1025 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 1026 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 1027 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1028 | * @retval None |
||
| 1029 | */ |
||
| 1030 | __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
||
| 1031 | { |
||
| 1032 | __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); |
||
| 1033 | |||
| 1034 | MODIFY_REG(*preg, |
||
| 1035 | DAC_DHR12L1_DACC1DHR, |
||
| 1036 | Data); |
||
| 1037 | } |
||
| 1038 | |||
| 1039 | /** |
||
| 1040 | * @brief Set the data to be loaded in the data holding register |
||
| 1041 | * in format 8 bits left alignment (LSB aligned on bit 0), |
||
| 1042 | * for the selected DAC channel. |
||
| 1043 | * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n |
||
| 1044 | * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned |
||
| 1045 | * @param DACx DAC instance |
||
| 1046 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 1047 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 1048 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 1049 | * @param Data Value between Min_Data=0x00 and Max_Data=0xFF |
||
| 1050 | * @retval None |
||
| 1051 | */ |
||
| 1052 | __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
||
| 1053 | { |
||
| 1054 | __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); |
||
| 1055 | |||
| 1056 | MODIFY_REG(*preg, |
||
| 1057 | DAC_DHR8R1_DACC1DHR, |
||
| 1058 | Data); |
||
| 1059 | } |
||
| 1060 | |||
| 1061 | |||
| 1062 | /** |
||
| 1063 | * @brief Set the data to be loaded in the data holding register |
||
| 1064 | * in format 12 bits left alignment (LSB aligned on bit 0), |
||
| 1065 | * for both DAC channels. |
||
| 1066 | * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n |
||
| 1067 | * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned |
||
| 1068 | * @param DACx DAC instance |
||
| 1069 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1070 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1071 | * @retval None |
||
| 1072 | */ |
||
| 1073 | __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, |
||
| 1074 | uint32_t DataChannel2) |
||
| 1075 | { |
||
| 1076 | MODIFY_REG(DACx->DHR12RD, |
||
| 1077 | (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), |
||
| 1078 | ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
||
| 1079 | } |
||
| 1080 | |||
| 1081 | /** |
||
| 1082 | * @brief Set the data to be loaded in the data holding register |
||
| 1083 | * in format 12 bits left alignment (MSB aligned on bit 15), |
||
| 1084 | * for both DAC channels. |
||
| 1085 | * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n |
||
| 1086 | * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned |
||
| 1087 | * @param DACx DAC instance |
||
| 1088 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1089 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1090 | * @retval None |
||
| 1091 | */ |
||
| 1092 | __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, |
||
| 1093 | uint32_t DataChannel2) |
||
| 1094 | { |
||
| 1095 | /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ |
||
| 1096 | /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ |
||
| 1097 | /* the 4 LSB must be taken into account for the shift value. */ |
||
| 1098 | MODIFY_REG(DACx->DHR12LD, |
||
| 1099 | (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), |
||
| 1100 | ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); |
||
| 1101 | } |
||
| 1102 | |||
| 1103 | /** |
||
| 1104 | * @brief Set the data to be loaded in the data holding register |
||
| 1105 | * in format 8 bits left alignment (LSB aligned on bit 0), |
||
| 1106 | * for both DAC channels. |
||
| 1107 | * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n |
||
| 1108 | * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned |
||
| 1109 | * @param DACx DAC instance |
||
| 1110 | * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF |
||
| 1111 | * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF |
||
| 1112 | * @retval None |
||
| 1113 | */ |
||
| 1114 | __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, |
||
| 1115 | uint32_t DataChannel2) |
||
| 1116 | { |
||
| 1117 | MODIFY_REG(DACx->DHR8RD, |
||
| 1118 | (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), |
||
| 1119 | ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
||
| 1120 | } |
||
| 1121 | |||
| 1122 | |||
| 1123 | /** |
||
| 1124 | * @brief Retrieve output data currently generated for the selected DAC channel. |
||
| 1125 | * @note Whatever alignment and resolution settings |
||
| 1126 | * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
||
| 1127 | * @ref LL_DAC_ConvertData12RightAligned(), ...), |
||
| 1128 | * output data format is 12 bits right aligned (LSB aligned on bit 0). |
||
| 1129 | * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n |
||
| 1130 | * DOR2 DACC2DOR LL_DAC_RetrieveOutputData |
||
| 1131 | * @param DACx DAC instance |
||
| 1132 | * @param DAC_Channel This parameter can be one of the following values: |
||
| 1133 | * @arg @ref LL_DAC_CHANNEL_1 |
||
| 1134 | * @arg @ref LL_DAC_CHANNEL_2 |
||
| 1135 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1136 | */ |
||
| 1137 | __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
||
| 1138 | { |
||
| 1139 | __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); |
||
| 1140 | |||
| 1141 | return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); |
||
| 1142 | } |
||
| 1143 | |||
| 1144 | /** |
||
| 1145 | * @} |
||
| 1146 | */ |
||
| 1147 | |||
| 1148 | /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management |
||
| 1149 | * @{ |
||
| 1150 | */ |
||
| 1151 | #if defined(DAC_SR_DMAUDR1) |
||
| 1152 | /** |
||
| 1153 | * @brief Get DAC underrun flag for DAC channel 1 |
||
| 1154 | * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 |
||
| 1155 | * @param DACx DAC instance |
||
| 1156 | * @retval State of bit (1 or 0). |
||
| 1157 | */ |
||
| 1158 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) |
||
| 1159 | { |
||
| 1160 | return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); |
||
| 1161 | } |
||
| 1162 | #endif /* DAC_SR_DMAUDR1 */ |
||
| 1163 | |||
| 1164 | #if defined(DAC_SR_DMAUDR2) |
||
| 1165 | /** |
||
| 1166 | * @brief Get DAC underrun flag for DAC channel 2 |
||
| 1167 | * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 |
||
| 1168 | * @param DACx DAC instance |
||
| 1169 | * @retval State of bit (1 or 0). |
||
| 1170 | */ |
||
| 1171 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) |
||
| 1172 | { |
||
| 1173 | return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); |
||
| 1174 | } |
||
| 1175 | #endif /* DAC_SR_DMAUDR2 */ |
||
| 1176 | |||
| 1177 | #if defined(DAC_SR_DMAUDR1) |
||
| 1178 | /** |
||
| 1179 | * @brief Clear DAC underrun flag for DAC channel 1 |
||
| 1180 | * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 |
||
| 1181 | * @param DACx DAC instance |
||
| 1182 | * @retval None |
||
| 1183 | */ |
||
| 1184 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) |
||
| 1185 | { |
||
| 1186 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); |
||
| 1187 | } |
||
| 1188 | #endif /* DAC_SR_DMAUDR1 */ |
||
| 1189 | |||
| 1190 | #if defined(DAC_SR_DMAUDR2) |
||
| 1191 | /** |
||
| 1192 | * @brief Clear DAC underrun flag for DAC channel 2 |
||
| 1193 | * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 |
||
| 1194 | * @param DACx DAC instance |
||
| 1195 | * @retval None |
||
| 1196 | */ |
||
| 1197 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) |
||
| 1198 | { |
||
| 1199 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); |
||
| 1200 | } |
||
| 1201 | #endif /* DAC_SR_DMAUDR2 */ |
||
| 1202 | |||
| 1203 | /** |
||
| 1204 | * @} |
||
| 1205 | */ |
||
| 1206 | |||
| 1207 | /** @defgroup DAC_LL_EF_IT_Management IT management |
||
| 1208 | * @{ |
||
| 1209 | */ |
||
| 1210 | #if defined(DAC_CR_DMAUDRIE1) |
||
| 1211 | /** |
||
| 1212 | * @brief Enable DMA underrun interrupt for DAC channel 1 |
||
| 1213 | * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 |
||
| 1214 | * @param DACx DAC instance |
||
| 1215 | * @retval None |
||
| 1216 | */ |
||
| 1217 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) |
||
| 1218 | { |
||
| 1219 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
||
| 1220 | } |
||
| 1221 | #endif /* DAC_CR_DMAUDRIE1 */ |
||
| 1222 | |||
| 1223 | #if defined(DAC_CR_DMAUDRIE2) |
||
| 1224 | /** |
||
| 1225 | * @brief Enable DMA underrun interrupt for DAC channel 2 |
||
| 1226 | * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 |
||
| 1227 | * @param DACx DAC instance |
||
| 1228 | * @retval None |
||
| 1229 | */ |
||
| 1230 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) |
||
| 1231 | { |
||
| 1232 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
||
| 1233 | } |
||
| 1234 | #endif /* DAC_CR_DMAUDRIE2 */ |
||
| 1235 | |||
| 1236 | #if defined(DAC_CR_DMAUDRIE1) |
||
| 1237 | /** |
||
| 1238 | * @brief Disable DMA underrun interrupt for DAC channel 1 |
||
| 1239 | * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 |
||
| 1240 | * @param DACx DAC instance |
||
| 1241 | * @retval None |
||
| 1242 | */ |
||
| 1243 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) |
||
| 1244 | { |
||
| 1245 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
||
| 1246 | } |
||
| 1247 | #endif /* DAC_CR_DMAUDRIE1 */ |
||
| 1248 | |||
| 1249 | #if defined(DAC_CR_DMAUDRIE2) |
||
| 1250 | /** |
||
| 1251 | * @brief Disable DMA underrun interrupt for DAC channel 2 |
||
| 1252 | * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 |
||
| 1253 | * @param DACx DAC instance |
||
| 1254 | * @retval None |
||
| 1255 | */ |
||
| 1256 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) |
||
| 1257 | { |
||
| 1258 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
||
| 1259 | } |
||
| 1260 | #endif /* DAC_CR_DMAUDRIE2 */ |
||
| 1261 | |||
| 1262 | #if defined(DAC_CR_DMAUDRIE1) |
||
| 1263 | /** |
||
| 1264 | * @brief Get DMA underrun interrupt for DAC channel 1 |
||
| 1265 | * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 |
||
| 1266 | * @param DACx DAC instance |
||
| 1267 | * @retval State of bit (1 or 0). |
||
| 1268 | */ |
||
| 1269 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) |
||
| 1270 | { |
||
| 1271 | return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); |
||
| 1272 | } |
||
| 1273 | #endif /* DAC_CR_DMAUDRIE1 */ |
||
| 1274 | |||
| 1275 | #if defined(DAC_CR_DMAUDRIE2) |
||
| 1276 | /** |
||
| 1277 | * @brief Get DMA underrun interrupt for DAC channel 2 |
||
| 1278 | * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 |
||
| 1279 | * @param DACx DAC instance |
||
| 1280 | * @retval State of bit (1 or 0). |
||
| 1281 | */ |
||
| 1282 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) |
||
| 1283 | { |
||
| 1284 | return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); |
||
| 1285 | } |
||
| 1286 | #endif /* DAC_CR_DMAUDRIE2 */ |
||
| 1287 | |||
| 1288 | /** |
||
| 1289 | * @} |
||
| 1290 | */ |
||
| 1291 | |||
| 1292 | #if defined(USE_FULL_LL_DRIVER) |
||
| 1293 | /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions |
||
| 1294 | * @{ |
||
| 1295 | */ |
||
| 1296 | |||
| 1297 | ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); |
||
| 1298 | ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); |
||
| 1299 | void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); |
||
| 1300 | |||
| 1301 | /** |
||
| 1302 | * @} |
||
| 1303 | */ |
||
| 1304 | #endif /* USE_FULL_LL_DRIVER */ |
||
| 1305 | |||
| 1306 | /** |
||
| 1307 | * @} |
||
| 1308 | */ |
||
| 1309 | |||
| 1310 | /** |
||
| 1311 | * @} |
||
| 1312 | */ |
||
| 1313 | |||
| 1314 | #endif /* DAC */ |
||
| 1315 | |||
| 1316 | /** |
||
| 1317 | * @} |
||
| 1318 | */ |
||
| 1319 | |||
| 1320 | #ifdef __cplusplus |
||
| 1321 | } |
||
| 1322 | #endif |
||
| 1323 | |||
| 1324 | #endif /* STM32F1xx_LL_DAC_H */ |
||
| 1325 | |||
| 1326 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |