WebSVN – dashGPS – Blame – /branches/dashGPS-bmp/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM HAL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef STM32F1xx_HAL_TIM_H
		22	#define STM32F1xx_HAL_TIM_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f1xx_hal_def.h"
		30
		31	/** @addtogroup STM32F1xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup TIM
		36	* @{
		37	*/
		38
		39	/* Exported types ------------------------------------------------------------*/
		40	/** @defgroup TIM_Exported_Types TIM Exported Types
		41	* @{
		42	*/
		43
		44	/**
		45	* @brief TIM Time base Configuration Structure definition
		46	*/
		47	typedef struct
		48	{
		49	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		50	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		51
		52	uint32_t CounterMode; /*!< Specifies the counter mode.
		53	This parameter can be a value of @ref TIM_Counter_Mode */
		54
		55	uint32_t Period; /*!< Specifies the period value to be loaded into the active
		56	Auto-Reload Register at the next update event.
		57	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
		58
		59	uint32_t ClockDivision; /*!< Specifies the clock division.
		60	This parameter can be a value of @ref TIM_ClockDivision */
		61
		62	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
		63	reaches zero, an update event is generated and counting restarts
		64	from the RCR value (N).
		65	This means in PWM mode that (N+1) corresponds to:
		66	- the number of PWM periods in edge-aligned mode
		67	- the number of half PWM period in center-aligned mode
		68	GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
		69	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
		70
		71	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
		72	This parameter can be a value of @ref TIM_AutoReloadPreload */
		73	} TIM_Base_InitTypeDef;
		74
		75	/**
		76	* @brief TIM Output Compare Configuration Structure definition
		77	*/
		78	typedef struct
		79	{
		80	uint32_t OCMode; /*!< Specifies the TIM mode.
		81	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		82
		83	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		84	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		85
		86	uint32_t OCPolarity; /*!< Specifies the output polarity.
		87	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		88
		89	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		90	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
		91	@note This parameter is valid only for timer instances supporting break feature. */
		92
		93	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
		94	This parameter can be a value of @ref TIM_Output_Fast_State
		95	@note This parameter is valid only in PWM1 and PWM2 mode. */
		96
		97
		98	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		99	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
		100	@note This parameter is valid only for timer instances supporting break feature. */
		101
		102	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		103	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
		104	@note This parameter is valid only for timer instances supporting break feature. */
		105	} TIM_OC_InitTypeDef;
		106
		107	/**
		108	* @brief TIM One Pulse Mode Configuration Structure definition
		109	*/
		110	typedef struct
		111	{
		112	uint32_t OCMode; /*!< Specifies the TIM mode.
		113	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		114
		115	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		116	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		117
		118	uint32_t OCPolarity; /*!< Specifies the output polarity.
		119	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		120
		121	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		122	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
		123	@note This parameter is valid only for timer instances supporting break feature. */
		124
		125	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		126	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
		127	@note This parameter is valid only for timer instances supporting break feature. */
		128
		129	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		130	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
		131	@note This parameter is valid only for timer instances supporting break feature. */
		132
		133	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		134	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		135
		136	uint32_t ICSelection; /*!< Specifies the input.
		137	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		138
		139	uint32_t ICFilter; /*!< Specifies the input capture filter.
		140	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		141	} TIM_OnePulse_InitTypeDef;
		142
		143	/**
		144	* @brief TIM Input Capture Configuration Structure definition
		145	*/
		146	typedef struct
		147	{
		148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		150
		151	uint32_t ICSelection; /*!< Specifies the input.
		152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		153
		154	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		155	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		156
		157	uint32_t ICFilter; /*!< Specifies the input capture filter.
		158	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		159	} TIM_IC_InitTypeDef;
		160
		161	/**
		162	* @brief TIM Encoder Configuration Structure definition
		163	*/
		164	typedef struct
		165	{
		166	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
		167	This parameter can be a value of @ref TIM_Encoder_Mode */
		168
		169	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
		170	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		171
		172	uint32_t IC1Selection; /*!< Specifies the input.
		173	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		174
		175	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
		176	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		177
		178	uint32_t IC1Filter; /*!< Specifies the input capture filter.
		179	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		180
		181	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
		182	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		183
		184	uint32_t IC2Selection; /*!< Specifies the input.
		185	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		186
		187	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
		188	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		189
		190	uint32_t IC2Filter; /*!< Specifies the input capture filter.
		191	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		192	} TIM_Encoder_InitTypeDef;
		193
		194	/**
		195	* @brief Clock Configuration Handle Structure definition
		196	*/
		197	typedef struct
		198	{
		199	uint32_t ClockSource; /*!< TIM clock sources
		200	This parameter can be a value of @ref TIM_Clock_Source */
		201	uint32_t ClockPolarity; /*!< TIM clock polarity
		202	This parameter can be a value of @ref TIM_Clock_Polarity */
		203	uint32_t ClockPrescaler; /*!< TIM clock prescaler
		204	This parameter can be a value of @ref TIM_Clock_Prescaler */
		205	uint32_t ClockFilter; /*!< TIM clock filter
		206	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		207	} TIM_ClockConfigTypeDef;
		208
		209	/**
		210	* @brief TIM Clear Input Configuration Handle Structure definition
		211	*/
		212	typedef struct
		213	{
		214	uint32_t ClearInputState; /*!< TIM clear Input state
		215	This parameter can be ENABLE or DISABLE */
		216	uint32_t ClearInputSource; /*!< TIM clear Input sources
		217	This parameter can be a value of @ref TIM_ClearInput_Source */
		218	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
		219	This parameter can be a value of @ref TIM_ClearInput_Polarity */
		220	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
		221	This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
		222	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
		223	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		224	} TIM_ClearInputConfigTypeDef;
		225
		226	/**
		227	* @brief TIM Master configuration Structure definition
		228	*/
		229	typedef struct
		230	{
		231	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
		232	This parameter can be a value of @ref TIM_Master_Mode_Selection */
		233	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
		234	This parameter can be a value of @ref TIM_Master_Slave_Mode
		235	@note When the Master/slave mode is enabled, the effect of
		236	an event on the trigger input (TRGI) is delayed to allow a
		237	perfect synchronization between the current timer and its
		238	slaves (through TRGO). It is not mandatory in case of timer
		239	synchronization mode. */
		240	} TIM_MasterConfigTypeDef;
		241
		242	/**
		243	* @brief TIM Slave configuration Structure definition
		244	*/
		245	typedef struct
		246	{
		247	uint32_t SlaveMode; /*!< Slave mode selection
		248	This parameter can be a value of @ref TIM_Slave_Mode */
		249	uint32_t InputTrigger; /*!< Input Trigger source
		250	This parameter can be a value of @ref TIM_Trigger_Selection */
		251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
		252	This parameter can be a value of @ref TIM_Trigger_Polarity */
		253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
		254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
		255	uint32_t TriggerFilter; /*!< Input trigger filter
		256	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		257
		258	} TIM_SlaveConfigTypeDef;
		259
		260	/**
		261	* @brief TIM Break input(s) and Dead time configuration Structure definition
		262	* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
		263	* filter and polarity.
		264	*/
		265	typedef struct
		266	{
		267	uint32_t OffStateRunMode; /*!< TIM off state in run mode
		268	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
		269	uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
		270	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
		271	uint32_t LockLevel; /*!< TIM Lock level
		272	This parameter can be a value of @ref TIM_Lock_level */
		273	uint32_t DeadTime; /*!< TIM dead Time
		274	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
		275	uint32_t BreakState; /*!< TIM Break State
		276	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
		277	uint32_t BreakPolarity; /*!< TIM Break input polarity
		278	This parameter can be a value of @ref TIM_Break_Polarity */
		279	uint32_t BreakFilter; /*!< Specifies the break input filter.
		280	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		281	uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
		282	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
		283	} TIM_BreakDeadTimeConfigTypeDef;
		284
		285	/**
		286	* @brief HAL State structures definition
		287	*/
		288	typedef enum
		289	{
		290	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
		291	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
		292	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
		293	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
		294	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
		295	} HAL_TIM_StateTypeDef;
		296
		297	/**
		298	* @brief HAL Active channel structures definition
		299	*/
		300	typedef enum
		301	{
		302	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
		303	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
		304	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
		305	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
		306	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
		307	} HAL_TIM_ActiveChannel;
		308
		309	/**
		310	* @brief TIM Time Base Handle Structure definition
		311	*/
		312	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		313	typedef struct __TIM_HandleTypeDef
		314	#else
		315	typedef struct
		316	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		317	{
		318	TIM_TypeDef Instance; /!< Register base address */
		319	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
		320	HAL_TIM_ActiveChannel Channel; /!< Active channel /
		321	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
		322	This array is accessed by a @ref DMA_Handle_index */
		323	HAL_LockTypeDef Lock; /!< Locking object /
		324	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
		325
		326	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		327	void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp Init Callback */
		328	void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp DeInit Callback */
		329	void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp Init Callback */
		330	void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp DeInit Callback */
		331	void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp Init Callback */
		332	void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp DeInit Callback */
		333	void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp Init Callback */
		334	void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp DeInit Callback */
		335	void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp Init Callback */
		336	void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp DeInit Callback */
		337	void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp Init Callback */
		338	void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp DeInit Callback */
		339	void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp Init Callback */
		340	void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp DeInit Callback */
		341	void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed Callback */
		342	void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed half complete Callback */
		343	void (* TriggerCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger Callback */
		344	void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger half complete Callback */
		345	void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture Callback */
		346	void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture half complete Callback */
		347	void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Output Compare Delay Elapsed Callback */
		348	void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished Callback */
		349	void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished half complete Callback */
		350	void (* ErrorCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Error Callback */
		351	void (* CommutationCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation Callback */
		352	void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation half complete Callback */
		353	void (* BreakCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Break Callback */
		354	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		355	} TIM_HandleTypeDef;
		356
		357	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		358	/**
		359	* @brief HAL TIM Callback ID enumeration definition
		360	*/
		361	typedef enum
		362	{
		363	HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /!< TIM Base MspInit Callback ID /
		364	,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /!< TIM Base MspDeInit Callback ID /
		365	,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /!< TIM IC MspInit Callback ID /
		366	,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /!< TIM IC MspDeInit Callback ID /
		367	,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /!< TIM OC MspInit Callback ID /
		368	,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /!< TIM OC MspDeInit Callback ID /
		369	,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /!< TIM PWM MspInit Callback ID /
		370	,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /!< TIM PWM MspDeInit Callback ID /
		371	,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /!< TIM One Pulse MspInit Callback ID /
		372	,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /!< TIM One Pulse MspDeInit Callback ID /
		373	,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /!< TIM Encoder MspInit Callback ID /
		374	,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /!< TIM Encoder MspDeInit Callback ID /
		375	,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /!< TIM Hall Sensor MspDeInit Callback ID /
		376	,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /!< TIM Hall Sensor MspDeInit Callback ID /
		377	,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /!< TIM Period Elapsed Callback ID /
		378	,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /!< TIM Period Elapsed half complete Callback ID /
		379	,HAL_TIM_TRIGGER_CB_ID = 0x10U /!< TIM Trigger Callback ID /
		380	,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /!< TIM Trigger half complete Callback ID /
		381
		382	,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /!< TIM Input Capture Callback ID /
		383	,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /!< TIM Input Capture half complete Callback ID /
		384	,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /!< TIM Output Compare Delay Elapsed Callback ID /
		385	,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /!< TIM PWM Pulse Finished Callback ID /
		386	,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /!< TIM PWM Pulse Finished half complete Callback ID /
		387	,HAL_TIM_ERROR_CB_ID = 0x17U /!< TIM Error Callback ID /
		388	,HAL_TIM_COMMUTATION_CB_ID = 0x18U /!< TIM Commutation Callback ID /
		389	,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /!< TIM Commutation half complete Callback ID /
		390	,HAL_TIM_BREAK_CB_ID = 0x1AU /!< TIM Break Callback ID /
		391	} HAL_TIM_CallbackIDTypeDef;
		392
		393	/**
		394	* @brief HAL TIM Callback pointer definition
		395	*/
		396	typedef void (pTIM_CallbackTypeDef)(TIM_HandleTypeDef htim); /!< pointer to the TIM callback function /
		397
		398	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		399
		400	/**
		401	* @}
		402	*/
		403	/* End of exported types -----------------------------------------------------*/
		404
		405	/* Exported constants --------------------------------------------------------*/
		406	/** @defgroup TIM_Exported_Constants TIM Exported Constants
		407	* @{
		408	*/
		409
		410	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
		411	* @{
		412	*/
		413	#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /!< OCREF_CLR is disabled /
		414	#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /!< OCREF_CLR is connected to ETRF input /
		415	/**
		416	* @}
		417	*/
		418
		419	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
		420	* @{
		421	*/
		422	#define TIM_DMABASE_CR1 0x00000000U
		423	#define TIM_DMABASE_CR2 0x00000001U
		424	#define TIM_DMABASE_SMCR 0x00000002U
		425	#define TIM_DMABASE_DIER 0x00000003U
		426	#define TIM_DMABASE_SR 0x00000004U
		427	#define TIM_DMABASE_EGR 0x00000005U
		428	#define TIM_DMABASE_CCMR1 0x00000006U
		429	#define TIM_DMABASE_CCMR2 0x00000007U
		430	#define TIM_DMABASE_CCER 0x00000008U
		431	#define TIM_DMABASE_CNT 0x00000009U
		432	#define TIM_DMABASE_PSC 0x0000000AU
		433	#define TIM_DMABASE_ARR 0x0000000BU
		434	#define TIM_DMABASE_RCR 0x0000000CU
		435	#define TIM_DMABASE_CCR1 0x0000000DU
		436	#define TIM_DMABASE_CCR2 0x0000000EU
		437	#define TIM_DMABASE_CCR3 0x0000000FU
		438	#define TIM_DMABASE_CCR4 0x00000010U
		439	#define TIM_DMABASE_BDTR 0x00000011U
		440	#define TIM_DMABASE_DCR 0x00000012U
		441	#define TIM_DMABASE_DMAR 0x00000013U
		442	/**
		443	* @}
		444	*/
		445
		446	/** @defgroup TIM_Event_Source TIM Event Source
		447	* @{
		448	*/
		449	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
		450	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
		451	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
		452	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
		453	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
		454	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /!< A commutation event is generated /
		455	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
		456	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /!< A break event is generated /
		457	/**
		458	* @}
		459	*/
		460
		461	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
		462	* @{
		463	*/
		464	#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /!< Polarity for TIx source /
		465	#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /!< Polarity for TIx source /
		466	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
		467	/**
		468	* @}
		469	*/
		470
		471	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
		472	* @{
		473	*/
		474	#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /!< Polarity for ETR source /
		475	#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /!< Polarity for ETR source /
		476	/**
		477	* @}
		478	*/
		479
		480	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
		481	* @{
		482	*/
		483	#define TIM_ETRPRESCALER_DIV1 0x00000000U /!< No prescaler is used /
		484	#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR input source is divided by 2 /
		485	#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR input source is divided by 4 /
		486	#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR input source is divided by 8 /
		487	/**
		488	* @}
		489	*/
		490
		491	/** @defgroup TIM_Counter_Mode TIM Counter Mode
		492	* @{
		493	*/
		494	#define TIM_COUNTERMODE_UP 0x00000000U /!< Counter used as up-counter /
		495	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as down-counter /
		496	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /!< Center-aligned mode 1 /
		497	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /!< Center-aligned mode 2 /
		498	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /!< Center-aligned mode 3 /
		499	/**
		500	* @}
		501	*/
		502
		503	/** @defgroup TIM_ClockDivision TIM Clock Division
		504	* @{
		505	*/
		506	#define TIM_CLOCKDIVISION_DIV1 0x00000000U /!< Clock division: tDTS=tCK_INT /
		507	#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< Clock division: tDTS=2tCK_INT */
		508	#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< Clock division: tDTS=4tCK_INT */
		509	/**
		510	* @}
		511	*/
		512
		513	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
		514	* @{
		515	*/
		516	#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /!< Capture/Compare 1 output disabled /
		517	#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /!< Capture/Compare 1 output enabled /
		518	/**
		519	* @}
		520	*/
		521
		522	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
		523	* @{
		524	*/
		525	#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /!< TIMx_ARR register is not buffered /
		526	#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /!< TIMx_ARR register is buffered /
		527
		528	/**
		529	* @}
		530	*/
		531
		532	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
		533	* @{
		534	*/
		535	#define TIM_OCFAST_DISABLE 0x00000000U /!< Output Compare fast disable /
		536	#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /!< Output Compare fast enable /
		537	/**
		538	* @}
		539	*/
		540
		541	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
		542	* @{
		543	*/
		544	#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /!< OCxN is disabled /
		545	#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /!< OCxN is enabled /
		546	/**
		547	* @}
		548	*/
		549
		550	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
		551	* @{
		552	*/
		553	#define TIM_OCPOLARITY_HIGH 0x00000000U /!< Capture/Compare output polarity /
		554	#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< Capture/Compare output polarity /
		555	/**
		556	* @}
		557	*/
		558
		559	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
		560	* @{
		561	*/
		562	#define TIM_OCNPOLARITY_HIGH 0x00000000U /!< Capture/Compare complementary output polarity /
		563	#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /!< Capture/Compare complementary output polarity /
		564	/**
		565	* @}
		566	*/
		567
		568	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
		569	* @{
		570	*/
		571	#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /!< Output Idle state: OCx=1 when MOE=0 /
		572	#define TIM_OCIDLESTATE_RESET 0x00000000U /!< Output Idle state: OCx=0 when MOE=0 /
		573	/**
		574	* @}
		575	*/
		576
		577	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
		578	* @{
		579	*/
		580	#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /!< Complementary output Idle state: OCxN=1 when MOE=0 /
		581	#define TIM_OCNIDLESTATE_RESET 0x00000000U /!< Complementary output Idle state: OCxN=0 when MOE=0 /
		582	/**
		583	* @}
		584	*/
		585
		586	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
		587	* @{
		588	*/
		589	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Capture triggered by rising edge on timer input /
		590	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Capture triggered by falling edge on timer input /
		591	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Capture triggered by both rising and falling edges on timer input/
		592	/**
		593	* @}
		594	*/
		595
		596	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
		597	* @{
		598	*/
		599	#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
		600	connected to IC1, IC2, IC3 or IC4, respectively */
		601	#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
		602	connected to IC2, IC1, IC4 or IC3, respectively */
		603	#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
		604	/**
		605	* @}
		606	*/
		607
		608	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
		609	* @{
		610	*/
		611	#define TIM_ICPSC_DIV1 0x00000000U /!< Capture performed each time an edge is detected on the capture input /
		612	#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /!< Capture performed once every 2 events /
		613	#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /!< Capture performed once every 4 events /
		614	#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /!< Capture performed once every 8 events /
		615	/**
		616	* @}
		617	*/
		618
		619	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
		620	* @{
		621	*/
		622	#define TIM_OPMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
		623	#define TIM_OPMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
		624	/**
		625	* @}
		626	*/
		627
		628	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
		629	* @{
		630	*/
		631	#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level /
		632	#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. /
		633	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. /
		634	/**
		635	* @}
		636	*/
		637
		638	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
		639	* @{
		640	*/
		641	#define TIM_IT_UPDATE TIM_DIER_UIE /!< Update interrupt /
		642	#define TIM_IT_CC1 TIM_DIER_CC1IE /!< Capture/Compare 1 interrupt /
		643	#define TIM_IT_CC2 TIM_DIER_CC2IE /!< Capture/Compare 2 interrupt /
		644	#define TIM_IT_CC3 TIM_DIER_CC3IE /!< Capture/Compare 3 interrupt /
		645	#define TIM_IT_CC4 TIM_DIER_CC4IE /!< Capture/Compare 4 interrupt /
		646	#define TIM_IT_COM TIM_DIER_COMIE /!< Commutation interrupt /
		647	#define TIM_IT_TRIGGER TIM_DIER_TIE /!< Trigger interrupt /
		648	#define TIM_IT_BREAK TIM_DIER_BIE /!< Break interrupt /
		649	/**
		650	* @}
		651	*/
		652
		653	/** @defgroup TIM_Commutation_Source TIM Commutation Source
		654	* @{
		655	*/
		656	#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input /
		657	#define TIM_COMMUTATION_SOFTWARE 0x00000000U /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit /
		658	/**
		659	* @}
		660	*/
		661
		662	/** @defgroup TIM_DMA_sources TIM DMA Sources
		663	* @{
		664	*/
		665	#define TIM_DMA_UPDATE TIM_DIER_UDE /!< DMA request is triggered by the update event /
		666	#define TIM_DMA_CC1 TIM_DIER_CC1DE /!< DMA request is triggered by the capture/compare macth 1 event /
		667	#define TIM_DMA_CC2 TIM_DIER_CC2DE /!< DMA request is triggered by the capture/compare macth 2 event event /
		668	#define TIM_DMA_CC3 TIM_DIER_CC3DE /!< DMA request is triggered by the capture/compare macth 3 event event /
		669	#define TIM_DMA_CC4 TIM_DIER_CC4DE /!< DMA request is triggered by the capture/compare macth 4 event event /
		670	#define TIM_DMA_COM TIM_DIER_COMDE /!< DMA request is triggered by the commutation event /
		671	#define TIM_DMA_TRIGGER TIM_DIER_TDE /!< DMA request is triggered by the trigger event /
		672	/**
		673	* @}
		674	*/
		675
		676	/** @defgroup TIM_Flag_definition TIM Flag Definition
		677	* @{
		678	*/
		679	#define TIM_FLAG_UPDATE TIM_SR_UIF /!< Update interrupt flag /
		680	#define TIM_FLAG_CC1 TIM_SR_CC1IF /!< Capture/Compare 1 interrupt flag /
		681	#define TIM_FLAG_CC2 TIM_SR_CC2IF /!< Capture/Compare 2 interrupt flag /
		682	#define TIM_FLAG_CC3 TIM_SR_CC3IF /!< Capture/Compare 3 interrupt flag /
		683	#define TIM_FLAG_CC4 TIM_SR_CC4IF /!< Capture/Compare 4 interrupt flag /
		684	#define TIM_FLAG_COM TIM_SR_COMIF /!< Commutation interrupt flag /
		685	#define TIM_FLAG_TRIGGER TIM_SR_TIF /!< Trigger interrupt flag /
		686	#define TIM_FLAG_BREAK TIM_SR_BIF /!< Break interrupt flag /
		687	#define TIM_FLAG_CC1OF TIM_SR_CC1OF /!< Capture 1 overcapture flag /
		688	#define TIM_FLAG_CC2OF TIM_SR_CC2OF /!< Capture 2 overcapture flag /
		689	#define TIM_FLAG_CC3OF TIM_SR_CC3OF /!< Capture 3 overcapture flag /
		690	#define TIM_FLAG_CC4OF TIM_SR_CC4OF /!< Capture 4 overcapture flag /
		691	/**
		692	* @}
		693	*/
		694
		695	/** @defgroup TIM_Channel TIM Channel
		696	* @{
		697	*/
		698	#define TIM_CHANNEL_1 0x00000000U /!< Capture/compare channel 1 identifier /
		699	#define TIM_CHANNEL_2 0x00000004U /!< Capture/compare channel 2 identifier /
		700	#define TIM_CHANNEL_3 0x00000008U /!< Capture/compare channel 3 identifier /
		701	#define TIM_CHANNEL_4 0x0000000CU /!< Capture/compare channel 4 identifier /
		702	#define TIM_CHANNEL_ALL 0x0000003CU /!< Global Capture/compare channel identifier /
		703	/**
		704	* @}
		705	*/
		706
		707	/** @defgroup TIM_Clock_Source TIM Clock Source
		708	* @{
		709	*/
		710	#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /!< External clock source mode 2 /
		711	#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /!< Internal clock source /
		712	#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /!< External clock source mode 1 (ITR0) /
		713	#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /!< External clock source mode 1 (ITR1) /
		714	#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /!< External clock source mode 1 (ITR2) /
		715	#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /!< External clock source mode 1 (ITR3) /
		716	#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /!< External clock source mode 1 (TTI1FP1 + edge detect.) /
		717	#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /!< External clock source mode 1 (TTI1FP1) /
		718	#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /!< External clock source mode 1 (TTI2FP2) /
		719	#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /!< External clock source mode 1 (ETRF) /
		720	/**
		721	* @}
		722	*/
		723
		724	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
		725	* @{
		726	*/
		727	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
		728	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
		729	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
		730	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
		731	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
		732	/**
		733	* @}
		734	*/
		735
		736	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
		737	* @{
		738	*/
		739	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		740	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
		741	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
		742	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
		743	/**
		744	* @}
		745	*/
		746
		747	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
		748	* @{
		749	*/
		750	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
		751	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
		752	/**
		753	* @}
		754	*/
		755
		756	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
		757	* @{
		758	*/
		759	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		760	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
		761	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
		762	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
		763	/**
		764	* @}
		765	*/
		766
		767	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
		768	* @{
		769	*/
		770	#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
		771	#define TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
		772	/**
		773	* @}
		774	*/
		775
		776	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
		777	* @{
		778	*/
		779	#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
		780	#define TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
		781	/**
		782	* @}
		783	*/
		784	/** @defgroup TIM_Lock_level TIM Lock level
		785	* @{
		786	*/
		787	#define TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF /
		788	#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
		789	#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
		790	#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
		791	/**
		792	* @}
		793	*/
		794
		795	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
		796	* @{
		797	*/
		798	#define TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break input BRK is enabled /
		799	#define TIM_BREAK_DISABLE 0x00000000U /!< Break input BRK is disabled /
		800	/**
		801	* @}
		802	*/
		803
		804	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
		805	* @{
		806	*/
		807	#define TIM_BREAKPOLARITY_LOW 0x00000000U /!< Break input BRK is active low /
		808	#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
		809	/**
		810	* @}
		811	*/
		812
		813	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
		814	* @{
		815	*/
		816	#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
		817	#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
		818	(if none of the break inputs BRK and BRK2 is active) */
		819	/**
		820	* @}
		821	*/
		822
		823	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
		824	* @{
		825	*/
		826	#define TIM_TRGO_RESET 0x00000000U /!< TIMx_EGR.UG bit is used as trigger output (TRGO) /
		827	#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< TIMx_CR1.CEN bit is used as trigger output (TRGO) /
		828	#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output (TRGO) /
		829	#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< Capture or a compare match 1 is used as trigger output (TRGO) /
		830	#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output (TRGO) /
		831	#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output(TRGO) /
		832	#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output(TRGO) /
		833	#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output(TRGO) /
		834	/**
		835	* @}
		836	*/
		837
		838	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
		839	* @{
		840	*/
		841	#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /!< No action /
		842	#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /!< Master/slave mode is selected /
		843	/**
		844	* @}
		845	*/
		846
		847	/** @defgroup TIM_Slave_Mode TIM Slave mode
		848	* @{
		849	*/
		850	#define TIM_SLAVEMODE_DISABLE 0x00000000U /!< Slave mode disabled /
		851	#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode /
		852	#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode /
		853	#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode /
		854	#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< External Clock Mode 1 /
		855	/**
		856	* @}
		857	*/
		858
		859	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
		860	* @{
		861	*/
		862	#define TIM_OCMODE_TIMING 0x00000000U /!< Frozen /
		863	#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!< Set channel to active level on match /
		864	#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!< Set channel to inactive level on match /
		865	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< Toggle /
		866	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!< PWM mode 1 /
		867	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< PWM mode 2 /
		868	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!< Force active level /
		869	#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!< Force inactive level /
		870	/**
		871	* @}
		872	*/
		873
		874	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
		875	* @{
		876	*/
		877	#define TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) /
		878	#define TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) /
		879	#define TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) /
		880	#define TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) /
		881	#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) /
		882	#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 1 (TI1FP1) /
		883	#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 2 (TI2FP2) /
		884	#define TIM_TS_ETRF (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered External Trigger input (ETRF) /
		885	#define TIM_TS_NONE 0x0000FFFFU /!< No trigger selected /
		886	/**
		887	* @}
		888	*/
		889
		890	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
		891	* @{
		892	*/
		893	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
		894	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
		895	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		896	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		897	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
		898	/**
		899	* @}
		900	*/
		901
		902	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
		903	* @{
		904	*/
		905	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		906	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
		907	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
		908	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
		909	/**
		910	* @}
		911	*/
		912
		913	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
		914	* @{
		915	*/
		916	#define TIM_TI1SELECTION_CH1 0x00000000U /!< The TIMx_CH1 pin is connected to TI1 input /
		917	#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) /
		918	/**
		919	* @}
		920	*/
		921
		922	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
		923	* @{
		924	*/
		925	#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA /
		926	#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		927	#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		928	#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		929	#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		930	#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		931	#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		932	#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		933	#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		934	#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		935	#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		936	#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		937	#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		938	#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		939	#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		940	#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		941	#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		942	#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		943	/**
		944	* @}
		945	*/
		946
		947	/** @defgroup DMA_Handle_index TIM DMA Handle Index
		948	* @{
		949	*/
		950	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /!< Index of the DMA handle used for Update DMA requests /
		951	#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
		952	#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
		953	#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
		954	#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
		955	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /!< Index of the DMA handle used for Commutation DMA requests /
		956	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /!< Index of the DMA handle used for Trigger DMA requests /
		957	/**
		958	* @}
		959	*/
		960
		961	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
		962	* @{
		963	*/
		964	#define TIM_CCx_ENABLE 0x00000001U /!< Input or output channel is enabled /
		965	#define TIM_CCx_DISABLE 0x00000000U /!< Input or output channel is disabled /
		966	#define TIM_CCxN_ENABLE 0x00000004U /!< Complementary output channel is enabled /
		967	#define TIM_CCxN_DISABLE 0x00000000U /!< Complementary output channel is enabled /
		968	/**
		969	* @}
		970	*/
		971
		972	/**
		973	* @}
		974	*/
		975	/* End of exported constants -------------------------------------------------*/
		976
		977	/* Exported macros -----------------------------------------------------------*/
		978	/** @defgroup TIM_Exported_Macros TIM Exported Macros
		979	* @{
		980	*/
		981
		982	/** @brief Reset TIM handle state.
		983	* @param __HANDLE__ TIM handle.
		984	* @retval None
		985	*/
		986	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		987	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
		988	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
		989	(__HANDLE__)->Base_MspInitCallback = NULL; \
		990	(__HANDLE__)->Base_MspDeInitCallback = NULL; \
		991	(__HANDLE__)->IC_MspInitCallback = NULL; \
		992	(__HANDLE__)->IC_MspDeInitCallback = NULL; \
		993	(__HANDLE__)->OC_MspInitCallback = NULL; \
		994	(__HANDLE__)->OC_MspDeInitCallback = NULL; \
		995	(__HANDLE__)->PWM_MspInitCallback = NULL; \
		996	(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
		997	(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
		998	(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
		999	(__HANDLE__)->Encoder_MspInitCallback = NULL; \
		1000	(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
		1001	(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
		1002	(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
		1003	} while(0)
		1004	#else
		1005	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
		1006	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1007
		1008	/**
		1009	* @brief Enable the TIM peripheral.
		1010	* @param __HANDLE__ TIM handle
		1011	* @retval None
		1012	*/
		1013	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
		1014
		1015	/**
		1016	* @brief Enable the TIM main Output.
		1017	* @param __HANDLE__ TIM handle
		1018	* @retval None
		1019	*/
		1020	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
		1021
		1022	/**
		1023	* @brief Disable the TIM peripheral.
		1024	* @param __HANDLE__ TIM handle
		1025	* @retval None
		1026	*/
		1027	#define __HAL_TIM_DISABLE(__HANDLE__) \
		1028	do { \
		1029	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
		1030	{ \
		1031	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
		1032	{ \
		1033	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
		1034	} \
		1035	} \
		1036	} while(0)
		1037
		1038	/**
		1039	* @brief Disable the TIM main Output.
		1040	* @param __HANDLE__ TIM handle
		1041	* @retval None
		1042	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
		1043	*/
		1044	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
		1045	do { \
		1046	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
		1047	{ \
		1048	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
		1049	{ \
		1050	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
		1051	} \
		1052	} \
		1053	} while(0)
		1054
		1055	/**
		1056	* @brief Disable the TIM main Output.
		1057	* @param __HANDLE__ TIM handle
		1058	* @retval None
		1059	* @note The Main Output Enable of a timer instance is disabled unconditionally
		1060	*/
		1061	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
		1062
		1063	/** @brief Enable the specified TIM interrupt.
		1064	* @param __HANDLE__ specifies the TIM Handle.
		1065	* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
		1066	* This parameter can be one of the following values:
		1067	* @arg TIM_IT_UPDATE: Update interrupt
		1068	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1069	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1070	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1071	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1072	* @arg TIM_IT_COM: Commutation interrupt
		1073	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1074	* @arg TIM_IT_BREAK: Break interrupt
		1075	* @retval None
		1076	*/
		1077	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
		1078
		1079	/** @brief Disable the specified TIM interrupt.
		1080	* @param __HANDLE__ specifies the TIM Handle.
		1081	* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
		1082	* This parameter can be one of the following values:
		1083	* @arg TIM_IT_UPDATE: Update interrupt
		1084	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1085	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1086	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1087	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1088	* @arg TIM_IT_COM: Commutation interrupt
		1089	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1090	* @arg TIM_IT_BREAK: Break interrupt
		1091	* @retval None
		1092	*/
		1093	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
		1094
		1095	/** @brief Enable the specified DMA request.
		1096	* @param __HANDLE__ specifies the TIM Handle.
		1097	* @param __DMA__ specifies the TIM DMA request to enable.
		1098	* This parameter can be one of the following values:
		1099	* @arg TIM_DMA_UPDATE: Update DMA request
		1100	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
		1101	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		1102	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		1103	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
		1104	* @arg TIM_DMA_COM: Commutation DMA request
		1105	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		1106	* @retval None
		1107	*/
		1108	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
		1109
		1110	/** @brief Disable the specified DMA request.
		1111	* @param __HANDLE__ specifies the TIM Handle.
		1112	* @param __DMA__ specifies the TIM DMA request to disable.
		1113	* This parameter can be one of the following values:
		1114	* @arg TIM_DMA_UPDATE: Update DMA request
		1115	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
		1116	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		1117	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		1118	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
		1119	* @arg TIM_DMA_COM: Commutation DMA request
		1120	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		1121	* @retval None
		1122	*/
		1123	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
		1124
		1125	/** @brief Check whether the specified TIM interrupt flag is set or not.
		1126	* @param __HANDLE__ specifies the TIM Handle.
		1127	* @param __FLAG__ specifies the TIM interrupt flag to check.
		1128	* This parameter can be one of the following values:
		1129	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		1130	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		1131	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		1132	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		1133	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		1134	* @arg TIM_FLAG_COM: Commutation interrupt flag
		1135	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
		1136	* @arg TIM_FLAG_BREAK: Break interrupt flag
		1137	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		1138	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		1139	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		1140	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		1141	* @retval The new state of __FLAG__ (TRUE or FALSE).
		1142	*/
		1143	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
		1144
		1145	/** @brief Clear the specified TIM interrupt flag.
		1146	* @param __HANDLE__ specifies the TIM Handle.
		1147	* @param __FLAG__ specifies the TIM interrupt flag to clear.
		1148	* This parameter can be one of the following values:
		1149	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		1150	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		1151	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		1152	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		1153	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		1154	* @arg TIM_FLAG_COM: Commutation interrupt flag
		1155	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
		1156	* @arg TIM_FLAG_BREAK: Break interrupt flag
		1157	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		1158	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		1159	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		1160	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		1161	* @retval The new state of __FLAG__ (TRUE or FALSE).
		1162	*/
		1163	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
		1164
		1165	/**
		1166	* @brief Check whether the specified TIM interrupt source is enabled or not.
		1167	* @param __HANDLE__ TIM handle
		1168	* @param __INTERRUPT__ specifies the TIM interrupt source to check.
		1169	* This parameter can be one of the following values:
		1170	* @arg TIM_IT_UPDATE: Update interrupt
		1171	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1172	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1173	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1174	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1175	* @arg TIM_IT_COM: Commutation interrupt
		1176	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1177	* @arg TIM_IT_BREAK: Break interrupt
		1178	* @retval The state of TIM_IT (SET or RESET).
		1179	*/
		1180	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
		1181	== (__INTERRUPT__)) ? SET : RESET)
		1182
		1183	/** @brief Clear the TIM interrupt pending bits.
		1184	* @param __HANDLE__ TIM handle
		1185	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
		1186	* This parameter can be one of the following values:
		1187	* @arg TIM_IT_UPDATE: Update interrupt
		1188	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1189	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1190	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1191	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1192	* @arg TIM_IT_COM: Commutation interrupt
		1193	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1194	* @arg TIM_IT_BREAK: Break interrupt
		1195	* @retval None
		1196	*/
		1197	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
		1198
		1199	/**
		1200	* @brief Indicates whether or not the TIM Counter is used as downcounter.
		1201	* @param __HANDLE__ TIM handle.
		1202	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
		1203	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
		1204	mode.
		1205	*/
		1206	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
		1207
		1208	/**
		1209	* @brief Set the TIM Prescaler on runtime.
		1210	* @param __HANDLE__ TIM handle.
		1211	* @param __PRESC__ specifies the Prescaler new value.
		1212	* @retval None
		1213	*/
		1214	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
		1215
		1216	/**
		1217	* @brief Set the TIM Counter Register value on runtime.
		1218	* @param __HANDLE__ TIM handle.
		1219	* @param __COUNTER__ specifies the Counter register new value.
		1220	* @retval None
		1221	*/
		1222	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
		1223
		1224	/**
		1225	* @brief Get the TIM Counter Register value on runtime.
		1226	* @param __HANDLE__ TIM handle.
		1227	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
		1228	*/
		1229	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
		1230
		1231	/**
		1232	* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
		1233	* @param __HANDLE__ TIM handle.
		1234	* @param __AUTORELOAD__ specifies the Counter register new value.
		1235	* @retval None
		1236	*/
		1237	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
		1238	do{ \
		1239	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
		1240	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
		1241	} while(0)
		1242
		1243	/**
		1244	* @brief Get the TIM Autoreload Register value on runtime.
		1245	* @param __HANDLE__ TIM handle.
		1246	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
		1247	*/
		1248	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
		1249
		1250	/**
		1251	* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
		1252	* @param __HANDLE__ TIM handle.
		1253	* @param __CKD__ specifies the clock division value.
		1254	* This parameter can be one of the following value:
		1255	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1256	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
		1257	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
		1258	* @retval None
		1259	*/
		1260	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
		1261	do{ \
		1262	(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
		1263	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
		1264	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
		1265	} while(0)
		1266
		1267	/**
		1268	* @brief Get the TIM Clock Division value on runtime.
		1269	* @param __HANDLE__ TIM handle.
		1270	* @retval The clock division can be one of the following values:
		1271	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1272	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
		1273	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
		1274	*/
		1275	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
		1276
		1277	/**
		1278	* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
		1279	* @param __HANDLE__ TIM handle.
		1280	* @param __CHANNEL__ TIM Channels to be configured.
		1281	* This parameter can be one of the following values:
		1282	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1283	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1284	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1285	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1286	* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
		1287	* This parameter can be one of the following values:
		1288	* @arg TIM_ICPSC_DIV1: no prescaler
		1289	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1290	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1291	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
		1292	* @retval None
		1293	*/
		1294	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
		1295	do{ \
		1296	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
		1297	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
		1298	} while(0)
		1299
		1300	/**
		1301	* @brief Get the TIM Input Capture prescaler on runtime.
		1302	* @param __HANDLE__ TIM handle.
		1303	* @param __CHANNEL__ TIM Channels to be configured.
		1304	* This parameter can be one of the following values:
		1305	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
		1306	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
		1307	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
		1308	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
		1309	* @retval The input capture prescaler can be one of the following values:
		1310	* @arg TIM_ICPSC_DIV1: no prescaler
		1311	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1312	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1313	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
		1314	*/
		1315	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
		1316	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
		1317	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
		1318	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
		1319	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
		1320
		1321	/**
		1322	* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
		1323	* @param __HANDLE__ TIM handle.
		1324	* @param __CHANNEL__ TIM Channels to be configured.
		1325	* This parameter can be one of the following values:
		1326	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1327	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1328	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1329	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1330	* @param __COMPARE__ specifies the Capture Compare register new value.
		1331	* @retval None
		1332	*/
		1333	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
		1334	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
		1335	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
		1336	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
		1337	((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
		1338
		1339	/**
		1340	* @brief Get the TIM Capture Compare Register value on runtime.
		1341	* @param __HANDLE__ TIM handle.
		1342	* @param __CHANNEL__ TIM Channel associated with the capture compare register
		1343	* This parameter can be one of the following values:
		1344	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
		1345	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
		1346	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
		1347	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
		1348	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
		1349	*/
		1350	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
		1351	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
		1352	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
		1353	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
		1354	((__HANDLE__)->Instance->CCR4))
		1355
		1356	/**
		1357	* @brief Set the TIM Output compare preload.
		1358	* @param __HANDLE__ TIM handle.
		1359	* @param __CHANNEL__ TIM Channels to be configured.
		1360	* This parameter can be one of the following values:
		1361	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1362	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1363	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1364	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1365	* @retval None
		1366	*/
		1367	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1368	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
		1369	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
		1370	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
		1371	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE))
		1372
		1373	/**
		1374	* @brief Reset the TIM Output compare preload.
		1375	* @param __HANDLE__ TIM handle.
		1376	* @param __CHANNEL__ TIM Channels to be configured.
		1377	* This parameter can be one of the following values:
		1378	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1379	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1380	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1381	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1382	* @retval None
		1383	*/
		1384	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1385	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
		1386	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
		1387	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
		1388	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
		1389
		1390	/**
		1391	* @brief Enable fast mode for a given channel.
		1392	* @param __HANDLE__ TIM handle.
		1393	* @param __CHANNEL__ TIM Channels to be configured.
		1394	* This parameter can be one of the following values:
		1395	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1396	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1397	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1398	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1399	* @note When fast mode is enabled an active edge on the trigger input acts
		1400	* like a compare match on CCx output. Delay to sample the trigger
		1401	* input and to activate CCx output is reduced to 3 clock cycles.
		1402	* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
		1403	* @retval None
		1404	*/
		1405	#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1406	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1FE) :\
		1407	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2FE) :\
		1408	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3FE) :\
		1409	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4FE))
		1410
		1411	/**
		1412	* @brief Disable fast mode for a given channel.
		1413	* @param __HANDLE__ TIM handle.
		1414	* @param __CHANNEL__ TIM Channels to be configured.
		1415	* This parameter can be one of the following values:
		1416	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1417	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1418	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1419	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1420	* @note When fast mode is disabled CCx output behaves normally depending
		1421	* on counter and CCRx values even when the trigger is ON. The minimum
		1422	* delay to activate CCx output when an active edge occurs on the
		1423	* trigger input is 5 clock cycles.
		1424	* @retval None
		1425	*/
		1426	#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1427	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
		1428	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
		1429	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
		1430	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
		1431
		1432	/**
		1433	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
		1434	* @param __HANDLE__ TIM handle.
		1435	* @note When the URS bit of the TIMx_CR1 register is set, only counter
		1436	* overflow/underflow generates an update interrupt or DMA request (if
		1437	* enabled)
		1438	* @retval None
		1439	*/
		1440	#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|= TIM_CR1_URS)
		1441
		1442	/**
		1443	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
		1444	* @param __HANDLE__ TIM handle.
		1445	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
		1446	* following events generate an update interrupt or DMA request (if
		1447	* enabled):
		1448	* _ Counter overflow underflow
		1449	* _ Setting the UG bit
		1450	* _ Update generation through the slave mode controller
		1451	* @retval None
		1452	*/
		1453	#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
		1454
		1455	/**
		1456	* @brief Set the TIM Capture x input polarity on runtime.
		1457	* @param __HANDLE__ TIM handle.
		1458	* @param __CHANNEL__ TIM Channels to be configured.
		1459	* This parameter can be one of the following values:
		1460	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1461	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1462	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1463	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1464	* @param __POLARITY__ Polarity for TIx source
		1465	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
		1466	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
		1467	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
		1468	* @retval None
		1469	*/
		1470	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
		1471	do{ \
		1472	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
		1473	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
		1474	}while(0)
		1475
		1476	/**
		1477	* @}
		1478	*/
		1479	/* End of exported macros ----------------------------------------------------*/
		1480
		1481	/* Private constants ---------------------------------------------------------*/
		1482	/** @defgroup TIM_Private_Constants TIM Private Constants
		1483	* @{
		1484	*/
		1485	/* The counter of a timer instance is disabled only if all the CCx and CCxN
		1486	channels have been disabled */
		1487	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
		1488	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
		1489	/**
		1490	* @}
		1491	*/
		1492	/* End of private constants --------------------------------------------------*/
		1493
		1494	/* Private macros ------------------------------------------------------------*/
		1495	/** @defgroup TIM_Private_Macros TIM Private Macros
		1496	* @{
		1497	*/
		1498	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
		1499	((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
		1500
		1501	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
		1502	((__BASE__) == TIM_DMABASE_CR2) \|\| \
		1503	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
		1504	((__BASE__) == TIM_DMABASE_DIER) \|\| \
		1505	((__BASE__) == TIM_DMABASE_SR) \|\| \
		1506	((__BASE__) == TIM_DMABASE_EGR) \|\| \
		1507	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
		1508	((__BASE__) == TIM_DMABASE_CCMR2) \|\| \
		1509	((__BASE__) == TIM_DMABASE_CCER) \|\| \
		1510	((__BASE__) == TIM_DMABASE_CNT) \|\| \
		1511	((__BASE__) == TIM_DMABASE_PSC) \|\| \
		1512	((__BASE__) == TIM_DMABASE_ARR) \|\| \
		1513	((__BASE__) == TIM_DMABASE_RCR) \|\| \
		1514	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
		1515	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
		1516	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
		1517	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
		1518	((__BASE__) == TIM_DMABASE_BDTR))
		1519
		1520	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1521
		1522	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
		1523	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
		1524	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
		1525	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
		1526	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
		1527
		1528	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
		1529	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
		1530	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
		1531
		1532	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
		1533	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
		1534
		1535	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
		1536	((__STATE__) == TIM_OCFAST_ENABLE))
		1537
		1538	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
		1539	((__POLARITY__) == TIM_OCPOLARITY_LOW))
		1540
		1541	#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) \|\| \
		1542	((__POLARITY__) == TIM_OCNPOLARITY_LOW))
		1543
		1544	#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) \|\| \
		1545	((__STATE__) == TIM_OCIDLESTATE_RESET))
		1546
		1547	#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) \|\| \
		1548	((__STATE__) == TIM_OCNIDLESTATE_RESET))
		1549
		1550	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
		1551	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
		1552	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
		1553
		1554	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
		1555	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
		1556	((__SELECTION__) == TIM_ICSELECTION_TRC))
		1557
		1558	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
		1559	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
		1560	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
		1561	((__PRESCALER__) == TIM_ICPSC_DIV8))
		1562
		1563	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
		1564	((__MODE__) == TIM_OPMODE_REPETITIVE))
		1565
		1566	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
		1567	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
		1568	((__MODE__) == TIM_ENCODERMODE_TI12))
		1569
		1570	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1571
		1572	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1573	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
		1574	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
		1575	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
		1576	((__CHANNEL__) == TIM_CHANNEL_ALL))
		1577
		1578	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1579	((__CHANNEL__) == TIM_CHANNEL_2))
		1580
		1581	#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1582	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
		1583	((__CHANNEL__) == TIM_CHANNEL_3))
		1584
		1585	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
		1586	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
		1587	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
		1588	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
		1589	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
		1590	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
		1591	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
		1592	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
		1593	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
		1594	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
		1595
		1596	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
		1597	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
		1598	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
		1599	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
		1600	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
		1601
		1602	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
		1603	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
		1604	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
		1605	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
		1606
		1607	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1608
		1609	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
		1610	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
		1611
		1612	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
		1613	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
		1614	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
		1615	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
		1616
		1617	#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1618
		1619	#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) \|\| \
		1620	((__STATE__) == TIM_OSSR_DISABLE))
		1621
		1622	#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) \|\| \
		1623	((__STATE__) == TIM_OSSI_DISABLE))
		1624
		1625	#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) \|\| \
		1626	((__LEVEL__) == TIM_LOCKLEVEL_1) \|\| \
		1627	((__LEVEL__) == TIM_LOCKLEVEL_2) \|\| \
		1628	((__LEVEL__) == TIM_LOCKLEVEL_3))
		1629
		1630	#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
		1631
		1632
		1633	#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) \|\| \
		1634	((__STATE__) == TIM_BREAK_DISABLE))
		1635
		1636	#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) \|\| \
		1637	((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
		1638
		1639	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
		1640	((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
		1641
		1642	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
		1643	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
		1644	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
		1645	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
		1646	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
		1647	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
		1648	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
		1649	((__SOURCE__) == TIM_TRGO_OC4REF))
		1650
		1651	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
		1652	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
		1653
		1654	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
		1655	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
		1656	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
		1657	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
		1658	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
		1659
		1660	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
		1661	((__MODE__) == TIM_OCMODE_PWM2))
		1662
		1663	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
		1664	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
		1665	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
		1666	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
		1667	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
		1668	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
		1669
		1670	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1671	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1672	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1673	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1674	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
		1675	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
		1676	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
		1677	((__SELECTION__) == TIM_TS_ETRF))
		1678
		1679	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1680	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1681	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1682	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1683	((__SELECTION__) == TIM_TS_NONE))
		1684
		1685	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
		1686	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
		1687	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
		1688	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
		1689	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
		1690
		1691	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
		1692	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
		1693	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
		1694	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
		1695
		1696	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1697
		1698	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
		1699	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
		1700
		1701	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
		1702	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
		1703	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
		1704	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
		1705	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
		1706	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
		1707	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
		1708	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
		1709	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
		1710	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
		1711	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
		1712	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
		1713	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
		1714	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
		1715	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
		1716	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
		1717	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
		1718	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
		1719
		1720	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1721
		1722	#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
		1723
		1724	#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
		1725
		1726	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
		1727	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
		1728	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
		1729	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
		1730	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
		1731
		1732	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
		1733	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
		1734	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
		1735	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
		1736	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
		1737
		1738	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
		1739	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
		1740	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
		1741	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
		1742	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U))))
		1743
		1744	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
		1745	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP))) :\
		1746	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
		1747	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
		1748	((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
		1749
		1750	/**
		1751	* @}
		1752	*/
		1753	/* End of private macros -----------------------------------------------------*/
		1754
		1755	/* Include TIM HAL Extended module */
		1756	#include "stm32f1xx_hal_tim_ex.h"
		1757
		1758	/* Exported functions --------------------------------------------------------*/
		1759	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
		1760	* @{
		1761	*/
		1762
		1763	/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
		1764	* @brief Time Base functions
		1765	* @{
		1766	*/
		1767	/* Time Base functions ********************************************************/
		1768	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
		1769	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
		1770	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
		1771	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
		1772	/* Blocking mode: Polling */
		1773	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
		1774	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
		1775	/* Non-Blocking mode: Interrupt */
		1776	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
		1777	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
		1778	/* Non-Blocking mode: DMA */
		1779	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
		1780	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
		1781	/**
		1782	* @}
		1783	*/
		1784
		1785	/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
		1786	* @brief TIM Output Compare functions
		1787	* @{
		1788	*/
		1789	/* Timer Output Compare functions *********************************************/
		1790	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
		1791	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
		1792	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
		1793	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
		1794	/* Blocking mode: Polling */
		1795	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1796	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1797	/* Non-Blocking mode: Interrupt */
		1798	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1799	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1800	/* Non-Blocking mode: DMA */
		1801	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1802	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1803	/**
		1804	* @}
		1805	*/
		1806
		1807	/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
		1808	* @brief TIM PWM functions
		1809	* @{
		1810	*/
		1811	/* Timer PWM functions ********************************************************/
		1812	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
		1813	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
		1814	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
		1815	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
		1816	/* Blocking mode: Polling */
		1817	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1818	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1819	/* Non-Blocking mode: Interrupt */
		1820	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1821	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1822	/* Non-Blocking mode: DMA */
		1823	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1824	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1825	/**
		1826	* @}
		1827	*/
		1828
		1829	/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
		1830	* @brief TIM Input Capture functions
		1831	* @{
		1832	*/
		1833	/* Timer Input Capture functions **********************************************/
		1834	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
		1835	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
		1836	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
		1837	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
		1838	/* Blocking mode: Polling */
		1839	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1840	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1841	/* Non-Blocking mode: Interrupt */
		1842	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1843	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1844	/* Non-Blocking mode: DMA */
		1845	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1846	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1847	/**
		1848	* @}
		1849	*/
		1850
		1851	/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
		1852	* @brief TIM One Pulse functions
		1853	* @{
		1854	*/
		1855	/* Timer One Pulse functions **************************************************/
		1856	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
		1857	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
		1858	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
		1859	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
		1860	/* Blocking mode: Polling */
		1861	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1862	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1863	/* Non-Blocking mode: Interrupt */
		1864	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1865	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1866	/**
		1867	* @}
		1868	*/
		1869
		1870	/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
		1871	* @brief TIM Encoder functions
		1872	* @{
		1873	*/
		1874	/* Timer Encoder functions ****************************************************/
		1875	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
		1876	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
		1877	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
		1878	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
		1879	/* Blocking mode: Polling */
		1880	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1881	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1882	/* Non-Blocking mode: Interrupt */
		1883	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1884	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1885	/* Non-Blocking mode: DMA */
		1886	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1,
		1887	uint32_t *pData2, uint16_t Length);
		1888	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1889	/**
		1890	* @}
		1891	*/
		1892
		1893	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
		1894	* @brief IRQ handler management
		1895	* @{
		1896	*/
		1897	/* Interrupt Handler functions ***********************************************/
		1898	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
		1899	/**
		1900	* @}
		1901	*/
		1902
		1903	/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
		1904	* @brief Peripheral Control functions
		1905	* @{
		1906	*/
		1907	/* Control functions *********************************************************/
		1908	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		1909	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		1910	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
		1911	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig,
		1912	uint32_t OutputChannel, uint32_t InputChannel);
		1913	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig,
		1914	uint32_t Channel);
		1915	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
		1916	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
		1917	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		1918	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		1919	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		1920	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		1921	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
		1922	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		1923	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		1924	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
		1925	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
		1926	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
		1927	/**
		1928	* @}
		1929	*/
		1930
		1931	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
		1932	* @brief TIM Callbacks functions
		1933	* @{
		1934	*/
		1935	/* Callback in non blocking modes (Interrupt and DMA) *************************/
		1936	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
		1937	void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
		1938	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
		1939	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
		1940	void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
		1941	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
		1942	void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
		1943	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
		1944	void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
		1945	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
		1946
		1947	/* Callbacks Register/UnRegister functions ***********************************/
		1948	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1949	HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
		1950	pTIM_CallbackTypeDef pCallback);
		1951	HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
		1952	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1953
		1954	/**
		1955	* @}
		1956	*/
		1957
		1958	/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
		1959	* @brief Peripheral State functions
		1960	* @{
		1961	*/
		1962	/* Peripheral State functions ************************************************/
		1963	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
		1964	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
		1965	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
		1966	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
		1967	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
		1968	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
		1969	/**
		1970	* @}
		1971	*/
		1972
		1973	/**
		1974	* @}
		1975	*/
		1976	/* End of exported functions -------------------------------------------------*/
		1977
		1978	/* Private functions----------------------------------------------------------*/
		1979	/** @defgroup TIM_Private_Functions TIM Private Functions
		1980	* @{
		1981	*/
		1982	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
		1983	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
		1984	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		1985	void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
		1986	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
		1987
		1988	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
		1989	void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
		1990	void TIM_DMAError(DMA_HandleTypeDef *hdma);
		1991	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
		1992	void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
		1993	void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
		1994
		1995	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1996	void TIM_ResetCallback(TIM_HandleTypeDef *htim);
		1997	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1998
		1999	/**
		2000	* @}
		2001	*/
		2002	/* End of private functions --------------------------------------------------*/
		2003
		2004	/**
		2005	* @}
		2006	*/
		2007
		2008	/**
		2009	* @}
		2010	*/
		2011
		2012	#ifdef __cplusplus
		2013	}
		2014	#endif
		2015
		2016	#endif /* STM32F1xx_HAL_TIM_H */
		2017
		2018	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories dashGPS

(root)/branches/dashGPS-bmp/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h – Rev 18