WebSVN – dashGPS – Blame – /branches/dashGPS-bmp/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_adc.h
		4	* @author MCD Application Team
		5	* @brief Header file containing functions prototypes of ADC HAL library.
		6	******************************************************************************
		7	* @attention
		8	*
		9	*
		10	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		11	* All rights reserved.</center></h2>
		12	*
		13	* This software component is licensed by ST under BSD 3-Clause license,
		14	* the "License"; You may not use this file except in compliance with the
		15	* License. You may obtain a copy of the License at:
		16	* opensource.org/licenses/BSD-3-Clause
		17	*
		18	******************************************************************************
		19	*/
		20
		21	/* Define to prevent recursive inclusion -------------------------------------*/
		22	#ifndef __STM32F1xx_HAL_ADC_H
		23	#define __STM32F1xx_HAL_ADC_H
		24
		25	#ifdef __cplusplus
		26	extern "C" {
		27	#endif
		28
		29	/* Includes ------------------------------------------------------------------*/
		30	#include "stm32f1xx_hal_def.h"
		31	/** @addtogroup STM32F1xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup ADC
		36	* @{
		37	*/
		38
		39	/* Exported types ------------------------------------------------------------*/
		40	/** @defgroup ADC_Exported_Types ADC Exported Types
		41	* @{
		42	*/
		43
		44	/**
		45	* @brief Structure definition of ADC and regular group initialization
		46	* @note Parameters of this structure are shared within 2 scopes:
		47	* - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
		48	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
		49	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
		50	* ADC can be either disabled or enabled without conversion on going on regular group.
		51	*/
		52	typedef struct
		53	{
		54	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
		55	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
		56	This parameter can be a value of @ref ADC_Data_align */
		57	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
		58	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
		59	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
		60	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
		61	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
		62	Scan direction is upward: from rank1 to rank 'n'.
		63	This parameter can be a value of @ref ADC_Scan_mode
		64	Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
		65	or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
		66	the last conversion of the sequence. All previous conversions would be overwritten by the last one.
		67	Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
		68	FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
		69	after the selected trigger occurred (software start or external trigger).
		70	This parameter can be set to ENABLE or DISABLE. */
		71	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
		72	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
		73	This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
		74	FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
		75	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
		76	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
		77	This parameter can be set to ENABLE or DISABLE. */
		78	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
		79	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
		80	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
		81	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
		82	If set to ADC_SOFTWARE_START, external triggers are disabled.
		83	If set to external trigger source, triggering is on event rising edge.
		84	This parameter can be a value of @ref ADC_External_trigger_source_Regular */
		85	}ADC_InitTypeDef;
		86
		87	/**
		88	* @brief Structure definition of ADC channel for regular group
		89	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
		90	* ADC can be either disabled or enabled without conversion on going on regular group.
		91	*/
		92	typedef struct
		93	{
		94	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
		95	This parameter can be a value of @ref ADC_channels
		96	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
		97	Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
		98	Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
		99	It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
		100	Refer to errata sheet of these devices for more details. */
		101	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
		102	This parameter can be a value of @ref ADC_regular_rank
		103	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
		104	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
		105	Unit: ADC clock cycles
		106	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
		107	This parameter can be a value of @ref ADC_sampling_times
		108	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
		109	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
		110	Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
		111	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
		112	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
		113	}ADC_ChannelConfTypeDef;
		114
		115	/**
		116	* @brief ADC Configuration analog watchdog definition
		117	* @note The setting of these parameters with function is conditioned to ADC state.
		118	* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
		119	*/
		120	typedef struct
		121	{
		122	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
		123	This parameter can be a value of @ref ADC_analog_watchdog_mode. */
		124	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
		125	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
		126	This parameter can be a value of @ref ADC_channels. */
		127	FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
		128	This parameter can be set to ENABLE or DISABLE */
		129	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		130	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		131	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		132	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		133	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
		134	}ADC_AnalogWDGConfTypeDef;
		135
		136	/**
		137	* @brief HAL ADC state machine: ADC states definition (bitfields)
		138	*/
		139	/* States of ADC global scope */
		140	#define HAL_ADC_STATE_RESET 0x00000000U /!< ADC not yet initialized or disabled /
		141	#define HAL_ADC_STATE_READY 0x00000001U /!< ADC peripheral ready for use /
		142	#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /!< ADC is busy to internal process (initialization, calibration) /
		143	#define HAL_ADC_STATE_TIMEOUT 0x00000004U /!< TimeOut occurrence /
		144
		145	/* States of ADC errors */
		146	#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /!< Internal error occurrence /
		147	#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /!< Configuration error occurrence /
		148	#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /!< DMA error occurrence /
		149
		150	/* States of ADC group regular */
		151	#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
		152	external trigger, low power auto power-on, multimode ADC master control) */
		153	#define HAL_ADC_STATE_REG_EOC 0x00000200U /!< Conversion data available on group regular /
		154	#define HAL_ADC_STATE_REG_OVR 0x00000400U /!< Not available on STM32F1 device: Overrun occurrence /
		155	#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /!< Not available on STM32F1 device: End Of Sampling flag raised /
		156
		157	/* States of ADC group injected */
		158	#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
		159	external trigger, low power auto power-on, multimode ADC master control) */
		160	#define HAL_ADC_STATE_INJ_EOC 0x00002000U /!< Conversion data available on group injected /
		161	#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /!< Not available on STM32F1 device: Injected queue overflow occurrence /
		162
		163	/* States of ADC analog watchdogs */
		164	#define HAL_ADC_STATE_AWD1 0x00010000U /!< Out-of-window occurrence of analog watchdog 1 /
		165	#define HAL_ADC_STATE_AWD2 0x00020000U /!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 /
		166	#define HAL_ADC_STATE_AWD3 0x00040000U /!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 /
		167
		168	/* States of ADC multi-mode */
		169	#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /!< ADC in multimode slave state, controlled by another ADC master ( /
		170
		171
		172	/**
		173	* @brief ADC handle Structure definition
		174	*/
		175	typedef struct __ADC_HandleTypeDef
		176	{
		177	ADC_TypeDef Instance; /!< Register base address */
		178
		179	ADC_InitTypeDef Init; /!< ADC required parameters /
		180
		181	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
		182
		183	HAL_LockTypeDef Lock; /!< ADC locking object /
		184
		185	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
		186
		187	__IO uint32_t ErrorCode; /!< ADC Error code /
		188
		189	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		190	void (* ConvCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC conversion complete callback */
		191	void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC conversion DMA half-transfer callback */
		192	void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC analog watchdog 1 callback */
		193	void (* ErrorCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC error callback */
		194	void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC group injected conversion complete callback / /!< ADC end of sampling callback */
		195	void (* MspInitCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC Msp Init callback */
		196	void (* MspDeInitCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC Msp DeInit callback */
		197	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		198	}ADC_HandleTypeDef;
		199
		200
		201	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		202	/**
		203	* @brief HAL ADC Callback ID enumeration definition
		204	*/
		205	typedef enum
		206	{
		207	HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /!< ADC conversion complete callback ID /
		208	HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /!< ADC conversion DMA half-transfer callback ID /
		209	HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /!< ADC analog watchdog 1 callback ID /
		210	HAL_ADC_ERROR_CB_ID = 0x03U, /!< ADC error callback ID /
		211	HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /!< ADC group injected conversion complete callback ID /
		212	HAL_ADC_MSPINIT_CB_ID = 0x09U, /!< ADC Msp Init callback ID /
		213	HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /!< ADC Msp DeInit callback ID /
		214	} HAL_ADC_CallbackIDTypeDef;
		215
		216	/**
		217	* @brief HAL ADC Callback pointer definition
		218	*/
		219	typedef void (pADC_CallbackTypeDef)(ADC_HandleTypeDef hadc); /!< pointer to a ADC callback function /
		220
		221	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		222
		223	/**
		224	* @}
		225	*/
		226
		227
		228
		229	/* Exported constants --------------------------------------------------------*/
		230
		231	/** @defgroup ADC_Exported_Constants ADC Exported Constants
		232	* @{
		233	*/
		234
		235	/** @defgroup ADC_Error_Code ADC Error Code
		236	* @{
		237	*/
		238	#define HAL_ADC_ERROR_NONE 0x00U /!< No error /
		239	#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
		240	enable/disable, erroneous state */
		241	#define HAL_ADC_ERROR_OVR 0x02U /!< Overrun error /
		242	#define HAL_ADC_ERROR_DMA 0x04U /!< DMA transfer error /
		243
		244	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		245	#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /!< Invalid Callback error /
		246	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		247	/**
		248	* @}
		249	*/
		250
		251
		252	/** @defgroup ADC_Data_align ADC data alignment
		253	* @{
		254	*/
		255	#define ADC_DATAALIGN_RIGHT 0x00000000U
		256	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
		257	/**
		258	* @}
		259	*/
		260
		261	/** @defgroup ADC_Scan_mode ADC scan mode
		262	* @{
		263	*/
		264	/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
		265	/* compatibility with other STM32 devices having a sequencer with */
		266	/* additional options. */
		267	#define ADC_SCAN_DISABLE 0x00000000U
		268	#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
		269	/**
		270	* @}
		271	*/
		272
		273	/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
		274	* @{
		275	*/
		276	#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
		277	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
		278	/**
		279	* @}
		280	*/
		281
		282	/** @defgroup ADC_channels ADC channels
		283	* @{
		284	*/
		285	/* Note: Depending on devices, some channels may not be available on package */
		286	/* pins. Refer to device datasheet for channels availability. */
		287	#define ADC_CHANNEL_0 0x00000000U
		288	#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
		289	#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
		290	#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		291	#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
		292	#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
		293	#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
		294	#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		295	#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
		296	#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_0))
		297	#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 ))
		298	#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		299	#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 ))
		300	#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
		301	#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
		302	#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		303	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
		304	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 \| ADC_SQR3_SQ1_0))
		305
		306	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
		307	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
		308	/**
		309	* @}
		310	*/
		311
		312	/** @defgroup ADC_sampling_times ADC sampling times
		313	* @{
		314	*/
		315	#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /!< Sampling time 1.5 ADC clock cycle /
		316	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /!< Sampling time 7.5 ADC clock cycles /
		317	#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /!< Sampling time 13.5 ADC clock cycles /
		318	#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 28.5 ADC clock cycles /
		319	#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /!< Sampling time 41.5 ADC clock cycles /
		320	#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 55.5 ADC clock cycles /
		321	#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 )) /!< Sampling time 71.5 ADC clock cycles /
		322	#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 239.5 ADC clock cycles /
		323	/**
		324	* @}
		325	*/
		326
		327	/** @defgroup ADC_regular_rank ADC rank into regular group
		328	* @{
		329	*/
		330	#define ADC_REGULAR_RANK_1 0x00000001U
		331	#define ADC_REGULAR_RANK_2 0x00000002U
		332	#define ADC_REGULAR_RANK_3 0x00000003U
		333	#define ADC_REGULAR_RANK_4 0x00000004U
		334	#define ADC_REGULAR_RANK_5 0x00000005U
		335	#define ADC_REGULAR_RANK_6 0x00000006U
		336	#define ADC_REGULAR_RANK_7 0x00000007U
		337	#define ADC_REGULAR_RANK_8 0x00000008U
		338	#define ADC_REGULAR_RANK_9 0x00000009U
		339	#define ADC_REGULAR_RANK_10 0x0000000AU
		340	#define ADC_REGULAR_RANK_11 0x0000000BU
		341	#define ADC_REGULAR_RANK_12 0x0000000CU
		342	#define ADC_REGULAR_RANK_13 0x0000000DU
		343	#define ADC_REGULAR_RANK_14 0x0000000EU
		344	#define ADC_REGULAR_RANK_15 0x0000000FU
		345	#define ADC_REGULAR_RANK_16 0x00000010U
		346	/**
		347	* @}
		348	*/
		349
		350	/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
		351	* @{
		352	*/
		353	#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
		354	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
		355	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
		356	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		357	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
		358	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
		359	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		360	/**
		361	* @}
		362	*/
		363
		364	/** @defgroup ADC_conversion_group ADC conversion group
		365	* @{
		366	*/
		367	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
		368	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
		369	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
		370	/**
		371	* @}
		372	*/
		373
		374	/** @defgroup ADC_Event_type ADC Event type
		375	* @{
		376	*/
		377	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /!< ADC Analog watchdog event /
		378
		379	#define ADC_AWD1_EVENT ADC_AWD_EVENT /!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs /
		380	/**
		381	* @}
		382	*/
		383
		384	/** @defgroup ADC_interrupts_definition ADC interrupts definition
		385	* @{
		386	*/
		387	#define ADC_IT_EOC ADC_CR1_EOCIE /!< ADC End of Regular Conversion interrupt source /
		388	#define ADC_IT_JEOC ADC_CR1_JEOCIE /!< ADC End of Injected Conversion interrupt source /
		389	#define ADC_IT_AWD ADC_CR1_AWDIE /!< ADC Analog watchdog interrupt source /
		390	/**
		391	* @}
		392	*/
		393
		394	/** @defgroup ADC_flags_definition ADC flags definition
		395	* @{
		396	*/
		397	#define ADC_FLAG_STRT ADC_SR_STRT /!< ADC Regular group start flag /
		398	#define ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC Injected group start flag /
		399	#define ADC_FLAG_EOC ADC_SR_EOC /!< ADC End of Regular conversion flag /
		400	#define ADC_FLAG_JEOC ADC_SR_JEOC /!< ADC End of Injected conversion flag /
		401	#define ADC_FLAG_AWD ADC_SR_AWD /!< ADC Analog watchdog flag /
		402	/**
		403	* @}
		404	*/
		405
		406
		407	/**
		408	* @}
		409	*/
		410
		411	/* Private constants ---------------------------------------------------------*/
		412
		413	/** @addtogroup ADC_Private_Constants ADC Private Constants
		414	* @{
		415	*/
		416
		417	/** @defgroup ADC_conversion_cycles ADC conversion cycles
		418	* @{
		419	*/
		420	/* ADC conversion cycles (unit: ADC clock cycles) */
		421	/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
		422	/* resolution 12 bits) */
		423	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
		424	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
		425	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
		426	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
		427	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
		428	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
		429	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
		430	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
		431	/**
		432	* @}
		433	*/
		434
		435	/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
		436	* @{
		437	*/
		438	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
		439	(ADC_SMPR2_SMP9_2 \| ADC_SMPR2_SMP8_2 \| ADC_SMPR2_SMP7_2 \| ADC_SMPR2_SMP6_2 \| \
		440	ADC_SMPR2_SMP5_2 \| ADC_SMPR2_SMP4_2 \| ADC_SMPR2_SMP3_2 \| ADC_SMPR2_SMP2_2 \| \
		441	ADC_SMPR2_SMP1_2 \| ADC_SMPR2_SMP0_2)
		442	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
		443	(ADC_SMPR1_SMP17_2 \| ADC_SMPR1_SMP16_2 \| ADC_SMPR1_SMP15_2 \| ADC_SMPR1_SMP14_2 \| \
		444	ADC_SMPR1_SMP13_2 \| ADC_SMPR1_SMP12_2 \| ADC_SMPR1_SMP11_2 \| ADC_SMPR1_SMP10_2 )
		445
		446	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
		447	(ADC_SMPR2_SMP9_1 \| ADC_SMPR2_SMP8_1 \| ADC_SMPR2_SMP7_1 \| ADC_SMPR2_SMP6_1 \| \
		448	ADC_SMPR2_SMP5_1 \| ADC_SMPR2_SMP4_1 \| ADC_SMPR2_SMP3_1 \| ADC_SMPR2_SMP2_1 \| \
		449	ADC_SMPR2_SMP1_1 \| ADC_SMPR2_SMP0_1)
		450	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
		451	(ADC_SMPR1_SMP17_1 \| ADC_SMPR1_SMP16_1 \| ADC_SMPR1_SMP15_1 \| ADC_SMPR1_SMP14_1 \| \
		452	ADC_SMPR1_SMP13_1 \| ADC_SMPR1_SMP12_1 \| ADC_SMPR1_SMP11_1 \| ADC_SMPR1_SMP10_1 )
		453
		454	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
		455	(ADC_SMPR2_SMP9_0 \| ADC_SMPR2_SMP8_0 \| ADC_SMPR2_SMP7_0 \| ADC_SMPR2_SMP6_0 \| \
		456	ADC_SMPR2_SMP5_0 \| ADC_SMPR2_SMP4_0 \| ADC_SMPR2_SMP3_0 \| ADC_SMPR2_SMP2_0 \| \
		457	ADC_SMPR2_SMP1_0 \| ADC_SMPR2_SMP0_0)
		458	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
		459	(ADC_SMPR1_SMP17_0 \| ADC_SMPR1_SMP16_0 \| ADC_SMPR1_SMP15_0 \| ADC_SMPR1_SMP14_0 \| \
		460	ADC_SMPR1_SMP13_0 \| ADC_SMPR1_SMP12_0 \| ADC_SMPR1_SMP11_0 \| ADC_SMPR1_SMP10_0 )
		461
		462	#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
		463	#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		464	#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
		465	#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		466	#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
		467	#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		468	#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
		469	#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		470
		471	#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
		472	#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		473	#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
		474	#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		475	#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
		476	#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		477	#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
		478	#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		479	/**
		480	* @}
		481	*/
		482
		483	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
		484	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD )
		485
		486	/**
		487	* @}
		488	*/
		489
		490
		491	/* Exported macro ------------------------------------------------------------*/
		492
		493	/** @defgroup ADC_Exported_Macros ADC Exported Macros
		494	* @{
		495	*/
		496	/* Macro for internal HAL driver usage, and possibly can be used into code of */
		497	/* final user. */
		498
		499	/**
		500	* @brief Enable the ADC peripheral
		501	* @note ADC enable requires a delay for ADC stabilization time
		502	* (refer to device datasheet, parameter tSTAB)
		503	* @note On STM32F1, if ADC is already enabled this macro trigs a conversion
		504	* SW start on regular group.
		505	* @param __HANDLE__: ADC handle
		506	* @retval None
		507	*/
		508	#define __HAL_ADC_ENABLE(__HANDLE__) \
		509	(SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
		510
		511	/**
		512	* @brief Disable the ADC peripheral
		513	* @param __HANDLE__: ADC handle
		514	* @retval None
		515	*/
		516	#define __HAL_ADC_DISABLE(__HANDLE__) \
		517	(CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
		518
		519	/** @brief Enable the ADC end of conversion interrupt.
		520	* @param __HANDLE__: ADC handle
		521	* @param __INTERRUPT__: ADC Interrupt
		522	* This parameter can be any combination of the following values:
		523	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		524	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		525	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		526	* @retval None
		527	*/
		528	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
		529	(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		530
		531	/** @brief Disable the ADC end of conversion interrupt.
		532	* @param __HANDLE__: ADC handle
		533	* @param __INTERRUPT__: ADC Interrupt
		534	* This parameter can be any combination of the following values:
		535	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		536	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		537	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		538	* @retval None
		539	*/
		540	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
		541	(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		542
		543	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
		544	* @param __HANDLE__: ADC handle
		545	* @param __INTERRUPT__: ADC interrupt source to check
		546	* This parameter can be any combination of the following values:
		547	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		548	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		549	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		550	* @retval None
		551	*/
		552	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
		553	(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
		554
		555	/** @brief Get the selected ADC's flag status.
		556	* @param __HANDLE__: ADC handle
		557	* @param __FLAG__: ADC flag
		558	* This parameter can be any combination of the following values:
		559	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		560	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		561	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		562	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		563	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		564	* @retval None
		565	*/
		566	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
		567	((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
		568
		569	/** @brief Clear the ADC's pending flags
		570	* @param __HANDLE__: ADC handle
		571	* @param __FLAG__: ADC flag
		572	* This parameter can be any combination of the following values:
		573	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		574	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		575	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		576	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		577	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		578	* @retval None
		579	*/
		580	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
		581	(WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
		582
		583	/** @brief Reset ADC handle state
		584	* @param __HANDLE__: ADC handle
		585	* @retval None
		586	*/
		587	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		588	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
		589	do{ \
		590	(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
		591	(__HANDLE__)->MspInitCallback = NULL; \
		592	(__HANDLE__)->MspDeInitCallback = NULL; \
		593	} while(0)
		594	#else
		595	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
		596	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
		597	#endif
		598
		599	/**
		600	* @}
		601	*/
		602
		603	/* Private macro ------------------------------------------------------------*/
		604
		605	/** @defgroup ADC_Private_Macros ADC Private Macros
		606	* @{
		607	*/
		608	/* Macro reserved for internal HAL driver usage, not intended to be used in */
		609	/* code of final user. */
		610
		611	/**
		612	* @brief Verification of ADC state: enabled or disabled
		613	* @param __HANDLE__: ADC handle
		614	* @retval SET (ADC enabled) or RESET (ADC disabled)
		615	*/
		616	#define ADC_IS_ENABLE(__HANDLE__) \
		617	((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
		618	) ? SET : RESET)
		619
		620	/**
		621	* @brief Test if conversion trigger of regular group is software start
		622	* or external trigger.
		623	* @param __HANDLE__: ADC handle
		624	* @retval SET (software start) or RESET (external trigger)
		625	*/
		626	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
		627	(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
		628
		629	/**
		630	* @brief Test if conversion trigger of injected group is software start
		631	* or external trigger.
		632	* @param __HANDLE__: ADC handle
		633	* @retval SET (software start) or RESET (external trigger)
		634	*/
		635	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
		636	(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
		637
		638	/**
		639	* @brief Simultaneously clears and sets specific bits of the handle State
		640	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
		641	* the first parameter is the ADC handle State, the second parameter is the
		642	* bit field to clear, the third and last parameter is the bit field to set.
		643	* @retval None
		644	*/
		645	#define ADC_STATE_CLR_SET MODIFY_REG
		646
		647	/**
		648	* @brief Clear ADC error code (set it to error code: "no error")
		649	* @param __HANDLE__: ADC handle
		650	* @retval None
		651	*/
		652	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
		653	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
		654
		655	/**
		656	* @brief Set ADC number of conversions into regular channel sequence length.
		657	* @param _NbrOfConversion_: Regular channel sequence length
		658	* @retval None
		659	*/
		660	#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
		661	(((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
		662
		663	/**
		664	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
		665	* @param _SAMPLETIME_: Sample time parameter.
		666	* @param _CHANNELNB_: Channel number.
		667	* @retval None
		668	*/
		669	#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
		670	((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
		671
		672	/**
		673	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
		674	* @param _SAMPLETIME_: Sample time parameter.
		675	* @param _CHANNELNB_: Channel number.
		676	* @retval None
		677	*/
		678	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
		679	((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
		680
		681	/**
		682	* @brief Set the selected regular channel rank for rank between 1 and 6.
		683	* @param _CHANNELNB_: Channel number.
		684	* @param _RANKNB_: Rank number.
		685	* @retval None
		686	*/
		687	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
		688	((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
		689
		690	/**
		691	* @brief Set the selected regular channel rank for rank between 7 and 12.
		692	* @param _CHANNELNB_: Channel number.
		693	* @param _RANKNB_: Rank number.
		694	* @retval None
		695	*/
		696	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
		697	((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
		698
		699	/**
		700	* @brief Set the selected regular channel rank for rank between 13 and 16.
		701	* @param _CHANNELNB_: Channel number.
		702	* @param _RANKNB_: Rank number.
		703	* @retval None
		704	*/
		705	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
		706	((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
		707
		708	/**
		709	* @brief Set the injected sequence length.
		710	* @param _JSQR_JL_: Sequence length.
		711	* @retval None
		712	*/
		713	#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
		714	(((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
		715
		716	/**
		717	* @brief Set the selected injected channel rank
		718	* Note: on STM32F1 devices, channel rank position in JSQR register
		719	* is depending on total number of ranks selected into
		720	* injected sequencer (ranks sequence starting from 4-JL)
		721	* @param _CHANNELNB_: Channel number.
		722	* @param _RANKNB_: Rank number.
		723	* @param _JSQR_JL_: Sequence length.
		724	* @retval None
		725	*/
		726	#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
		727	((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
		728
		729	/**
		730	* @brief Enable ADC continuous conversion mode.
		731	* @param _CONTINUOUS_MODE_: Continuous mode.
		732	* @retval None
		733	*/
		734	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
		735	((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
		736
		737	/**
		738	* @brief Configures the number of discontinuous conversions for the regular group channels.
		739	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
		740	* @retval None
		741	*/
		742	#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
		743	(((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
		744
		745	/**
		746	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
		747	* @param _SCAN_MODE_: Scan conversion mode.
		748	* @retval None
		749	*/
		750	/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
		751	/* is equivalent to ADC_SCAN_ENABLE. */
		752	#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
		753	(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) \|\| ((_SCAN_MODE_) == ENABLE) \
		754	)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
		755	)
		756
		757	/**
		758	* @brief Get the maximum ADC conversion cycles on all channels.
		759	* Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
		760	* Approximation of sampling time within 4 ranges, returns the highest value:
		761	* below 7.5 cycles {1.5 cycle; 7.5 cycles},
		762	* between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
		763	* between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
		764	* equal to 239.5 cycles
		765	* Unit: ADC clock cycles
		766	* @param __HANDLE__: ADC handle
		767	* @retval ADC conversion cycles on all channels
		768	*/
		769	#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
		770	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
		771	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
		772	\
		773	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
		774	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
		775	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
		776	: \
		777	((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
		778	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \|\| \
		779	((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
		780	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
		781	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
		782	)
		783
		784	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
		785	((ALIGN) == ADC_DATAALIGN_LEFT) )
		786
		787	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
		788	((SCAN_MODE) == ADC_SCAN_ENABLE) )
		789
		790	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
		791	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
		792
		793	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
		794	((CHANNEL) == ADC_CHANNEL_1) \|\| \
		795	((CHANNEL) == ADC_CHANNEL_2) \|\| \
		796	((CHANNEL) == ADC_CHANNEL_3) \|\| \
		797	((CHANNEL) == ADC_CHANNEL_4) \|\| \
		798	((CHANNEL) == ADC_CHANNEL_5) \|\| \
		799	((CHANNEL) == ADC_CHANNEL_6) \|\| \
		800	((CHANNEL) == ADC_CHANNEL_7) \|\| \
		801	((CHANNEL) == ADC_CHANNEL_8) \|\| \
		802	((CHANNEL) == ADC_CHANNEL_9) \|\| \
		803	((CHANNEL) == ADC_CHANNEL_10) \|\| \
		804	((CHANNEL) == ADC_CHANNEL_11) \|\| \
		805	((CHANNEL) == ADC_CHANNEL_12) \|\| \
		806	((CHANNEL) == ADC_CHANNEL_13) \|\| \
		807	((CHANNEL) == ADC_CHANNEL_14) \|\| \
		808	((CHANNEL) == ADC_CHANNEL_15) \|\| \
		809	((CHANNEL) == ADC_CHANNEL_16) \|\| \
		810	((CHANNEL) == ADC_CHANNEL_17) )
		811
		812	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) \|\| \
		813	((TIME) == ADC_SAMPLETIME_7CYCLES_5) \|\| \
		814	((TIME) == ADC_SAMPLETIME_13CYCLES_5) \|\| \
		815	((TIME) == ADC_SAMPLETIME_28CYCLES_5) \|\| \
		816	((TIME) == ADC_SAMPLETIME_41CYCLES_5) \|\| \
		817	((TIME) == ADC_SAMPLETIME_55CYCLES_5) \|\| \
		818	((TIME) == ADC_SAMPLETIME_71CYCLES_5) \|\| \
		819	((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
		820
		821	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
		822	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
		823	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
		824	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
		825	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
		826	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
		827	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
		828	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
		829	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
		830	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
		831	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
		832	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
		833	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
		834	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
		835	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
		836	((CHANNEL) == ADC_REGULAR_RANK_16) )
		837
		838	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
		839	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
		840	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
		841	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
		842	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
		843	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
		844	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
		845
		846	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) \|\| \
		847	((CONVERSION) == ADC_INJECTED_GROUP) \|\| \
		848	((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
		849
		850	#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
		851
		852
		853	/** @defgroup ADC_range_verification ADC range verification
		854	* For a unique ADC resolution: 12 bits
		855	* @{
		856	*/
		857	#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
		858	/**
		859	* @}
		860	*/
		861
		862	/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
		863	* @{
		864	*/
		865	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
		866	/**
		867	* @}
		868	*/
		869
		870	/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
		871	* @{
		872	*/
		873	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
		874	/**
		875	* @}
		876	*/
		877
		878	/**
		879	* @}
		880	*/
		881
		882	/* Include ADC HAL Extension module */
		883	#include "stm32f1xx_hal_adc_ex.h"
		884
		885	/* Exported functions --------------------------------------------------------*/
		886	/** @addtogroup ADC_Exported_Functions
		887	* @{
		888	*/
		889
		890	/** @addtogroup ADC_Exported_Functions_Group1
		891	* @{
		892	*/
		893
		894
		895	/* Initialization and de-initialization functions **********************************/
		896	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
		897	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
		898	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
		899	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
		900
		901	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		902	/* Callbacks Register/UnRegister functions ***********************************/
		903	HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
		904	HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
		905	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		906
		907	/**
		908	* @}
		909	*/
		910
		911	/* IO operation functions *****************************************************/
		912
		913	/** @addtogroup ADC_Exported_Functions_Group2
		914	* @{
		915	*/
		916
		917
		918	/* Blocking mode: Polling */
		919	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
		920	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
		921	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
		922	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
		923
		924	/* Non-blocking mode: Interruption */
		925	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
		926	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
		927
		928	/* Non-blocking mode: DMA */
		929	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
		930	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
		931
		932	/* ADC retrieve conversion value intended to be used with polling or interruption */
		933	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
		934
		935	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
		936	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
		937	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
		938	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
		939	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
		940	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
		941	/**
		942	* @}
		943	*/
		944
		945
		946	/* Peripheral Control functions ***********************************************/
		947	/** @addtogroup ADC_Exported_Functions_Group3
		948	* @{
		949	*/
		950	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
		951	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
		952	/**
		953	* @}
		954	*/
		955
		956
		957	/* Peripheral State functions *************************************************/
		958	/** @addtogroup ADC_Exported_Functions_Group4
		959	* @{
		960	*/
		961	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
		962	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
		963	/**
		964	* @}
		965	*/
		966
		967
		968	/**
		969	* @}
		970	*/
		971
		972
		973	/* Internal HAL driver functions **********************************************/
		974	/** @addtogroup ADC_Private_Functions
		975	* @{
		976	*/
		977	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
		978	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
		979	void ADC_StabilizationTime(uint32_t DelayUs);
		980	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
		981	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
		982	void ADC_DMAError(DMA_HandleTypeDef *hdma);
		983	/**
		984	* @}
		985	*/
		986
		987
		988	/**
		989	* @}
		990	*/
		991
		992	/**
		993	* @}
		994	*/
		995
		996	#ifdef __cplusplus
		997	}
		998	#endif
		999
		1000
		1001	#endif /* __STM32F1xx_HAL_ADC_H */
		1002
		1003	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories dashGPS

(root)/branches/dashGPS-bmp/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h – Rev 18