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| 2 | mjames | 1 | /**************************************************************************//** |
| 2 | * @file os_tick_gtim.c |
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| 3 | * @brief CMSIS OS Tick implementation for Generic Timer |
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| 4 | * @version V1.0.1 |
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| 5 | * @date 24. November 2017 |
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| 6 | ******************************************************************************/ |
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| 7 | /* |
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| 8 | * Copyright (c) 2017 ARM Limited. All rights reserved. |
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| 9 | * |
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| 10 | * SPDX-License-Identifier: Apache-2.0 |
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| 11 | * |
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| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
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| 13 | * not use this file except in compliance with the License. |
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| 14 | * You may obtain a copy of the License at |
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| 15 | * |
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| 16 | * www.apache.org/licenses/LICENSE-2.0 |
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| 17 | * |
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| 18 | * Unless required by applicable law or agreed to in writing, software |
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| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
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| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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| 21 | * See the License for the specific language governing permissions and |
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| 22 | * limitations under the License. |
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| 23 | */ |
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| 24 | |||
| 25 | #include "os_tick.h" |
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| 26 | #include "irq_ctrl.h" |
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| 27 | |||
| 28 | #include "RTE_Components.h" |
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| 29 | #include CMSIS_device_header |
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| 30 | |||
| 31 | #ifndef GTIM_IRQ_PRIORITY |
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| 32 | #define GTIM_IRQ_PRIORITY 0xFFU |
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| 33 | #endif |
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| 34 | |||
| 35 | #ifndef GTIM_IRQ_NUM |
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| 36 | #define GTIM_IRQ_NUM SecurePhyTimer_IRQn |
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| 37 | #endif |
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| 38 | |||
| 39 | // Timer interrupt pending flag |
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| 40 | static uint8_t GTIM_PendIRQ; |
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| 41 | |||
| 42 | // Timer tick frequency |
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| 43 | static uint32_t GTIM_Clock; |
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| 44 | |||
| 45 | // Timer load value |
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| 46 | static uint32_t GTIM_Load; |
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| 47 | |||
| 48 | // Setup OS Tick. |
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| 49 | int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { |
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| 50 | uint32_t prio, bits; |
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| 51 | |||
| 52 | if (freq == 0U) { |
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| 53 | return (-1); |
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| 54 | } |
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| 55 | |||
| 56 | GTIM_PendIRQ = 0U; |
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| 57 | |||
| 58 | // Get timer clock |
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| 59 | #ifdef SCTR_BASE |
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| 60 | GTIM_Clock = *(uint32_t*)(SCTR_BASE+0x20); |
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| 61 | #else |
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| 62 | // FVP REFCLK CNTControl 100MHz |
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| 63 | GTIM_Clock = 100000000UL; |
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| 64 | #endif |
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| 65 | |||
| 66 | PL1_SetCounterFrequency(GTIM_Clock); |
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| 67 | |||
| 68 | // Calculate load value |
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| 69 | GTIM_Load = (GTIM_Clock / freq) - 1U; |
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| 70 | |||
| 71 | // Disable Generic Timer and set load value |
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| 72 | PL1_SetControl(0U); |
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| 73 | PL1_SetLoadValue(GTIM_Load); |
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| 74 | |||
| 75 | // Disable corresponding IRQ |
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| 76 | IRQ_Disable(GTIM_IRQ_NUM); |
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| 77 | IRQ_ClearPending(GTIM_IRQ_NUM); |
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| 78 | |||
| 79 | // Determine number of implemented priority bits |
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| 80 | IRQ_SetPriority(GTIM_IRQ_NUM, 0xFFU); |
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| 81 | |||
| 82 | prio = IRQ_GetPriority(GTIM_IRQ_NUM); |
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| 83 | |||
| 84 | // At least bits [7:4] must be implemented |
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| 85 | if ((prio & 0xF0U) == 0U) { |
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| 86 | return (-1); |
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| 87 | } |
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| 88 | |||
| 89 | for (bits = 0; bits < 4; bits++) { |
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| 90 | if ((prio & 0x01) != 0) { |
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| 91 | break; |
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| 92 | } |
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| 93 | prio >>= 1; |
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| 94 | } |
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| 95 | |||
| 96 | // Adjust configured priority to the number of implemented priority bits |
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| 97 | prio = (GTIM_IRQ_PRIORITY << bits) & 0xFFUL; |
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| 98 | |||
| 99 | // Set Private Timer interrupt priority |
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| 100 | IRQ_SetPriority(GTIM_IRQ_NUM, prio-1U); |
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| 101 | |||
| 102 | // Set edge-triggered IRQ |
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| 103 | IRQ_SetMode(GTIM_IRQ_NUM, IRQ_MODE_TRIG_EDGE); |
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| 104 | |||
| 105 | // Register tick interrupt handler function |
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| 106 | IRQ_SetHandler(GTIM_IRQ_NUM, handler); |
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| 107 | |||
| 108 | // Enable corresponding interrupt |
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| 109 | IRQ_Enable(GTIM_IRQ_NUM); |
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| 110 | |||
| 111 | // Enable system counter and timer control |
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| 112 | #ifdef SCTR_BASE |
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| 113 | *(uint32_t*)SCTR_BASE |= 3U; |
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| 114 | #endif |
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| 115 | |||
| 116 | // Enable timer control |
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| 117 | PL1_SetControl(1U); |
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| 118 | |||
| 119 | return (0); |
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| 120 | } |
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| 121 | |||
| 122 | /// Enable OS Tick. |
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| 123 | void OS_Tick_Enable (void) { |
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| 124 | uint32_t ctrl; |
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| 125 | |||
| 126 | // Set pending interrupt if flag set |
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| 127 | if (GTIM_PendIRQ != 0U) { |
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| 128 | GTIM_PendIRQ = 0U; |
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| 129 | IRQ_SetPending (GTIM_IRQ_NUM); |
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| 130 | } |
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| 131 | |||
| 132 | // Start the Private Timer |
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| 133 | ctrl = PL1_GetControl(); |
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| 134 | // Set bit: Timer enable |
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| 135 | ctrl |= 1U; |
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| 136 | PL1_SetControl(ctrl); |
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| 137 | } |
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| 138 | |||
| 139 | /// Disable OS Tick. |
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| 140 | void OS_Tick_Disable (void) { |
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| 141 | uint32_t ctrl; |
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| 142 | |||
| 143 | // Stop the Private Timer |
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| 144 | ctrl = PL1_GetControl(); |
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| 145 | // Clear bit: Timer enable |
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| 146 | ctrl &= ~1U; |
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| 147 | PL1_SetControl(ctrl); |
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| 148 | |||
| 149 | // Remember pending interrupt flag |
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| 150 | if (IRQ_GetPending(GTIM_IRQ_NUM) != 0) { |
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| 151 | IRQ_ClearPending(GTIM_IRQ_NUM); |
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| 152 | GTIM_PendIRQ = 1U; |
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| 153 | } |
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| 154 | } |
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| 155 | |||
| 156 | // Acknowledge OS Tick IRQ. |
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| 157 | void OS_Tick_AcknowledgeIRQ (void) { |
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| 158 | IRQ_ClearPending (GTIM_IRQ_NUM); |
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| 159 | PL1_SetLoadValue(GTIM_Load); |
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| 160 | } |
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| 161 | |||
| 162 | // Get OS Tick IRQ number. |
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| 163 | int32_t OS_Tick_GetIRQn (void) { |
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| 164 | return (GTIM_IRQ_NUM); |
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| 165 | } |
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| 166 | |||
| 167 | // Get OS Tick clock. |
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| 168 | uint32_t OS_Tick_GetClock (void) { |
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| 169 | return (GTIM_Clock); |
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| 170 | } |
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| 171 | |||
| 172 | // Get OS Tick interval. |
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| 173 | uint32_t OS_Tick_GetInterval (void) { |
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| 174 | return (GTIM_Load + 1U); |
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| 175 | } |
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| 176 | |||
| 177 | // Get OS Tick count value. |
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| 178 | uint32_t OS_Tick_GetCount (void) { |
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| 179 | return (GTIM_Load - PL1_GetCurrentValue()); |
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| 180 | } |
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| 181 | |||
| 182 | // Get OS Tick overflow status. |
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| 183 | uint32_t OS_Tick_GetOverflow (void) { |
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| 184 | CNTP_CTL_Type cntp_ctl; |
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| 185 | cntp_ctl.w = PL1_GetControl(); |
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| 186 | return (cntp_ctl.b.ISTATUS); |
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| 187 | } |