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| 2 | mjames | 1 | /** |
| 2 | *************** (C) COPYRIGHT 2017 STMicroelectronics ************************ |
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| 3 | * @file startup_stm32f101xe.s |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief STM32F101xE Value Line Devices vector table for Atollic toolchain. |
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| 6 | * This module performs: |
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| 7 | * - Set the initial SP |
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| 8 | * - Set the initial PC == Reset_Handler, |
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| 9 | * - Set the vector table entries with the exceptions ISR address |
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| 10 | * - Configure the clock system |
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| 11 | * - Branches to main in the C library (which eventually |
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| 12 | * calls main()). |
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| 13 | * After Reset the Cortex-M3 processor is in Thread mode, |
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| 14 | * priority is Privileged, and the Stack is set to Main. |
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| 15 | ****************************************************************************** |
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| 16 | * @attention |
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| 17 | * |
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| 18 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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| 19 | * All rights reserved.</center></h2> |
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| 20 | * |
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| 21 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 22 | * the "License"; You may not use this file except in compliance with the |
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| 23 | * License. You may obtain a copy of the License at: |
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| 24 | * opensource.org/licenses/BSD-3-Clause |
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| 25 | * |
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| 26 | ****************************************************************************** |
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| 27 | */ |
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| 28 | |||
| 29 | .syntax unified |
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| 30 | .cpu cortex-m3 |
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| 31 | .fpu softvfp |
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| 32 | .thumb |
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| 33 | |||
| 34 | .global g_pfnVectors |
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| 35 | .global Default_Handler |
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| 36 | |||
| 37 | /* start address for the initialization values of the .data section. |
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| 38 | defined in linker script */ |
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| 39 | .word _sidata |
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| 40 | /* start address for the .data section. defined in linker script */ |
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| 41 | .word _sdata |
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| 42 | /* end address for the .data section. defined in linker script */ |
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| 43 | .word _edata |
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| 44 | /* start address for the .bss section. defined in linker script */ |
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| 45 | .word _sbss |
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| 46 | /* end address for the .bss section. defined in linker script */ |
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| 47 | .word _ebss |
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| 48 | |||
| 49 | .equ BootRAM, 0xF1E0F85F |
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| 50 | /** |
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| 51 | * @brief This is the code that gets called when the processor first |
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| 52 | * starts execution following a reset event. Only the absolutely |
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| 53 | * necessary set is performed, after which the application |
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| 54 | * supplied main() routine is called. |
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| 55 | * @param None |
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| 56 | * @retval : None |
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| 57 | */ |
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| 58 | |||
| 59 | .section .text.Reset_Handler |
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| 60 | .weak Reset_Handler |
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| 61 | .type Reset_Handler, %function |
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| 62 | Reset_Handler: |
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| 63 | |||
| 64 | /* Copy the data segment initializers from flash to SRAM */ |
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| 65 | movs r1, #0 |
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| 66 | b LoopCopyDataInit |
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| 67 | |||
| 68 | CopyDataInit: |
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| 69 | ldr r3, =_sidata |
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| 70 | ldr r3, [r3, r1] |
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| 71 | str r3, [r0, r1] |
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| 72 | adds r1, r1, #4 |
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| 73 | |||
| 74 | LoopCopyDataInit: |
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| 75 | ldr r0, =_sdata |
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| 76 | ldr r3, =_edata |
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| 77 | adds r2, r0, r1 |
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| 78 | cmp r2, r3 |
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| 79 | bcc CopyDataInit |
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| 80 | ldr r2, =_sbss |
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| 81 | b LoopFillZerobss |
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| 82 | /* Zero fill the bss segment. */ |
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| 83 | FillZerobss: |
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| 84 | movs r3, #0 |
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| 85 | str r3, [r2], #4 |
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| 86 | |||
| 87 | LoopFillZerobss: |
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| 88 | ldr r3, = _ebss |
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| 89 | cmp r2, r3 |
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| 90 | bcc FillZerobss |
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| 91 | |||
| 92 | /* Call the clock system intitialization function.*/ |
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| 93 | bl SystemInit |
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| 94 | /* Call static constructors */ |
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| 95 | bl __libc_init_array |
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| 96 | /* Call the application's entry point.*/ |
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| 97 | bl main |
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| 98 | bx lr |
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| 99 | .size Reset_Handler, .-Reset_Handler |
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| 100 | |||
| 101 | /** |
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| 102 | * @brief This is the code that gets called when the processor receives an |
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| 103 | * unexpected interrupt. This simply enters an infinite loop, preserving |
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| 104 | * the system state for examination by a debugger. |
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| 105 | * |
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| 106 | * @param None |
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| 107 | * @retval : None |
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| 108 | */ |
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| 109 | .section .text.Default_Handler,"ax",%progbits |
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| 110 | Default_Handler: |
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| 111 | Infinite_Loop: |
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| 112 | b Infinite_Loop |
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| 113 | .size Default_Handler, .-Default_Handler |
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| 114 | /****************************************************************************** |
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| 115 | * |
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| 116 | * The minimal vector table for a Cortex M3. Note that the proper constructs |
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| 117 | * must be placed on this to ensure that it ends up at physical address |
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| 118 | * 0x0000.0000. |
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| 119 | * |
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| 120 | ******************************************************************************/ |
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| 121 | .section .isr_vector,"a",%progbits |
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| 122 | .type g_pfnVectors, %object |
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| 123 | .size g_pfnVectors, .-g_pfnVectors |
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| 124 | |||
| 125 | |||
| 126 | g_pfnVectors: |
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| 127 | |||
| 128 | .word _estack |
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| 129 | .word Reset_Handler |
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| 130 | .word NMI_Handler |
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| 131 | .word HardFault_Handler |
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| 132 | .word MemManage_Handler |
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| 133 | .word BusFault_Handler |
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| 134 | .word UsageFault_Handler |
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| 135 | .word 0 |
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| 136 | .word 0 |
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| 137 | .word 0 |
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| 138 | .word 0 |
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| 139 | .word SVC_Handler |
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| 140 | .word DebugMon_Handler |
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| 141 | .word 0 |
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| 142 | .word PendSV_Handler |
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| 143 | .word SysTick_Handler |
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| 144 | .word WWDG_IRQHandler |
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| 145 | .word PVD_IRQHandler |
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| 146 | .word TAMPER_IRQHandler |
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| 147 | .word RTC_IRQHandler |
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| 148 | .word FLASH_IRQHandler |
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| 149 | .word RCC_IRQHandler |
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| 150 | .word EXTI0_IRQHandler |
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| 151 | .word EXTI1_IRQHandler |
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| 152 | .word EXTI2_IRQHandler |
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| 153 | .word EXTI3_IRQHandler |
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| 154 | .word EXTI4_IRQHandler |
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| 155 | .word DMA1_Channel1_IRQHandler |
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| 156 | .word DMA1_Channel2_IRQHandler |
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| 157 | .word DMA1_Channel3_IRQHandler |
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| 158 | .word DMA1_Channel4_IRQHandler |
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| 159 | .word DMA1_Channel5_IRQHandler |
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| 160 | .word DMA1_Channel6_IRQHandler |
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| 161 | .word DMA1_Channel7_IRQHandler |
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| 162 | .word ADC1_IRQHandler |
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| 163 | .word 0 |
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| 164 | .word 0 |
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| 165 | .word 0 |
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| 166 | .word 0 |
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| 167 | .word EXTI9_5_IRQHandler |
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| 168 | .word 0 |
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| 169 | .word 0 |
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| 170 | .word 0 |
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| 171 | .word 0 |
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| 172 | .word TIM2_IRQHandler |
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| 173 | .word TIM3_IRQHandler |
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| 174 | .word TIM4_IRQHandler |
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| 175 | .word I2C1_EV_IRQHandler |
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| 176 | .word I2C1_ER_IRQHandler |
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| 177 | .word I2C2_EV_IRQHandler |
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| 178 | .word I2C2_ER_IRQHandler |
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| 179 | .word SPI1_IRQHandler |
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| 180 | .word SPI2_IRQHandler |
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| 181 | .word USART1_IRQHandler |
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| 182 | .word USART2_IRQHandler |
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| 183 | .word USART3_IRQHandler |
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| 184 | .word EXTI15_10_IRQHandler |
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| 185 | .word RTC_Alarm_IRQHandler |
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| 186 | .word 0 |
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| 187 | .word 0 |
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| 188 | .word 0 |
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| 189 | .word 0 |
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| 190 | .word 0 |
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| 191 | .word 0 |
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| 192 | .word FSMC_IRQHandler |
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| 193 | .word 0 |
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| 194 | .word TIM5_IRQHandler |
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| 195 | .word SPI3_IRQHandler |
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| 196 | .word UART4_IRQHandler |
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| 197 | .word UART5_IRQHandler |
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| 198 | .word TIM6_IRQHandler |
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| 199 | .word TIM7_IRQHandler |
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| 200 | .word DMA2_Channel1_IRQHandler |
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| 201 | .word DMA2_Channel2_IRQHandler |
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| 202 | .word DMA2_Channel3_IRQHandler |
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| 203 | .word DMA2_Channel4_5_IRQHandler |
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| 204 | .word 0 |
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| 205 | .word 0 |
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| 206 | .word 0 |
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| 207 | .word 0 |
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| 208 | .word 0 |
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| 209 | .word 0 |
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| 210 | .word 0 |
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| 211 | .word 0 |
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| 212 | .word 0 |
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| 213 | .word 0 |
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| 214 | .word 0 |
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| 215 | .word 0 |
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| 216 | .word 0 |
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| 217 | .word 0 |
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| 218 | .word 0 |
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| 219 | .word 0 |
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| 220 | .word 0 |
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| 221 | .word 0 |
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| 222 | .word 0 |
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| 223 | .word 0 |
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| 224 | .word 0 |
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| 225 | .word 0 |
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| 226 | .word 0 |
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| 227 | .word 0 |
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| 228 | .word 0 |
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| 229 | .word 0 |
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| 230 | .word 0 |
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| 231 | .word 0 |
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| 232 | .word 0 |
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| 233 | .word 0 |
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| 234 | .word 0 |
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| 235 | .word 0 |
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| 236 | .word 0 |
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| 237 | .word 0 |
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| 238 | .word 0 |
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| 239 | .word 0 |
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| 240 | .word 0 |
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| 241 | .word 0 |
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| 242 | .word 0 |
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| 243 | .word 0 |
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| 244 | .word 0 |
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| 245 | .word 0 |
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| 246 | .word 0 |
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| 247 | .word 0 |
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| 248 | .word BootRAM /* @0x1E0. This is for boot in RAM mode for |
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| 249 | STM32F10x High Density devices. */ |
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| 250 | |||
| 251 | /******************************************************************************* |
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| 252 | * |
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| 253 | * Provide weak aliases for each Exception handler to the Default_Handler. |
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| 254 | * As they are weak aliases, any function with the same name will override |
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| 255 | * this definition. |
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| 256 | * |
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| 257 | *******************************************************************************/ |
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| 258 | |||
| 259 | .weak NMI_Handler |
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| 260 | .thumb_set NMI_Handler,Default_Handler |
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| 261 | |||
| 262 | .weak HardFault_Handler |
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| 263 | .thumb_set HardFault_Handler,Default_Handler |
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| 264 | |||
| 265 | .weak MemManage_Handler |
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| 266 | .thumb_set MemManage_Handler,Default_Handler |
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| 267 | |||
| 268 | .weak BusFault_Handler |
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| 269 | .thumb_set BusFault_Handler,Default_Handler |
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| 270 | |||
| 271 | .weak UsageFault_Handler |
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| 272 | .thumb_set UsageFault_Handler,Default_Handler |
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| 273 | |||
| 274 | .weak SVC_Handler |
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| 275 | .thumb_set SVC_Handler,Default_Handler |
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| 276 | |||
| 277 | .weak DebugMon_Handler |
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| 278 | .thumb_set DebugMon_Handler,Default_Handler |
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| 279 | |||
| 280 | .weak PendSV_Handler |
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| 281 | .thumb_set PendSV_Handler,Default_Handler |
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| 282 | |||
| 283 | .weak SysTick_Handler |
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| 284 | .thumb_set SysTick_Handler,Default_Handler |
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| 285 | |||
| 286 | .weak WWDG_IRQHandler |
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| 287 | .thumb_set WWDG_IRQHandler,Default_Handler |
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| 288 | |||
| 289 | .weak PVD_IRQHandler |
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| 290 | .thumb_set PVD_IRQHandler,Default_Handler |
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| 291 | |||
| 292 | .weak TAMPER_IRQHandler |
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| 293 | .thumb_set TAMPER_IRQHandler,Default_Handler |
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| 294 | |||
| 295 | .weak RTC_IRQHandler |
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| 296 | .thumb_set RTC_IRQHandler,Default_Handler |
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| 297 | |||
| 298 | .weak FLASH_IRQHandler |
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| 299 | .thumb_set FLASH_IRQHandler,Default_Handler |
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| 300 | |||
| 301 | .weak RCC_IRQHandler |
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| 302 | .thumb_set RCC_IRQHandler,Default_Handler |
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| 303 | |||
| 304 | .weak EXTI0_IRQHandler |
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| 305 | .thumb_set EXTI0_IRQHandler,Default_Handler |
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| 306 | |||
| 307 | .weak EXTI1_IRQHandler |
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| 308 | .thumb_set EXTI1_IRQHandler,Default_Handler |
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| 309 | |||
| 310 | .weak EXTI2_IRQHandler |
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| 311 | .thumb_set EXTI2_IRQHandler,Default_Handler |
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| 312 | |||
| 313 | .weak EXTI3_IRQHandler |
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| 314 | .thumb_set EXTI3_IRQHandler,Default_Handler |
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| 315 | |||
| 316 | .weak EXTI4_IRQHandler |
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| 317 | .thumb_set EXTI4_IRQHandler,Default_Handler |
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| 318 | |||
| 319 | .weak DMA1_Channel1_IRQHandler |
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| 320 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler |
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| 321 | |||
| 322 | .weak DMA1_Channel2_IRQHandler |
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| 323 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler |
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| 324 | |||
| 325 | .weak DMA1_Channel3_IRQHandler |
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| 326 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler |
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| 327 | |||
| 328 | .weak DMA1_Channel4_IRQHandler |
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| 329 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler |
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| 330 | |||
| 331 | .weak DMA1_Channel5_IRQHandler |
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| 332 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler |
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| 333 | |||
| 334 | .weak DMA1_Channel6_IRQHandler |
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| 335 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler |
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| 336 | |||
| 337 | .weak DMA1_Channel7_IRQHandler |
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| 338 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler |
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| 339 | |||
| 340 | .weak ADC1_IRQHandler |
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| 341 | .thumb_set ADC1_IRQHandler,Default_Handler |
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| 342 | |||
| 343 | .weak EXTI9_5_IRQHandler |
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| 344 | .thumb_set EXTI9_5_IRQHandler,Default_Handler |
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| 345 | |||
| 346 | .weak TIM2_IRQHandler |
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| 347 | .thumb_set TIM2_IRQHandler,Default_Handler |
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| 348 | |||
| 349 | .weak TIM3_IRQHandler |
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| 350 | .thumb_set TIM3_IRQHandler,Default_Handler |
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| 351 | |||
| 352 | .weak TIM4_IRQHandler |
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| 353 | .thumb_set TIM4_IRQHandler,Default_Handler |
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| 354 | |||
| 355 | .weak I2C1_EV_IRQHandler |
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| 356 | .thumb_set I2C1_EV_IRQHandler,Default_Handler |
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| 357 | |||
| 358 | .weak I2C1_ER_IRQHandler |
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| 359 | .thumb_set I2C1_ER_IRQHandler,Default_Handler |
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| 360 | |||
| 361 | .weak I2C2_EV_IRQHandler |
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| 362 | .thumb_set I2C2_EV_IRQHandler,Default_Handler |
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| 363 | |||
| 364 | .weak I2C2_ER_IRQHandler |
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| 365 | .thumb_set I2C2_ER_IRQHandler,Default_Handler |
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| 366 | |||
| 367 | .weak SPI1_IRQHandler |
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| 368 | .thumb_set SPI1_IRQHandler,Default_Handler |
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| 369 | |||
| 370 | .weak SPI2_IRQHandler |
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| 371 | .thumb_set SPI2_IRQHandler,Default_Handler |
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| 372 | |||
| 373 | .weak USART1_IRQHandler |
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| 374 | .thumb_set USART1_IRQHandler,Default_Handler |
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| 375 | |||
| 376 | .weak USART2_IRQHandler |
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| 377 | .thumb_set USART2_IRQHandler,Default_Handler |
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| 378 | |||
| 379 | .weak USART3_IRQHandler |
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| 380 | .thumb_set USART3_IRQHandler,Default_Handler |
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| 381 | |||
| 382 | .weak EXTI15_10_IRQHandler |
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| 383 | .thumb_set EXTI15_10_IRQHandler,Default_Handler |
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| 384 | |||
| 385 | .weak RTC_Alarm_IRQHandler |
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| 386 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler |
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| 387 | |||
| 388 | .weak FSMC_IRQHandler |
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| 389 | .thumb_set FSMC_IRQHandler,Default_Handler |
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| 390 | |||
| 391 | .weak TIM5_IRQHandler |
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| 392 | .thumb_set TIM5_IRQHandler,Default_Handler |
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| 393 | |||
| 394 | .weak SPI3_IRQHandler |
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| 395 | .thumb_set SPI3_IRQHandler,Default_Handler |
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| 396 | |||
| 397 | .weak UART4_IRQHandler |
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| 398 | .thumb_set UART4_IRQHandler,Default_Handler |
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| 399 | |||
| 400 | .weak UART5_IRQHandler |
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| 401 | .thumb_set UART5_IRQHandler,Default_Handler |
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| 402 | |||
| 403 | .weak TIM6_IRQHandler |
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| 404 | .thumb_set TIM6_IRQHandler,Default_Handler |
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| 405 | |||
| 406 | .weak TIM7_IRQHandler |
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| 407 | .thumb_set TIM7_IRQHandler,Default_Handler |
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| 408 | |||
| 409 | .weak DMA2_Channel1_IRQHandler |
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| 410 | .thumb_set DMA2_Channel1_IRQHandler,Default_Handler |
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| 411 | |||
| 412 | .weak DMA2_Channel2_IRQHandler |
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| 413 | .thumb_set DMA2_Channel2_IRQHandler,Default_Handler |
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| 414 | |||
| 415 | .weak DMA2_Channel3_IRQHandler |
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| 416 | .thumb_set DMA2_Channel3_IRQHandler,Default_Handler |
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| 417 | |||
| 418 | .weak DMA2_Channel4_5_IRQHandler |
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| 419 | .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler |
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| 420 | |||
| 421 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |