WebSVN – dashGPS – Blame – /branches/dashGPS-bmp/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f100xe.h
		4	* @author MCD Application Team
		5	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		6	* This file contains all the peripheral register's definitions, bits
		7	* definitions and memory mapping for STM32F1xx devices.
		8	*
		9	* This file contains:
		10	* - Data structures and the address mapping for all peripherals
		11	* - Peripheral's registers declarations and bits definition
		12	* - Macros to access peripheral�s registers hardware
		13	*
		14	******************************************************************************
		15	* @attention
		16	*
		17	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
		18	* All rights reserved.</center></h2>
		19	*
		20	* This software component is licensed by ST under BSD 3-Clause license,
		21	* the "License"; You may not use this file except in compliance with the
		22	* License. You may obtain a copy of the License at:
		23	* opensource.org/licenses/BSD-3-Clause
		24	*
		25	******************************************************************************
		26	*/
		27
		28
		29	/** @addtogroup CMSIS
		30	* @{
		31	*/
		32
		33	/** @addtogroup stm32f100xe
		34	* @{
		35	*/
		36
		37	#ifndef __STM32F100xE_H
		38	#define __STM32F100xE_H
		39
		40	#ifdef __cplusplus
		41	extern "C" {
		42	#endif
		43
		44	/** @addtogroup Configuration_section_for_CMSIS
		45	* @{
		46	*/
		47	/**
		48	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		49	*/
		50	#define __CM3_REV 0x0200U /!< Core Revision r2p0 /
		51	#define __MPU_PRESENT 0U /!< Other STM32 devices does not provide an MPU /
		52	#define __NVIC_PRIO_BITS 4U /!< STM32 uses 4 Bits for the Priority Levels /
		53	#define __Vendor_SysTickConfig 0U /!< Set to 1 if different SysTick Config is used /
		54
		55	/**
		56	* @}
		57	*/
		58
		59	/** @addtogroup Peripheral_interrupt_number_definition
		60	* @{
		61	*/
		62
		63	/**
		64	* @brief STM32F10x Interrupt Number Definition, according to the selected device
		65	* in @ref Library_configuration_section
		66	*/
		67
		68	/!< Interrupt Number Definition /
		69	typedef enum
		70	{
		71	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
		72	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
		73	HardFault_IRQn = -13, /!< 3 Cortex-M3 Hard Fault Interrupt /
		74	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		75	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		76	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		77	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		78	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		79	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		80	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		81
		82	/**** STM32 specific Interrupt Numbers *******************************************************/
		83	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		84	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		85	TAMPER_IRQn = 2, /!< Tamper Interrupt /
		86	RTC_IRQn = 3, /!< RTC global Interrupt /
		87	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		88	RCC_IRQn = 5, /!< RCC global Interrupt /
		89	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		90	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		91	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		92	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		93	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		94	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		95	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		96	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		97	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		98	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		99	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		100	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		101	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
		102	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		103	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
		104	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
		105	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
		106	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
		107	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		108	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		109	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		110	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		111	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		112	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		113	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		114	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		115	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		116	USART1_IRQn = 37, /!< USART1 global Interrupt /
		117	USART2_IRQn = 38, /!< USART2 global Interrupt /
		118	USART3_IRQn = 39, /!< USART3 global Interrupt /
		119	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		120	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		121	CEC_IRQn = 42, /!< HDMI-CEC Interrupt /
		122	TIM12_IRQn = 43, /!< TIM12 global Interrupt /
		123	TIM13_IRQn = 44, /!< TIM13 global Interrupt /
		124	TIM14_IRQn = 45, /!< TIM14 global Interrupt /
		125	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
		126	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
		127	UART4_IRQn = 52, /!< UART4 global Interrupt /
		128	UART5_IRQn = 53, /!< UART5 global Interrupt /
		129	TIM6_DAC_IRQn = 54, /!< TIM6 and DAC underrun Interrupt /
		130	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
		131	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
		132	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
		133	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
		134	DMA2_Channel4_5_IRQn = 59, /!< DMA2 Channel 4 and Channel 5 global Interrupt /
		135	DMA2_Channel4_IRQn = 59, /!< DMA2 Channel 4 global Interrupt /
		136	DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
		137	mapped at position 60 only if the MISC_REMAP bit in
		138	the AFIO_MAPR2 register is set) */
		139	} IRQn_Type;
		140
		141	/**
		142	* @}
		143	*/
		144
		145	#include "core_cm3.h"
		146	#include "system_stm32f1xx.h"
		147	#include <stdint.h>
		148
		149	/** @addtogroup Peripheral_registers_structures
		150	* @{
		151	*/
		152
		153	/**
		154	* @brief Analog to Digital Converter
		155	*/
		156
		157	typedef struct
		158	{
		159	__IO uint32_t SR;
		160	__IO uint32_t CR1;
		161	__IO uint32_t CR2;
		162	__IO uint32_t SMPR1;
		163	__IO uint32_t SMPR2;
		164	__IO uint32_t JOFR1;
		165	__IO uint32_t JOFR2;
		166	__IO uint32_t JOFR3;
		167	__IO uint32_t JOFR4;
		168	__IO uint32_t HTR;
		169	__IO uint32_t LTR;
		170	__IO uint32_t SQR1;
		171	__IO uint32_t SQR2;
		172	__IO uint32_t SQR3;
		173	__IO uint32_t JSQR;
		174	__IO uint32_t JDR1;
		175	__IO uint32_t JDR2;
		176	__IO uint32_t JDR3;
		177	__IO uint32_t JDR4;
		178	__IO uint32_t DR;
		179	} ADC_TypeDef;
		180
		181	typedef struct
		182	{
		183	__IO uint32_t SR; /!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address /
		184	__IO uint32_t CR1; /!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 /
		185	__IO uint32_t CR2; /!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 /
		186	uint32_t RESERVED[16];
		187	__IO uint32_t DR; /!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C /
		188	} ADC_Common_TypeDef;
		189
		190	/**
		191	* @brief Backup Registers
		192	*/
		193
		194	typedef struct
		195	{
		196	uint32_t RESERVED0;
		197	__IO uint32_t DR1;
		198	__IO uint32_t DR2;
		199	__IO uint32_t DR3;
		200	__IO uint32_t DR4;
		201	__IO uint32_t DR5;
		202	__IO uint32_t DR6;
		203	__IO uint32_t DR7;
		204	__IO uint32_t DR8;
		205	__IO uint32_t DR9;
		206	__IO uint32_t DR10;
		207	__IO uint32_t RTCCR;
		208	__IO uint32_t CR;
		209	__IO uint32_t CSR;
		210	uint32_t RESERVED13[2];
		211	__IO uint32_t DR11;
		212	__IO uint32_t DR12;
		213	__IO uint32_t DR13;
		214	__IO uint32_t DR14;
		215	__IO uint32_t DR15;
		216	__IO uint32_t DR16;
		217	__IO uint32_t DR17;
		218	__IO uint32_t DR18;
		219	__IO uint32_t DR19;
		220	__IO uint32_t DR20;
		221	__IO uint32_t DR21;
		222	__IO uint32_t DR22;
		223	__IO uint32_t DR23;
		224	__IO uint32_t DR24;
		225	__IO uint32_t DR25;
		226	__IO uint32_t DR26;
		227	__IO uint32_t DR27;
		228	__IO uint32_t DR28;
		229	__IO uint32_t DR29;
		230	__IO uint32_t DR30;
		231	__IO uint32_t DR31;
		232	__IO uint32_t DR32;
		233	__IO uint32_t DR33;
		234	__IO uint32_t DR34;
		235	__IO uint32_t DR35;
		236	__IO uint32_t DR36;
		237	__IO uint32_t DR37;
		238	__IO uint32_t DR38;
		239	__IO uint32_t DR39;
		240	__IO uint32_t DR40;
		241	__IO uint32_t DR41;
		242	__IO uint32_t DR42;
		243	} BKP_TypeDef;
		244
		245
		246	/**
		247	* @brief Consumer Electronics Control (CEC)
		248	*/
		249	typedef struct
		250	{
		251	__IO uint32_t CFGR;
		252	__IO uint32_t OAR;
		253	__IO uint32_t PRES;
		254	__IO uint32_t ESR;
		255	__IO uint32_t CSR;
		256	__IO uint32_t TXD;
		257	__IO uint32_t RXD;
		258	} CEC_TypeDef;
		259
		260	/**
		261	* @brief CRC calculation unit
		262	*/
		263
		264	typedef struct
		265	{
		266	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		267	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		268	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		269	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		270	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		271	} CRC_TypeDef;
		272
		273	/**
		274	* @brief Digital to Analog Converter
		275	*/
		276
		277	typedef struct
		278	{
		279	__IO uint32_t CR;
		280	__IO uint32_t SWTRIGR;
		281	__IO uint32_t DHR12R1;
		282	__IO uint32_t DHR12L1;
		283	__IO uint32_t DHR8R1;
		284	__IO uint32_t DHR12R2;
		285	__IO uint32_t DHR12L2;
		286	__IO uint32_t DHR8R2;
		287	__IO uint32_t DHR12RD;
		288	__IO uint32_t DHR12LD;
		289	__IO uint32_t DHR8RD;
		290	__IO uint32_t DOR1;
		291	__IO uint32_t DOR2;
		292	__IO uint32_t SR;
		293	} DAC_TypeDef;
		294
		295	/**
		296	* @brief Debug MCU
		297	*/
		298
		299	typedef struct
		300	{
		301	__IO uint32_t IDCODE;
		302	__IO uint32_t CR;
		303	}DBGMCU_TypeDef;
		304
		305	/**
		306	* @brief DMA Controller
		307	*/
		308
		309	typedef struct
		310	{
		311	__IO uint32_t CCR;
		312	__IO uint32_t CNDTR;
		313	__IO uint32_t CPAR;
		314	__IO uint32_t CMAR;
		315	} DMA_Channel_TypeDef;
		316
		317	typedef struct
		318	{
		319	__IO uint32_t ISR;
		320	__IO uint32_t IFCR;
		321	} DMA_TypeDef;
		322
		323
		324
		325	/**
		326	* @brief External Interrupt/Event Controller
		327	*/
		328
		329	typedef struct
		330	{
		331	__IO uint32_t IMR;
		332	__IO uint32_t EMR;
		333	__IO uint32_t RTSR;
		334	__IO uint32_t FTSR;
		335	__IO uint32_t SWIER;
		336	__IO uint32_t PR;
		337	} EXTI_TypeDef;
		338
		339	/**
		340	* @brief FLASH Registers
		341	*/
		342
		343	typedef struct
		344	{
		345	__IO uint32_t ACR;
		346	__IO uint32_t KEYR;
		347	__IO uint32_t OPTKEYR;
		348	__IO uint32_t SR;
		349	__IO uint32_t CR;
		350	__IO uint32_t AR;
		351	__IO uint32_t RESERVED;
		352	__IO uint32_t OBR;
		353	__IO uint32_t WRPR;
		354	} FLASH_TypeDef;
		355
		356	/**
		357	* @brief Option Bytes Registers
		358	*/
		359
		360	typedef struct
		361	{
		362	__IO uint16_t RDP;
		363	__IO uint16_t USER;
		364	__IO uint16_t Data0;
		365	__IO uint16_t Data1;
		366	__IO uint16_t WRP0;
		367	__IO uint16_t WRP1;
		368	__IO uint16_t WRP2;
		369	__IO uint16_t WRP3;
		370	} OB_TypeDef;
		371
		372	/**
		373	* @brief Flexible Static Memory Controller
		374	*/
		375
		376	typedef struct
		377	{
		378	__IO uint32_t BTCR[8];
		379	} FSMC_Bank1_TypeDef;
		380
		381	/**
		382	* @brief Flexible Static Memory Controller Bank1E
		383	*/
		384
		385	typedef struct
		386	{
		387	__IO uint32_t BWTR[7];
		388	} FSMC_Bank1E_TypeDef;
		389
		390	/**
		391	* @brief General Purpose I/O
		392	*/
		393
		394	typedef struct
		395	{
		396	__IO uint32_t CRL;
		397	__IO uint32_t CRH;
		398	__IO uint32_t IDR;
		399	__IO uint32_t ODR;
		400	__IO uint32_t BSRR;
		401	__IO uint32_t BRR;
		402	__IO uint32_t LCKR;
		403	} GPIO_TypeDef;
		404
		405	/**
		406	* @brief Alternate Function I/O
		407	*/
		408
		409	typedef struct
		410	{
		411	__IO uint32_t EVCR;
		412	__IO uint32_t MAPR;
		413	__IO uint32_t EXTICR[4];
		414	uint32_t RESERVED0;
		415	__IO uint32_t MAPR2;
		416	} AFIO_TypeDef;
		417	/**
		418	* @brief Inter Integrated Circuit Interface
		419	*/
		420
		421	typedef struct
		422	{
		423	__IO uint32_t CR1;
		424	__IO uint32_t CR2;
		425	__IO uint32_t OAR1;
		426	__IO uint32_t OAR2;
		427	__IO uint32_t DR;
		428	__IO uint32_t SR1;
		429	__IO uint32_t SR2;
		430	__IO uint32_t CCR;
		431	__IO uint32_t TRISE;
		432	} I2C_TypeDef;
		433
		434	/**
		435	* @brief Independent WATCHDOG
		436	*/
		437
		438	typedef struct
		439	{
		440	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		441	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		442	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		443	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		444	} IWDG_TypeDef;
		445
		446	/**
		447	* @brief Power Control
		448	*/
		449
		450	typedef struct
		451	{
		452	__IO uint32_t CR;
		453	__IO uint32_t CSR;
		454	} PWR_TypeDef;
		455
		456	/**
		457	* @brief Reset and Clock Control
		458	*/
		459
		460	typedef struct
		461	{
		462	__IO uint32_t CR;
		463	__IO uint32_t CFGR;
		464	__IO uint32_t CIR;
		465	__IO uint32_t APB2RSTR;
		466	__IO uint32_t APB1RSTR;
		467	__IO uint32_t AHBENR;
		468	__IO uint32_t APB2ENR;
		469	__IO uint32_t APB1ENR;
		470	__IO uint32_t BDCR;
		471	__IO uint32_t CSR;
		472
		473
		474	uint32_t RESERVED0;
		475	__IO uint32_t CFGR2;
		476	} RCC_TypeDef;
		477
		478	/**
		479	* @brief Real-Time Clock
		480	*/
		481
		482	typedef struct
		483	{
		484	__IO uint32_t CRH;
		485	__IO uint32_t CRL;
		486	__IO uint32_t PRLH;
		487	__IO uint32_t PRLL;
		488	__IO uint32_t DIVH;
		489	__IO uint32_t DIVL;
		490	__IO uint32_t CNTH;
		491	__IO uint32_t CNTL;
		492	__IO uint32_t ALRH;
		493	__IO uint32_t ALRL;
		494	} RTC_TypeDef;
		495
		496	/**
		497	* @brief Serial Peripheral Interface
		498	*/
		499
		500	typedef struct
		501	{
		502	__IO uint32_t CR1;
		503	__IO uint32_t CR2;
		504	__IO uint32_t SR;
		505	__IO uint32_t DR;
		506	__IO uint32_t CRCPR;
		507	__IO uint32_t RXCRCR;
		508	__IO uint32_t TXCRCR;
		509	} SPI_TypeDef;
		510
		511	/**
		512	* @brief TIM Timers
		513	*/
		514	typedef struct
		515	{
		516	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		517	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		518	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		519	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		520	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		521	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		522	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		523	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		524	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		525	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		526	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		527	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		528	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
		529	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		530	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		531	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		532	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		533	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
		534	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		535	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
		536	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		537	}TIM_TypeDef;
		538
		539
		540	/**
		541	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		542	*/
		543
		544	typedef struct
		545	{
		546	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		547	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		548	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		549	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		550	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		551	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		552	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		553	} USART_TypeDef;
		554
		555
		556
		557	/**
		558	* @brief Window WATCHDOG
		559	*/
		560
		561	typedef struct
		562	{
		563	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		564	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		565	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		566	} WWDG_TypeDef;
		567
		568	/**
		569	* @}
		570	*/
		571
		572	/** @addtogroup Peripheral_memory_map
		573	* @{
		574	*/
		575
		576
		577	#define FLASH_BASE 0x08000000UL /!< FLASH base address in the alias region /
		578	#define FLASH_BANK1_END 0x0807FFFFUL /!< FLASH END address of bank1 /
		579	#define SRAM_BASE 0x20000000UL /!< SRAM base address in the alias region /
		580	#define PERIPH_BASE 0x40000000UL /!< Peripheral base address in the alias region /
		581
		582	#define SRAM_BB_BASE 0x22000000UL /!< SRAM base address in the bit-band region /
		583	#define PERIPH_BB_BASE 0x42000000UL /!< Peripheral base address in the bit-band region /
		584
		585	#define FSMC_BASE 0x60000000UL /!< FSMC base address /
		586	#define FSMC_R_BASE 0xA0000000UL /!< FSMC registers base address /
		587
		588	/!< Peripheral memory map /
		589	#define APB1PERIPH_BASE PERIPH_BASE
		590	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
		591	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
		592
		593	#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
		594	#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
		595	#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
		596	#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)
		597	#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)
		598	#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)
		599	#define TIM12_BASE (APB1PERIPH_BASE + 0x00001800UL)
		600	#define TIM13_BASE (APB1PERIPH_BASE + 0x00001C00UL)
		601	#define TIM14_BASE (APB1PERIPH_BASE + 0x00002000UL)
		602	#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
		603	#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
		604	#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
		605	#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
		606	#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)
		607	#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
		608	#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
		609	#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)
		610	#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)
		611	#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
		612	#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
		613	#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
		614	#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
		615	#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)
		616	#define CEC_BASE (APB1PERIPH_BASE + 0x00007800UL)
		617	#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)
		618	#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
		619	#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)
		620	#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
		621	#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
		622	#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
		623	#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)
		624	#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00UL)
		625	#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000UL)
		626	#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
		627	#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
		628	#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
		629	#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
		630	#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL)
		631	#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL)
		632	#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL)
		633
		634
		635	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
		636	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
		637	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
		638	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)
		639	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)
		640	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)
		641	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)
		642	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)
		643	#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL)
		644	#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL)
		645	#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL)
		646	#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL)
		647	#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL)
		648	#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL)
		649	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
		650	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
		651
		652	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /!< Flash registers base address /
		653	#define FLASHSIZE_BASE 0x1FFFF7E0UL /!< FLASH Size register base address /
		654	#define UID_BASE 0x1FFFF7E8UL /!< Unique device ID register base address /
		655	#define OB_BASE 0x1FFFF800UL /!< Flash Option Bytes base address /
		656
		657
		658	#define FSMC_BANK1 (FSMC_BASE) /!< FSMC Bank1 base address /
		659	#define FSMC_BANK1_1 (FSMC_BANK1) /!< FSMC Bank1_1 base address /
		660	#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL) /!< FSMC Bank1_2 base address /
		661	#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL) /!< FSMC Bank1_3 base address /
		662	#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL) /!< FSMC Bank1_4 base address /
		663
		664
		665	#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000UL) /!< FSMC Bank1 registers base address /
		666	#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104UL) /!< FSMC Bank1E registers base address /
		667
		668	#define DBGMCU_BASE 0xE0042000UL /!< Debug MCU registers base address /
		669
		670
		671
		672	/**
		673	* @}
		674	*/
		675
		676	/** @addtogroup Peripheral_declaration
		677	* @{
		678	*/
		679
		680	#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
		681	#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
		682	#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
		683	#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
		684	#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
		685	#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
		686	#define TIM12 ((TIM_TypeDef *)TIM12_BASE)
		687	#define TIM13 ((TIM_TypeDef *)TIM13_BASE)
		688	#define TIM14 ((TIM_TypeDef *)TIM14_BASE)
		689	#define RTC ((RTC_TypeDef *)RTC_BASE)
		690	#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
		691	#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
		692	#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
		693	#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
		694	#define USART2 ((USART_TypeDef *)USART2_BASE)
		695	#define USART3 ((USART_TypeDef *)USART3_BASE)
		696	#define UART4 ((USART_TypeDef *)UART4_BASE)
		697	#define UART5 ((USART_TypeDef *)UART5_BASE)
		698	#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
		699	#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
		700	#define BKP ((BKP_TypeDef *)BKP_BASE)
		701	#define PWR ((PWR_TypeDef *)PWR_BASE)
		702	#define DAC1 ((DAC_TypeDef *)DAC_BASE)
		703	#define DAC ((DAC_TypeDef )DAC_BASE) / Kept for legacy purpose */
		704	#define CEC ((CEC_TypeDef *)CEC_BASE)
		705	#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
		706	#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
		707	#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
		708	#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
		709	#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
		710	#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
		711	#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
		712	#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
		713	#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)
		714	#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
		715	#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
		716	#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
		717	#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
		718	#define USART1 ((USART_TypeDef *)USART1_BASE)
		719	#define TIM15 ((TIM_TypeDef *)TIM15_BASE)
		720	#define TIM16 ((TIM_TypeDef *)TIM16_BASE)
		721	#define TIM17 ((TIM_TypeDef *)TIM17_BASE)
		722	#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
		723	#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
		724	#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
		725	#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
		726	#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
		727	#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
		728	#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
		729	#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
		730	#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
		731	#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
		732	#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
		733	#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
		734	#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
		735	#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
		736	#define RCC ((RCC_TypeDef *)RCC_BASE)
		737	#define CRC ((CRC_TypeDef *)CRC_BASE)
		738	#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
		739	#define OB ((OB_TypeDef *)OB_BASE)
		740	#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)
		741	#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)
		742	#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
		743
		744
		745	/**
		746	* @}
		747	*/
		748
		749	/** @addtogroup Exported_constants
		750	* @{
		751	*/
		752
		753	/** @addtogroup Peripheral_Registers_Bits_Definition
		754	* @{
		755	*/
		756
		757	/******************************************************************************/
		758	/* Peripheral Registers_Bits_Definition */
		759	/******************************************************************************/
		760
		761	/******************************************************************************/
		762	/* */
		763	/* CRC calculation unit (CRC) */
		764	/* */
		765	/******************************************************************************/
		766
		767	/***************** Bit definition for CRC_DR register *******************/
		768	#define CRC_DR_DR_Pos (0U)
		769	#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /!< 0xFFFFFFFF /
		770	#define CRC_DR_DR CRC_DR_DR_Msk /!< Data register bits /
		771
		772	/***************** Bit definition for CRC_IDR register ******************/
		773	#define CRC_IDR_IDR_Pos (0U)
		774	#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /!< 0x000000FF /
		775	#define CRC_IDR_IDR CRC_IDR_IDR_Msk /!< General-purpose 8-bit data register bits /
		776
		777	/****************** Bit definition for CRC_CR register ******************/
		778	#define CRC_CR_RESET_Pos (0U)
		779	#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /!< 0x00000001 /
		780	#define CRC_CR_RESET CRC_CR_RESET_Msk /!< RESET bit /
		781
		782	/******************************************************************************/
		783	/* */
		784	/* Power Control */
		785	/* */
		786	/******************************************************************************/
		787
		788	/****************** Bit definition for PWR_CR register ******************/
		789	#define PWR_CR_LPDS_Pos (0U)
		790	#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /!< 0x00000001 /
		791	#define PWR_CR_LPDS PWR_CR_LPDS_Msk /!< Low-Power Deepsleep /
		792	#define PWR_CR_PDDS_Pos (1U)
		793	#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /!< 0x00000002 /
		794	#define PWR_CR_PDDS PWR_CR_PDDS_Msk /!< Power Down Deepsleep /
		795	#define PWR_CR_CWUF_Pos (2U)
		796	#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /!< 0x00000004 /
		797	#define PWR_CR_CWUF PWR_CR_CWUF_Msk /!< Clear Wakeup Flag /
		798	#define PWR_CR_CSBF_Pos (3U)
		799	#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /!< 0x00000008 /
		800	#define PWR_CR_CSBF PWR_CR_CSBF_Msk /!< Clear Standby Flag /
		801	#define PWR_CR_PVDE_Pos (4U)
		802	#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /!< 0x00000010 /
		803	#define PWR_CR_PVDE PWR_CR_PVDE_Msk /!< Power Voltage Detector Enable /
		804
		805	#define PWR_CR_PLS_Pos (5U)
		806	#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /!< 0x000000E0 /
		807	#define PWR_CR_PLS PWR_CR_PLS_Msk /!< PLS[2:0] bits (PVD Level Selection) /
		808	#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /!< 0x00000020 /
		809	#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /!< 0x00000040 /
		810	#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /!< 0x00000080 /
		811
		812	/!< PVD level configuration /
		813	#define PWR_CR_PLS_LEV0 0x00000000U /!< PVD level 2.2V /
		814	#define PWR_CR_PLS_LEV1 0x00000020U /!< PVD level 2.3V /
		815	#define PWR_CR_PLS_LEV2 0x00000040U /!< PVD level 2.4V /
		816	#define PWR_CR_PLS_LEV3 0x00000060U /!< PVD level 2.5V /
		817	#define PWR_CR_PLS_LEV4 0x00000080U /!< PVD level 2.6V /
		818	#define PWR_CR_PLS_LEV5 0x000000A0U /!< PVD level 2.7V /
		819	#define PWR_CR_PLS_LEV6 0x000000C0U /!< PVD level 2.8V /
		820	#define PWR_CR_PLS_LEV7 0x000000E0U /!< PVD level 2.9V /
		821
		822	/* Legacy defines */
		823	#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
		824	#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
		825	#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
		826	#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
		827	#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
		828	#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
		829	#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
		830	#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
		831
		832	#define PWR_CR_DBP_Pos (8U)
		833	#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /!< 0x00000100 /
		834	#define PWR_CR_DBP PWR_CR_DBP_Msk /!< Disable Backup Domain write protection /
		835
		836
		837	/***************** Bit definition for PWR_CSR register ******************/
		838	#define PWR_CSR_WUF_Pos (0U)
		839	#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /!< 0x00000001 /
		840	#define PWR_CSR_WUF PWR_CSR_WUF_Msk /!< Wakeup Flag /
		841	#define PWR_CSR_SBF_Pos (1U)
		842	#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /!< 0x00000002 /
		843	#define PWR_CSR_SBF PWR_CSR_SBF_Msk /!< Standby Flag /
		844	#define PWR_CSR_PVDO_Pos (2U)
		845	#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /!< 0x00000004 /
		846	#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /!< PVD Output /
		847	#define PWR_CSR_EWUP_Pos (8U)
		848	#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /!< 0x00000100 /
		849	#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /!< Enable WKUP pin /
		850
		851	/******************************************************************************/
		852	/* */
		853	/* Backup registers */
		854	/* */
		855	/******************************************************************************/
		856
		857	/***************** Bit definition for BKP_DR1 register ******************/
		858	#define BKP_DR1_D_Pos (0U)
		859	#define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /!< 0x0000FFFF /
		860	#define BKP_DR1_D BKP_DR1_D_Msk /!< Backup data /
		861
		862	/***************** Bit definition for BKP_DR2 register ******************/
		863	#define BKP_DR2_D_Pos (0U)
		864	#define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /!< 0x0000FFFF /
		865	#define BKP_DR2_D BKP_DR2_D_Msk /!< Backup data /
		866
		867	/***************** Bit definition for BKP_DR3 register ******************/
		868	#define BKP_DR3_D_Pos (0U)
		869	#define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /!< 0x0000FFFF /
		870	#define BKP_DR3_D BKP_DR3_D_Msk /!< Backup data /
		871
		872	/***************** Bit definition for BKP_DR4 register ******************/
		873	#define BKP_DR4_D_Pos (0U)
		874	#define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /!< 0x0000FFFF /
		875	#define BKP_DR4_D BKP_DR4_D_Msk /!< Backup data /
		876
		877	/***************** Bit definition for BKP_DR5 register ******************/
		878	#define BKP_DR5_D_Pos (0U)
		879	#define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /!< 0x0000FFFF /
		880	#define BKP_DR5_D BKP_DR5_D_Msk /!< Backup data /
		881
		882	/***************** Bit definition for BKP_DR6 register ******************/
		883	#define BKP_DR6_D_Pos (0U)
		884	#define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /!< 0x0000FFFF /
		885	#define BKP_DR6_D BKP_DR6_D_Msk /!< Backup data /
		886
		887	/***************** Bit definition for BKP_DR7 register ******************/
		888	#define BKP_DR7_D_Pos (0U)
		889	#define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /!< 0x0000FFFF /
		890	#define BKP_DR7_D BKP_DR7_D_Msk /!< Backup data /
		891
		892	/***************** Bit definition for BKP_DR8 register ******************/
		893	#define BKP_DR8_D_Pos (0U)
		894	#define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /!< 0x0000FFFF /
		895	#define BKP_DR8_D BKP_DR8_D_Msk /!< Backup data /
		896
		897	/***************** Bit definition for BKP_DR9 register ******************/
		898	#define BKP_DR9_D_Pos (0U)
		899	#define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /!< 0x0000FFFF /
		900	#define BKP_DR9_D BKP_DR9_D_Msk /!< Backup data /
		901
		902	/***************** Bit definition for BKP_DR10 register *****************/
		903	#define BKP_DR10_D_Pos (0U)
		904	#define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /!< 0x0000FFFF /
		905	#define BKP_DR10_D BKP_DR10_D_Msk /!< Backup data /
		906
		907	/***************** Bit definition for BKP_DR11 register *****************/
		908	#define BKP_DR11_D_Pos (0U)
		909	#define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos) /!< 0x0000FFFF /
		910	#define BKP_DR11_D BKP_DR11_D_Msk /!< Backup data /
		911
		912	/***************** Bit definition for BKP_DR12 register *****************/
		913	#define BKP_DR12_D_Pos (0U)
		914	#define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos) /!< 0x0000FFFF /
		915	#define BKP_DR12_D BKP_DR12_D_Msk /!< Backup data /
		916
		917	/***************** Bit definition for BKP_DR13 register *****************/
		918	#define BKP_DR13_D_Pos (0U)
		919	#define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos) /!< 0x0000FFFF /
		920	#define BKP_DR13_D BKP_DR13_D_Msk /!< Backup data /
		921
		922	/***************** Bit definition for BKP_DR14 register *****************/
		923	#define BKP_DR14_D_Pos (0U)
		924	#define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos) /!< 0x0000FFFF /
		925	#define BKP_DR14_D BKP_DR14_D_Msk /!< Backup data /
		926
		927	/***************** Bit definition for BKP_DR15 register *****************/
		928	#define BKP_DR15_D_Pos (0U)
		929	#define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos) /!< 0x0000FFFF /
		930	#define BKP_DR15_D BKP_DR15_D_Msk /!< Backup data /
		931
		932	/***************** Bit definition for BKP_DR16 register *****************/
		933	#define BKP_DR16_D_Pos (0U)
		934	#define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos) /!< 0x0000FFFF /
		935	#define BKP_DR16_D BKP_DR16_D_Msk /!< Backup data /
		936
		937	/***************** Bit definition for BKP_DR17 register *****************/
		938	#define BKP_DR17_D_Pos (0U)
		939	#define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos) /!< 0x0000FFFF /
		940	#define BKP_DR17_D BKP_DR17_D_Msk /!< Backup data /
		941
		942	/**************** Bit definition for BKP_DR18 register ******************/
		943	#define BKP_DR18_D_Pos (0U)
		944	#define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos) /!< 0x0000FFFF /
		945	#define BKP_DR18_D BKP_DR18_D_Msk /!< Backup data /
		946
		947	/***************** Bit definition for BKP_DR19 register *****************/
		948	#define BKP_DR19_D_Pos (0U)
		949	#define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos) /!< 0x0000FFFF /
		950	#define BKP_DR19_D BKP_DR19_D_Msk /!< Backup data /
		951
		952	/***************** Bit definition for BKP_DR20 register *****************/
		953	#define BKP_DR20_D_Pos (0U)
		954	#define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos) /!< 0x0000FFFF /
		955	#define BKP_DR20_D BKP_DR20_D_Msk /!< Backup data /
		956
		957	/***************** Bit definition for BKP_DR21 register *****************/
		958	#define BKP_DR21_D_Pos (0U)
		959	#define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos) /!< 0x0000FFFF /
		960	#define BKP_DR21_D BKP_DR21_D_Msk /!< Backup data /
		961
		962	/***************** Bit definition for BKP_DR22 register *****************/
		963	#define BKP_DR22_D_Pos (0U)
		964	#define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos) /!< 0x0000FFFF /
		965	#define BKP_DR22_D BKP_DR22_D_Msk /!< Backup data /
		966
		967	/***************** Bit definition for BKP_DR23 register *****************/
		968	#define BKP_DR23_D_Pos (0U)
		969	#define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos) /!< 0x0000FFFF /
		970	#define BKP_DR23_D BKP_DR23_D_Msk /!< Backup data /
		971
		972	/***************** Bit definition for BKP_DR24 register *****************/
		973	#define BKP_DR24_D_Pos (0U)
		974	#define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos) /!< 0x0000FFFF /
		975	#define BKP_DR24_D BKP_DR24_D_Msk /!< Backup data /
		976
		977	/***************** Bit definition for BKP_DR25 register *****************/
		978	#define BKP_DR25_D_Pos (0U)
		979	#define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos) /!< 0x0000FFFF /
		980	#define BKP_DR25_D BKP_DR25_D_Msk /!< Backup data /
		981
		982	/***************** Bit definition for BKP_DR26 register *****************/
		983	#define BKP_DR26_D_Pos (0U)
		984	#define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos) /!< 0x0000FFFF /
		985	#define BKP_DR26_D BKP_DR26_D_Msk /!< Backup data /
		986
		987	/***************** Bit definition for BKP_DR27 register *****************/
		988	#define BKP_DR27_D_Pos (0U)
		989	#define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos) /!< 0x0000FFFF /
		990	#define BKP_DR27_D BKP_DR27_D_Msk /!< Backup data /
		991
		992	/***************** Bit definition for BKP_DR28 register *****************/
		993	#define BKP_DR28_D_Pos (0U)
		994	#define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos) /!< 0x0000FFFF /
		995	#define BKP_DR28_D BKP_DR28_D_Msk /!< Backup data /
		996
		997	/***************** Bit definition for BKP_DR29 register *****************/
		998	#define BKP_DR29_D_Pos (0U)
		999	#define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos) /!< 0x0000FFFF /
		1000	#define BKP_DR29_D BKP_DR29_D_Msk /!< Backup data /
		1001
		1002	/***************** Bit definition for BKP_DR30 register *****************/
		1003	#define BKP_DR30_D_Pos (0U)
		1004	#define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos) /!< 0x0000FFFF /
		1005	#define BKP_DR30_D BKP_DR30_D_Msk /!< Backup data /
		1006
		1007	/***************** Bit definition for BKP_DR31 register *****************/
		1008	#define BKP_DR31_D_Pos (0U)
		1009	#define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos) /!< 0x0000FFFF /
		1010	#define BKP_DR31_D BKP_DR31_D_Msk /!< Backup data /
		1011
		1012	/***************** Bit definition for BKP_DR32 register *****************/
		1013	#define BKP_DR32_D_Pos (0U)
		1014	#define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos) /!< 0x0000FFFF /
		1015	#define BKP_DR32_D BKP_DR32_D_Msk /!< Backup data /
		1016
		1017	/***************** Bit definition for BKP_DR33 register *****************/
		1018	#define BKP_DR33_D_Pos (0U)
		1019	#define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos) /!< 0x0000FFFF /
		1020	#define BKP_DR33_D BKP_DR33_D_Msk /!< Backup data /
		1021
		1022	/***************** Bit definition for BKP_DR34 register *****************/
		1023	#define BKP_DR34_D_Pos (0U)
		1024	#define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos) /!< 0x0000FFFF /
		1025	#define BKP_DR34_D BKP_DR34_D_Msk /!< Backup data /
		1026
		1027	/***************** Bit definition for BKP_DR35 register *****************/
		1028	#define BKP_DR35_D_Pos (0U)
		1029	#define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos) /!< 0x0000FFFF /
		1030	#define BKP_DR35_D BKP_DR35_D_Msk /!< Backup data /
		1031
		1032	/***************** Bit definition for BKP_DR36 register *****************/
		1033	#define BKP_DR36_D_Pos (0U)
		1034	#define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos) /!< 0x0000FFFF /
		1035	#define BKP_DR36_D BKP_DR36_D_Msk /!< Backup data /
		1036
		1037	/***************** Bit definition for BKP_DR37 register *****************/
		1038	#define BKP_DR37_D_Pos (0U)
		1039	#define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos) /!< 0x0000FFFF /
		1040	#define BKP_DR37_D BKP_DR37_D_Msk /!< Backup data /
		1041
		1042	/***************** Bit definition for BKP_DR38 register *****************/
		1043	#define BKP_DR38_D_Pos (0U)
		1044	#define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos) /!< 0x0000FFFF /
		1045	#define BKP_DR38_D BKP_DR38_D_Msk /!< Backup data /
		1046
		1047	/***************** Bit definition for BKP_DR39 register *****************/
		1048	#define BKP_DR39_D_Pos (0U)
		1049	#define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos) /!< 0x0000FFFF /
		1050	#define BKP_DR39_D BKP_DR39_D_Msk /!< Backup data /
		1051
		1052	/***************** Bit definition for BKP_DR40 register *****************/
		1053	#define BKP_DR40_D_Pos (0U)
		1054	#define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos) /!< 0x0000FFFF /
		1055	#define BKP_DR40_D BKP_DR40_D_Msk /!< Backup data /
		1056
		1057	/***************** Bit definition for BKP_DR41 register *****************/
		1058	#define BKP_DR41_D_Pos (0U)
		1059	#define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos) /!< 0x0000FFFF /
		1060	#define BKP_DR41_D BKP_DR41_D_Msk /!< Backup data /
		1061
		1062	/***************** Bit definition for BKP_DR42 register *****************/
		1063	#define BKP_DR42_D_Pos (0U)
		1064	#define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos) /!< 0x0000FFFF /
		1065	#define BKP_DR42_D BKP_DR42_D_Msk /!< Backup data /
		1066
		1067	#define RTC_BKP_NUMBER 42
		1068
		1069	/**************** Bit definition for BKP_RTCCR register *****************/
		1070	#define BKP_RTCCR_CAL_Pos (0U)
		1071	#define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /!< 0x0000007F /
		1072	#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /!< Calibration value /
		1073	#define BKP_RTCCR_CCO_Pos (7U)
		1074	#define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /!< 0x00000080 /
		1075	#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /!< Calibration Clock Output /
		1076	#define BKP_RTCCR_ASOE_Pos (8U)
		1077	#define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /!< 0x00000100 /
		1078	#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /!< Alarm or Second Output Enable /
		1079	#define BKP_RTCCR_ASOS_Pos (9U)
		1080	#define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /!< 0x00000200 /
		1081	#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /!< Alarm or Second Output Selection /
		1082
		1083	/****************** Bit definition for BKP_CR register ******************/
		1084	#define BKP_CR_TPE_Pos (0U)
		1085	#define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /!< 0x00000001 /
		1086	#define BKP_CR_TPE BKP_CR_TPE_Msk /!< TAMPER pin enable /
		1087	#define BKP_CR_TPAL_Pos (1U)
		1088	#define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /!< 0x00000002 /
		1089	#define BKP_CR_TPAL BKP_CR_TPAL_Msk /!< TAMPER pin active level /
		1090
		1091	/***************** Bit definition for BKP_CSR register ******************/
		1092	#define BKP_CSR_CTE_Pos (0U)
		1093	#define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /!< 0x00000001 /
		1094	#define BKP_CSR_CTE BKP_CSR_CTE_Msk /!< Clear Tamper event /
		1095	#define BKP_CSR_CTI_Pos (1U)
		1096	#define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /!< 0x00000002 /
		1097	#define BKP_CSR_CTI BKP_CSR_CTI_Msk /!< Clear Tamper Interrupt /
		1098	#define BKP_CSR_TPIE_Pos (2U)
		1099	#define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /!< 0x00000004 /
		1100	#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /!< TAMPER Pin interrupt enable /
		1101	#define BKP_CSR_TEF_Pos (8U)
		1102	#define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /!< 0x00000100 /
		1103	#define BKP_CSR_TEF BKP_CSR_TEF_Msk /!< Tamper Event Flag /
		1104	#define BKP_CSR_TIF_Pos (9U)
		1105	#define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /!< 0x00000200 /
		1106	#define BKP_CSR_TIF BKP_CSR_TIF_Msk /!< Tamper Interrupt Flag /
		1107
		1108	/******************************************************************************/
		1109	/* */
		1110	/* Reset and Clock Control */
		1111	/* */
		1112	/******************************************************************************/
		1113
		1114	/****************** Bit definition for RCC_CR register ******************/
		1115	#define RCC_CR_HSION_Pos (0U)
		1116	#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /!< 0x00000001 /
		1117	#define RCC_CR_HSION RCC_CR_HSION_Msk /!< Internal High Speed clock enable /
		1118	#define RCC_CR_HSIRDY_Pos (1U)
		1119	#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /!< 0x00000002 /
		1120	#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /!< Internal High Speed clock ready flag /
		1121	#define RCC_CR_HSITRIM_Pos (3U)
		1122	#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /!< 0x000000F8 /
		1123	#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /!< Internal High Speed clock trimming /
		1124	#define RCC_CR_HSICAL_Pos (8U)
		1125	#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /!< 0x0000FF00 /
		1126	#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /!< Internal High Speed clock Calibration /
		1127	#define RCC_CR_HSEON_Pos (16U)
		1128	#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /!< 0x00010000 /
		1129	#define RCC_CR_HSEON RCC_CR_HSEON_Msk /!< External High Speed clock enable /
		1130	#define RCC_CR_HSERDY_Pos (17U)
		1131	#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /!< 0x00020000 /
		1132	#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /!< External High Speed clock ready flag /
		1133	#define RCC_CR_HSEBYP_Pos (18U)
		1134	#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /!< 0x00040000 /
		1135	#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /!< External High Speed clock Bypass /
		1136	#define RCC_CR_CSSON_Pos (19U)
		1137	#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /!< 0x00080000 /
		1138	#define RCC_CR_CSSON RCC_CR_CSSON_Msk /!< Clock Security System enable /
		1139	#define RCC_CR_PLLON_Pos (24U)
		1140	#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /!< 0x01000000 /
		1141	#define RCC_CR_PLLON RCC_CR_PLLON_Msk /!< PLL enable /
		1142	#define RCC_CR_PLLRDY_Pos (25U)
		1143	#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /!< 0x02000000 /
		1144	#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /!< PLL clock ready flag /
		1145
		1146
		1147	/***************** Bit definition for RCC_CFGR register *****************/
		1148	/!< SW configuration /
		1149	#define RCC_CFGR_SW_Pos (0U)
		1150	#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /!< 0x00000003 /
		1151	#define RCC_CFGR_SW RCC_CFGR_SW_Msk /!< SW[1:0] bits (System clock Switch) /
		1152	#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /!< 0x00000001 /
		1153	#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /!< 0x00000002 /
		1154
		1155	#define RCC_CFGR_SW_HSI 0x00000000U /!< HSI selected as system clock /
		1156	#define RCC_CFGR_SW_HSE 0x00000001U /!< HSE selected as system clock /
		1157	#define RCC_CFGR_SW_PLL 0x00000002U /!< PLL selected as system clock /
		1158
		1159	/!< SWS configuration /
		1160	#define RCC_CFGR_SWS_Pos (2U)
		1161	#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /!< 0x0000000C /
		1162	#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /!< SWS[1:0] bits (System Clock Switch Status) /
		1163	#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /!< 0x00000004 /
		1164	#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /!< 0x00000008 /
		1165
		1166	#define RCC_CFGR_SWS_HSI 0x00000000U /!< HSI oscillator used as system clock /
		1167	#define RCC_CFGR_SWS_HSE 0x00000004U /!< HSE oscillator used as system clock /
		1168	#define RCC_CFGR_SWS_PLL 0x00000008U /!< PLL used as system clock /
		1169
		1170	/!< HPRE configuration /
		1171	#define RCC_CFGR_HPRE_Pos (4U)
		1172	#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /!< 0x000000F0 /
		1173	#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /!< HPRE[3:0] bits (AHB prescaler) /
		1174	#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /!< 0x00000010 /
		1175	#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /!< 0x00000020 /
		1176	#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /!< 0x00000040 /
		1177	#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /!< 0x00000080 /
		1178
		1179	#define RCC_CFGR_HPRE_DIV1 0x00000000U /!< SYSCLK not divided /
		1180	#define RCC_CFGR_HPRE_DIV2 0x00000080U /!< SYSCLK divided by 2 /
		1181	#define RCC_CFGR_HPRE_DIV4 0x00000090U /!< SYSCLK divided by 4 /
		1182	#define RCC_CFGR_HPRE_DIV8 0x000000A0U /!< SYSCLK divided by 8 /
		1183	#define RCC_CFGR_HPRE_DIV16 0x000000B0U /!< SYSCLK divided by 16 /
		1184	#define RCC_CFGR_HPRE_DIV64 0x000000C0U /!< SYSCLK divided by 64 /
		1185	#define RCC_CFGR_HPRE_DIV128 0x000000D0U /!< SYSCLK divided by 128 /
		1186	#define RCC_CFGR_HPRE_DIV256 0x000000E0U /!< SYSCLK divided by 256 /
		1187	#define RCC_CFGR_HPRE_DIV512 0x000000F0U /!< SYSCLK divided by 512 /
		1188
		1189	/!< PPRE1 configuration /
		1190	#define RCC_CFGR_PPRE1_Pos (8U)
		1191	#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000700 /
		1192	#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /!< PRE1[2:0] bits (APB1 prescaler) /
		1193	#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000100 /
		1194	#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000200 /
		1195	#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000400 /
		1196
		1197	#define RCC_CFGR_PPRE1_DIV1 0x00000000U /!< HCLK not divided /
		1198	#define RCC_CFGR_PPRE1_DIV2 0x00000400U /!< HCLK divided by 2 /
		1199	#define RCC_CFGR_PPRE1_DIV4 0x00000500U /!< HCLK divided by 4 /
		1200	#define RCC_CFGR_PPRE1_DIV8 0x00000600U /!< HCLK divided by 8 /
		1201	#define RCC_CFGR_PPRE1_DIV16 0x00000700U /!< HCLK divided by 16 /
		1202
		1203	/!< PPRE2 configuration /
		1204	#define RCC_CFGR_PPRE2_Pos (11U)
		1205	#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /!< 0x00003800 /
		1206	#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /!< PRE2[2:0] bits (APB2 prescaler) /
		1207	#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /!< 0x00000800 /
		1208	#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /!< 0x00001000 /
		1209	#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /!< 0x00002000 /
		1210
		1211	#define RCC_CFGR_PPRE2_DIV1 0x00000000U /!< HCLK not divided /
		1212	#define RCC_CFGR_PPRE2_DIV2 0x00002000U /!< HCLK divided by 2 /
		1213	#define RCC_CFGR_PPRE2_DIV4 0x00002800U /!< HCLK divided by 4 /
		1214	#define RCC_CFGR_PPRE2_DIV8 0x00003000U /!< HCLK divided by 8 /
		1215	#define RCC_CFGR_PPRE2_DIV16 0x00003800U /!< HCLK divided by 16 /
		1216
		1217	/!< ADCPPRE configuration /
		1218	#define RCC_CFGR_ADCPRE_Pos (14U)
		1219	#define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /!< 0x0000C000 /
		1220	#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /!< ADCPRE[1:0] bits (ADC prescaler) /
		1221	#define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /!< 0x00004000 /
		1222	#define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /!< 0x00008000 /
		1223
		1224	#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /!< PCLK2 divided by 2 /
		1225	#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /!< PCLK2 divided by 4 /
		1226	#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /!< PCLK2 divided by 6 /
		1227	#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /!< PCLK2 divided by 8 /
		1228
		1229	#define RCC_CFGR_PLLSRC_Pos (16U)
		1230	#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /!< 0x00010000 /
		1231	#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /!< PLL entry clock source /
		1232
		1233	#define RCC_CFGR_PLLXTPRE_Pos (17U)
		1234	#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /!< 0x00020000 /
		1235	#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /!< HSE divider for PLL entry /
		1236
		1237	/!< PLLMUL configuration /
		1238	#define RCC_CFGR_PLLMULL_Pos (18U)
		1239	#define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /!< 0x003C0000 /
		1240	#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /!< PLLMUL[3:0] bits (PLL multiplication factor) /
		1241	#define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /!< 0x00040000 /
		1242	#define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /!< 0x00080000 /
		1243	#define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /!< 0x00100000 /
		1244	#define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /!< 0x00200000 /
		1245
		1246	#define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /!< PREDIV1 clock not divided for PLL entry /
		1247	#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /!< PREDIV1 clock divided by 2 for PLL entry /
		1248
		1249	#define RCC_CFGR_PLLMULL2 0x00000000U /!< PLL input clock2 */
		1250	#define RCC_CFGR_PLLMULL3_Pos (18U)
		1251	#define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /!< 0x00040000 /
		1252	#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /!< PLL input clock3 */
		1253	#define RCC_CFGR_PLLMULL4_Pos (19U)
		1254	#define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /!< 0x00080000 /
		1255	#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /!< PLL input clock4 */
		1256	#define RCC_CFGR_PLLMULL5_Pos (18U)
		1257	#define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /!< 0x000C0000 /
		1258	#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /!< PLL input clock5 */
		1259	#define RCC_CFGR_PLLMULL6_Pos (20U)
		1260	#define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /!< 0x00100000 /
		1261	#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /!< PLL input clock6 */
		1262	#define RCC_CFGR_PLLMULL7_Pos (18U)
		1263	#define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /!< 0x00140000 /
		1264	#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /!< PLL input clock7 */
		1265	#define RCC_CFGR_PLLMULL8_Pos (19U)
		1266	#define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /!< 0x00180000 /
		1267	#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /!< PLL input clock8 */
		1268	#define RCC_CFGR_PLLMULL9_Pos (18U)
		1269	#define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /!< 0x001C0000 /
		1270	#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /!< PLL input clock9 */
		1271	#define RCC_CFGR_PLLMULL10_Pos (21U)
		1272	#define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /!< 0x00200000 /
		1273	#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /!< PLL input clock10 /
		1274	#define RCC_CFGR_PLLMULL11_Pos (18U)
		1275	#define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /!< 0x00240000 /
		1276	#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /!< PLL input clock11 */
		1277	#define RCC_CFGR_PLLMULL12_Pos (19U)
		1278	#define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /!< 0x00280000 /
		1279	#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /!< PLL input clock12 */
		1280	#define RCC_CFGR_PLLMULL13_Pos (18U)
		1281	#define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /!< 0x002C0000 /
		1282	#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /!< PLL input clock13 */
		1283	#define RCC_CFGR_PLLMULL14_Pos (20U)
		1284	#define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /!< 0x00300000 /
		1285	#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /!< PLL input clock14 */
		1286	#define RCC_CFGR_PLLMULL15_Pos (18U)
		1287	#define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /!< 0x00340000 /
		1288	#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /!< PLL input clock15 */
		1289	#define RCC_CFGR_PLLMULL16_Pos (19U)
		1290	#define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /!< 0x00380000 /
		1291	#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /!< PLL input clock16 */
		1292
		1293	/!< MCO configuration /
		1294	#define RCC_CFGR_MCO_Pos (24U)
		1295	#define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /!< 0x07000000 /
		1296	#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /!< MCO[2:0] bits (Microcontroller Clock Output) /
		1297	#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /!< 0x01000000 /
		1298	#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /!< 0x02000000 /
		1299	#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /!< 0x04000000 /
		1300
		1301	#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /!< No clock /
		1302	#define RCC_CFGR_MCO_SYSCLK 0x04000000U /!< System clock selected as MCO source /
		1303	#define RCC_CFGR_MCO_HSI 0x05000000U /!< HSI clock selected as MCO source /
		1304	#define RCC_CFGR_MCO_HSE 0x06000000U /!< HSE clock selected as MCO source /
		1305	#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /!< PLL clock divided by 2 selected as MCO source /
		1306
		1307	/* Reference defines */
		1308	#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
		1309	#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
		1310	#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
		1311	#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
		1312	#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
		1313	#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
		1314	#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
		1315	#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
		1316	#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
		1317
		1318	/!<*************** Bit definition for RCC_CIR register ******************/
		1319	#define RCC_CIR_LSIRDYF_Pos (0U)
		1320	#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /!< 0x00000001 /
		1321	#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /!< LSI Ready Interrupt flag /
		1322	#define RCC_CIR_LSERDYF_Pos (1U)
		1323	#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /!< 0x00000002 /
		1324	#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /!< LSE Ready Interrupt flag /
		1325	#define RCC_CIR_HSIRDYF_Pos (2U)
		1326	#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /!< 0x00000004 /
		1327	#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /!< HSI Ready Interrupt flag /
		1328	#define RCC_CIR_HSERDYF_Pos (3U)
		1329	#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /!< 0x00000008 /
		1330	#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /!< HSE Ready Interrupt flag /
		1331	#define RCC_CIR_PLLRDYF_Pos (4U)
		1332	#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /!< 0x00000010 /
		1333	#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /!< PLL Ready Interrupt flag /
		1334	#define RCC_CIR_CSSF_Pos (7U)
		1335	#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /!< 0x00000080 /
		1336	#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /!< Clock Security System Interrupt flag /
		1337	#define RCC_CIR_LSIRDYIE_Pos (8U)
		1338	#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /!< 0x00000100 /
		1339	#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /!< LSI Ready Interrupt Enable /
		1340	#define RCC_CIR_LSERDYIE_Pos (9U)
		1341	#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /!< 0x00000200 /
		1342	#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /!< LSE Ready Interrupt Enable /
		1343	#define RCC_CIR_HSIRDYIE_Pos (10U)
		1344	#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /!< 0x00000400 /
		1345	#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /!< HSI Ready Interrupt Enable /
		1346	#define RCC_CIR_HSERDYIE_Pos (11U)
		1347	#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /!< 0x00000800 /
		1348	#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /!< HSE Ready Interrupt Enable /
		1349	#define RCC_CIR_PLLRDYIE_Pos (12U)
		1350	#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /!< 0x00001000 /
		1351	#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /!< PLL Ready Interrupt Enable /
		1352	#define RCC_CIR_LSIRDYC_Pos (16U)
		1353	#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /!< 0x00010000 /
		1354	#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /!< LSI Ready Interrupt Clear /
		1355	#define RCC_CIR_LSERDYC_Pos (17U)
		1356	#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /!< 0x00020000 /
		1357	#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /!< LSE Ready Interrupt Clear /
		1358	#define RCC_CIR_HSIRDYC_Pos (18U)
		1359	#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /!< 0x00040000 /
		1360	#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /!< HSI Ready Interrupt Clear /
		1361	#define RCC_CIR_HSERDYC_Pos (19U)
		1362	#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /!< 0x00080000 /
		1363	#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /!< HSE Ready Interrupt Clear /
		1364	#define RCC_CIR_PLLRDYC_Pos (20U)
		1365	#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /!< 0x00100000 /
		1366	#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /!< PLL Ready Interrupt Clear /
		1367	#define RCC_CIR_CSSC_Pos (23U)
		1368	#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /!< 0x00800000 /
		1369	#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /!< Clock Security System Interrupt Clear /
		1370
		1371
		1372	/*************** Bit definition for RCC_APB2RSTR register ***************/
		1373	#define RCC_APB2RSTR_AFIORST_Pos (0U)
		1374	#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /!< 0x00000001 /
		1375	#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /!< Alternate Function I/O reset /
		1376	#define RCC_APB2RSTR_IOPARST_Pos (2U)
		1377	#define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /!< 0x00000004 /
		1378	#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /!< I/O port A reset /
		1379	#define RCC_APB2RSTR_IOPBRST_Pos (3U)
		1380	#define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /!< 0x00000008 /
		1381	#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /!< I/O port B reset /
		1382	#define RCC_APB2RSTR_IOPCRST_Pos (4U)
		1383	#define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /!< 0x00000010 /
		1384	#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /!< I/O port C reset /
		1385	#define RCC_APB2RSTR_IOPDRST_Pos (5U)
		1386	#define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /!< 0x00000020 /
		1387	#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /!< I/O port D reset /
		1388	#define RCC_APB2RSTR_ADC1RST_Pos (9U)
		1389	#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /!< 0x00000200 /
		1390	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /!< ADC 1 interface reset /
		1391
		1392
		1393	#define RCC_APB2RSTR_TIM1RST_Pos (11U)
		1394	#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /!< 0x00000800 /
		1395	#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /!< TIM1 Timer reset /
		1396	#define RCC_APB2RSTR_SPI1RST_Pos (12U)
		1397	#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /!< 0x00001000 /
		1398	#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /!< SPI 1 reset /
		1399	#define RCC_APB2RSTR_USART1RST_Pos (14U)
		1400	#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /!< 0x00004000 /
		1401	#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /!< USART1 reset /
		1402
		1403	#define RCC_APB2RSTR_TIM15RST_Pos (16U)
		1404	#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /!< 0x00010000 /
		1405	#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /!< TIM15 Timer reset /
		1406	#define RCC_APB2RSTR_TIM16RST_Pos (17U)
		1407	#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /!< 0x00020000 /
		1408	#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /!< TIM16 Timer reset /
		1409	#define RCC_APB2RSTR_TIM17RST_Pos (18U)
		1410	#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /!< 0x00040000 /
		1411	#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /!< TIM17 Timer reset /
		1412
		1413	#define RCC_APB2RSTR_IOPERST_Pos (6U)
		1414	#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /!< 0x00000040 /
		1415	#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /!< I/O port E reset /
		1416
		1417
		1418	#define RCC_APB2RSTR_IOPFRST_Pos (7U)
		1419	#define RCC_APB2RSTR_IOPFRST_Msk (0x1UL << RCC_APB2RSTR_IOPFRST_Pos) /!< 0x00000080 /
		1420	#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /!< I/O port F reset /
		1421	#define RCC_APB2RSTR_IOPGRST_Pos (8U)
		1422	#define RCC_APB2RSTR_IOPGRST_Msk (0x1UL << RCC_APB2RSTR_IOPGRST_Pos) /!< 0x00000100 /
		1423	#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /!< I/O port G reset /
		1424
		1425
		1426	/*************** Bit definition for RCC_APB1RSTR register ***************/
		1427	#define RCC_APB1RSTR_TIM2RST_Pos (0U)
		1428	#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /!< 0x00000001 /
		1429	#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /!< Timer 2 reset /
		1430	#define RCC_APB1RSTR_TIM3RST_Pos (1U)
		1431	#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /!< 0x00000002 /
		1432	#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /!< Timer 3 reset /
		1433	#define RCC_APB1RSTR_WWDGRST_Pos (11U)
		1434	#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /!< 0x00000800 /
		1435	#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /!< Window Watchdog reset /
		1436	#define RCC_APB1RSTR_USART2RST_Pos (17U)
		1437	#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /!< 0x00020000 /
		1438	#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /!< USART 2 reset /
		1439	#define RCC_APB1RSTR_I2C1RST_Pos (21U)
		1440	#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /!< 0x00200000 /
		1441	#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /!< I2C 1 reset /
		1442
		1443
		1444	#define RCC_APB1RSTR_BKPRST_Pos (27U)
		1445	#define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /!< 0x08000000 /
		1446	#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /!< Backup interface reset /
		1447	#define RCC_APB1RSTR_PWRRST_Pos (28U)
		1448	#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /!< 0x10000000 /
		1449	#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /!< Power interface reset /
		1450
		1451	#define RCC_APB1RSTR_TIM4RST_Pos (2U)
		1452	#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /!< 0x00000004 /
		1453	#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /!< Timer 4 reset /
		1454	#define RCC_APB1RSTR_SPI2RST_Pos (14U)
		1455	#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /!< 0x00004000 /
		1456	#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /!< SPI 2 reset /
		1457	#define RCC_APB1RSTR_USART3RST_Pos (18U)
		1458	#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /!< 0x00040000 /
		1459	#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /!< USART 3 reset /
		1460	#define RCC_APB1RSTR_I2C2RST_Pos (22U)
		1461	#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /!< 0x00400000 /
		1462	#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /!< I2C 2 reset /
		1463
		1464
		1465
		1466	#define RCC_APB1RSTR_TIM6RST_Pos (4U)
		1467	#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /!< 0x00000010 /
		1468	#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /!< Timer 6 reset /
		1469	#define RCC_APB1RSTR_TIM7RST_Pos (5U)
		1470	#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /!< 0x00000020 /
		1471	#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /!< Timer 7 reset /
		1472	#define RCC_APB1RSTR_CECRST_Pos (30U)
		1473	#define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos) /!< 0x40000000 /
		1474	#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /!< CEC interface reset /
		1475
		1476	#define RCC_APB1RSTR_TIM5RST_Pos (3U)
		1477	#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /!< 0x00000008 /
		1478	#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /!< Timer 5 reset /
		1479	#define RCC_APB1RSTR_TIM12RST_Pos (6U)
		1480	#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /!< 0x00000040 /
		1481	#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk /!< TIM12 Timer reset /
		1482	#define RCC_APB1RSTR_TIM13RST_Pos (7U)
		1483	#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /!< 0x00000080 /
		1484	#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk /!< TIM13 Timer reset /
		1485	#define RCC_APB1RSTR_TIM14RST_Pos (8U)
		1486	#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /!< 0x00000100 /
		1487	#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /!< TIM14 Timer reset /
		1488	#define RCC_APB1RSTR_SPI3RST_Pos (15U)
		1489	#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /!< 0x00008000 /
		1490	#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /!< SPI 3 reset /
		1491	#define RCC_APB1RSTR_UART4RST_Pos (19U)
		1492	#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /!< 0x00080000 /
		1493	#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /!< UART 4 reset /
		1494	#define RCC_APB1RSTR_UART5RST_Pos (20U)
		1495	#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /!< 0x00100000 /
		1496	#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /!< UART 5 reset /
		1497
		1498
		1499	#define RCC_APB1RSTR_DACRST_Pos (29U)
		1500	#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /!< 0x20000000 /
		1501	#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /!< DAC interface reset /
		1502
		1503	/**************** Bit definition for RCC_AHBENR register ****************/
		1504	#define RCC_AHBENR_DMA1EN_Pos (0U)
		1505	#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /!< 0x00000001 /
		1506	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /!< DMA1 clock enable /
		1507	#define RCC_AHBENR_SRAMEN_Pos (2U)
		1508	#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /!< 0x00000004 /
		1509	#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /!< SRAM interface clock enable /
		1510	#define RCC_AHBENR_FLITFEN_Pos (4U)
		1511	#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /!< 0x00000010 /
		1512	#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /!< FLITF clock enable /
		1513	#define RCC_AHBENR_CRCEN_Pos (6U)
		1514	#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /!< 0x00000040 /
		1515	#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /!< CRC clock enable /
		1516
		1517	#define RCC_AHBENR_DMA2EN_Pos (1U)
		1518	#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /!< 0x00000002 /
		1519	#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /!< DMA2 clock enable /
		1520
		1521	#define RCC_AHBENR_FSMCEN_Pos (8U)
		1522	#define RCC_AHBENR_FSMCEN_Msk (0x1UL << RCC_AHBENR_FSMCEN_Pos) /!< 0x00000100 /
		1523	#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /!< FSMC clock enable /
		1524
		1525
		1526	/**************** Bit definition for RCC_APB2ENR register ***************/
		1527	#define RCC_APB2ENR_AFIOEN_Pos (0U)
		1528	#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /!< 0x00000001 /
		1529	#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /!< Alternate Function I/O clock enable /
		1530	#define RCC_APB2ENR_IOPAEN_Pos (2U)
		1531	#define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /!< 0x00000004 /
		1532	#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /!< I/O port A clock enable /
		1533	#define RCC_APB2ENR_IOPBEN_Pos (3U)
		1534	#define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /!< 0x00000008 /
		1535	#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /!< I/O port B clock enable /
		1536	#define RCC_APB2ENR_IOPCEN_Pos (4U)
		1537	#define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /!< 0x00000010 /
		1538	#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /!< I/O port C clock enable /
		1539	#define RCC_APB2ENR_IOPDEN_Pos (5U)
		1540	#define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /!< 0x00000020 /
		1541	#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /!< I/O port D clock enable /
		1542	#define RCC_APB2ENR_ADC1EN_Pos (9U)
		1543	#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /!< 0x00000200 /
		1544	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /!< ADC 1 interface clock enable /
		1545
		1546
		1547	#define RCC_APB2ENR_TIM1EN_Pos (11U)
		1548	#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /!< 0x00000800 /
		1549	#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /!< TIM1 Timer clock enable /
		1550	#define RCC_APB2ENR_SPI1EN_Pos (12U)
		1551	#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /!< 0x00001000 /
		1552	#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /!< SPI 1 clock enable /
		1553	#define RCC_APB2ENR_USART1EN_Pos (14U)
		1554	#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /!< 0x00004000 /
		1555	#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /!< USART1 clock enable /
		1556
		1557	#define RCC_APB2ENR_TIM15EN_Pos (16U)
		1558	#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /!< 0x00010000 /
		1559	#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /!< TIM15 Timer clock enable /
		1560	#define RCC_APB2ENR_TIM16EN_Pos (17U)
		1561	#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /!< 0x00020000 /
		1562	#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /!< TIM16 Timer clock enable /
		1563	#define RCC_APB2ENR_TIM17EN_Pos (18U)
		1564	#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /!< 0x00040000 /
		1565	#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /!< TIM17 Timer clock enable /
		1566
		1567	#define RCC_APB2ENR_IOPEEN_Pos (6U)
		1568	#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /!< 0x00000040 /
		1569	#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /!< I/O port E clock enable /
		1570
		1571
		1572	#define RCC_APB2ENR_IOPFEN_Pos (7U)
		1573	#define RCC_APB2ENR_IOPFEN_Msk (0x1UL << RCC_APB2ENR_IOPFEN_Pos) /!< 0x00000080 /
		1574	#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /!< I/O port F clock enable /
		1575	#define RCC_APB2ENR_IOPGEN_Pos (8U)
		1576	#define RCC_APB2ENR_IOPGEN_Msk (0x1UL << RCC_APB2ENR_IOPGEN_Pos) /!< 0x00000100 /
		1577	#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /!< I/O port G clock enable /
		1578
		1579
		1580	/*************** Bit definition for RCC_APB1ENR register ****************/
		1581	#define RCC_APB1ENR_TIM2EN_Pos (0U)
		1582	#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /!< 0x00000001 /
		1583	#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /!< Timer 2 clock enabled/
		1584	#define RCC_APB1ENR_TIM3EN_Pos (1U)
		1585	#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /!< 0x00000002 /
		1586	#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /!< Timer 3 clock enable /
		1587	#define RCC_APB1ENR_WWDGEN_Pos (11U)
		1588	#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /!< 0x00000800 /
		1589	#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /!< Window Watchdog clock enable /
		1590	#define RCC_APB1ENR_USART2EN_Pos (17U)
		1591	#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /!< 0x00020000 /
		1592	#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /!< USART 2 clock enable /
		1593	#define RCC_APB1ENR_I2C1EN_Pos (21U)
		1594	#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /!< 0x00200000 /
		1595	#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /!< I2C 1 clock enable /
		1596
		1597
		1598	#define RCC_APB1ENR_BKPEN_Pos (27U)
		1599	#define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /!< 0x08000000 /
		1600	#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /!< Backup interface clock enable /
		1601	#define RCC_APB1ENR_PWREN_Pos (28U)
		1602	#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /!< 0x10000000 /
		1603	#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /!< Power interface clock enable /
		1604
		1605	#define RCC_APB1ENR_TIM4EN_Pos (2U)
		1606	#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /!< 0x00000004 /
		1607	#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /!< Timer 4 clock enable /
		1608	#define RCC_APB1ENR_SPI2EN_Pos (14U)
		1609	#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /!< 0x00004000 /
		1610	#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /!< SPI 2 clock enable /
		1611	#define RCC_APB1ENR_USART3EN_Pos (18U)
		1612	#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /!< 0x00040000 /
		1613	#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /!< USART 3 clock enable /
		1614	#define RCC_APB1ENR_I2C2EN_Pos (22U)
		1615	#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /!< 0x00400000 /
		1616	#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /!< I2C 2 clock enable /
		1617
		1618
		1619
		1620	#define RCC_APB1ENR_TIM6EN_Pos (4U)
		1621	#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /!< 0x00000010 /
		1622	#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /!< Timer 6 clock enable /
		1623	#define RCC_APB1ENR_TIM7EN_Pos (5U)
		1624	#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /!< 0x00000020 /
		1625	#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /!< Timer 7 clock enable /
		1626	#define RCC_APB1ENR_CECEN_Pos (30U)
		1627	#define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos) /!< 0x40000000 /
		1628	#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /!< CEC interface clock enable /
		1629
		1630	#define RCC_APB1ENR_TIM5EN_Pos (3U)
		1631	#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /!< 0x00000008 /
		1632	#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /!< Timer 5 clock enable /
		1633	#define RCC_APB1ENR_TIM12EN_Pos (6U)
		1634	#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /!< 0x00000040 /
		1635	#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk /!< TIM12 Timer clock enable /
		1636	#define RCC_APB1ENR_TIM13EN_Pos (7U)
		1637	#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /!< 0x00000080 /
		1638	#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk /!< TIM13 Timer clock enable /
		1639	#define RCC_APB1ENR_TIM14EN_Pos (8U)
		1640	#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /!< 0x00000100 /
		1641	#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /!< TIM14 Timer clock enable /
		1642	#define RCC_APB1ENR_SPI3EN_Pos (15U)
		1643	#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /!< 0x00008000 /
		1644	#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /!< SPI 3 clock enable /
		1645	#define RCC_APB1ENR_UART4EN_Pos (19U)
		1646	#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /!< 0x00080000 /
		1647	#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /!< UART 4 clock enable /
		1648	#define RCC_APB1ENR_UART5EN_Pos (20U)
		1649	#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /!< 0x00100000 /
		1650	#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /!< UART 5 clock enable /
		1651
		1652
		1653	#define RCC_APB1ENR_DACEN_Pos (29U)
		1654	#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /!< 0x20000000 /
		1655	#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /!< DAC interface clock enable /
		1656
		1657	/***************** Bit definition for RCC_BDCR register *****************/
		1658	#define RCC_BDCR_LSEON_Pos (0U)
		1659	#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /!< 0x00000001 /
		1660	#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /!< External Low Speed oscillator enable /
		1661	#define RCC_BDCR_LSERDY_Pos (1U)
		1662	#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /!< 0x00000002 /
		1663	#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /!< External Low Speed oscillator Ready /
		1664	#define RCC_BDCR_LSEBYP_Pos (2U)
		1665	#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /!< 0x00000004 /
		1666	#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /!< External Low Speed oscillator Bypass /
		1667
		1668	#define RCC_BDCR_RTCSEL_Pos (8U)
		1669	#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /!< 0x00000300 /
		1670	#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /!< RTCSEL[1:0] bits (RTC clock source selection) /
		1671	#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /!< 0x00000100 /
		1672	#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /!< 0x00000200 /
		1673
		1674	/!< RTC congiguration /
		1675	#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /!< No clock /
		1676	#define RCC_BDCR_RTCSEL_LSE 0x00000100U /!< LSE oscillator clock used as RTC clock /
		1677	#define RCC_BDCR_RTCSEL_LSI 0x00000200U /!< LSI oscillator clock used as RTC clock /
		1678	#define RCC_BDCR_RTCSEL_HSE 0x00000300U /!< HSE oscillator clock divided by 128 used as RTC clock /
		1679
		1680	#define RCC_BDCR_RTCEN_Pos (15U)
		1681	#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /!< 0x00008000 /
		1682	#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /!< RTC clock enable /
		1683	#define RCC_BDCR_BDRST_Pos (16U)
		1684	#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /!< 0x00010000 /
		1685	#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /!< Backup domain software reset /
		1686
		1687	/***************** Bit definition for RCC_CSR register ******************/
		1688	#define RCC_CSR_LSION_Pos (0U)
		1689	#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /!< 0x00000001 /
		1690	#define RCC_CSR_LSION RCC_CSR_LSION_Msk /!< Internal Low Speed oscillator enable /
		1691	#define RCC_CSR_LSIRDY_Pos (1U)
		1692	#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /!< 0x00000002 /
		1693	#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /!< Internal Low Speed oscillator Ready /
		1694	#define RCC_CSR_RMVF_Pos (24U)
		1695	#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /!< 0x01000000 /
		1696	#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /!< Remove reset flag /
		1697	#define RCC_CSR_PINRSTF_Pos (26U)
		1698	#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /!< 0x04000000 /
		1699	#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /!< PIN reset flag /
		1700	#define RCC_CSR_PORRSTF_Pos (27U)
		1701	#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /!< 0x08000000 /
		1702	#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /!< POR/PDR reset flag /
		1703	#define RCC_CSR_SFTRSTF_Pos (28U)
		1704	#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /!< 0x10000000 /
		1705	#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /!< Software Reset flag /
		1706	#define RCC_CSR_IWDGRSTF_Pos (29U)
		1707	#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /!< 0x20000000 /
		1708	#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /!< Independent Watchdog reset flag /
		1709	#define RCC_CSR_WWDGRSTF_Pos (30U)
		1710	#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /!< 0x40000000 /
		1711	#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /!< Window watchdog reset flag /
		1712	#define RCC_CSR_LPWRRSTF_Pos (31U)
		1713	#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /!< 0x80000000 /
		1714	#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /!< Low-Power reset flag /
		1715
		1716
		1717	/***************** Bit definition for RCC_CFGR2 register ****************/
		1718	/!< PREDIV1 configuration /
		1719	#define RCC_CFGR2_PREDIV1_Pos (0U)
		1720	#define RCC_CFGR2_PREDIV1_Msk (0xFUL << RCC_CFGR2_PREDIV1_Pos) /!< 0x0000000F /
		1721	#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /!< PREDIV1[3:0] bits /
		1722	#define RCC_CFGR2_PREDIV1_0 (0x1UL << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000001 /
		1723	#define RCC_CFGR2_PREDIV1_1 (0x2UL << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000002 /
		1724	#define RCC_CFGR2_PREDIV1_2 (0x4UL << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000004 /
		1725	#define RCC_CFGR2_PREDIV1_3 (0x8UL << RCC_CFGR2_PREDIV1_Pos) /!< 0x00000008 /
		1726
		1727	#define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /!< PREDIV1 input clock not divided /
		1728	#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
		1729	#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV2_Pos) /!< 0x00000001 /
		1730	#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /!< PREDIV1 input clock divided by 2 /
		1731	#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U)
		1732	#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV3_Pos) /!< 0x00000002 /
		1733	#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /!< PREDIV1 input clock divided by 3 /
		1734	#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U)
		1735	#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV4_Pos) /!< 0x00000003 /
		1736	#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /!< PREDIV1 input clock divided by 4 /
		1737	#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U)
		1738	#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV5_Pos) /!< 0x00000004 /
		1739	#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /!< PREDIV1 input clock divided by 5 /
		1740	#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U)
		1741	#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV6_Pos) /!< 0x00000005 /
		1742	#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /!< PREDIV1 input clock divided by 6 /
		1743	#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U)
		1744	#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV7_Pos) /!< 0x00000006 /
		1745	#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /!< PREDIV1 input clock divided by 7 /
		1746	#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U)
		1747	#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV8_Pos) /!< 0x00000007 /
		1748	#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /!< PREDIV1 input clock divided by 8 /
		1749	#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U)
		1750	#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV9_Pos) /!< 0x00000008 /
		1751	#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /!< PREDIV1 input clock divided by 9 /
		1752	#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U)
		1753	#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV1_DIV10_Pos) /!< 0x00000009 /
		1754	#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /!< PREDIV1 input clock divided by 10 /
		1755	#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U)
		1756	#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV11_Pos) /!< 0x0000000A /
		1757	#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /!< PREDIV1 input clock divided by 11 /
		1758	#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U)
		1759	#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV1_DIV12_Pos) /!< 0x0000000B /
		1760	#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /!< PREDIV1 input clock divided by 12 /
		1761	#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U)
		1762	#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV13_Pos) /!< 0x0000000C /
		1763	#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /!< PREDIV1 input clock divided by 13 /
		1764	#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U)
		1765	#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV1_DIV14_Pos) /!< 0x0000000D /
		1766	#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /!< PREDIV1 input clock divided by 14 /
		1767	#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U)
		1768	#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV15_Pos) /!< 0x0000000E /
		1769	#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /!< PREDIV1 input clock divided by 15 /
		1770	#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U)
		1771	#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV1_DIV16_Pos) /!< 0x0000000F /
		1772	#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /!< PREDIV1 input clock divided by 16 /
		1773
		1774	/******************************************************************************/
		1775	/* */
		1776	/* General Purpose and Alternate Function I/O */
		1777	/* */
		1778	/******************************************************************************/
		1779
		1780	/***************** Bit definition for GPIO_CRL register *****************/
		1781	#define GPIO_CRL_MODE_Pos (0U)
		1782	#define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /!< 0x33333333 /
		1783	#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /!< Port x mode bits /
		1784
		1785	#define GPIO_CRL_MODE0_Pos (0U)
		1786	#define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /!< 0x00000003 /
		1787	#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
		1788	#define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /!< 0x00000001 /
		1789	#define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /!< 0x00000002 /
		1790
		1791	#define GPIO_CRL_MODE1_Pos (4U)
		1792	#define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /!< 0x00000030 /
		1793	#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
		1794	#define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /!< 0x00000010 /
		1795	#define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /!< 0x00000020 /
		1796
		1797	#define GPIO_CRL_MODE2_Pos (8U)
		1798	#define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /!< 0x00000300 /
		1799	#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
		1800	#define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /!< 0x00000100 /
		1801	#define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /!< 0x00000200 /
		1802
		1803	#define GPIO_CRL_MODE3_Pos (12U)
		1804	#define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /!< 0x00003000 /
		1805	#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
		1806	#define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /!< 0x00001000 /
		1807	#define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /!< 0x00002000 /
		1808
		1809	#define GPIO_CRL_MODE4_Pos (16U)
		1810	#define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /!< 0x00030000 /
		1811	#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
		1812	#define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /!< 0x00010000 /
		1813	#define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /!< 0x00020000 /
		1814
		1815	#define GPIO_CRL_MODE5_Pos (20U)
		1816	#define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /!< 0x00300000 /
		1817	#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
		1818	#define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /!< 0x00100000 /
		1819	#define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /!< 0x00200000 /
		1820
		1821	#define GPIO_CRL_MODE6_Pos (24U)
		1822	#define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /!< 0x03000000 /
		1823	#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
		1824	#define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /!< 0x01000000 /
		1825	#define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /!< 0x02000000 /
		1826
		1827	#define GPIO_CRL_MODE7_Pos (28U)
		1828	#define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /!< 0x30000000 /
		1829	#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
		1830	#define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /!< 0x10000000 /
		1831	#define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /!< 0x20000000 /
		1832
		1833	#define GPIO_CRL_CNF_Pos (2U)
		1834	#define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /!< 0xCCCCCCCC /
		1835	#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /!< Port x configuration bits /
		1836
		1837	#define GPIO_CRL_CNF0_Pos (2U)
		1838	#define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /!< 0x0000000C /
		1839	#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
		1840	#define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /!< 0x00000004 /
		1841	#define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /!< 0x00000008 /
		1842
		1843	#define GPIO_CRL_CNF1_Pos (6U)
		1844	#define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /!< 0x000000C0 /
		1845	#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
		1846	#define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /!< 0x00000040 /
		1847	#define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /!< 0x00000080 /
		1848
		1849	#define GPIO_CRL_CNF2_Pos (10U)
		1850	#define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /!< 0x00000C00 /
		1851	#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
		1852	#define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /!< 0x00000400 /
		1853	#define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /!< 0x00000800 /
		1854
		1855	#define GPIO_CRL_CNF3_Pos (14U)
		1856	#define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /!< 0x0000C000 /
		1857	#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
		1858	#define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /!< 0x00004000 /
		1859	#define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /!< 0x00008000 /
		1860
		1861	#define GPIO_CRL_CNF4_Pos (18U)
		1862	#define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /!< 0x000C0000 /
		1863	#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
		1864	#define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /!< 0x00040000 /
		1865	#define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /!< 0x00080000 /
		1866
		1867	#define GPIO_CRL_CNF5_Pos (22U)
		1868	#define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /!< 0x00C00000 /
		1869	#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
		1870	#define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /!< 0x00400000 /
		1871	#define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /!< 0x00800000 /
		1872
		1873	#define GPIO_CRL_CNF6_Pos (26U)
		1874	#define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /!< 0x0C000000 /
		1875	#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
		1876	#define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /!< 0x04000000 /
		1877	#define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /!< 0x08000000 /
		1878
		1879	#define GPIO_CRL_CNF7_Pos (30U)
		1880	#define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /!< 0xC0000000 /
		1881	#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
		1882	#define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /!< 0x40000000 /
		1883	#define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /!< 0x80000000 /
		1884
		1885	/***************** Bit definition for GPIO_CRH register *****************/
		1886	#define GPIO_CRH_MODE_Pos (0U)
		1887	#define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /!< 0x33333333 /
		1888	#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /!< Port x mode bits /
		1889
		1890	#define GPIO_CRH_MODE8_Pos (0U)
		1891	#define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /!< 0x00000003 /
		1892	#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
		1893	#define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /!< 0x00000001 /
		1894	#define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /!< 0x00000002 /
		1895
		1896	#define GPIO_CRH_MODE9_Pos (4U)
		1897	#define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /!< 0x00000030 /
		1898	#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
		1899	#define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /!< 0x00000010 /
		1900	#define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /!< 0x00000020 /
		1901
		1902	#define GPIO_CRH_MODE10_Pos (8U)
		1903	#define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /!< 0x00000300 /
		1904	#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
		1905	#define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /!< 0x00000100 /
		1906	#define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /!< 0x00000200 /
		1907
		1908	#define GPIO_CRH_MODE11_Pos (12U)
		1909	#define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /!< 0x00003000 /
		1910	#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
		1911	#define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /!< 0x00001000 /
		1912	#define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /!< 0x00002000 /
		1913
		1914	#define GPIO_CRH_MODE12_Pos (16U)
		1915	#define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /!< 0x00030000 /
		1916	#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
		1917	#define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /!< 0x00010000 /
		1918	#define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /!< 0x00020000 /
		1919
		1920	#define GPIO_CRH_MODE13_Pos (20U)
		1921	#define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /!< 0x00300000 /
		1922	#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
		1923	#define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /!< 0x00100000 /
		1924	#define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /!< 0x00200000 /
		1925
		1926	#define GPIO_CRH_MODE14_Pos (24U)
		1927	#define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /!< 0x03000000 /
		1928	#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
		1929	#define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /!< 0x01000000 /
		1930	#define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /!< 0x02000000 /
		1931
		1932	#define GPIO_CRH_MODE15_Pos (28U)
		1933	#define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /!< 0x30000000 /
		1934	#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
		1935	#define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /!< 0x10000000 /
		1936	#define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /!< 0x20000000 /
		1937
		1938	#define GPIO_CRH_CNF_Pos (2U)
		1939	#define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /!< 0xCCCCCCCC /
		1940	#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /!< Port x configuration bits /
		1941
		1942	#define GPIO_CRH_CNF8_Pos (2U)
		1943	#define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /!< 0x0000000C /
		1944	#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
		1945	#define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /!< 0x00000004 /
		1946	#define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /!< 0x00000008 /
		1947
		1948	#define GPIO_CRH_CNF9_Pos (6U)
		1949	#define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /!< 0x000000C0 /
		1950	#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
		1951	#define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /!< 0x00000040 /
		1952	#define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /!< 0x00000080 /
		1953
		1954	#define GPIO_CRH_CNF10_Pos (10U)
		1955	#define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /!< 0x00000C00 /
		1956	#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
		1957	#define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /!< 0x00000400 /
		1958	#define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /!< 0x00000800 /
		1959
		1960	#define GPIO_CRH_CNF11_Pos (14U)
		1961	#define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /!< 0x0000C000 /
		1962	#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
		1963	#define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /!< 0x00004000 /
		1964	#define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /!< 0x00008000 /
		1965
		1966	#define GPIO_CRH_CNF12_Pos (18U)
		1967	#define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /!< 0x000C0000 /
		1968	#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
		1969	#define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /!< 0x00040000 /
		1970	#define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /!< 0x00080000 /
		1971
		1972	#define GPIO_CRH_CNF13_Pos (22U)
		1973	#define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /!< 0x00C00000 /
		1974	#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
		1975	#define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /!< 0x00400000 /
		1976	#define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /!< 0x00800000 /
		1977
		1978	#define GPIO_CRH_CNF14_Pos (26U)
		1979	#define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /!< 0x0C000000 /
		1980	#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
		1981	#define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /!< 0x04000000 /
		1982	#define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /!< 0x08000000 /
		1983
		1984	#define GPIO_CRH_CNF15_Pos (30U)
		1985	#define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /!< 0xC0000000 /
		1986	#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
		1987	#define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /!< 0x40000000 /
		1988	#define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /!< 0x80000000 /
		1989
		1990	/!<*************** Bit definition for GPIO_IDR register *****************/
		1991	#define GPIO_IDR_IDR0_Pos (0U)
		1992	#define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /!< 0x00000001 /
		1993	#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /!< Port input data, bit 0 /
		1994	#define GPIO_IDR_IDR1_Pos (1U)
		1995	#define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /!< 0x00000002 /
		1996	#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /!< Port input data, bit 1 /
		1997	#define GPIO_IDR_IDR2_Pos (2U)
		1998	#define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /!< 0x00000004 /
		1999	#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /!< Port input data, bit 2 /
		2000	#define GPIO_IDR_IDR3_Pos (3U)
		2001	#define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /!< 0x00000008 /
		2002	#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /!< Port input data, bit 3 /
		2003	#define GPIO_IDR_IDR4_Pos (4U)
		2004	#define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /!< 0x00000010 /
		2005	#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /!< Port input data, bit 4 /
		2006	#define GPIO_IDR_IDR5_Pos (5U)
		2007	#define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /!< 0x00000020 /
		2008	#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /!< Port input data, bit 5 /
		2009	#define GPIO_IDR_IDR6_Pos (6U)
		2010	#define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /!< 0x00000040 /
		2011	#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /!< Port input data, bit 6 /
		2012	#define GPIO_IDR_IDR7_Pos (7U)
		2013	#define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /!< 0x00000080 /
		2014	#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /!< Port input data, bit 7 /
		2015	#define GPIO_IDR_IDR8_Pos (8U)
		2016	#define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /!< 0x00000100 /
		2017	#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /!< Port input data, bit 8 /
		2018	#define GPIO_IDR_IDR9_Pos (9U)
		2019	#define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /!< 0x00000200 /
		2020	#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /!< Port input data, bit 9 /
		2021	#define GPIO_IDR_IDR10_Pos (10U)
		2022	#define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /!< 0x00000400 /
		2023	#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /!< Port input data, bit 10 /
		2024	#define GPIO_IDR_IDR11_Pos (11U)
		2025	#define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /!< 0x00000800 /
		2026	#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /!< Port input data, bit 11 /
		2027	#define GPIO_IDR_IDR12_Pos (12U)
		2028	#define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /!< 0x00001000 /
		2029	#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /!< Port input data, bit 12 /
		2030	#define GPIO_IDR_IDR13_Pos (13U)
		2031	#define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /!< 0x00002000 /
		2032	#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /!< Port input data, bit 13 /
		2033	#define GPIO_IDR_IDR14_Pos (14U)
		2034	#define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /!< 0x00004000 /
		2035	#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /!< Port input data, bit 14 /
		2036	#define GPIO_IDR_IDR15_Pos (15U)
		2037	#define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /!< 0x00008000 /
		2038	#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /!< Port input data, bit 15 /
		2039
		2040	/***************** Bit definition for GPIO_ODR register *****************/
		2041	#define GPIO_ODR_ODR0_Pos (0U)
		2042	#define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /!< 0x00000001 /
		2043	#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /!< Port output data, bit 0 /
		2044	#define GPIO_ODR_ODR1_Pos (1U)
		2045	#define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /!< 0x00000002 /
		2046	#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /!< Port output data, bit 1 /
		2047	#define GPIO_ODR_ODR2_Pos (2U)
		2048	#define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /!< 0x00000004 /
		2049	#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /!< Port output data, bit 2 /
		2050	#define GPIO_ODR_ODR3_Pos (3U)
		2051	#define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /!< 0x00000008 /
		2052	#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /!< Port output data, bit 3 /
		2053	#define GPIO_ODR_ODR4_Pos (4U)
		2054	#define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /!< 0x00000010 /
		2055	#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /!< Port output data, bit 4 /
		2056	#define GPIO_ODR_ODR5_Pos (5U)
		2057	#define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /!< 0x00000020 /
		2058	#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /!< Port output data, bit 5 /
		2059	#define GPIO_ODR_ODR6_Pos (6U)
		2060	#define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /!< 0x00000040 /
		2061	#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /!< Port output data, bit 6 /
		2062	#define GPIO_ODR_ODR7_Pos (7U)
		2063	#define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /!< 0x00000080 /
		2064	#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /!< Port output data, bit 7 /
		2065	#define GPIO_ODR_ODR8_Pos (8U)
		2066	#define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /!< 0x00000100 /
		2067	#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /!< Port output data, bit 8 /
		2068	#define GPIO_ODR_ODR9_Pos (9U)
		2069	#define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /!< 0x00000200 /
		2070	#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /!< Port output data, bit 9 /
		2071	#define GPIO_ODR_ODR10_Pos (10U)
		2072	#define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /!< 0x00000400 /
		2073	#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /!< Port output data, bit 10 /
		2074	#define GPIO_ODR_ODR11_Pos (11U)
		2075	#define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /!< 0x00000800 /
		2076	#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /!< Port output data, bit 11 /
		2077	#define GPIO_ODR_ODR12_Pos (12U)
		2078	#define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /!< 0x00001000 /
		2079	#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /!< Port output data, bit 12 /
		2080	#define GPIO_ODR_ODR13_Pos (13U)
		2081	#define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /!< 0x00002000 /
		2082	#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /!< Port output data, bit 13 /
		2083	#define GPIO_ODR_ODR14_Pos (14U)
		2084	#define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /!< 0x00004000 /
		2085	#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /!< Port output data, bit 14 /
		2086	#define GPIO_ODR_ODR15_Pos (15U)
		2087	#define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /!< 0x00008000 /
		2088	#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /!< Port output data, bit 15 /
		2089
		2090	/**************** Bit definition for GPIO_BSRR register *****************/
		2091	#define GPIO_BSRR_BS0_Pos (0U)
		2092	#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /!< 0x00000001 /
		2093	#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /!< Port x Set bit 0 /
		2094	#define GPIO_BSRR_BS1_Pos (1U)
		2095	#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /!< 0x00000002 /
		2096	#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /!< Port x Set bit 1 /
		2097	#define GPIO_BSRR_BS2_Pos (2U)
		2098	#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /!< 0x00000004 /
		2099	#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /!< Port x Set bit 2 /
		2100	#define GPIO_BSRR_BS3_Pos (3U)
		2101	#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /!< 0x00000008 /
		2102	#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /!< Port x Set bit 3 /
		2103	#define GPIO_BSRR_BS4_Pos (4U)
		2104	#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /!< 0x00000010 /
		2105	#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /!< Port x Set bit 4 /
		2106	#define GPIO_BSRR_BS5_Pos (5U)
		2107	#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /!< 0x00000020 /
		2108	#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /!< Port x Set bit 5 /
		2109	#define GPIO_BSRR_BS6_Pos (6U)
		2110	#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /!< 0x00000040 /
		2111	#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /!< Port x Set bit 6 /
		2112	#define GPIO_BSRR_BS7_Pos (7U)
		2113	#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /!< 0x00000080 /
		2114	#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /!< Port x Set bit 7 /
		2115	#define GPIO_BSRR_BS8_Pos (8U)
		2116	#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /!< 0x00000100 /
		2117	#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /!< Port x Set bit 8 /
		2118	#define GPIO_BSRR_BS9_Pos (9U)
		2119	#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /!< 0x00000200 /
		2120	#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /!< Port x Set bit 9 /
		2121	#define GPIO_BSRR_BS10_Pos (10U)
		2122	#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /!< 0x00000400 /
		2123	#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /!< Port x Set bit 10 /
		2124	#define GPIO_BSRR_BS11_Pos (11U)
		2125	#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /!< 0x00000800 /
		2126	#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /!< Port x Set bit 11 /
		2127	#define GPIO_BSRR_BS12_Pos (12U)
		2128	#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /!< 0x00001000 /
		2129	#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /!< Port x Set bit 12 /
		2130	#define GPIO_BSRR_BS13_Pos (13U)
		2131	#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /!< 0x00002000 /
		2132	#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /!< Port x Set bit 13 /
		2133	#define GPIO_BSRR_BS14_Pos (14U)
		2134	#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /!< 0x00004000 /
		2135	#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /!< Port x Set bit 14 /
		2136	#define GPIO_BSRR_BS15_Pos (15U)
		2137	#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /!< 0x00008000 /
		2138	#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /!< Port x Set bit 15 /
		2139
		2140	#define GPIO_BSRR_BR0_Pos (16U)
		2141	#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /!< 0x00010000 /
		2142	#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /!< Port x Reset bit 0 /
		2143	#define GPIO_BSRR_BR1_Pos (17U)
		2144	#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /!< 0x00020000 /
		2145	#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /!< Port x Reset bit 1 /
		2146	#define GPIO_BSRR_BR2_Pos (18U)
		2147	#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /!< 0x00040000 /
		2148	#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /!< Port x Reset bit 2 /
		2149	#define GPIO_BSRR_BR3_Pos (19U)
		2150	#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /!< 0x00080000 /
		2151	#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /!< Port x Reset bit 3 /
		2152	#define GPIO_BSRR_BR4_Pos (20U)
		2153	#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /!< 0x00100000 /
		2154	#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /!< Port x Reset bit 4 /
		2155	#define GPIO_BSRR_BR5_Pos (21U)
		2156	#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /!< 0x00200000 /
		2157	#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /!< Port x Reset bit 5 /
		2158	#define GPIO_BSRR_BR6_Pos (22U)
		2159	#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /!< 0x00400000 /
		2160	#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /!< Port x Reset bit 6 /
		2161	#define GPIO_BSRR_BR7_Pos (23U)
		2162	#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /!< 0x00800000 /
		2163	#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /!< Port x Reset bit 7 /
		2164	#define GPIO_BSRR_BR8_Pos (24U)
		2165	#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /!< 0x01000000 /
		2166	#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /!< Port x Reset bit 8 /
		2167	#define GPIO_BSRR_BR9_Pos (25U)
		2168	#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /!< 0x02000000 /
		2169	#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /!< Port x Reset bit 9 /
		2170	#define GPIO_BSRR_BR10_Pos (26U)
		2171	#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /!< 0x04000000 /
		2172	#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /!< Port x Reset bit 10 /
		2173	#define GPIO_BSRR_BR11_Pos (27U)
		2174	#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /!< 0x08000000 /
		2175	#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /!< Port x Reset bit 11 /
		2176	#define GPIO_BSRR_BR12_Pos (28U)
		2177	#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /!< 0x10000000 /
		2178	#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /!< Port x Reset bit 12 /
		2179	#define GPIO_BSRR_BR13_Pos (29U)
		2180	#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /!< 0x20000000 /
		2181	#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /!< Port x Reset bit 13 /
		2182	#define GPIO_BSRR_BR14_Pos (30U)
		2183	#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /!< 0x40000000 /
		2184	#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /!< Port x Reset bit 14 /
		2185	#define GPIO_BSRR_BR15_Pos (31U)
		2186	#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /!< 0x80000000 /
		2187	#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /!< Port x Reset bit 15 /
		2188
		2189	/***************** Bit definition for GPIO_BRR register *****************/
		2190	#define GPIO_BRR_BR0_Pos (0U)
		2191	#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /!< 0x00000001 /
		2192	#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /!< Port x Reset bit 0 /
		2193	#define GPIO_BRR_BR1_Pos (1U)
		2194	#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /!< 0x00000002 /
		2195	#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /!< Port x Reset bit 1 /
		2196	#define GPIO_BRR_BR2_Pos (2U)
		2197	#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /!< 0x00000004 /
		2198	#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /!< Port x Reset bit 2 /
		2199	#define GPIO_BRR_BR3_Pos (3U)
		2200	#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /!< 0x00000008 /
		2201	#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /!< Port x Reset bit 3 /
		2202	#define GPIO_BRR_BR4_Pos (4U)
		2203	#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /!< 0x00000010 /
		2204	#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /!< Port x Reset bit 4 /
		2205	#define GPIO_BRR_BR5_Pos (5U)
		2206	#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /!< 0x00000020 /
		2207	#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /!< Port x Reset bit 5 /
		2208	#define GPIO_BRR_BR6_Pos (6U)
		2209	#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /!< 0x00000040 /
		2210	#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /!< Port x Reset bit 6 /
		2211	#define GPIO_BRR_BR7_Pos (7U)
		2212	#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /!< 0x00000080 /
		2213	#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /!< Port x Reset bit 7 /
		2214	#define GPIO_BRR_BR8_Pos (8U)
		2215	#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /!< 0x00000100 /
		2216	#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /!< Port x Reset bit 8 /
		2217	#define GPIO_BRR_BR9_Pos (9U)
		2218	#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /!< 0x00000200 /
		2219	#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /!< Port x Reset bit 9 /
		2220	#define GPIO_BRR_BR10_Pos (10U)
		2221	#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /!< 0x00000400 /
		2222	#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /!< Port x Reset bit 10 /
		2223	#define GPIO_BRR_BR11_Pos (11U)
		2224	#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /!< 0x00000800 /
		2225	#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /!< Port x Reset bit 11 /
		2226	#define GPIO_BRR_BR12_Pos (12U)
		2227	#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /!< 0x00001000 /
		2228	#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /!< Port x Reset bit 12 /
		2229	#define GPIO_BRR_BR13_Pos (13U)
		2230	#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /!< 0x00002000 /
		2231	#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /!< Port x Reset bit 13 /
		2232	#define GPIO_BRR_BR14_Pos (14U)
		2233	#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /!< 0x00004000 /
		2234	#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /!< Port x Reset bit 14 /
		2235	#define GPIO_BRR_BR15_Pos (15U)
		2236	#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /!< 0x00008000 /
		2237	#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /!< Port x Reset bit 15 /
		2238
		2239	/**************** Bit definition for GPIO_LCKR register *****************/
		2240	#define GPIO_LCKR_LCK0_Pos (0U)
		2241	#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /!< 0x00000001 /
		2242	#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /!< Port x Lock bit 0 /
		2243	#define GPIO_LCKR_LCK1_Pos (1U)
		2244	#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /!< 0x00000002 /
		2245	#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /!< Port x Lock bit 1 /
		2246	#define GPIO_LCKR_LCK2_Pos (2U)
		2247	#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /!< 0x00000004 /
		2248	#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /!< Port x Lock bit 2 /
		2249	#define GPIO_LCKR_LCK3_Pos (3U)
		2250	#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /!< 0x00000008 /
		2251	#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /!< Port x Lock bit 3 /
		2252	#define GPIO_LCKR_LCK4_Pos (4U)
		2253	#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /!< 0x00000010 /
		2254	#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /!< Port x Lock bit 4 /
		2255	#define GPIO_LCKR_LCK5_Pos (5U)
		2256	#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /!< 0x00000020 /
		2257	#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /!< Port x Lock bit 5 /
		2258	#define GPIO_LCKR_LCK6_Pos (6U)
		2259	#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /!< 0x00000040 /
		2260	#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /!< Port x Lock bit 6 /
		2261	#define GPIO_LCKR_LCK7_Pos (7U)
		2262	#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /!< 0x00000080 /
		2263	#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /!< Port x Lock bit 7 /
		2264	#define GPIO_LCKR_LCK8_Pos (8U)
		2265	#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /!< 0x00000100 /
		2266	#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /!< Port x Lock bit 8 /
		2267	#define GPIO_LCKR_LCK9_Pos (9U)
		2268	#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /!< 0x00000200 /
		2269	#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /!< Port x Lock bit 9 /
		2270	#define GPIO_LCKR_LCK10_Pos (10U)
		2271	#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /!< 0x00000400 /
		2272	#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /!< Port x Lock bit 10 /
		2273	#define GPIO_LCKR_LCK11_Pos (11U)
		2274	#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /!< 0x00000800 /
		2275	#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /!< Port x Lock bit 11 /
		2276	#define GPIO_LCKR_LCK12_Pos (12U)
		2277	#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /!< 0x00001000 /
		2278	#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /!< Port x Lock bit 12 /
		2279	#define GPIO_LCKR_LCK13_Pos (13U)
		2280	#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /!< 0x00002000 /
		2281	#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /!< Port x Lock bit 13 /
		2282	#define GPIO_LCKR_LCK14_Pos (14U)
		2283	#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /!< 0x00004000 /
		2284	#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /!< Port x Lock bit 14 /
		2285	#define GPIO_LCKR_LCK15_Pos (15U)
		2286	#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /!< 0x00008000 /
		2287	#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /!< Port x Lock bit 15 /
		2288	#define GPIO_LCKR_LCKK_Pos (16U)
		2289	#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /!< 0x00010000 /
		2290	#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /!< Lock key /
		2291
		2292	/----------------------------------------------------------------------------/
		2293
		2294	/**************** Bit definition for AFIO_EVCR register *****************/
		2295	#define AFIO_EVCR_PIN_Pos (0U)
		2296	#define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /!< 0x0000000F /
		2297	#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /!< PIN[3:0] bits (Pin selection) /
		2298	#define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /!< 0x00000001 /
		2299	#define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /!< 0x00000002 /
		2300	#define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /!< 0x00000004 /
		2301	#define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /!< 0x00000008 /
		2302
		2303	/!< PIN configuration /
		2304	#define AFIO_EVCR_PIN_PX0 0x00000000U /!< Pin 0 selected /
		2305	#define AFIO_EVCR_PIN_PX1_Pos (0U)
		2306	#define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /!< 0x00000001 /
		2307	#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /!< Pin 1 selected /
		2308	#define AFIO_EVCR_PIN_PX2_Pos (1U)
		2309	#define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /!< 0x00000002 /
		2310	#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /!< Pin 2 selected /
		2311	#define AFIO_EVCR_PIN_PX3_Pos (0U)
		2312	#define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /!< 0x00000003 /
		2313	#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /!< Pin 3 selected /
		2314	#define AFIO_EVCR_PIN_PX4_Pos (2U)
		2315	#define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /!< 0x00000004 /
		2316	#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /!< Pin 4 selected /
		2317	#define AFIO_EVCR_PIN_PX5_Pos (0U)
		2318	#define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /!< 0x00000005 /
		2319	#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /!< Pin 5 selected /
		2320	#define AFIO_EVCR_PIN_PX6_Pos (1U)
		2321	#define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /!< 0x00000006 /
		2322	#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /!< Pin 6 selected /
		2323	#define AFIO_EVCR_PIN_PX7_Pos (0U)
		2324	#define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /!< 0x00000007 /
		2325	#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /!< Pin 7 selected /
		2326	#define AFIO_EVCR_PIN_PX8_Pos (3U)
		2327	#define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /!< 0x00000008 /
		2328	#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /!< Pin 8 selected /
		2329	#define AFIO_EVCR_PIN_PX9_Pos (0U)
		2330	#define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /!< 0x00000009 /
		2331	#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /!< Pin 9 selected /
		2332	#define AFIO_EVCR_PIN_PX10_Pos (1U)
		2333	#define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /!< 0x0000000A /
		2334	#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /!< Pin 10 selected /
		2335	#define AFIO_EVCR_PIN_PX11_Pos (0U)
		2336	#define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /!< 0x0000000B /
		2337	#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /!< Pin 11 selected /
		2338	#define AFIO_EVCR_PIN_PX12_Pos (2U)
		2339	#define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /!< 0x0000000C /
		2340	#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /!< Pin 12 selected /
		2341	#define AFIO_EVCR_PIN_PX13_Pos (0U)
		2342	#define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /!< 0x0000000D /
		2343	#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /!< Pin 13 selected /
		2344	#define AFIO_EVCR_PIN_PX14_Pos (1U)
		2345	#define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /!< 0x0000000E /
		2346	#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /!< Pin 14 selected /
		2347	#define AFIO_EVCR_PIN_PX15_Pos (0U)
		2348	#define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /!< 0x0000000F /
		2349	#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /!< Pin 15 selected /
		2350
		2351	#define AFIO_EVCR_PORT_Pos (4U)
		2352	#define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /!< 0x00000070 /
		2353	#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /!< PORT[2:0] bits (Port selection) /
		2354	#define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /!< 0x00000010 /
		2355	#define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /!< 0x00000020 /
		2356	#define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /!< 0x00000040 /
		2357
		2358	/!< PORT configuration /
		2359	#define AFIO_EVCR_PORT_PA 0x00000000 /!< Port A selected /
		2360	#define AFIO_EVCR_PORT_PB_Pos (4U)
		2361	#define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /!< 0x00000010 /
		2362	#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /!< Port B selected /
		2363	#define AFIO_EVCR_PORT_PC_Pos (5U)
		2364	#define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /!< 0x00000020 /
		2365	#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /!< Port C selected /
		2366	#define AFIO_EVCR_PORT_PD_Pos (4U)
		2367	#define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /!< 0x00000030 /
		2368	#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /!< Port D selected /
		2369	#define AFIO_EVCR_PORT_PE_Pos (6U)
		2370	#define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /!< 0x00000040 /
		2371	#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /!< Port E selected /
		2372
		2373	#define AFIO_EVCR_EVOE_Pos (7U)
		2374	#define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /!< 0x00000080 /
		2375	#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /!< Event Output Enable /
		2376
		2377	/**************** Bit definition for AFIO_MAPR register *****************/
		2378	#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
		2379	#define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /!< 0x00000001 /
		2380	#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /!< SPI1 remapping /
		2381	#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
		2382	#define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /!< 0x00000002 /
		2383	#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /!< I2C1 remapping /
		2384	#define AFIO_MAPR_USART1_REMAP_Pos (2U)
		2385	#define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /!< 0x00000004 /
		2386	#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /!< USART1 remapping /
		2387	#define AFIO_MAPR_USART2_REMAP_Pos (3U)
		2388	#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /!< 0x00000008 /
		2389	#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /!< USART2 remapping /
		2390
		2391	#define AFIO_MAPR_USART3_REMAP_Pos (4U)
		2392	#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000030 /
		2393	#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /!< USART3_REMAP[1:0] bits (USART3 remapping) /
		2394	#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000010 /
		2395	#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000020 /
		2396
		2397	/* USART3_REMAP configuration */
		2398	#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
		2399	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
		2400	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /!< 0x00000010 /
		2401	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
		2402	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
		2403	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /!< 0x00000030 /
		2404	#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
		2405
		2406	#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
		2407	#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x000000C0 /
		2408	#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
		2409	#define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000040 /
		2410	#define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000080 /
		2411
		2412	/!< TIM1_REMAP configuration /
		2413	#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
		2414	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
		2415	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /!< 0x00000040 /
		2416	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
		2417	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
		2418	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /!< 0x000000C0 /
		2419	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
		2420
		2421	#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
		2422	#define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000300 /
		2423	#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
		2424	#define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000100 /
		2425	#define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000200 /
		2426
		2427	/!< TIM2_REMAP configuration /
		2428	#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
		2429	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
		2430	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /!< 0x00000100 /
		2431	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
		2432	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
		2433	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /!< 0x00000200 /
		2434	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
		2435	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
		2436	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /!< 0x00000300 /
		2437	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
		2438
		2439	#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
		2440	#define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000C00 /
		2441	#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
		2442	#define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000400 /
		2443	#define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000800 /
		2444
		2445	/!< TIM3_REMAP configuration /
		2446	#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
		2447	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
		2448	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /!< 0x00000800 /
		2449	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
		2450	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
		2451	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /!< 0x00000C00 /
		2452	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
		2453
		2454	#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
		2455	#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /!< 0x00001000 /
		2456	#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /!< TIM4_REMAP bit (TIM4 remapping) /
		2457
		2458
		2459	#define AFIO_MAPR_PD01_REMAP_Pos (15U)
		2460	#define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /!< 0x00008000 /
		2461	#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
		2462	#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
		2463	#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /!< 0x00010000 /
		2464	#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /!< TIM5 Channel4 Internal Remap /
		2465
		2466	/!< SWJ_CFG configuration /
		2467	#define AFIO_MAPR_SWJ_CFG_Pos (24U)
		2468	#define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x07000000 /
		2469	#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
		2470	#define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x01000000 /
		2471	#define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x02000000 /
		2472	#define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x04000000 /
		2473
		2474	#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
		2475	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
		2476	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /!< 0x01000000 /
		2477	#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
		2478	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
		2479	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /!< 0x02000000 /
		2480	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /!< JTAG-DP Disabled and SW-DP Enabled /
		2481	#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
		2482	#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /!< 0x04000000 /
		2483	#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /!< JTAG-DP Disabled and SW-DP Disabled /
		2484
		2485
		2486	/*************** Bit definition for AFIO_EXTICR1 register ***************/
		2487	#define AFIO_EXTICR1_EXTI0_Pos (0U)
		2488	#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /!< 0x0000000F /
		2489	#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /!< EXTI 0 configuration /
		2490	#define AFIO_EXTICR1_EXTI1_Pos (4U)
		2491	#define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /!< 0x000000F0 /
		2492	#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /!< EXTI 1 configuration /
		2493	#define AFIO_EXTICR1_EXTI2_Pos (8U)
		2494	#define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /!< 0x00000F00 /
		2495	#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /!< EXTI 2 configuration /
		2496	#define AFIO_EXTICR1_EXTI3_Pos (12U)
		2497	#define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /!< 0x0000F000 /
		2498	#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /!< EXTI 3 configuration /
		2499
		2500	/!< EXTI0 configuration /
		2501	#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /!< PA[0] pin /
		2502	#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
		2503	#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /!< 0x00000001 /
		2504	#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /!< PB[0] pin /
		2505	#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
		2506	#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /!< 0x00000002 /
		2507	#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /!< PC[0] pin /
		2508	#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
		2509	#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /!< 0x00000003 /
		2510	#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /!< PD[0] pin /
		2511	#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
		2512	#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /!< 0x00000004 /
		2513	#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /!< PE[0] pin /
		2514	#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
		2515	#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /!< 0x00000005 /
		2516	#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /!< PF[0] pin /
		2517	#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
		2518	#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /!< 0x00000006 /
		2519	#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /!< PG[0] pin /
		2520
		2521	/!< EXTI1 configuration /
		2522	#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /!< PA[1] pin /
		2523	#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
		2524	#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /!< 0x00000010 /
		2525	#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /!< PB[1] pin /
		2526	#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
		2527	#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /!< 0x00000020 /
		2528	#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /!< PC[1] pin /
		2529	#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
		2530	#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /!< 0x00000030 /
		2531	#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /!< PD[1] pin /
		2532	#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
		2533	#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /!< 0x00000040 /
		2534	#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /!< PE[1] pin /
		2535	#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
		2536	#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /!< 0x00000050 /
		2537	#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /!< PF[1] pin /
		2538	#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
		2539	#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /!< 0x00000060 /
		2540	#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /!< PG[1] pin /
		2541
		2542	/!< EXTI2 configuration /
		2543	#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /!< PA[2] pin /
		2544	#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
		2545	#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /!< 0x00000100 /
		2546	#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /!< PB[2] pin /
		2547	#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
		2548	#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /!< 0x00000200 /
		2549	#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /!< PC[2] pin /
		2550	#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
		2551	#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /!< 0x00000300 /
		2552	#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /!< PD[2] pin /
		2553	#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
		2554	#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /!< 0x00000400 /
		2555	#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /!< PE[2] pin /
		2556	#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
		2557	#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /!< 0x00000500 /
		2558	#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /!< PF[2] pin /
		2559	#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
		2560	#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /!< 0x00000600 /
		2561	#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /!< PG[2] pin /
		2562
		2563	/!< EXTI3 configuration /
		2564	#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /!< PA[3] pin /
		2565	#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
		2566	#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /!< 0x00001000 /
		2567	#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /!< PB[3] pin /
		2568	#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
		2569	#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /!< 0x00002000 /
		2570	#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /!< PC[3] pin /
		2571	#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
		2572	#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /!< 0x00003000 /
		2573	#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /!< PD[3] pin /
		2574	#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
		2575	#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /!< 0x00004000 /
		2576	#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /!< PE[3] pin /
		2577	#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
		2578	#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /!< 0x00005000 /
		2579	#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /!< PF[3] pin /
		2580	#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
		2581	#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /!< 0x00006000 /
		2582	#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /!< PG[3] pin /
		2583
		2584	/*************** Bit definition for AFIO_EXTICR2 register ***************/
		2585	#define AFIO_EXTICR2_EXTI4_Pos (0U)
		2586	#define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /!< 0x0000000F /
		2587	#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /!< EXTI 4 configuration /
		2588	#define AFIO_EXTICR2_EXTI5_Pos (4U)
		2589	#define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /!< 0x000000F0 /
		2590	#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /!< EXTI 5 configuration /
		2591	#define AFIO_EXTICR2_EXTI6_Pos (8U)
		2592	#define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /!< 0x00000F00 /
		2593	#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /!< EXTI 6 configuration /
		2594	#define AFIO_EXTICR2_EXTI7_Pos (12U)
		2595	#define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /!< 0x0000F000 /
		2596	#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /!< EXTI 7 configuration /
		2597
		2598	/!< EXTI4 configuration /
		2599	#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /!< PA[4] pin /
		2600	#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
		2601	#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /!< 0x00000001 /
		2602	#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /!< PB[4] pin /
		2603	#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
		2604	#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /!< 0x00000002 /
		2605	#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /!< PC[4] pin /
		2606	#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
		2607	#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /!< 0x00000003 /
		2608	#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /!< PD[4] pin /
		2609	#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
		2610	#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /!< 0x00000004 /
		2611	#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /!< PE[4] pin /
		2612	#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
		2613	#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /!< 0x00000005 /
		2614	#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /!< PF[4] pin /
		2615	#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
		2616	#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /!< 0x00000006 /
		2617	#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /!< PG[4] pin /
		2618
		2619	/* EXTI5 configuration */
		2620	#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /!< PA[5] pin /
		2621	#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
		2622	#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /!< 0x00000010 /
		2623	#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /!< PB[5] pin /
		2624	#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
		2625	#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /!< 0x00000020 /
		2626	#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /!< PC[5] pin /
		2627	#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
		2628	#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /!< 0x00000030 /
		2629	#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /!< PD[5] pin /
		2630	#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
		2631	#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /!< 0x00000040 /
		2632	#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /!< PE[5] pin /
		2633	#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
		2634	#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /!< 0x00000050 /
		2635	#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /!< PF[5] pin /
		2636	#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
		2637	#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /!< 0x00000060 /
		2638	#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /!< PG[5] pin /
		2639
		2640	/!< EXTI6 configuration /
		2641	#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /!< PA[6] pin /
		2642	#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
		2643	#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /!< 0x00000100 /
		2644	#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /!< PB[6] pin /
		2645	#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
		2646	#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /!< 0x00000200 /
		2647	#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /!< PC[6] pin /
		2648	#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
		2649	#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /!< 0x00000300 /
		2650	#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /!< PD[6] pin /
		2651	#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
		2652	#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /!< 0x00000400 /
		2653	#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /!< PE[6] pin /
		2654	#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
		2655	#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /!< 0x00000500 /
		2656	#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /!< PF[6] pin /
		2657	#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
		2658	#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /!< 0x00000600 /
		2659	#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /!< PG[6] pin /
		2660
		2661	/!< EXTI7 configuration /
		2662	#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /!< PA[7] pin /
		2663	#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
		2664	#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /!< 0x00001000 /
		2665	#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /!< PB[7] pin /
		2666	#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
		2667	#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /!< 0x00002000 /
		2668	#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /!< PC[7] pin /
		2669	#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
		2670	#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /!< 0x00003000 /
		2671	#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /!< PD[7] pin /
		2672	#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
		2673	#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /!< 0x00004000 /
		2674	#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /!< PE[7] pin /
		2675	#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
		2676	#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /!< 0x00005000 /
		2677	#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /!< PF[7] pin /
		2678	#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
		2679	#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /!< 0x00006000 /
		2680	#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /!< PG[7] pin /
		2681
		2682	/*************** Bit definition for AFIO_EXTICR3 register ***************/
		2683	#define AFIO_EXTICR3_EXTI8_Pos (0U)
		2684	#define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /!< 0x0000000F /
		2685	#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /!< EXTI 8 configuration /
		2686	#define AFIO_EXTICR3_EXTI9_Pos (4U)
		2687	#define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /!< 0x000000F0 /
		2688	#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /!< EXTI 9 configuration /
		2689	#define AFIO_EXTICR3_EXTI10_Pos (8U)
		2690	#define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /!< 0x00000F00 /
		2691	#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /!< EXTI 10 configuration /
		2692	#define AFIO_EXTICR3_EXTI11_Pos (12U)
		2693	#define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /!< 0x0000F000 /
		2694	#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /!< EXTI 11 configuration /
		2695
		2696	/!< EXTI8 configuration /
		2697	#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /!< PA[8] pin /
		2698	#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
		2699	#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /!< 0x00000001 /
		2700	#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /!< PB[8] pin /
		2701	#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
		2702	#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /!< 0x00000002 /
		2703	#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /!< PC[8] pin /
		2704	#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
		2705	#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /!< 0x00000003 /
		2706	#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /!< PD[8] pin /
		2707	#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
		2708	#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /!< 0x00000004 /
		2709	#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /!< PE[8] pin /
		2710	#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
		2711	#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /!< 0x00000005 /
		2712	#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /!< PF[8] pin /
		2713	#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
		2714	#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /!< 0x00000006 /
		2715	#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /!< PG[8] pin /
		2716
		2717	/!< EXTI9 configuration /
		2718	#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /!< PA[9] pin /
		2719	#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
		2720	#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /!< 0x00000010 /
		2721	#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /!< PB[9] pin /
		2722	#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
		2723	#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /!< 0x00000020 /
		2724	#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /!< PC[9] pin /
		2725	#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
		2726	#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /!< 0x00000030 /
		2727	#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /!< PD[9] pin /
		2728	#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
		2729	#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /!< 0x00000040 /
		2730	#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /!< PE[9] pin /
		2731	#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
		2732	#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /!< 0x00000050 /
		2733	#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /!< PF[9] pin /
		2734	#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
		2735	#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /!< 0x00000060 /
		2736	#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /!< PG[9] pin /
		2737
		2738	/!< EXTI10 configuration /
		2739	#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /!< PA[10] pin /
		2740	#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
		2741	#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /!< 0x00000100 /
		2742	#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /!< PB[10] pin /
		2743	#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
		2744	#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /!< 0x00000200 /
		2745	#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /!< PC[10] pin /
		2746	#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
		2747	#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /!< 0x00000300 /
		2748	#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /!< PD[10] pin /
		2749	#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
		2750	#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /!< 0x00000400 /
		2751	#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /!< PE[10] pin /
		2752	#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
		2753	#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /!< 0x00000500 /
		2754	#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /!< PF[10] pin /
		2755	#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
		2756	#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /!< 0x00000600 /
		2757	#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /!< PG[10] pin /
		2758
		2759	/!< EXTI11 configuration /
		2760	#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /!< PA[11] pin /
		2761	#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
		2762	#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /!< 0x00001000 /
		2763	#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /!< PB[11] pin /
		2764	#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
		2765	#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /!< 0x00002000 /
		2766	#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /!< PC[11] pin /
		2767	#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
		2768	#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /!< 0x00003000 /
		2769	#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /!< PD[11] pin /
		2770	#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
		2771	#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /!< 0x00004000 /
		2772	#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /!< PE[11] pin /
		2773	#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
		2774	#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /!< 0x00005000 /
		2775	#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /!< PF[11] pin /
		2776	#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
		2777	#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /!< 0x00006000 /
		2778	#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /!< PG[11] pin /
		2779
		2780	/*************** Bit definition for AFIO_EXTICR4 register ***************/
		2781	#define AFIO_EXTICR4_EXTI12_Pos (0U)
		2782	#define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /!< 0x0000000F /
		2783	#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /!< EXTI 12 configuration /
		2784	#define AFIO_EXTICR4_EXTI13_Pos (4U)
		2785	#define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /!< 0x000000F0 /
		2786	#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /!< EXTI 13 configuration /
		2787	#define AFIO_EXTICR4_EXTI14_Pos (8U)
		2788	#define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /!< 0x00000F00 /
		2789	#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /!< EXTI 14 configuration /
		2790	#define AFIO_EXTICR4_EXTI15_Pos (12U)
		2791	#define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /!< 0x0000F000 /
		2792	#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /!< EXTI 15 configuration /
		2793
		2794	/* EXTI12 configuration */
		2795	#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /!< PA[12] pin /
		2796	#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
		2797	#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /!< 0x00000001 /
		2798	#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /!< PB[12] pin /
		2799	#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
		2800	#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /!< 0x00000002 /
		2801	#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /!< PC[12] pin /
		2802	#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
		2803	#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /!< 0x00000003 /
		2804	#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /!< PD[12] pin /
		2805	#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
		2806	#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /!< 0x00000004 /
		2807	#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /!< PE[12] pin /
		2808	#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
		2809	#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /!< 0x00000005 /
		2810	#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /!< PF[12] pin /
		2811	#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
		2812	#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /!< 0x00000006 /
		2813	#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /!< PG[12] pin /
		2814
		2815	/* EXTI13 configuration */
		2816	#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /!< PA[13] pin /
		2817	#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
		2818	#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /!< 0x00000010 /
		2819	#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /!< PB[13] pin /
		2820	#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
		2821	#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /!< 0x00000020 /
		2822	#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /!< PC[13] pin /
		2823	#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
		2824	#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /!< 0x00000030 /
		2825	#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /!< PD[13] pin /
		2826	#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
		2827	#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /!< 0x00000040 /
		2828	#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /!< PE[13] pin /
		2829	#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
		2830	#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /!< 0x00000050 /
		2831	#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /!< PF[13] pin /
		2832	#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
		2833	#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /!< 0x00000060 /
		2834	#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /!< PG[13] pin /
		2835
		2836	/!< EXTI14 configuration /
		2837	#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /!< PA[14] pin /
		2838	#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
		2839	#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /!< 0x00000100 /
		2840	#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /!< PB[14] pin /
		2841	#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
		2842	#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /!< 0x00000200 /
		2843	#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /!< PC[14] pin /
		2844	#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
		2845	#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /!< 0x00000300 /
		2846	#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /!< PD[14] pin /
		2847	#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
		2848	#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /!< 0x00000400 /
		2849	#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /!< PE[14] pin /
		2850	#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
		2851	#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /!< 0x00000500 /
		2852	#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /!< PF[14] pin /
		2853	#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
		2854	#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /!< 0x00000600 /
		2855	#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /!< PG[14] pin /
		2856
		2857	/!< EXTI15 configuration /
		2858	#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /!< PA[15] pin /
		2859	#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
		2860	#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /!< 0x00001000 /
		2861	#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /!< PB[15] pin /
		2862	#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
		2863	#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /!< 0x00002000 /
		2864	#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /!< PC[15] pin /
		2865	#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
		2866	#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /!< 0x00003000 /
		2867	#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /!< PD[15] pin /
		2868	#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
		2869	#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /!< 0x00004000 /
		2870	#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /!< PE[15] pin /
		2871	#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
		2872	#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /!< 0x00005000 /
		2873	#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /!< PF[15] pin /
		2874	#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
		2875	#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /!< 0x00006000 /
		2876	#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /!< PG[15] pin /
		2877
		2878	/**************** Bit definition for AFIO_MAPR2 register ****************/
		2879	#define AFIO_MAPR2_TIM15_REMAP_Pos (0U)
		2880	#define AFIO_MAPR2_TIM15_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM15_REMAP_Pos) /!< 0x00000001 /
		2881	#define AFIO_MAPR2_TIM15_REMAP AFIO_MAPR2_TIM15_REMAP_Msk /!< TIM15 remapping /
		2882	#define AFIO_MAPR2_TIM16_REMAP_Pos (1U)
		2883	#define AFIO_MAPR2_TIM16_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM16_REMAP_Pos) /!< 0x00000002 /
		2884	#define AFIO_MAPR2_TIM16_REMAP AFIO_MAPR2_TIM16_REMAP_Msk /!< TIM16 remapping /
		2885	#define AFIO_MAPR2_TIM17_REMAP_Pos (2U)
		2886	#define AFIO_MAPR2_TIM17_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM17_REMAP_Pos) /!< 0x00000004 /
		2887	#define AFIO_MAPR2_TIM17_REMAP AFIO_MAPR2_TIM17_REMAP_Msk /!< TIM17 remapping /
		2888	#define AFIO_MAPR2_CEC_REMAP_Pos (3U)
		2889	#define AFIO_MAPR2_CEC_REMAP_Msk (0x1UL << AFIO_MAPR2_CEC_REMAP_Pos) /!< 0x00000008 /
		2890	#define AFIO_MAPR2_CEC_REMAP AFIO_MAPR2_CEC_REMAP_Msk /!< CEC remapping /
		2891	#define AFIO_MAPR2_TIM1_DMA_REMAP_Pos (4U)
		2892	#define AFIO_MAPR2_TIM1_DMA_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM1_DMA_REMAP_Pos) /!< 0x00000010 /
		2893	#define AFIO_MAPR2_TIM1_DMA_REMAP AFIO_MAPR2_TIM1_DMA_REMAP_Msk /!< TIM1_DMA remapping /
		2894
		2895	#define AFIO_MAPR2_TIM13_REMAP_Pos (8U)
		2896	#define AFIO_MAPR2_TIM13_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM13_REMAP_Pos) /!< 0x00000100 /
		2897	#define AFIO_MAPR2_TIM13_REMAP AFIO_MAPR2_TIM13_REMAP_Msk /!< TIM13 remapping /
		2898	#define AFIO_MAPR2_TIM14_REMAP_Pos (9U)
		2899	#define AFIO_MAPR2_TIM14_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM14_REMAP_Pos) /!< 0x00000200 /
		2900	#define AFIO_MAPR2_TIM14_REMAP AFIO_MAPR2_TIM14_REMAP_Msk /!< TIM14 remapping /
		2901	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos (11U)
		2902	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos) /!< 0x00000800 /
		2903	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk /!< TIM6/TIM7 and DAC DMA remapping /
		2904	#define AFIO_MAPR2_TIM12_REMAP_Pos (12U)
		2905	#define AFIO_MAPR2_TIM12_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM12_REMAP_Pos) /!< 0x00001000 /
		2906	#define AFIO_MAPR2_TIM12_REMAP AFIO_MAPR2_TIM12_REMAP_Msk /!< TIM12 remapping /
		2907	#define AFIO_MAPR2_MISC_REMAP_Pos (13U)
		2908	#define AFIO_MAPR2_MISC_REMAP_Msk (0x1UL << AFIO_MAPR2_MISC_REMAP_Pos) /!< 0x00002000 /
		2909	#define AFIO_MAPR2_MISC_REMAP AFIO_MAPR2_MISC_REMAP_Msk /!< Miscellaneous remapping /
		2910
		2911	#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U)
		2912	#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1UL << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /!< 0x00000400 /
		2913	#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /!< FSMC NADV remapping /
		2914
		2915	/******************************************************************************/
		2916	/* */
		2917	/* External Interrupt/Event Controller */
		2918	/* */
		2919	/******************************************************************************/
		2920
		2921	/***************** Bit definition for EXTI_IMR register *****************/
		2922	#define EXTI_IMR_MR0_Pos (0U)
		2923	#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /!< 0x00000001 /
		2924	#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /!< Interrupt Mask on line 0 /
		2925	#define EXTI_IMR_MR1_Pos (1U)
		2926	#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /!< 0x00000002 /
		2927	#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /!< Interrupt Mask on line 1 /
		2928	#define EXTI_IMR_MR2_Pos (2U)
		2929	#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /!< 0x00000004 /
		2930	#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /!< Interrupt Mask on line 2 /
		2931	#define EXTI_IMR_MR3_Pos (3U)
		2932	#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /!< 0x00000008 /
		2933	#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /!< Interrupt Mask on line 3 /
		2934	#define EXTI_IMR_MR4_Pos (4U)
		2935	#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /!< 0x00000010 /
		2936	#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /!< Interrupt Mask on line 4 /
		2937	#define EXTI_IMR_MR5_Pos (5U)
		2938	#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /!< 0x00000020 /
		2939	#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /!< Interrupt Mask on line 5 /
		2940	#define EXTI_IMR_MR6_Pos (6U)
		2941	#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /!< 0x00000040 /
		2942	#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /!< Interrupt Mask on line 6 /
		2943	#define EXTI_IMR_MR7_Pos (7U)
		2944	#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /!< 0x00000080 /
		2945	#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /!< Interrupt Mask on line 7 /
		2946	#define EXTI_IMR_MR8_Pos (8U)
		2947	#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /!< 0x00000100 /
		2948	#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /!< Interrupt Mask on line 8 /
		2949	#define EXTI_IMR_MR9_Pos (9U)
		2950	#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /!< 0x00000200 /
		2951	#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /!< Interrupt Mask on line 9 /
		2952	#define EXTI_IMR_MR10_Pos (10U)
		2953	#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /!< 0x00000400 /
		2954	#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /!< Interrupt Mask on line 10 /
		2955	#define EXTI_IMR_MR11_Pos (11U)
		2956	#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /!< 0x00000800 /
		2957	#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /!< Interrupt Mask on line 11 /
		2958	#define EXTI_IMR_MR12_Pos (12U)
		2959	#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /!< 0x00001000 /
		2960	#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /!< Interrupt Mask on line 12 /
		2961	#define EXTI_IMR_MR13_Pos (13U)
		2962	#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /!< 0x00002000 /
		2963	#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /!< Interrupt Mask on line 13 /
		2964	#define EXTI_IMR_MR14_Pos (14U)
		2965	#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /!< 0x00004000 /
		2966	#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /!< Interrupt Mask on line 14 /
		2967	#define EXTI_IMR_MR15_Pos (15U)
		2968	#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /!< 0x00008000 /
		2969	#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /!< Interrupt Mask on line 15 /
		2970	#define EXTI_IMR_MR16_Pos (16U)
		2971	#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /!< 0x00010000 /
		2972	#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /!< Interrupt Mask on line 16 /
		2973	#define EXTI_IMR_MR17_Pos (17U)
		2974	#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /!< 0x00020000 /
		2975	#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /!< Interrupt Mask on line 17 /
		2976
		2977	/* References Defines */
		2978	#define EXTI_IMR_IM0 EXTI_IMR_MR0
		2979	#define EXTI_IMR_IM1 EXTI_IMR_MR1
		2980	#define EXTI_IMR_IM2 EXTI_IMR_MR2
		2981	#define EXTI_IMR_IM3 EXTI_IMR_MR3
		2982	#define EXTI_IMR_IM4 EXTI_IMR_MR4
		2983	#define EXTI_IMR_IM5 EXTI_IMR_MR5
		2984	#define EXTI_IMR_IM6 EXTI_IMR_MR6
		2985	#define EXTI_IMR_IM7 EXTI_IMR_MR7
		2986	#define EXTI_IMR_IM8 EXTI_IMR_MR8
		2987	#define EXTI_IMR_IM9 EXTI_IMR_MR9
		2988	#define EXTI_IMR_IM10 EXTI_IMR_MR10
		2989	#define EXTI_IMR_IM11 EXTI_IMR_MR11
		2990	#define EXTI_IMR_IM12 EXTI_IMR_MR12
		2991	#define EXTI_IMR_IM13 EXTI_IMR_MR13
		2992	#define EXTI_IMR_IM14 EXTI_IMR_MR14
		2993	#define EXTI_IMR_IM15 EXTI_IMR_MR15
		2994	#define EXTI_IMR_IM16 EXTI_IMR_MR16
		2995	#define EXTI_IMR_IM17 EXTI_IMR_MR17
		2996	#define EXTI_IMR_IM 0x0003FFFFU /!< Interrupt Mask All /
		2997
		2998	/***************** Bit definition for EXTI_EMR register *****************/
		2999	#define EXTI_EMR_MR0_Pos (0U)
		3000	#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /!< 0x00000001 /
		3001	#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /!< Event Mask on line 0 /
		3002	#define EXTI_EMR_MR1_Pos (1U)
		3003	#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /!< 0x00000002 /
		3004	#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /!< Event Mask on line 1 /
		3005	#define EXTI_EMR_MR2_Pos (2U)
		3006	#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /!< 0x00000004 /
		3007	#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /!< Event Mask on line 2 /
		3008	#define EXTI_EMR_MR3_Pos (3U)
		3009	#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /!< 0x00000008 /
		3010	#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /!< Event Mask on line 3 /
		3011	#define EXTI_EMR_MR4_Pos (4U)
		3012	#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /!< 0x00000010 /
		3013	#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /!< Event Mask on line 4 /
		3014	#define EXTI_EMR_MR5_Pos (5U)
		3015	#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /!< 0x00000020 /
		3016	#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /!< Event Mask on line 5 /
		3017	#define EXTI_EMR_MR6_Pos (6U)
		3018	#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /!< 0x00000040 /
		3019	#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /!< Event Mask on line 6 /
		3020	#define EXTI_EMR_MR7_Pos (7U)
		3021	#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /!< 0x00000080 /
		3022	#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /!< Event Mask on line 7 /
		3023	#define EXTI_EMR_MR8_Pos (8U)
		3024	#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /!< 0x00000100 /
		3025	#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /!< Event Mask on line 8 /
		3026	#define EXTI_EMR_MR9_Pos (9U)
		3027	#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /!< 0x00000200 /
		3028	#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /!< Event Mask on line 9 /
		3029	#define EXTI_EMR_MR10_Pos (10U)
		3030	#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /!< 0x00000400 /
		3031	#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /!< Event Mask on line 10 /
		3032	#define EXTI_EMR_MR11_Pos (11U)
		3033	#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /!< 0x00000800 /
		3034	#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /!< Event Mask on line 11 /
		3035	#define EXTI_EMR_MR12_Pos (12U)
		3036	#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /!< 0x00001000 /
		3037	#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /!< Event Mask on line 12 /
		3038	#define EXTI_EMR_MR13_Pos (13U)
		3039	#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /!< 0x00002000 /
		3040	#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /!< Event Mask on line 13 /
		3041	#define EXTI_EMR_MR14_Pos (14U)
		3042	#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /!< 0x00004000 /
		3043	#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /!< Event Mask on line 14 /
		3044	#define EXTI_EMR_MR15_Pos (15U)
		3045	#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /!< 0x00008000 /
		3046	#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /!< Event Mask on line 15 /
		3047	#define EXTI_EMR_MR16_Pos (16U)
		3048	#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /!< 0x00010000 /
		3049	#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /!< Event Mask on line 16 /
		3050	#define EXTI_EMR_MR17_Pos (17U)
		3051	#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /!< 0x00020000 /
		3052	#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /!< Event Mask on line 17 /
		3053
		3054	/* References Defines */
		3055	#define EXTI_EMR_EM0 EXTI_EMR_MR0
		3056	#define EXTI_EMR_EM1 EXTI_EMR_MR1
		3057	#define EXTI_EMR_EM2 EXTI_EMR_MR2
		3058	#define EXTI_EMR_EM3 EXTI_EMR_MR3
		3059	#define EXTI_EMR_EM4 EXTI_EMR_MR4
		3060	#define EXTI_EMR_EM5 EXTI_EMR_MR5
		3061	#define EXTI_EMR_EM6 EXTI_EMR_MR6
		3062	#define EXTI_EMR_EM7 EXTI_EMR_MR7
		3063	#define EXTI_EMR_EM8 EXTI_EMR_MR8
		3064	#define EXTI_EMR_EM9 EXTI_EMR_MR9
		3065	#define EXTI_EMR_EM10 EXTI_EMR_MR10
		3066	#define EXTI_EMR_EM11 EXTI_EMR_MR11
		3067	#define EXTI_EMR_EM12 EXTI_EMR_MR12
		3068	#define EXTI_EMR_EM13 EXTI_EMR_MR13
		3069	#define EXTI_EMR_EM14 EXTI_EMR_MR14
		3070	#define EXTI_EMR_EM15 EXTI_EMR_MR15
		3071	#define EXTI_EMR_EM16 EXTI_EMR_MR16
		3072	#define EXTI_EMR_EM17 EXTI_EMR_MR17
		3073
		3074	/**************** Bit definition for EXTI_RTSR register *****************/
		3075	#define EXTI_RTSR_TR0_Pos (0U)
		3076	#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /!< 0x00000001 /
		3077	#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /!< Rising trigger event configuration bit of line 0 /
		3078	#define EXTI_RTSR_TR1_Pos (1U)
		3079	#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /!< 0x00000002 /
		3080	#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /!< Rising trigger event configuration bit of line 1 /
		3081	#define EXTI_RTSR_TR2_Pos (2U)
		3082	#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /!< 0x00000004 /
		3083	#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /!< Rising trigger event configuration bit of line 2 /
		3084	#define EXTI_RTSR_TR3_Pos (3U)
		3085	#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /!< 0x00000008 /
		3086	#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /!< Rising trigger event configuration bit of line 3 /
		3087	#define EXTI_RTSR_TR4_Pos (4U)
		3088	#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /!< 0x00000010 /
		3089	#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /!< Rising trigger event configuration bit of line 4 /
		3090	#define EXTI_RTSR_TR5_Pos (5U)
		3091	#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /!< 0x00000020 /
		3092	#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /!< Rising trigger event configuration bit of line 5 /
		3093	#define EXTI_RTSR_TR6_Pos (6U)
		3094	#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /!< 0x00000040 /
		3095	#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /!< Rising trigger event configuration bit of line 6 /
		3096	#define EXTI_RTSR_TR7_Pos (7U)
		3097	#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /!< 0x00000080 /
		3098	#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /!< Rising trigger event configuration bit of line 7 /
		3099	#define EXTI_RTSR_TR8_Pos (8U)
		3100	#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /!< 0x00000100 /
		3101	#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /!< Rising trigger event configuration bit of line 8 /
		3102	#define EXTI_RTSR_TR9_Pos (9U)
		3103	#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /!< 0x00000200 /
		3104	#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /!< Rising trigger event configuration bit of line 9 /
		3105	#define EXTI_RTSR_TR10_Pos (10U)
		3106	#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /!< 0x00000400 /
		3107	#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /!< Rising trigger event configuration bit of line 10 /
		3108	#define EXTI_RTSR_TR11_Pos (11U)
		3109	#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /!< 0x00000800 /
		3110	#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /!< Rising trigger event configuration bit of line 11 /
		3111	#define EXTI_RTSR_TR12_Pos (12U)
		3112	#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /!< 0x00001000 /
		3113	#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /!< Rising trigger event configuration bit of line 12 /
		3114	#define EXTI_RTSR_TR13_Pos (13U)
		3115	#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /!< 0x00002000 /
		3116	#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /!< Rising trigger event configuration bit of line 13 /
		3117	#define EXTI_RTSR_TR14_Pos (14U)
		3118	#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /!< 0x00004000 /
		3119	#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /!< Rising trigger event configuration bit of line 14 /
		3120	#define EXTI_RTSR_TR15_Pos (15U)
		3121	#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /!< 0x00008000 /
		3122	#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /!< Rising trigger event configuration bit of line 15 /
		3123	#define EXTI_RTSR_TR16_Pos (16U)
		3124	#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /!< 0x00010000 /
		3125	#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /!< Rising trigger event configuration bit of line 16 /
		3126	#define EXTI_RTSR_TR17_Pos (17U)
		3127	#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /!< 0x00020000 /
		3128	#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /!< Rising trigger event configuration bit of line 17 /
		3129
		3130	/* References Defines */
		3131	#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
		3132	#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
		3133	#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
		3134	#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
		3135	#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
		3136	#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
		3137	#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
		3138	#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
		3139	#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
		3140	#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
		3141	#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
		3142	#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
		3143	#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
		3144	#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
		3145	#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
		3146	#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
		3147	#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
		3148	#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
		3149
		3150	/**************** Bit definition for EXTI_FTSR register *****************/
		3151	#define EXTI_FTSR_TR0_Pos (0U)
		3152	#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /!< 0x00000001 /
		3153	#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /!< Falling trigger event configuration bit of line 0 /
		3154	#define EXTI_FTSR_TR1_Pos (1U)
		3155	#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /!< 0x00000002 /
		3156	#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /!< Falling trigger event configuration bit of line 1 /
		3157	#define EXTI_FTSR_TR2_Pos (2U)
		3158	#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /!< 0x00000004 /
		3159	#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /!< Falling trigger event configuration bit of line 2 /
		3160	#define EXTI_FTSR_TR3_Pos (3U)
		3161	#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /!< 0x00000008 /
		3162	#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /!< Falling trigger event configuration bit of line 3 /
		3163	#define EXTI_FTSR_TR4_Pos (4U)
		3164	#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /!< 0x00000010 /
		3165	#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /!< Falling trigger event configuration bit of line 4 /
		3166	#define EXTI_FTSR_TR5_Pos (5U)
		3167	#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /!< 0x00000020 /
		3168	#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /!< Falling trigger event configuration bit of line 5 /
		3169	#define EXTI_FTSR_TR6_Pos (6U)
		3170	#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /!< 0x00000040 /
		3171	#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /!< Falling trigger event configuration bit of line 6 /
		3172	#define EXTI_FTSR_TR7_Pos (7U)
		3173	#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /!< 0x00000080 /
		3174	#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /!< Falling trigger event configuration bit of line 7 /
		3175	#define EXTI_FTSR_TR8_Pos (8U)
		3176	#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /!< 0x00000100 /
		3177	#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /!< Falling trigger event configuration bit of line 8 /
		3178	#define EXTI_FTSR_TR9_Pos (9U)
		3179	#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /!< 0x00000200 /
		3180	#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /!< Falling trigger event configuration bit of line 9 /
		3181	#define EXTI_FTSR_TR10_Pos (10U)
		3182	#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /!< 0x00000400 /
		3183	#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /!< Falling trigger event configuration bit of line 10 /
		3184	#define EXTI_FTSR_TR11_Pos (11U)
		3185	#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /!< 0x00000800 /
		3186	#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /!< Falling trigger event configuration bit of line 11 /
		3187	#define EXTI_FTSR_TR12_Pos (12U)
		3188	#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /!< 0x00001000 /
		3189	#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /!< Falling trigger event configuration bit of line 12 /
		3190	#define EXTI_FTSR_TR13_Pos (13U)
		3191	#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /!< 0x00002000 /
		3192	#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /!< Falling trigger event configuration bit of line 13 /
		3193	#define EXTI_FTSR_TR14_Pos (14U)
		3194	#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /!< 0x00004000 /
		3195	#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /!< Falling trigger event configuration bit of line 14 /
		3196	#define EXTI_FTSR_TR15_Pos (15U)
		3197	#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /!< 0x00008000 /
		3198	#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /!< Falling trigger event configuration bit of line 15 /
		3199	#define EXTI_FTSR_TR16_Pos (16U)
		3200	#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /!< 0x00010000 /
		3201	#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /!< Falling trigger event configuration bit of line 16 /
		3202	#define EXTI_FTSR_TR17_Pos (17U)
		3203	#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /!< 0x00020000 /
		3204	#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /!< Falling trigger event configuration bit of line 17 /
		3205
		3206	/* References Defines */
		3207	#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
		3208	#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
		3209	#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
		3210	#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
		3211	#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
		3212	#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
		3213	#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
		3214	#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
		3215	#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
		3216	#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
		3217	#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
		3218	#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
		3219	#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
		3220	#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
		3221	#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
		3222	#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
		3223	#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
		3224	#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
		3225
		3226	/**************** Bit definition for EXTI_SWIER register ****************/
		3227	#define EXTI_SWIER_SWIER0_Pos (0U)
		3228	#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /!< 0x00000001 /
		3229	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /!< Software Interrupt on line 0 /
		3230	#define EXTI_SWIER_SWIER1_Pos (1U)
		3231	#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /!< 0x00000002 /
		3232	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /!< Software Interrupt on line 1 /
		3233	#define EXTI_SWIER_SWIER2_Pos (2U)
		3234	#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /!< 0x00000004 /
		3235	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /!< Software Interrupt on line 2 /
		3236	#define EXTI_SWIER_SWIER3_Pos (3U)
		3237	#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /!< 0x00000008 /
		3238	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /!< Software Interrupt on line 3 /
		3239	#define EXTI_SWIER_SWIER4_Pos (4U)
		3240	#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /!< 0x00000010 /
		3241	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /!< Software Interrupt on line 4 /
		3242	#define EXTI_SWIER_SWIER5_Pos (5U)
		3243	#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /!< 0x00000020 /
		3244	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /!< Software Interrupt on line 5 /
		3245	#define EXTI_SWIER_SWIER6_Pos (6U)
		3246	#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /!< 0x00000040 /
		3247	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /!< Software Interrupt on line 6 /
		3248	#define EXTI_SWIER_SWIER7_Pos (7U)
		3249	#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /!< 0x00000080 /
		3250	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /!< Software Interrupt on line 7 /
		3251	#define EXTI_SWIER_SWIER8_Pos (8U)
		3252	#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /!< 0x00000100 /
		3253	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /!< Software Interrupt on line 8 /
		3254	#define EXTI_SWIER_SWIER9_Pos (9U)
		3255	#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /!< 0x00000200 /
		3256	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /!< Software Interrupt on line 9 /
		3257	#define EXTI_SWIER_SWIER10_Pos (10U)
		3258	#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /!< 0x00000400 /
		3259	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /!< Software Interrupt on line 10 /
		3260	#define EXTI_SWIER_SWIER11_Pos (11U)
		3261	#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /!< 0x00000800 /
		3262	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /!< Software Interrupt on line 11 /
		3263	#define EXTI_SWIER_SWIER12_Pos (12U)
		3264	#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /!< 0x00001000 /
		3265	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /!< Software Interrupt on line 12 /
		3266	#define EXTI_SWIER_SWIER13_Pos (13U)
		3267	#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /!< 0x00002000 /
		3268	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /!< Software Interrupt on line 13 /
		3269	#define EXTI_SWIER_SWIER14_Pos (14U)
		3270	#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /!< 0x00004000 /
		3271	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /!< Software Interrupt on line 14 /
		3272	#define EXTI_SWIER_SWIER15_Pos (15U)
		3273	#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /!< 0x00008000 /
		3274	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /!< Software Interrupt on line 15 /
		3275	#define EXTI_SWIER_SWIER16_Pos (16U)
		3276	#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /!< 0x00010000 /
		3277	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /!< Software Interrupt on line 16 /
		3278	#define EXTI_SWIER_SWIER17_Pos (17U)
		3279	#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /!< 0x00020000 /
		3280	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /!< Software Interrupt on line 17 /
		3281
		3282	/* References Defines */
		3283	#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
		3284	#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
		3285	#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
		3286	#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
		3287	#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
		3288	#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
		3289	#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
		3290	#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
		3291	#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
		3292	#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
		3293	#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
		3294	#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
		3295	#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
		3296	#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
		3297	#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
		3298	#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
		3299	#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
		3300	#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
		3301
		3302	/***************** Bit definition for EXTI_PR register ******************/
		3303	#define EXTI_PR_PR0_Pos (0U)
		3304	#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /!< 0x00000001 /
		3305	#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /!< Pending bit for line 0 /
		3306	#define EXTI_PR_PR1_Pos (1U)
		3307	#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /!< 0x00000002 /
		3308	#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /!< Pending bit for line 1 /
		3309	#define EXTI_PR_PR2_Pos (2U)
		3310	#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /!< 0x00000004 /
		3311	#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /!< Pending bit for line 2 /
		3312	#define EXTI_PR_PR3_Pos (3U)
		3313	#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /!< 0x00000008 /
		3314	#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /!< Pending bit for line 3 /
		3315	#define EXTI_PR_PR4_Pos (4U)
		3316	#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /!< 0x00000010 /
		3317	#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /!< Pending bit for line 4 /
		3318	#define EXTI_PR_PR5_Pos (5U)
		3319	#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /!< 0x00000020 /
		3320	#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /!< Pending bit for line 5 /
		3321	#define EXTI_PR_PR6_Pos (6U)
		3322	#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /!< 0x00000040 /
		3323	#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /!< Pending bit for line 6 /
		3324	#define EXTI_PR_PR7_Pos (7U)
		3325	#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /!< 0x00000080 /
		3326	#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /!< Pending bit for line 7 /
		3327	#define EXTI_PR_PR8_Pos (8U)
		3328	#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /!< 0x00000100 /
		3329	#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /!< Pending bit for line 8 /
		3330	#define EXTI_PR_PR9_Pos (9U)
		3331	#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /!< 0x00000200 /
		3332	#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /!< Pending bit for line 9 /
		3333	#define EXTI_PR_PR10_Pos (10U)
		3334	#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /!< 0x00000400 /
		3335	#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /!< Pending bit for line 10 /
		3336	#define EXTI_PR_PR11_Pos (11U)
		3337	#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /!< 0x00000800 /
		3338	#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /!< Pending bit for line 11 /
		3339	#define EXTI_PR_PR12_Pos (12U)
		3340	#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /!< 0x00001000 /
		3341	#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /!< Pending bit for line 12 /
		3342	#define EXTI_PR_PR13_Pos (13U)
		3343	#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /!< 0x00002000 /
		3344	#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /!< Pending bit for line 13 /
		3345	#define EXTI_PR_PR14_Pos (14U)
		3346	#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /!< 0x00004000 /
		3347	#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /!< Pending bit for line 14 /
		3348	#define EXTI_PR_PR15_Pos (15U)
		3349	#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /!< 0x00008000 /
		3350	#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /!< Pending bit for line 15 /
		3351	#define EXTI_PR_PR16_Pos (16U)
		3352	#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /!< 0x00010000 /
		3353	#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /!< Pending bit for line 16 /
		3354	#define EXTI_PR_PR17_Pos (17U)
		3355	#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /!< 0x00020000 /
		3356	#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /!< Pending bit for line 17 /
		3357
		3358	/* References Defines */
		3359	#define EXTI_PR_PIF0 EXTI_PR_PR0
		3360	#define EXTI_PR_PIF1 EXTI_PR_PR1
		3361	#define EXTI_PR_PIF2 EXTI_PR_PR2
		3362	#define EXTI_PR_PIF3 EXTI_PR_PR3
		3363	#define EXTI_PR_PIF4 EXTI_PR_PR4
		3364	#define EXTI_PR_PIF5 EXTI_PR_PR5
		3365	#define EXTI_PR_PIF6 EXTI_PR_PR6
		3366	#define EXTI_PR_PIF7 EXTI_PR_PR7
		3367	#define EXTI_PR_PIF8 EXTI_PR_PR8
		3368	#define EXTI_PR_PIF9 EXTI_PR_PR9
		3369	#define EXTI_PR_PIF10 EXTI_PR_PR10
		3370	#define EXTI_PR_PIF11 EXTI_PR_PR11
		3371	#define EXTI_PR_PIF12 EXTI_PR_PR12
		3372	#define EXTI_PR_PIF13 EXTI_PR_PR13
		3373	#define EXTI_PR_PIF14 EXTI_PR_PR14
		3374	#define EXTI_PR_PIF15 EXTI_PR_PR15
		3375	#define EXTI_PR_PIF16 EXTI_PR_PR16
		3376	#define EXTI_PR_PIF17 EXTI_PR_PR17
		3377
		3378	/******************************************************************************/
		3379	/* */
		3380	/* DMA Controller */
		3381	/* */
		3382	/******************************************************************************/
		3383
		3384	/***************** Bit definition for DMA_ISR register ******************/
		3385	#define DMA_ISR_GIF1_Pos (0U)
		3386	#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /!< 0x00000001 /
		3387	#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /!< Channel 1 Global interrupt flag /
		3388	#define DMA_ISR_TCIF1_Pos (1U)
		3389	#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /!< 0x00000002 /
		3390	#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /!< Channel 1 Transfer Complete flag /
		3391	#define DMA_ISR_HTIF1_Pos (2U)
		3392	#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /!< 0x00000004 /
		3393	#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /!< Channel 1 Half Transfer flag /
		3394	#define DMA_ISR_TEIF1_Pos (3U)
		3395	#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /!< 0x00000008 /
		3396	#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /!< Channel 1 Transfer Error flag /
		3397	#define DMA_ISR_GIF2_Pos (4U)
		3398	#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /!< 0x00000010 /
		3399	#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /!< Channel 2 Global interrupt flag /
		3400	#define DMA_ISR_TCIF2_Pos (5U)
		3401	#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /!< 0x00000020 /
		3402	#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /!< Channel 2 Transfer Complete flag /
		3403	#define DMA_ISR_HTIF2_Pos (6U)
		3404	#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /!< 0x00000040 /
		3405	#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /!< Channel 2 Half Transfer flag /
		3406	#define DMA_ISR_TEIF2_Pos (7U)
		3407	#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /!< 0x00000080 /
		3408	#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /!< Channel 2 Transfer Error flag /
		3409	#define DMA_ISR_GIF3_Pos (8U)
		3410	#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /!< 0x00000100 /
		3411	#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /!< Channel 3 Global interrupt flag /
		3412	#define DMA_ISR_TCIF3_Pos (9U)
		3413	#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /!< 0x00000200 /
		3414	#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /!< Channel 3 Transfer Complete flag /
		3415	#define DMA_ISR_HTIF3_Pos (10U)
		3416	#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /!< 0x00000400 /
		3417	#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /!< Channel 3 Half Transfer flag /
		3418	#define DMA_ISR_TEIF3_Pos (11U)
		3419	#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /!< 0x00000800 /
		3420	#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /!< Channel 3 Transfer Error flag /
		3421	#define DMA_ISR_GIF4_Pos (12U)
		3422	#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /!< 0x00001000 /
		3423	#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /!< Channel 4 Global interrupt flag /
		3424	#define DMA_ISR_TCIF4_Pos (13U)
		3425	#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /!< 0x00002000 /
		3426	#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /!< Channel 4 Transfer Complete flag /
		3427	#define DMA_ISR_HTIF4_Pos (14U)
		3428	#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /!< 0x00004000 /
		3429	#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /!< Channel 4 Half Transfer flag /
		3430	#define DMA_ISR_TEIF4_Pos (15U)
		3431	#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /!< 0x00008000 /
		3432	#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /!< Channel 4 Transfer Error flag /
		3433	#define DMA_ISR_GIF5_Pos (16U)
		3434	#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /!< 0x00010000 /
		3435	#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /!< Channel 5 Global interrupt flag /
		3436	#define DMA_ISR_TCIF5_Pos (17U)
		3437	#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /!< 0x00020000 /
		3438	#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /!< Channel 5 Transfer Complete flag /
		3439	#define DMA_ISR_HTIF5_Pos (18U)
		3440	#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /!< 0x00040000 /
		3441	#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /!< Channel 5 Half Transfer flag /
		3442	#define DMA_ISR_TEIF5_Pos (19U)
		3443	#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /!< 0x00080000 /
		3444	#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /!< Channel 5 Transfer Error flag /
		3445	#define DMA_ISR_GIF6_Pos (20U)
		3446	#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /!< 0x00100000 /
		3447	#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /!< Channel 6 Global interrupt flag /
		3448	#define DMA_ISR_TCIF6_Pos (21U)
		3449	#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /!< 0x00200000 /
		3450	#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /!< Channel 6 Transfer Complete flag /
		3451	#define DMA_ISR_HTIF6_Pos (22U)
		3452	#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /!< 0x00400000 /
		3453	#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /!< Channel 6 Half Transfer flag /
		3454	#define DMA_ISR_TEIF6_Pos (23U)
		3455	#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /!< 0x00800000 /
		3456	#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /!< Channel 6 Transfer Error flag /
		3457	#define DMA_ISR_GIF7_Pos (24U)
		3458	#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /!< 0x01000000 /
		3459	#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /!< Channel 7 Global interrupt flag /
		3460	#define DMA_ISR_TCIF7_Pos (25U)
		3461	#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /!< 0x02000000 /
		3462	#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /!< Channel 7 Transfer Complete flag /
		3463	#define DMA_ISR_HTIF7_Pos (26U)
		3464	#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /!< 0x04000000 /
		3465	#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /!< Channel 7 Half Transfer flag /
		3466	#define DMA_ISR_TEIF7_Pos (27U)
		3467	#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /!< 0x08000000 /
		3468	#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /!< Channel 7 Transfer Error flag /
		3469
		3470	/***************** Bit definition for DMA_IFCR register *****************/
		3471	#define DMA_IFCR_CGIF1_Pos (0U)
		3472	#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /!< 0x00000001 /
		3473	#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /!< Channel 1 Global interrupt clear /
		3474	#define DMA_IFCR_CTCIF1_Pos (1U)
		3475	#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /!< 0x00000002 /
		3476	#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /!< Channel 1 Transfer Complete clear /
		3477	#define DMA_IFCR_CHTIF1_Pos (2U)
		3478	#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /!< 0x00000004 /
		3479	#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /!< Channel 1 Half Transfer clear /
		3480	#define DMA_IFCR_CTEIF1_Pos (3U)
		3481	#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /!< 0x00000008 /
		3482	#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /!< Channel 1 Transfer Error clear /
		3483	#define DMA_IFCR_CGIF2_Pos (4U)
		3484	#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /!< 0x00000010 /
		3485	#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /!< Channel 2 Global interrupt clear /
		3486	#define DMA_IFCR_CTCIF2_Pos (5U)
		3487	#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /!< 0x00000020 /
		3488	#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /!< Channel 2 Transfer Complete clear /
		3489	#define DMA_IFCR_CHTIF2_Pos (6U)
		3490	#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /!< 0x00000040 /
		3491	#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /!< Channel 2 Half Transfer clear /
		3492	#define DMA_IFCR_CTEIF2_Pos (7U)
		3493	#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /!< 0x00000080 /
		3494	#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /!< Channel 2 Transfer Error clear /
		3495	#define DMA_IFCR_CGIF3_Pos (8U)
		3496	#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /!< 0x00000100 /
		3497	#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /!< Channel 3 Global interrupt clear /
		3498	#define DMA_IFCR_CTCIF3_Pos (9U)
		3499	#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /!< 0x00000200 /
		3500	#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /!< Channel 3 Transfer Complete clear /
		3501	#define DMA_IFCR_CHTIF3_Pos (10U)
		3502	#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /!< 0x00000400 /
		3503	#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /!< Channel 3 Half Transfer clear /
		3504	#define DMA_IFCR_CTEIF3_Pos (11U)
		3505	#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /!< 0x00000800 /
		3506	#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /!< Channel 3 Transfer Error clear /
		3507	#define DMA_IFCR_CGIF4_Pos (12U)
		3508	#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /!< 0x00001000 /
		3509	#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /!< Channel 4 Global interrupt clear /
		3510	#define DMA_IFCR_CTCIF4_Pos (13U)
		3511	#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /!< 0x00002000 /
		3512	#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /!< Channel 4 Transfer Complete clear /
		3513	#define DMA_IFCR_CHTIF4_Pos (14U)
		3514	#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /!< 0x00004000 /
		3515	#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /!< Channel 4 Half Transfer clear /
		3516	#define DMA_IFCR_CTEIF4_Pos (15U)
		3517	#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /!< 0x00008000 /
		3518	#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /!< Channel 4 Transfer Error clear /
		3519	#define DMA_IFCR_CGIF5_Pos (16U)
		3520	#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /!< 0x00010000 /
		3521	#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /!< Channel 5 Global interrupt clear /
		3522	#define DMA_IFCR_CTCIF5_Pos (17U)
		3523	#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /!< 0x00020000 /
		3524	#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /!< Channel 5 Transfer Complete clear /
		3525	#define DMA_IFCR_CHTIF5_Pos (18U)
		3526	#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /!< 0x00040000 /
		3527	#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /!< Channel 5 Half Transfer clear /
		3528	#define DMA_IFCR_CTEIF5_Pos (19U)
		3529	#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /!< 0x00080000 /
		3530	#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /!< Channel 5 Transfer Error clear /
		3531	#define DMA_IFCR_CGIF6_Pos (20U)
		3532	#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /!< 0x00100000 /
		3533	#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /!< Channel 6 Global interrupt clear /
		3534	#define DMA_IFCR_CTCIF6_Pos (21U)
		3535	#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /!< 0x00200000 /
		3536	#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /!< Channel 6 Transfer Complete clear /
		3537	#define DMA_IFCR_CHTIF6_Pos (22U)
		3538	#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /!< 0x00400000 /
		3539	#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /!< Channel 6 Half Transfer clear /
		3540	#define DMA_IFCR_CTEIF6_Pos (23U)
		3541	#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /!< 0x00800000 /
		3542	#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /!< Channel 6 Transfer Error clear /
		3543	#define DMA_IFCR_CGIF7_Pos (24U)
		3544	#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /!< 0x01000000 /
		3545	#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /!< Channel 7 Global interrupt clear /
		3546	#define DMA_IFCR_CTCIF7_Pos (25U)
		3547	#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /!< 0x02000000 /
		3548	#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /!< Channel 7 Transfer Complete clear /
		3549	#define DMA_IFCR_CHTIF7_Pos (26U)
		3550	#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /!< 0x04000000 /
		3551	#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /!< Channel 7 Half Transfer clear /
		3552	#define DMA_IFCR_CTEIF7_Pos (27U)
		3553	#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /!< 0x08000000 /
		3554	#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /!< Channel 7 Transfer Error clear /
		3555
		3556	/***************** Bit definition for DMA_CCR register *****************/
		3557	#define DMA_CCR_EN_Pos (0U)
		3558	#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /!< 0x00000001 /
		3559	#define DMA_CCR_EN DMA_CCR_EN_Msk /!< Channel enable /
		3560	#define DMA_CCR_TCIE_Pos (1U)
		3561	#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /!< 0x00000002 /
		3562	#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /!< Transfer complete interrupt enable /
		3563	#define DMA_CCR_HTIE_Pos (2U)
		3564	#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /!< 0x00000004 /
		3565	#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /!< Half Transfer interrupt enable /
		3566	#define DMA_CCR_TEIE_Pos (3U)
		3567	#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /!< 0x00000008 /
		3568	#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /!< Transfer error interrupt enable /
		3569	#define DMA_CCR_DIR_Pos (4U)
		3570	#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /!< 0x00000010 /
		3571	#define DMA_CCR_DIR DMA_CCR_DIR_Msk /!< Data transfer direction /
		3572	#define DMA_CCR_CIRC_Pos (5U)
		3573	#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /!< 0x00000020 /
		3574	#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /!< Circular mode /
		3575	#define DMA_CCR_PINC_Pos (6U)
		3576	#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /!< 0x00000040 /
		3577	#define DMA_CCR_PINC DMA_CCR_PINC_Msk /!< Peripheral increment mode /
		3578	#define DMA_CCR_MINC_Pos (7U)
		3579	#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /!< 0x00000080 /
		3580	#define DMA_CCR_MINC DMA_CCR_MINC_Msk /!< Memory increment mode /
		3581
		3582	#define DMA_CCR_PSIZE_Pos (8U)
		3583	#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /!< 0x00000300 /
		3584	#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /!< PSIZE[1:0] bits (Peripheral size) /
		3585	#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /!< 0x00000100 /
		3586	#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /!< 0x00000200 /
		3587
		3588	#define DMA_CCR_MSIZE_Pos (10U)
		3589	#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /!< 0x00000C00 /
		3590	#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /!< MSIZE[1:0] bits (Memory size) /
		3591	#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /!< 0x00000400 /
		3592	#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /!< 0x00000800 /
		3593
		3594	#define DMA_CCR_PL_Pos (12U)
		3595	#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /!< 0x00003000 /
		3596	#define DMA_CCR_PL DMA_CCR_PL_Msk /!< PL[1:0] bits(Channel Priority level) /
		3597	#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /!< 0x00001000 /
		3598	#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /!< 0x00002000 /
		3599
		3600	#define DMA_CCR_MEM2MEM_Pos (14U)
		3601	#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /!< 0x00004000 /
		3602	#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /!< Memory to memory mode /
		3603
		3604	/**************** Bit definition for DMA_CNDTR register ****************/
		3605	#define DMA_CNDTR_NDT_Pos (0U)
		3606	#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /!< 0x0000FFFF /
		3607	#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /!< Number of data to Transfer /
		3608
		3609	/**************** Bit definition for DMA_CPAR register *****************/
		3610	#define DMA_CPAR_PA_Pos (0U)
		3611	#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /!< 0xFFFFFFFF /
		3612	#define DMA_CPAR_PA DMA_CPAR_PA_Msk /!< Peripheral Address /
		3613
		3614	/**************** Bit definition for DMA_CMAR register *****************/
		3615	#define DMA_CMAR_MA_Pos (0U)
		3616	#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /!< 0xFFFFFFFF /
		3617	#define DMA_CMAR_MA DMA_CMAR_MA_Msk /!< Memory Address /
		3618
		3619	/******************************************************************************/
		3620	/* */
		3621	/* Analog to Digital Converter (ADC) */
		3622	/* */
		3623	/******************************************************************************/
		3624
		3625	/*
		3626	* @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
		3627	*/
		3628	/* Note: No specific macro feature on this device */
		3629
		3630	/****************** Bit definition for ADC_SR register ******************/
		3631	#define ADC_SR_AWD_Pos (0U)
		3632	#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /!< 0x00000001 /
		3633	#define ADC_SR_AWD ADC_SR_AWD_Msk /!< ADC analog watchdog 1 flag /
		3634	#define ADC_SR_EOS_Pos (1U)
		3635	#define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /!< 0x00000002 /
		3636	#define ADC_SR_EOS ADC_SR_EOS_Msk /!< ADC group regular end of sequence conversions flag /
		3637	#define ADC_SR_JEOS_Pos (2U)
		3638	#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /!< 0x00000004 /
		3639	#define ADC_SR_JEOS ADC_SR_JEOS_Msk /!< ADC group injected end of sequence conversions flag /
		3640	#define ADC_SR_JSTRT_Pos (3U)
		3641	#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /!< 0x00000008 /
		3642	#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /!< ADC group injected conversion start flag /
		3643	#define ADC_SR_STRT_Pos (4U)
		3644	#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /!< 0x00000010 /
		3645	#define ADC_SR_STRT ADC_SR_STRT_Msk /!< ADC group regular conversion start flag /
		3646
		3647	/* Legacy defines */
		3648	#define ADC_SR_EOC (ADC_SR_EOS)
		3649	#define ADC_SR_JEOC (ADC_SR_JEOS)
		3650
		3651	/***************** Bit definition for ADC_CR1 register ******************/
		3652	#define ADC_CR1_AWDCH_Pos (0U)
		3653	#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /!< 0x0000001F /
		3654	#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /!< ADC analog watchdog 1 monitored channel selection /
		3655	#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /!< 0x00000001 /
		3656	#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /!< 0x00000002 /
		3657	#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /!< 0x00000004 /
		3658	#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /!< 0x00000008 /
		3659	#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /!< 0x00000010 /
		3660
		3661	#define ADC_CR1_EOSIE_Pos (5U)
		3662	#define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /!< 0x00000020 /
		3663	#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /!< ADC group regular end of sequence conversions interrupt /
		3664	#define ADC_CR1_AWDIE_Pos (6U)
		3665	#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /!< 0x00000040 /
		3666	#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /!< ADC analog watchdog 1 interrupt /
		3667	#define ADC_CR1_JEOSIE_Pos (7U)
		3668	#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /!< 0x00000080 /
		3669	#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /!< ADC group injected end of sequence conversions interrupt /
		3670	#define ADC_CR1_SCAN_Pos (8U)
		3671	#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /!< 0x00000100 /
		3672	#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /!< ADC scan mode /
		3673	#define ADC_CR1_AWDSGL_Pos (9U)
		3674	#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /!< 0x00000200 /
		3675	#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /!< ADC analog watchdog 1 monitoring a single channel or all channels /
		3676	#define ADC_CR1_JAUTO_Pos (10U)
		3677	#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /!< 0x00000400 /
		3678	#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /!< ADC group injected automatic trigger mode /
		3679	#define ADC_CR1_DISCEN_Pos (11U)
		3680	#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /!< 0x00000800 /
		3681	#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /
		3682	#define ADC_CR1_JDISCEN_Pos (12U)
		3683	#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /!< 0x00001000 /
		3684	#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /!< ADC group injected sequencer discontinuous mode /
		3685
		3686	#define ADC_CR1_DISCNUM_Pos (13U)
		3687	#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /!< 0x0000E000 /
		3688	#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /!< ADC group regular sequencer discontinuous number of ranks /
		3689	#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /!< 0x00002000 /
		3690	#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /!< 0x00004000 /
		3691	#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /!< 0x00008000 /
		3692
		3693	#define ADC_CR1_JAWDEN_Pos (22U)
		3694	#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /!< 0x00400000 /
		3695	#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group injected /
		3696	#define ADC_CR1_AWDEN_Pos (23U)
		3697	#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /!< 0x00800000 /
		3698	#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group regular /
		3699
		3700	/* Legacy defines */
		3701	#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
		3702	#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
		3703
		3704	/***************** Bit definition for ADC_CR2 register ******************/
		3705	#define ADC_CR2_ADON_Pos (0U)
		3706	#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /!< 0x00000001 /
		3707	#define ADC_CR2_ADON ADC_CR2_ADON_Msk /!< ADC enable /
		3708	#define ADC_CR2_CONT_Pos (1U)
		3709	#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /!< 0x00000002 /
		3710	#define ADC_CR2_CONT ADC_CR2_CONT_Msk /!< ADC group regular continuous conversion mode /
		3711	#define ADC_CR2_CAL_Pos (2U)
		3712	#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /!< 0x00000004 /
		3713	#define ADC_CR2_CAL ADC_CR2_CAL_Msk /!< ADC calibration start /
		3714	#define ADC_CR2_RSTCAL_Pos (3U)
		3715	#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /!< 0x00000008 /
		3716	#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /!< ADC calibration reset /
		3717	#define ADC_CR2_DMA_Pos (8U)
		3718	#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /!< 0x00000100 /
		3719	#define ADC_CR2_DMA ADC_CR2_DMA_Msk /!< ADC DMA transfer enable /
		3720	#define ADC_CR2_ALIGN_Pos (11U)
		3721	#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /!< 0x00000800 /
		3722	#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /!< ADC data alignement /
		3723
		3724	#define ADC_CR2_JEXTSEL_Pos (12U)
		3725	#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00007000 /
		3726	#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /!< ADC group injected external trigger source /
		3727	#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00001000 /
		3728	#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00002000 /
		3729	#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00004000 /
		3730
		3731	#define ADC_CR2_JEXTTRIG_Pos (15U)
		3732	#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /!< 0x00008000 /
		3733	#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /!< ADC group injected external trigger enable /
		3734
		3735	#define ADC_CR2_EXTSEL_Pos (17U)
		3736	#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /!< 0x000E0000 /
		3737	#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /!< ADC group regular external trigger source /
		3738	#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /!< 0x00020000 /
		3739	#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /!< 0x00040000 /
		3740	#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /!< 0x00080000 /
		3741
		3742	#define ADC_CR2_EXTTRIG_Pos (20U)
		3743	#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /!< 0x00100000 /
		3744	#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /!< ADC group regular external trigger enable /
		3745	#define ADC_CR2_JSWSTART_Pos (21U)
		3746	#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /!< 0x00200000 /
		3747	#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /!< ADC group injected conversion start /
		3748	#define ADC_CR2_SWSTART_Pos (22U)
		3749	#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /!< 0x00400000 /
		3750	#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /!< ADC group regular conversion start /
		3751	#define ADC_CR2_TSVREFE_Pos (23U)
		3752	#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /!< 0x00800000 /
		3753	#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /!< ADC internal path to VrefInt and temperature sensor enable /
		3754
		3755	/**************** Bit definition for ADC_SMPR1 register *****************/
		3756	#define ADC_SMPR1_SMP10_Pos (0U)
		3757	#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /!< 0x00000007 /
		3758	#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /!< ADC channel 10 sampling time selection /
		3759	#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /!< 0x00000001 /
		3760	#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /!< 0x00000002 /
		3761	#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /!< 0x00000004 /
		3762
		3763	#define ADC_SMPR1_SMP11_Pos (3U)
		3764	#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /!< 0x00000038 /
		3765	#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /!< ADC channel 11 sampling time selection /
		3766	#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /!< 0x00000008 /
		3767	#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /!< 0x00000010 /
		3768	#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /!< 0x00000020 /
		3769
		3770	#define ADC_SMPR1_SMP12_Pos (6U)
		3771	#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /!< 0x000001C0 /
		3772	#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /!< ADC channel 12 sampling time selection /
		3773	#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /!< 0x00000040 /
		3774	#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /!< 0x00000080 /
		3775	#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /!< 0x00000100 /
		3776
		3777	#define ADC_SMPR1_SMP13_Pos (9U)
		3778	#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /!< 0x00000E00 /
		3779	#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /!< ADC channel 13 sampling time selection /
		3780	#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /!< 0x00000200 /
		3781	#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /!< 0x00000400 /
		3782	#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /!< 0x00000800 /
		3783
		3784	#define ADC_SMPR1_SMP14_Pos (12U)
		3785	#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /!< 0x00007000 /
		3786	#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /!< ADC channel 14 sampling time selection /
		3787	#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /!< 0x00001000 /
		3788	#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /!< 0x00002000 /
		3789	#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /!< 0x00004000 /
		3790
		3791	#define ADC_SMPR1_SMP15_Pos (15U)
		3792	#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /!< 0x00038000 /
		3793	#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /!< ADC channel 15 sampling time selection /
		3794	#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /!< 0x00008000 /
		3795	#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /!< 0x00010000 /
		3796	#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /!< 0x00020000 /
		3797
		3798	#define ADC_SMPR1_SMP16_Pos (18U)
		3799	#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /!< 0x001C0000 /
		3800	#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /!< ADC channel 16 sampling time selection /
		3801	#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /!< 0x00040000 /
		3802	#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /!< 0x00080000 /
		3803	#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /!< 0x00100000 /
		3804
		3805	#define ADC_SMPR1_SMP17_Pos (21U)
		3806	#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /!< 0x00E00000 /
		3807	#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /!< ADC channel 17 sampling time selection /
		3808	#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /!< 0x00200000 /
		3809	#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /!< 0x00400000 /
		3810	#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /!< 0x00800000 /
		3811
		3812	/**************** Bit definition for ADC_SMPR2 register *****************/
		3813	#define ADC_SMPR2_SMP0_Pos (0U)
		3814	#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /!< 0x00000007 /
		3815	#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /!< ADC channel 0 sampling time selection /
		3816	#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /!< 0x00000001 /
		3817	#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /!< 0x00000002 /
		3818	#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /!< 0x00000004 /
		3819
		3820	#define ADC_SMPR2_SMP1_Pos (3U)
		3821	#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /!< 0x00000038 /
		3822	#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /!< ADC channel 1 sampling time selection /
		3823	#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /!< 0x00000008 /
		3824	#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /!< 0x00000010 /
		3825	#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /!< 0x00000020 /
		3826
		3827	#define ADC_SMPR2_SMP2_Pos (6U)
		3828	#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /!< 0x000001C0 /
		3829	#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /!< ADC channel 2 sampling time selection /
		3830	#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /!< 0x00000040 /
		3831	#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /!< 0x00000080 /
		3832	#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /!< 0x00000100 /
		3833
		3834	#define ADC_SMPR2_SMP3_Pos (9U)
		3835	#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /!< 0x00000E00 /
		3836	#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /!< ADC channel 3 sampling time selection /
		3837	#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /!< 0x00000200 /
		3838	#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /!< 0x00000400 /
		3839	#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /!< 0x00000800 /
		3840
		3841	#define ADC_SMPR2_SMP4_Pos (12U)
		3842	#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /!< 0x00007000 /
		3843	#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /!< ADC channel 4 sampling time selection /
		3844	#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /!< 0x00001000 /
		3845	#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /!< 0x00002000 /
		3846	#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /!< 0x00004000 /
		3847
		3848	#define ADC_SMPR2_SMP5_Pos (15U)
		3849	#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /!< 0x00038000 /
		3850	#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /!< ADC channel 5 sampling time selection /
		3851	#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /!< 0x00008000 /
		3852	#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /!< 0x00010000 /
		3853	#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /!< 0x00020000 /
		3854
		3855	#define ADC_SMPR2_SMP6_Pos (18U)
		3856	#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /!< 0x001C0000 /
		3857	#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /!< ADC channel 6 sampling time selection /
		3858	#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /!< 0x00040000 /
		3859	#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /!< 0x00080000 /
		3860	#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /!< 0x00100000 /
		3861
		3862	#define ADC_SMPR2_SMP7_Pos (21U)
		3863	#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /!< 0x00E00000 /
		3864	#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /!< ADC channel 7 sampling time selection /
		3865	#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /!< 0x00200000 /
		3866	#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /!< 0x00400000 /
		3867	#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /!< 0x00800000 /
		3868
		3869	#define ADC_SMPR2_SMP8_Pos (24U)
		3870	#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /!< 0x07000000 /
		3871	#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /!< ADC channel 8 sampling time selection /
		3872	#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /!< 0x01000000 /
		3873	#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /!< 0x02000000 /
		3874	#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /!< 0x04000000 /
		3875
		3876	#define ADC_SMPR2_SMP9_Pos (27U)
		3877	#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /!< 0x38000000 /
		3878	#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /!< ADC channel 9 sampling time selection /
		3879	#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /!< 0x08000000 /
		3880	#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /!< 0x10000000 /
		3881	#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /!< 0x20000000 /
		3882
		3883	/**************** Bit definition for ADC_JOFR1 register *****************/
		3884	#define ADC_JOFR1_JOFFSET1_Pos (0U)
		3885	#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /!< 0x00000FFF /
		3886	#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /!< ADC group injected sequencer rank 1 offset value /
		3887
		3888	/**************** Bit definition for ADC_JOFR2 register *****************/
		3889	#define ADC_JOFR2_JOFFSET2_Pos (0U)
		3890	#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /!< 0x00000FFF /
		3891	#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /!< ADC group injected sequencer rank 2 offset value /
		3892
		3893	/**************** Bit definition for ADC_JOFR3 register *****************/
		3894	#define ADC_JOFR3_JOFFSET3_Pos (0U)
		3895	#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /!< 0x00000FFF /
		3896	#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /!< ADC group injected sequencer rank 3 offset value /
		3897
		3898	/**************** Bit definition for ADC_JOFR4 register *****************/
		3899	#define ADC_JOFR4_JOFFSET4_Pos (0U)
		3900	#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /!< 0x00000FFF /
		3901	#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /!< ADC group injected sequencer rank 4 offset value /
		3902
		3903	/***************** Bit definition for ADC_HTR register ******************/
		3904	#define ADC_HTR_HT_Pos (0U)
		3905	#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /!< 0x00000FFF /
		3906	#define ADC_HTR_HT ADC_HTR_HT_Msk /!< ADC analog watchdog 1 threshold high /
		3907
		3908	/***************** Bit definition for ADC_LTR register ******************/
		3909	#define ADC_LTR_LT_Pos (0U)
		3910	#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /!< 0x00000FFF /
		3911	#define ADC_LTR_LT ADC_LTR_LT_Msk /!< ADC analog watchdog 1 threshold low /
		3912
		3913	/***************** Bit definition for ADC_SQR1 register *****************/
		3914	#define ADC_SQR1_SQ13_Pos (0U)
		3915	#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /!< 0x0000001F /
		3916	#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /!< ADC group regular sequencer rank 13 /
		3917	#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /!< 0x00000001 /
		3918	#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /!< 0x00000002 /
		3919	#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /!< 0x00000004 /
		3920	#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /!< 0x00000008 /
		3921	#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /!< 0x00000010 /
		3922
		3923	#define ADC_SQR1_SQ14_Pos (5U)
		3924	#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /!< 0x000003E0 /
		3925	#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /!< ADC group regular sequencer rank 14 /
		3926	#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /!< 0x00000020 /
		3927	#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /!< 0x00000040 /
		3928	#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /!< 0x00000080 /
		3929	#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /!< 0x00000100 /
		3930	#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /!< 0x00000200 /
		3931
		3932	#define ADC_SQR1_SQ15_Pos (10U)
		3933	#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /!< 0x00007C00 /
		3934	#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /!< ADC group regular sequencer rank 15 /
		3935	#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /!< 0x00000400 /
		3936	#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /!< 0x00000800 /
		3937	#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /!< 0x00001000 /
		3938	#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /!< 0x00002000 /
		3939	#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /!< 0x00004000 /
		3940
		3941	#define ADC_SQR1_SQ16_Pos (15U)
		3942	#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /!< 0x000F8000 /
		3943	#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /!< ADC group regular sequencer rank 16 /
		3944	#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /!< 0x00008000 /
		3945	#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /!< 0x00010000 /
		3946	#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /!< 0x00020000 /
		3947	#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /!< 0x00040000 /
		3948	#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /!< 0x00080000 /
		3949
		3950	#define ADC_SQR1_L_Pos (20U)
		3951	#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /!< 0x00F00000 /
		3952	#define ADC_SQR1_L ADC_SQR1_L_Msk /!< ADC group regular sequencer scan length /
		3953	#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /!< 0x00100000 /
		3954	#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /!< 0x00200000 /
		3955	#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /!< 0x00400000 /
		3956	#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /!< 0x00800000 /
		3957
		3958	/***************** Bit definition for ADC_SQR2 register *****************/
		3959	#define ADC_SQR2_SQ7_Pos (0U)
		3960	#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /!< 0x0000001F /
		3961	#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /!< ADC group regular sequencer rank 7 /
		3962	#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /!< 0x00000001 /
		3963	#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /!< 0x00000002 /
		3964	#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /!< 0x00000004 /
		3965	#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /!< 0x00000008 /
		3966	#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /!< 0x00000010 /
		3967
		3968	#define ADC_SQR2_SQ8_Pos (5U)
		3969	#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /!< 0x000003E0 /
		3970	#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /!< ADC group regular sequencer rank 8 /
		3971	#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /!< 0x00000020 /
		3972	#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /!< 0x00000040 /
		3973	#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /!< 0x00000080 /
		3974	#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /!< 0x00000100 /
		3975	#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /!< 0x00000200 /
		3976
		3977	#define ADC_SQR2_SQ9_Pos (10U)
		3978	#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /!< 0x00007C00 /
		3979	#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /!< ADC group regular sequencer rank 9 /
		3980	#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /!< 0x00000400 /
		3981	#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /!< 0x00000800 /
		3982	#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /!< 0x00001000 /
		3983	#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /!< 0x00002000 /
		3984	#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /!< 0x00004000 /
		3985
		3986	#define ADC_SQR2_SQ10_Pos (15U)
		3987	#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /!< 0x000F8000 /
		3988	#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /!< ADC group regular sequencer rank 10 /
		3989	#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /!< 0x00008000 /
		3990	#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /!< 0x00010000 /
		3991	#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /!< 0x00020000 /
		3992	#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /!< 0x00040000 /
		3993	#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /!< 0x00080000 /
		3994
		3995	#define ADC_SQR2_SQ11_Pos (20U)
		3996	#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /!< 0x01F00000 /
		3997	#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /!< ADC group regular sequencer rank 1 /
		3998	#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /!< 0x00100000 /
		3999	#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /!< 0x00200000 /
		4000	#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /!< 0x00400000 /
		4001	#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /!< 0x00800000 /
		4002	#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /!< 0x01000000 /
		4003
		4004	#define ADC_SQR2_SQ12_Pos (25U)
		4005	#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /!< 0x3E000000 /
		4006	#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /!< ADC group regular sequencer rank 12 /
		4007	#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /!< 0x02000000 /
		4008	#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /!< 0x04000000 /
		4009	#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /!< 0x08000000 /
		4010	#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /!< 0x10000000 /
		4011	#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /!< 0x20000000 /
		4012
		4013	/***************** Bit definition for ADC_SQR3 register *****************/
		4014	#define ADC_SQR3_SQ1_Pos (0U)
		4015	#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /!< 0x0000001F /
		4016	#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /!< ADC group regular sequencer rank 1 /
		4017	#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /!< 0x00000001 /
		4018	#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /!< 0x00000002 /
		4019	#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /!< 0x00000004 /
		4020	#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /!< 0x00000008 /
		4021	#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /!< 0x00000010 /
		4022
		4023	#define ADC_SQR3_SQ2_Pos (5U)
		4024	#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /!< 0x000003E0 /
		4025	#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /!< ADC group regular sequencer rank 2 /
		4026	#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /!< 0x00000020 /
		4027	#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /!< 0x00000040 /
		4028	#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /!< 0x00000080 /
		4029	#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /!< 0x00000100 /
		4030	#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /!< 0x00000200 /
		4031
		4032	#define ADC_SQR3_SQ3_Pos (10U)
		4033	#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /!< 0x00007C00 /
		4034	#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /!< ADC group regular sequencer rank 3 /
		4035	#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /!< 0x00000400 /
		4036	#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /!< 0x00000800 /
		4037	#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /!< 0x00001000 /
		4038	#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /!< 0x00002000 /
		4039	#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /!< 0x00004000 /
		4040
		4041	#define ADC_SQR3_SQ4_Pos (15U)
		4042	#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /!< 0x000F8000 /
		4043	#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /!< ADC group regular sequencer rank 4 /
		4044	#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /!< 0x00008000 /
		4045	#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /!< 0x00010000 /
		4046	#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /!< 0x00020000 /
		4047	#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /!< 0x00040000 /
		4048	#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /!< 0x00080000 /
		4049
		4050	#define ADC_SQR3_SQ5_Pos (20U)
		4051	#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /!< 0x01F00000 /
		4052	#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /!< ADC group regular sequencer rank 5 /
		4053	#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /!< 0x00100000 /
		4054	#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /!< 0x00200000 /
		4055	#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /!< 0x00400000 /
		4056	#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /!< 0x00800000 /
		4057	#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /!< 0x01000000 /
		4058
		4059	#define ADC_SQR3_SQ6_Pos (25U)
		4060	#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /!< 0x3E000000 /
		4061	#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /!< ADC group regular sequencer rank 6 /
		4062	#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /!< 0x02000000 /
		4063	#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /!< 0x04000000 /
		4064	#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /!< 0x08000000 /
		4065	#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /!< 0x10000000 /
		4066	#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /!< 0x20000000 /
		4067
		4068	/***************** Bit definition for ADC_JSQR register *****************/
		4069	#define ADC_JSQR_JSQ1_Pos (0U)
		4070	#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /!< 0x0000001F /
		4071	#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /!< ADC group injected sequencer rank 1 /
		4072	#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000001 /
		4073	#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000002 /
		4074	#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000004 /
		4075	#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000008 /
		4076	#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000010 /
		4077
		4078	#define ADC_JSQR_JSQ2_Pos (5U)
		4079	#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /!< 0x000003E0 /
		4080	#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /!< ADC group injected sequencer rank 2 /
		4081	#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000020 /
		4082	#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000040 /
		4083	#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000080 /
		4084	#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000100 /
		4085	#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000200 /
		4086
		4087	#define ADC_JSQR_JSQ3_Pos (10U)
		4088	#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /!< 0x00007C00 /
		4089	#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /!< ADC group injected sequencer rank 3 /
		4090	#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /!< 0x00000400 /
		4091	#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /!< 0x00000800 /
		4092	#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /!< 0x00001000 /
		4093	#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /!< 0x00002000 /
		4094	#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /!< 0x00004000 /
		4095
		4096	#define ADC_JSQR_JSQ4_Pos (15U)
		4097	#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /!< 0x000F8000 /
		4098	#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /!< ADC group injected sequencer rank 4 /
		4099	#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /!< 0x00008000 /
		4100	#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /!< 0x00010000 /
		4101	#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /!< 0x00020000 /
		4102	#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /!< 0x00040000 /
		4103	#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /!< 0x00080000 /
		4104
		4105	#define ADC_JSQR_JL_Pos (20U)
		4106	#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /!< 0x00300000 /
		4107	#define ADC_JSQR_JL ADC_JSQR_JL_Msk /!< ADC group injected sequencer scan length /
		4108	#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /!< 0x00100000 /
		4109	#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /!< 0x00200000 /
		4110
		4111	/***************** Bit definition for ADC_JDR1 register *****************/
		4112	#define ADC_JDR1_JDATA_Pos (0U)
		4113	#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /!< 0x0000FFFF /
		4114	#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /!< ADC group injected sequencer rank 1 conversion data /
		4115
		4116	/***************** Bit definition for ADC_JDR2 register *****************/
		4117	#define ADC_JDR2_JDATA_Pos (0U)
		4118	#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /!< 0x0000FFFF /
		4119	#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /!< ADC group injected sequencer rank 2 conversion data /
		4120
		4121	/***************** Bit definition for ADC_JDR3 register *****************/
		4122	#define ADC_JDR3_JDATA_Pos (0U)
		4123	#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /!< 0x0000FFFF /
		4124	#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /!< ADC group injected sequencer rank 3 conversion data /
		4125
		4126	/***************** Bit definition for ADC_JDR4 register *****************/
		4127	#define ADC_JDR4_JDATA_Pos (0U)
		4128	#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /!< 0x0000FFFF /
		4129	#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /!< ADC group injected sequencer rank 4 conversion data /
		4130
		4131	/****************** Bit definition for ADC_DR register ******************/
		4132	#define ADC_DR_DATA_Pos (0U)
		4133	#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /!< 0x0000FFFF /
		4134	#define ADC_DR_DATA ADC_DR_DATA_Msk /!< ADC group regular conversion data /
		4135	/******************************************************************************/
		4136	/* */
		4137	/* Digital to Analog Converter */
		4138	/* */
		4139	/******************************************************************************/
		4140
		4141	/****************** Bit definition for DAC_CR register ******************/
		4142	#define DAC_CR_EN1_Pos (0U)
		4143	#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /!< 0x00000001 /
		4144	#define DAC_CR_EN1 DAC_CR_EN1_Msk /!< DAC channel1 enable /
		4145	#define DAC_CR_BOFF1_Pos (1U)
		4146	#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /!< 0x00000002 /
		4147	#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /!< DAC channel1 output buffer disable /
		4148	#define DAC_CR_TEN1_Pos (2U)
		4149	#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /!< 0x00000004 /
		4150	#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /!< DAC channel1 Trigger enable /
		4151
		4152	#define DAC_CR_TSEL1_Pos (3U)
		4153	#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /!< 0x00000038 /
		4154	#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
		4155	#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /!< 0x00000008 /
		4156	#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /!< 0x00000010 /
		4157	#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /!< 0x00000020 /
		4158
		4159	#define DAC_CR_WAVE1_Pos (6U)
		4160	#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /!< 0x000000C0 /
		4161	#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
		4162	#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /!< 0x00000040 /
		4163	#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /!< 0x00000080 /
		4164
		4165	#define DAC_CR_MAMP1_Pos (8U)
		4166	#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /!< 0x00000F00 /
		4167	#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
		4168	#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /!< 0x00000100 /
		4169	#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /!< 0x00000200 /
		4170	#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /!< 0x00000400 /
		4171	#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /!< 0x00000800 /
		4172
		4173	#define DAC_CR_DMAEN1_Pos (12U)
		4174	#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /!< 0x00001000 /
		4175	#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /!< DAC channel1 DMA enable /
		4176	#define DAC_CR_EN2_Pos (16U)
		4177	#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /!< 0x00010000 /
		4178	#define DAC_CR_EN2 DAC_CR_EN2_Msk /!< DAC channel2 enable /
		4179	#define DAC_CR_BOFF2_Pos (17U)
		4180	#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /!< 0x00020000 /
		4181	#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /!< DAC channel2 output buffer disable /
		4182	#define DAC_CR_TEN2_Pos (18U)
		4183	#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /!< 0x00040000 /
		4184	#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /!< DAC channel2 Trigger enable /
		4185
		4186	#define DAC_CR_TSEL2_Pos (19U)
		4187	#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /!< 0x00380000 /
		4188	#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
		4189	#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /!< 0x00080000 /
		4190	#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /!< 0x00100000 /
		4191	#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /!< 0x00200000 /
		4192
		4193	#define DAC_CR_WAVE2_Pos (22U)
		4194	#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /!< 0x00C00000 /
		4195	#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
		4196	#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /!< 0x00400000 /
		4197	#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /!< 0x00800000 /
		4198
		4199	#define DAC_CR_MAMP2_Pos (24U)
		4200	#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /!< 0x0F000000 /
		4201	#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
		4202	#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /!< 0x01000000 /
		4203	#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /!< 0x02000000 /
		4204	#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /!< 0x04000000 /
		4205	#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /!< 0x08000000 /
		4206
		4207	#define DAC_CR_DMAEN2_Pos (28U)
		4208	#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /!< 0x10000000 /
		4209	#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /!< DAC channel2 DMA enabled /
		4210
		4211	#define DAC_CR_DMAUDRIE1_Pos (13U)
		4212	#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /!< 0x00002000 /
		4213	#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /!< DAC channel1 DMA underrun interrupt enable /
		4214	#define DAC_CR_DMAUDRIE2_Pos (29U)
		4215	#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /!< 0x20000000 /
		4216	#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /!< DAC channel2 DMA underrun interrupt enable /
		4217
		4218	/*************** Bit definition for DAC_SWTRIGR register ****************/
		4219	#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
		4220	#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /!< 0x00000001 /
		4221	#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /!< DAC channel1 software trigger /
		4222	#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
		4223	#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /!< 0x00000002 /
		4224	#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /!< DAC channel2 software trigger /
		4225
		4226	/*************** Bit definition for DAC_DHR12R1 register ****************/
		4227	#define DAC_DHR12R1_DACC1DHR_Pos (0U)
		4228	#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /!< 0x00000FFF /
		4229	#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /!< DAC channel1 12-bit Right aligned data /
		4230
		4231	/*************** Bit definition for DAC_DHR12L1 register ****************/
		4232	#define DAC_DHR12L1_DACC1DHR_Pos (4U)
		4233	#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /!< 0x0000FFF0 /
		4234	#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /!< DAC channel1 12-bit Left aligned data /
		4235
		4236	/**************** Bit definition for DAC_DHR8R1 register ****************/
		4237	#define DAC_DHR8R1_DACC1DHR_Pos (0U)
		4238	#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /!< 0x000000FF /
		4239	#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /!< DAC channel1 8-bit Right aligned data /
		4240
		4241	/*************** Bit definition for DAC_DHR12R2 register ****************/
		4242	#define DAC_DHR12R2_DACC2DHR_Pos (0U)
		4243	#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /!< 0x00000FFF /
		4244	#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /!< DAC channel2 12-bit Right aligned data /
		4245
		4246	/*************** Bit definition for DAC_DHR12L2 register ****************/
		4247	#define DAC_DHR12L2_DACC2DHR_Pos (4U)
		4248	#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /!< 0x0000FFF0 /
		4249	#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /!< DAC channel2 12-bit Left aligned data /
		4250
		4251	/**************** Bit definition for DAC_DHR8R2 register ****************/
		4252	#define DAC_DHR8R2_DACC2DHR_Pos (0U)
		4253	#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /!< 0x000000FF /
		4254	#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /!< DAC channel2 8-bit Right aligned data /
		4255
		4256	/*************** Bit definition for DAC_DHR12RD register ****************/
		4257	#define DAC_DHR12RD_DACC1DHR_Pos (0U)
		4258	#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /!< 0x00000FFF /
		4259	#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /!< DAC channel1 12-bit Right aligned data /
		4260	#define DAC_DHR12RD_DACC2DHR_Pos (16U)
		4261	#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /!< 0x0FFF0000 /
		4262	#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /!< DAC channel2 12-bit Right aligned data /
		4263
		4264	/*************** Bit definition for DAC_DHR12LD register ****************/
		4265	#define DAC_DHR12LD_DACC1DHR_Pos (4U)
		4266	#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /!< 0x0000FFF0 /
		4267	#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /!< DAC channel1 12-bit Left aligned data /
		4268	#define DAC_DHR12LD_DACC2DHR_Pos (20U)
		4269	#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /!< 0xFFF00000 /
		4270	#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /!< DAC channel2 12-bit Left aligned data /
		4271
		4272	/**************** Bit definition for DAC_DHR8RD register ****************/
		4273	#define DAC_DHR8RD_DACC1DHR_Pos (0U)
		4274	#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /!< 0x000000FF /
		4275	#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /!< DAC channel1 8-bit Right aligned data /
		4276	#define DAC_DHR8RD_DACC2DHR_Pos (8U)
		4277	#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /!< 0x0000FF00 /
		4278	#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /!< DAC channel2 8-bit Right aligned data /
		4279
		4280	/***************** Bit definition for DAC_DOR1 register *****************/
		4281	#define DAC_DOR1_DACC1DOR_Pos (0U)
		4282	#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /!< 0x00000FFF /
		4283	#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /!< DAC channel1 data output /
		4284
		4285	/***************** Bit definition for DAC_DOR2 register *****************/
		4286	#define DAC_DOR2_DACC2DOR_Pos (0U)
		4287	#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /!< 0x00000FFF /
		4288	#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /!< DAC channel2 data output /
		4289
		4290	/****************** Bit definition for DAC_SR register ******************/
		4291	#define DAC_SR_DMAUDR1_Pos (13U)
		4292	#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /!< 0x00002000 /
		4293	#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /!< DAC channel1 DMA underrun flag /
		4294	#define DAC_SR_DMAUDR2_Pos (29U)
		4295	#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /!< 0x20000000 /
		4296	#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /!< DAC channel2 DMA underrun flag /
		4297
		4298	/******************************************************************************/
		4299	/* */
		4300	/* CEC */
		4301	/* */
		4302	/******************************************************************************/
		4303	/****************** Bit definition for CEC_CFGR register ****************/
		4304	#define CEC_CFGR_PE_Pos (0U)
		4305	#define CEC_CFGR_PE_Msk (0x1UL << CEC_CFGR_PE_Pos) /!< 0x00000001 /
		4306	#define CEC_CFGR_PE CEC_CFGR_PE_Msk /!< Peripheral Enable /
		4307	#define CEC_CFGR_IE_Pos (1U)
		4308	#define CEC_CFGR_IE_Msk (0x1UL << CEC_CFGR_IE_Pos) /!< 0x00000002 /
		4309	#define CEC_CFGR_IE CEC_CFGR_IE_Msk /!< Interrupt Enable /
		4310	#define CEC_CFGR_BTEM_Pos (2U)
		4311	#define CEC_CFGR_BTEM_Msk (0x1UL << CEC_CFGR_BTEM_Pos) /!< 0x00000004 /
		4312	#define CEC_CFGR_BTEM CEC_CFGR_BTEM_Msk /!< Bit Timing Error Mode /
		4313	#define CEC_CFGR_BPEM_Pos (3U)
		4314	#define CEC_CFGR_BPEM_Msk (0x1UL << CEC_CFGR_BPEM_Pos) /!< 0x00000008 /
		4315	#define CEC_CFGR_BPEM CEC_CFGR_BPEM_Msk /!< Bit Period Error Mode /
		4316
		4317	/****************** Bit definition for CEC_OAR register ****************/
		4318	#define CEC_OAR_OA_Pos (0U)
		4319	#define CEC_OAR_OA_Msk (0xFUL << CEC_OAR_OA_Pos) /!< 0x0000000F /
		4320	#define CEC_OAR_OA CEC_OAR_OA_Msk /!< OA[3:0]: Own Address /
		4321	#define CEC_OAR_OA_0 (0x1UL << CEC_OAR_OA_Pos) /!< 0x00000001 /
		4322	#define CEC_OAR_OA_1 (0x2UL << CEC_OAR_OA_Pos) /!< 0x00000002 /
		4323	#define CEC_OAR_OA_2 (0x4UL << CEC_OAR_OA_Pos) /!< 0x00000004 /
		4324	#define CEC_OAR_OA_3 (0x8UL << CEC_OAR_OA_Pos) /!< 0x00000008 /
		4325
		4326	/****************** Bit definition for CEC_PRES register ****************/
		4327	#define CEC_PRES_PRES_Pos (0U)
		4328	#define CEC_PRES_PRES_Msk (0x3FFFUL << CEC_PRES_PRES_Pos) /!< 0x00003FFF /
		4329	#define CEC_PRES_PRES CEC_PRES_PRES_Msk /!< Prescaler Counter Value /
		4330
		4331	/****************** Bit definition for CEC_ESR register ****************/
		4332	#define CEC_ESR_BTE_Pos (0U)
		4333	#define CEC_ESR_BTE_Msk (0x1UL << CEC_ESR_BTE_Pos) /!< 0x00000001 /
		4334	#define CEC_ESR_BTE CEC_ESR_BTE_Msk /!< Bit Timing Error /
		4335	#define CEC_ESR_BPE_Pos (1U)
		4336	#define CEC_ESR_BPE_Msk (0x1UL << CEC_ESR_BPE_Pos) /!< 0x00000002 /
		4337	#define CEC_ESR_BPE CEC_ESR_BPE_Msk /!< Bit Period Error /
		4338	#define CEC_ESR_RBTFE_Pos (2U)
		4339	#define CEC_ESR_RBTFE_Msk (0x1UL << CEC_ESR_RBTFE_Pos) /!< 0x00000004 /
		4340	#define CEC_ESR_RBTFE CEC_ESR_RBTFE_Msk /!< Rx Block Transfer Finished Error /
		4341	#define CEC_ESR_SBE_Pos (3U)
		4342	#define CEC_ESR_SBE_Msk (0x1UL << CEC_ESR_SBE_Pos) /!< 0x00000008 /
		4343	#define CEC_ESR_SBE CEC_ESR_SBE_Msk /!< Start Bit Error /
		4344	#define CEC_ESR_ACKE_Pos (4U)
		4345	#define CEC_ESR_ACKE_Msk (0x1UL << CEC_ESR_ACKE_Pos) /!< 0x00000010 /
		4346	#define CEC_ESR_ACKE CEC_ESR_ACKE_Msk /!< Block Acknowledge Error /
		4347	#define CEC_ESR_LINE_Pos (5U)
		4348	#define CEC_ESR_LINE_Msk (0x1UL << CEC_ESR_LINE_Pos) /!< 0x00000020 /
		4349	#define CEC_ESR_LINE CEC_ESR_LINE_Msk /!< Line Error /
		4350	#define CEC_ESR_TBTFE_Pos (6U)
		4351	#define CEC_ESR_TBTFE_Msk (0x1UL << CEC_ESR_TBTFE_Pos) /!< 0x00000040 /
		4352	#define CEC_ESR_TBTFE CEC_ESR_TBTFE_Msk /!< Tx Block Transfer Finished Error /
		4353
		4354	/****************** Bit definition for CEC_CSR register ****************/
		4355	#define CEC_CSR_TSOM_Pos (0U)
		4356	#define CEC_CSR_TSOM_Msk (0x1UL << CEC_CSR_TSOM_Pos) /!< 0x00000001 /
		4357	#define CEC_CSR_TSOM CEC_CSR_TSOM_Msk /!< Tx Start Of Message /
		4358	#define CEC_CSR_TEOM_Pos (1U)
		4359	#define CEC_CSR_TEOM_Msk (0x1UL << CEC_CSR_TEOM_Pos) /!< 0x00000002 /
		4360	#define CEC_CSR_TEOM CEC_CSR_TEOM_Msk /!< Tx End Of Message /
		4361	#define CEC_CSR_TERR_Pos (2U)
		4362	#define CEC_CSR_TERR_Msk (0x1UL << CEC_CSR_TERR_Pos) /!< 0x00000004 /
		4363	#define CEC_CSR_TERR CEC_CSR_TERR_Msk /!< Tx Error /
		4364	#define CEC_CSR_TBTRF_Pos (3U)
		4365	#define CEC_CSR_TBTRF_Msk (0x1UL << CEC_CSR_TBTRF_Pos) /!< 0x00000008 /
		4366	#define CEC_CSR_TBTRF CEC_CSR_TBTRF_Msk /!< Tx Byte Transfer Request or Block Transfer Finished /
		4367	#define CEC_CSR_RSOM_Pos (4U)
		4368	#define CEC_CSR_RSOM_Msk (0x1UL << CEC_CSR_RSOM_Pos) /!< 0x00000010 /
		4369	#define CEC_CSR_RSOM CEC_CSR_RSOM_Msk /!< Rx Start Of Message /
		4370	#define CEC_CSR_REOM_Pos (5U)
		4371	#define CEC_CSR_REOM_Msk (0x1UL << CEC_CSR_REOM_Pos) /!< 0x00000020 /
		4372	#define CEC_CSR_REOM CEC_CSR_REOM_Msk /!< Rx End Of Message /
		4373	#define CEC_CSR_RERR_Pos (6U)
		4374	#define CEC_CSR_RERR_Msk (0x1UL << CEC_CSR_RERR_Pos) /!< 0x00000040 /
		4375	#define CEC_CSR_RERR CEC_CSR_RERR_Msk /!< Rx Error /
		4376	#define CEC_CSR_RBTF_Pos (7U)
		4377	#define CEC_CSR_RBTF_Msk (0x1UL << CEC_CSR_RBTF_Pos) /!< 0x00000080 /
		4378	#define CEC_CSR_RBTF CEC_CSR_RBTF_Msk /!< Rx Block Transfer Finished /
		4379
		4380	/****************** Bit definition for CEC_TXD register ****************/
		4381	#define CEC_TXD_TXD_Pos (0U)
		4382	#define CEC_TXD_TXD_Msk (0xFFUL << CEC_TXD_TXD_Pos) /!< 0x000000FF /
		4383	#define CEC_TXD_TXD CEC_TXD_TXD_Msk /!< Tx Data register /
		4384
		4385	/****************** Bit definition for CEC_RXD register ****************/
		4386	#define CEC_RXD_RXD_Pos (0U)
		4387	#define CEC_RXD_RXD_Msk (0xFFUL << CEC_RXD_RXD_Pos) /!< 0x000000FF /
		4388	#define CEC_RXD_RXD CEC_RXD_RXD_Msk /!< Rx Data register /
		4389
		4390	/*****************************************************************************/
		4391	/* */
		4392	/* Timers (TIM) */
		4393	/* */
		4394	/*****************************************************************************/
		4395	/***************** Bit definition for TIM_CR1 register *****************/
		4396	#define TIM_CR1_CEN_Pos (0U)
		4397	#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /!< 0x00000001 /
		4398	#define TIM_CR1_CEN TIM_CR1_CEN_Msk /!<Counter enable /
		4399	#define TIM_CR1_UDIS_Pos (1U)
		4400	#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /!< 0x00000002 /
		4401	#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /!<Update disable /
		4402	#define TIM_CR1_URS_Pos (2U)
		4403	#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /!< 0x00000004 /
		4404	#define TIM_CR1_URS TIM_CR1_URS_Msk /!<Update request source /
		4405	#define TIM_CR1_OPM_Pos (3U)
		4406	#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /!< 0x00000008 /
		4407	#define TIM_CR1_OPM TIM_CR1_OPM_Msk /!<One pulse mode /
		4408	#define TIM_CR1_DIR_Pos (4U)
		4409	#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /!< 0x00000010 /
		4410	#define TIM_CR1_DIR TIM_CR1_DIR_Msk /!<Direction /
		4411
		4412	#define TIM_CR1_CMS_Pos (5U)
		4413	#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /!< 0x00000060 /
		4414	#define TIM_CR1_CMS TIM_CR1_CMS_Msk /!<CMS[1:0] bits (Center-aligned mode selection) /
		4415	#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /!< 0x00000020 /
		4416	#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /!< 0x00000040 /
		4417
		4418	#define TIM_CR1_ARPE_Pos (7U)
		4419	#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /!< 0x00000080 /
		4420	#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /!<Auto-reload preload enable /
		4421
		4422	#define TIM_CR1_CKD_Pos (8U)
		4423	#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /!< 0x00000300 /
		4424	#define TIM_CR1_CKD TIM_CR1_CKD_Msk /!<CKD[1:0] bits (clock division) /
		4425	#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /!< 0x00000100 /
		4426	#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /!< 0x00000200 /
		4427
		4428	/***************** Bit definition for TIM_CR2 register *****************/
		4429	#define TIM_CR2_CCPC_Pos (0U)
		4430	#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /!< 0x00000001 /
		4431	#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /!<Capture/Compare Preloaded Control /
		4432	#define TIM_CR2_CCUS_Pos (2U)
		4433	#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /!< 0x00000004 /
		4434	#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /!<Capture/Compare Control Update Selection /
		4435	#define TIM_CR2_CCDS_Pos (3U)
		4436	#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /!< 0x00000008 /
		4437	#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /!<Capture/Compare DMA Selection /
		4438
		4439	#define TIM_CR2_MMS_Pos (4U)
		4440	#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /!< 0x00000070 /
		4441	#define TIM_CR2_MMS TIM_CR2_MMS_Msk /!<MMS[2:0] bits (Master Mode Selection) /
		4442	#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /!< 0x00000010 /
		4443	#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /!< 0x00000020 /
		4444	#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /!< 0x00000040 /
		4445
		4446	#define TIM_CR2_TI1S_Pos (7U)
		4447	#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /!< 0x00000080 /
		4448	#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /!<TI1 Selection /
		4449	#define TIM_CR2_OIS1_Pos (8U)
		4450	#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /!< 0x00000100 /
		4451	#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /!<Output Idle state 1 (OC1 output) /
		4452	#define TIM_CR2_OIS1N_Pos (9U)
		4453	#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /!< 0x00000200 /
		4454	#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /!<Output Idle state 1 (OC1N output) /
		4455	#define TIM_CR2_OIS2_Pos (10U)
		4456	#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /!< 0x00000400 /
		4457	#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /!<Output Idle state 2 (OC2 output) /
		4458	#define TIM_CR2_OIS2N_Pos (11U)
		4459	#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /!< 0x00000800 /
		4460	#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /!<Output Idle state 2 (OC2N output) /
		4461	#define TIM_CR2_OIS3_Pos (12U)
		4462	#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /!< 0x00001000 /
		4463	#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /!<Output Idle state 3 (OC3 output) /
		4464	#define TIM_CR2_OIS3N_Pos (13U)
		4465	#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /!< 0x00002000 /
		4466	#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /!<Output Idle state 3 (OC3N output) /
		4467	#define TIM_CR2_OIS4_Pos (14U)
		4468	#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /!< 0x00004000 /
		4469	#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /!<Output Idle state 4 (OC4 output) /
		4470
		4471	/***************** Bit definition for TIM_SMCR register ****************/
		4472	#define TIM_SMCR_SMS_Pos (0U)
		4473	#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /!< 0x00000007 /
		4474	#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /!<SMS[2:0] bits (Slave mode selection) /
		4475	#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /!< 0x00000001 /
		4476	#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /!< 0x00000002 /
		4477	#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /!< 0x00000004 /
		4478
		4479	#define TIM_SMCR_TS_Pos (4U)
		4480	#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /!< 0x00000070 /
		4481	#define TIM_SMCR_TS TIM_SMCR_TS_Msk /!<TS[2:0] bits (Trigger selection) /
		4482	#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /!< 0x00000010 /
		4483	#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /!< 0x00000020 /
		4484	#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /!< 0x00000040 /
		4485
		4486	#define TIM_SMCR_MSM_Pos (7U)
		4487	#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /!< 0x00000080 /
		4488	#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /!<Master/slave mode /
		4489
		4490	#define TIM_SMCR_ETF_Pos (8U)
		4491	#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /!< 0x00000F00 /
		4492	#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /!<ETF[3:0] bits (External trigger filter) /
		4493	#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /!< 0x00000100 /
		4494	#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /!< 0x00000200 /
		4495	#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /!< 0x00000400 /
		4496	#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /!< 0x00000800 /
		4497
		4498	#define TIM_SMCR_ETPS_Pos (12U)
		4499	#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /!< 0x00003000 /
		4500	#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /!<ETPS[1:0] bits (External trigger prescaler) /
		4501	#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /!< 0x00001000 /
		4502	#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /!< 0x00002000 /
		4503
		4504	#define TIM_SMCR_ECE_Pos (14U)
		4505	#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /!< 0x00004000 /
		4506	#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /!<External clock enable /
		4507	#define TIM_SMCR_ETP_Pos (15U)
		4508	#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /!< 0x00008000 /
		4509	#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /!<External trigger polarity /
		4510
		4511	/***************** Bit definition for TIM_DIER register ****************/
		4512	#define TIM_DIER_UIE_Pos (0U)
		4513	#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /!< 0x00000001 /
		4514	#define TIM_DIER_UIE TIM_DIER_UIE_Msk /!<Update interrupt enable /
		4515	#define TIM_DIER_CC1IE_Pos (1U)
		4516	#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /!< 0x00000002 /
		4517	#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /!<Capture/Compare 1 interrupt enable /
		4518	#define TIM_DIER_CC2IE_Pos (2U)
		4519	#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /!< 0x00000004 /
		4520	#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /!<Capture/Compare 2 interrupt enable /
		4521	#define TIM_DIER_CC3IE_Pos (3U)
		4522	#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /!< 0x00000008 /
		4523	#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /!<Capture/Compare 3 interrupt enable /
		4524	#define TIM_DIER_CC4IE_Pos (4U)
		4525	#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /!< 0x00000010 /
		4526	#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /!<Capture/Compare 4 interrupt enable /
		4527	#define TIM_DIER_COMIE_Pos (5U)
		4528	#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /!< 0x00000020 /
		4529	#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /!<COM interrupt enable /
		4530	#define TIM_DIER_TIE_Pos (6U)
		4531	#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /!< 0x00000040 /
		4532	#define TIM_DIER_TIE TIM_DIER_TIE_Msk /!<Trigger interrupt enable /
		4533	#define TIM_DIER_BIE_Pos (7U)
		4534	#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /!< 0x00000080 /
		4535	#define TIM_DIER_BIE TIM_DIER_BIE_Msk /!<Break interrupt enable /
		4536	#define TIM_DIER_UDE_Pos (8U)
		4537	#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /!< 0x00000100 /
		4538	#define TIM_DIER_UDE TIM_DIER_UDE_Msk /!<Update DMA request enable /
		4539	#define TIM_DIER_CC1DE_Pos (9U)
		4540	#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /!< 0x00000200 /
		4541	#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /!<Capture/Compare 1 DMA request enable /
		4542	#define TIM_DIER_CC2DE_Pos (10U)
		4543	#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /!< 0x00000400 /
		4544	#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /!<Capture/Compare 2 DMA request enable /
		4545	#define TIM_DIER_CC3DE_Pos (11U)
		4546	#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /!< 0x00000800 /
		4547	#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /!<Capture/Compare 3 DMA request enable /
		4548	#define TIM_DIER_CC4DE_Pos (12U)
		4549	#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /!< 0x00001000 /
		4550	#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /!<Capture/Compare 4 DMA request enable /
		4551	#define TIM_DIER_COMDE_Pos (13U)
		4552	#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /!< 0x00002000 /
		4553	#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /!<COM DMA request enable /
		4554	#define TIM_DIER_TDE_Pos (14U)
		4555	#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /!< 0x00004000 /
		4556	#define TIM_DIER_TDE TIM_DIER_TDE_Msk /!<Trigger DMA request enable /
		4557
		4558	/****************** Bit definition for TIM_SR register *****************/
		4559	#define TIM_SR_UIF_Pos (0U)
		4560	#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /!< 0x00000001 /
		4561	#define TIM_SR_UIF TIM_SR_UIF_Msk /!<Update interrupt Flag /
		4562	#define TIM_SR_CC1IF_Pos (1U)
		4563	#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /!< 0x00000002 /
		4564	#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /!<Capture/Compare 1 interrupt Flag /
		4565	#define TIM_SR_CC2IF_Pos (2U)
		4566	#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /!< 0x00000004 /
		4567	#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /!<Capture/Compare 2 interrupt Flag /
		4568	#define TIM_SR_CC3IF_Pos (3U)
		4569	#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /!< 0x00000008 /
		4570	#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /!<Capture/Compare 3 interrupt Flag /
		4571	#define TIM_SR_CC4IF_Pos (4U)
		4572	#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /!< 0x00000010 /
		4573	#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /!<Capture/Compare 4 interrupt Flag /
		4574	#define TIM_SR_COMIF_Pos (5U)
		4575	#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /!< 0x00000020 /
		4576	#define TIM_SR_COMIF TIM_SR_COMIF_Msk /!<COM interrupt Flag /
		4577	#define TIM_SR_TIF_Pos (6U)
		4578	#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /!< 0x00000040 /
		4579	#define TIM_SR_TIF TIM_SR_TIF_Msk /!<Trigger interrupt Flag /
		4580	#define TIM_SR_BIF_Pos (7U)
		4581	#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /!< 0x00000080 /
		4582	#define TIM_SR_BIF TIM_SR_BIF_Msk /!<Break interrupt Flag /
		4583	#define TIM_SR_CC1OF_Pos (9U)
		4584	#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /!< 0x00000200 /
		4585	#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /!<Capture/Compare 1 Overcapture Flag /
		4586	#define TIM_SR_CC2OF_Pos (10U)
		4587	#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /!< 0x00000400 /
		4588	#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /!<Capture/Compare 2 Overcapture Flag /
		4589	#define TIM_SR_CC3OF_Pos (11U)
		4590	#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /!< 0x00000800 /
		4591	#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /!<Capture/Compare 3 Overcapture Flag /
		4592	#define TIM_SR_CC4OF_Pos (12U)
		4593	#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /!< 0x00001000 /
		4594	#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /!<Capture/Compare 4 Overcapture Flag /
		4595
		4596	/***************** Bit definition for TIM_EGR register *****************/
		4597	#define TIM_EGR_UG_Pos (0U)
		4598	#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /!< 0x00000001 /
		4599	#define TIM_EGR_UG TIM_EGR_UG_Msk /!<Update Generation /
		4600	#define TIM_EGR_CC1G_Pos (1U)
		4601	#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /!< 0x00000002 /
		4602	#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /!<Capture/Compare 1 Generation /
		4603	#define TIM_EGR_CC2G_Pos (2U)
		4604	#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /!< 0x00000004 /
		4605	#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /!<Capture/Compare 2 Generation /
		4606	#define TIM_EGR_CC3G_Pos (3U)
		4607	#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /!< 0x00000008 /
		4608	#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /!<Capture/Compare 3 Generation /
		4609	#define TIM_EGR_CC4G_Pos (4U)
		4610	#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /!< 0x00000010 /
		4611	#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /!<Capture/Compare 4 Generation /
		4612	#define TIM_EGR_COMG_Pos (5U)
		4613	#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /!< 0x00000020 /
		4614	#define TIM_EGR_COMG TIM_EGR_COMG_Msk /!<Capture/Compare Control Update Generation /
		4615	#define TIM_EGR_TG_Pos (6U)
		4616	#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /!< 0x00000040 /
		4617	#define TIM_EGR_TG TIM_EGR_TG_Msk /!<Trigger Generation /
		4618	#define TIM_EGR_BG_Pos (7U)
		4619	#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /!< 0x00000080 /
		4620	#define TIM_EGR_BG TIM_EGR_BG_Msk /!<Break Generation /
		4621
		4622	/**************** Bit definition for TIM_CCMR1 register ****************/
		4623	#define TIM_CCMR1_CC1S_Pos (0U)
		4624	#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /!< 0x00000003 /
		4625	#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
		4626	#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /!< 0x00000001 /
		4627	#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /!< 0x00000002 /
		4628
		4629	#define TIM_CCMR1_OC1FE_Pos (2U)
		4630	#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /!< 0x00000004 /
		4631	#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /!<Output Compare 1 Fast enable /
		4632	#define TIM_CCMR1_OC1PE_Pos (3U)
		4633	#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /!< 0x00000008 /
		4634	#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /!<Output Compare 1 Preload enable /
		4635
		4636	#define TIM_CCMR1_OC1M_Pos (4U)
		4637	#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000070 /
		4638	#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /!<OC1M[2:0] bits (Output Compare 1 Mode) /
		4639	#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000010 /
		4640	#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000020 /
		4641	#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000040 /
		4642
		4643	#define TIM_CCMR1_OC1CE_Pos (7U)
		4644	#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /!< 0x00000080 /
		4645	#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /!<Output Compare 1Clear Enable /
		4646
		4647	#define TIM_CCMR1_CC2S_Pos (8U)
		4648	#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /!< 0x00000300 /
		4649	#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
		4650	#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /!< 0x00000100 /
		4651	#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /!< 0x00000200 /
		4652
		4653	#define TIM_CCMR1_OC2FE_Pos (10U)
		4654	#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /!< 0x00000400 /
		4655	#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /!<Output Compare 2 Fast enable /
		4656	#define TIM_CCMR1_OC2PE_Pos (11U)
		4657	#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /!< 0x00000800 /
		4658	#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /!<Output Compare 2 Preload enable /
		4659
		4660	#define TIM_CCMR1_OC2M_Pos (12U)
		4661	#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /!< 0x00007000 /
		4662	#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /!<OC2M[2:0] bits (Output Compare 2 Mode) /
		4663	#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /!< 0x00001000 /
		4664	#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /!< 0x00002000 /
		4665	#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /!< 0x00004000 /
		4666
		4667	#define TIM_CCMR1_OC2CE_Pos (15U)
		4668	#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /!< 0x00008000 /
		4669	#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /!<Output Compare 2 Clear Enable /
		4670
		4671	/---------------------------------------------------------------------------/
		4672
		4673	#define TIM_CCMR1_IC1PSC_Pos (2U)
		4674	#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /!< 0x0000000C /
		4675	#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
		4676	#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000004 /
		4677	#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000008 /
		4678
		4679	#define TIM_CCMR1_IC1F_Pos (4U)
		4680	#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /!< 0x000000F0 /
		4681	#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /!<IC1F[3:0] bits (Input Capture 1 Filter) /
		4682	#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000010 /
		4683	#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000020 /
		4684	#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000040 /
		4685	#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000080 /
		4686
		4687	#define TIM_CCMR1_IC2PSC_Pos (10U)
		4688	#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000C00 /
		4689	#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
		4690	#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000400 /
		4691	#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000800 /
		4692
		4693	#define TIM_CCMR1_IC2F_Pos (12U)
		4694	#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /!< 0x0000F000 /
		4695	#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /!<IC2F[3:0] bits (Input Capture 2 Filter) /
		4696	#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /!< 0x00001000 /
		4697	#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /!< 0x00002000 /
		4698	#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /!< 0x00004000 /
		4699	#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /!< 0x00008000 /
		4700
		4701	/**************** Bit definition for TIM_CCMR2 register ****************/
		4702	#define TIM_CCMR2_CC3S_Pos (0U)
		4703	#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /!< 0x00000003 /
		4704	#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
		4705	#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /!< 0x00000001 /
		4706	#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /!< 0x00000002 /
		4707
		4708	#define TIM_CCMR2_OC3FE_Pos (2U)
		4709	#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /!< 0x00000004 /
		4710	#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /!<Output Compare 3 Fast enable /
		4711	#define TIM_CCMR2_OC3PE_Pos (3U)
		4712	#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /!< 0x00000008 /
		4713	#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /!<Output Compare 3 Preload enable /
		4714
		4715	#define TIM_CCMR2_OC3M_Pos (4U)
		4716	#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000070 /
		4717	#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /!<OC3M[2:0] bits (Output Compare 3 Mode) /
		4718	#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000010 /
		4719	#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000020 /
		4720	#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000040 /
		4721
		4722	#define TIM_CCMR2_OC3CE_Pos (7U)
		4723	#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /!< 0x00000080 /
		4724	#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /!<Output Compare 3 Clear Enable /
		4725
		4726	#define TIM_CCMR2_CC4S_Pos (8U)
		4727	#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /!< 0x00000300 /
		4728	#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
		4729	#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /!< 0x00000100 /
		4730	#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /!< 0x00000200 /
		4731
		4732	#define TIM_CCMR2_OC4FE_Pos (10U)
		4733	#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /!< 0x00000400 /
		4734	#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /!<Output Compare 4 Fast enable /
		4735	#define TIM_CCMR2_OC4PE_Pos (11U)
		4736	#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /!< 0x00000800 /
		4737	#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /!<Output Compare 4 Preload enable /
		4738
		4739	#define TIM_CCMR2_OC4M_Pos (12U)
		4740	#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /!< 0x00007000 /
		4741	#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /!<OC4M[2:0] bits (Output Compare 4 Mode) /
		4742	#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /!< 0x00001000 /
		4743	#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /!< 0x00002000 /
		4744	#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /!< 0x00004000 /
		4745
		4746	#define TIM_CCMR2_OC4CE_Pos (15U)
		4747	#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /!< 0x00008000 /
		4748	#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /!<Output Compare 4 Clear Enable /
		4749
		4750	/---------------------------------------------------------------------------/
		4751
		4752	#define TIM_CCMR2_IC3PSC_Pos (2U)
		4753	#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /!< 0x0000000C /
		4754	#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
		4755	#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000004 /
		4756	#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000008 /
		4757
		4758	#define TIM_CCMR2_IC3F_Pos (4U)
		4759	#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /!< 0x000000F0 /
		4760	#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /!<IC3F[3:0] bits (Input Capture 3 Filter) /
		4761	#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000010 /
		4762	#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000020 /
		4763	#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000040 /
		4764	#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000080 /
		4765
		4766	#define TIM_CCMR2_IC4PSC_Pos (10U)
		4767	#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000C00 /
		4768	#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
		4769	#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000400 /
		4770	#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000800 /
		4771
		4772	#define TIM_CCMR2_IC4F_Pos (12U)
		4773	#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /!< 0x0000F000 /
		4774	#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /!<IC4F[3:0] bits (Input Capture 4 Filter) /
		4775	#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /!< 0x00001000 /
		4776	#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /!< 0x00002000 /
		4777	#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /!< 0x00004000 /
		4778	#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /!< 0x00008000 /
		4779
		4780	/***************** Bit definition for TIM_CCER register ****************/
		4781	#define TIM_CCER_CC1E_Pos (0U)
		4782	#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /!< 0x00000001 /
		4783	#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /!<Capture/Compare 1 output enable /
		4784	#define TIM_CCER_CC1P_Pos (1U)
		4785	#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /!< 0x00000002 /
		4786	#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /!<Capture/Compare 1 output Polarity /
		4787	#define TIM_CCER_CC1NE_Pos (2U)
		4788	#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /!< 0x00000004 /
		4789	#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /!<Capture/Compare 1 Complementary output enable /
		4790	#define TIM_CCER_CC1NP_Pos (3U)
		4791	#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /!< 0x00000008 /
		4792	#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /!<Capture/Compare 1 Complementary output Polarity /
		4793	#define TIM_CCER_CC2E_Pos (4U)
		4794	#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /!< 0x00000010 /
		4795	#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /!<Capture/Compare 2 output enable /
		4796	#define TIM_CCER_CC2P_Pos (5U)
		4797	#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /!< 0x00000020 /
		4798	#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /!<Capture/Compare 2 output Polarity /
		4799	#define TIM_CCER_CC2NE_Pos (6U)
		4800	#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /!< 0x00000040 /
		4801	#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /!<Capture/Compare 2 Complementary output enable /
		4802	#define TIM_CCER_CC2NP_Pos (7U)
		4803	#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /!< 0x00000080 /
		4804	#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /!<Capture/Compare 2 Complementary output Polarity /
		4805	#define TIM_CCER_CC3E_Pos (8U)
		4806	#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /!< 0x00000100 /
		4807	#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /!<Capture/Compare 3 output enable /
		4808	#define TIM_CCER_CC3P_Pos (9U)
		4809	#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /!< 0x00000200 /
		4810	#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /!<Capture/Compare 3 output Polarity /
		4811	#define TIM_CCER_CC3NE_Pos (10U)
		4812	#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /!< 0x00000400 /
		4813	#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /!<Capture/Compare 3 Complementary output enable /
		4814	#define TIM_CCER_CC3NP_Pos (11U)
		4815	#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /!< 0x00000800 /
		4816	#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /!<Capture/Compare 3 Complementary output Polarity /
		4817	#define TIM_CCER_CC4E_Pos (12U)
		4818	#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /!< 0x00001000 /
		4819	#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /!<Capture/Compare 4 output enable /
		4820	#define TIM_CCER_CC4P_Pos (13U)
		4821	#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /!< 0x00002000 /
		4822	#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /!<Capture/Compare 4 output Polarity /
		4823
		4824	/***************** Bit definition for TIM_CNT register *****************/
		4825	#define TIM_CNT_CNT_Pos (0U)
		4826	#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /!< 0xFFFFFFFF /
		4827	#define TIM_CNT_CNT TIM_CNT_CNT_Msk /!<Counter Value /
		4828
		4829	/***************** Bit definition for TIM_PSC register *****************/
		4830	#define TIM_PSC_PSC_Pos (0U)
		4831	#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /!< 0x0000FFFF /
		4832	#define TIM_PSC_PSC TIM_PSC_PSC_Msk /!<Prescaler Value /
		4833
		4834	/***************** Bit definition for TIM_ARR register *****************/
		4835	#define TIM_ARR_ARR_Pos (0U)
		4836	#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /!< 0xFFFFFFFF /
		4837	#define TIM_ARR_ARR TIM_ARR_ARR_Msk /!<actual auto-reload Value /
		4838
		4839	/***************** Bit definition for TIM_RCR register *****************/
		4840	#define TIM_RCR_REP_Pos (0U)
		4841	#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /!< 0x000000FF /
		4842	#define TIM_RCR_REP TIM_RCR_REP_Msk /!<Repetition Counter Value /
		4843
		4844	/***************** Bit definition for TIM_CCR1 register ****************/
		4845	#define TIM_CCR1_CCR1_Pos (0U)
		4846	#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /!< 0x0000FFFF /
		4847	#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /!<Capture/Compare 1 Value /
		4848
		4849	/***************** Bit definition for TIM_CCR2 register ****************/
		4850	#define TIM_CCR2_CCR2_Pos (0U)
		4851	#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /!< 0x0000FFFF /
		4852	#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /!<Capture/Compare 2 Value /
		4853
		4854	/***************** Bit definition for TIM_CCR3 register ****************/
		4855	#define TIM_CCR3_CCR3_Pos (0U)
		4856	#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /!< 0x0000FFFF /
		4857	#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /!<Capture/Compare 3 Value /
		4858
		4859	/***************** Bit definition for TIM_CCR4 register ****************/
		4860	#define TIM_CCR4_CCR4_Pos (0U)
		4861	#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /!< 0x0000FFFF /
		4862	#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /!<Capture/Compare 4 Value /
		4863
		4864	/***************** Bit definition for TIM_BDTR register ****************/
		4865	#define TIM_BDTR_DTG_Pos (0U)
		4866	#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /!< 0x000000FF /
		4867	#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /!<DTG[0:7] bits (Dead-Time Generator set-up) /
		4868	#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /!< 0x00000001 /
		4869	#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /!< 0x00000002 /
		4870	#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /!< 0x00000004 /
		4871	#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /!< 0x00000008 /
		4872	#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /!< 0x00000010 /
		4873	#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /!< 0x00000020 /
		4874	#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /!< 0x00000040 /
		4875	#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /!< 0x00000080 /
		4876
		4877	#define TIM_BDTR_LOCK_Pos (8U)
		4878	#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /!< 0x00000300 /
		4879	#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /!<LOCK[1:0] bits (Lock Configuration) /
		4880	#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /!< 0x00000100 /
		4881	#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /!< 0x00000200 /
		4882
		4883	#define TIM_BDTR_OSSI_Pos (10U)
		4884	#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /!< 0x00000400 /
		4885	#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /!<Off-State Selection for Idle mode /
		4886	#define TIM_BDTR_OSSR_Pos (11U)
		4887	#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /!< 0x00000800 /
		4888	#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /!<Off-State Selection for Run mode /
		4889	#define TIM_BDTR_BKE_Pos (12U)
		4890	#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /!< 0x00001000 /
		4891	#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /!<Break enable /
		4892	#define TIM_BDTR_BKP_Pos (13U)
		4893	#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /!< 0x00002000 /
		4894	#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /!<Break Polarity /
		4895	#define TIM_BDTR_AOE_Pos (14U)
		4896	#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /!< 0x00004000 /
		4897	#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /!<Automatic Output enable /
		4898	#define TIM_BDTR_MOE_Pos (15U)
		4899	#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /!< 0x00008000 /
		4900	#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /!<Main Output enable /
		4901
		4902	/***************** Bit definition for TIM_DCR register *****************/
		4903	#define TIM_DCR_DBA_Pos (0U)
		4904	#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /!< 0x0000001F /
		4905	#define TIM_DCR_DBA TIM_DCR_DBA_Msk /!<DBA[4:0] bits (DMA Base Address) /
		4906	#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /!< 0x00000001 /
		4907	#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /!< 0x00000002 /
		4908	#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /!< 0x00000004 /
		4909	#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /!< 0x00000008 /
		4910	#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /!< 0x00000010 /
		4911
		4912	#define TIM_DCR_DBL_Pos (8U)
		4913	#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /!< 0x00001F00 /
		4914	#define TIM_DCR_DBL TIM_DCR_DBL_Msk /!<DBL[4:0] bits (DMA Burst Length) /
		4915	#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /!< 0x00000100 /
		4916	#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /!< 0x00000200 /
		4917	#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /!< 0x00000400 /
		4918	#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /!< 0x00000800 /
		4919	#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /!< 0x00001000 /
		4920
		4921	/***************** Bit definition for TIM_DMAR register ****************/
		4922	#define TIM_DMAR_DMAB_Pos (0U)
		4923	#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /!< 0x0000FFFF /
		4924	#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /!<DMA register for burst accesses /
		4925
		4926	/******************************************************************************/
		4927	/* */
		4928	/* Real-Time Clock */
		4929	/* */
		4930	/******************************************************************************/
		4931
		4932	/***************** Bit definition for RTC_CRH register ******************/
		4933	#define RTC_CRH_SECIE_Pos (0U)
		4934	#define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /!< 0x00000001 /
		4935	#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /!< Second Interrupt Enable /
		4936	#define RTC_CRH_ALRIE_Pos (1U)
		4937	#define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /!< 0x00000002 /
		4938	#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /!< Alarm Interrupt Enable /
		4939	#define RTC_CRH_OWIE_Pos (2U)
		4940	#define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /!< 0x00000004 /
		4941	#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /!< OverfloW Interrupt Enable /
		4942
		4943	/***************** Bit definition for RTC_CRL register ******************/
		4944	#define RTC_CRL_SECF_Pos (0U)
		4945	#define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /!< 0x00000001 /
		4946	#define RTC_CRL_SECF RTC_CRL_SECF_Msk /!< Second Flag /
		4947	#define RTC_CRL_ALRF_Pos (1U)
		4948	#define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /!< 0x00000002 /
		4949	#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /!< Alarm Flag /
		4950	#define RTC_CRL_OWF_Pos (2U)
		4951	#define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /!< 0x00000004 /
		4952	#define RTC_CRL_OWF RTC_CRL_OWF_Msk /!< OverfloW Flag /
		4953	#define RTC_CRL_RSF_Pos (3U)
		4954	#define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /!< 0x00000008 /
		4955	#define RTC_CRL_RSF RTC_CRL_RSF_Msk /!< Registers Synchronized Flag /
		4956	#define RTC_CRL_CNF_Pos (4U)
		4957	#define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /!< 0x00000010 /
		4958	#define RTC_CRL_CNF RTC_CRL_CNF_Msk /!< Configuration Flag /
		4959	#define RTC_CRL_RTOFF_Pos (5U)
		4960	#define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /!< 0x00000020 /
		4961	#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /!< RTC operation OFF /
		4962
		4963	/***************** Bit definition for RTC_PRLH register *****************/
		4964	#define RTC_PRLH_PRL_Pos (0U)
		4965	#define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /!< 0x0000000F /
		4966	#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /!< RTC Prescaler Reload Value High /
		4967
		4968	/***************** Bit definition for RTC_PRLL register *****************/
		4969	#define RTC_PRLL_PRL_Pos (0U)
		4970	#define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /!< 0x0000FFFF /
		4971	#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /!< RTC Prescaler Reload Value Low /
		4972
		4973	/***************** Bit definition for RTC_DIVH register *****************/
		4974	#define RTC_DIVH_RTC_DIV_Pos (0U)
		4975	#define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /!< 0x0000000F /
		4976	#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /!< RTC Clock Divider High /
		4977
		4978	/***************** Bit definition for RTC_DIVL register *****************/
		4979	#define RTC_DIVL_RTC_DIV_Pos (0U)
		4980	#define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /!< 0x0000FFFF /
		4981	#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /!< RTC Clock Divider Low /
		4982
		4983	/***************** Bit definition for RTC_CNTH register *****************/
		4984	#define RTC_CNTH_RTC_CNT_Pos (0U)
		4985	#define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /!< 0x0000FFFF /
		4986	#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /!< RTC Counter High /
		4987
		4988	/***************** Bit definition for RTC_CNTL register *****************/
		4989	#define RTC_CNTL_RTC_CNT_Pos (0U)
		4990	#define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /!< 0x0000FFFF /
		4991	#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /!< RTC Counter Low /
		4992
		4993	/***************** Bit definition for RTC_ALRH register *****************/
		4994	#define RTC_ALRH_RTC_ALR_Pos (0U)
		4995	#define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /!< 0x0000FFFF /
		4996	#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /!< RTC Alarm High /
		4997
		4998	/***************** Bit definition for RTC_ALRL register *****************/
		4999	#define RTC_ALRL_RTC_ALR_Pos (0U)
		5000	#define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /!< 0x0000FFFF /
		5001	#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /!< RTC Alarm Low /
		5002
		5003	/******************************************************************************/
		5004	/* */
		5005	/* Independent WATCHDOG (IWDG) */
		5006	/* */
		5007	/******************************************************************************/
		5008
		5009	/***************** Bit definition for IWDG_KR register ******************/
		5010	#define IWDG_KR_KEY_Pos (0U)
		5011	#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /!< 0x0000FFFF /
		5012	#define IWDG_KR_KEY IWDG_KR_KEY_Msk /!< Key value (write only, read 0000h) /
		5013
		5014	/***************** Bit definition for IWDG_PR register ******************/
		5015	#define IWDG_PR_PR_Pos (0U)
		5016	#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /!< 0x00000007 /
		5017	#define IWDG_PR_PR IWDG_PR_PR_Msk /!< PR[2:0] (Prescaler divider) /
		5018	#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /!< 0x00000001 /
		5019	#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /!< 0x00000002 /
		5020	#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /!< 0x00000004 /
		5021
		5022	/***************** Bit definition for IWDG_RLR register *****************/
		5023	#define IWDG_RLR_RL_Pos (0U)
		5024	#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /!< 0x00000FFF /
		5025	#define IWDG_RLR_RL IWDG_RLR_RL_Msk /!< Watchdog counter reload value /
		5026
		5027	/***************** Bit definition for IWDG_SR register ******************/
		5028	#define IWDG_SR_PVU_Pos (0U)
		5029	#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /!< 0x00000001 /
		5030	#define IWDG_SR_PVU IWDG_SR_PVU_Msk /!< Watchdog prescaler value update /
		5031	#define IWDG_SR_RVU_Pos (1U)
		5032	#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /!< 0x00000002 /
		5033	#define IWDG_SR_RVU IWDG_SR_RVU_Msk /!< Watchdog counter reload value update /
		5034
		5035	/******************************************************************************/
		5036	/* */
		5037	/* Window WATCHDOG (WWDG) */
		5038	/* */
		5039	/******************************************************************************/
		5040
		5041	/***************** Bit definition for WWDG_CR register ******************/
		5042	#define WWDG_CR_T_Pos (0U)
		5043	#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /!< 0x0000007F /
		5044	#define WWDG_CR_T WWDG_CR_T_Msk /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
		5045	#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /!< 0x00000001 /
		5046	#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /!< 0x00000002 /
		5047	#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /!< 0x00000004 /
		5048	#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /!< 0x00000008 /
		5049	#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /!< 0x00000010 /
		5050	#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /!< 0x00000020 /
		5051	#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /!< 0x00000040 /
		5052
		5053	/* Legacy defines */
		5054	#define WWDG_CR_T0 WWDG_CR_T_0
		5055	#define WWDG_CR_T1 WWDG_CR_T_1
		5056	#define WWDG_CR_T2 WWDG_CR_T_2
		5057	#define WWDG_CR_T3 WWDG_CR_T_3
		5058	#define WWDG_CR_T4 WWDG_CR_T_4
		5059	#define WWDG_CR_T5 WWDG_CR_T_5
		5060	#define WWDG_CR_T6 WWDG_CR_T_6
		5061
		5062	#define WWDG_CR_WDGA_Pos (7U)
		5063	#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /!< 0x00000080 /
		5064	#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /!< Activation bit /
		5065
		5066	/***************** Bit definition for WWDG_CFR register *****************/
		5067	#define WWDG_CFR_W_Pos (0U)
		5068	#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /!< 0x0000007F /
		5069	#define WWDG_CFR_W WWDG_CFR_W_Msk /!< W[6:0] bits (7-bit window value) /
		5070	#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /!< 0x00000001 /
		5071	#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /!< 0x00000002 /
		5072	#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /!< 0x00000004 /
		5073	#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /!< 0x00000008 /
		5074	#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /!< 0x00000010 /
		5075	#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /!< 0x00000020 /
		5076	#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /!< 0x00000040 /
		5077
		5078	/* Legacy defines */
		5079	#define WWDG_CFR_W0 WWDG_CFR_W_0
		5080	#define WWDG_CFR_W1 WWDG_CFR_W_1
		5081	#define WWDG_CFR_W2 WWDG_CFR_W_2
		5082	#define WWDG_CFR_W3 WWDG_CFR_W_3
		5083	#define WWDG_CFR_W4 WWDG_CFR_W_4
		5084	#define WWDG_CFR_W5 WWDG_CFR_W_5
		5085	#define WWDG_CFR_W6 WWDG_CFR_W_6
		5086
		5087	#define WWDG_CFR_WDGTB_Pos (7U)
		5088	#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /!< 0x00000180 /
		5089	#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /!< WDGTB[1:0] bits (Timer Base) /
		5090	#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /!< 0x00000080 /
		5091	#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /!< 0x00000100 /
		5092
		5093	/* Legacy defines */
		5094	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
		5095	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
		5096
		5097	#define WWDG_CFR_EWI_Pos (9U)
		5098	#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /!< 0x00000200 /
		5099	#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /!< Early Wakeup Interrupt /
		5100
		5101	/***************** Bit definition for WWDG_SR register ******************/
		5102	#define WWDG_SR_EWIF_Pos (0U)
		5103	#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /!< 0x00000001 /
		5104	#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /!< Early Wakeup Interrupt Flag /
		5105
		5106	/******************************************************************************/
		5107	/* */
		5108	/* Flexible Static Memory Controller */
		5109	/* */
		5110	/******************************************************************************/
		5111
		5112	/**************** Bit definition for FSMC_BCRx (x=1..4) register ********/
		5113	#define FSMC_BCRx_MBKEN_Pos (0U)
		5114	#define FSMC_BCRx_MBKEN_Msk (0x1UL << FSMC_BCRx_MBKEN_Pos) /!< 0x00000001 /
		5115	#define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /!< Memory bank enable bit /
		5116	#define FSMC_BCRx_MUXEN_Pos (1U)
		5117	#define FSMC_BCRx_MUXEN_Msk (0x1UL << FSMC_BCRx_MUXEN_Pos) /!< 0x00000002 /
		5118	#define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /!< Address/data multiplexing enable bit /
		5119
		5120	#define FSMC_BCRx_MTYP_Pos (2U)
		5121	#define FSMC_BCRx_MTYP_Msk (0x3UL << FSMC_BCRx_MTYP_Pos) /!< 0x0000000C /
		5122	#define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /!< MTYP[1:0] bits (Memory type) /
		5123	#define FSMC_BCRx_MTYP_0 (0x1UL << FSMC_BCRx_MTYP_Pos) /!< 0x00000004 /
		5124	#define FSMC_BCRx_MTYP_1 (0x2UL << FSMC_BCRx_MTYP_Pos) /!< 0x00000008 /
		5125
		5126	#define FSMC_BCRx_MWID_Pos (4U)
		5127	#define FSMC_BCRx_MWID_Msk (0x3UL << FSMC_BCRx_MWID_Pos) /!< 0x00000030 /
		5128	#define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /!< MWID[1:0] bits (Memory data bus width) /
		5129	#define FSMC_BCRx_MWID_0 (0x1UL << FSMC_BCRx_MWID_Pos) /!< 0x00000010 /
		5130	#define FSMC_BCRx_MWID_1 (0x2UL << FSMC_BCRx_MWID_Pos) /!< 0x00000020 /
		5131
		5132	#define FSMC_BCRx_FACCEN_Pos (6U)
		5133	#define FSMC_BCRx_FACCEN_Msk (0x1UL << FSMC_BCRx_FACCEN_Pos) /!< 0x00000040 /
		5134	#define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /!< Flash access enable /
		5135	#define FSMC_BCRx_BURSTEN_Pos (8U)
		5136	#define FSMC_BCRx_BURSTEN_Msk (0x1UL << FSMC_BCRx_BURSTEN_Pos) /!< 0x00000100 /
		5137	#define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /!< Burst enable bit /
		5138	#define FSMC_BCRx_WAITPOL_Pos (9U)
		5139	#define FSMC_BCRx_WAITPOL_Msk (0x1UL << FSMC_BCRx_WAITPOL_Pos) /!< 0x00000200 /
		5140	#define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /!< Wait signal polarity bit /
		5141	#define FSMC_BCRx_WRAPMOD_Pos (10U)
		5142	#define FSMC_BCRx_WRAPMOD_Msk (0x1UL << FSMC_BCRx_WRAPMOD_Pos) /!< 0x00000400 /
		5143	#define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /!< Wrapped burst mode support /
		5144	#define FSMC_BCRx_WAITCFG_Pos (11U)
		5145	#define FSMC_BCRx_WAITCFG_Msk (0x1UL << FSMC_BCRx_WAITCFG_Pos) /!< 0x00000800 /
		5146	#define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /!< Wait timing configuration /
		5147	#define FSMC_BCRx_WREN_Pos (12U)
		5148	#define FSMC_BCRx_WREN_Msk (0x1UL << FSMC_BCRx_WREN_Pos) /!< 0x00001000 /
		5149	#define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /!< Write enable bit /
		5150	#define FSMC_BCRx_WAITEN_Pos (13U)
		5151	#define FSMC_BCRx_WAITEN_Msk (0x1UL << FSMC_BCRx_WAITEN_Pos) /!< 0x00002000 /
		5152	#define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /!< Wait enable bit /
		5153	#define FSMC_BCRx_EXTMOD_Pos (14U)
		5154	#define FSMC_BCRx_EXTMOD_Msk (0x1UL << FSMC_BCRx_EXTMOD_Pos) /!< 0x00004000 /
		5155	#define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /!< Extended mode enable /
		5156	#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
		5157	#define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /!< 0x00008000 /
		5158	#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /!< Asynchronous wait /
		5159	#define FSMC_BCRx_CBURSTRW_Pos (19U)
		5160	#define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /!< 0x00080000 /
		5161	#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /!< Write burst enable /
		5162
		5163	/**************** Bit definition for FSMC_BTRx (x=1..4) register ****/
		5164	#define FSMC_BTRx_ADDSET_Pos (0U)
		5165	#define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /!< 0x0000000F /
		5166	#define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /!< ADDSET[3:0] bits (Address setup phase duration) /
		5167	#define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /!< 0x00000001 /
		5168	#define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /!< 0x00000002 /
		5169	#define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /!< 0x00000004 /
		5170	#define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /!< 0x00000008 /
		5171
		5172	#define FSMC_BTRx_ADDHLD_Pos (4U)
		5173	#define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /!< 0x000000F0 /
		5174	#define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		5175	#define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000010 /
		5176	#define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000020 /
		5177	#define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000040 /
		5178	#define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /!< 0x00000080 /
		5179
		5180	#define FSMC_BTRx_DATAST_Pos (8U)
		5181	#define FSMC_BTRx_DATAST_Msk (0xFFUL << FSMC_BTRx_DATAST_Pos) /!< 0x0000FF00 /
		5182	#define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /!< DATAST [3:0] bits (Data-phase duration) /
		5183	#define FSMC_BTRx_DATAST_0 (0x01UL << FSMC_BTRx_DATAST_Pos) /!< 0x00000100 /
		5184	#define FSMC_BTRx_DATAST_1 (0x02UL << FSMC_BTRx_DATAST_Pos) /!< 0x00000200 /
		5185	#define FSMC_BTRx_DATAST_2 (0x04UL << FSMC_BTRx_DATAST_Pos) /!< 0x00000400 /
		5186	#define FSMC_BTRx_DATAST_3 (0x08UL << FSMC_BTRx_DATAST_Pos) /!< 0x00000800 /
		5187	#define FSMC_BTRx_DATAST_4 (0x10UL << FSMC_BTRx_DATAST_Pos) /!< 0x00001000 /
		5188	#define FSMC_BTRx_DATAST_5 (0x20UL << FSMC_BTRx_DATAST_Pos) /!< 0x00002000 /
		5189	#define FSMC_BTRx_DATAST_6 (0x40UL << FSMC_BTRx_DATAST_Pos) /!< 0x00004000 /
		5190	#define FSMC_BTRx_DATAST_7 (0x80UL << FSMC_BTRx_DATAST_Pos) /!< 0x00008000 /
		5191
		5192	#define FSMC_BTRx_BUSTURN_Pos (16U)
		5193	#define FSMC_BTRx_BUSTURN_Msk (0xFUL << FSMC_BTRx_BUSTURN_Pos) /!< 0x000F0000 /
		5194	#define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
		5195	#define FSMC_BTRx_BUSTURN_0 (0x1UL << FSMC_BTRx_BUSTURN_Pos) /!< 0x00010000 /
		5196	#define FSMC_BTRx_BUSTURN_1 (0x2UL << FSMC_BTRx_BUSTURN_Pos) /!< 0x00020000 /
		5197	#define FSMC_BTRx_BUSTURN_2 (0x4UL << FSMC_BTRx_BUSTURN_Pos) /!< 0x00040000 /
		5198	#define FSMC_BTRx_BUSTURN_3 (0x8UL << FSMC_BTRx_BUSTURN_Pos) /!< 0x00080000 /
		5199
		5200	#define FSMC_BTRx_CLKDIV_Pos (20U)
		5201	#define FSMC_BTRx_CLKDIV_Msk (0xFUL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00F00000 /
		5202	#define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /!< CLKDIV[3:0] bits (Clock divide ratio) /
		5203	#define FSMC_BTRx_CLKDIV_0 (0x1UL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00100000 /
		5204	#define FSMC_BTRx_CLKDIV_1 (0x2UL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00200000 /
		5205	#define FSMC_BTRx_CLKDIV_2 (0x4UL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00400000 /
		5206	#define FSMC_BTRx_CLKDIV_3 (0x8UL << FSMC_BTRx_CLKDIV_Pos) /!< 0x00800000 /
		5207
		5208	#define FSMC_BTRx_DATLAT_Pos (24U)
		5209	#define FSMC_BTRx_DATLAT_Msk (0xFUL << FSMC_BTRx_DATLAT_Pos) /!< 0x0F000000 /
		5210	#define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /!< DATLA[3:0] bits (Data latency) /
		5211	#define FSMC_BTRx_DATLAT_0 (0x1UL << FSMC_BTRx_DATLAT_Pos) /!< 0x01000000 /
		5212	#define FSMC_BTRx_DATLAT_1 (0x2UL << FSMC_BTRx_DATLAT_Pos) /!< 0x02000000 /
		5213	#define FSMC_BTRx_DATLAT_2 (0x4UL << FSMC_BTRx_DATLAT_Pos) /!< 0x04000000 /
		5214	#define FSMC_BTRx_DATLAT_3 (0x8UL << FSMC_BTRx_DATLAT_Pos) /!< 0x08000000 /
		5215
		5216	#define FSMC_BTRx_ACCMOD_Pos (28U)
		5217	#define FSMC_BTRx_ACCMOD_Msk (0x3UL << FSMC_BTRx_ACCMOD_Pos) /!< 0x30000000 /
		5218	#define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /!< ACCMOD[1:0] bits (Access mode) /
		5219	#define FSMC_BTRx_ACCMOD_0 (0x1UL << FSMC_BTRx_ACCMOD_Pos) /!< 0x10000000 /
		5220	#define FSMC_BTRx_ACCMOD_1 (0x2UL << FSMC_BTRx_ACCMOD_Pos) /!< 0x20000000 /
		5221
		5222	/**************** Bit definition for FSMC_BWTRx (x=1..4) register ****/
		5223	#define FSMC_BWTRx_ADDSET_Pos (0U)
		5224	#define FSMC_BWTRx_ADDSET_Msk (0xFUL << FSMC_BWTRx_ADDSET_Pos) /!< 0x0000000F /
		5225	#define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /!< ADDSET[3:0] bits (Address setup phase duration) /
		5226	#define FSMC_BWTRx_ADDSET_0 (0x1UL << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000001 /
		5227	#define FSMC_BWTRx_ADDSET_1 (0x2UL << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000002 /
		5228	#define FSMC_BWTRx_ADDSET_2 (0x4UL << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000004 /
		5229	#define FSMC_BWTRx_ADDSET_3 (0x8UL << FSMC_BWTRx_ADDSET_Pos) /!< 0x00000008 /
		5230
		5231	#define FSMC_BWTRx_ADDHLD_Pos (4U)
		5232	#define FSMC_BWTRx_ADDHLD_Msk (0xFUL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x000000F0 /
		5233	#define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /!< ADDHLD[3:0] bits (Address-hold phase duration) /
		5234	#define FSMC_BWTRx_ADDHLD_0 (0x1UL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000010 /
		5235	#define FSMC_BWTRx_ADDHLD_1 (0x2UL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000020 /
		5236	#define FSMC_BWTRx_ADDHLD_2 (0x4UL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000040 /
		5237	#define FSMC_BWTRx_ADDHLD_3 (0x8UL << FSMC_BWTRx_ADDHLD_Pos) /!< 0x00000080 /
		5238
		5239	#define FSMC_BWTRx_DATAST_Pos (8U)
		5240	#define FSMC_BWTRx_DATAST_Msk (0xFFUL << FSMC_BWTRx_DATAST_Pos) /!< 0x0000FF00 /
		5241	#define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /!< DATAST [3:0] bits (Data-phase duration) /
		5242	#define FSMC_BWTRx_DATAST_0 (0x01UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00000100 /
		5243	#define FSMC_BWTRx_DATAST_1 (0x02UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00000200 /
		5244	#define FSMC_BWTRx_DATAST_2 (0x04UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00000400 /
		5245	#define FSMC_BWTRx_DATAST_3 (0x08UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00000800 /
		5246	#define FSMC_BWTRx_DATAST_4 (0x10UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00001000 /
		5247	#define FSMC_BWTRx_DATAST_5 (0x20UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00002000 /
		5248	#define FSMC_BWTRx_DATAST_6 (0x40UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00004000 /
		5249	#define FSMC_BWTRx_DATAST_7 (0x80UL << FSMC_BWTRx_DATAST_Pos) /!< 0x00008000 /
		5250
		5251	#define FSMC_BWTRx_CLKDIV_Pos (20U)
		5252	#define FSMC_BWTRx_CLKDIV_Msk (0xFUL << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00F00000 /
		5253	#define FSMC_BWTRx_CLKDIV FSMC_BWTRx_CLKDIV_Msk /!< CLKDIV[3:0] bits (Clock divide ratio) /
		5254	#define FSMC_BWTRx_CLKDIV_0 (0x1UL << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00100000 /
		5255	#define FSMC_BWTRx_CLKDIV_1 (0x2UL << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00200000 /
		5256	#define FSMC_BWTRx_CLKDIV_2 (0x4UL << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00400000 /
		5257	#define FSMC_BWTRx_CLKDIV_3 (0x8UL << FSMC_BWTRx_CLKDIV_Pos) /!< 0x00800000 /
		5258
		5259	#define FSMC_BWTRx_DATLAT_Pos (24U)
		5260	#define FSMC_BWTRx_DATLAT_Msk (0xFUL << FSMC_BWTRx_DATLAT_Pos) /!< 0x0F000000 /
		5261	#define FSMC_BWTRx_DATLAT FSMC_BWTRx_DATLAT_Msk /!< DATLA[3:0] bits (Data latency) /
		5262	#define FSMC_BWTRx_DATLAT_0 (0x1UL << FSMC_BWTRx_DATLAT_Pos) /!< 0x01000000 /
		5263	#define FSMC_BWTRx_DATLAT_1 (0x2UL << FSMC_BWTRx_DATLAT_Pos) /!< 0x02000000 /
		5264	#define FSMC_BWTRx_DATLAT_2 (0x4UL << FSMC_BWTRx_DATLAT_Pos) /!< 0x04000000 /
		5265	#define FSMC_BWTRx_DATLAT_3 (0x8UL << FSMC_BWTRx_DATLAT_Pos) /!< 0x08000000 /
		5266
		5267	#define FSMC_BWTRx_ACCMOD_Pos (28U)
		5268	#define FSMC_BWTRx_ACCMOD_Msk (0x3UL << FSMC_BWTRx_ACCMOD_Pos) /!< 0x30000000 /
		5269	#define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /!< ACCMOD[1:0] bits (Access mode) /
		5270	#define FSMC_BWTRx_ACCMOD_0 (0x1UL << FSMC_BWTRx_ACCMOD_Pos) /!< 0x10000000 /
		5271	#define FSMC_BWTRx_ACCMOD_1 (0x2UL << FSMC_BWTRx_ACCMOD_Pos) /!< 0x20000000 /
		5272
		5273
		5274
		5275	/******************************************************************************/
		5276	/* */
		5277	/* Serial Peripheral Interface */
		5278	/* */
		5279	/******************************************************************************/
		5280
		5281	/***************** Bit definition for SPI_CR1 register ******************/
		5282	#define SPI_CR1_CPHA_Pos (0U)
		5283	#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /!< 0x00000001 /
		5284	#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /!< Clock Phase /
		5285	#define SPI_CR1_CPOL_Pos (1U)
		5286	#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /!< 0x00000002 /
		5287	#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /!< Clock Polarity /
		5288	#define SPI_CR1_MSTR_Pos (2U)
		5289	#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /!< 0x00000004 /
		5290	#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /!< Master Selection /
		5291
		5292	#define SPI_CR1_BR_Pos (3U)
		5293	#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /!< 0x00000038 /
		5294	#define SPI_CR1_BR SPI_CR1_BR_Msk /!< BR[2:0] bits (Baud Rate Control) /
		5295	#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /!< 0x00000008 /
		5296	#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /!< 0x00000010 /
		5297	#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /!< 0x00000020 /
		5298
		5299	#define SPI_CR1_SPE_Pos (6U)
		5300	#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /!< 0x00000040 /
		5301	#define SPI_CR1_SPE SPI_CR1_SPE_Msk /!< SPI Enable /
		5302	#define SPI_CR1_LSBFIRST_Pos (7U)
		5303	#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /!< 0x00000080 /
		5304	#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /!< Frame Format /
		5305	#define SPI_CR1_SSI_Pos (8U)
		5306	#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /!< 0x00000100 /
		5307	#define SPI_CR1_SSI SPI_CR1_SSI_Msk /!< Internal slave select /
		5308	#define SPI_CR1_SSM_Pos (9U)
		5309	#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /!< 0x00000200 /
		5310	#define SPI_CR1_SSM SPI_CR1_SSM_Msk /!< Software slave management /
		5311	#define SPI_CR1_RXONLY_Pos (10U)
		5312	#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /!< 0x00000400 /
		5313	#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /!< Receive only /
		5314	#define SPI_CR1_DFF_Pos (11U)
		5315	#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /!< 0x00000800 /
		5316	#define SPI_CR1_DFF SPI_CR1_DFF_Msk /!< Data Frame Format /
		5317	#define SPI_CR1_CRCNEXT_Pos (12U)
		5318	#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /!< 0x00001000 /
		5319	#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /!< Transmit CRC next /
		5320	#define SPI_CR1_CRCEN_Pos (13U)
		5321	#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /!< 0x00002000 /
		5322	#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /!< Hardware CRC calculation enable /
		5323	#define SPI_CR1_BIDIOE_Pos (14U)
		5324	#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /!< 0x00004000 /
		5325	#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /!< Output enable in bidirectional mode /
		5326	#define SPI_CR1_BIDIMODE_Pos (15U)
		5327	#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /!< 0x00008000 /
		5328	#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /!< Bidirectional data mode enable /
		5329
		5330	/***************** Bit definition for SPI_CR2 register ******************/
		5331	#define SPI_CR2_RXDMAEN_Pos (0U)
		5332	#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /!< 0x00000001 /
		5333	#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /!< Rx Buffer DMA Enable /
		5334	#define SPI_CR2_TXDMAEN_Pos (1U)
		5335	#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /!< 0x00000002 /
		5336	#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /!< Tx Buffer DMA Enable /
		5337	#define SPI_CR2_SSOE_Pos (2U)
		5338	#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /!< 0x00000004 /
		5339	#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /!< SS Output Enable /
		5340	#define SPI_CR2_ERRIE_Pos (5U)
		5341	#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /!< 0x00000020 /
		5342	#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /!< Error Interrupt Enable /
		5343	#define SPI_CR2_RXNEIE_Pos (6U)
		5344	#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /!< 0x00000040 /
		5345	#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /!< RX buffer Not Empty Interrupt Enable /
		5346	#define SPI_CR2_TXEIE_Pos (7U)
		5347	#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /!< 0x00000080 /
		5348	#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /!< Tx buffer Empty Interrupt Enable /
		5349
		5350	/****************** Bit definition for SPI_SR register ******************/
		5351	#define SPI_SR_RXNE_Pos (0U)
		5352	#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /!< 0x00000001 /
		5353	#define SPI_SR_RXNE SPI_SR_RXNE_Msk /!< Receive buffer Not Empty /
		5354	#define SPI_SR_TXE_Pos (1U)
		5355	#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /!< 0x00000002 /
		5356	#define SPI_SR_TXE SPI_SR_TXE_Msk /!< Transmit buffer Empty /
		5357	#define SPI_SR_CHSIDE_Pos (2U)
		5358	#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /!< 0x00000004 /
		5359	#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /!< Channel side /
		5360	#define SPI_SR_UDR_Pos (3U)
		5361	#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /!< 0x00000008 /
		5362	#define SPI_SR_UDR SPI_SR_UDR_Msk /!< Underrun flag /
		5363	#define SPI_SR_CRCERR_Pos (4U)
		5364	#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /!< 0x00000010 /
		5365	#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /!< CRC Error flag /
		5366	#define SPI_SR_MODF_Pos (5U)
		5367	#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /!< 0x00000020 /
		5368	#define SPI_SR_MODF SPI_SR_MODF_Msk /!< Mode fault /
		5369	#define SPI_SR_OVR_Pos (6U)
		5370	#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /!< 0x00000040 /
		5371	#define SPI_SR_OVR SPI_SR_OVR_Msk /!< Overrun flag /
		5372	#define SPI_SR_BSY_Pos (7U)
		5373	#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /!< 0x00000080 /
		5374	#define SPI_SR_BSY SPI_SR_BSY_Msk /!< Busy flag /
		5375
		5376	/****************** Bit definition for SPI_DR register ******************/
		5377	#define SPI_DR_DR_Pos (0U)
		5378	#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /!< 0x0000FFFF /
		5379	#define SPI_DR_DR SPI_DR_DR_Msk /!< Data Register /
		5380
		5381	/***************** Bit definition for SPI_CRCPR register ****************/
		5382	#define SPI_CRCPR_CRCPOLY_Pos (0U)
		5383	#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /!< 0x0000FFFF /
		5384	#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /!< CRC polynomial register /
		5385
		5386	/**************** Bit definition for SPI_RXCRCR register ****************/
		5387	#define SPI_RXCRCR_RXCRC_Pos (0U)
		5388	#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /!< 0x0000FFFF /
		5389	#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /!< Rx CRC Register /
		5390
		5391	/**************** Bit definition for SPI_TXCRCR register ****************/
		5392	#define SPI_TXCRCR_TXCRC_Pos (0U)
		5393	#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /!< 0x0000FFFF /
		5394	#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /!< Tx CRC Register /
		5395
		5396
		5397
		5398	/******************************************************************************/
		5399	/* */
		5400	/* Inter-integrated Circuit Interface */
		5401	/* */
		5402	/******************************************************************************/
		5403
		5404	/***************** Bit definition for I2C_CR1 register ******************/
		5405	#define I2C_CR1_PE_Pos (0U)
		5406	#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /!< 0x00000001 /
		5407	#define I2C_CR1_PE I2C_CR1_PE_Msk /!< Peripheral Enable /
		5408	#define I2C_CR1_SMBUS_Pos (1U)
		5409	#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /!< 0x00000002 /
		5410	#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /!< SMBus Mode /
		5411	#define I2C_CR1_SMBTYPE_Pos (3U)
		5412	#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /!< 0x00000008 /
		5413	#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /!< SMBus Type /
		5414	#define I2C_CR1_ENARP_Pos (4U)
		5415	#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /!< 0x00000010 /
		5416	#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /!< ARP Enable /
		5417	#define I2C_CR1_ENPEC_Pos (5U)
		5418	#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /!< 0x00000020 /
		5419	#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /!< PEC Enable /
		5420	#define I2C_CR1_ENGC_Pos (6U)
		5421	#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /!< 0x00000040 /
		5422	#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /!< General Call Enable /
		5423	#define I2C_CR1_NOSTRETCH_Pos (7U)
		5424	#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /!< 0x00000080 /
		5425	#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /!< Clock Stretching Disable (Slave mode) /
		5426	#define I2C_CR1_START_Pos (8U)
		5427	#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /!< 0x00000100 /
		5428	#define I2C_CR1_START I2C_CR1_START_Msk /!< Start Generation /
		5429	#define I2C_CR1_STOP_Pos (9U)
		5430	#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /!< 0x00000200 /
		5431	#define I2C_CR1_STOP I2C_CR1_STOP_Msk /!< Stop Generation /
		5432	#define I2C_CR1_ACK_Pos (10U)
		5433	#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /!< 0x00000400 /
		5434	#define I2C_CR1_ACK I2C_CR1_ACK_Msk /!< Acknowledge Enable /
		5435	#define I2C_CR1_POS_Pos (11U)
		5436	#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /!< 0x00000800 /
		5437	#define I2C_CR1_POS I2C_CR1_POS_Msk /!< Acknowledge/PEC Position (for data reception) /
		5438	#define I2C_CR1_PEC_Pos (12U)
		5439	#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /!< 0x00001000 /
		5440	#define I2C_CR1_PEC I2C_CR1_PEC_Msk /!< Packet Error Checking /
		5441	#define I2C_CR1_ALERT_Pos (13U)
		5442	#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /!< 0x00002000 /
		5443	#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /!< SMBus Alert /
		5444	#define I2C_CR1_SWRST_Pos (15U)
		5445	#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /!< 0x00008000 /
		5446	#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /!< Software Reset /
		5447
		5448	/***************** Bit definition for I2C_CR2 register ******************/
		5449	#define I2C_CR2_FREQ_Pos (0U)
		5450	#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /!< 0x0000003F /
		5451	#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
		5452	#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /!< 0x00000001 /
		5453	#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /!< 0x00000002 /
		5454	#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /!< 0x00000004 /
		5455	#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /!< 0x00000008 /
		5456	#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /!< 0x00000010 /
		5457	#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /!< 0x00000020 /
		5458
		5459	#define I2C_CR2_ITERREN_Pos (8U)
		5460	#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /!< 0x00000100 /
		5461	#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /!< Error Interrupt Enable /
		5462	#define I2C_CR2_ITEVTEN_Pos (9U)
		5463	#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /!< 0x00000200 /
		5464	#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /!< Event Interrupt Enable /
		5465	#define I2C_CR2_ITBUFEN_Pos (10U)
		5466	#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /!< 0x00000400 /
		5467	#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /!< Buffer Interrupt Enable /
		5468	#define I2C_CR2_DMAEN_Pos (11U)
		5469	#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /!< 0x00000800 /
		5470	#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /!< DMA Requests Enable /
		5471	#define I2C_CR2_LAST_Pos (12U)
		5472	#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /!< 0x00001000 /
		5473	#define I2C_CR2_LAST I2C_CR2_LAST_Msk /!< DMA Last Transfer /
		5474
		5475	/***************** Bit definition for I2C_OAR1 register *****************/
		5476	#define I2C_OAR1_ADD1_7 0x000000FEU /!< Interface Address /
		5477	#define I2C_OAR1_ADD8_9 0x00000300U /!< Interface Address /
		5478
		5479	#define I2C_OAR1_ADD0_Pos (0U)
		5480	#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /!< 0x00000001 /
		5481	#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /!< Bit 0 /
		5482	#define I2C_OAR1_ADD1_Pos (1U)
		5483	#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /!< 0x00000002 /
		5484	#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /!< Bit 1 /
		5485	#define I2C_OAR1_ADD2_Pos (2U)
		5486	#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /!< 0x00000004 /
		5487	#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /!< Bit 2 /
		5488	#define I2C_OAR1_ADD3_Pos (3U)
		5489	#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /!< 0x00000008 /
		5490	#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /!< Bit 3 /
		5491	#define I2C_OAR1_ADD4_Pos (4U)
		5492	#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /!< 0x00000010 /
		5493	#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /!< Bit 4 /
		5494	#define I2C_OAR1_ADD5_Pos (5U)
		5495	#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /!< 0x00000020 /
		5496	#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /!< Bit 5 /
		5497	#define I2C_OAR1_ADD6_Pos (6U)
		5498	#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /!< 0x00000040 /
		5499	#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /!< Bit 6 /
		5500	#define I2C_OAR1_ADD7_Pos (7U)
		5501	#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /!< 0x00000080 /
		5502	#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /!< Bit 7 /
		5503	#define I2C_OAR1_ADD8_Pos (8U)
		5504	#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /!< 0x00000100 /
		5505	#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /!< Bit 8 /
		5506	#define I2C_OAR1_ADD9_Pos (9U)
		5507	#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /!< 0x00000200 /
		5508	#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /!< Bit 9 /
		5509
		5510	#define I2C_OAR1_ADDMODE_Pos (15U)
		5511	#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /!< 0x00008000 /
		5512	#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /!< Addressing Mode (Slave mode) /
		5513
		5514	/***************** Bit definition for I2C_OAR2 register *****************/
		5515	#define I2C_OAR2_ENDUAL_Pos (0U)
		5516	#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /!< 0x00000001 /
		5517	#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /!< Dual addressing mode enable /
		5518	#define I2C_OAR2_ADD2_Pos (1U)
		5519	#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /!< 0x000000FE /
		5520	#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /!< Interface address /
		5521
		5522	/****************** Bit definition for I2C_DR register ******************/
		5523	#define I2C_DR_DR_Pos (0U)
		5524	#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /!< 0x000000FF /
		5525	#define I2C_DR_DR I2C_DR_DR_Msk /!< 8-bit Data Register /
		5526
		5527	/***************** Bit definition for I2C_SR1 register ******************/
		5528	#define I2C_SR1_SB_Pos (0U)
		5529	#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /!< 0x00000001 /
		5530	#define I2C_SR1_SB I2C_SR1_SB_Msk /!< Start Bit (Master mode) /
		5531	#define I2C_SR1_ADDR_Pos (1U)
		5532	#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /!< 0x00000002 /
		5533	#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /!< Address sent (master mode)/matched (slave mode) /
		5534	#define I2C_SR1_BTF_Pos (2U)
		5535	#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /!< 0x00000004 /
		5536	#define I2C_SR1_BTF I2C_SR1_BTF_Msk /!< Byte Transfer Finished /
		5537	#define I2C_SR1_ADD10_Pos (3U)
		5538	#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /!< 0x00000008 /
		5539	#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /!< 10-bit header sent (Master mode) /
		5540	#define I2C_SR1_STOPF_Pos (4U)
		5541	#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /!< 0x00000010 /
		5542	#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /!< Stop detection (Slave mode) /
		5543	#define I2C_SR1_RXNE_Pos (6U)
		5544	#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /!< 0x00000040 /
		5545	#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /!< Data Register not Empty (receivers) /
		5546	#define I2C_SR1_TXE_Pos (7U)
		5547	#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /!< 0x00000080 /
		5548	#define I2C_SR1_TXE I2C_SR1_TXE_Msk /!< Data Register Empty (transmitters) /
		5549	#define I2C_SR1_BERR_Pos (8U)
		5550	#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /!< 0x00000100 /
		5551	#define I2C_SR1_BERR I2C_SR1_BERR_Msk /!< Bus Error /
		5552	#define I2C_SR1_ARLO_Pos (9U)
		5553	#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /!< 0x00000200 /
		5554	#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /!< Arbitration Lost (master mode) /
		5555	#define I2C_SR1_AF_Pos (10U)
		5556	#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /!< 0x00000400 /
		5557	#define I2C_SR1_AF I2C_SR1_AF_Msk /!< Acknowledge Failure /
		5558	#define I2C_SR1_OVR_Pos (11U)
		5559	#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /!< 0x00000800 /
		5560	#define I2C_SR1_OVR I2C_SR1_OVR_Msk /!< Overrun/Underrun /
		5561	#define I2C_SR1_PECERR_Pos (12U)
		5562	#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /!< 0x00001000 /
		5563	#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /!< PEC Error in reception /
		5564	#define I2C_SR1_TIMEOUT_Pos (14U)
		5565	#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /!< 0x00004000 /
		5566	#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /!< Timeout or Tlow Error /
		5567	#define I2C_SR1_SMBALERT_Pos (15U)
		5568	#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /!< 0x00008000 /
		5569	#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /!< SMBus Alert /
		5570
		5571	/***************** Bit definition for I2C_SR2 register ******************/
		5572	#define I2C_SR2_MSL_Pos (0U)
		5573	#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /!< 0x00000001 /
		5574	#define I2C_SR2_MSL I2C_SR2_MSL_Msk /!< Master/Slave /
		5575	#define I2C_SR2_BUSY_Pos (1U)
		5576	#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /!< 0x00000002 /
		5577	#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /!< Bus Busy /
		5578	#define I2C_SR2_TRA_Pos (2U)
		5579	#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /!< 0x00000004 /
		5580	#define I2C_SR2_TRA I2C_SR2_TRA_Msk /!< Transmitter/Receiver /
		5581	#define I2C_SR2_GENCALL_Pos (4U)
		5582	#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /!< 0x00000010 /
		5583	#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /!< General Call Address (Slave mode) /
		5584	#define I2C_SR2_SMBDEFAULT_Pos (5U)
		5585	#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /!< 0x00000020 /
		5586	#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /!< SMBus Device Default Address (Slave mode) /
		5587	#define I2C_SR2_SMBHOST_Pos (6U)
		5588	#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /!< 0x00000040 /
		5589	#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /!< SMBus Host Header (Slave mode) /
		5590	#define I2C_SR2_DUALF_Pos (7U)
		5591	#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /!< 0x00000080 /
		5592	#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /!< Dual Flag (Slave mode) /
		5593	#define I2C_SR2_PEC_Pos (8U)
		5594	#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /!< 0x0000FF00 /
		5595	#define I2C_SR2_PEC I2C_SR2_PEC_Msk /!< Packet Error Checking Register /
		5596
		5597	/***************** Bit definition for I2C_CCR register ******************/
		5598	#define I2C_CCR_CCR_Pos (0U)
		5599	#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /!< 0x00000FFF /
		5600	#define I2C_CCR_CCR I2C_CCR_CCR_Msk /!< Clock Control Register in Fast/Standard mode (Master mode) /
		5601	#define I2C_CCR_DUTY_Pos (14U)
		5602	#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /!< 0x00004000 /
		5603	#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /!< Fast Mode Duty Cycle /
		5604	#define I2C_CCR_FS_Pos (15U)
		5605	#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /!< 0x00008000 /
		5606	#define I2C_CCR_FS I2C_CCR_FS_Msk /!< I2C Master Mode Selection /
		5607
		5608	/**************** Bit definition for I2C_TRISE register *****************/
		5609	#define I2C_TRISE_TRISE_Pos (0U)
		5610	#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /!< 0x0000003F /
		5611	#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
		5612
		5613	/******************************************************************************/
		5614	/* */
		5615	/* Universal Synchronous Asynchronous Receiver Transmitter */
		5616	/* */
		5617	/******************************************************************************/
		5618
		5619	/***************** Bit definition for USART_SR register *****************/
		5620	#define USART_SR_PE_Pos (0U)
		5621	#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /!< 0x00000001 /
		5622	#define USART_SR_PE USART_SR_PE_Msk /!< Parity Error /
		5623	#define USART_SR_FE_Pos (1U)
		5624	#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /!< 0x00000002 /
		5625	#define USART_SR_FE USART_SR_FE_Msk /!< Framing Error /
		5626	#define USART_SR_NE_Pos (2U)
		5627	#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /!< 0x00000004 /
		5628	#define USART_SR_NE USART_SR_NE_Msk /!< Noise Error Flag /
		5629	#define USART_SR_ORE_Pos (3U)
		5630	#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /!< 0x00000008 /
		5631	#define USART_SR_ORE USART_SR_ORE_Msk /!< OverRun Error /
		5632	#define USART_SR_IDLE_Pos (4U)
		5633	#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /!< 0x00000010 /
		5634	#define USART_SR_IDLE USART_SR_IDLE_Msk /!< IDLE line detected /
		5635	#define USART_SR_RXNE_Pos (5U)
		5636	#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /!< 0x00000020 /
		5637	#define USART_SR_RXNE USART_SR_RXNE_Msk /!< Read Data Register Not Empty /
		5638	#define USART_SR_TC_Pos (6U)
		5639	#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /!< 0x00000040 /
		5640	#define USART_SR_TC USART_SR_TC_Msk /!< Transmission Complete /
		5641	#define USART_SR_TXE_Pos (7U)
		5642	#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /!< 0x00000080 /
		5643	#define USART_SR_TXE USART_SR_TXE_Msk /!< Transmit Data Register Empty /
		5644	#define USART_SR_LBD_Pos (8U)
		5645	#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /!< 0x00000100 /
		5646	#define USART_SR_LBD USART_SR_LBD_Msk /!< LIN Break Detection Flag /
		5647	#define USART_SR_CTS_Pos (9U)
		5648	#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /!< 0x00000200 /
		5649	#define USART_SR_CTS USART_SR_CTS_Msk /!< CTS Flag /
		5650
		5651	/***************** Bit definition for USART_DR register *****************/
		5652	#define USART_DR_DR_Pos (0U)
		5653	#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /!< 0x000001FF /
		5654	#define USART_DR_DR USART_DR_DR_Msk /!< Data value /
		5655
		5656	/**************** Bit definition for USART_BRR register *****************/
		5657	#define USART_BRR_DIV_Fraction_Pos (0U)
		5658	#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /!< 0x0000000F /
		5659	#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /!< Fraction of USARTDIV /
		5660	#define USART_BRR_DIV_Mantissa_Pos (4U)
		5661	#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /!< 0x0000FFF0 /
		5662	#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /!< Mantissa of USARTDIV /
		5663
		5664	/**************** Bit definition for USART_CR1 register *****************/
		5665	#define USART_CR1_SBK_Pos (0U)
		5666	#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /!< 0x00000001 /
		5667	#define USART_CR1_SBK USART_CR1_SBK_Msk /!< Send Break /
		5668	#define USART_CR1_RWU_Pos (1U)
		5669	#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /!< 0x00000002 /
		5670	#define USART_CR1_RWU USART_CR1_RWU_Msk /!< Receiver wakeup /
		5671	#define USART_CR1_RE_Pos (2U)
		5672	#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /!< 0x00000004 /
		5673	#define USART_CR1_RE USART_CR1_RE_Msk /!< Receiver Enable /
		5674	#define USART_CR1_TE_Pos (3U)
		5675	#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /!< 0x00000008 /
		5676	#define USART_CR1_TE USART_CR1_TE_Msk /!< Transmitter Enable /
		5677	#define USART_CR1_IDLEIE_Pos (4U)
		5678	#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /!< 0x00000010 /
		5679	#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /!< IDLE Interrupt Enable /
		5680	#define USART_CR1_RXNEIE_Pos (5U)
		5681	#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /!< 0x00000020 /
		5682	#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /!< RXNE Interrupt Enable /
		5683	#define USART_CR1_TCIE_Pos (6U)
		5684	#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /!< 0x00000040 /
		5685	#define USART_CR1_TCIE USART_CR1_TCIE_Msk /!< Transmission Complete Interrupt Enable /
		5686	#define USART_CR1_TXEIE_Pos (7U)
		5687	#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /!< 0x00000080 /
		5688	#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /!< PE Interrupt Enable /
		5689	#define USART_CR1_PEIE_Pos (8U)
		5690	#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /!< 0x00000100 /
		5691	#define USART_CR1_PEIE USART_CR1_PEIE_Msk /!< PE Interrupt Enable /
		5692	#define USART_CR1_PS_Pos (9U)
		5693	#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /!< 0x00000200 /
		5694	#define USART_CR1_PS USART_CR1_PS_Msk /!< Parity Selection /
		5695	#define USART_CR1_PCE_Pos (10U)
		5696	#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /!< 0x00000400 /
		5697	#define USART_CR1_PCE USART_CR1_PCE_Msk /!< Parity Control Enable /
		5698	#define USART_CR1_WAKE_Pos (11U)
		5699	#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /!< 0x00000800 /
		5700	#define USART_CR1_WAKE USART_CR1_WAKE_Msk /!< Wakeup method /
		5701	#define USART_CR1_M_Pos (12U)
		5702	#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /!< 0x00001000 /
		5703	#define USART_CR1_M USART_CR1_M_Msk /!< Word length /
		5704	#define USART_CR1_UE_Pos (13U)
		5705	#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /!< 0x00002000 /
		5706	#define USART_CR1_UE USART_CR1_UE_Msk /!< USART Enable /
		5707	#define USART_CR1_OVER8_Pos (15U)
		5708	#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /!< 0x00008000 /
		5709	#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /!< USART Oversmapling 8-bits /
		5710
		5711	/**************** Bit definition for USART_CR2 register *****************/
		5712	#define USART_CR2_ADD_Pos (0U)
		5713	#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /!< 0x0000000F /
		5714	#define USART_CR2_ADD USART_CR2_ADD_Msk /!< Address of the USART node /
		5715	#define USART_CR2_LBDL_Pos (5U)
		5716	#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /!< 0x00000020 /
		5717	#define USART_CR2_LBDL USART_CR2_LBDL_Msk /!< LIN Break Detection Length /
		5718	#define USART_CR2_LBDIE_Pos (6U)
		5719	#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /!< 0x00000040 /
		5720	#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /!< LIN Break Detection Interrupt Enable /
		5721	#define USART_CR2_LBCL_Pos (8U)
		5722	#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /!< 0x00000100 /
		5723	#define USART_CR2_LBCL USART_CR2_LBCL_Msk /!< Last Bit Clock pulse /
		5724	#define USART_CR2_CPHA_Pos (9U)
		5725	#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /!< 0x00000200 /
		5726	#define USART_CR2_CPHA USART_CR2_CPHA_Msk /!< Clock Phase /
		5727	#define USART_CR2_CPOL_Pos (10U)
		5728	#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /!< 0x00000400 /
		5729	#define USART_CR2_CPOL USART_CR2_CPOL_Msk /!< Clock Polarity /
		5730	#define USART_CR2_CLKEN_Pos (11U)
		5731	#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /!< 0x00000800 /
		5732	#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /!< Clock Enable /
		5733
		5734	#define USART_CR2_STOP_Pos (12U)
		5735	#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /!< 0x00003000 /
		5736	#define USART_CR2_STOP USART_CR2_STOP_Msk /!< STOP[1:0] bits (STOP bits) /
		5737	#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /!< 0x00001000 /
		5738	#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /!< 0x00002000 /
		5739
		5740	#define USART_CR2_LINEN_Pos (14U)
		5741	#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /!< 0x00004000 /
		5742	#define USART_CR2_LINEN USART_CR2_LINEN_Msk /!< LIN mode enable /
		5743
		5744	/**************** Bit definition for USART_CR3 register *****************/
		5745	#define USART_CR3_EIE_Pos (0U)
		5746	#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /!< 0x00000001 /
		5747	#define USART_CR3_EIE USART_CR3_EIE_Msk /!< Error Interrupt Enable /
		5748	#define USART_CR3_IREN_Pos (1U)
		5749	#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /!< 0x00000002 /
		5750	#define USART_CR3_IREN USART_CR3_IREN_Msk /!< IrDA mode Enable /
		5751	#define USART_CR3_IRLP_Pos (2U)
		5752	#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /!< 0x00000004 /
		5753	#define USART_CR3_IRLP USART_CR3_IRLP_Msk /!< IrDA Low-Power /
		5754	#define USART_CR3_HDSEL_Pos (3U)
		5755	#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /!< 0x00000008 /
		5756	#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /!< Half-Duplex Selection /
		5757	#define USART_CR3_NACK_Pos (4U)
		5758	#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /!< 0x00000010 /
		5759	#define USART_CR3_NACK USART_CR3_NACK_Msk /!< Smartcard NACK enable /
		5760	#define USART_CR3_SCEN_Pos (5U)
		5761	#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /!< 0x00000020 /
		5762	#define USART_CR3_SCEN USART_CR3_SCEN_Msk /!< Smartcard mode enable /
		5763	#define USART_CR3_DMAR_Pos (6U)
		5764	#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /!< 0x00000040 /
		5765	#define USART_CR3_DMAR USART_CR3_DMAR_Msk /!< DMA Enable Receiver /
		5766	#define USART_CR3_DMAT_Pos (7U)
		5767	#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /!< 0x00000080 /
		5768	#define USART_CR3_DMAT USART_CR3_DMAT_Msk /!< DMA Enable Transmitter /
		5769	#define USART_CR3_RTSE_Pos (8U)
		5770	#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /!< 0x00000100 /
		5771	#define USART_CR3_RTSE USART_CR3_RTSE_Msk /!< RTS Enable /
		5772	#define USART_CR3_CTSE_Pos (9U)
		5773	#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /!< 0x00000200 /
		5774	#define USART_CR3_CTSE USART_CR3_CTSE_Msk /!< CTS Enable /
		5775	#define USART_CR3_CTSIE_Pos (10U)
		5776	#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /!< 0x00000400 /
		5777	#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /!< CTS Interrupt Enable /
		5778	#define USART_CR3_ONEBIT_Pos (11U)
		5779	#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /!< 0x00000800 /
		5780	#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /!< One Bit method /
		5781
		5782	/**************** Bit definition for USART_GTPR register ****************/
		5783	#define USART_GTPR_PSC_Pos (0U)
		5784	#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /!< 0x000000FF /
		5785	#define USART_GTPR_PSC USART_GTPR_PSC_Msk /!< PSC[7:0] bits (Prescaler value) /
		5786	#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /!< 0x00000001 /
		5787	#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /!< 0x00000002 /
		5788	#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /!< 0x00000004 /
		5789	#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /!< 0x00000008 /
		5790	#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /!< 0x00000010 /
		5791	#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /!< 0x00000020 /
		5792	#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /!< 0x00000040 /
		5793	#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /!< 0x00000080 /
		5794
		5795	#define USART_GTPR_GT_Pos (8U)
		5796	#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /!< 0x0000FF00 /
		5797	#define USART_GTPR_GT USART_GTPR_GT_Msk /!< Guard time value /
		5798
		5799	/******************************************************************************/
		5800	/* */
		5801	/* Debug MCU */
		5802	/* */
		5803	/******************************************************************************/
		5804
		5805	/************** Bit definition for DBGMCU_IDCODE register ***************/
		5806	#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
		5807	#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /!< 0x00000FFF /
		5808	#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /!< Device Identifier /
		5809
		5810	#define DBGMCU_IDCODE_REV_ID_Pos (16U)
		5811	#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0xFFFF0000 /
		5812	#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /!< REV_ID[15:0] bits (Revision Identifier) /
		5813	#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00010000 /
		5814	#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00020000 /
		5815	#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00040000 /
		5816	#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00080000 /
		5817	#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00100000 /
		5818	#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00200000 /
		5819	#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00400000 /
		5820	#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00800000 /
		5821	#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x01000000 /
		5822	#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x02000000 /
		5823	#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x04000000 /
		5824	#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x08000000 /
		5825	#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x10000000 /
		5826	#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x20000000 /
		5827	#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x40000000 /
		5828	#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x80000000 /
		5829
		5830	/**************** Bit definition for DBGMCU_CR register *****************/
		5831	#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
		5832	#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /!< 0x00000001 /
		5833	#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /!< Debug Sleep Mode /
		5834	#define DBGMCU_CR_DBG_STOP_Pos (1U)
		5835	#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /!< 0x00000002 /
		5836	#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /!< Debug Stop Mode /
		5837	#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
		5838	#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /!< 0x00000004 /
		5839	#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /!< Debug Standby mode /
		5840	#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
		5841	#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /!< 0x00000020 /
		5842	#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /!< Trace Pin Assignment Control /
		5843
		5844	#define DBGMCU_CR_TRACE_MODE_Pos (6U)
		5845	#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x000000C0 /
		5846	#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
		5847	#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000040 /
		5848	#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000080 /
		5849
		5850	#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
		5851	#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /!< 0x00000100 /
		5852	#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /!< Debug Independent Watchdog stopped when Core is halted /
		5853	#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
		5854	#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /!< 0x00000200 /
		5855	#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /!< Debug Window Watchdog stopped when Core is halted /
		5856	#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
		5857	#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /!< 0x00000400 /
		5858	#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /!< TIM1 counter stopped when core is halted /
		5859	#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
		5860	#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /!< 0x00000800 /
		5861	#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /!< TIM2 counter stopped when core is halted /
		5862	#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
		5863	#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /!< 0x00001000 /
		5864	#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /!< TIM3 counter stopped when core is halted /
		5865	#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
		5866	#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /!< 0x00002000 /
		5867	#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /!< TIM4 counter stopped when core is halted /
		5868	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
		5869	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /!< 0x00008000 /
		5870	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		5871	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
		5872	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /!< 0x00010000 /
		5873	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		5874	#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
		5875	#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos) /!< 0x00040000 /
		5876	#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /!< TIM5 counter stopped when core is halted /
		5877	#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
		5878	#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos) /!< 0x00080000 /
		5879	#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /!< TIM6 counter stopped when core is halted /
		5880	#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
		5881	#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos) /!< 0x00100000 /
		5882	#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /!< TIM7 counter stopped when core is halted /
		5883	#define DBGMCU_CR_DBG_TIM15_STOP_Pos (22U)
		5884	#define DBGMCU_CR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM15_STOP_Pos) /!< 0x00400000 /
		5885	#define DBGMCU_CR_DBG_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP_Msk /!< Debug TIM15 stopped when Core is halted /
		5886	#define DBGMCU_CR_DBG_TIM16_STOP_Pos (23U)
		5887	#define DBGMCU_CR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM16_STOP_Pos) /!< 0x00800000 /
		5888	#define DBGMCU_CR_DBG_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP_Msk /!< Debug TIM16 stopped when Core is halted /
		5889	#define DBGMCU_CR_DBG_TIM17_STOP_Pos (24U)
		5890	#define DBGMCU_CR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM17_STOP_Pos) /!< 0x01000000 /
		5891	#define DBGMCU_CR_DBG_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP_Msk /!< Debug TIM17 stopped when Core is halted /
		5892	#define DBGMCU_CR_DBG_TIM12_STOP_Pos (25U)
		5893	#define DBGMCU_CR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM12_STOP_Pos) /!< 0x02000000 /
		5894	#define DBGMCU_CR_DBG_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP_Msk /!< Debug TIM12 stopped when Core is halted /
		5895	#define DBGMCU_CR_DBG_TIM13_STOP_Pos (26U)
		5896	#define DBGMCU_CR_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM13_STOP_Pos) /!< 0x04000000 /
		5897	#define DBGMCU_CR_DBG_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP_Msk /!< Debug TIM13 stopped when Core is halted /
		5898	#define DBGMCU_CR_DBG_TIM14_STOP_Pos (27U)
		5899	#define DBGMCU_CR_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM14_STOP_Pos) /!< 0x08000000 /
		5900	#define DBGMCU_CR_DBG_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP_Msk /!< Debug TIM14 stopped when Core is halted /
		5901
		5902	/******************************************************************************/
		5903	/* */
		5904	/* FLASH and Option Bytes Registers */
		5905	/* */
		5906	/******************************************************************************/
		5907	/***************** Bit definition for FLASH_ACR register ****************/
		5908	#define FLASH_ACR_HLFCYA_Pos (3U)
		5909	#define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /!< 0x00000008 /
		5910	#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /!< Flash Half Cycle Access Enable /
		5911
		5912	/**************** Bit definition for FLASH_KEYR register ****************/
		5913	#define FLASH_KEYR_FKEYR_Pos (0U)
		5914	#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /!< 0xFFFFFFFF /
		5915	#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /!< FPEC Key /
		5916
		5917	#define RDP_KEY_Pos (0U)
		5918	#define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /!< 0x000000A5 /
		5919	#define RDP_KEY RDP_KEY_Msk /!< RDP Key /
		5920	#define FLASH_KEY1_Pos (0U)
		5921	#define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /!< 0x45670123 /
		5922	#define FLASH_KEY1 FLASH_KEY1_Msk /!< FPEC Key1 /
		5923	#define FLASH_KEY2_Pos (0U)
		5924	#define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /!< 0xCDEF89AB /
		5925	#define FLASH_KEY2 FLASH_KEY2_Msk /!< FPEC Key2 /
		5926
		5927	/*************** Bit definition for FLASH_OPTKEYR register **************/
		5928	#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
		5929	#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /!< 0xFFFFFFFF /
		5930	#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /!< Option Byte Key /
		5931
		5932	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
		5933	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
		5934
		5935	/**************** Bit definition for FLASH_SR register ******************/
		5936	#define FLASH_SR_BSY_Pos (0U)
		5937	#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /!< 0x00000001 /
		5938	#define FLASH_SR_BSY FLASH_SR_BSY_Msk /!< Busy /
		5939	#define FLASH_SR_PGERR_Pos (2U)
		5940	#define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /!< 0x00000004 /
		5941	#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /!< Programming Error /
		5942	#define FLASH_SR_WRPRTERR_Pos (4U)
		5943	#define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /!< 0x00000010 /
		5944	#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /!< Write Protection Error /
		5945	#define FLASH_SR_EOP_Pos (5U)
		5946	#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /!< 0x00000020 /
		5947	#define FLASH_SR_EOP FLASH_SR_EOP_Msk /!< End of operation /
		5948
		5949	/***************** Bit definition for FLASH_CR register *****************/
		5950	#define FLASH_CR_PG_Pos (0U)
		5951	#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /!< 0x00000001 /
		5952	#define FLASH_CR_PG FLASH_CR_PG_Msk /!< Programming /
		5953	#define FLASH_CR_PER_Pos (1U)
		5954	#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /!< 0x00000002 /
		5955	#define FLASH_CR_PER FLASH_CR_PER_Msk /!< Page Erase /
		5956	#define FLASH_CR_MER_Pos (2U)
		5957	#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /!< 0x00000004 /
		5958	#define FLASH_CR_MER FLASH_CR_MER_Msk /!< Mass Erase /
		5959	#define FLASH_CR_OPTPG_Pos (4U)
		5960	#define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /!< 0x00000010 /
		5961	#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /!< Option Byte Programming /
		5962	#define FLASH_CR_OPTER_Pos (5U)
		5963	#define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /!< 0x00000020 /
		5964	#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /!< Option Byte Erase /
		5965	#define FLASH_CR_STRT_Pos (6U)
		5966	#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /!< 0x00000040 /
		5967	#define FLASH_CR_STRT FLASH_CR_STRT_Msk /!< Start /
		5968	#define FLASH_CR_LOCK_Pos (7U)
		5969	#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /!< 0x00000080 /
		5970	#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /!< Lock /
		5971	#define FLASH_CR_OPTWRE_Pos (9U)
		5972	#define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /!< 0x00000200 /
		5973	#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /!< Option Bytes Write Enable /
		5974	#define FLASH_CR_ERRIE_Pos (10U)
		5975	#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /!< 0x00000400 /
		5976	#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /!< Error Interrupt Enable /
		5977	#define FLASH_CR_EOPIE_Pos (12U)
		5978	#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /!< 0x00001000 /
		5979	#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /!< End of operation interrupt enable /
		5980
		5981	/***************** Bit definition for FLASH_AR register *****************/
		5982	#define FLASH_AR_FAR_Pos (0U)
		5983	#define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /!< 0xFFFFFFFF /
		5984	#define FLASH_AR_FAR FLASH_AR_FAR_Msk /!< Flash Address /
		5985
		5986	/**************** Bit definition for FLASH_OBR register *****************/
		5987	#define FLASH_OBR_OPTERR_Pos (0U)
		5988	#define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /!< 0x00000001 /
		5989	#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /!< Option Byte Error /
		5990	#define FLASH_OBR_RDPRT_Pos (1U)
		5991	#define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos) /!< 0x00000002 /
		5992	#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /!< Read protection /
		5993
		5994	#define FLASH_OBR_IWDG_SW_Pos (2U)
		5995	#define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /!< 0x00000004 /
		5996	#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /!< IWDG SW /
		5997	#define FLASH_OBR_nRST_STOP_Pos (3U)
		5998	#define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /!< 0x00000008 /
		5999	#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /!< nRST_STOP /
		6000	#define FLASH_OBR_nRST_STDBY_Pos (4U)
		6001	#define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /!< 0x00000010 /
		6002	#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /!< nRST_STDBY /
		6003	#define FLASH_OBR_USER_Pos (2U)
		6004	#define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /!< 0x0000001C /
		6005	#define FLASH_OBR_USER FLASH_OBR_USER_Msk /!< User Option Bytes /
		6006	#define FLASH_OBR_DATA0_Pos (10U)
		6007	#define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /!< 0x0003FC00 /
		6008	#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /!< Data0 /
		6009	#define FLASH_OBR_DATA1_Pos (18U)
		6010	#define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /!< 0x03FC0000 /
		6011	#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /!< Data1 /
		6012
		6013	/**************** Bit definition for FLASH_WRPR register ****************/
		6014	#define FLASH_WRPR_WRP_Pos (0U)
		6015	#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /!< 0xFFFFFFFF /
		6016	#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /!< Write Protect /
		6017
		6018	/----------------------------------------------------------------------------/
		6019
		6020	/**************** Bit definition for FLASH_RDP register *****************/
		6021	#define FLASH_RDP_RDP_Pos (0U)
		6022	#define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos) /!< 0x000000FF /
		6023	#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /!< Read protection option byte /
		6024	#define FLASH_RDP_nRDP_Pos (8U)
		6025	#define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos) /!< 0x0000FF00 /
		6026	#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /!< Read protection complemented option byte /
		6027
		6028	/**************** Bit definition for FLASH_USER register ****************/
		6029	#define FLASH_USER_USER_Pos (16U)
		6030	#define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos) /!< 0x00FF0000 /
		6031	#define FLASH_USER_USER FLASH_USER_USER_Msk /!< User option byte /
		6032	#define FLASH_USER_nUSER_Pos (24U)
		6033	#define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos) /!< 0xFF000000 /
		6034	#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /!< User complemented option byte /
		6035
		6036	/**************** Bit definition for FLASH_Data0 register ***************/
		6037	#define FLASH_DATA0_DATA0_Pos (0U)
		6038	#define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos) /!< 0x000000FF /
		6039	#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /!< User data storage option byte /
		6040	#define FLASH_DATA0_nDATA0_Pos (8U)
		6041	#define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos) /!< 0x0000FF00 /
		6042	#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /!< User data storage complemented option byte /
		6043
		6044	/**************** Bit definition for FLASH_Data1 register ***************/
		6045	#define FLASH_DATA1_DATA1_Pos (16U)
		6046	#define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos) /!< 0x00FF0000 /
		6047	#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /!< User data storage option byte /
		6048	#define FLASH_DATA1_nDATA1_Pos (24U)
		6049	#define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos) /!< 0xFF000000 /
		6050	#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /!< User data storage complemented option byte /
		6051
		6052	/**************** Bit definition for FLASH_WRP0 register ****************/
		6053	#define FLASH_WRP0_WRP0_Pos (0U)
		6054	#define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos) /!< 0x000000FF /
		6055	#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /!< Flash memory write protection option bytes /
		6056	#define FLASH_WRP0_nWRP0_Pos (8U)
		6057	#define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /!< 0x0000FF00 /
		6058	#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /!< Flash memory write protection complemented option bytes /
		6059
		6060	/**************** Bit definition for FLASH_WRP1 register ****************/
		6061	#define FLASH_WRP1_WRP1_Pos (16U)
		6062	#define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos) /!< 0x00FF0000 /
		6063	#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /!< Flash memory write protection option bytes /
		6064	#define FLASH_WRP1_nWRP1_Pos (24U)
		6065	#define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos) /!< 0xFF000000 /
		6066	#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /!< Flash memory write protection complemented option bytes /
		6067
		6068	/**************** Bit definition for FLASH_WRP2 register ****************/
		6069	#define FLASH_WRP2_WRP2_Pos (0U)
		6070	#define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos) /!< 0x000000FF /
		6071	#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /!< Flash memory write protection option bytes /
		6072	#define FLASH_WRP2_nWRP2_Pos (8U)
		6073	#define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos) /!< 0x0000FF00 /
		6074	#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /!< Flash memory write protection complemented option bytes /
		6075
		6076	/**************** Bit definition for FLASH_WRP3 register ****************/
		6077	#define FLASH_WRP3_WRP3_Pos (16U)
		6078	#define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos) /!< 0x00FF0000 /
		6079	#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /!< Flash memory write protection option bytes /
		6080	#define FLASH_WRP3_nWRP3_Pos (24U)
		6081	#define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /!< 0xFF000000 /
		6082	#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /!< Flash memory write protection complemented option bytes /
		6083
		6084
		6085
		6086	/**
		6087	* @}
		6088	*/
		6089
		6090	/**
		6091	* @}
		6092	*/
		6093
		6094	/** @addtogroup Exported_macro
		6095	* @{
		6096	*/
		6097
		6098	/**************************** ADC Instances *******************************/
		6099	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
		6100
		6101	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
		6102
		6103	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		6104
		6105	/**************************** CEC Instances *******************************/
		6106	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
		6107
		6108	/**************************** CRC Instances *******************************/
		6109	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		6110
		6111	/**************************** DAC Instances *******************************/
		6112	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
		6113
		6114	/**************************** DMA Instances *******************************/
		6115	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		6116	((INSTANCE) == DMA1_Channel2) \|\| \
		6117	((INSTANCE) == DMA1_Channel3) \|\| \
		6118	((INSTANCE) == DMA1_Channel4) \|\| \
		6119	((INSTANCE) == DMA1_Channel5) \|\| \
		6120	((INSTANCE) == DMA1_Channel6) \|\| \
		6121	((INSTANCE) == DMA1_Channel7) \|\| \
		6122	((INSTANCE) == DMA2_Channel1) \|\| \
		6123	((INSTANCE) == DMA2_Channel2) \|\| \
		6124	((INSTANCE) == DMA2_Channel3) \|\| \
		6125	((INSTANCE) == DMA2_Channel4) \|\| \
		6126	((INSTANCE) == DMA2_Channel5))
		6127
		6128	/***************************** GPIO Instances *****************************/
		6129	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		6130	((INSTANCE) == GPIOB) \|\| \
		6131	((INSTANCE) == GPIOC) \|\| \
		6132	((INSTANCE) == GPIOD) \|\| \
		6133	((INSTANCE) == GPIOE) \|\| \
		6134	((INSTANCE) == GPIOF) \|\| \
		6135	((INSTANCE) == GPIOG))
		6136
		6137	/************************** GPIO Alternate Function Instances *************/
		6138	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		6139
		6140	/************************** GPIO Lock Instances ***************************/
		6141	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		6142
		6143	/****************************** I2C Instances *****************************/
		6144	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		6145	((INSTANCE) == I2C2))
		6146
		6147	/***************************** SMBUS Instances ****************************/
		6148	#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
		6149
		6150	/**************************** IWDG Instances ******************************/
		6151	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		6152
		6153	/****************************** SPI Instances *****************************/
		6154	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		6155	((INSTANCE) == SPI2) \|\| \
		6156	((INSTANCE) == SPI3))
		6157
		6158	/**************************** START TIM Instances *************************/
		6159	/**************************** TIM Instances *******************************/
		6160	#define IS_TIM_INSTANCE(INSTANCE)\
		6161	(((INSTANCE) == TIM1) \|\| \
		6162	((INSTANCE) == TIM2) \|\| \
		6163	((INSTANCE) == TIM3) \|\| \
		6164	((INSTANCE) == TIM4) \|\| \
		6165	((INSTANCE) == TIM5) \|\| \
		6166	((INSTANCE) == TIM6) \|\| \
		6167	((INSTANCE) == TIM7) \|\| \
		6168	((INSTANCE) == TIM12) \|\| \
		6169	((INSTANCE) == TIM13) \|\| \
		6170	((INSTANCE) == TIM14) \|\| \
		6171	((INSTANCE) == TIM15) \|\| \
		6172	((INSTANCE) == TIM16) \|\| \
		6173	((INSTANCE) == TIM17))
		6174
		6175	#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
		6176
		6177	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
		6178	(((INSTANCE) == TIM1) \|\| \
		6179	((INSTANCE) == TIM2) \|\| \
		6180	((INSTANCE) == TIM3) \|\| \
		6181	((INSTANCE) == TIM4) \|\| \
		6182	((INSTANCE) == TIM5) \|\| \
		6183	((INSTANCE) == TIM12) \|\| \
		6184	((INSTANCE) == TIM13) \|\| \
		6185	((INSTANCE) == TIM14) \|\| \
		6186	((INSTANCE) == TIM15) \|\| \
		6187	((INSTANCE) == TIM16) \|\| \
		6188	((INSTANCE) == TIM17))
		6189
		6190	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
		6191	(((INSTANCE) == TIM1) \|\| \
		6192	((INSTANCE) == TIM2) \|\| \
		6193	((INSTANCE) == TIM3) \|\| \
		6194	((INSTANCE) == TIM4) \|\| \
		6195	((INSTANCE) == TIM5) \|\| \
		6196	((INSTANCE) == TIM12) \|\| \
		6197	((INSTANCE) == TIM15))
		6198
		6199	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
		6200	(((INSTANCE) == TIM1) \|\| \
		6201	((INSTANCE) == TIM2) \|\| \
		6202	((INSTANCE) == TIM3) \|\| \
		6203	((INSTANCE) == TIM4) \|\| \
		6204	((INSTANCE) == TIM5))
		6205
		6206	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
		6207	(((INSTANCE) == TIM1) \|\| \
		6208	((INSTANCE) == TIM2) \|\| \
		6209	((INSTANCE) == TIM3) \|\| \
		6210	((INSTANCE) == TIM4) \|\| \
		6211	((INSTANCE) == TIM5))
		6212
		6213	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
		6214	(((INSTANCE) == TIM1) \|\| \
		6215	((INSTANCE) == TIM2) \|\| \
		6216	((INSTANCE) == TIM3) \|\| \
		6217	((INSTANCE) == TIM4) \|\| \
		6218	((INSTANCE) == TIM5))
		6219
		6220	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
		6221	(((INSTANCE) == TIM1) \|\| \
		6222	((INSTANCE) == TIM2) \|\| \
		6223	((INSTANCE) == TIM3) \|\| \
		6224	((INSTANCE) == TIM4) \|\| \
		6225	((INSTANCE) == TIM5))
		6226
		6227	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
		6228	(((INSTANCE) == TIM1) \|\| \
		6229	((INSTANCE) == TIM2) \|\| \
		6230	((INSTANCE) == TIM3) \|\| \
		6231	((INSTANCE) == TIM4) \|\| \
		6232	((INSTANCE) == TIM5) \|\| \
		6233	((INSTANCE) == TIM12) \|\| \
		6234	((INSTANCE) == TIM15))
		6235
		6236	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
		6237	(((INSTANCE) == TIM1) \|\| \
		6238	((INSTANCE) == TIM2) \|\| \
		6239	((INSTANCE) == TIM3) \|\| \
		6240	((INSTANCE) == TIM4) \|\| \
		6241	((INSTANCE) == TIM5) \|\| \
		6242	((INSTANCE) == TIM12) \|\| \
		6243	((INSTANCE) == TIM15))
		6244
		6245	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
		6246	(((INSTANCE) == TIM1) \|\| \
		6247	((INSTANCE) == TIM2) \|\| \
		6248	((INSTANCE) == TIM3) \|\| \
		6249	((INSTANCE) == TIM4) \|\| \
		6250	((INSTANCE) == TIM5))
		6251
		6252	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
		6253	(((INSTANCE) == TIM1) \|\| \
		6254	((INSTANCE) == TIM2) \|\| \
		6255	((INSTANCE) == TIM3) \|\| \
		6256	((INSTANCE) == TIM4) \|\| \
		6257	((INSTANCE) == TIM5))
		6258
		6259	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
		6260	(((INSTANCE) == TIM1) \|\| \
		6261	((INSTANCE) == TIM2) \|\| \
		6262	((INSTANCE) == TIM3) \|\| \
		6263	((INSTANCE) == TIM4) \|\| \
		6264	((INSTANCE) == TIM5))
		6265
		6266	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
		6267	(((INSTANCE) == TIM1) \|\| \
		6268	((INSTANCE) == TIM2) \|\| \
		6269	((INSTANCE) == TIM3) \|\| \
		6270	((INSTANCE) == TIM4) \|\| \
		6271	((INSTANCE) == TIM5) \|\| \
		6272	((INSTANCE) == TIM6) \|\| \
		6273	((INSTANCE) == TIM7) \|\| \
		6274	((INSTANCE) == TIM12) \|\| \
		6275	((INSTANCE) == TIM15))
		6276
		6277	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
		6278	(((INSTANCE) == TIM1) \|\| \
		6279	((INSTANCE) == TIM2) \|\| \
		6280	((INSTANCE) == TIM3) \|\| \
		6281	((INSTANCE) == TIM4) \|\| \
		6282	((INSTANCE) == TIM5) \|\| \
		6283	((INSTANCE) == TIM12) \|\| \
		6284	((INSTANCE) == TIM15))
		6285
		6286	#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
		6287
		6288	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
		6289	(((INSTANCE) == TIM1) \|\| \
		6290	((INSTANCE) == TIM2) \|\| \
		6291	((INSTANCE) == TIM3) \|\| \
		6292	((INSTANCE) == TIM4) \|\| \
		6293	((INSTANCE) == TIM5) \|\| \
		6294	((INSTANCE) == TIM15) \|\| \
		6295	((INSTANCE) == TIM16) \|\| \
		6296	((INSTANCE) == TIM17))
		6297
		6298	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
		6299	(((INSTANCE) == TIM1) \|\| \
		6300	((INSTANCE) == TIM15) \|\| \
		6301	((INSTANCE) == TIM16) \|\| \
		6302	((INSTANCE) == TIM17))
		6303
		6304	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		6305	((((INSTANCE) == TIM1) && \
		6306	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6307	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6308	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6309	((CHANNEL) == TIM_CHANNEL_4))) \
		6310	\|\| \
		6311	(((INSTANCE) == TIM2) && \
		6312	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6313	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6314	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6315	((CHANNEL) == TIM_CHANNEL_4))) \
		6316	\|\| \
		6317	(((INSTANCE) == TIM3) && \
		6318	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6319	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6320	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6321	((CHANNEL) == TIM_CHANNEL_4))) \
		6322	\|\| \
		6323	(((INSTANCE) == TIM4) && \
		6324	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6325	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6326	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6327	((CHANNEL) == TIM_CHANNEL_4))) \
		6328	\|\| \
		6329	(((INSTANCE) == TIM5) && \
		6330	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6331	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6332	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		6333	((CHANNEL) == TIM_CHANNEL_4))) \
		6334	\|\| \
		6335	(((INSTANCE) == TIM12) && \
		6336	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6337	((CHANNEL) == TIM_CHANNEL_2))) \
		6338	\|\| \
		6339	(((INSTANCE) == TIM13) && \
		6340	(((CHANNEL) == TIM_CHANNEL_1))) \
		6341	\|\| \
		6342	(((INSTANCE) == TIM14) && \
		6343	(((CHANNEL) == TIM_CHANNEL_1))) \
		6344	\|\| \
		6345	(((INSTANCE) == TIM15) && \
		6346	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6347	((CHANNEL) == TIM_CHANNEL_2))) \
		6348	\|\| \
		6349	(((INSTANCE) == TIM16) && \
		6350	(((CHANNEL) == TIM_CHANNEL_1))) \
		6351	\|\| \
		6352	(((INSTANCE) == TIM17) && \
		6353	(((CHANNEL) == TIM_CHANNEL_1))))
		6354
		6355	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
		6356	((((INSTANCE) == TIM1) && \
		6357	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		6358	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		6359	((CHANNEL) == TIM_CHANNEL_3))) \
		6360	\|\| \
		6361	(((INSTANCE) == TIM15) && \
		6362	((CHANNEL) == TIM_CHANNEL_1)) \
		6363	\|\| \
		6364	(((INSTANCE) == TIM16) && \
		6365	((CHANNEL) == TIM_CHANNEL_1)) \
		6366	\|\| \
		6367	(((INSTANCE) == TIM17) && \
		6368	((CHANNEL) == TIM_CHANNEL_1)))
		6369
		6370	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
		6371	(((INSTANCE) == TIM1) \|\| \
		6372	((INSTANCE) == TIM2) \|\| \
		6373	((INSTANCE) == TIM3) \|\| \
		6374	((INSTANCE) == TIM4) \|\| \
		6375	((INSTANCE) == TIM5))
		6376
		6377	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
		6378	(((INSTANCE) == TIM1) \|\| \
		6379	((INSTANCE) == TIM15) \|\| \
		6380	((INSTANCE) == TIM16) \|\| \
		6381	((INSTANCE) == TIM17))
		6382
		6383	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
		6384	(((INSTANCE) == TIM1) \|\| \
		6385	((INSTANCE) == TIM2) \|\| \
		6386	((INSTANCE) == TIM3) \|\| \
		6387	((INSTANCE) == TIM4) \|\| \
		6388	((INSTANCE) == TIM5) \|\| \
		6389	((INSTANCE) == TIM12) \|\| \
		6390	((INSTANCE) == TIM13) \|\| \
		6391	((INSTANCE) == TIM14) \|\| \
		6392	((INSTANCE) == TIM15) \|\| \
		6393	((INSTANCE) == TIM16) \|\| \
		6394	((INSTANCE) == TIM17))
		6395
		6396	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
		6397	(((INSTANCE) == TIM1) \|\| \
		6398	((INSTANCE) == TIM2) \|\| \
		6399	((INSTANCE) == TIM3) \|\| \
		6400	((INSTANCE) == TIM4) \|\| \
		6401	((INSTANCE) == TIM5) \|\| \
		6402	((INSTANCE) == TIM6) \|\| \
		6403	((INSTANCE) == TIM7) \|\| \
		6404	((INSTANCE) == TIM15) \|\| \
		6405	((INSTANCE) == TIM16) \|\| \
		6406	((INSTANCE) == TIM17))
		6407
		6408	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
		6409	(((INSTANCE) == TIM1) \|\| \
		6410	((INSTANCE) == TIM2) \|\| \
		6411	((INSTANCE) == TIM3) \|\| \
		6412	((INSTANCE) == TIM4) \|\| \
		6413	((INSTANCE) == TIM5) \|\| \
		6414	((INSTANCE) == TIM15) \|\| \
		6415	((INSTANCE) == TIM16) \|\| \
		6416	((INSTANCE) == TIM17))
		6417
		6418	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
		6419	(((INSTANCE) == TIM1) \|\| \
		6420	((INSTANCE) == TIM15) \|\| \
		6421	((INSTANCE) == TIM16) \|\| \
		6422	((INSTANCE) == TIM17))
		6423
		6424	#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
		6425	((INSTANCE) == TIM2) \|\| \
		6426	((INSTANCE) == TIM3) \|\| \
		6427	((INSTANCE) == TIM4) \|\| \
		6428	((INSTANCE) == TIM5))
		6429
		6430	#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
		6431	((INSTANCE) == TIM2) \|\| \
		6432	((INSTANCE) == TIM3) \|\| \
		6433	((INSTANCE) == TIM4) \|\| \
		6434	((INSTANCE) == TIM5))
		6435
		6436	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
		6437
		6438	/**************************** END TIM Instances ***************************/
		6439
		6440
		6441	/****************** USART Instances : Synchronous mode ********************/
		6442	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6443	((INSTANCE) == USART2) \|\| \
		6444	((INSTANCE) == USART3))
		6445
		6446	/****************** UART Instances : Asynchronous mode ********************/
		6447	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6448	((INSTANCE) == USART2) \|\| \
		6449	((INSTANCE) == USART3) \|\| \
		6450	((INSTANCE) == UART4) \|\| \
		6451	((INSTANCE) == UART5))
		6452
		6453	/****************** UART Instances : Half-Duplex mode ********************/
		6454	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6455	((INSTANCE) == USART2) \|\| \
		6456	((INSTANCE) == USART3) \|\| \
		6457	((INSTANCE) == UART4) \|\| \
		6458	((INSTANCE) == UART5))
		6459
		6460	/****************** UART Instances : LIN mode ********************/
		6461	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6462	((INSTANCE) == USART2) \|\| \
		6463	((INSTANCE) == USART3) \|\| \
		6464	((INSTANCE) == UART4) \|\| \
		6465	((INSTANCE) == UART5))
		6466
		6467	/**************** UART Instances : Hardware Flow control ******************/
		6468	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6469	((INSTANCE) == USART2) \|\| \
		6470	((INSTANCE) == USART3))
		6471
		6472	/******************* UART Instances : Smard card mode *********************/
		6473	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6474	((INSTANCE) == USART2) \|\| \
		6475	((INSTANCE) == USART3))
		6476
		6477	/********************* UART Instances : IRDA mode *************************/
		6478	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6479	((INSTANCE) == USART2) \|\| \
		6480	((INSTANCE) == USART3) \|\| \
		6481	((INSTANCE) == UART4) \|\| \
		6482	((INSTANCE) == UART5))
		6483
		6484	/*************** UART Instances : Multi-Processor mode ********************/
		6485	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6486	((INSTANCE) == USART2) \|\| \
		6487	((INSTANCE) == USART3) \|\| \
		6488	((INSTANCE) == UART4) \|\| \
		6489	((INSTANCE) == UART5))
		6490
		6491	/*************** UART Instances : DMA mode available ********************/
		6492	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		6493	((INSTANCE) == USART2) \|\| \
		6494	((INSTANCE) == USART3) \|\| \
		6495	((INSTANCE) == UART4) \|\| \
		6496	((INSTANCE) == UART5))
		6497
		6498	/**************************** RTC Instances *******************************/
		6499	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		6500
		6501	/************************** WWDG Instances ***************************/
		6502	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		6503
		6504
		6505
		6506
		6507	#define RCC_HSE_MIN 4000000U
		6508	#define RCC_HSE_MAX 26000000U
		6509
		6510	#define RCC_MAX_FREQUENCY 24000000U
		6511
		6512	/**
		6513	* @}
		6514	*/
		6515	/******************************************************************************/
		6516	/* For a painless codes migration between the STM32F1xx device product */
		6517	/* lines, the aliases defined below are put in place to overcome the */
		6518	/* differences in the interrupt handlers and IRQn definitions. */
		6519	/* No need to update developed interrupt code when moving across */
		6520	/* product lines within the same STM32F1 Family */
		6521	/******************************************************************************/
		6522
		6523	/* Aliases for __IRQn */
		6524	#define ADC1_2_IRQn ADC1_IRQn
		6525	#define USBWakeUp_IRQn CEC_IRQn
		6526	#define OTG_FS_WKUP_IRQn CEC_IRQn
		6527	#define TIM8_BRK_IRQn TIM12_IRQn
		6528	#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
		6529	#define TIM8_UP_TIM13_IRQn TIM13_IRQn
		6530	#define TIM8_UP_IRQn TIM13_IRQn
		6531	#define TIM8_TRG_COM_IRQn TIM14_IRQn
		6532	#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
		6533	#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
		6534	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
		6535	#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
		6536	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
		6537	#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
		6538	#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
		6539	#define TIM10_IRQn TIM1_UP_TIM16_IRQn
		6540	#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
		6541	#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
		6542	#define TIM6_IRQn TIM6_DAC_IRQn
		6543
		6544
		6545	/* Aliases for __IRQHandler */
		6546	#define ADC1_2_IRQHandler ADC1_IRQHandler
		6547	#define USBWakeUp_IRQHandler CEC_IRQHandler
		6548	#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
		6549	#define TIM8_BRK_IRQHandler TIM12_IRQHandler
		6550	#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
		6551	#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
		6552	#define TIM8_UP_IRQHandler TIM13_IRQHandler
		6553	#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
		6554	#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
		6555	#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
		6556	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
		6557	#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
		6558	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		6559	#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		6560	#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
		6561	#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
		6562	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
		6563	#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
		6564	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
		6565
		6566
		6567	/**
		6568	* @}
		6569	*/
		6570
		6571	/**
		6572	* @}
		6573	*/
		6574
		6575
		6576	#ifdef __cplusplus
		6577	}
		6578	#endif /* __cplusplus */
		6579
		6580	#endif /* __STM32F100xE_H */
		6581
		6582
		6583
		6584	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories dashGPS

(root)/branches/dashGPS-bmp/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h – Rev 18