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/* ----------------------------------------------------------------------
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 * Project:      CMSIS DSP Library
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 * Title:        arm_power_q31.c
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 * Description:  Sum of the squares of the elements of a Q31 vector
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 *
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 * $Date:        27. January 2017
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 * $Revision:    V.1.5.1
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 *
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 * Target Processor: Cortex-M cores
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 * -------------------------------------------------------------------- */
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/*
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 * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
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 *
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 * SPDX-License-Identifier: Apache-2.0
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 *
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 * Licensed under the Apache License, Version 2.0 (the License); you may
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 * not use this file except in compliance with the License.
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 * You may obtain a copy of the License at
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 *
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 * www.apache.org/licenses/LICENSE-2.0
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 *
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 * Unless required by applicable law or agreed to in writing, software
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 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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 * See the License for the specific language governing permissions and
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 * limitations under the License.
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 */
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#include "arm_math.h"
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/**
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 * @ingroup groupStats
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 */
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/**
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 * @addtogroup power
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 * @{
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 */
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/**
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 * @brief Sum of the squares of the elements of a Q31 vector.
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 * @param[in]       *pSrc points to the input vector
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 * @param[in]       blockSize length of the input vector
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 * @param[out]      *pResult sum of the squares value returned here
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 * @return none.
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 *
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 * @details
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 * <b>Scaling and Overflow Behavior:</b>
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 *
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 * \par
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 * The function is implemented using a 64-bit internal accumulator.
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 * The input is represented in 1.31 format.
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 * Intermediate multiplication yields a 2.62 format, and this
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 * result is truncated to 2.48 format by discarding the lower 14 bits.
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 * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
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 * With 15 guard bits in the accumulator, there is no risk of overflow, and the
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 * full precision of the intermediate multiplication is preserved.
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 * Finally, the return result is in 16.48 format.
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 *
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 */
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void arm_power_q31(
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  q31_t * pSrc,
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  uint32_t blockSize,
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  q63_t * pResult)
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{
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  q63_t sum = 0;                                 /* Temporary result storage */
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  q31_t in;
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  uint32_t blkCnt;                               /* loop counter */
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#if defined (ARM_MATH_DSP)
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  /* Run the below code for Cortex-M4 and Cortex-M3 */
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  /*loop Unrolling */
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  blkCnt = blockSize >> 2U;
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  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
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   ** a second loop below computes the remaining 1 to 3 samples. */
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  while (blkCnt > 0U)
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  {
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    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
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    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
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    in = *pSrc++;
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    sum += ((q63_t) in * in) >> 14U;
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    in = *pSrc++;
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    sum += ((q63_t) in * in) >> 14U;
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    in = *pSrc++;
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    sum += ((q63_t) in * in) >> 14U;
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    in = *pSrc++;
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    sum += ((q63_t) in * in) >> 14U;
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    /* Decrement the loop counter */
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    blkCnt--;
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  }
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  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
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   ** No loop unrolling is used. */
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  blkCnt = blockSize % 0x4U;
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#else
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  /* Run the below code for Cortex-M0 */
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  /* Loop over blockSize number of values */
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  blkCnt = blockSize;
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#endif /* #if defined (ARM_MATH_DSP) */
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  while (blkCnt > 0U)
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  {
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    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
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    /* Compute Power and then store the result in a temporary variable, sum. */
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    in = *pSrc++;
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    sum += ((q63_t) in * in) >> 14U;
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    /* Decrement the loop counter */
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    blkCnt--;
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  }
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  /* Store the results in 16.48 format  */
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  *pResult = sum;
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}
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/**
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 * @} end of power group
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 */