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| 56 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_ll_rcc.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief RCC LL module driver. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright(c) 2017 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | #if defined(USE_FULL_LL_DRIVER) |
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| 20 | |||
| 21 | /* Includes ------------------------------------------------------------------*/ |
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| 22 | #include "stm32l1xx_ll_rcc.h" |
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| 23 | /** @addtogroup STM32L1xx_LL_Driver |
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| 24 | * @{ |
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| 25 | */ |
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| 26 | |||
| 27 | #if defined(RCC) |
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| 28 | |||
| 29 | /** @defgroup RCC_LL RCC |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | |||
| 33 | /* Private types -------------------------------------------------------------*/ |
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| 34 | /* Private variables ---------------------------------------------------------*/ |
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| 35 | |||
| 36 | /* Private constants ---------------------------------------------------------*/ |
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| 37 | /* Private macros ------------------------------------------------------------*/ |
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| 38 | /* Private function prototypes -----------------------------------------------*/ |
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| 39 | /** @defgroup RCC_LL_Private_Functions RCC Private functions |
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| 40 | * @{ |
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| 41 | */ |
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| 42 | uint32_t RCC_GetSystemClockFreq(void); |
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| 43 | uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); |
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| 44 | uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); |
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| 45 | uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); |
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| 46 | uint32_t RCC_PLL_GetFreqDomain_SYS(void); |
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| 47 | /** |
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| 48 | * @} |
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| 49 | */ |
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| 50 | |||
| 51 | |||
| 52 | /* Exported functions --------------------------------------------------------*/ |
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| 53 | /** @addtogroup RCC_LL_Exported_Functions |
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| 54 | * @{ |
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| 55 | */ |
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| 56 | |||
| 57 | /** @addtogroup RCC_LL_EF_Init |
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| 58 | * @{ |
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| 59 | */ |
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| 60 | |||
| 61 | /** |
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| 62 | * @brief Reset the RCC clock configuration to the default reset state. |
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| 63 | * @note The default reset state of the clock configuration is given below: |
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| 64 | * - MSI ON and used as system clock source |
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| 65 | * - HSE, HSI and PLL OFF |
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| 66 | * - AHB, APB1 and APB2 prescaler set to 1. |
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| 67 | * - CSS, MCO OFF |
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| 68 | * - All interrupts disabled |
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| 69 | * @note This function doesn't modify the configuration of the |
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| 70 | * - Peripheral clocks |
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| 71 | * - LSI, LSE and RTC clocks |
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| 72 | * @retval An ErrorStatus enumeration value: |
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| 73 | * - SUCCESS: RCC registers are de-initialized |
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| 74 | * - ERROR: not applicable |
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| 75 | */ |
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| 76 | ErrorStatus LL_RCC_DeInit(void) |
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| 77 | { |
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| 78 | __IO uint32_t vl_mask; |
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| 79 | |||
| 80 | /* Set MSION bit */ |
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| 81 | LL_RCC_MSI_Enable(); |
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| 82 | |||
| 83 | /* Insure MSIRDY bit is set before writing default MSIRANGE value */ |
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| 84 | while (LL_RCC_MSI_IsReady() == 0U) |
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| 85 | { |
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| 86 | __NOP(); |
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| 87 | } |
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| 88 | |||
| 89 | /* Set MSIRANGE default value */ |
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| 90 | LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5); |
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| 91 | /* Set MSITRIM bits to the reset value*/ |
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| 92 | LL_RCC_MSI_SetCalibTrimming(0U); |
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| 93 | |||
| 94 | /* Set HSITRIM bits to the reset value*/ |
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| 95 | LL_RCC_HSI_SetCalibTrimming(0x10U); |
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| 96 | |||
| 97 | /* Reset SW, HPRE, PPRE and MCOSEL bits */ |
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| 98 | vl_mask = 0xFFFFFFFFU; |
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| 99 | CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL)); |
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| 100 | LL_RCC_WriteReg(CFGR, vl_mask); |
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| 101 | |||
| 102 | /* Read CR register */ |
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| 103 | vl_mask = LL_RCC_ReadReg(CR); |
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| 104 | |||
| 105 | /* Reset HSION, HSEON, CSSON, PLLON bits */ |
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| 106 | CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION)); |
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| 107 | LL_RCC_WriteReg(CR, vl_mask); |
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| 108 | |||
| 109 | /* Reset HSEBYP bit */ |
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| 110 | LL_RCC_HSE_DisableBypass(); |
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| 111 | |||
| 112 | /* Insure PLL is disabled before to reset PLLSRC/PLLMUL/PLLDIV in CFGR register */ |
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| 113 | while(LL_RCC_PLL_IsReady() != 0U) {}; |
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| 114 | |||
| 115 | /* Reset CFGR register */ |
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| 116 | LL_RCC_WriteReg(CFGR, 0x00000000U); |
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| 117 | |||
| 118 | /* Disable all interrupts */ |
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| 119 | LL_RCC_WriteReg(CIR, 0x00000000U); |
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| 120 | |||
| 121 | /* Clear pending flags */ |
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| 122 | #if defined(RCC_LSECSS_SUPPORT) |
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| 123 | vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | \ |
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| 124 | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_LSECSSC | LL_RCC_CIR_CSSC); |
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| 125 | #else |
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| 126 | vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | \ |
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| 127 | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_CSSC); |
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| 128 | #endif /* RCC_LSECSS_SUPPORT */ |
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| 129 | LL_RCC_WriteReg(CIR, vl_mask); |
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| 130 | |||
| 131 | /* Clear reset flags */ |
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| 132 | LL_RCC_ClearResetFlags(); |
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| 133 | |||
| 134 | return SUCCESS; |
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| 135 | } |
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| 136 | |||
| 137 | /** |
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| 138 | * @} |
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| 139 | */ |
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| 140 | |||
| 141 | /** @addtogroup RCC_LL_EF_Get_Freq |
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| 142 | * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks |
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| 143 | * and different peripheral clocks available on the device. |
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| 144 | * @note If SYSCLK source is MSI, function returns values based on MSI clock(*) |
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| 145 | * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) |
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| 146 | * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) |
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| 147 | * @note If SYSCLK source is PLL, function returns values based on |
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| 148 | * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. |
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| 149 | * @note (*) MSI clock depends on the selected MSI range but the real value |
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| 150 | * may vary depending on the variations in voltage and temperature. |
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| 151 | * @note (**) HSI_VALUE is a defined constant but the real value may vary |
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| 152 | * depending on the variations in voltage and temperature. |
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| 153 | * @note (***) HSE_VALUE is a defined constant, user has to ensure that |
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| 154 | * HSE_VALUE is same as the real frequency of the crystal used. |
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| 155 | * Otherwise, this function may have wrong result. |
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| 156 | * @note The result of this function could be incorrect when using fractional |
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| 157 | * value for HSE crystal. |
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| 158 | * @note This function can be used by the user application to compute the |
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| 159 | * baud-rate for the communication peripherals or configure other parameters. |
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| 160 | * @{ |
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| 161 | */ |
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| 162 | |||
| 163 | /** |
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| 164 | * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks |
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| 165 | * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function |
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| 166 | * must be called to update structure fields. Otherwise, any |
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| 167 | * configuration based on this function will be incorrect. |
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| 168 | * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies |
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| 169 | * @retval None |
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| 170 | */ |
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| 171 | void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) |
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| 172 | { |
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| 173 | /* Get SYSCLK frequency */ |
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| 174 | RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); |
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| 175 | |||
| 176 | /* HCLK clock frequency */ |
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| 177 | RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); |
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| 178 | |||
| 179 | /* PCLK1 clock frequency */ |
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| 180 | RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); |
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| 181 | |||
| 182 | /* PCLK2 clock frequency */ |
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| 183 | RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); |
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| 184 | } |
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| 185 | |||
| 186 | /** |
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| 187 | * @} |
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| 188 | */ |
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| 189 | |||
| 190 | /** |
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| 191 | * @} |
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| 192 | */ |
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| 193 | |||
| 194 | /** @addtogroup RCC_LL_Private_Functions |
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| 195 | * @{ |
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| 196 | */ |
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| 197 | |||
| 198 | /** |
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| 199 | * @brief Return SYSTEM clock frequency |
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| 200 | * @retval SYSTEM clock frequency (in Hz) |
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| 201 | */ |
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| 202 | uint32_t RCC_GetSystemClockFreq(void) |
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| 203 | { |
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| 204 | uint32_t frequency; |
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| 205 | |||
| 206 | /* Get SYSCLK source -------------------------------------------------------*/ |
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| 207 | switch (LL_RCC_GetSysClkSource()) |
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| 208 | { |
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| 209 | case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ |
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| 210 | frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); |
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| 211 | break; |
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| 212 | |||
| 213 | case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ |
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| 214 | frequency = HSI_VALUE; |
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| 215 | break; |
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| 216 | |||
| 217 | case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ |
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| 218 | frequency = HSE_VALUE; |
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| 219 | break; |
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| 220 | |||
| 221 | case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ |
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| 222 | frequency = RCC_PLL_GetFreqDomain_SYS(); |
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| 223 | break; |
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| 224 | |||
| 225 | default: |
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| 226 | frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); |
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| 227 | break; |
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| 228 | } |
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| 229 | |||
| 230 | return frequency; |
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| 231 | } |
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| 232 | |||
| 233 | /** |
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| 234 | * @brief Return HCLK clock frequency |
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| 235 | * @param SYSCLK_Frequency SYSCLK clock frequency |
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| 236 | * @retval HCLK clock frequency (in Hz) |
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| 237 | */ |
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| 238 | uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) |
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| 239 | { |
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| 240 | /* HCLK clock frequency */ |
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| 241 | return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); |
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| 242 | } |
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| 243 | |||
| 244 | /** |
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| 245 | * @brief Return PCLK1 clock frequency |
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| 246 | * @param HCLK_Frequency HCLK clock frequency |
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| 247 | * @retval PCLK1 clock frequency (in Hz) |
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| 248 | */ |
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| 249 | uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) |
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| 250 | { |
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| 251 | /* PCLK1 clock frequency */ |
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| 252 | return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); |
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| 253 | } |
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| 254 | |||
| 255 | /** |
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| 256 | * @brief Return PCLK2 clock frequency |
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| 257 | * @param HCLK_Frequency HCLK clock frequency |
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| 258 | * @retval PCLK2 clock frequency (in Hz) |
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| 259 | */ |
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| 260 | uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) |
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| 261 | { |
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| 262 | /* PCLK2 clock frequency */ |
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| 263 | return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); |
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| 264 | } |
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| 265 | |||
| 266 | /** |
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| 267 | * @brief Return PLL clock frequency used for system domain |
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| 268 | * @retval PLL clock frequency (in Hz) |
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| 269 | */ |
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| 270 | uint32_t RCC_PLL_GetFreqDomain_SYS(void) |
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| 271 | { |
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| 272 | uint32_t pllsource, pllinputfreq; |
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| 273 | |||
| 274 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ |
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| 275 | |||
| 276 | /* Get PLL source */ |
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| 277 | pllsource = LL_RCC_PLL_GetMainSource(); |
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| 278 | |||
| 279 | switch (pllsource) |
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| 280 | { |
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| 281 | case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ |
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| 282 | pllinputfreq = HSI_VALUE; |
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| 283 | break; |
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| 284 | |||
| 285 | case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ |
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| 286 | pllinputfreq = HSE_VALUE; |
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| 287 | break; |
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| 288 | |||
| 289 | default: |
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| 290 | pllinputfreq = HSI_VALUE; |
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| 291 | break; |
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| 292 | } |
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| 293 | return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider()); |
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| 294 | } |
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| 295 | /** |
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| 296 | * @} |
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| 297 | */ |
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| 298 | |||
| 299 | /** |
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| 300 | * @} |
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| 301 | */ |
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| 302 | |||
| 303 | #endif /* defined(RCC) */ |
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| 304 | |||
| 305 | /** |
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| 306 | * @} |
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| 307 | */ |
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| 308 | |||
| 309 | #endif /* USE_FULL_LL_DRIVER */ |
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| 310 | |||
| 311 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |