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/**

  ******************************************************************************

  * @file    stm32l1xx_ll_rcc.c

  * @author  MCD Application Team

  * @brief   RCC LL module driver.

  ******************************************************************************

  * @attention

  *

  * Copyright (c) 2017 STMicroelectronics.

  * All rights reserved.

  *

  * This software is licensed under terms that can be found in the LICENSE file in

  * the root directory of this software component.

  * If no LICENSE file comes with this software, it is provided AS-IS.

  ******************************************************************************

  */

#if defined(USE_FULL_LL_DRIVER)

/* Includes ------------------------------------------------------------------*/

#include "stm32l1xx_ll_rcc.h"

/** @addtogroup STM32L1xx_LL_Driver

  * @{

  */

#if defined(RCC)

/** @defgroup RCC_LL RCC

  * @{

  */

/* Private types -------------------------------------------------------------*/

/* Private variables ---------------------------------------------------------*/

/* Private constants ---------------------------------------------------------*/

/* Private macros ------------------------------------------------------------*/

/* Private function prototypes -----------------------------------------------*/

/** @defgroup RCC_LL_Private_Functions RCC Private functions

  * @{

  */

static uint32_t RCC_GetSystemClockFreq(void);

static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);

static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);

static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);

static uint32_t RCC_PLL_GetFreqDomain_SYS(void);

/**

  * @}

  */

/* Exported functions --------------------------------------------------------*/

/** @addtogroup RCC_LL_Exported_Functions

  * @{

  */

/** @addtogroup RCC_LL_EF_Init

  * @{

  */

/**

  * @brief  Reset the RCC clock configuration to the default reset state.

  * @note   The default reset state of the clock configuration is given below:

  *         - MSI  ON and used as system clock source

  *         - HSE, HSI and PLL OFF

  *         - AHB, APB1 and APB2 prescaler set to 1.

  *         - CSS, MCO OFF

  *         - All interrupts disabled

  * @note   This function doesn't modify the configuration of the

  *         - Peripheral clocks

  *         - LSI, LSE and RTC clocks

  * @retval An ErrorStatus enumeration value:

  *          - SUCCESS: RCC registers are de-initialized

  *          - ERROR: not applicable

  */

ErrorStatus LL_RCC_DeInit(void)

{

  __IO uint32_t vl_mask;

  /* Set MSION bit */

  LL_RCC_MSI_Enable();

  /* Insure MSIRDY bit is set before writing default MSIRANGE value */

  while (LL_RCC_MSI_IsReady() == 0U)

  {

    __NOP();

  }

  /* Set MSIRANGE default value */

  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);

  /* Set MSITRIM bits to the reset value*/

  LL_RCC_MSI_SetCalibTrimming(0U);

  /* Set HSITRIM bits to the reset value*/

  LL_RCC_HSI_SetCalibTrimming(0x10U);

  /* Reset SW, HPRE, PPRE and MCOSEL bits */

  vl_mask = 0xFFFFFFFFU;

  CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));

  LL_RCC_WriteReg(CFGR, vl_mask);

  /* Read CR register */

  vl_mask = LL_RCC_ReadReg(CR);

  /* Reset HSION, HSEON, CSSON, PLLON bits */

  CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION));

  LL_RCC_WriteReg(CR, vl_mask);

  /* Reset HSEBYP bit */

  LL_RCC_HSE_DisableBypass();

  /* Insure PLL is disabled before to reset PLLSRC/PLLMUL/PLLDIV in CFGR register */

  while(LL_RCC_PLL_IsReady() != 0U) {};

  /* Reset CFGR register */

  LL_RCC_WriteReg(CFGR, 0x00000000U);

  /* Disable all interrupts */

  LL_RCC_WriteReg(CIR, 0x00000000U);

  /* Clear pending flags */

#if defined(RCC_LSECSS_SUPPORT)

  vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | \

             LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_LSECSSC | LL_RCC_CIR_CSSC);

#else

  vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | \

             LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_CSSC);

#endif /* RCC_LSECSS_SUPPORT */

  LL_RCC_WriteReg(CIR, vl_mask);

  /* Clear reset flags */

  LL_RCC_ClearResetFlags();

  return SUCCESS;

}

/**

  * @}

  */

/** @addtogroup RCC_LL_EF_Get_Freq

  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks

  *         and different peripheral clocks available on the device.

  * @note   If SYSCLK source is MSI, function returns values based on MSI clock(*)

  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)

  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)

  * @note   If SYSCLK source is PLL, function returns values based on

  *         HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.

  * @note   (*) MSI clock depends on the selected MSI range but the real value

  *             may vary depending on the variations in voltage and temperature.

  * @note   (**) HSI_VALUE is a defined constant but the real value may vary

  *              depending on the variations in voltage and temperature.

  * @note   (***) HSE_VALUE is a defined constant, user has to ensure that

  *               HSE_VALUE is same as the real frequency of the crystal used.

  *               Otherwise, this function may have wrong result.

  * @note   The result of this function could be incorrect when using fractional

  *         value for HSE crystal.

  * @note   This function can be used by the user application to compute the

  *         baud-rate for the communication peripherals or configure other parameters.

  * @{

  */

/**

  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks

  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function

  *         must be called to update structure fields. Otherwise, any

  *         configuration based on this function will be incorrect.

  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies

  * @retval None

  */

void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)

{

  /* Get SYSCLK frequency */

  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();

  /* HCLK clock frequency */

  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);

  /* PCLK1 clock frequency */

  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);

  /* PCLK2 clock frequency */

  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);

}

/**

  * @}

  */

/**

  * @}

  */

/** @addtogroup RCC_LL_Private_Functions

  * @{

  */

/**

  * @brief  Return SYSTEM clock frequency

  * @retval SYSTEM clock frequency (in Hz)

  */

static uint32_t RCC_GetSystemClockFreq(void)

{

  uint32_t frequency;

  /* Get SYSCLK source -------------------------------------------------------*/

  switch (LL_RCC_GetSysClkSource())

  {

    case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */

      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());

      break;

    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */

      frequency = HSI_VALUE;

      break;

    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */

      frequency = HSE_VALUE;

      break;

    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */

      frequency = RCC_PLL_GetFreqDomain_SYS();

      break;

    default:

      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());

      break;

  }

  return frequency;

}

/**

  * @brief  Return HCLK clock frequency

  * @param  SYSCLK_Frequency SYSCLK clock frequency

  * @retval HCLK clock frequency (in Hz)

  */

static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)

{

  /* HCLK clock frequency */

  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());

}

/**

  * @brief  Return PCLK1 clock frequency

  * @param  HCLK_Frequency HCLK clock frequency

  * @retval PCLK1 clock frequency (in Hz)

  */

static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)

{

  /* PCLK1 clock frequency */

  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());

}

/**

  * @brief  Return PCLK2 clock frequency

  * @param  HCLK_Frequency HCLK clock frequency

  * @retval PCLK2 clock frequency (in Hz)

  */

static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)

{

  /* PCLK2 clock frequency */

  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());

}

/**

  * @brief  Return PLL clock frequency used for system domain

  * @retval PLL clock frequency (in Hz)

  */

static uint32_t RCC_PLL_GetFreqDomain_SYS(void)

{

  uint32_t pllsource, pllinputfreq;

  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */

  /* Get PLL source */

  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)

  {

    case LL_RCC_PLLSOURCE_HSI:       /* HSI used as PLL clock source */

      pllinputfreq = HSI_VALUE;

      break;

    case LL_RCC_PLLSOURCE_HSE:       /* HSE used as PLL clock source */

      pllinputfreq = HSE_VALUE;

      break;

    default:

      pllinputfreq = HSI_VALUE;

      break;

  }

  return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());

}

/**

  * @}

  */

/**

  * @}

  */

#endif /* defined(RCC) */

/**

  * @}

  */

#endif /* USE_FULL_LL_DRIVER */