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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 77 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_ll_dma.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief DMA LL module driver. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * Copyright (c) 2017 STMicroelectronics. |
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| 10 | * All rights reserved. |
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| 11 | * |
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| 12 | * This software is licensed under terms that can be found in the LICENSE file |
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| 13 | * in the root directory of this software component. |
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| 14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | */ |
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| 18 | #if defined(USE_FULL_LL_DRIVER) |
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| 19 | |||
| 20 | /* Includes ------------------------------------------------------------------*/ |
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| 21 | #include "stm32l1xx_ll_dma.h" |
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| 22 | #include "stm32l1xx_ll_bus.h" |
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| 23 | #ifdef USE_FULL_ASSERT |
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| 24 | #include "stm32_assert.h" |
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| 25 | #else |
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| 26 | #define assert_param(expr) ((void)0U) |
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| 27 | #endif |
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| 28 | |||
| 29 | /** @addtogroup STM32L1xx_LL_Driver |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | |||
| 33 | #if defined (DMA1) || defined (DMA2) |
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| 34 | |||
| 35 | /** @defgroup DMA_LL DMA |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |||
| 39 | /* Private types -------------------------------------------------------------*/ |
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| 40 | /* Private variables ---------------------------------------------------------*/ |
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| 41 | /* Private constants ---------------------------------------------------------*/ |
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| 42 | /* Private macros ------------------------------------------------------------*/ |
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| 43 | /** @addtogroup DMA_LL_Private_Macros |
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| 44 | * @{ |
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| 45 | */ |
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| 46 | #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ |
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| 47 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ |
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| 48 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) |
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| 49 | |||
| 50 | #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ |
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| 51 | ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) |
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| 52 | |||
| 53 | #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ |
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| 54 | ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) |
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| 55 | |||
| 56 | #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ |
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| 57 | ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) |
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| 58 | |||
| 59 | #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ |
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| 60 | ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ |
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| 61 | ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) |
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| 62 | |||
| 63 | #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ |
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| 64 | ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ |
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| 65 | ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) |
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| 66 | |||
| 67 | #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) |
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| 68 | |||
| 69 | |||
| 70 | #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ |
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| 71 | ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ |
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| 72 | ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ |
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| 73 | ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) |
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| 74 | |||
| 75 | #if defined (DMA2) |
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| 76 | #if defined (DMA2_Channel6) && defined (DMA2_Channel7) |
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| 77 | #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ |
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| 78 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
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| 79 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
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| 80 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
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| 81 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
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| 82 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
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| 83 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
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| 84 | ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ |
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| 85 | (((INSTANCE) == DMA2) && \ |
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| 86 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
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| 87 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
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| 88 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
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| 89 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
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| 90 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
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| 91 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
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| 92 | ((CHANNEL) == LL_DMA_CHANNEL_7)))) |
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| 93 | #else |
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| 94 | #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ |
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| 95 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
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| 96 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
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| 97 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
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| 98 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
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| 99 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
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| 100 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
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| 101 | ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ |
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| 102 | (((INSTANCE) == DMA2) && \ |
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| 103 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
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| 104 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
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| 105 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
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| 106 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
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| 107 | ((CHANNEL) == LL_DMA_CHANNEL_5)))) |
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| 108 | #endif |
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| 109 | #else |
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| 110 | #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ |
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| 111 | (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ |
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| 112 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
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| 113 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
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| 114 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
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| 115 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
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| 116 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
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| 117 | ((CHANNEL) == LL_DMA_CHANNEL_7)))) |
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| 118 | #endif |
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| 119 | /** |
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| 120 | * @} |
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| 121 | */ |
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| 122 | |||
| 123 | /* Private function prototypes -----------------------------------------------*/ |
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| 124 | |||
| 125 | /* Exported functions --------------------------------------------------------*/ |
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| 126 | /** @addtogroup DMA_LL_Exported_Functions |
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| 127 | * @{ |
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| 128 | */ |
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| 129 | |||
| 130 | /** @addtogroup DMA_LL_EF_Init |
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| 131 | * @{ |
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| 132 | */ |
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| 133 | |||
| 134 | /** |
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| 135 | * @brief De-initialize the DMA registers to their default reset values. |
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| 136 | * @param DMAx DMAx Instance |
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| 137 | * @param Channel This parameter can be one of the following values: |
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| 138 | * @arg @ref LL_DMA_CHANNEL_1 |
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| 139 | * @arg @ref LL_DMA_CHANNEL_2 |
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| 140 | * @arg @ref LL_DMA_CHANNEL_3 |
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| 141 | * @arg @ref LL_DMA_CHANNEL_4 |
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| 142 | * @arg @ref LL_DMA_CHANNEL_5 |
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| 143 | * @arg @ref LL_DMA_CHANNEL_6 |
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| 144 | * @arg @ref LL_DMA_CHANNEL_7 |
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| 145 | * @arg @ref LL_DMA_CHANNEL_ALL |
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| 146 | * @retval An ErrorStatus enumeration value: |
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| 147 | * - SUCCESS: DMA registers are de-initialized |
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| 148 | * - ERROR: DMA registers are not de-initialized |
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| 149 | */ |
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| 150 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) |
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| 151 | { |
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| 152 | DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; |
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| 153 | ErrorStatus status = SUCCESS; |
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| 154 | |||
| 155 | /* Check the DMA Instance DMAx and Channel parameters*/ |
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| 156 | assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); |
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| 157 | |||
| 158 | if (Channel == LL_DMA_CHANNEL_ALL) |
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| 159 | { |
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| 160 | if (DMAx == DMA1) |
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| 161 | { |
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| 162 | /* Force reset of DMA clock */ |
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| 163 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); |
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| 164 | |||
| 165 | /* Release reset of DMA clock */ |
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| 166 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); |
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| 167 | } |
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| 168 | #if defined(DMA2) |
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| 169 | else if (DMAx == DMA2) |
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| 170 | { |
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| 171 | /* Force reset of DMA clock */ |
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| 172 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); |
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| 173 | |||
| 174 | /* Release reset of DMA clock */ |
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| 175 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); |
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| 176 | } |
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| 177 | #endif |
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| 178 | else |
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| 179 | { |
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| 180 | status = ERROR; |
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| 181 | } |
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| 182 | } |
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| 183 | else |
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| 184 | { |
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| 185 | tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); |
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| 186 | |||
| 187 | /* Disable the selected DMAx_Channely */ |
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| 188 | CLEAR_BIT(tmp->CCR, DMA_CCR_EN); |
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| 189 | |||
| 190 | /* Reset DMAx_Channely control register */ |
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| 191 | LL_DMA_WriteReg(tmp, CCR, 0U); |
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| 192 | |||
| 193 | /* Reset DMAx_Channely remaining bytes register */ |
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| 194 | LL_DMA_WriteReg(tmp, CNDTR, 0U); |
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| 195 | |||
| 196 | /* Reset DMAx_Channely peripheral address register */ |
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| 197 | LL_DMA_WriteReg(tmp, CPAR, 0U); |
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| 198 | |||
| 199 | /* Reset DMAx_Channely memory address register */ |
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| 200 | LL_DMA_WriteReg(tmp, CMAR, 0U); |
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| 201 | |||
| 202 | |||
| 203 | if (Channel == LL_DMA_CHANNEL_1) |
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| 204 | { |
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| 205 | /* Reset interrupt pending bits for DMAx Channel1 */ |
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| 206 | LL_DMA_ClearFlag_GI1(DMAx); |
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| 207 | } |
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| 208 | else if (Channel == LL_DMA_CHANNEL_2) |
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| 209 | { |
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| 210 | /* Reset interrupt pending bits for DMAx Channel2 */ |
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| 211 | LL_DMA_ClearFlag_GI2(DMAx); |
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| 212 | } |
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| 213 | else if (Channel == LL_DMA_CHANNEL_3) |
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| 214 | { |
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| 215 | /* Reset interrupt pending bits for DMAx Channel3 */ |
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| 216 | LL_DMA_ClearFlag_GI3(DMAx); |
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| 217 | } |
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| 218 | else if (Channel == LL_DMA_CHANNEL_4) |
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| 219 | { |
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| 220 | /* Reset interrupt pending bits for DMAx Channel4 */ |
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| 221 | LL_DMA_ClearFlag_GI4(DMAx); |
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| 222 | } |
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| 223 | else if (Channel == LL_DMA_CHANNEL_5) |
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| 224 | { |
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| 225 | /* Reset interrupt pending bits for DMAx Channel5 */ |
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| 226 | LL_DMA_ClearFlag_GI5(DMAx); |
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| 227 | } |
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| 228 | |||
| 229 | else if (Channel == LL_DMA_CHANNEL_6) |
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| 230 | { |
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| 231 | /* Reset interrupt pending bits for DMAx Channel6 */ |
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| 232 | LL_DMA_ClearFlag_GI6(DMAx); |
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| 233 | } |
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| 234 | else if (Channel == LL_DMA_CHANNEL_7) |
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| 235 | { |
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| 236 | /* Reset interrupt pending bits for DMAx Channel7 */ |
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| 237 | LL_DMA_ClearFlag_GI7(DMAx); |
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| 238 | } |
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| 239 | else |
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| 240 | { |
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| 241 | status = ERROR; |
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| 242 | } |
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| 243 | } |
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| 244 | |||
| 245 | return status; |
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| 246 | } |
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| 247 | |||
| 248 | /** |
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| 249 | * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. |
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| 250 | * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : |
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| 251 | * @arg @ref __LL_DMA_GET_INSTANCE |
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| 252 | * @arg @ref __LL_DMA_GET_CHANNEL |
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| 253 | * @param DMAx DMAx Instance |
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| 254 | * @param Channel This parameter can be one of the following values: |
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| 255 | * @arg @ref LL_DMA_CHANNEL_1 |
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| 256 | * @arg @ref LL_DMA_CHANNEL_2 |
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| 257 | * @arg @ref LL_DMA_CHANNEL_3 |
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| 258 | * @arg @ref LL_DMA_CHANNEL_4 |
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| 259 | * @arg @ref LL_DMA_CHANNEL_5 |
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| 260 | * @arg @ref LL_DMA_CHANNEL_6 |
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| 261 | * @arg @ref LL_DMA_CHANNEL_7 |
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| 262 | * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. |
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| 263 | * @retval An ErrorStatus enumeration value: |
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| 264 | * - SUCCESS: DMA registers are initialized |
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| 265 | * - ERROR: Not applicable |
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| 266 | */ |
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| 267 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) |
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| 268 | { |
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| 269 | /* Check the DMA Instance DMAx and Channel parameters*/ |
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| 270 | assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); |
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| 271 | |||
| 272 | /* Check the DMA parameters from DMA_InitStruct */ |
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| 273 | assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); |
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| 274 | assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); |
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| 275 | assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); |
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| 276 | assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); |
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| 277 | assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); |
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| 278 | assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); |
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| 279 | assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); |
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| 280 | assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); |
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| 281 | |||
| 282 | /*---------------------------- DMAx CCR Configuration ------------------------ |
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| 283 | * Configure DMAx_Channely: data transfer direction, data transfer mode, |
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| 284 | * peripheral and memory increment mode, |
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| 285 | * data size alignment and priority level with parameters : |
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| 286 | * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits |
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| 287 | * - Mode: DMA_CCR_CIRC bit |
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| 288 | * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit |
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| 289 | * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit |
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| 290 | * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits |
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| 291 | * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits |
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| 292 | * - Priority: DMA_CCR_PL[1:0] bits |
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| 293 | */ |
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| 294 | LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ |
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| 295 | DMA_InitStruct->Mode | \ |
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| 296 | DMA_InitStruct->PeriphOrM2MSrcIncMode | \ |
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| 297 | DMA_InitStruct->MemoryOrM2MDstIncMode | \ |
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| 298 | DMA_InitStruct->PeriphOrM2MSrcDataSize | \ |
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| 299 | DMA_InitStruct->MemoryOrM2MDstDataSize | \ |
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| 300 | DMA_InitStruct->Priority); |
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| 301 | |||
| 302 | /*-------------------------- DMAx CMAR Configuration ------------------------- |
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| 303 | * Configure the memory or destination base address with parameter : |
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| 304 | * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits |
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| 305 | */ |
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| 306 | LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); |
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| 307 | |||
| 308 | /*-------------------------- DMAx CPAR Configuration ------------------------- |
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| 309 | * Configure the peripheral or source base address with parameter : |
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| 310 | * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits |
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| 311 | */ |
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| 312 | LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); |
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| 313 | |||
| 314 | /*--------------------------- DMAx CNDTR Configuration ----------------------- |
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| 315 | * Configure the peripheral base address with parameter : |
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| 316 | * - NbData: DMA_CNDTR_NDT[15:0] bits |
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| 317 | */ |
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| 318 | LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); |
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| 319 | |||
| 320 | |||
| 321 | return SUCCESS; |
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| 322 | } |
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| 323 | |||
| 324 | /** |
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| 325 | * @brief Set each @ref LL_DMA_InitTypeDef field to default value. |
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| 326 | * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. |
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| 327 | * @retval None |
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| 328 | */ |
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| 329 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) |
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| 330 | { |
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| 331 | /* Set DMA_InitStruct fields to default values */ |
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| 332 | DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; |
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| 333 | DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; |
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| 334 | DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; |
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| 335 | DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; |
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| 336 | DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; |
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| 337 | DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; |
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| 338 | DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; |
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| 339 | DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; |
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| 340 | DMA_InitStruct->NbData = 0x00000000U; |
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| 341 | DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; |
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| 342 | } |
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| 343 | |||
| 344 | /** |
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| 345 | * @} |
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| 346 | */ |
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| 347 | |||
| 348 | /** |
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| 349 | * @} |
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| 350 | */ |
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| 351 | |||
| 352 | /** |
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| 353 | * @} |
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| 354 | */ |
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| 355 | |||
| 356 | #endif /* DMA1 || DMA2 */ |
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| 357 | |||
| 358 | /** |
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| 359 | * @} |
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| 360 | */ |
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| 361 | |||
| 362 | #endif /* USE_FULL_LL_DRIVER */ |
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| 363 | |||
| 364 |