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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 77 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_ll_adc.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief ADC LL module driver |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved. |
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| 11 | * |
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| 12 | * This software is licensed under terms that can be found in the LICENSE file |
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| 13 | * in the root directory of this software component. |
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| 14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | */ |
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| 18 | #if defined(USE_FULL_LL_DRIVER) |
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| 19 | |||
| 20 | /* Includes ------------------------------------------------------------------*/ |
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| 21 | #include "stm32l1xx_ll_adc.h" |
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| 22 | #include "stm32l1xx_ll_bus.h" |
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| 23 | |||
| 24 | #ifdef USE_FULL_ASSERT |
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| 25 | #include "stm32_assert.h" |
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| 26 | #else |
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| 27 | #define assert_param(expr) ((void)0U) |
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| 28 | #endif |
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| 29 | |||
| 30 | /** @addtogroup STM32L1xx_LL_Driver |
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| 31 | * @{ |
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| 32 | */ |
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| 33 | |||
| 34 | #if defined (ADC1) |
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| 35 | |||
| 36 | /** @addtogroup ADC_LL ADC |
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| 37 | * @{ |
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| 38 | */ |
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| 39 | |||
| 40 | /* Private types -------------------------------------------------------------*/ |
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| 41 | /* Private variables ---------------------------------------------------------*/ |
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| 42 | /* Private constants ---------------------------------------------------------*/ |
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| 43 | /* Private macros ------------------------------------------------------------*/ |
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| 44 | |||
| 45 | /** @addtogroup ADC_LL_Private_Macros |
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| 46 | * @{ |
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| 47 | */ |
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| 48 | |||
| 49 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 50 | /* common to several ADC instances. */ |
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| 51 | #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ |
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| 52 | ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ |
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| 53 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ |
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| 54 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ |
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| 55 | ) |
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| 56 | |||
| 57 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 58 | /* ADC instance. */ |
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| 59 | #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ |
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| 60 | ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ |
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| 61 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ |
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| 62 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ |
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| 63 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ |
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| 64 | ) |
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| 65 | |||
| 66 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
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| 67 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
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| 68 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
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| 69 | ) |
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| 70 | |||
| 71 | #define IS_LL_ADC_LOW_POWER_AUTOWAIT(__LOW_POWER__) \ |
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| 72 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_NONE) \ |
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| 73 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ |
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| 74 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES) \ |
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| 75 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES) \ |
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| 76 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES) \ |
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| 77 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES) \ |
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| 78 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES) \ |
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| 79 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES) \ |
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| 80 | ) |
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| 81 | |||
| 82 | #define IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(__LOW_POWER__) \ |
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| 83 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_NONE) \ |
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| 84 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE) \ |
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| 85 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE) \ |
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| 86 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES) \ |
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| 87 | ) |
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| 88 | |||
| 89 | #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
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| 90 | ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
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| 91 | || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
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| 92 | ) |
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| 93 | |||
| 94 | #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
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| 95 | ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
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| 96 | || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
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| 97 | ) |
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| 98 | |||
| 99 | #define IS_LL_ADC_CHANNELS_BANK(__CHANNELS_BANK__) \ |
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| 100 | ( ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_A) \ |
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| 101 | || ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_B) \ |
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| 102 | ) |
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| 103 | |||
| 104 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 105 | /* ADC group regular */ |
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| 106 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
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| 107 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
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| 108 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ |
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| 109 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
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| 110 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
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| 111 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
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| 112 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
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| 113 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH3) \ |
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| 114 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ |
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| 115 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
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| 116 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ |
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| 117 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_CH2) \ |
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| 118 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO) \ |
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| 119 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
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| 120 | ) |
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| 121 | |||
| 122 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
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| 123 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
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| 124 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
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| 125 | ) |
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| 126 | |||
| 127 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
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| 128 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
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| 129 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ |
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| 130 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
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| 131 | ) |
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| 132 | |||
| 133 | #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ |
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| 134 | ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ |
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| 135 | || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ |
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| 136 | ) |
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| 137 | |||
| 138 | #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
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| 139 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
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| 140 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
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| 141 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
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| 142 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
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| 143 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
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| 144 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
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| 145 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
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| 146 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
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| 147 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
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| 148 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
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| 149 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
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| 150 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
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| 151 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
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| 152 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
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| 153 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
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| 154 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
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| 155 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
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| 156 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS) \ |
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| 157 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_18RANKS) \ |
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| 158 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_19RANKS) \ |
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| 159 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_20RANKS) \ |
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| 160 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_21RANKS) \ |
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| 161 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_22RANKS) \ |
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| 162 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_23RANKS) \ |
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| 163 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_24RANKS) \ |
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| 164 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_25RANKS) \ |
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| 165 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_26RANKS) \ |
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| 166 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_27RANKS) \ |
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| 167 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_28RANKS) \ |
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| 168 | ) |
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| 169 | #else |
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| 170 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
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| 171 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
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| 172 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
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| 173 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
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| 174 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
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| 175 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
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| 176 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
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| 177 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
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| 178 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
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| 179 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
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| 180 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
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| 181 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
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| 182 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
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| 183 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
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| 184 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
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| 185 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
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| 186 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
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| 187 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS) \ |
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| 188 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_18RANKS) \ |
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| 189 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_19RANKS) \ |
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| 190 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_20RANKS) \ |
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| 191 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_21RANKS) \ |
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| 192 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_22RANKS) \ |
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| 193 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_23RANKS) \ |
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| 194 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_24RANKS) \ |
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| 195 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_25RANKS) \ |
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| 196 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_26RANKS) \ |
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| 197 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_27RANKS) \ |
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| 198 | ) |
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| 199 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC) || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
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| 200 | |||
| 201 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
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| 202 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
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| 203 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
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| 204 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
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| 205 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
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| 206 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
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| 207 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
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| 208 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
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| 209 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
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| 210 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
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| 211 | ) |
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| 212 | |||
| 213 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 214 | /* ADC group injected */ |
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| 215 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
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| 216 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
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| 217 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH1) \ |
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| 218 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) \ |
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| 219 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
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| 220 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
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| 221 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
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| 222 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
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| 223 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ |
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| 224 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ |
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| 225 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
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| 226 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM10_CH1) \ |
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| 227 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ |
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| 228 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
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| 229 | ) |
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| 230 | |||
| 231 | #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ |
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| 232 | ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ |
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| 233 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ |
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| 234 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ |
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| 235 | ) |
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| 236 | |||
| 237 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
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| 238 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
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| 239 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
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| 240 | ) |
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| 241 | |||
| 242 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
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| 243 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
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| 244 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
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| 245 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
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| 246 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
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| 247 | ) |
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| 248 | |||
| 249 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
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| 250 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
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| 251 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
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| 252 | ) |
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| 253 | |||
| 254 | /** |
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| 255 | * @} |
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| 256 | */ |
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| 257 | |||
| 258 | |||
| 259 | /* Private function prototypes -----------------------------------------------*/ |
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| 260 | |||
| 261 | /* Exported functions --------------------------------------------------------*/ |
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| 262 | /** @addtogroup ADC_LL_Exported_Functions |
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| 263 | * @{ |
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| 264 | */ |
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| 265 | |||
| 266 | /** @addtogroup ADC_LL_EF_Init |
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| 267 | * @{ |
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| 268 | */ |
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| 269 | |||
| 270 | /** |
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| 271 | * @brief De-initialize registers of all ADC instances belonging to |
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| 272 | * the same ADC common instance to their default reset values. |
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| 273 | * @param ADCxy_COMMON ADC common instance |
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| 274 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
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| 275 | * @retval An ErrorStatus enumeration value: |
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| 276 | * - SUCCESS: ADC common registers are de-initialized |
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| 277 | * - ERROR: not applicable |
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| 278 | */ |
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| 279 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
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| 280 | { |
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| 281 | /* Check the parameters */ |
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| 282 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
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| 283 | |||
| 284 | /* Force reset of ADC clock (core clock) */ |
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| 285 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); |
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| 286 | |||
| 287 | /* Release reset of ADC clock (core clock) */ |
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| 288 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); |
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| 289 | |||
| 290 | return SUCCESS; |
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| 291 | } |
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| 292 | |||
| 293 | /** |
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| 294 | * @brief Initialize some features of ADC common parameters |
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| 295 | * (all ADC instances belonging to the same ADC common instance) |
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| 296 | * and multimode (for devices with several ADC instances available). |
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| 297 | * @note The setting of ADC common parameters is conditioned to |
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| 298 | * ADC instances state: |
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| 299 | * All ADC instances belonging to the same ADC common instance |
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| 300 | * must be disabled. |
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| 301 | * @param ADCxy_COMMON ADC common instance |
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| 302 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
||
| 303 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
||
| 304 | * @retval An ErrorStatus enumeration value: |
||
| 305 | * - SUCCESS: ADC common registers are initialized |
||
| 306 | * - ERROR: ADC common registers are not initialized |
||
| 307 | */ |
||
| 308 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
||
| 309 | { |
||
| 310 | ErrorStatus status = SUCCESS; |
||
| 311 | |||
| 312 | /* Check the parameters */ |
||
| 313 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
||
| 314 | assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); |
||
| 315 | |||
| 316 | /* Note: Hardware constraint (refer to description of functions */ |
||
| 317 | /* "LL_ADC_SetCommonXXX()": */ |
||
| 318 | /* On this STM32 series, setting of these features is conditioned to */ |
||
| 319 | /* ADC state: */ |
||
| 320 | /* All ADC instances of the ADC common group must be disabled. */ |
||
| 321 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
||
| 322 | { |
||
| 323 | /* Configuration of ADC hierarchical scope: */ |
||
| 324 | /* - common to several ADC */ |
||
| 325 | /* (all ADC instances belonging to the same ADC common instance) */ |
||
| 326 | /* - Set ADC clock (conversion clock) */ |
||
| 327 | LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); |
||
| 328 | } |
||
| 329 | else |
||
| 330 | { |
||
| 331 | /* Initialization error: One or several ADC instances belonging to */ |
||
| 332 | /* the same ADC common instance are not disabled. */ |
||
| 333 | status = ERROR; |
||
| 334 | } |
||
| 335 | |||
| 336 | return status; |
||
| 337 | } |
||
| 338 | |||
| 339 | /** |
||
| 340 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
||
| 341 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
||
| 342 | * whose fields will be set to default values. |
||
| 343 | * @retval None |
||
| 344 | */ |
||
| 345 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
||
| 346 | { |
||
| 347 | /* Set ADC_CommonInitStruct fields to default values */ |
||
| 348 | /* Set fields of ADC common */ |
||
| 349 | /* (all ADC instances belonging to the same ADC common instance) */ |
||
| 350 | ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; |
||
| 351 | |||
| 352 | } |
||
| 353 | |||
| 354 | /** |
||
| 355 | * @brief De-initialize registers of the selected ADC instance |
||
| 356 | * to their default reset values. |
||
| 357 | * @note To reset all ADC instances quickly (perform a hard reset), |
||
| 358 | * use function @ref LL_ADC_CommonDeInit(). |
||
| 359 | * @param ADCx ADC instance |
||
| 360 | * @retval An ErrorStatus enumeration value: |
||
| 361 | * - SUCCESS: ADC registers are de-initialized |
||
| 362 | * - ERROR: ADC registers are not de-initialized |
||
| 363 | */ |
||
| 364 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
||
| 365 | { |
||
| 366 | ErrorStatus status = SUCCESS; |
||
| 367 | |||
| 368 | /* Check the parameters */ |
||
| 369 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
||
| 370 | |||
| 371 | /* Disable ADC instance if not already disabled. */ |
||
| 372 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
||
| 373 | { |
||
| 374 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
||
| 375 | /* have an external trigger event occurring during the conversion stop */ |
||
| 376 | /* ADC disable process. */ |
||
| 377 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
||
| 378 | |||
| 379 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
||
| 380 | /* have an external trigger event occurring during the conversion stop */ |
||
| 381 | /* ADC disable process. */ |
||
| 382 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
||
| 383 | |||
| 384 | /* Disable the ADC instance */ |
||
| 385 | LL_ADC_Disable(ADCx); |
||
| 386 | } |
||
| 387 | |||
| 388 | /* Check whether ADC state is compliant with expected state */ |
||
| 389 | /* (hardware requirements of bits state to reset registers below) */ |
||
| 390 | if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) |
||
| 391 | { |
||
| 392 | /* ========== Reset ADC registers ========== */ |
||
| 393 | /* Reset register SR */ |
||
| 394 | CLEAR_BIT(ADCx->SR, |
||
| 395 | ( LL_ADC_FLAG_STRT |
||
| 396 | | LL_ADC_FLAG_JSTRT |
||
| 397 | | LL_ADC_FLAG_EOCS |
||
| 398 | | LL_ADC_FLAG_OVR |
||
| 399 | | LL_ADC_FLAG_JEOS |
||
| 400 | | LL_ADC_FLAG_AWD1 ) |
||
| 401 | ); |
||
| 402 | |||
| 403 | /* Reset register CR1 */ |
||
| 404 | CLEAR_BIT(ADCx->CR1, |
||
| 405 | ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN |
||
| 406 | | ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD |
||
| 407 | | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
||
| 408 | | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
||
| 409 | | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
||
| 410 | | ADC_CR1_AWDCH ) |
||
| 411 | ); |
||
| 412 | |||
| 413 | /* Reset register CR2 */ |
||
| 414 | #if defined(ADC_CR2_CFG) |
||
| 415 | CLEAR_BIT(ADCx->CR2, |
||
| 416 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
||
| 417 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
||
| 418 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
||
| 419 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
||
| 420 | | ADC_CR2_CFG | ADC_CR2_CONT | ADC_CR2_ADON ) |
||
| 421 | ); |
||
| 422 | #else |
||
| 423 | CLEAR_BIT(ADCx->CR2, |
||
| 424 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
||
| 425 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
||
| 426 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
||
| 427 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
||
| 428 | | ADC_CR2_CONT | ADC_CR2_ADON ) |
||
| 429 | ); |
||
| 430 | #endif /* ADC_CR2_CFG */ |
||
| 431 | |||
| 432 | /* Reset register SMPR1 */ |
||
| 433 | /* Note: On STM32L1, ADC channels 27, 28, 29, 30, 31 are not available */ |
||
| 434 | /* on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 435 | #if defined(ADC_SMPR0_SMP31) |
||
| 436 | CLEAR_BIT(ADCx->SMPR1, |
||
| 437 | ( ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 |
||
| 438 | | ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
||
| 439 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
||
| 440 | | ADC_SMPR1_SMP20 ) |
||
| 441 | ); |
||
| 442 | #else |
||
| 443 | CLEAR_BIT(ADCx->SMPR1, |
||
| 444 | ( ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
||
| 445 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
||
| 446 | | ADC_SMPR1_SMP20 ) |
||
| 447 | ); |
||
| 448 | #endif /* ADC_SMPR0_SMP31 */ |
||
| 449 | |||
| 450 | /* Reset register SMPR2 */ |
||
| 451 | CLEAR_BIT(ADCx->SMPR2, |
||
| 452 | ( ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 |
||
| 453 | | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 |
||
| 454 | | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 |
||
| 455 | | ADC_SMPR2_SMP10 ) |
||
| 456 | ); |
||
| 457 | |||
| 458 | /* Reset register SMPR3 */ |
||
| 459 | CLEAR_BIT(ADCx->SMPR3, |
||
| 460 | ( ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 |
||
| 461 | | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 |
||
| 462 | | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 |
||
| 463 | | ADC_SMPR3_SMP0 ) |
||
| 464 | ); |
||
| 465 | |||
| 466 | #if defined(ADC_SMPR0_SMP31) |
||
| 467 | /* Reset register SMPR0 */ |
||
| 468 | CLEAR_BIT(ADCx->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)); |
||
| 469 | #endif /* ADC_SMPR0_SMP31 */ |
||
| 470 | |||
| 471 | /* Reset register JOFR1 */ |
||
| 472 | CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
||
| 473 | /* Reset register JOFR2 */ |
||
| 474 | CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
||
| 475 | /* Reset register JOFR3 */ |
||
| 476 | CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
||
| 477 | /* Reset register JOFR4 */ |
||
| 478 | CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
||
| 479 | |||
| 480 | /* Reset register HTR */ |
||
| 481 | SET_BIT(ADCx->HTR, ADC_HTR_HT); |
||
| 482 | /* Reset register LTR */ |
||
| 483 | CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
||
| 484 | |||
| 485 | /* Reset register SQR1 */ |
||
| 486 | CLEAR_BIT(ADCx->SQR1, |
||
| 487 | ( ADC_SQR1_L |
||
| 488 | #if defined(ADC_SQR1_SQ28) |
||
| 489 | | ADC_SQR1_SQ28 | ADC_SQR1_SQ27 |
||
| 490 | #endif |
||
| 491 | | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) |
||
| 492 | ); |
||
| 493 | |||
| 494 | /* Reset register SQR2 */ |
||
| 495 | CLEAR_BIT(ADCx->SQR2, |
||
| 496 | ( ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 |
||
| 497 | | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19) |
||
| 498 | ); |
||
| 499 | |||
| 500 | /* Reset register SQR3 */ |
||
| 501 | CLEAR_BIT(ADCx->SQR3, |
||
| 502 | ( ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 |
||
| 503 | | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13) |
||
| 504 | ); |
||
| 505 | |||
| 506 | /* Reset register SQR4 */ |
||
| 507 | CLEAR_BIT(ADCx->SQR4, |
||
| 508 | ( ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 |
||
| 509 | | ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 ) |
||
| 510 | ); |
||
| 511 | |||
| 512 | /* Reset register SQR5 */ |
||
| 513 | CLEAR_BIT(ADCx->SQR5, |
||
| 514 | ( ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 |
||
| 515 | | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 ) |
||
| 516 | ); |
||
| 517 | |||
| 518 | |||
| 519 | /* Reset register JSQR */ |
||
| 520 | CLEAR_BIT(ADCx->JSQR, |
||
| 521 | ( ADC_JSQR_JL |
||
| 522 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
||
| 523 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
||
| 524 | ); |
||
| 525 | |||
| 526 | /* Reset register DR */ |
||
| 527 | /* bits in access mode read only, no direct reset applicable */ |
||
| 528 | |||
| 529 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
||
| 530 | /* bits in access mode read only, no direct reset applicable */ |
||
| 531 | |||
| 532 | /* Reset register CCR */ |
||
| 533 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); |
||
| 534 | } |
||
| 535 | |||
| 536 | return status; |
||
| 537 | } |
||
| 538 | |||
| 539 | /** |
||
| 540 | * @brief Initialize some features of ADC instance. |
||
| 541 | * @note These parameters have an impact on ADC scope: ADC instance. |
||
| 542 | * Affects both group regular and group injected (availability |
||
| 543 | * of ADC group injected depends on STM32 families). |
||
| 544 | * Refer to corresponding unitary functions into |
||
| 545 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
||
| 546 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
||
| 547 | * is conditioned to ADC state: |
||
| 548 | * ADC instance must be disabled. |
||
| 549 | * This condition is applied to all ADC features, for efficiency |
||
| 550 | * and compatibility over all STM32 families. However, the different |
||
| 551 | * features can be set under different ADC state conditions |
||
| 552 | * (setting possible with ADC enabled without conversion on going, |
||
| 553 | * ADC enabled with conversion on going, ...) |
||
| 554 | * Each feature can be updated afterwards with a unitary function |
||
| 555 | * and potentially with ADC in a different state than disabled, |
||
| 556 | * refer to description of each function for setting |
||
| 557 | * conditioned to ADC state. |
||
| 558 | * @note After using this function, some other features must be configured |
||
| 559 | * using LL unitary functions. |
||
| 560 | * The minimum configuration remaining to be done is: |
||
| 561 | * - Set ADC group regular or group injected sequencer: |
||
| 562 | * map channel on the selected sequencer rank. |
||
| 563 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
||
| 564 | * - Set ADC channel sampling time |
||
| 565 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
||
| 566 | * @param ADCx ADC instance |
||
| 567 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
||
| 568 | * @retval An ErrorStatus enumeration value: |
||
| 569 | * - SUCCESS: ADC registers are initialized |
||
| 570 | * - ERROR: ADC registers are not initialized |
||
| 571 | */ |
||
| 572 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
||
| 573 | { |
||
| 574 | ErrorStatus status = SUCCESS; |
||
| 575 | |||
| 576 | /* Check the parameters */ |
||
| 577 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
||
| 578 | |||
| 579 | assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); |
||
| 580 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
||
| 581 | /* Note: On STM32L1, low power feature is set by concatenating */ |
||
| 582 | /* values of @ref ADC_LL_EC_LP_MODE_AUTOWAIT */ |
||
| 583 | /* and @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF. */ |
||
| 584 | /* Check of the parameter is done for each of group of values, */ |
||
| 585 | /* by excluding the other group of values. */ |
||
| 586 | assert_param(IS_LL_ADC_LOW_POWER_AUTOWAIT(ADC_InitStruct->LowPowerMode & ~(ADC_CR1_PDI | ADC_CR1_PDD))); |
||
| 587 | assert_param(IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(ADC_InitStruct->LowPowerMode & ~(ADC_CR2_DELS))); |
||
| 588 | assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
||
| 589 | |||
| 590 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 591 | /* ADC instance must be disabled. */ |
||
| 592 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
||
| 593 | { |
||
| 594 | /* Configuration of ADC hierarchical scope: */ |
||
| 595 | /* - ADC instance */ |
||
| 596 | /* - Set ADC data resolution */ |
||
| 597 | /* - Set ADC conversion data alignment */ |
||
| 598 | /* - Set ADC low power mode */ |
||
| 599 | MODIFY_REG(ADCx->CR1, |
||
| 600 | ADC_CR1_RES |
||
| 601 | | ADC_CR1_PDI |
||
| 602 | | ADC_CR1_PDD |
||
| 603 | | ADC_CR1_SCAN |
||
| 604 | , |
||
| 605 | ADC_InitStruct->Resolution |
||
| 606 | | (ADC_InitStruct->LowPowerMode & (ADC_CR1_PDI | ADC_CR1_PDD)) |
||
| 607 | | ADC_InitStruct->SequencersScanMode |
||
| 608 | ); |
||
| 609 | |||
| 610 | MODIFY_REG(ADCx->CR2, |
||
| 611 | ADC_CR2_ALIGN |
||
| 612 | | ADC_CR2_DELS |
||
| 613 | , |
||
| 614 | ADC_InitStruct->DataAlignment |
||
| 615 | | (ADC_InitStruct->LowPowerMode & ADC_CR2_DELS) |
||
| 616 | ); |
||
| 617 | |||
| 618 | } |
||
| 619 | else |
||
| 620 | { |
||
| 621 | /* Initialization error: ADC instance is not disabled. */ |
||
| 622 | status = ERROR; |
||
| 623 | } |
||
| 624 | return status; |
||
| 625 | } |
||
| 626 | |||
| 627 | /** |
||
| 628 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
||
| 629 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
||
| 630 | * whose fields will be set to default values. |
||
| 631 | * @retval None |
||
| 632 | */ |
||
| 633 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
||
| 634 | { |
||
| 635 | /* Set ADC_InitStruct fields to default values */ |
||
| 636 | /* Set fields of ADC instance */ |
||
| 637 | ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; |
||
| 638 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
||
| 639 | ADC_InitStruct->LowPowerMode = (LL_ADC_LP_AUTOWAIT_NONE | LL_ADC_LP_AUTOPOWEROFF_NONE); |
||
| 640 | |||
| 641 | /* Enable scan mode to have a generic behavior with ADC of other */ |
||
| 642 | /* STM32 families, without this setting available: */ |
||
| 643 | /* ADC group regular sequencer and ADC group injected sequencer depend */ |
||
| 644 | /* only of their own configuration. */ |
||
| 645 | ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
||
| 646 | |||
| 647 | } |
||
| 648 | |||
| 649 | /** |
||
| 650 | * @brief Initialize some features of ADC group regular. |
||
| 651 | * @note These parameters have an impact on ADC scope: ADC group regular. |
||
| 652 | * Refer to corresponding unitary functions into |
||
| 653 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
||
| 654 | * (functions with prefix "REG"). |
||
| 655 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
||
| 656 | * is conditioned to ADC state: |
||
| 657 | * ADC instance must be disabled. |
||
| 658 | * This condition is applied to all ADC features, for efficiency |
||
| 659 | * and compatibility over all STM32 families. However, the different |
||
| 660 | * features can be set under different ADC state conditions |
||
| 661 | * (setting possible with ADC enabled without conversion on going, |
||
| 662 | * ADC enabled with conversion on going, ...) |
||
| 663 | * Each feature can be updated afterwards with a unitary function |
||
| 664 | * and potentially with ADC in a different state than disabled, |
||
| 665 | * refer to description of each function for setting |
||
| 666 | * conditioned to ADC state. |
||
| 667 | * @note After using this function, other features must be configured |
||
| 668 | * using LL unitary functions. |
||
| 669 | * The minimum configuration remaining to be done is: |
||
| 670 | * - Set ADC group regular or group injected sequencer: |
||
| 671 | * map channel on the selected sequencer rank. |
||
| 672 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
||
| 673 | * - Set ADC channel sampling time |
||
| 674 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
||
| 675 | * @param ADCx ADC instance |
||
| 676 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
||
| 677 | * @retval An ErrorStatus enumeration value: |
||
| 678 | * - SUCCESS: ADC registers are initialized |
||
| 679 | * - ERROR: ADC registers are not initialized |
||
| 680 | */ |
||
| 681 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
||
| 682 | { |
||
| 683 | ErrorStatus status = SUCCESS; |
||
| 684 | |||
| 685 | /* Check the parameters */ |
||
| 686 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
||
| 687 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
||
| 688 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
||
| 689 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
||
| 690 | { |
||
| 691 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
||
| 692 | } |
||
| 693 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
||
| 694 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
||
| 695 | |||
| 696 | /* ADC group regular continuous mode and discontinuous mode */ |
||
| 697 | /* can not be enabled simultenaeously */ |
||
| 698 | assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) |
||
| 699 | || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); |
||
| 700 | |||
| 701 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 702 | /* ADC instance must be disabled. */ |
||
| 703 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
||
| 704 | { |
||
| 705 | /* Configuration of ADC hierarchical scope: */ |
||
| 706 | /* - ADC group regular */ |
||
| 707 | /* - Set ADC group regular trigger source */ |
||
| 708 | /* - Set ADC group regular sequencer length */ |
||
| 709 | /* - Set ADC group regular sequencer discontinuous mode */ |
||
| 710 | /* - Set ADC group regular continuous mode */ |
||
| 711 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
||
| 712 | /* transfer by DMA, and DMA requests mode */ |
||
| 713 | /* Note: On this STM32 series, ADC trigger edge is set when starting */ |
||
| 714 | /* ADC conversion. */ |
||
| 715 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
||
| 716 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
||
| 717 | { |
||
| 718 | MODIFY_REG(ADCx->CR1, |
||
| 719 | ADC_CR1_DISCEN |
||
| 720 | | ADC_CR1_DISCNUM |
||
| 721 | , |
||
| 722 | ADC_REG_InitStruct->SequencerLength |
||
| 723 | | ADC_REG_InitStruct->SequencerDiscont |
||
| 724 | ); |
||
| 725 | } |
||
| 726 | else |
||
| 727 | { |
||
| 728 | MODIFY_REG(ADCx->CR1, |
||
| 729 | ADC_CR1_DISCEN |
||
| 730 | | ADC_CR1_DISCNUM |
||
| 731 | , |
||
| 732 | ADC_REG_InitStruct->SequencerLength |
||
| 733 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
||
| 734 | ); |
||
| 735 | } |
||
| 736 | |||
| 737 | MODIFY_REG(ADCx->CR2, |
||
| 738 | ADC_CR2_EXTSEL |
||
| 739 | | ADC_CR2_EXTEN |
||
| 740 | | ADC_CR2_CONT |
||
| 741 | | ADC_CR2_DMA |
||
| 742 | | ADC_CR2_DDS |
||
| 743 | , |
||
| 744 | (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) |
||
| 745 | | ADC_REG_InitStruct->ContinuousMode |
||
| 746 | | ADC_REG_InitStruct->DMATransfer |
||
| 747 | ); |
||
| 748 | |||
| 749 | /* Set ADC group regular sequencer length and scan direction */ |
||
| 750 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 751 | /* Note: If ADC instance feature scan mode is disabled */ |
||
| 752 | /* (refer to ADC instance initialization structure */ |
||
| 753 | /* parameter @ref SequencersScanMode */ |
||
| 754 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
||
| 755 | /* this parameter is discarded. */ |
||
| 756 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
||
| 757 | } |
||
| 758 | else |
||
| 759 | { |
||
| 760 | /* Initialization error: ADC instance is not disabled. */ |
||
| 761 | status = ERROR; |
||
| 762 | } |
||
| 763 | return status; |
||
| 764 | } |
||
| 765 | |||
| 766 | /** |
||
| 767 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
||
| 768 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
||
| 769 | * whose fields will be set to default values. |
||
| 770 | * @retval None |
||
| 771 | */ |
||
| 772 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
||
| 773 | { |
||
| 774 | /* Set ADC_REG_InitStruct fields to default values */ |
||
| 775 | /* Set fields of ADC group regular */ |
||
| 776 | /* Note: On this STM32 series, ADC trigger edge is set when starting */ |
||
| 777 | /* ADC conversion. */ |
||
| 778 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
||
| 779 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
||
| 780 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
||
| 781 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
||
| 782 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
||
| 783 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
||
| 784 | } |
||
| 785 | |||
| 786 | /** |
||
| 787 | * @brief Initialize some features of ADC group injected. |
||
| 788 | * @note These parameters have an impact on ADC scope: ADC group injected. |
||
| 789 | * Refer to corresponding unitary functions into |
||
| 790 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
||
| 791 | * (functions with prefix "INJ"). |
||
| 792 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
||
| 793 | * is conditioned to ADC state: |
||
| 794 | * ADC instance must be disabled. |
||
| 795 | * This condition is applied to all ADC features, for efficiency |
||
| 796 | * and compatibility over all STM32 families. However, the different |
||
| 797 | * features can be set under different ADC state conditions |
||
| 798 | * (setting possible with ADC enabled without conversion on going, |
||
| 799 | * ADC enabled with conversion on going, ...) |
||
| 800 | * Each feature can be updated afterwards with a unitary function |
||
| 801 | * and potentially with ADC in a different state than disabled, |
||
| 802 | * refer to description of each function for setting |
||
| 803 | * conditioned to ADC state. |
||
| 804 | * @note After using this function, other features must be configured |
||
| 805 | * using LL unitary functions. |
||
| 806 | * The minimum configuration remaining to be done is: |
||
| 807 | * - Set ADC group injected sequencer: |
||
| 808 | * map channel on the selected sequencer rank. |
||
| 809 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
||
| 810 | * - Set ADC channel sampling time |
||
| 811 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
||
| 812 | * @param ADCx ADC instance |
||
| 813 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
||
| 814 | * @retval An ErrorStatus enumeration value: |
||
| 815 | * - SUCCESS: ADC registers are initialized |
||
| 816 | * - ERROR: ADC registers are not initialized |
||
| 817 | */ |
||
| 818 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
||
| 819 | { |
||
| 820 | ErrorStatus status = SUCCESS; |
||
| 821 | |||
| 822 | /* Check the parameters */ |
||
| 823 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
||
| 824 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
||
| 825 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
||
| 826 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
||
| 827 | { |
||
| 828 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
||
| 829 | } |
||
| 830 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
||
| 831 | |||
| 832 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 833 | /* ADC instance must be disabled. */ |
||
| 834 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
||
| 835 | { |
||
| 836 | /* Configuration of ADC hierarchical scope: */ |
||
| 837 | /* - ADC group injected */ |
||
| 838 | /* - Set ADC group injected trigger source */ |
||
| 839 | /* - Set ADC group injected sequencer length */ |
||
| 840 | /* - Set ADC group injected sequencer discontinuous mode */ |
||
| 841 | /* - Set ADC group injected conversion trigger: independent or */ |
||
| 842 | /* from ADC group regular */ |
||
| 843 | /* Note: On this STM32 series, ADC trigger edge is set when starting */ |
||
| 844 | /* ADC conversion. */ |
||
| 845 | /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
||
| 846 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
||
| 847 | { |
||
| 848 | MODIFY_REG(ADCx->CR1, |
||
| 849 | ADC_CR1_JDISCEN |
||
| 850 | | ADC_CR1_JAUTO |
||
| 851 | , |
||
| 852 | ADC_INJ_InitStruct->SequencerDiscont |
||
| 853 | | ADC_INJ_InitStruct->TrigAuto |
||
| 854 | ); |
||
| 855 | } |
||
| 856 | else |
||
| 857 | { |
||
| 858 | MODIFY_REG(ADCx->CR1, |
||
| 859 | ADC_CR1_JDISCEN |
||
| 860 | | ADC_CR1_JAUTO |
||
| 861 | , |
||
| 862 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
||
| 863 | | ADC_INJ_InitStruct->TrigAuto |
||
| 864 | ); |
||
| 865 | } |
||
| 866 | |||
| 867 | MODIFY_REG(ADCx->CR2, |
||
| 868 | ADC_CR2_JEXTSEL |
||
| 869 | | ADC_CR2_JEXTEN |
||
| 870 | , |
||
| 871 | (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) |
||
| 872 | ); |
||
| 873 | |||
| 874 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 875 | /* Note: If ADC instance feature scan mode is disabled */ |
||
| 876 | /* (refer to ADC instance initialization structure */ |
||
| 877 | /* parameter @ref SequencersScanMode */ |
||
| 878 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
||
| 879 | /* this parameter is discarded. */ |
||
| 880 | LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
||
| 881 | } |
||
| 882 | else |
||
| 883 | { |
||
| 884 | /* Initialization error: ADC instance is not disabled. */ |
||
| 885 | status = ERROR; |
||
| 886 | } |
||
| 887 | return status; |
||
| 888 | } |
||
| 889 | |||
| 890 | /** |
||
| 891 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
||
| 892 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
||
| 893 | * whose fields will be set to default values. |
||
| 894 | * @retval None |
||
| 895 | */ |
||
| 896 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
||
| 897 | { |
||
| 898 | /* Set ADC_INJ_InitStruct fields to default values */ |
||
| 899 | /* Set fields of ADC group injected */ |
||
| 900 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
||
| 901 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
||
| 902 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
||
| 903 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
||
| 904 | } |
||
| 905 | |||
| 906 | /** |
||
| 907 | * @} |
||
| 908 | */ |
||
| 909 | |||
| 910 | /** |
||
| 911 | * @} |
||
| 912 | */ |
||
| 913 | |||
| 914 | /** |
||
| 915 | * @} |
||
| 916 | */ |
||
| 917 | |||
| 918 | #endif /* ADC1 */ |
||
| 919 | |||
| 920 | /** |
||
| 921 | * @} |
||
| 922 | */ |
||
| 923 | |||
| 924 | #endif /* USE_FULL_LL_DRIVER */ |