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/**

  ******************************************************************************

  * @file    stm32l1xx_hal_rcc.c

  * @author  MCD Application Team

  * @brief   RCC HAL module driver.

  *          This file provides firmware functions to manage the following

  *          functionalities of the Reset and Clock Control (RCC) peripheral:

  *           + Initialization and de-initialization functions

  *           + Peripheral Control functions

  *

  @verbatim

  ==============================================================================

                      ##### RCC specific features #####

  ==============================================================================

    [..]

      After reset the device is running from multispeed internal oscillator clock

      (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled,

      and all peripherals are off except internal SRAM, Flash and JTAG.

      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;

          all peripherals mapped on these buses are running at MSI speed.

      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.

      (+) All GPIOs are in input floating state, except the JTAG pins which

          are assigned to be used for debug purpose.

    [..] Once the device started from reset, the user application has to:

      (+) Configure the clock source to be used to drive the System clock

          (if the application needs higher frequency/performance)

      (+) Configure the System clock frequency and Flash settings

      (+) Configure the AHB and APB buses prescalers

      (+) Enable the clock for the peripheral(s) to be used

      (+) Configure the clock source(s) for peripherals whose clocks are not

          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)

          (*) SDIO only for STM32L1xxxD devices

                      ##### RCC Limitations #####

  ==============================================================================

    [..]

      A delay between an RCC peripheral clock enable and the effective peripheral

      enabling should be taken into account in order to manage the peripheral read/write

      from/to registers.

      (+) This delay depends on the peripheral mapping.

        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]

      Workarounds:

      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been

          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.

  @endverbatim

  ******************************************************************************

  * @attention

  *

  * Copyright (c) 2017 STMicroelectronics.

  * All rights reserved.

  *

  * This software is licensed under terms that can be found in the LICENSE file in

  * the root directory of this software component.

  * If no LICENSE file comes with this software, it is provided AS-IS.

  ******************************************************************************

  */

/* Includes ------------------------------------------------------------------*/

#include "stm32l1xx_hal.h"

/** @addtogroup STM32L1xx_HAL_Driver

  * @{

  */

/** @defgroup RCC RCC

* @brief RCC HAL module driver

  * @{

  */

#ifdef HAL_RCC_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/

/* Private define ------------------------------------------------------------*/

/* Private macro -------------------------------------------------------------*/

/** @defgroup RCC_Private_Macros RCC Private Macros

  * @{

  */

#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()

#define MCO1_GPIO_PORT        GPIOA

#define MCO1_PIN              GPIO_PIN_8

/**

  * @}

  */

/* Private variables ---------------------------------------------------------*/

/** @defgroup RCC_Private_Variables RCC Private Variables

  * @{

  */

extern const uint8_t PLLMulTable[];          /* Defined in CMSIS (system_stm32l0xx.c)*/

/**

  * @}

  */

/* Private function prototypes -----------------------------------------------*/

/** @defgroup RCC_Private_Functions RCC Private Functions

  * @{

  */

static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange);

/**

  * @}

  */

/* Exported functions ---------------------------------------------------------*/

/** @defgroup RCC_Exported_Functions RCC Exported Functions

  * @{

  */

/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions

  *  @brief    Initialization and Configuration functions

  *

  @verbatim

  ===============================================================================

           ##### Initialization and de-initialization functions #####

  ===============================================================================

    [..]

      This section provides functions allowing to configure the internal/external oscillators

      (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1

      and APB2).

    [..] Internal/external clock and PLL configuration

      (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz,

          131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz.

      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through

          the PLL as System clock source.

      (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC

          clock source.

      (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or

          through the PLL as System clock source. Can be used also as RTC clock source.

      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

      (#) PLL (clocked by HSI or HSE), featuring different output clocks:

        (++) The first output is used to generate the high speed system clock (up to 32 MHz)

        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)

      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()

          and if a HSE clock failure occurs(HSE used directly or through PLL as System

          clock source), the System clocks automatically switched to MSI and an interrupt

          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI

          (Non-Maskable Interrupt) exception vector.

      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE,

          HSE or PLL clock (through a configurable prescaler) on PA8 pin.

    [..] System, AHB and APB buses clocks configuration

      (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,

          HSE and PLL.

          The AHB clock (HCLK) is derived from System clock through configurable

          prescaler and used to clock the CPU, memory and peripherals mapped

          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived

          from AHB clock through configurable prescalers and used to clock

          the peripherals mapped on these buses. You can use

          "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:

          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock

              divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()

              macros to configure this clock.

          (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock

              divided by 2 to 16. You have to use __HAL_RCC_LCD_CONFIG()

              macros to configure this clock.

          (+@) USB OTG FS: USB OTG FS require a frequency equal to 48 MHz

              to work correctly. This clock is derived of the main PLL through PLL Multiplier.

          (+@) IWDG clock which is always the LSI clock.

      (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz

          and PCLK1 32 MHz. Depending on the device voltage range, the maximum

          frequency should be adapted accordingly.

  @endverbatim

  * @{

  */

/*

  Additional consideration on the HCLK based on Latency settings:

  +----------------------------------------------------------------------+

  | Latency       |                HCLK clock frequency (MHz)            |

  |               |------------------------------------------------------|

  |               | voltage range 1  | voltage range 2 | voltage range 3 |

  |               |      1.8 V       |     1.5 V       |      1.2 V      |

  |---------------|------------------|-----------------|-----------------|

  |0WS(1CPU cycle)| 0 < HCLK <= 16   | 0 < HCLK <= 8   | 0 < HCLK <= 2   |

  |---------------|------------------|-----------------|-----------------|

  |1WS(2CPU cycle)| 16 < HCLK <= 32  | 8 < HCLK <= 16  | 2 < HCLK <= 4   |

  +----------------------------------------------------------------------+

  The following table gives the different clock source frequencies depending on the product

  voltage range:

  +------------------------------------------------------------------------------------------+

  | Product voltage |                    Clock frequency                                     |

  |                 |------------------|-----------------------------|-----------------------|

  |      range      |   MSI   |   HSI  |              HSE            |          PLL          |

  |-----------------|---------|--------|-----------------------------|-----------------------|

  | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) |         32 MHz        |

  |                 |         |        |      or 24 MHz (crystal)    | (PLLVCO max = 96 MHz) |

  |-----------------|---------|--------|-----------------------------|-----------------------|

  | Range 2 (1.5 V) | 4.2 MHz | 16 MHz |         16 MHz              |         16 MHz        |

  |                 |         |        |                             | (PLLVCO max = 48 MHz) |

  |-----------------|---------|--------|-----------------------------|-----------------------|

  | Range 3 (1.2 V) | 4.2 MHz |   NA   |         8 MHz               |           4 MHz       |

  |                 |         |        |                             | (PLLVCO max = 24 MHz) |

  +------------------------------------------------------------------------------------------+

  */

/**

  * @brief  Resets the RCC clock configuration to the default reset state.

  * @note   The default reset state of the clock configuration is given below:

  *            - MSI ON and used as system clock source

  *            - HSI, HSE and PLL  OFF

  *            - AHB, APB1 and APB2 prescaler set to 1.

  *            - CSS and MCO1 OFF

  *            - All interrupts disabled

  * @note   This function does not modify the configuration of the

  *            - Peripheral clocks

  *            - LSI, LSE and RTC clocks

  * @retval HAL status

  */

HAL_StatusTypeDef HAL_RCC_DeInit(void)

{

  uint32_t tickstart;

  HAL_StatusTypeDef status;

  /* Set MSIClockRange, HSITRIM and MSITRIM bits to the reset values */

  MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSITRIM | RCC_ICSCR_HSITRIM | RCC_ICSCR_MSIRANGE), \

            ((RCC_MSICALIBRATION_DEFAULT << RCC_ICSCR_MSITRIM_Pos) | (RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos) | RCC_ICSCR_MSIRANGE_5));

  /* Set MSION bit */

  SET_BIT(RCC->CR, RCC_CR_MSION);

  /* Get Start Tick*/

  tickstart = HAL_GetTick();

  /* Wait till MSI is ready */

  while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)

  {

    if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Switch SYSCLK to MSI*/

  CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);

  /* Wait till MSI as SYSCLK status is ready */

  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)

  {

    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Update the SystemCoreClock global variable */

  SystemCoreClock = MSI_VALUE;

  /* Configure the source of time base considering new system clock settings  */

  status = HAL_InitTick(uwTickPrio);

  if(status != HAL_OK)

  {

    return status;

  }

  /* Reset HSION, HSEON, CSSON & PLLON bits */

  CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);

  /* Reset HSEBYP bit */

  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);

  /* Get Start Tick*/

  tickstart = HAL_GetTick();

  /* Wait till PLL is not ready */

  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)

  {

    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Reset CFGR register */

  CLEAR_REG(RCC->CFGR);

  /* Disable all interrupts */

  CLEAR_REG(RCC->CIR);

  /* Clear all flags */

#if defined(RCC_LSECSS_SUPPORT)

  WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC |  RCC_CIR_LSECSSC | RCC_CIR_CSSC);

#else

  WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC |  RCC_CIR_CSSC);

#endif

  /* Clear all reset flags */

  SET_BIT(RCC->CSR, RCC_CSR_RMVF);

  return HAL_OK;

}

/**

  * @brief  Initializes the RCC Oscillators according to the specified parameters in the

  *         RCC_OscInitTypeDef.

  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that

  *         contains the configuration information for the RCC Oscillators.

  * @note   The PLL is not disabled when used as system clock.

  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not

  *         supported by this macro. User should request a transition to LSE Off

  *         first and then LSE On or LSE Bypass.

  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not

  *         supported by this macro. User should request a transition to HSE Off

  *         first and then HSE On or HSE Bypass.

  * @retval HAL status

  */

HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)

{

  uint32_t tickstart;

  HAL_StatusTypeDef status;

  uint32_t sysclk_source, pll_config;

  /* Check the parameters */

  if(RCC_OscInitStruct == NULL)

  {

    return HAL_ERROR;

  }

  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();

  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();

  /*------------------------------- HSE Configuration ------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)

  {

    /* Check the parameters */

    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */

    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)

       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))

    {

      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))

      {

        return HAL_ERROR;

      }

    }

    else

    {

      /* Set the new HSE configuration ---------------------------------------*/

      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);

      /* Check the HSE State */

      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)

      {

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSE is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)

        {

          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

      else

      {

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSE is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)

        {

           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

  }

  /*----------------------------- HSI Configuration --------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)

  {

    /* Check the parameters */

    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));

    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */

    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)

       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))

    {

      /* When HSI is used as system clock it will not disabled */

      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))

      {

        return HAL_ERROR;

      }

      /* Otherwise, just the calibration is allowed */

      else

      {

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/

        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);

      }

    }

    else

    {

      /* Check the HSI State */

      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)

      {

        /* Enable the Internal High Speed oscillator (HSI). */

        __HAL_RCC_HSI_ENABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSI is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)

        {

          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/

        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);

      }

      else

      {

        /* Disable the Internal High Speed oscillator (HSI). */

        __HAL_RCC_HSI_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSI is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)

        {

          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

  }

  /*----------------------------- MSI Configuration --------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)

  {

    /* When the MSI is used as system clock it will not be disabled */

    if(sysclk_source == RCC_CFGR_SWS_MSI)

    {

      if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))

      {

        return HAL_ERROR;

      }

      /* Otherwise, just the calibration and MSI range change are allowed */

      else

      {

       /* Check MSICalibrationValue and MSIClockRange input parameters */

        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));

        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)

           must be correctly programmed according to the frequency of the CPU clock

           (HCLK) and the supply voltage of the device. */

        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())

        {

          /* First increase number of wait states update if necessary */

          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)

          {

            return HAL_ERROR;

          }

          /* Selects the Multiple Speed oscillator (MSI) clock range .*/

          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);

          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/

          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);

        }

        else

        {

          /* Else, keep current flash latency while decreasing applies */

          /* Selects the Multiple Speed oscillator (MSI) clock range .*/

          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);

          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/

          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);

          /* Decrease number of wait states update if necessary */

          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)

          {

            return HAL_ERROR;

          }

        }

        /* Update the SystemCoreClock global variable */

        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))

                           >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];

        /* Configure the source of time base considering new system clocks settings*/

        status = HAL_InitTick(uwTickPrio);

        if(status != HAL_OK)

        {

          return status;

        }

      }

    }

    else

    {

      /* Check MSI State */

      assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));

      /* Check the MSI State */

      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)

      {

        /* Enable the Multi Speed oscillator (MSI). */

        __HAL_RCC_MSI_ENABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till MSI is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)

        {

          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

        /* Check MSICalibrationValue and MSIClockRange input parameters */

        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));

        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

        /* Selects the Multiple Speed oscillator (MSI) clock range .*/

        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);

         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/

        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);

      }

      else

      {

        /* Disable the Multi Speed oscillator (MSI). */

        __HAL_RCC_MSI_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till MSI is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)

        {

          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

  }

  /*------------------------------ LSI Configuration -------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)

  {

    /* Check the parameters */

    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */

    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)

    {

      /* Enable the Internal Low Speed oscillator (LSI). */

      __HAL_RCC_LSI_ENABLE();

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSI is ready */

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)

      {

        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    else

    {

      /* Disable the Internal Low Speed oscillator (LSI). */

      __HAL_RCC_LSI_DISABLE();

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSI is disabled */

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)

      {

        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

  }

  /*------------------------------ LSE Configuration -------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)

  {

    FlagStatus       pwrclkchanged = RESET;

    /* Check the parameters */

    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */

    /* Requires to enable write access to Backup Domain of necessary */

    if(__HAL_RCC_PWR_IS_CLK_DISABLED())

    {

      __HAL_RCC_PWR_CLK_ENABLE();

      pwrclkchanged = SET;

    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))

    {

      /* Enable write access to Backup domain */

      SET_BIT(PWR->CR, PWR_CR_DBP);

      /* Wait for Backup domain Write protection disable */

      tickstart = HAL_GetTick();

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))

      {

        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    /* Set the new LSE configuration -----------------------------------------*/

    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);

    /* Check the LSE State */

    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)

    {

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSE is ready */

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)

      {

        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    else

    {

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSE is disabled */

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)

      {

        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    /* Require to disable power clock if necessary */

    if(pwrclkchanged == SET)

    {

      __HAL_RCC_PWR_CLK_DISABLE();

    }

  }

  /*-------------------------------- PLL Configuration -----------------------*/

  /* Check the parameters */

  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)

  {

    /* Check if the PLL is used as system clock or not */

    if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)

    {

      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)

      {

        /* Check the parameters */

        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));

        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));

        assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));

        /* Disable the main PLL. */

        __HAL_RCC_PLL_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)

        {

          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

        /* Configure the main PLL clock source, multiplication and division factors. */

        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,

                             RCC_OscInitStruct->PLL.PLLMUL,

                             RCC_OscInitStruct->PLL.PLLDIV);

        /* Enable the main PLL. */

        __HAL_RCC_PLL_ENABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)

        {

          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

      else

      {

        /* Disable the main PLL. */

        __HAL_RCC_PLL_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)

        {

          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

    else

    {

      /* Check if there is a request to disable the PLL used as System clock source */

      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)

      {

        return HAL_ERROR;

      }

      else

      {

        /* Do not return HAL_ERROR if request repeats the current configuration */

        pll_config = RCC->CFGR;

        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||

           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||

           (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))

        {

          return HAL_ERROR;

        }

      }

    }

  }

  return HAL_OK;

}

/**

  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified

  *         parameters in the RCC_ClkInitStruct.

  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that

  *         contains the configuration information for the RCC peripheral.

  * @param  FLatency FLASH Latency

  *          The value of this parameter depend on device used within the same series

  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency

  *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function

  *

  * @note   The MSI is used (enabled by hardware) as system clock source after

  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case

  *         of failure of the HSE used directly or indirectly as system clock

  *         (if the Clock Security System CSS is enabled).

  *

  * @note   A switch from one clock source to another occurs only if the target

  *         clock source is ready (clock stable after start-up delay or PLL locked).

  *         If a clock source which is not yet ready is selected, the switch will

  *         occur when the clock source will be ready.

  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is

  *         currently used as system clock source.

  * @note   Depending on the device voltage range, the software has to set correctly

  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency

  *         (for more details refer to section above "Initialization/de-initialization functions")

  * @retval HAL status

  */

HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)

{

  uint32_t tickstart;

  HAL_StatusTypeDef status;

  /* Check the parameters */

  if(RCC_ClkInitStruct == NULL)

  {

    return HAL_ERROR;

  }

  assert_param(IS_FLASH_LATENCY(FLatency));

  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)

  must be correctly programmed according to the frequency of the CPU clock

  (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */

  if(FLatency > __HAL_FLASH_GET_LATENCY())

  {

    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */

    __HAL_FLASH_SET_LATENCY(FLatency);

    /* Check that the new number of wait states is taken into account to access the Flash

    memory by reading the FLASH_ACR register */

    if(__HAL_FLASH_GET_LATENCY() != FLatency)

    {

      return HAL_ERROR;

    }

  }

  /*-------------------------- HCLK Configuration --------------------------*/

  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)

  {

    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));

    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);

  }

  /*------------------------- SYSCLK Configuration ---------------------------*/

  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)

  {

    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */

    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)

    {

      /* Check the HSE ready flag */

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)

      {

        return HAL_ERROR;

      }

    }

    /* PLL is selected as System Clock Source */

    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)

    {

      /* Check the PLL ready flag */

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)

      {

        return HAL_ERROR;

      }

    }

    /* HSI is selected as System Clock Source */

    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)

    {

      /* Check the HSI ready flag */

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)

      {

        return HAL_ERROR;

      }

    }

    /* MSI is selected as System Clock Source */

    else

    {

      /* Check the MSI ready flag */

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)

      {

        return HAL_ERROR;

      }

    }

    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);

    /* Get Start Tick */

    tickstart = HAL_GetTick();

    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)

    {

      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)

      {

        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)