Rev 61 | Go to most recent revision | Details | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
56 | mjames | 1 | /** |
2 | ****************************************************************************** |
||
3 | * @file stm32l1xx_hal_i2c.c |
||
4 | * @author MCD Application Team |
||
5 | * @brief I2C HAL module driver. |
||
6 | * This file provides firmware functions to manage the following |
||
7 | * functionalities of the Inter Integrated Circuit (I2C) peripheral: |
||
8 | * + Initialization and de-initialization functions |
||
9 | * + IO operation functions |
||
10 | * + Peripheral State, Mode and Error functions |
||
11 | * |
||
12 | @verbatim |
||
13 | ============================================================================== |
||
14 | ##### How to use this driver ##### |
||
15 | ============================================================================== |
||
16 | [..] |
||
17 | The I2C HAL driver can be used as follows: |
||
18 | |||
19 | (#) Declare a I2C_HandleTypeDef handle structure, for example: |
||
20 | I2C_HandleTypeDef hi2c; |
||
21 | |||
22 | (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: |
||
23 | (##) Enable the I2Cx interface clock |
||
24 | (##) I2C pins configuration |
||
25 | (+++) Enable the clock for the I2C GPIOs |
||
26 | (+++) Configure I2C pins as alternate function open-drain |
||
27 | (##) NVIC configuration if you need to use interrupt process |
||
28 | (+++) Configure the I2Cx interrupt priority |
||
29 | (+++) Enable the NVIC I2C IRQ Channel |
||
30 | (##) DMA Configuration if you need to use DMA process |
||
31 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel |
||
32 | (+++) Enable the DMAx interface clock using |
||
33 | (+++) Configure the DMA handle parameters |
||
34 | (+++) Configure the DMA Tx or Rx channel |
||
35 | (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle |
||
36 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on |
||
37 | the DMA Tx or Rx channel |
||
38 | |||
39 | (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, |
||
40 | Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. |
||
41 | |||
42 | (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware |
||
43 | (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API. |
||
44 | |||
45 | (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() |
||
46 | |||
47 | (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : |
||
48 | |||
49 | *** Polling mode IO operation *** |
||
50 | ================================= |
||
51 | [..] |
||
52 | (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() |
||
53 | (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() |
||
54 | (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() |
||
55 | (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() |
||
56 | |||
57 | *** Polling mode IO MEM operation *** |
||
58 | ===================================== |
||
59 | [..] |
||
60 | (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() |
||
61 | (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() |
||
62 | |||
63 | |||
64 | *** Interrupt mode IO operation *** |
||
65 | =================================== |
||
66 | [..] |
||
67 | (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() |
||
68 | (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can |
||
69 | add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() |
||
70 | (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() |
||
71 | (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can |
||
72 | add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() |
||
73 | (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() |
||
74 | (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can |
||
75 | add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() |
||
76 | (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() |
||
77 | (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can |
||
78 | add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() |
||
79 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
||
80 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
||
81 | (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() |
||
82 | (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can |
||
83 | add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() |
||
84 | |||
85 | *** Interrupt mode or DMA mode IO sequential operation *** |
||
86 | ========================================================== |
||
87 | [..] |
||
88 | (@) These interfaces allow to manage a sequential transfer with a repeated start condition |
||
89 | when a direction change during transfer |
||
90 | [..] |
||
91 | (+) A specific option field manage the different steps of a sequential transfer |
||
92 | (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below: |
||
93 | (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode |
||
94 | (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address |
||
95 | and data to transfer without a final stop condition |
||
96 | (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address |
||
97 | and data to transfer without a final stop condition, an then permit a call the same master sequential interface |
||
98 | several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() |
||
99 | or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) |
||
100 | (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address |
||
101 | and with new data to transfer if the direction change or manage only the new data to transfer |
||
102 | if no direction change and without a final stop condition in both cases |
||
103 | (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address |
||
104 | and with new data to transfer if the direction change or manage only the new data to transfer |
||
105 | if no direction change and with a final stop condition in both cases |
||
106 | (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential |
||
107 | interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). |
||
108 | Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
||
109 | or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
||
110 | or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
||
111 | or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). |
||
112 | Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit |
||
113 | without stopping the communication and so generate a restart condition. |
||
114 | (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential |
||
115 | interface. |
||
116 | Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
||
117 | or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
||
118 | or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
||
119 | or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). |
||
120 | Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. |
||
121 | |||
122 | (+) Differents sequential I2C interfaces are listed below: |
||
123 | (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() |
||
124 | or using @ref HAL_I2C_Master_Seq_Transmit_DMA() |
||
125 | (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can |
||
126 | add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() |
||
127 | (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() |
||
128 | or using @ref HAL_I2C_Master_Seq_Receive_DMA() |
||
129 | (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can |
||
130 | add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() |
||
131 | (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() |
||
132 | (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can |
||
133 | add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() |
||
134 | (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() |
||
135 | (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can |
||
136 | add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). |
||
137 | (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can |
||
138 | add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() |
||
139 | (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() |
||
140 | or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() |
||
141 | (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can |
||
142 | add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() |
||
143 | (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() |
||
144 | or using @ref HAL_I2C_Slave_Seq_Receive_DMA() |
||
145 | (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can |
||
146 | add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() |
||
147 | (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
||
148 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
||
149 | |||
150 | *** Interrupt mode IO MEM operation *** |
||
151 | ======================================= |
||
152 | [..] |
||
153 | (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using |
||
154 | @ref HAL_I2C_Mem_Write_IT() |
||
155 | (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can |
||
156 | add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() |
||
157 | (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using |
||
158 | @ref HAL_I2C_Mem_Read_IT() |
||
159 | (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can |
||
160 | add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() |
||
161 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
||
162 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
||
163 | |||
164 | *** DMA mode IO operation *** |
||
165 | ============================== |
||
166 | [..] |
||
167 | (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using |
||
168 | @ref HAL_I2C_Master_Transmit_DMA() |
||
169 | (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can |
||
170 | add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() |
||
171 | (+) Receive in master mode an amount of data in non-blocking mode (DMA) using |
||
172 | @ref HAL_I2C_Master_Receive_DMA() |
||
173 | (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can |
||
174 | add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() |
||
175 | (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using |
||
176 | @ref HAL_I2C_Slave_Transmit_DMA() |
||
177 | (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can |
||
178 | add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() |
||
179 | (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using |
||
180 | @ref HAL_I2C_Slave_Receive_DMA() |
||
181 | (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can |
||
182 | add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() |
||
183 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
||
184 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
||
185 | (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() |
||
186 | (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can |
||
187 | add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() |
||
188 | |||
189 | *** DMA mode IO MEM operation *** |
||
190 | ================================= |
||
191 | [..] |
||
192 | (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using |
||
193 | @ref HAL_I2C_Mem_Write_DMA() |
||
194 | (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can |
||
195 | add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() |
||
196 | (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using |
||
197 | @ref HAL_I2C_Mem_Read_DMA() |
||
198 | (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can |
||
199 | add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() |
||
200 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
||
201 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
||
202 | |||
203 | |||
204 | *** I2C HAL driver macros list *** |
||
205 | ================================== |
||
206 | [..] |
||
207 | Below the list of most used macros in I2C HAL driver. |
||
208 | |||
209 | (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral |
||
210 | (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral |
||
211 | (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not |
||
212 | (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag |
||
213 | (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt |
||
214 | (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt |
||
215 | |||
216 | *** Callback registration *** |
||
217 | ============================================= |
||
218 | [..] |
||
219 | The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 |
||
220 | allows the user to configure dynamically the driver callbacks. |
||
221 | Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() |
||
222 | to register an interrupt callback. |
||
223 | [..] |
||
224 | Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: |
||
225 | (+) MasterTxCpltCallback : callback for Master transmission end of transfer. |
||
226 | (+) MasterRxCpltCallback : callback for Master reception end of transfer. |
||
227 | (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. |
||
228 | (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. |
||
229 | (+) ListenCpltCallback : callback for end of listen mode. |
||
230 | (+) MemTxCpltCallback : callback for Memory transmission end of transfer. |
||
231 | (+) MemRxCpltCallback : callback for Memory reception end of transfer. |
||
232 | (+) ErrorCallback : callback for error detection. |
||
233 | (+) AbortCpltCallback : callback for abort completion process. |
||
234 | (+) MspInitCallback : callback for Msp Init. |
||
235 | (+) MspDeInitCallback : callback for Msp DeInit. |
||
236 | This function takes as parameters the HAL peripheral handle, the Callback ID |
||
237 | and a pointer to the user callback function. |
||
238 | [..] |
||
239 | For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). |
||
240 | [..] |
||
241 | Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default |
||
242 | weak function. |
||
243 | @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, |
||
244 | and the Callback ID. |
||
245 | This function allows to reset following callbacks: |
||
246 | (+) MasterTxCpltCallback : callback for Master transmission end of transfer. |
||
247 | (+) MasterRxCpltCallback : callback for Master reception end of transfer. |
||
248 | (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. |
||
249 | (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. |
||
250 | (+) ListenCpltCallback : callback for end of listen mode. |
||
251 | (+) MemTxCpltCallback : callback for Memory transmission end of transfer. |
||
252 | (+) MemRxCpltCallback : callback for Memory reception end of transfer. |
||
253 | (+) ErrorCallback : callback for error detection. |
||
254 | (+) AbortCpltCallback : callback for abort completion process. |
||
255 | (+) MspInitCallback : callback for Msp Init. |
||
256 | (+) MspDeInitCallback : callback for Msp DeInit. |
||
257 | [..] |
||
258 | For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). |
||
259 | [..] |
||
260 | By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET |
||
261 | all callbacks are set to the corresponding weak functions: |
||
262 | examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). |
||
263 | Exception done for MspInit and MspDeInit functions that are |
||
264 | reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when |
||
265 | these callbacks are null (not registered beforehand). |
||
266 | If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() |
||
267 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
||
268 | [..] |
||
269 | Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. |
||
270 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
||
271 | in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, |
||
272 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
||
273 | Then, the user first registers the MspInit/MspDeInit user callbacks |
||
274 | using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() |
||
275 | or @ref HAL_I2C_Init() function. |
||
276 | [..] |
||
277 | When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or |
||
278 | not defined, the callback registration feature is not available and all callbacks |
||
279 | are set to the corresponding weak functions. |
||
280 | |||
281 | |||
282 | |||
283 | [..] |
||
284 | (@) You can refer to the I2C HAL driver header file for more useful macros |
||
285 | |||
286 | @endverbatim |
||
287 | ****************************************************************************** |
||
288 | * @attention |
||
289 | * |
||
290 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||
291 | * All rights reserved.</center></h2> |
||
292 | * |
||
293 | * This software component is licensed by ST under BSD 3-Clause license, |
||
294 | * the "License"; You may not use this file except in compliance with the |
||
295 | * License. You may obtain a copy of the License at: |
||
296 | * opensource.org/licenses/BSD-3-Clause |
||
297 | * |
||
298 | ****************************************************************************** |
||
299 | */ |
||
300 | |||
301 | /* Includes ------------------------------------------------------------------*/ |
||
302 | #include "stm32l1xx_hal.h" |
||
303 | |||
304 | /** @addtogroup STM32L1xx_HAL_Driver |
||
305 | * @{ |
||
306 | */ |
||
307 | |||
308 | /** @defgroup I2C I2C |
||
309 | * @brief I2C HAL module driver |
||
310 | * @{ |
||
311 | */ |
||
312 | |||
313 | #ifdef HAL_I2C_MODULE_ENABLED |
||
314 | |||
315 | /* Private typedef -----------------------------------------------------------*/ |
||
316 | /* Private define ------------------------------------------------------------*/ |
||
317 | /** @addtogroup I2C_Private_Define |
||
318 | * @{ |
||
319 | */ |
||
320 | #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ |
||
321 | #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ |
||
322 | #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ |
||
323 | #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ |
||
324 | |||
325 | /* Private define for @ref PreviousState usage */ |
||
326 | #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ |
||
327 | #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ |
||
328 | #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ |
||
329 | #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ |
||
330 | #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ |
||
331 | #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ |
||
332 | |||
333 | /** |
||
334 | * @} |
||
335 | */ |
||
336 | |||
337 | /* Private macro -------------------------------------------------------------*/ |
||
338 | /* Private variables ---------------------------------------------------------*/ |
||
339 | /* Private function prototypes -----------------------------------------------*/ |
||
340 | |||
341 | /** @defgroup I2C_Private_Functions I2C Private Functions |
||
342 | * @{ |
||
343 | */ |
||
344 | /* Private functions to handle DMA transfer */ |
||
345 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); |
||
346 | static void I2C_DMAError(DMA_HandleTypeDef *hdma); |
||
347 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); |
||
348 | |||
349 | static void I2C_ITError(I2C_HandleTypeDef *hi2c); |
||
350 | |||
351 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
||
352 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
||
353 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
||
354 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
||
355 | |||
356 | /* Private functions to handle flags during polling transfer */ |
||
357 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); |
||
358 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); |
||
359 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
||
360 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
||
361 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
||
362 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
||
363 | static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); |
||
364 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); |
||
365 | |||
366 | /* Private functions for I2C transfer IRQ handler */ |
||
367 | static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); |
||
368 | static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); |
||
369 | static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); |
||
370 | static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); |
||
371 | static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); |
||
372 | static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); |
||
373 | static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); |
||
374 | |||
375 | static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); |
||
376 | static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); |
||
377 | static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); |
||
378 | static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); |
||
379 | static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); |
||
380 | static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); |
||
381 | static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); |
||
382 | |||
383 | static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); |
||
384 | |||
385 | /* Private function to Convert Specific options */ |
||
386 | static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); |
||
387 | /** |
||
388 | * @} |
||
389 | */ |
||
390 | |||
391 | /* Exported functions --------------------------------------------------------*/ |
||
392 | |||
393 | /** @defgroup I2C_Exported_Functions I2C Exported Functions |
||
394 | * @{ |
||
395 | */ |
||
396 | |||
397 | /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions |
||
398 | * @brief Initialization and Configuration functions |
||
399 | * |
||
400 | @verbatim |
||
401 | =============================================================================== |
||
402 | ##### Initialization and de-initialization functions ##### |
||
403 | =============================================================================== |
||
404 | [..] This subsection provides a set of functions allowing to initialize and |
||
405 | deinitialize the I2Cx peripheral: |
||
406 | |||
407 | (+) User must Implement HAL_I2C_MspInit() function in which he configures |
||
408 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). |
||
409 | |||
410 | (+) Call the function HAL_I2C_Init() to configure the selected device with |
||
411 | the selected configuration: |
||
412 | (++) Communication Speed |
||
413 | (++) Duty cycle |
||
414 | (++) Addressing mode |
||
415 | (++) Own Address 1 |
||
416 | (++) Dual Addressing mode |
||
417 | (++) Own Address 2 |
||
418 | (++) General call mode |
||
419 | (++) Nostretch mode |
||
420 | |||
421 | (+) Call the function HAL_I2C_DeInit() to restore the default configuration |
||
422 | of the selected I2Cx peripheral. |
||
423 | |||
424 | @endverbatim |
||
425 | * @{ |
||
426 | */ |
||
427 | |||
428 | /** |
||
429 | * @brief Initializes the I2C according to the specified parameters |
||
430 | * in the I2C_InitTypeDef and initialize the associated handle. |
||
431 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
432 | * the configuration information for the specified I2C. |
||
433 | * @retval HAL status |
||
434 | */ |
||
435 | HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) |
||
436 | { |
||
437 | uint32_t freqrange; |
||
438 | uint32_t pclk1; |
||
439 | |||
440 | /* Check the I2C handle allocation */ |
||
441 | if (hi2c == NULL) |
||
442 | { |
||
443 | return HAL_ERROR; |
||
444 | } |
||
445 | |||
446 | /* Check the parameters */ |
||
447 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
||
448 | assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); |
||
449 | assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); |
||
450 | assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); |
||
451 | assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); |
||
452 | assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); |
||
453 | assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); |
||
454 | assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); |
||
455 | assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); |
||
456 | |||
457 | if (hi2c->State == HAL_I2C_STATE_RESET) |
||
458 | { |
||
459 | /* Allocate lock resource and initialize it */ |
||
460 | hi2c->Lock = HAL_UNLOCKED; |
||
461 | |||
462 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
463 | /* Init the I2C Callback settings */ |
||
464 | hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ |
||
465 | hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ |
||
466 | hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ |
||
467 | hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ |
||
468 | hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ |
||
469 | hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ |
||
470 | hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ |
||
471 | hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ |
||
472 | hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ |
||
473 | hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ |
||
474 | |||
475 | if (hi2c->MspInitCallback == NULL) |
||
476 | { |
||
477 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
||
478 | } |
||
479 | |||
480 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
||
481 | hi2c->MspInitCallback(hi2c); |
||
482 | #else |
||
483 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
||
484 | HAL_I2C_MspInit(hi2c); |
||
485 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
486 | } |
||
487 | |||
488 | hi2c->State = HAL_I2C_STATE_BUSY; |
||
489 | |||
490 | /* Disable the selected I2C peripheral */ |
||
491 | __HAL_I2C_DISABLE(hi2c); |
||
492 | |||
493 | /*Reset I2C*/ |
||
494 | hi2c->Instance->CR1 |= I2C_CR1_SWRST; |
||
495 | hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; |
||
496 | |||
497 | /* Get PCLK1 frequency */ |
||
498 | pclk1 = HAL_RCC_GetPCLK1Freq(); |
||
499 | |||
500 | /* Check the minimum allowed PCLK1 frequency */ |
||
501 | if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) |
||
502 | { |
||
503 | return HAL_ERROR; |
||
504 | } |
||
505 | |||
506 | /* Calculate frequency range */ |
||
507 | freqrange = I2C_FREQRANGE(pclk1); |
||
508 | |||
509 | /*---------------------------- I2Cx CR2 Configuration ----------------------*/ |
||
510 | /* Configure I2Cx: Frequency range */ |
||
511 | MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); |
||
512 | |||
513 | /*---------------------------- I2Cx TRISE Configuration --------------------*/ |
||
514 | /* Configure I2Cx: Rise Time */ |
||
515 | MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); |
||
516 | |||
517 | /*---------------------------- I2Cx CCR Configuration ----------------------*/ |
||
518 | /* Configure I2Cx: Speed */ |
||
519 | MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); |
||
520 | |||
521 | /*---------------------------- I2Cx CR1 Configuration ----------------------*/ |
||
522 | /* Configure I2Cx: Generalcall and NoStretch mode */ |
||
523 | MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); |
||
524 | |||
525 | /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ |
||
526 | /* Configure I2Cx: Own Address1 and addressing mode */ |
||
527 | MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); |
||
528 | |||
529 | /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ |
||
530 | /* Configure I2Cx: Dual mode and Own Address2 */ |
||
531 | MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); |
||
532 | |||
533 | /* Enable the selected I2C peripheral */ |
||
534 | __HAL_I2C_ENABLE(hi2c); |
||
535 | |||
536 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
537 | hi2c->State = HAL_I2C_STATE_READY; |
||
538 | hi2c->PreviousState = I2C_STATE_NONE; |
||
539 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
540 | |||
541 | return HAL_OK; |
||
542 | } |
||
543 | |||
544 | /** |
||
545 | * @brief DeInitialize the I2C peripheral. |
||
546 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
547 | * the configuration information for the specified I2C. |
||
548 | * @retval HAL status |
||
549 | */ |
||
550 | HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) |
||
551 | { |
||
552 | /* Check the I2C handle allocation */ |
||
553 | if (hi2c == NULL) |
||
554 | { |
||
555 | return HAL_ERROR; |
||
556 | } |
||
557 | |||
558 | /* Check the parameters */ |
||
559 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
||
560 | |||
561 | hi2c->State = HAL_I2C_STATE_BUSY; |
||
562 | |||
563 | /* Disable the I2C Peripheral Clock */ |
||
564 | __HAL_I2C_DISABLE(hi2c); |
||
565 | |||
566 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
567 | if (hi2c->MspDeInitCallback == NULL) |
||
568 | { |
||
569 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
||
570 | } |
||
571 | |||
572 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
||
573 | hi2c->MspDeInitCallback(hi2c); |
||
574 | #else |
||
575 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
||
576 | HAL_I2C_MspDeInit(hi2c); |
||
577 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
578 | |||
579 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
580 | hi2c->State = HAL_I2C_STATE_RESET; |
||
581 | hi2c->PreviousState = I2C_STATE_NONE; |
||
582 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
583 | |||
584 | /* Release Lock */ |
||
585 | __HAL_UNLOCK(hi2c); |
||
586 | |||
587 | return HAL_OK; |
||
588 | } |
||
589 | |||
590 | /** |
||
591 | * @brief Initialize the I2C MSP. |
||
592 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
593 | * the configuration information for the specified I2C. |
||
594 | * @retval None |
||
595 | */ |
||
596 | __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) |
||
597 | { |
||
598 | /* Prevent unused argument(s) compilation warning */ |
||
599 | UNUSED(hi2c); |
||
600 | |||
601 | /* NOTE : This function should not be modified, when the callback is needed, |
||
602 | the HAL_I2C_MspInit could be implemented in the user file |
||
603 | */ |
||
604 | } |
||
605 | |||
606 | /** |
||
607 | * @brief DeInitialize the I2C MSP. |
||
608 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
609 | * the configuration information for the specified I2C. |
||
610 | * @retval None |
||
611 | */ |
||
612 | __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) |
||
613 | { |
||
614 | /* Prevent unused argument(s) compilation warning */ |
||
615 | UNUSED(hi2c); |
||
616 | |||
617 | /* NOTE : This function should not be modified, when the callback is needed, |
||
618 | the HAL_I2C_MspDeInit could be implemented in the user file |
||
619 | */ |
||
620 | } |
||
621 | |||
622 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
623 | /** |
||
624 | * @brief Register a User I2C Callback |
||
625 | * To be used instead of the weak predefined callback |
||
626 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
627 | * the configuration information for the specified I2C. |
||
628 | * @param CallbackID ID of the callback to be registered |
||
629 | * This parameter can be one of the following values: |
||
630 | * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID |
||
631 | * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID |
||
632 | * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID |
||
633 | * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID |
||
634 | * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID |
||
635 | * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID |
||
636 | * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID |
||
637 | * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID |
||
638 | * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID |
||
639 | * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID |
||
640 | * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID |
||
641 | * @param pCallback pointer to the Callback function |
||
642 | * @retval HAL status |
||
643 | */ |
||
644 | HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) |
||
645 | { |
||
646 | HAL_StatusTypeDef status = HAL_OK; |
||
647 | |||
648 | if (pCallback == NULL) |
||
649 | { |
||
650 | /* Update the error code */ |
||
651 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
652 | |||
653 | return HAL_ERROR; |
||
654 | } |
||
655 | /* Process locked */ |
||
656 | __HAL_LOCK(hi2c); |
||
657 | |||
658 | if (HAL_I2C_STATE_READY == hi2c->State) |
||
659 | { |
||
660 | switch (CallbackID) |
||
661 | { |
||
662 | case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : |
||
663 | hi2c->MasterTxCpltCallback = pCallback; |
||
664 | break; |
||
665 | |||
666 | case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : |
||
667 | hi2c->MasterRxCpltCallback = pCallback; |
||
668 | break; |
||
669 | |||
670 | case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : |
||
671 | hi2c->SlaveTxCpltCallback = pCallback; |
||
672 | break; |
||
673 | |||
674 | case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : |
||
675 | hi2c->SlaveRxCpltCallback = pCallback; |
||
676 | break; |
||
677 | |||
678 | case HAL_I2C_LISTEN_COMPLETE_CB_ID : |
||
679 | hi2c->ListenCpltCallback = pCallback; |
||
680 | break; |
||
681 | |||
682 | case HAL_I2C_MEM_TX_COMPLETE_CB_ID : |
||
683 | hi2c->MemTxCpltCallback = pCallback; |
||
684 | break; |
||
685 | |||
686 | case HAL_I2C_MEM_RX_COMPLETE_CB_ID : |
||
687 | hi2c->MemRxCpltCallback = pCallback; |
||
688 | break; |
||
689 | |||
690 | case HAL_I2C_ERROR_CB_ID : |
||
691 | hi2c->ErrorCallback = pCallback; |
||
692 | break; |
||
693 | |||
694 | case HAL_I2C_ABORT_CB_ID : |
||
695 | hi2c->AbortCpltCallback = pCallback; |
||
696 | break; |
||
697 | |||
698 | case HAL_I2C_MSPINIT_CB_ID : |
||
699 | hi2c->MspInitCallback = pCallback; |
||
700 | break; |
||
701 | |||
702 | case HAL_I2C_MSPDEINIT_CB_ID : |
||
703 | hi2c->MspDeInitCallback = pCallback; |
||
704 | break; |
||
705 | |||
706 | default : |
||
707 | /* Update the error code */ |
||
708 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
709 | |||
710 | /* Return error status */ |
||
711 | status = HAL_ERROR; |
||
712 | break; |
||
713 | } |
||
714 | } |
||
715 | else if (HAL_I2C_STATE_RESET == hi2c->State) |
||
716 | { |
||
717 | switch (CallbackID) |
||
718 | { |
||
719 | case HAL_I2C_MSPINIT_CB_ID : |
||
720 | hi2c->MspInitCallback = pCallback; |
||
721 | break; |
||
722 | |||
723 | case HAL_I2C_MSPDEINIT_CB_ID : |
||
724 | hi2c->MspDeInitCallback = pCallback; |
||
725 | break; |
||
726 | |||
727 | default : |
||
728 | /* Update the error code */ |
||
729 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
730 | |||
731 | /* Return error status */ |
||
732 | status = HAL_ERROR; |
||
733 | break; |
||
734 | } |
||
735 | } |
||
736 | else |
||
737 | { |
||
738 | /* Update the error code */ |
||
739 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
740 | |||
741 | /* Return error status */ |
||
742 | status = HAL_ERROR; |
||
743 | } |
||
744 | |||
745 | /* Release Lock */ |
||
746 | __HAL_UNLOCK(hi2c); |
||
747 | return status; |
||
748 | } |
||
749 | |||
750 | /** |
||
751 | * @brief Unregister an I2C Callback |
||
752 | * I2C callback is redirected to the weak predefined callback |
||
753 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
754 | * the configuration information for the specified I2C. |
||
755 | * @param CallbackID ID of the callback to be unregistered |
||
756 | * This parameter can be one of the following values: |
||
757 | * This parameter can be one of the following values: |
||
758 | * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID |
||
759 | * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID |
||
760 | * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID |
||
761 | * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID |
||
762 | * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID |
||
763 | * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID |
||
764 | * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID |
||
765 | * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID |
||
766 | * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID |
||
767 | * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID |
||
768 | * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID |
||
769 | * @retval HAL status |
||
770 | */ |
||
771 | HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) |
||
772 | { |
||
773 | HAL_StatusTypeDef status = HAL_OK; |
||
774 | |||
775 | /* Process locked */ |
||
776 | __HAL_LOCK(hi2c); |
||
777 | |||
778 | if (HAL_I2C_STATE_READY == hi2c->State) |
||
779 | { |
||
780 | switch (CallbackID) |
||
781 | { |
||
782 | case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : |
||
783 | hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ |
||
784 | break; |
||
785 | |||
786 | case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : |
||
787 | hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ |
||
788 | break; |
||
789 | |||
790 | case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : |
||
791 | hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ |
||
792 | break; |
||
793 | |||
794 | case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : |
||
795 | hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ |
||
796 | break; |
||
797 | |||
798 | case HAL_I2C_LISTEN_COMPLETE_CB_ID : |
||
799 | hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ |
||
800 | break; |
||
801 | |||
802 | case HAL_I2C_MEM_TX_COMPLETE_CB_ID : |
||
803 | hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ |
||
804 | break; |
||
805 | |||
806 | case HAL_I2C_MEM_RX_COMPLETE_CB_ID : |
||
807 | hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ |
||
808 | break; |
||
809 | |||
810 | case HAL_I2C_ERROR_CB_ID : |
||
811 | hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ |
||
812 | break; |
||
813 | |||
814 | case HAL_I2C_ABORT_CB_ID : |
||
815 | hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ |
||
816 | break; |
||
817 | |||
818 | case HAL_I2C_MSPINIT_CB_ID : |
||
819 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
||
820 | break; |
||
821 | |||
822 | case HAL_I2C_MSPDEINIT_CB_ID : |
||
823 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
||
824 | break; |
||
825 | |||
826 | default : |
||
827 | /* Update the error code */ |
||
828 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
829 | |||
830 | /* Return error status */ |
||
831 | status = HAL_ERROR; |
||
832 | break; |
||
833 | } |
||
834 | } |
||
835 | else if (HAL_I2C_STATE_RESET == hi2c->State) |
||
836 | { |
||
837 | switch (CallbackID) |
||
838 | { |
||
839 | case HAL_I2C_MSPINIT_CB_ID : |
||
840 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
||
841 | break; |
||
842 | |||
843 | case HAL_I2C_MSPDEINIT_CB_ID : |
||
844 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
||
845 | break; |
||
846 | |||
847 | default : |
||
848 | /* Update the error code */ |
||
849 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
850 | |||
851 | /* Return error status */ |
||
852 | status = HAL_ERROR; |
||
853 | break; |
||
854 | } |
||
855 | } |
||
856 | else |
||
857 | { |
||
858 | /* Update the error code */ |
||
859 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
860 | |||
861 | /* Return error status */ |
||
862 | status = HAL_ERROR; |
||
863 | } |
||
864 | |||
865 | /* Release Lock */ |
||
866 | __HAL_UNLOCK(hi2c); |
||
867 | return status; |
||
868 | } |
||
869 | |||
870 | /** |
||
871 | * @brief Register the Slave Address Match I2C Callback |
||
872 | * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback |
||
873 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
874 | * the configuration information for the specified I2C. |
||
875 | * @param pCallback pointer to the Address Match Callback function |
||
876 | * @retval HAL status |
||
877 | */ |
||
878 | HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) |
||
879 | { |
||
880 | HAL_StatusTypeDef status = HAL_OK; |
||
881 | |||
882 | if (pCallback == NULL) |
||
883 | { |
||
884 | /* Update the error code */ |
||
885 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
886 | |||
887 | return HAL_ERROR; |
||
888 | } |
||
889 | /* Process locked */ |
||
890 | __HAL_LOCK(hi2c); |
||
891 | |||
892 | if (HAL_I2C_STATE_READY == hi2c->State) |
||
893 | { |
||
894 | hi2c->AddrCallback = pCallback; |
||
895 | } |
||
896 | else |
||
897 | { |
||
898 | /* Update the error code */ |
||
899 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
900 | |||
901 | /* Return error status */ |
||
902 | status = HAL_ERROR; |
||
903 | } |
||
904 | |||
905 | /* Release Lock */ |
||
906 | __HAL_UNLOCK(hi2c); |
||
907 | return status; |
||
908 | } |
||
909 | |||
910 | /** |
||
911 | * @brief UnRegister the Slave Address Match I2C Callback |
||
912 | * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback |
||
913 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
914 | * the configuration information for the specified I2C. |
||
915 | * @retval HAL status |
||
916 | */ |
||
917 | HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) |
||
918 | { |
||
919 | HAL_StatusTypeDef status = HAL_OK; |
||
920 | |||
921 | /* Process locked */ |
||
922 | __HAL_LOCK(hi2c); |
||
923 | |||
924 | if (HAL_I2C_STATE_READY == hi2c->State) |
||
925 | { |
||
926 | hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ |
||
927 | } |
||
928 | else |
||
929 | { |
||
930 | /* Update the error code */ |
||
931 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
||
932 | |||
933 | /* Return error status */ |
||
934 | status = HAL_ERROR; |
||
935 | } |
||
936 | |||
937 | /* Release Lock */ |
||
938 | __HAL_UNLOCK(hi2c); |
||
939 | return status; |
||
940 | } |
||
941 | |||
942 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
943 | |||
944 | /** |
||
945 | * @} |
||
946 | */ |
||
947 | |||
948 | /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions |
||
949 | * @brief Data transfers functions |
||
950 | * |
||
951 | @verbatim |
||
952 | =============================================================================== |
||
953 | ##### IO operation functions ##### |
||
954 | =============================================================================== |
||
955 | [..] |
||
956 | This subsection provides a set of functions allowing to manage the I2C data |
||
957 | transfers. |
||
958 | |||
959 | (#) There are two modes of transfer: |
||
960 | (++) Blocking mode : The communication is performed in the polling mode. |
||
961 | The status of all data processing is returned by the same function |
||
962 | after finishing transfer. |
||
963 | (++) No-Blocking mode : The communication is performed using Interrupts |
||
964 | or DMA. These functions return the status of the transfer startup. |
||
965 | The end of the data processing will be indicated through the |
||
966 | dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when |
||
967 | using DMA mode. |
||
968 | |||
969 | (#) Blocking mode functions are : |
||
970 | (++) HAL_I2C_Master_Transmit() |
||
971 | (++) HAL_I2C_Master_Receive() |
||
972 | (++) HAL_I2C_Slave_Transmit() |
||
973 | (++) HAL_I2C_Slave_Receive() |
||
974 | (++) HAL_I2C_Mem_Write() |
||
975 | (++) HAL_I2C_Mem_Read() |
||
976 | (++) HAL_I2C_IsDeviceReady() |
||
977 | |||
978 | (#) No-Blocking mode functions with Interrupt are : |
||
979 | (++) HAL_I2C_Master_Transmit_IT() |
||
980 | (++) HAL_I2C_Master_Receive_IT() |
||
981 | (++) HAL_I2C_Slave_Transmit_IT() |
||
982 | (++) HAL_I2C_Slave_Receive_IT() |
||
983 | (++) HAL_I2C_Mem_Write_IT() |
||
984 | (++) HAL_I2C_Mem_Read_IT() |
||
985 | (++) HAL_I2C_Master_Seq_Transmit_IT() |
||
986 | (++) HAL_I2C_Master_Seq_Receive_IT() |
||
987 | (++) HAL_I2C_Slave_Seq_Transmit_IT() |
||
988 | (++) HAL_I2C_Slave_Seq_Receive_IT() |
||
989 | (++) HAL_I2C_EnableListen_IT() |
||
990 | (++) HAL_I2C_DisableListen_IT() |
||
991 | (++) HAL_I2C_Master_Abort_IT() |
||
992 | |||
993 | (#) No-Blocking mode functions with DMA are : |
||
994 | (++) HAL_I2C_Master_Transmit_DMA() |
||
995 | (++) HAL_I2C_Master_Receive_DMA() |
||
996 | (++) HAL_I2C_Slave_Transmit_DMA() |
||
997 | (++) HAL_I2C_Slave_Receive_DMA() |
||
998 | (++) HAL_I2C_Mem_Write_DMA() |
||
999 | (++) HAL_I2C_Mem_Read_DMA() |
||
1000 | (++) HAL_I2C_Master_Seq_Transmit_DMA() |
||
1001 | (++) HAL_I2C_Master_Seq_Receive_DMA() |
||
1002 | (++) HAL_I2C_Slave_Seq_Transmit_DMA() |
||
1003 | (++) HAL_I2C_Slave_Seq_Receive_DMA() |
||
1004 | |||
1005 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
||
1006 | (++) HAL_I2C_MasterTxCpltCallback() |
||
1007 | (++) HAL_I2C_MasterRxCpltCallback() |
||
1008 | (++) HAL_I2C_SlaveTxCpltCallback() |
||
1009 | (++) HAL_I2C_SlaveRxCpltCallback() |
||
1010 | (++) HAL_I2C_MemTxCpltCallback() |
||
1011 | (++) HAL_I2C_MemRxCpltCallback() |
||
1012 | (++) HAL_I2C_AddrCallback() |
||
1013 | (++) HAL_I2C_ListenCpltCallback() |
||
1014 | (++) HAL_I2C_ErrorCallback() |
||
1015 | (++) HAL_I2C_AbortCpltCallback() |
||
1016 | |||
1017 | @endverbatim |
||
1018 | * @{ |
||
1019 | */ |
||
1020 | |||
1021 | /** |
||
1022 | * @brief Transmits in master mode an amount of data in blocking mode. |
||
1023 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1024 | * the configuration information for the specified I2C. |
||
1025 | * @param DevAddress Target device address: The device 7 bits address value |
||
1026 | * in datasheet must be shifted to the left before calling the interface |
||
1027 | * @param pData Pointer to data buffer |
||
1028 | * @param Size Amount of data to be sent |
||
1029 | * @param Timeout Timeout duration |
||
1030 | * @retval HAL status |
||
1031 | */ |
||
1032 | HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
1033 | { |
||
1034 | /* Init tickstart for timeout management*/ |
||
1035 | uint32_t tickstart = HAL_GetTick(); |
||
1036 | |||
1037 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1038 | { |
||
1039 | /* Wait until BUSY flag is reset */ |
||
1040 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
1041 | { |
||
1042 | return HAL_BUSY; |
||
1043 | } |
||
1044 | |||
1045 | /* Process Locked */ |
||
1046 | __HAL_LOCK(hi2c); |
||
1047 | |||
1048 | /* Check if the I2C is already enabled */ |
||
1049 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1050 | { |
||
1051 | /* Enable I2C peripheral */ |
||
1052 | __HAL_I2C_ENABLE(hi2c); |
||
1053 | } |
||
1054 | |||
1055 | /* Disable Pos */ |
||
1056 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1057 | |||
1058 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
1059 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
1060 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1061 | |||
1062 | /* Prepare transfer parameters */ |
||
1063 | hi2c->pBuffPtr = pData; |
||
1064 | hi2c->XferCount = Size; |
||
1065 | hi2c->XferSize = hi2c->XferCount; |
||
1066 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1067 | |||
1068 | /* Send Slave Address */ |
||
1069 | if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
||
1070 | { |
||
1071 | return HAL_ERROR; |
||
1072 | } |
||
1073 | |||
1074 | /* Clear ADDR flag */ |
||
1075 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1076 | |||
1077 | while (hi2c->XferSize > 0U) |
||
1078 | { |
||
1079 | /* Wait until TXE flag is set */ |
||
1080 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1081 | { |
||
1082 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
1083 | { |
||
1084 | /* Generate Stop */ |
||
1085 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1086 | } |
||
1087 | return HAL_ERROR; |
||
1088 | } |
||
1089 | |||
1090 | /* Write data to DR */ |
||
1091 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
1092 | |||
1093 | /* Increment Buffer pointer */ |
||
1094 | hi2c->pBuffPtr++; |
||
1095 | |||
1096 | /* Update counter */ |
||
1097 | hi2c->XferCount--; |
||
1098 | hi2c->XferSize--; |
||
1099 | |||
1100 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
1101 | { |
||
1102 | /* Write data to DR */ |
||
1103 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
1104 | |||
1105 | /* Increment Buffer pointer */ |
||
1106 | hi2c->pBuffPtr++; |
||
1107 | |||
1108 | /* Update counter */ |
||
1109 | hi2c->XferCount--; |
||
1110 | hi2c->XferSize--; |
||
1111 | } |
||
1112 | |||
1113 | /* Wait until BTF flag is set */ |
||
1114 | if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1115 | { |
||
1116 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
1117 | { |
||
1118 | /* Generate Stop */ |
||
1119 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1120 | } |
||
1121 | return HAL_ERROR; |
||
1122 | } |
||
1123 | } |
||
1124 | |||
1125 | /* Generate Stop */ |
||
1126 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1127 | |||
1128 | hi2c->State = HAL_I2C_STATE_READY; |
||
1129 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1130 | |||
1131 | /* Process Unlocked */ |
||
1132 | __HAL_UNLOCK(hi2c); |
||
1133 | |||
1134 | return HAL_OK; |
||
1135 | } |
||
1136 | else |
||
1137 | { |
||
1138 | return HAL_BUSY; |
||
1139 | } |
||
1140 | } |
||
1141 | |||
1142 | /** |
||
1143 | * @brief Receives in master mode an amount of data in blocking mode. |
||
1144 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1145 | * the configuration information for the specified I2C. |
||
1146 | * @param DevAddress Target device address: The device 7 bits address value |
||
1147 | * in datasheet must be shifted to the left before calling the interface |
||
1148 | * @param pData Pointer to data buffer |
||
1149 | * @param Size Amount of data to be sent |
||
1150 | * @param Timeout Timeout duration |
||
1151 | * @retval HAL status |
||
1152 | */ |
||
1153 | HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
1154 | { |
||
1155 | /* Init tickstart for timeout management*/ |
||
1156 | uint32_t tickstart = HAL_GetTick(); |
||
1157 | |||
1158 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1159 | { |
||
1160 | /* Wait until BUSY flag is reset */ |
||
1161 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
1162 | { |
||
1163 | return HAL_BUSY; |
||
1164 | } |
||
1165 | |||
1166 | /* Process Locked */ |
||
1167 | __HAL_LOCK(hi2c); |
||
1168 | |||
1169 | /* Check if the I2C is already enabled */ |
||
1170 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1171 | { |
||
1172 | /* Enable I2C peripheral */ |
||
1173 | __HAL_I2C_ENABLE(hi2c); |
||
1174 | } |
||
1175 | |||
1176 | /* Disable Pos */ |
||
1177 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1178 | |||
1179 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
1180 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
1181 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1182 | |||
1183 | /* Prepare transfer parameters */ |
||
1184 | hi2c->pBuffPtr = pData; |
||
1185 | hi2c->XferCount = Size; |
||
1186 | hi2c->XferSize = hi2c->XferCount; |
||
1187 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1188 | |||
1189 | /* Send Slave Address */ |
||
1190 | if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
||
1191 | { |
||
1192 | return HAL_ERROR; |
||
1193 | } |
||
1194 | |||
1195 | if (hi2c->XferSize == 0U) |
||
1196 | { |
||
1197 | /* Clear ADDR flag */ |
||
1198 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1199 | |||
1200 | /* Generate Stop */ |
||
1201 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1202 | } |
||
1203 | else if (hi2c->XferSize == 1U) |
||
1204 | { |
||
1205 | /* Disable Acknowledge */ |
||
1206 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1207 | |||
1208 | /* Clear ADDR flag */ |
||
1209 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1210 | |||
1211 | /* Generate Stop */ |
||
1212 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1213 | } |
||
1214 | else if (hi2c->XferSize == 2U) |
||
1215 | { |
||
1216 | /* Disable Acknowledge */ |
||
1217 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1218 | |||
1219 | /* Enable Pos */ |
||
1220 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1221 | |||
1222 | /* Clear ADDR flag */ |
||
1223 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1224 | } |
||
1225 | else |
||
1226 | { |
||
1227 | /* Enable Acknowledge */ |
||
1228 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1229 | |||
1230 | /* Clear ADDR flag */ |
||
1231 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1232 | } |
||
1233 | |||
1234 | while (hi2c->XferSize > 0U) |
||
1235 | { |
||
1236 | if (hi2c->XferSize <= 3U) |
||
1237 | { |
||
1238 | /* One byte */ |
||
1239 | if (hi2c->XferSize == 1U) |
||
1240 | { |
||
1241 | /* Wait until RXNE flag is set */ |
||
1242 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1243 | { |
||
1244 | return HAL_ERROR; |
||
1245 | } |
||
1246 | |||
1247 | /* Read data from DR */ |
||
1248 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1249 | |||
1250 | /* Increment Buffer pointer */ |
||
1251 | hi2c->pBuffPtr++; |
||
1252 | |||
1253 | /* Update counter */ |
||
1254 | hi2c->XferSize--; |
||
1255 | hi2c->XferCount--; |
||
1256 | } |
||
1257 | /* Two bytes */ |
||
1258 | else if (hi2c->XferSize == 2U) |
||
1259 | { |
||
1260 | /* Wait until BTF flag is set */ |
||
1261 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
1262 | { |
||
1263 | return HAL_ERROR; |
||
1264 | } |
||
1265 | |||
1266 | /* Generate Stop */ |
||
1267 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1268 | |||
1269 | /* Read data from DR */ |
||
1270 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1271 | |||
1272 | /* Increment Buffer pointer */ |
||
1273 | hi2c->pBuffPtr++; |
||
1274 | |||
1275 | /* Update counter */ |
||
1276 | hi2c->XferSize--; |
||
1277 | hi2c->XferCount--; |
||
1278 | |||
1279 | /* Read data from DR */ |
||
1280 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1281 | |||
1282 | /* Increment Buffer pointer */ |
||
1283 | hi2c->pBuffPtr++; |
||
1284 | |||
1285 | /* Update counter */ |
||
1286 | hi2c->XferSize--; |
||
1287 | hi2c->XferCount--; |
||
1288 | } |
||
1289 | /* 3 Last bytes */ |
||
1290 | else |
||
1291 | { |
||
1292 | /* Wait until BTF flag is set */ |
||
1293 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
1294 | { |
||
1295 | return HAL_ERROR; |
||
1296 | } |
||
1297 | |||
1298 | /* Disable Acknowledge */ |
||
1299 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1300 | |||
1301 | /* Read data from DR */ |
||
1302 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1303 | |||
1304 | /* Increment Buffer pointer */ |
||
1305 | hi2c->pBuffPtr++; |
||
1306 | |||
1307 | /* Update counter */ |
||
1308 | hi2c->XferSize--; |
||
1309 | hi2c->XferCount--; |
||
1310 | |||
1311 | /* Wait until BTF flag is set */ |
||
1312 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
1313 | { |
||
1314 | return HAL_ERROR; |
||
1315 | } |
||
1316 | |||
1317 | /* Generate Stop */ |
||
1318 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
1319 | |||
1320 | /* Read data from DR */ |
||
1321 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1322 | |||
1323 | /* Increment Buffer pointer */ |
||
1324 | hi2c->pBuffPtr++; |
||
1325 | |||
1326 | /* Update counter */ |
||
1327 | hi2c->XferSize--; |
||
1328 | hi2c->XferCount--; |
||
1329 | |||
1330 | /* Read data from DR */ |
||
1331 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1332 | |||
1333 | /* Increment Buffer pointer */ |
||
1334 | hi2c->pBuffPtr++; |
||
1335 | |||
1336 | /* Update counter */ |
||
1337 | hi2c->XferSize--; |
||
1338 | hi2c->XferCount--; |
||
1339 | } |
||
1340 | } |
||
1341 | else |
||
1342 | { |
||
1343 | /* Wait until RXNE flag is set */ |
||
1344 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1345 | { |
||
1346 | return HAL_ERROR; |
||
1347 | } |
||
1348 | |||
1349 | /* Read data from DR */ |
||
1350 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1351 | |||
1352 | /* Increment Buffer pointer */ |
||
1353 | hi2c->pBuffPtr++; |
||
1354 | |||
1355 | /* Update counter */ |
||
1356 | hi2c->XferSize--; |
||
1357 | hi2c->XferCount--; |
||
1358 | |||
1359 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
||
1360 | { |
||
1361 | /* Read data from DR */ |
||
1362 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1363 | |||
1364 | /* Increment Buffer pointer */ |
||
1365 | hi2c->pBuffPtr++; |
||
1366 | |||
1367 | /* Update counter */ |
||
1368 | hi2c->XferSize--; |
||
1369 | hi2c->XferCount--; |
||
1370 | } |
||
1371 | } |
||
1372 | } |
||
1373 | |||
1374 | hi2c->State = HAL_I2C_STATE_READY; |
||
1375 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1376 | |||
1377 | /* Process Unlocked */ |
||
1378 | __HAL_UNLOCK(hi2c); |
||
1379 | |||
1380 | return HAL_OK; |
||
1381 | } |
||
1382 | else |
||
1383 | { |
||
1384 | return HAL_BUSY; |
||
1385 | } |
||
1386 | } |
||
1387 | |||
1388 | /** |
||
1389 | * @brief Transmits in slave mode an amount of data in blocking mode. |
||
1390 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1391 | * the configuration information for the specified I2C. |
||
1392 | * @param pData Pointer to data buffer |
||
1393 | * @param Size Amount of data to be sent |
||
1394 | * @param Timeout Timeout duration |
||
1395 | * @retval HAL status |
||
1396 | */ |
||
1397 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
1398 | { |
||
1399 | /* Init tickstart for timeout management*/ |
||
1400 | uint32_t tickstart = HAL_GetTick(); |
||
1401 | |||
1402 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1403 | { |
||
1404 | if ((pData == NULL) || (Size == 0U)) |
||
1405 | { |
||
1406 | return HAL_ERROR; |
||
1407 | } |
||
1408 | |||
1409 | /* Process Locked */ |
||
1410 | __HAL_LOCK(hi2c); |
||
1411 | |||
1412 | /* Check if the I2C is already enabled */ |
||
1413 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1414 | { |
||
1415 | /* Enable I2C peripheral */ |
||
1416 | __HAL_I2C_ENABLE(hi2c); |
||
1417 | } |
||
1418 | |||
1419 | /* Disable Pos */ |
||
1420 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1421 | |||
1422 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
1423 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
1424 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1425 | |||
1426 | /* Prepare transfer parameters */ |
||
1427 | hi2c->pBuffPtr = pData; |
||
1428 | hi2c->XferCount = Size; |
||
1429 | hi2c->XferSize = hi2c->XferCount; |
||
1430 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1431 | |||
1432 | /* Enable Address Acknowledge */ |
||
1433 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1434 | |||
1435 | /* Wait until ADDR flag is set */ |
||
1436 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
||
1437 | { |
||
1438 | return HAL_ERROR; |
||
1439 | } |
||
1440 | |||
1441 | /* Clear ADDR flag */ |
||
1442 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1443 | |||
1444 | /* If 10bit addressing mode is selected */ |
||
1445 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) |
||
1446 | { |
||
1447 | /* Wait until ADDR flag is set */ |
||
1448 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
||
1449 | { |
||
1450 | return HAL_ERROR; |
||
1451 | } |
||
1452 | |||
1453 | /* Clear ADDR flag */ |
||
1454 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1455 | } |
||
1456 | |||
1457 | while (hi2c->XferSize > 0U) |
||
1458 | { |
||
1459 | /* Wait until TXE flag is set */ |
||
1460 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1461 | { |
||
1462 | /* Disable Address Acknowledge */ |
||
1463 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1464 | |||
1465 | return HAL_ERROR; |
||
1466 | } |
||
1467 | |||
1468 | /* Write data to DR */ |
||
1469 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
1470 | |||
1471 | /* Increment Buffer pointer */ |
||
1472 | hi2c->pBuffPtr++; |
||
1473 | |||
1474 | /* Update counter */ |
||
1475 | hi2c->XferCount--; |
||
1476 | hi2c->XferSize--; |
||
1477 | |||
1478 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
1479 | { |
||
1480 | /* Write data to DR */ |
||
1481 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
1482 | |||
1483 | /* Increment Buffer pointer */ |
||
1484 | hi2c->pBuffPtr++; |
||
1485 | |||
1486 | /* Update counter */ |
||
1487 | hi2c->XferCount--; |
||
1488 | hi2c->XferSize--; |
||
1489 | } |
||
1490 | } |
||
1491 | |||
1492 | /* Wait until AF flag is set */ |
||
1493 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) |
||
1494 | { |
||
1495 | return HAL_ERROR; |
||
1496 | } |
||
1497 | |||
1498 | /* Clear AF flag */ |
||
1499 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
1500 | |||
1501 | /* Disable Address Acknowledge */ |
||
1502 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1503 | |||
1504 | hi2c->State = HAL_I2C_STATE_READY; |
||
1505 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1506 | |||
1507 | /* Process Unlocked */ |
||
1508 | __HAL_UNLOCK(hi2c); |
||
1509 | |||
1510 | return HAL_OK; |
||
1511 | } |
||
1512 | else |
||
1513 | { |
||
1514 | return HAL_BUSY; |
||
1515 | } |
||
1516 | } |
||
1517 | |||
1518 | /** |
||
1519 | * @brief Receive in slave mode an amount of data in blocking mode |
||
1520 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1521 | * the configuration information for the specified I2C. |
||
1522 | * @param pData Pointer to data buffer |
||
1523 | * @param Size Amount of data to be sent |
||
1524 | * @param Timeout Timeout duration |
||
1525 | * @retval HAL status |
||
1526 | */ |
||
1527 | HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
1528 | { |
||
1529 | /* Init tickstart for timeout management*/ |
||
1530 | uint32_t tickstart = HAL_GetTick(); |
||
1531 | |||
1532 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1533 | { |
||
1534 | if ((pData == NULL) || (Size == (uint16_t)0)) |
||
1535 | { |
||
1536 | return HAL_ERROR; |
||
1537 | } |
||
1538 | |||
1539 | /* Process Locked */ |
||
1540 | __HAL_LOCK(hi2c); |
||
1541 | |||
1542 | /* Check if the I2C is already enabled */ |
||
1543 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1544 | { |
||
1545 | /* Enable I2C peripheral */ |
||
1546 | __HAL_I2C_ENABLE(hi2c); |
||
1547 | } |
||
1548 | |||
1549 | /* Disable Pos */ |
||
1550 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1551 | |||
1552 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
1553 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
1554 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1555 | |||
1556 | /* Prepare transfer parameters */ |
||
1557 | hi2c->pBuffPtr = pData; |
||
1558 | hi2c->XferCount = Size; |
||
1559 | hi2c->XferSize = hi2c->XferCount; |
||
1560 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1561 | |||
1562 | /* Enable Address Acknowledge */ |
||
1563 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1564 | |||
1565 | /* Wait until ADDR flag is set */ |
||
1566 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
||
1567 | { |
||
1568 | return HAL_ERROR; |
||
1569 | } |
||
1570 | |||
1571 | /* Clear ADDR flag */ |
||
1572 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
1573 | |||
1574 | while (hi2c->XferSize > 0U) |
||
1575 | { |
||
1576 | /* Wait until RXNE flag is set */ |
||
1577 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1578 | { |
||
1579 | /* Disable Address Acknowledge */ |
||
1580 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1581 | |||
1582 | return HAL_ERROR; |
||
1583 | } |
||
1584 | |||
1585 | /* Read data from DR */ |
||
1586 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1587 | |||
1588 | /* Increment Buffer pointer */ |
||
1589 | hi2c->pBuffPtr++; |
||
1590 | |||
1591 | /* Update counter */ |
||
1592 | hi2c->XferSize--; |
||
1593 | hi2c->XferCount--; |
||
1594 | |||
1595 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
1596 | { |
||
1597 | /* Read data from DR */ |
||
1598 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
1599 | |||
1600 | /* Increment Buffer pointer */ |
||
1601 | hi2c->pBuffPtr++; |
||
1602 | |||
1603 | /* Update counter */ |
||
1604 | hi2c->XferSize--; |
||
1605 | hi2c->XferCount--; |
||
1606 | } |
||
1607 | } |
||
1608 | |||
1609 | /* Wait until STOP flag is set */ |
||
1610 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
1611 | { |
||
1612 | /* Disable Address Acknowledge */ |
||
1613 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1614 | |||
1615 | return HAL_ERROR; |
||
1616 | } |
||
1617 | |||
1618 | /* Clear STOP flag */ |
||
1619 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
||
1620 | |||
1621 | /* Disable Address Acknowledge */ |
||
1622 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1623 | |||
1624 | hi2c->State = HAL_I2C_STATE_READY; |
||
1625 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1626 | |||
1627 | /* Process Unlocked */ |
||
1628 | __HAL_UNLOCK(hi2c); |
||
1629 | |||
1630 | return HAL_OK; |
||
1631 | } |
||
1632 | else |
||
1633 | { |
||
1634 | return HAL_BUSY; |
||
1635 | } |
||
1636 | } |
||
1637 | |||
1638 | /** |
||
1639 | * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt |
||
1640 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1641 | * the configuration information for the specified I2C. |
||
1642 | * @param DevAddress Target device address: The device 7 bits address value |
||
1643 | * in datasheet must be shifted to the left before calling the interface |
||
1644 | * @param pData Pointer to data buffer |
||
1645 | * @param Size Amount of data to be sent |
||
1646 | * @retval HAL status |
||
1647 | */ |
||
1648 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
1649 | { |
||
1650 | __IO uint32_t count = 0U; |
||
1651 | |||
1652 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1653 | { |
||
1654 | /* Wait until BUSY flag is reset */ |
||
1655 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
1656 | do |
||
1657 | { |
||
1658 | count--; |
||
1659 | if (count == 0U) |
||
1660 | { |
||
1661 | hi2c->PreviousState = I2C_STATE_NONE; |
||
1662 | hi2c->State = HAL_I2C_STATE_READY; |
||
1663 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1664 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
1665 | |||
1666 | /* Process Unlocked */ |
||
1667 | __HAL_UNLOCK(hi2c); |
||
1668 | |||
1669 | return HAL_ERROR; |
||
1670 | } |
||
1671 | } |
||
1672 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
1673 | |||
1674 | /* Process Locked */ |
||
1675 | __HAL_LOCK(hi2c); |
||
1676 | |||
1677 | /* Check if the I2C is already enabled */ |
||
1678 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1679 | { |
||
1680 | /* Enable I2C peripheral */ |
||
1681 | __HAL_I2C_ENABLE(hi2c); |
||
1682 | } |
||
1683 | |||
1684 | /* Disable Pos */ |
||
1685 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1686 | |||
1687 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
1688 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
1689 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1690 | |||
1691 | /* Prepare transfer parameters */ |
||
1692 | hi2c->pBuffPtr = pData; |
||
1693 | hi2c->XferCount = Size; |
||
1694 | hi2c->XferSize = hi2c->XferCount; |
||
1695 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1696 | hi2c->Devaddress = DevAddress; |
||
1697 | |||
1698 | /* Generate Start */ |
||
1699 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
1700 | |||
1701 | /* Process Unlocked */ |
||
1702 | __HAL_UNLOCK(hi2c); |
||
1703 | |||
1704 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
1705 | to avoid the risk of I2C interrupt handle execution before current |
||
1706 | process unlock */ |
||
1707 | /* Enable EVT, BUF and ERR interrupt */ |
||
1708 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
1709 | |||
1710 | return HAL_OK; |
||
1711 | } |
||
1712 | else |
||
1713 | { |
||
1714 | return HAL_BUSY; |
||
1715 | } |
||
1716 | } |
||
1717 | |||
1718 | /** |
||
1719 | * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt |
||
1720 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1721 | * the configuration information for the specified I2C. |
||
1722 | * @param DevAddress Target device address: The device 7 bits address value |
||
1723 | * in datasheet must be shifted to the left before calling the interface |
||
1724 | * @param pData Pointer to data buffer |
||
1725 | * @param Size Amount of data to be sent |
||
1726 | * @retval HAL status |
||
1727 | */ |
||
1728 | HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
1729 | { |
||
1730 | __IO uint32_t count = 0U; |
||
1731 | |||
1732 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1733 | { |
||
1734 | /* Wait until BUSY flag is reset */ |
||
1735 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
1736 | do |
||
1737 | { |
||
1738 | count--; |
||
1739 | if (count == 0U) |
||
1740 | { |
||
1741 | hi2c->PreviousState = I2C_STATE_NONE; |
||
1742 | hi2c->State = HAL_I2C_STATE_READY; |
||
1743 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1744 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
1745 | |||
1746 | /* Process Unlocked */ |
||
1747 | __HAL_UNLOCK(hi2c); |
||
1748 | |||
1749 | return HAL_ERROR; |
||
1750 | } |
||
1751 | } |
||
1752 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
1753 | |||
1754 | /* Process Locked */ |
||
1755 | __HAL_LOCK(hi2c); |
||
1756 | |||
1757 | /* Check if the I2C is already enabled */ |
||
1758 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1759 | { |
||
1760 | /* Enable I2C peripheral */ |
||
1761 | __HAL_I2C_ENABLE(hi2c); |
||
1762 | } |
||
1763 | |||
1764 | /* Disable Pos */ |
||
1765 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1766 | |||
1767 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
1768 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
1769 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1770 | |||
1771 | /* Prepare transfer parameters */ |
||
1772 | hi2c->pBuffPtr = pData; |
||
1773 | hi2c->XferCount = Size; |
||
1774 | hi2c->XferSize = hi2c->XferCount; |
||
1775 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1776 | hi2c->Devaddress = DevAddress; |
||
1777 | |||
1778 | /* Enable Acknowledge */ |
||
1779 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1780 | |||
1781 | /* Generate Start */ |
||
1782 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
1783 | |||
1784 | /* Process Unlocked */ |
||
1785 | __HAL_UNLOCK(hi2c); |
||
1786 | |||
1787 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
1788 | to avoid the risk of I2C interrupt handle execution before current |
||
1789 | process unlock */ |
||
1790 | |||
1791 | /* Enable EVT, BUF and ERR interrupt */ |
||
1792 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
1793 | |||
1794 | return HAL_OK; |
||
1795 | } |
||
1796 | else |
||
1797 | { |
||
1798 | return HAL_BUSY; |
||
1799 | } |
||
1800 | } |
||
1801 | |||
1802 | /** |
||
1803 | * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt |
||
1804 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1805 | * the configuration information for the specified I2C. |
||
1806 | * @param pData Pointer to data buffer |
||
1807 | * @param Size Amount of data to be sent |
||
1808 | * @retval HAL status |
||
1809 | */ |
||
1810 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
1811 | { |
||
1812 | |||
1813 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1814 | { |
||
1815 | if ((pData == NULL) || (Size == 0U)) |
||
1816 | { |
||
1817 | return HAL_ERROR; |
||
1818 | } |
||
1819 | |||
1820 | /* Process Locked */ |
||
1821 | __HAL_LOCK(hi2c); |
||
1822 | |||
1823 | /* Check if the I2C is already enabled */ |
||
1824 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1825 | { |
||
1826 | /* Enable I2C peripheral */ |
||
1827 | __HAL_I2C_ENABLE(hi2c); |
||
1828 | } |
||
1829 | |||
1830 | /* Disable Pos */ |
||
1831 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1832 | |||
1833 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
1834 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
1835 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1836 | |||
1837 | /* Prepare transfer parameters */ |
||
1838 | hi2c->pBuffPtr = pData; |
||
1839 | hi2c->XferCount = Size; |
||
1840 | hi2c->XferSize = hi2c->XferCount; |
||
1841 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1842 | |||
1843 | /* Enable Address Acknowledge */ |
||
1844 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1845 | |||
1846 | /* Process Unlocked */ |
||
1847 | __HAL_UNLOCK(hi2c); |
||
1848 | |||
1849 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
1850 | to avoid the risk of I2C interrupt handle execution before current |
||
1851 | process unlock */ |
||
1852 | |||
1853 | /* Enable EVT, BUF and ERR interrupt */ |
||
1854 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
1855 | |||
1856 | return HAL_OK; |
||
1857 | } |
||
1858 | else |
||
1859 | { |
||
1860 | return HAL_BUSY; |
||
1861 | } |
||
1862 | } |
||
1863 | |||
1864 | /** |
||
1865 | * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt |
||
1866 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1867 | * the configuration information for the specified I2C. |
||
1868 | * @param pData Pointer to data buffer |
||
1869 | * @param Size Amount of data to be sent |
||
1870 | * @retval HAL status |
||
1871 | */ |
||
1872 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
1873 | { |
||
1874 | |||
1875 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1876 | { |
||
1877 | if ((pData == NULL) || (Size == 0U)) |
||
1878 | { |
||
1879 | return HAL_ERROR; |
||
1880 | } |
||
1881 | |||
1882 | /* Process Locked */ |
||
1883 | __HAL_LOCK(hi2c); |
||
1884 | |||
1885 | /* Check if the I2C is already enabled */ |
||
1886 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1887 | { |
||
1888 | /* Enable I2C peripheral */ |
||
1889 | __HAL_I2C_ENABLE(hi2c); |
||
1890 | } |
||
1891 | |||
1892 | /* Disable Pos */ |
||
1893 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1894 | |||
1895 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
1896 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
1897 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1898 | |||
1899 | /* Prepare transfer parameters */ |
||
1900 | hi2c->pBuffPtr = pData; |
||
1901 | hi2c->XferCount = Size; |
||
1902 | hi2c->XferSize = hi2c->XferCount; |
||
1903 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1904 | |||
1905 | /* Enable Address Acknowledge */ |
||
1906 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
1907 | |||
1908 | /* Process Unlocked */ |
||
1909 | __HAL_UNLOCK(hi2c); |
||
1910 | |||
1911 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
1912 | to avoid the risk of I2C interrupt handle execution before current |
||
1913 | process unlock */ |
||
1914 | |||
1915 | /* Enable EVT, BUF and ERR interrupt */ |
||
1916 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
1917 | |||
1918 | return HAL_OK; |
||
1919 | } |
||
1920 | else |
||
1921 | { |
||
1922 | return HAL_BUSY; |
||
1923 | } |
||
1924 | } |
||
1925 | |||
1926 | /** |
||
1927 | * @brief Transmit in master mode an amount of data in non-blocking mode with DMA |
||
1928 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
1929 | * the configuration information for the specified I2C. |
||
1930 | * @param DevAddress Target device address: The device 7 bits address value |
||
1931 | * in datasheet must be shifted to the left before calling the interface |
||
1932 | * @param pData Pointer to data buffer |
||
1933 | * @param Size Amount of data to be sent |
||
1934 | * @retval HAL status |
||
1935 | */ |
||
1936 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
1937 | { |
||
1938 | __IO uint32_t count = 0U; |
||
1939 | HAL_StatusTypeDef dmaxferstatus; |
||
1940 | |||
1941 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
1942 | { |
||
1943 | /* Wait until BUSY flag is reset */ |
||
1944 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
1945 | do |
||
1946 | { |
||
1947 | count--; |
||
1948 | if (count == 0U) |
||
1949 | { |
||
1950 | hi2c->PreviousState = I2C_STATE_NONE; |
||
1951 | hi2c->State = HAL_I2C_STATE_READY; |
||
1952 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
1953 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
1954 | |||
1955 | /* Process Unlocked */ |
||
1956 | __HAL_UNLOCK(hi2c); |
||
1957 | |||
1958 | return HAL_ERROR; |
||
1959 | } |
||
1960 | } |
||
1961 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
1962 | |||
1963 | /* Process Locked */ |
||
1964 | __HAL_LOCK(hi2c); |
||
1965 | |||
1966 | /* Check if the I2C is already enabled */ |
||
1967 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
1968 | { |
||
1969 | /* Enable I2C peripheral */ |
||
1970 | __HAL_I2C_ENABLE(hi2c); |
||
1971 | } |
||
1972 | |||
1973 | /* Disable Pos */ |
||
1974 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
1975 | |||
1976 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
1977 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
1978 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
1979 | |||
1980 | /* Prepare transfer parameters */ |
||
1981 | hi2c->pBuffPtr = pData; |
||
1982 | hi2c->XferCount = Size; |
||
1983 | hi2c->XferSize = hi2c->XferCount; |
||
1984 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
1985 | hi2c->Devaddress = DevAddress; |
||
1986 | |||
1987 | if (hi2c->XferSize > 0U) |
||
1988 | { |
||
1989 | /* Set the I2C DMA transfer complete callback */ |
||
1990 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
1991 | |||
1992 | /* Set the DMA error callback */ |
||
1993 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
1994 | |||
1995 | /* Set the unused DMA callbacks to NULL */ |
||
1996 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
1997 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
1998 | |||
1999 | /* Enable the DMA channel */ |
||
2000 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
2001 | |||
2002 | if (dmaxferstatus == HAL_OK) |
||
2003 | { |
||
2004 | /* Enable Acknowledge */ |
||
2005 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2006 | |||
2007 | /* Generate Start */ |
||
2008 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2009 | |||
2010 | /* Process Unlocked */ |
||
2011 | __HAL_UNLOCK(hi2c); |
||
2012 | |||
2013 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2014 | to avoid the risk of I2C interrupt handle execution before current |
||
2015 | process unlock */ |
||
2016 | |||
2017 | /* Enable EVT and ERR interrupt */ |
||
2018 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
2019 | |||
2020 | /* Enable DMA Request */ |
||
2021 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
2022 | } |
||
2023 | else |
||
2024 | { |
||
2025 | /* Update I2C state */ |
||
2026 | hi2c->State = HAL_I2C_STATE_READY; |
||
2027 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2028 | |||
2029 | /* Update I2C error code */ |
||
2030 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
2031 | |||
2032 | /* Process Unlocked */ |
||
2033 | __HAL_UNLOCK(hi2c); |
||
2034 | |||
2035 | return HAL_ERROR; |
||
2036 | } |
||
2037 | } |
||
2038 | else |
||
2039 | { |
||
2040 | /* Enable Acknowledge */ |
||
2041 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2042 | |||
2043 | /* Generate Start */ |
||
2044 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2045 | |||
2046 | /* Process Unlocked */ |
||
2047 | __HAL_UNLOCK(hi2c); |
||
2048 | |||
2049 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2050 | to avoid the risk of I2C interrupt handle execution before current |
||
2051 | process unlock */ |
||
2052 | |||
2053 | /* Enable EVT, BUF and ERR interrupt */ |
||
2054 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
2055 | } |
||
2056 | |||
2057 | return HAL_OK; |
||
2058 | } |
||
2059 | else |
||
2060 | { |
||
2061 | return HAL_BUSY; |
||
2062 | } |
||
2063 | } |
||
2064 | |||
2065 | /** |
||
2066 | * @brief Receive in master mode an amount of data in non-blocking mode with DMA |
||
2067 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2068 | * the configuration information for the specified I2C. |
||
2069 | * @param DevAddress Target device address: The device 7 bits address value |
||
2070 | * in datasheet must be shifted to the left before calling the interface |
||
2071 | * @param pData Pointer to data buffer |
||
2072 | * @param Size Amount of data to be sent |
||
2073 | * @retval HAL status |
||
2074 | */ |
||
2075 | HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
||
2076 | { |
||
2077 | __IO uint32_t count = 0U; |
||
2078 | HAL_StatusTypeDef dmaxferstatus; |
||
2079 | |||
2080 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2081 | { |
||
2082 | /* Wait until BUSY flag is reset */ |
||
2083 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
2084 | do |
||
2085 | { |
||
2086 | count--; |
||
2087 | if (count == 0U) |
||
2088 | { |
||
2089 | hi2c->PreviousState = I2C_STATE_NONE; |
||
2090 | hi2c->State = HAL_I2C_STATE_READY; |
||
2091 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2092 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
2093 | |||
2094 | /* Process Unlocked */ |
||
2095 | __HAL_UNLOCK(hi2c); |
||
2096 | |||
2097 | return HAL_ERROR; |
||
2098 | } |
||
2099 | } |
||
2100 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
2101 | |||
2102 | /* Process Locked */ |
||
2103 | __HAL_LOCK(hi2c); |
||
2104 | |||
2105 | /* Check if the I2C is already enabled */ |
||
2106 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2107 | { |
||
2108 | /* Enable I2C peripheral */ |
||
2109 | __HAL_I2C_ENABLE(hi2c); |
||
2110 | } |
||
2111 | |||
2112 | /* Disable Pos */ |
||
2113 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2114 | |||
2115 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
2116 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
2117 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2118 | |||
2119 | /* Prepare transfer parameters */ |
||
2120 | hi2c->pBuffPtr = pData; |
||
2121 | hi2c->XferCount = Size; |
||
2122 | hi2c->XferSize = hi2c->XferCount; |
||
2123 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2124 | hi2c->Devaddress = DevAddress; |
||
2125 | |||
2126 | if (hi2c->XferSize > 0U) |
||
2127 | { |
||
2128 | /* Set the I2C DMA transfer complete callback */ |
||
2129 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
2130 | |||
2131 | /* Set the DMA error callback */ |
||
2132 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
2133 | |||
2134 | /* Set the unused DMA callbacks to NULL */ |
||
2135 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
2136 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
2137 | |||
2138 | /* Enable the DMA channel */ |
||
2139 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
2140 | |||
2141 | if (dmaxferstatus == HAL_OK) |
||
2142 | { |
||
2143 | /* Enable Acknowledge */ |
||
2144 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2145 | |||
2146 | /* Generate Start */ |
||
2147 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2148 | |||
2149 | /* Process Unlocked */ |
||
2150 | __HAL_UNLOCK(hi2c); |
||
2151 | |||
2152 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2153 | to avoid the risk of I2C interrupt handle execution before current |
||
2154 | process unlock */ |
||
2155 | |||
2156 | /* Enable EVT and ERR interrupt */ |
||
2157 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
2158 | |||
2159 | /* Enable DMA Request */ |
||
2160 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
2161 | } |
||
2162 | else |
||
2163 | { |
||
2164 | /* Update I2C state */ |
||
2165 | hi2c->State = HAL_I2C_STATE_READY; |
||
2166 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2167 | |||
2168 | /* Update I2C error code */ |
||
2169 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
2170 | |||
2171 | /* Process Unlocked */ |
||
2172 | __HAL_UNLOCK(hi2c); |
||
2173 | |||
2174 | return HAL_ERROR; |
||
2175 | } |
||
2176 | } |
||
2177 | else |
||
2178 | { |
||
2179 | /* Enable Acknowledge */ |
||
2180 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2181 | |||
2182 | /* Generate Start */ |
||
2183 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2184 | |||
2185 | /* Process Unlocked */ |
||
2186 | __HAL_UNLOCK(hi2c); |
||
2187 | |||
2188 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2189 | to avoid the risk of I2C interrupt handle execution before current |
||
2190 | process unlock */ |
||
2191 | |||
2192 | /* Enable EVT, BUF and ERR interrupt */ |
||
2193 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
2194 | } |
||
2195 | |||
2196 | return HAL_OK; |
||
2197 | } |
||
2198 | else |
||
2199 | { |
||
2200 | return HAL_BUSY; |
||
2201 | } |
||
2202 | } |
||
2203 | |||
2204 | /** |
||
2205 | * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA |
||
2206 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2207 | * the configuration information for the specified I2C. |
||
2208 | * @param pData Pointer to data buffer |
||
2209 | * @param Size Amount of data to be sent |
||
2210 | * @retval HAL status |
||
2211 | */ |
||
2212 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
2213 | { |
||
2214 | HAL_StatusTypeDef dmaxferstatus; |
||
2215 | |||
2216 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2217 | { |
||
2218 | if ((pData == NULL) || (Size == 0U)) |
||
2219 | { |
||
2220 | return HAL_ERROR; |
||
2221 | } |
||
2222 | |||
2223 | /* Process Locked */ |
||
2224 | __HAL_LOCK(hi2c); |
||
2225 | |||
2226 | /* Check if the I2C is already enabled */ |
||
2227 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2228 | { |
||
2229 | /* Enable I2C peripheral */ |
||
2230 | __HAL_I2C_ENABLE(hi2c); |
||
2231 | } |
||
2232 | |||
2233 | /* Disable Pos */ |
||
2234 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2235 | |||
2236 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
2237 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
2238 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2239 | |||
2240 | /* Prepare transfer parameters */ |
||
2241 | hi2c->pBuffPtr = pData; |
||
2242 | hi2c->XferCount = Size; |
||
2243 | hi2c->XferSize = hi2c->XferCount; |
||
2244 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2245 | |||
2246 | /* Set the I2C DMA transfer complete callback */ |
||
2247 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
2248 | |||
2249 | /* Set the DMA error callback */ |
||
2250 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
2251 | |||
2252 | /* Set the unused DMA callbacks to NULL */ |
||
2253 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
2254 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
2255 | |||
2256 | /* Enable the DMA channel */ |
||
2257 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
2258 | |||
2259 | if (dmaxferstatus == HAL_OK) |
||
2260 | { |
||
2261 | /* Enable Address Acknowledge */ |
||
2262 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2263 | |||
2264 | /* Process Unlocked */ |
||
2265 | __HAL_UNLOCK(hi2c); |
||
2266 | |||
2267 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2268 | to avoid the risk of I2C interrupt handle execution before current |
||
2269 | process unlock */ |
||
2270 | /* Enable EVT and ERR interrupt */ |
||
2271 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
2272 | |||
2273 | /* Enable DMA Request */ |
||
2274 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
2275 | |||
2276 | return HAL_OK; |
||
2277 | } |
||
2278 | else |
||
2279 | { |
||
2280 | /* Update I2C state */ |
||
2281 | hi2c->State = HAL_I2C_STATE_READY; |
||
2282 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2283 | |||
2284 | /* Update I2C error code */ |
||
2285 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
2286 | |||
2287 | /* Process Unlocked */ |
||
2288 | __HAL_UNLOCK(hi2c); |
||
2289 | |||
2290 | return HAL_ERROR; |
||
2291 | } |
||
2292 | } |
||
2293 | else |
||
2294 | { |
||
2295 | return HAL_BUSY; |
||
2296 | } |
||
2297 | } |
||
2298 | |||
2299 | /** |
||
2300 | * @brief Receive in slave mode an amount of data in non-blocking mode with DMA |
||
2301 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2302 | * the configuration information for the specified I2C. |
||
2303 | * @param pData Pointer to data buffer |
||
2304 | * @param Size Amount of data to be sent |
||
2305 | * @retval HAL status |
||
2306 | */ |
||
2307 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
||
2308 | { |
||
2309 | HAL_StatusTypeDef dmaxferstatus; |
||
2310 | |||
2311 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2312 | { |
||
2313 | if ((pData == NULL) || (Size == 0U)) |
||
2314 | { |
||
2315 | return HAL_ERROR; |
||
2316 | } |
||
2317 | |||
2318 | /* Process Locked */ |
||
2319 | __HAL_LOCK(hi2c); |
||
2320 | |||
2321 | /* Check if the I2C is already enabled */ |
||
2322 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2323 | { |
||
2324 | /* Enable I2C peripheral */ |
||
2325 | __HAL_I2C_ENABLE(hi2c); |
||
2326 | } |
||
2327 | |||
2328 | /* Disable Pos */ |
||
2329 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2330 | |||
2331 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
2332 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
2333 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2334 | |||
2335 | /* Prepare transfer parameters */ |
||
2336 | hi2c->pBuffPtr = pData; |
||
2337 | hi2c->XferCount = Size; |
||
2338 | hi2c->XferSize = hi2c->XferCount; |
||
2339 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2340 | |||
2341 | /* Set the I2C DMA transfer complete callback */ |
||
2342 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
2343 | |||
2344 | /* Set the DMA error callback */ |
||
2345 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
2346 | |||
2347 | /* Set the unused DMA callbacks to NULL */ |
||
2348 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
2349 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
2350 | |||
2351 | /* Enable the DMA channel */ |
||
2352 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
2353 | |||
2354 | if (dmaxferstatus == HAL_OK) |
||
2355 | { |
||
2356 | /* Enable Address Acknowledge */ |
||
2357 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2358 | |||
2359 | /* Process Unlocked */ |
||
2360 | __HAL_UNLOCK(hi2c); |
||
2361 | |||
2362 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2363 | to avoid the risk of I2C interrupt handle execution before current |
||
2364 | process unlock */ |
||
2365 | /* Enable EVT and ERR interrupt */ |
||
2366 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
2367 | |||
2368 | /* Enable DMA Request */ |
||
2369 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
2370 | |||
2371 | return HAL_OK; |
||
2372 | } |
||
2373 | else |
||
2374 | { |
||
2375 | /* Update I2C state */ |
||
2376 | hi2c->State = HAL_I2C_STATE_READY; |
||
2377 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2378 | |||
2379 | /* Update I2C error code */ |
||
2380 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
2381 | |||
2382 | /* Process Unlocked */ |
||
2383 | __HAL_UNLOCK(hi2c); |
||
2384 | |||
2385 | return HAL_ERROR; |
||
2386 | } |
||
2387 | } |
||
2388 | else |
||
2389 | { |
||
2390 | return HAL_BUSY; |
||
2391 | } |
||
2392 | } |
||
2393 | |||
2394 | /** |
||
2395 | * @brief Write an amount of data in blocking mode to a specific memory address |
||
2396 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2397 | * the configuration information for the specified I2C. |
||
2398 | * @param DevAddress Target device address: The device 7 bits address value |
||
2399 | * in datasheet must be shifted to the left before calling the interface |
||
2400 | * @param MemAddress Internal memory address |
||
2401 | * @param MemAddSize Size of internal memory address |
||
2402 | * @param pData Pointer to data buffer |
||
2403 | * @param Size Amount of data to be sent |
||
2404 | * @param Timeout Timeout duration |
||
2405 | * @retval HAL status |
||
2406 | */ |
||
2407 | HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
2408 | { |
||
2409 | /* Init tickstart for timeout management*/ |
||
2410 | uint32_t tickstart = HAL_GetTick(); |
||
2411 | |||
2412 | /* Check the parameters */ |
||
2413 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
2414 | |||
2415 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2416 | { |
||
2417 | /* Wait until BUSY flag is reset */ |
||
2418 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
2419 | { |
||
2420 | return HAL_BUSY; |
||
2421 | } |
||
2422 | |||
2423 | /* Process Locked */ |
||
2424 | __HAL_LOCK(hi2c); |
||
2425 | |||
2426 | /* Check if the I2C is already enabled */ |
||
2427 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2428 | { |
||
2429 | /* Enable I2C peripheral */ |
||
2430 | __HAL_I2C_ENABLE(hi2c); |
||
2431 | } |
||
2432 | |||
2433 | /* Disable Pos */ |
||
2434 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2435 | |||
2436 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
2437 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
2438 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2439 | |||
2440 | /* Prepare transfer parameters */ |
||
2441 | hi2c->pBuffPtr = pData; |
||
2442 | hi2c->XferCount = Size; |
||
2443 | hi2c->XferSize = hi2c->XferCount; |
||
2444 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2445 | |||
2446 | /* Send Slave Address and Memory Address */ |
||
2447 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
||
2448 | { |
||
2449 | return HAL_ERROR; |
||
2450 | } |
||
2451 | |||
2452 | while (hi2c->XferSize > 0U) |
||
2453 | { |
||
2454 | /* Wait until TXE flag is set */ |
||
2455 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
2456 | { |
||
2457 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
2458 | { |
||
2459 | /* Generate Stop */ |
||
2460 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2461 | } |
||
2462 | return HAL_ERROR; |
||
2463 | } |
||
2464 | |||
2465 | /* Write data to DR */ |
||
2466 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
2467 | |||
2468 | /* Increment Buffer pointer */ |
||
2469 | hi2c->pBuffPtr++; |
||
2470 | |||
2471 | /* Update counter */ |
||
2472 | hi2c->XferSize--; |
||
2473 | hi2c->XferCount--; |
||
2474 | |||
2475 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
||
2476 | { |
||
2477 | /* Write data to DR */ |
||
2478 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
2479 | |||
2480 | /* Increment Buffer pointer */ |
||
2481 | hi2c->pBuffPtr++; |
||
2482 | |||
2483 | /* Update counter */ |
||
2484 | hi2c->XferSize--; |
||
2485 | hi2c->XferCount--; |
||
2486 | } |
||
2487 | } |
||
2488 | |||
2489 | /* Wait until BTF flag is set */ |
||
2490 | if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
2491 | { |
||
2492 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
2493 | { |
||
2494 | /* Generate Stop */ |
||
2495 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2496 | } |
||
2497 | return HAL_ERROR; |
||
2498 | } |
||
2499 | |||
2500 | /* Generate Stop */ |
||
2501 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2502 | |||
2503 | hi2c->State = HAL_I2C_STATE_READY; |
||
2504 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2505 | |||
2506 | /* Process Unlocked */ |
||
2507 | __HAL_UNLOCK(hi2c); |
||
2508 | |||
2509 | return HAL_OK; |
||
2510 | } |
||
2511 | else |
||
2512 | { |
||
2513 | return HAL_BUSY; |
||
2514 | } |
||
2515 | } |
||
2516 | |||
2517 | /** |
||
2518 | * @brief Read an amount of data in blocking mode from a specific memory address |
||
2519 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2520 | * the configuration information for the specified I2C. |
||
2521 | * @param DevAddress Target device address: The device 7 bits address value |
||
2522 | * in datasheet must be shifted to the left before calling the interface |
||
2523 | * @param MemAddress Internal memory address |
||
2524 | * @param MemAddSize Size of internal memory address |
||
2525 | * @param pData Pointer to data buffer |
||
2526 | * @param Size Amount of data to be sent |
||
2527 | * @param Timeout Timeout duration |
||
2528 | * @retval HAL status |
||
2529 | */ |
||
2530 | HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
||
2531 | { |
||
2532 | /* Init tickstart for timeout management*/ |
||
2533 | uint32_t tickstart = HAL_GetTick(); |
||
2534 | |||
2535 | /* Check the parameters */ |
||
2536 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
2537 | |||
2538 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2539 | { |
||
2540 | /* Wait until BUSY flag is reset */ |
||
2541 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
2542 | { |
||
2543 | return HAL_BUSY; |
||
2544 | } |
||
2545 | |||
2546 | /* Process Locked */ |
||
2547 | __HAL_LOCK(hi2c); |
||
2548 | |||
2549 | /* Check if the I2C is already enabled */ |
||
2550 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2551 | { |
||
2552 | /* Enable I2C peripheral */ |
||
2553 | __HAL_I2C_ENABLE(hi2c); |
||
2554 | } |
||
2555 | |||
2556 | /* Disable Pos */ |
||
2557 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2558 | |||
2559 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
2560 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
2561 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2562 | |||
2563 | /* Prepare transfer parameters */ |
||
2564 | hi2c->pBuffPtr = pData; |
||
2565 | hi2c->XferCount = Size; |
||
2566 | hi2c->XferSize = hi2c->XferCount; |
||
2567 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2568 | |||
2569 | /* Send Slave Address and Memory Address */ |
||
2570 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
||
2571 | { |
||
2572 | return HAL_ERROR; |
||
2573 | } |
||
2574 | |||
2575 | if (hi2c->XferSize == 0U) |
||
2576 | { |
||
2577 | /* Clear ADDR flag */ |
||
2578 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
2579 | |||
2580 | /* Generate Stop */ |
||
2581 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2582 | } |
||
2583 | else if (hi2c->XferSize == 1U) |
||
2584 | { |
||
2585 | /* Disable Acknowledge */ |
||
2586 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2587 | |||
2588 | /* Clear ADDR flag */ |
||
2589 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
2590 | |||
2591 | /* Generate Stop */ |
||
2592 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2593 | } |
||
2594 | else if (hi2c->XferSize == 2U) |
||
2595 | { |
||
2596 | /* Disable Acknowledge */ |
||
2597 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2598 | |||
2599 | /* Enable Pos */ |
||
2600 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2601 | |||
2602 | /* Clear ADDR flag */ |
||
2603 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
2604 | } |
||
2605 | else |
||
2606 | { |
||
2607 | /* Clear ADDR flag */ |
||
2608 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
2609 | } |
||
2610 | |||
2611 | while (hi2c->XferSize > 0U) |
||
2612 | { |
||
2613 | if (hi2c->XferSize <= 3U) |
||
2614 | { |
||
2615 | /* One byte */ |
||
2616 | if (hi2c->XferSize == 1U) |
||
2617 | { |
||
2618 | /* Wait until RXNE flag is set */ |
||
2619 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
2620 | { |
||
2621 | return HAL_ERROR; |
||
2622 | } |
||
2623 | |||
2624 | /* Read data from DR */ |
||
2625 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2626 | |||
2627 | /* Increment Buffer pointer */ |
||
2628 | hi2c->pBuffPtr++; |
||
2629 | |||
2630 | /* Update counter */ |
||
2631 | hi2c->XferSize--; |
||
2632 | hi2c->XferCount--; |
||
2633 | } |
||
2634 | /* Two bytes */ |
||
2635 | else if (hi2c->XferSize == 2U) |
||
2636 | { |
||
2637 | /* Wait until BTF flag is set */ |
||
2638 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
2639 | { |
||
2640 | return HAL_ERROR; |
||
2641 | } |
||
2642 | |||
2643 | /* Generate Stop */ |
||
2644 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2645 | |||
2646 | /* Read data from DR */ |
||
2647 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2648 | |||
2649 | /* Increment Buffer pointer */ |
||
2650 | hi2c->pBuffPtr++; |
||
2651 | |||
2652 | /* Update counter */ |
||
2653 | hi2c->XferSize--; |
||
2654 | hi2c->XferCount--; |
||
2655 | |||
2656 | /* Read data from DR */ |
||
2657 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2658 | |||
2659 | /* Increment Buffer pointer */ |
||
2660 | hi2c->pBuffPtr++; |
||
2661 | |||
2662 | /* Update counter */ |
||
2663 | hi2c->XferSize--; |
||
2664 | hi2c->XferCount--; |
||
2665 | } |
||
2666 | /* 3 Last bytes */ |
||
2667 | else |
||
2668 | { |
||
2669 | /* Wait until BTF flag is set */ |
||
2670 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
2671 | { |
||
2672 | return HAL_ERROR; |
||
2673 | } |
||
2674 | |||
2675 | /* Disable Acknowledge */ |
||
2676 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2677 | |||
2678 | /* Read data from DR */ |
||
2679 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2680 | |||
2681 | /* Increment Buffer pointer */ |
||
2682 | hi2c->pBuffPtr++; |
||
2683 | |||
2684 | /* Update counter */ |
||
2685 | hi2c->XferSize--; |
||
2686 | hi2c->XferCount--; |
||
2687 | |||
2688 | /* Wait until BTF flag is set */ |
||
2689 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
||
2690 | { |
||
2691 | return HAL_ERROR; |
||
2692 | } |
||
2693 | |||
2694 | /* Generate Stop */ |
||
2695 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
2696 | |||
2697 | /* Read data from DR */ |
||
2698 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2699 | |||
2700 | /* Increment Buffer pointer */ |
||
2701 | hi2c->pBuffPtr++; |
||
2702 | |||
2703 | /* Update counter */ |
||
2704 | hi2c->XferSize--; |
||
2705 | hi2c->XferCount--; |
||
2706 | |||
2707 | /* Read data from DR */ |
||
2708 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2709 | |||
2710 | /* Increment Buffer pointer */ |
||
2711 | hi2c->pBuffPtr++; |
||
2712 | |||
2713 | /* Update counter */ |
||
2714 | hi2c->XferSize--; |
||
2715 | hi2c->XferCount--; |
||
2716 | } |
||
2717 | } |
||
2718 | else |
||
2719 | { |
||
2720 | /* Wait until RXNE flag is set */ |
||
2721 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
||
2722 | { |
||
2723 | return HAL_ERROR; |
||
2724 | } |
||
2725 | |||
2726 | /* Read data from DR */ |
||
2727 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2728 | |||
2729 | /* Increment Buffer pointer */ |
||
2730 | hi2c->pBuffPtr++; |
||
2731 | |||
2732 | /* Update counter */ |
||
2733 | hi2c->XferSize--; |
||
2734 | hi2c->XferCount--; |
||
2735 | |||
2736 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
||
2737 | { |
||
2738 | /* Read data from DR */ |
||
2739 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
2740 | |||
2741 | /* Increment Buffer pointer */ |
||
2742 | hi2c->pBuffPtr++; |
||
2743 | |||
2744 | /* Update counter */ |
||
2745 | hi2c->XferSize--; |
||
2746 | hi2c->XferCount--; |
||
2747 | } |
||
2748 | } |
||
2749 | } |
||
2750 | |||
2751 | hi2c->State = HAL_I2C_STATE_READY; |
||
2752 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2753 | |||
2754 | /* Process Unlocked */ |
||
2755 | __HAL_UNLOCK(hi2c); |
||
2756 | |||
2757 | return HAL_OK; |
||
2758 | } |
||
2759 | else |
||
2760 | { |
||
2761 | return HAL_BUSY; |
||
2762 | } |
||
2763 | } |
||
2764 | |||
2765 | /** |
||
2766 | * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address |
||
2767 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2768 | * the configuration information for the specified I2C. |
||
2769 | * @param DevAddress Target device address: The device 7 bits address value |
||
2770 | * in datasheet must be shifted to the left before calling the interface |
||
2771 | * @param MemAddress Internal memory address |
||
2772 | * @param MemAddSize Size of internal memory address |
||
2773 | * @param pData Pointer to data buffer |
||
2774 | * @param Size Amount of data to be sent |
||
2775 | * @retval HAL status |
||
2776 | */ |
||
2777 | HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
2778 | { |
||
2779 | __IO uint32_t count = 0U; |
||
2780 | |||
2781 | /* Check the parameters */ |
||
2782 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
2783 | |||
2784 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2785 | { |
||
2786 | /* Wait until BUSY flag is reset */ |
||
2787 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
2788 | do |
||
2789 | { |
||
2790 | count--; |
||
2791 | if (count == 0U) |
||
2792 | { |
||
2793 | hi2c->PreviousState = I2C_STATE_NONE; |
||
2794 | hi2c->State = HAL_I2C_STATE_READY; |
||
2795 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2796 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
2797 | |||
2798 | /* Process Unlocked */ |
||
2799 | __HAL_UNLOCK(hi2c); |
||
2800 | |||
2801 | return HAL_ERROR; |
||
2802 | } |
||
2803 | } |
||
2804 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
2805 | |||
2806 | /* Process Locked */ |
||
2807 | __HAL_LOCK(hi2c); |
||
2808 | |||
2809 | /* Check if the I2C is already enabled */ |
||
2810 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2811 | { |
||
2812 | /* Enable I2C peripheral */ |
||
2813 | __HAL_I2C_ENABLE(hi2c); |
||
2814 | } |
||
2815 | |||
2816 | /* Disable Pos */ |
||
2817 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2818 | |||
2819 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
2820 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
2821 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2822 | |||
2823 | /* Prepare transfer parameters */ |
||
2824 | hi2c->pBuffPtr = pData; |
||
2825 | hi2c->XferCount = Size; |
||
2826 | hi2c->XferSize = hi2c->XferCount; |
||
2827 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2828 | hi2c->Devaddress = DevAddress; |
||
2829 | hi2c->Memaddress = MemAddress; |
||
2830 | hi2c->MemaddSize = MemAddSize; |
||
2831 | hi2c->EventCount = 0U; |
||
2832 | |||
2833 | /* Generate Start */ |
||
2834 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2835 | |||
2836 | /* Process Unlocked */ |
||
2837 | __HAL_UNLOCK(hi2c); |
||
2838 | |||
2839 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2840 | to avoid the risk of I2C interrupt handle execution before current |
||
2841 | process unlock */ |
||
2842 | |||
2843 | /* Enable EVT, BUF and ERR interrupt */ |
||
2844 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
2845 | |||
2846 | return HAL_OK; |
||
2847 | } |
||
2848 | else |
||
2849 | { |
||
2850 | return HAL_BUSY; |
||
2851 | } |
||
2852 | } |
||
2853 | |||
2854 | /** |
||
2855 | * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address |
||
2856 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2857 | * the configuration information for the specified I2C. |
||
2858 | * @param DevAddress Target device address |
||
2859 | * @param MemAddress Internal memory address |
||
2860 | * @param MemAddSize Size of internal memory address |
||
2861 | * @param pData Pointer to data buffer |
||
2862 | * @param Size Amount of data to be sent |
||
2863 | * @retval HAL status |
||
2864 | */ |
||
2865 | HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
2866 | { |
||
2867 | __IO uint32_t count = 0U; |
||
2868 | |||
2869 | /* Check the parameters */ |
||
2870 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
2871 | |||
2872 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2873 | { |
||
2874 | /* Wait until BUSY flag is reset */ |
||
2875 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
2876 | do |
||
2877 | { |
||
2878 | count--; |
||
2879 | if (count == 0U) |
||
2880 | { |
||
2881 | hi2c->PreviousState = I2C_STATE_NONE; |
||
2882 | hi2c->State = HAL_I2C_STATE_READY; |
||
2883 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2884 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
2885 | |||
2886 | /* Process Unlocked */ |
||
2887 | __HAL_UNLOCK(hi2c); |
||
2888 | |||
2889 | return HAL_ERROR; |
||
2890 | } |
||
2891 | } |
||
2892 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
2893 | |||
2894 | /* Process Locked */ |
||
2895 | __HAL_LOCK(hi2c); |
||
2896 | |||
2897 | /* Check if the I2C is already enabled */ |
||
2898 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2899 | { |
||
2900 | /* Enable I2C peripheral */ |
||
2901 | __HAL_I2C_ENABLE(hi2c); |
||
2902 | } |
||
2903 | |||
2904 | /* Disable Pos */ |
||
2905 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
2906 | |||
2907 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
2908 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
2909 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
2910 | |||
2911 | /* Prepare transfer parameters */ |
||
2912 | hi2c->pBuffPtr = pData; |
||
2913 | hi2c->XferCount = Size; |
||
2914 | hi2c->XferSize = hi2c->XferCount; |
||
2915 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
2916 | hi2c->Devaddress = DevAddress; |
||
2917 | hi2c->Memaddress = MemAddress; |
||
2918 | hi2c->MemaddSize = MemAddSize; |
||
2919 | hi2c->EventCount = 0U; |
||
2920 | |||
2921 | /* Enable Acknowledge */ |
||
2922 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
2923 | |||
2924 | /* Generate Start */ |
||
2925 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
2926 | |||
2927 | /* Process Unlocked */ |
||
2928 | __HAL_UNLOCK(hi2c); |
||
2929 | |||
2930 | if (hi2c->XferSize > 0U) |
||
2931 | { |
||
2932 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
2933 | to avoid the risk of I2C interrupt handle execution before current |
||
2934 | process unlock */ |
||
2935 | |||
2936 | /* Enable EVT, BUF and ERR interrupt */ |
||
2937 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
2938 | } |
||
2939 | return HAL_OK; |
||
2940 | } |
||
2941 | else |
||
2942 | { |
||
2943 | return HAL_BUSY; |
||
2944 | } |
||
2945 | } |
||
2946 | |||
2947 | /** |
||
2948 | * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address |
||
2949 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
2950 | * the configuration information for the specified I2C. |
||
2951 | * @param DevAddress Target device address: The device 7 bits address value |
||
2952 | * in datasheet must be shifted to the left before calling the interface |
||
2953 | * @param MemAddress Internal memory address |
||
2954 | * @param MemAddSize Size of internal memory address |
||
2955 | * @param pData Pointer to data buffer |
||
2956 | * @param Size Amount of data to be sent |
||
2957 | * @retval HAL status |
||
2958 | */ |
||
2959 | HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
2960 | { |
||
2961 | __IO uint32_t count = 0U; |
||
2962 | HAL_StatusTypeDef dmaxferstatus; |
||
2963 | |||
2964 | /* Init tickstart for timeout management*/ |
||
2965 | uint32_t tickstart = HAL_GetTick(); |
||
2966 | |||
2967 | /* Check the parameters */ |
||
2968 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
2969 | |||
2970 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
2971 | { |
||
2972 | /* Wait until BUSY flag is reset */ |
||
2973 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
2974 | do |
||
2975 | { |
||
2976 | count--; |
||
2977 | if (count == 0U) |
||
2978 | { |
||
2979 | hi2c->PreviousState = I2C_STATE_NONE; |
||
2980 | hi2c->State = HAL_I2C_STATE_READY; |
||
2981 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
2982 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
2983 | |||
2984 | /* Process Unlocked */ |
||
2985 | __HAL_UNLOCK(hi2c); |
||
2986 | |||
2987 | return HAL_ERROR; |
||
2988 | } |
||
2989 | } |
||
2990 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
2991 | |||
2992 | /* Process Locked */ |
||
2993 | __HAL_LOCK(hi2c); |
||
2994 | |||
2995 | /* Check if the I2C is already enabled */ |
||
2996 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
2997 | { |
||
2998 | /* Enable I2C peripheral */ |
||
2999 | __HAL_I2C_ENABLE(hi2c); |
||
3000 | } |
||
3001 | |||
3002 | /* Disable Pos */ |
||
3003 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3004 | |||
3005 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
3006 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
3007 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3008 | |||
3009 | /* Prepare transfer parameters */ |
||
3010 | hi2c->pBuffPtr = pData; |
||
3011 | hi2c->XferCount = Size; |
||
3012 | hi2c->XferSize = hi2c->XferCount; |
||
3013 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
3014 | |||
3015 | if (hi2c->XferSize > 0U) |
||
3016 | { |
||
3017 | /* Set the I2C DMA transfer complete callback */ |
||
3018 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
3019 | |||
3020 | /* Set the DMA error callback */ |
||
3021 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
3022 | |||
3023 | /* Set the unused DMA callbacks to NULL */ |
||
3024 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
3025 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
3026 | |||
3027 | /* Enable the DMA channel */ |
||
3028 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
3029 | |||
3030 | if (dmaxferstatus == HAL_OK) |
||
3031 | { |
||
3032 | /* Send Slave Address and Memory Address */ |
||
3033 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
||
3034 | { |
||
3035 | /* Abort the ongoing DMA */ |
||
3036 | dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); |
||
3037 | |||
3038 | /* Prevent unused argument(s) compilation and MISRA warning */ |
||
3039 | UNUSED(dmaxferstatus); |
||
3040 | |||
3041 | /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */ |
||
3042 | if (hi2c->hdmatx != NULL) |
||
3043 | { |
||
3044 | hi2c->hdmatx->XferCpltCallback = NULL; |
||
3045 | } |
||
3046 | |||
3047 | /* Disable Acknowledge */ |
||
3048 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3049 | |||
3050 | hi2c->XferSize = 0U; |
||
3051 | hi2c->XferCount = 0U; |
||
3052 | |||
3053 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
3054 | __HAL_I2C_DISABLE(hi2c); |
||
3055 | |||
3056 | return HAL_ERROR; |
||
3057 | } |
||
3058 | |||
3059 | /* Clear ADDR flag */ |
||
3060 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
3061 | |||
3062 | /* Process Unlocked */ |
||
3063 | __HAL_UNLOCK(hi2c); |
||
3064 | |||
3065 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3066 | to avoid the risk of I2C interrupt handle execution before current |
||
3067 | process unlock */ |
||
3068 | /* Enable ERR interrupt */ |
||
3069 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
||
3070 | |||
3071 | /* Enable DMA Request */ |
||
3072 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
3073 | |||
3074 | return HAL_OK; |
||
3075 | } |
||
3076 | else |
||
3077 | { |
||
3078 | /* Update I2C state */ |
||
3079 | hi2c->State = HAL_I2C_STATE_READY; |
||
3080 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3081 | |||
3082 | /* Update I2C error code */ |
||
3083 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
3084 | |||
3085 | /* Process Unlocked */ |
||
3086 | __HAL_UNLOCK(hi2c); |
||
3087 | |||
3088 | return HAL_ERROR; |
||
3089 | } |
||
3090 | } |
||
3091 | else |
||
3092 | { |
||
3093 | /* Update I2C state */ |
||
3094 | hi2c->State = HAL_I2C_STATE_READY; |
||
3095 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3096 | |||
3097 | /* Update I2C error code */ |
||
3098 | hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; |
||
3099 | |||
3100 | /* Process Unlocked */ |
||
3101 | __HAL_UNLOCK(hi2c); |
||
3102 | |||
3103 | return HAL_ERROR; |
||
3104 | } |
||
3105 | } |
||
3106 | else |
||
3107 | { |
||
3108 | return HAL_BUSY; |
||
3109 | } |
||
3110 | } |
||
3111 | |||
3112 | /** |
||
3113 | * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. |
||
3114 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3115 | * the configuration information for the specified I2C. |
||
3116 | * @param DevAddress Target device address: The device 7 bits address value |
||
3117 | * in datasheet must be shifted to the left before calling the interface |
||
3118 | * @param MemAddress Internal memory address |
||
3119 | * @param MemAddSize Size of internal memory address |
||
3120 | * @param pData Pointer to data buffer |
||
3121 | * @param Size Amount of data to be read |
||
3122 | * @retval HAL status |
||
3123 | */ |
||
3124 | HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
||
3125 | { |
||
3126 | /* Init tickstart for timeout management*/ |
||
3127 | uint32_t tickstart = HAL_GetTick(); |
||
3128 | __IO uint32_t count = 0U; |
||
3129 | HAL_StatusTypeDef dmaxferstatus; |
||
3130 | |||
3131 | /* Check the parameters */ |
||
3132 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
||
3133 | |||
3134 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3135 | { |
||
3136 | /* Wait until BUSY flag is reset */ |
||
3137 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3138 | do |
||
3139 | { |
||
3140 | count--; |
||
3141 | if (count == 0U) |
||
3142 | { |
||
3143 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3144 | hi2c->State = HAL_I2C_STATE_READY; |
||
3145 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3146 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3147 | |||
3148 | /* Process Unlocked */ |
||
3149 | __HAL_UNLOCK(hi2c); |
||
3150 | |||
3151 | return HAL_ERROR; |
||
3152 | } |
||
3153 | } |
||
3154 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3155 | |||
3156 | /* Process Locked */ |
||
3157 | __HAL_LOCK(hi2c); |
||
3158 | |||
3159 | /* Check if the I2C is already enabled */ |
||
3160 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3161 | { |
||
3162 | /* Enable I2C peripheral */ |
||
3163 | __HAL_I2C_ENABLE(hi2c); |
||
3164 | } |
||
3165 | |||
3166 | /* Disable Pos */ |
||
3167 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3168 | |||
3169 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
3170 | hi2c->Mode = HAL_I2C_MODE_MEM; |
||
3171 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3172 | |||
3173 | /* Prepare transfer parameters */ |
||
3174 | hi2c->pBuffPtr = pData; |
||
3175 | hi2c->XferCount = Size; |
||
3176 | hi2c->XferSize = hi2c->XferCount; |
||
3177 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
3178 | |||
3179 | if (hi2c->XferSize > 0U) |
||
3180 | { |
||
3181 | /* Set the I2C DMA transfer complete callback */ |
||
3182 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
3183 | |||
3184 | /* Set the DMA error callback */ |
||
3185 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
3186 | |||
3187 | /* Set the unused DMA callbacks to NULL */ |
||
3188 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
3189 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
3190 | |||
3191 | /* Enable the DMA channel */ |
||
3192 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
3193 | |||
3194 | if (dmaxferstatus == HAL_OK) |
||
3195 | { |
||
3196 | /* Send Slave Address and Memory Address */ |
||
3197 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
||
3198 | { |
||
3199 | /* Abort the ongoing DMA */ |
||
3200 | dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); |
||
3201 | |||
3202 | /* Prevent unused argument(s) compilation and MISRA warning */ |
||
3203 | UNUSED(dmaxferstatus); |
||
3204 | |||
3205 | /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */ |
||
3206 | if (hi2c->hdmarx != NULL) |
||
3207 | { |
||
3208 | hi2c->hdmarx->XferCpltCallback = NULL; |
||
3209 | } |
||
3210 | |||
3211 | /* Disable Acknowledge */ |
||
3212 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3213 | |||
3214 | hi2c->XferSize = 0U; |
||
3215 | hi2c->XferCount = 0U; |
||
3216 | |||
3217 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
3218 | __HAL_I2C_DISABLE(hi2c); |
||
3219 | |||
3220 | return HAL_ERROR; |
||
3221 | } |
||
3222 | |||
3223 | if (hi2c->XferSize == 1U) |
||
3224 | { |
||
3225 | /* Disable Acknowledge */ |
||
3226 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3227 | } |
||
3228 | else |
||
3229 | { |
||
3230 | /* Enable Last DMA bit */ |
||
3231 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
3232 | } |
||
3233 | |||
3234 | /* Clear ADDR flag */ |
||
3235 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
3236 | |||
3237 | /* Process Unlocked */ |
||
3238 | __HAL_UNLOCK(hi2c); |
||
3239 | |||
3240 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3241 | to avoid the risk of I2C interrupt handle execution before current |
||
3242 | process unlock */ |
||
3243 | /* Enable ERR interrupt */ |
||
3244 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
||
3245 | |||
3246 | /* Enable DMA Request */ |
||
3247 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
3248 | } |
||
3249 | else |
||
3250 | { |
||
3251 | /* Update I2C state */ |
||
3252 | hi2c->State = HAL_I2C_STATE_READY; |
||
3253 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3254 | |||
3255 | /* Update I2C error code */ |
||
3256 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
3257 | |||
3258 | /* Process Unlocked */ |
||
3259 | __HAL_UNLOCK(hi2c); |
||
3260 | |||
3261 | return HAL_ERROR; |
||
3262 | } |
||
3263 | } |
||
3264 | else |
||
3265 | { |
||
3266 | /* Send Slave Address and Memory Address */ |
||
3267 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
||
3268 | { |
||
3269 | return HAL_ERROR; |
||
3270 | } |
||
3271 | |||
3272 | /* Clear ADDR flag */ |
||
3273 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
3274 | |||
3275 | /* Generate Stop */ |
||
3276 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
3277 | |||
3278 | hi2c->State = HAL_I2C_STATE_READY; |
||
3279 | |||
3280 | /* Process Unlocked */ |
||
3281 | __HAL_UNLOCK(hi2c); |
||
3282 | } |
||
3283 | |||
3284 | return HAL_OK; |
||
3285 | } |
||
3286 | else |
||
3287 | { |
||
3288 | return HAL_BUSY; |
||
3289 | } |
||
3290 | } |
||
3291 | |||
3292 | /** |
||
3293 | * @brief Checks if target device is ready for communication. |
||
3294 | * @note This function is used with Memory devices |
||
3295 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3296 | * the configuration information for the specified I2C. |
||
3297 | * @param DevAddress Target device address: The device 7 bits address value |
||
3298 | * in datasheet must be shifted to the left before calling the interface |
||
3299 | * @param Trials Number of trials |
||
3300 | * @param Timeout Timeout duration |
||
3301 | * @retval HAL status |
||
3302 | */ |
||
3303 | HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) |
||
3304 | { |
||
3305 | /* Get tick */ |
||
3306 | uint32_t tickstart = HAL_GetTick(); |
||
3307 | uint32_t I2C_Trials = 1U; |
||
3308 | FlagStatus tmp1; |
||
3309 | FlagStatus tmp2; |
||
3310 | |||
3311 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3312 | { |
||
3313 | /* Wait until BUSY flag is reset */ |
||
3314 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
3315 | { |
||
3316 | return HAL_BUSY; |
||
3317 | } |
||
3318 | |||
3319 | /* Process Locked */ |
||
3320 | __HAL_LOCK(hi2c); |
||
3321 | |||
3322 | /* Check if the I2C is already enabled */ |
||
3323 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3324 | { |
||
3325 | /* Enable I2C peripheral */ |
||
3326 | __HAL_I2C_ENABLE(hi2c); |
||
3327 | } |
||
3328 | |||
3329 | /* Disable Pos */ |
||
3330 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3331 | |||
3332 | hi2c->State = HAL_I2C_STATE_BUSY; |
||
3333 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3334 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
3335 | |||
3336 | do |
||
3337 | { |
||
3338 | /* Generate Start */ |
||
3339 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3340 | |||
3341 | /* Wait until SB flag is set */ |
||
3342 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) |
||
3343 | { |
||
3344 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
3345 | { |
||
3346 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
3347 | } |
||
3348 | return HAL_TIMEOUT; |
||
3349 | } |
||
3350 | |||
3351 | /* Send slave address */ |
||
3352 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
3353 | |||
3354 | /* Wait until ADDR or AF flag are set */ |
||
3355 | /* Get tick */ |
||
3356 | tickstart = HAL_GetTick(); |
||
3357 | |||
3358 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
||
3359 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
||
3360 | while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) |
||
3361 | { |
||
3362 | if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) |
||
3363 | { |
||
3364 | hi2c->State = HAL_I2C_STATE_TIMEOUT; |
||
3365 | } |
||
3366 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
||
3367 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
||
3368 | } |
||
3369 | |||
3370 | hi2c->State = HAL_I2C_STATE_READY; |
||
3371 | |||
3372 | /* Check if the ADDR flag has been set */ |
||
3373 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) |
||
3374 | { |
||
3375 | /* Generate Stop */ |
||
3376 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
3377 | |||
3378 | /* Clear ADDR Flag */ |
||
3379 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
3380 | |||
3381 | /* Wait until BUSY flag is reset */ |
||
3382 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
3383 | { |
||
3384 | return HAL_ERROR; |
||
3385 | } |
||
3386 | |||
3387 | hi2c->State = HAL_I2C_STATE_READY; |
||
3388 | |||
3389 | /* Process Unlocked */ |
||
3390 | __HAL_UNLOCK(hi2c); |
||
3391 | |||
3392 | return HAL_OK; |
||
3393 | } |
||
3394 | else |
||
3395 | { |
||
3396 | /* Generate Stop */ |
||
3397 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
3398 | |||
3399 | /* Clear AF Flag */ |
||
3400 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
3401 | |||
3402 | /* Wait until BUSY flag is reset */ |
||
3403 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
||
3404 | { |
||
3405 | return HAL_ERROR; |
||
3406 | } |
||
3407 | } |
||
3408 | |||
3409 | /* Increment Trials */ |
||
3410 | I2C_Trials++; |
||
3411 | } |
||
3412 | while (I2C_Trials < Trials); |
||
3413 | |||
3414 | hi2c->State = HAL_I2C_STATE_READY; |
||
3415 | |||
3416 | /* Process Unlocked */ |
||
3417 | __HAL_UNLOCK(hi2c); |
||
3418 | |||
3419 | return HAL_ERROR; |
||
3420 | } |
||
3421 | else |
||
3422 | { |
||
3423 | return HAL_BUSY; |
||
3424 | } |
||
3425 | } |
||
3426 | |||
3427 | /** |
||
3428 | * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. |
||
3429 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
3430 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3431 | * the configuration information for the specified I2C. |
||
3432 | * @param DevAddress Target device address: The device 7 bits address value |
||
3433 | * in datasheet must be shifted to the left before calling the interface |
||
3434 | * @param pData Pointer to data buffer |
||
3435 | * @param Size Amount of data to be sent |
||
3436 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
3437 | * @retval HAL status |
||
3438 | */ |
||
3439 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
3440 | { |
||
3441 | __IO uint32_t Prev_State = 0x00U; |
||
3442 | __IO uint32_t count = 0x00U; |
||
3443 | |||
3444 | /* Check the parameters */ |
||
3445 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
3446 | |||
3447 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3448 | { |
||
3449 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
3450 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
3451 | { |
||
3452 | /* Wait until BUSY flag is reset */ |
||
3453 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3454 | do |
||
3455 | { |
||
3456 | count--; |
||
3457 | if (count == 0U) |
||
3458 | { |
||
3459 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3460 | hi2c->State = HAL_I2C_STATE_READY; |
||
3461 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3462 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3463 | |||
3464 | /* Process Unlocked */ |
||
3465 | __HAL_UNLOCK(hi2c); |
||
3466 | |||
3467 | return HAL_ERROR; |
||
3468 | } |
||
3469 | } |
||
3470 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3471 | } |
||
3472 | |||
3473 | /* Process Locked */ |
||
3474 | __HAL_LOCK(hi2c); |
||
3475 | |||
3476 | /* Check if the I2C is already enabled */ |
||
3477 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3478 | { |
||
3479 | /* Enable I2C peripheral */ |
||
3480 | __HAL_I2C_ENABLE(hi2c); |
||
3481 | } |
||
3482 | |||
3483 | /* Disable Pos */ |
||
3484 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3485 | |||
3486 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
3487 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
3488 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3489 | |||
3490 | /* Prepare transfer parameters */ |
||
3491 | hi2c->pBuffPtr = pData; |
||
3492 | hi2c->XferCount = Size; |
||
3493 | hi2c->XferSize = hi2c->XferCount; |
||
3494 | hi2c->XferOptions = XferOptions; |
||
3495 | hi2c->Devaddress = DevAddress; |
||
3496 | |||
3497 | Prev_State = hi2c->PreviousState; |
||
3498 | |||
3499 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
3500 | /* Mean Previous state is same as current state */ |
||
3501 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
3502 | { |
||
3503 | /* Generate Start */ |
||
3504 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3505 | } |
||
3506 | |||
3507 | /* Process Unlocked */ |
||
3508 | __HAL_UNLOCK(hi2c); |
||
3509 | |||
3510 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3511 | to avoid the risk of I2C interrupt handle execution before current |
||
3512 | process unlock */ |
||
3513 | |||
3514 | /* Enable EVT, BUF and ERR interrupt */ |
||
3515 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
3516 | |||
3517 | return HAL_OK; |
||
3518 | } |
||
3519 | else |
||
3520 | { |
||
3521 | return HAL_BUSY; |
||
3522 | } |
||
3523 | } |
||
3524 | |||
3525 | /** |
||
3526 | * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. |
||
3527 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
3528 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3529 | * the configuration information for the specified I2C. |
||
3530 | * @param DevAddress Target device address: The device 7 bits address value |
||
3531 | * in datasheet must be shifted to the left before calling the interface |
||
3532 | * @param pData Pointer to data buffer |
||
3533 | * @param Size Amount of data to be sent |
||
3534 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
3535 | * @retval HAL status |
||
3536 | */ |
||
3537 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
3538 | { |
||
3539 | __IO uint32_t Prev_State = 0x00U; |
||
3540 | __IO uint32_t count = 0x00U; |
||
3541 | HAL_StatusTypeDef dmaxferstatus; |
||
3542 | |||
3543 | /* Check the parameters */ |
||
3544 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
3545 | |||
3546 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3547 | { |
||
3548 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
3549 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
3550 | { |
||
3551 | /* Wait until BUSY flag is reset */ |
||
3552 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3553 | do |
||
3554 | { |
||
3555 | count--; |
||
3556 | if (count == 0U) |
||
3557 | { |
||
3558 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3559 | hi2c->State = HAL_I2C_STATE_READY; |
||
3560 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3561 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3562 | |||
3563 | /* Process Unlocked */ |
||
3564 | __HAL_UNLOCK(hi2c); |
||
3565 | |||
3566 | return HAL_ERROR; |
||
3567 | } |
||
3568 | } |
||
3569 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3570 | } |
||
3571 | |||
3572 | /* Process Locked */ |
||
3573 | __HAL_LOCK(hi2c); |
||
3574 | |||
3575 | /* Check if the I2C is already enabled */ |
||
3576 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3577 | { |
||
3578 | /* Enable I2C peripheral */ |
||
3579 | __HAL_I2C_ENABLE(hi2c); |
||
3580 | } |
||
3581 | |||
3582 | /* Disable Pos */ |
||
3583 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3584 | |||
3585 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
||
3586 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
3587 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3588 | |||
3589 | /* Prepare transfer parameters */ |
||
3590 | hi2c->pBuffPtr = pData; |
||
3591 | hi2c->XferCount = Size; |
||
3592 | hi2c->XferSize = hi2c->XferCount; |
||
3593 | hi2c->XferOptions = XferOptions; |
||
3594 | hi2c->Devaddress = DevAddress; |
||
3595 | |||
3596 | Prev_State = hi2c->PreviousState; |
||
3597 | |||
3598 | if (hi2c->XferSize > 0U) |
||
3599 | { |
||
3600 | /* Set the I2C DMA transfer complete callback */ |
||
3601 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
3602 | |||
3603 | /* Set the DMA error callback */ |
||
3604 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
3605 | |||
3606 | /* Set the unused DMA callbacks to NULL */ |
||
3607 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
3608 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
3609 | |||
3610 | /* Enable the DMA channel */ |
||
3611 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
3612 | |||
3613 | if (dmaxferstatus == HAL_OK) |
||
3614 | { |
||
3615 | /* Enable Acknowledge */ |
||
3616 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3617 | |||
3618 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
3619 | /* Mean Previous state is same as current state */ |
||
3620 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
3621 | { |
||
3622 | /* Generate Start */ |
||
3623 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3624 | } |
||
3625 | |||
3626 | /* Process Unlocked */ |
||
3627 | __HAL_UNLOCK(hi2c); |
||
3628 | |||
3629 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3630 | to avoid the risk of I2C interrupt handle execution before current |
||
3631 | process unlock */ |
||
3632 | |||
3633 | /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ |
||
3634 | /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ |
||
3635 | if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
||
3636 | { |
||
3637 | /* Enable DMA Request */ |
||
3638 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
3639 | } |
||
3640 | |||
3641 | /* Enable EVT and ERR interrupt */ |
||
3642 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
3643 | } |
||
3644 | else |
||
3645 | { |
||
3646 | /* Update I2C state */ |
||
3647 | hi2c->State = HAL_I2C_STATE_READY; |
||
3648 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3649 | |||
3650 | /* Update I2C error code */ |
||
3651 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
3652 | |||
3653 | /* Process Unlocked */ |
||
3654 | __HAL_UNLOCK(hi2c); |
||
3655 | |||
3656 | return HAL_ERROR; |
||
3657 | } |
||
3658 | } |
||
3659 | else |
||
3660 | { |
||
3661 | /* Enable Acknowledge */ |
||
3662 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3663 | |||
3664 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
3665 | /* Mean Previous state is same as current state */ |
||
3666 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
3667 | { |
||
3668 | /* Generate Start */ |
||
3669 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3670 | } |
||
3671 | |||
3672 | /* Process Unlocked */ |
||
3673 | __HAL_UNLOCK(hi2c); |
||
3674 | |||
3675 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3676 | to avoid the risk of I2C interrupt handle execution before current |
||
3677 | process unlock */ |
||
3678 | |||
3679 | /* Enable EVT, BUF and ERR interrupt */ |
||
3680 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
3681 | } |
||
3682 | |||
3683 | return HAL_OK; |
||
3684 | } |
||
3685 | else |
||
3686 | { |
||
3687 | return HAL_BUSY; |
||
3688 | } |
||
3689 | } |
||
3690 | |||
3691 | /** |
||
3692 | * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt |
||
3693 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
3694 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3695 | * the configuration information for the specified I2C. |
||
3696 | * @param DevAddress Target device address: The device 7 bits address value |
||
3697 | * in datasheet must be shifted to the left before calling the interface |
||
3698 | * @param pData Pointer to data buffer |
||
3699 | * @param Size Amount of data to be sent |
||
3700 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
3701 | * @retval HAL status |
||
3702 | */ |
||
3703 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
3704 | { |
||
3705 | __IO uint32_t Prev_State = 0x00U; |
||
3706 | __IO uint32_t count = 0U; |
||
3707 | uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
3708 | |||
3709 | /* Check the parameters */ |
||
3710 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
3711 | |||
3712 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3713 | { |
||
3714 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
3715 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
3716 | { |
||
3717 | /* Wait until BUSY flag is reset */ |
||
3718 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3719 | do |
||
3720 | { |
||
3721 | count--; |
||
3722 | if (count == 0U) |
||
3723 | { |
||
3724 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3725 | hi2c->State = HAL_I2C_STATE_READY; |
||
3726 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3727 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3728 | |||
3729 | /* Process Unlocked */ |
||
3730 | __HAL_UNLOCK(hi2c); |
||
3731 | |||
3732 | return HAL_ERROR; |
||
3733 | } |
||
3734 | } |
||
3735 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3736 | } |
||
3737 | |||
3738 | /* Process Locked */ |
||
3739 | __HAL_LOCK(hi2c); |
||
3740 | |||
3741 | /* Check if the I2C is already enabled */ |
||
3742 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3743 | { |
||
3744 | /* Enable I2C peripheral */ |
||
3745 | __HAL_I2C_ENABLE(hi2c); |
||
3746 | } |
||
3747 | |||
3748 | /* Disable Pos */ |
||
3749 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3750 | |||
3751 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
3752 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
3753 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3754 | |||
3755 | /* Prepare transfer parameters */ |
||
3756 | hi2c->pBuffPtr = pData; |
||
3757 | hi2c->XferCount = Size; |
||
3758 | hi2c->XferSize = hi2c->XferCount; |
||
3759 | hi2c->XferOptions = XferOptions; |
||
3760 | hi2c->Devaddress = DevAddress; |
||
3761 | |||
3762 | Prev_State = hi2c->PreviousState; |
||
3763 | |||
3764 | if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) |
||
3765 | { |
||
3766 | if (Prev_State == I2C_STATE_MASTER_BUSY_RX) |
||
3767 | { |
||
3768 | /* Disable Acknowledge */ |
||
3769 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3770 | |||
3771 | /* Enable Pos */ |
||
3772 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3773 | |||
3774 | /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ |
||
3775 | enableIT &= ~I2C_IT_BUF; |
||
3776 | } |
||
3777 | else |
||
3778 | { |
||
3779 | /* Enable Acknowledge */ |
||
3780 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3781 | } |
||
3782 | } |
||
3783 | else |
||
3784 | { |
||
3785 | /* Enable Acknowledge */ |
||
3786 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3787 | } |
||
3788 | |||
3789 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
3790 | /* Mean Previous state is same as current state */ |
||
3791 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
3792 | { |
||
3793 | /* Generate Start */ |
||
3794 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3795 | } |
||
3796 | |||
3797 | /* Process Unlocked */ |
||
3798 | __HAL_UNLOCK(hi2c); |
||
3799 | |||
3800 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3801 | to avoid the risk of I2C interrupt handle execution before current |
||
3802 | process unlock */ |
||
3803 | |||
3804 | /* Enable interrupts */ |
||
3805 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
||
3806 | |||
3807 | return HAL_OK; |
||
3808 | } |
||
3809 | else |
||
3810 | { |
||
3811 | return HAL_BUSY; |
||
3812 | } |
||
3813 | } |
||
3814 | |||
3815 | /** |
||
3816 | * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA |
||
3817 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
3818 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
3819 | * the configuration information for the specified I2C. |
||
3820 | * @param DevAddress Target device address: The device 7 bits address value |
||
3821 | * in datasheet must be shifted to the left before calling the interface |
||
3822 | * @param pData Pointer to data buffer |
||
3823 | * @param Size Amount of data to be sent |
||
3824 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
3825 | * @retval HAL status |
||
3826 | */ |
||
3827 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
3828 | { |
||
3829 | __IO uint32_t Prev_State = 0x00U; |
||
3830 | __IO uint32_t count = 0U; |
||
3831 | uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
3832 | HAL_StatusTypeDef dmaxferstatus; |
||
3833 | |||
3834 | /* Check the parameters */ |
||
3835 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
3836 | |||
3837 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
3838 | { |
||
3839 | /* Check Busy Flag only if FIRST call of Master interface */ |
||
3840 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
||
3841 | { |
||
3842 | /* Wait until BUSY flag is reset */ |
||
3843 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
||
3844 | do |
||
3845 | { |
||
3846 | count--; |
||
3847 | if (count == 0U) |
||
3848 | { |
||
3849 | hi2c->PreviousState = I2C_STATE_NONE; |
||
3850 | hi2c->State = HAL_I2C_STATE_READY; |
||
3851 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3852 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
3853 | |||
3854 | /* Process Unlocked */ |
||
3855 | __HAL_UNLOCK(hi2c); |
||
3856 | |||
3857 | return HAL_ERROR; |
||
3858 | } |
||
3859 | } |
||
3860 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
||
3861 | } |
||
3862 | |||
3863 | /* Process Locked */ |
||
3864 | __HAL_LOCK(hi2c); |
||
3865 | |||
3866 | /* Check if the I2C is already enabled */ |
||
3867 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
3868 | { |
||
3869 | /* Enable I2C peripheral */ |
||
3870 | __HAL_I2C_ENABLE(hi2c); |
||
3871 | } |
||
3872 | |||
3873 | /* Disable Pos */ |
||
3874 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3875 | |||
3876 | /* Clear Last DMA bit */ |
||
3877 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
3878 | |||
3879 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
||
3880 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
||
3881 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
3882 | |||
3883 | /* Prepare transfer parameters */ |
||
3884 | hi2c->pBuffPtr = pData; |
||
3885 | hi2c->XferCount = Size; |
||
3886 | hi2c->XferSize = hi2c->XferCount; |
||
3887 | hi2c->XferOptions = XferOptions; |
||
3888 | hi2c->Devaddress = DevAddress; |
||
3889 | |||
3890 | Prev_State = hi2c->PreviousState; |
||
3891 | |||
3892 | if (hi2c->XferSize > 0U) |
||
3893 | { |
||
3894 | if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) |
||
3895 | { |
||
3896 | if (Prev_State == I2C_STATE_MASTER_BUSY_RX) |
||
3897 | { |
||
3898 | /* Disable Acknowledge */ |
||
3899 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3900 | |||
3901 | /* Enable Pos */ |
||
3902 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
3903 | |||
3904 | /* Enable Last DMA bit */ |
||
3905 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
3906 | } |
||
3907 | else |
||
3908 | { |
||
3909 | /* Enable Acknowledge */ |
||
3910 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3911 | } |
||
3912 | } |
||
3913 | else |
||
3914 | { |
||
3915 | /* Enable Acknowledge */ |
||
3916 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3917 | |||
3918 | if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
||
3919 | { |
||
3920 | /* Enable Last DMA bit */ |
||
3921 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
3922 | } |
||
3923 | } |
||
3924 | |||
3925 | /* Set the I2C DMA transfer complete callback */ |
||
3926 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
3927 | |||
3928 | /* Set the DMA error callback */ |
||
3929 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
3930 | |||
3931 | /* Set the unused DMA callbacks to NULL */ |
||
3932 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
3933 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
3934 | |||
3935 | /* Enable the DMA channel */ |
||
3936 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
3937 | |||
3938 | if (dmaxferstatus == HAL_OK) |
||
3939 | { |
||
3940 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
3941 | /* Mean Previous state is same as current state */ |
||
3942 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
3943 | { |
||
3944 | /* Generate Start */ |
||
3945 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
3946 | |||
3947 | /* Update interrupt for only EVT and ERR */ |
||
3948 | enableIT = (I2C_IT_EVT | I2C_IT_ERR); |
||
3949 | } |
||
3950 | else |
||
3951 | { |
||
3952 | /* Update interrupt for only ERR */ |
||
3953 | enableIT = I2C_IT_ERR; |
||
3954 | } |
||
3955 | |||
3956 | /* Process Unlocked */ |
||
3957 | __HAL_UNLOCK(hi2c); |
||
3958 | |||
3959 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
3960 | to avoid the risk of I2C interrupt handle execution before current |
||
3961 | process unlock */ |
||
3962 | |||
3963 | /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ |
||
3964 | /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ |
||
3965 | if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
||
3966 | { |
||
3967 | /* Enable DMA Request */ |
||
3968 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
3969 | } |
||
3970 | |||
3971 | /* Enable EVT and ERR interrupt */ |
||
3972 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
||
3973 | } |
||
3974 | else |
||
3975 | { |
||
3976 | /* Update I2C state */ |
||
3977 | hi2c->State = HAL_I2C_STATE_READY; |
||
3978 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
3979 | |||
3980 | /* Update I2C error code */ |
||
3981 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
3982 | |||
3983 | /* Process Unlocked */ |
||
3984 | __HAL_UNLOCK(hi2c); |
||
3985 | |||
3986 | return HAL_ERROR; |
||
3987 | } |
||
3988 | } |
||
3989 | else |
||
3990 | { |
||
3991 | /* Enable Acknowledge */ |
||
3992 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
3993 | |||
3994 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
||
3995 | /* Mean Previous state is same as current state */ |
||
3996 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
||
3997 | { |
||
3998 | /* Generate Start */ |
||
3999 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
4000 | } |
||
4001 | |||
4002 | /* Process Unlocked */ |
||
4003 | __HAL_UNLOCK(hi2c); |
||
4004 | |||
4005 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4006 | to avoid the risk of I2C interrupt handle execution before current |
||
4007 | process unlock */ |
||
4008 | |||
4009 | /* Enable interrupts */ |
||
4010 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
||
4011 | } |
||
4012 | return HAL_OK; |
||
4013 | } |
||
4014 | else |
||
4015 | { |
||
4016 | return HAL_BUSY; |
||
4017 | } |
||
4018 | } |
||
4019 | |||
4020 | /** |
||
4021 | * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt |
||
4022 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
4023 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4024 | * the configuration information for the specified I2C. |
||
4025 | * @param pData Pointer to data buffer |
||
4026 | * @param Size Amount of data to be sent |
||
4027 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
4028 | * @retval HAL status |
||
4029 | */ |
||
4030 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
4031 | { |
||
4032 | /* Check the parameters */ |
||
4033 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
4034 | |||
4035 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
4036 | { |
||
4037 | if ((pData == NULL) || (Size == 0U)) |
||
4038 | { |
||
4039 | return HAL_ERROR; |
||
4040 | } |
||
4041 | |||
4042 | /* Process Locked */ |
||
4043 | __HAL_LOCK(hi2c); |
||
4044 | |||
4045 | /* Check if the I2C is already enabled */ |
||
4046 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4047 | { |
||
4048 | /* Enable I2C peripheral */ |
||
4049 | __HAL_I2C_ENABLE(hi2c); |
||
4050 | } |
||
4051 | |||
4052 | /* Disable Pos */ |
||
4053 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4054 | |||
4055 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
||
4056 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
4057 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
4058 | |||
4059 | /* Prepare transfer parameters */ |
||
4060 | hi2c->pBuffPtr = pData; |
||
4061 | hi2c->XferCount = Size; |
||
4062 | hi2c->XferSize = hi2c->XferCount; |
||
4063 | hi2c->XferOptions = XferOptions; |
||
4064 | |||
4065 | /* Clear ADDR flag */ |
||
4066 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
4067 | |||
4068 | /* Process Unlocked */ |
||
4069 | __HAL_UNLOCK(hi2c); |
||
4070 | |||
4071 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4072 | to avoid the risk of I2C interrupt handle execution before current |
||
4073 | process unlock */ |
||
4074 | |||
4075 | /* Enable EVT, BUF and ERR interrupt */ |
||
4076 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
4077 | |||
4078 | return HAL_OK; |
||
4079 | } |
||
4080 | else |
||
4081 | { |
||
4082 | return HAL_BUSY; |
||
4083 | } |
||
4084 | } |
||
4085 | |||
4086 | /** |
||
4087 | * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA |
||
4088 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
4089 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4090 | * the configuration information for the specified I2C. |
||
4091 | * @param pData Pointer to data buffer |
||
4092 | * @param Size Amount of data to be sent |
||
4093 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
4094 | * @retval HAL status |
||
4095 | */ |
||
4096 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
4097 | { |
||
4098 | HAL_StatusTypeDef dmaxferstatus; |
||
4099 | |||
4100 | /* Check the parameters */ |
||
4101 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
4102 | |||
4103 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
4104 | { |
||
4105 | if ((pData == NULL) || (Size == 0U)) |
||
4106 | { |
||
4107 | return HAL_ERROR; |
||
4108 | } |
||
4109 | |||
4110 | /* Process Locked */ |
||
4111 | __HAL_LOCK(hi2c); |
||
4112 | |||
4113 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
||
4114 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4115 | |||
4116 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
||
4117 | /* and then toggle the HAL slave RX state to TX state */ |
||
4118 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
||
4119 | { |
||
4120 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
4121 | { |
||
4122 | /* Abort DMA Xfer if any */ |
||
4123 | if (hi2c->hdmarx != NULL) |
||
4124 | { |
||
4125 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4126 | |||
4127 | /* Set the I2C DMA Abort callback : |
||
4128 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
4129 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
||
4130 | |||
4131 | /* Abort DMA RX */ |
||
4132 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
||
4133 | { |
||
4134 | /* Call Directly XferAbortCallback function in case of error */ |
||
4135 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
||
4136 | } |
||
4137 | } |
||
4138 | } |
||
4139 | } |
||
4140 | else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
||
4141 | { |
||
4142 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
4143 | { |
||
4144 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4145 | |||
4146 | /* Abort DMA Xfer if any */ |
||
4147 | if (hi2c->hdmatx != NULL) |
||
4148 | { |
||
4149 | /* Set the I2C DMA Abort callback : |
||
4150 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
4151 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
||
4152 | |||
4153 | /* Abort DMA TX */ |
||
4154 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
||
4155 | { |
||
4156 | /* Call Directly XferAbortCallback function in case of error */ |
||
4157 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
||
4158 | } |
||
4159 | } |
||
4160 | } |
||
4161 | } |
||
4162 | else |
||
4163 | { |
||
4164 | /* Nothing to do */ |
||
4165 | } |
||
4166 | |||
4167 | /* Check if the I2C is already enabled */ |
||
4168 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4169 | { |
||
4170 | /* Enable I2C peripheral */ |
||
4171 | __HAL_I2C_ENABLE(hi2c); |
||
4172 | } |
||
4173 | |||
4174 | /* Disable Pos */ |
||
4175 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4176 | |||
4177 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
||
4178 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
4179 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
4180 | |||
4181 | /* Prepare transfer parameters */ |
||
4182 | hi2c->pBuffPtr = pData; |
||
4183 | hi2c->XferCount = Size; |
||
4184 | hi2c->XferSize = hi2c->XferCount; |
||
4185 | hi2c->XferOptions = XferOptions; |
||
4186 | |||
4187 | /* Set the I2C DMA transfer complete callback */ |
||
4188 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
||
4189 | |||
4190 | /* Set the DMA error callback */ |
||
4191 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
||
4192 | |||
4193 | /* Set the unused DMA callbacks to NULL */ |
||
4194 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
||
4195 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
4196 | |||
4197 | /* Enable the DMA channel */ |
||
4198 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
||
4199 | |||
4200 | if (dmaxferstatus == HAL_OK) |
||
4201 | { |
||
4202 | /* Enable Address Acknowledge */ |
||
4203 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4204 | |||
4205 | /* Clear ADDR flag */ |
||
4206 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
4207 | |||
4208 | /* Process Unlocked */ |
||
4209 | __HAL_UNLOCK(hi2c); |
||
4210 | |||
4211 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4212 | to avoid the risk of I2C interrupt handle execution before current |
||
4213 | process unlock */ |
||
4214 | /* Enable EVT and ERR interrupt */ |
||
4215 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4216 | |||
4217 | /* Enable DMA Request */ |
||
4218 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
||
4219 | |||
4220 | return HAL_OK; |
||
4221 | } |
||
4222 | else |
||
4223 | { |
||
4224 | /* Update I2C state */ |
||
4225 | hi2c->State = HAL_I2C_STATE_READY; |
||
4226 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4227 | |||
4228 | /* Update I2C error code */ |
||
4229 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
4230 | |||
4231 | /* Process Unlocked */ |
||
4232 | __HAL_UNLOCK(hi2c); |
||
4233 | |||
4234 | return HAL_ERROR; |
||
4235 | } |
||
4236 | } |
||
4237 | else |
||
4238 | { |
||
4239 | return HAL_BUSY; |
||
4240 | } |
||
4241 | } |
||
4242 | |||
4243 | /** |
||
4244 | * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt |
||
4245 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
4246 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4247 | * the configuration information for the specified I2C. |
||
4248 | * @param pData Pointer to data buffer |
||
4249 | * @param Size Amount of data to be sent |
||
4250 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
4251 | * @retval HAL status |
||
4252 | */ |
||
4253 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
4254 | { |
||
4255 | /* Check the parameters */ |
||
4256 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
4257 | |||
4258 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
4259 | { |
||
4260 | if ((pData == NULL) || (Size == 0U)) |
||
4261 | { |
||
4262 | return HAL_ERROR; |
||
4263 | } |
||
4264 | |||
4265 | /* Process Locked */ |
||
4266 | __HAL_LOCK(hi2c); |
||
4267 | |||
4268 | /* Check if the I2C is already enabled */ |
||
4269 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4270 | { |
||
4271 | /* Enable I2C peripheral */ |
||
4272 | __HAL_I2C_ENABLE(hi2c); |
||
4273 | } |
||
4274 | |||
4275 | /* Disable Pos */ |
||
4276 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4277 | |||
4278 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
||
4279 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
4280 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
4281 | |||
4282 | /* Prepare transfer parameters */ |
||
4283 | hi2c->pBuffPtr = pData; |
||
4284 | hi2c->XferCount = Size; |
||
4285 | hi2c->XferSize = hi2c->XferCount; |
||
4286 | hi2c->XferOptions = XferOptions; |
||
4287 | |||
4288 | /* Clear ADDR flag */ |
||
4289 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
4290 | |||
4291 | /* Process Unlocked */ |
||
4292 | __HAL_UNLOCK(hi2c); |
||
4293 | |||
4294 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4295 | to avoid the risk of I2C interrupt handle execution before current |
||
4296 | process unlock */ |
||
4297 | |||
4298 | /* Enable EVT, BUF and ERR interrupt */ |
||
4299 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
4300 | |||
4301 | return HAL_OK; |
||
4302 | } |
||
4303 | else |
||
4304 | { |
||
4305 | return HAL_BUSY; |
||
4306 | } |
||
4307 | } |
||
4308 | |||
4309 | /** |
||
4310 | * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA |
||
4311 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
||
4312 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4313 | * the configuration information for the specified I2C. |
||
4314 | * @param pData Pointer to data buffer |
||
4315 | * @param Size Amount of data to be sent |
||
4316 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
||
4317 | * @retval HAL status |
||
4318 | */ |
||
4319 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
||
4320 | { |
||
4321 | HAL_StatusTypeDef dmaxferstatus; |
||
4322 | |||
4323 | /* Check the parameters */ |
||
4324 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
||
4325 | |||
4326 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
4327 | { |
||
4328 | if ((pData == NULL) || (Size == 0U)) |
||
4329 | { |
||
4330 | return HAL_ERROR; |
||
4331 | } |
||
4332 | |||
4333 | /* Process Locked */ |
||
4334 | __HAL_LOCK(hi2c); |
||
4335 | |||
4336 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
||
4337 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4338 | |||
4339 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
||
4340 | /* and then toggle the HAL slave RX state to TX state */ |
||
4341 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
||
4342 | { |
||
4343 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
4344 | { |
||
4345 | /* Abort DMA Xfer if any */ |
||
4346 | if (hi2c->hdmarx != NULL) |
||
4347 | { |
||
4348 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4349 | |||
4350 | /* Set the I2C DMA Abort callback : |
||
4351 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
4352 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
||
4353 | |||
4354 | /* Abort DMA RX */ |
||
4355 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
||
4356 | { |
||
4357 | /* Call Directly XferAbortCallback function in case of error */ |
||
4358 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
||
4359 | } |
||
4360 | } |
||
4361 | } |
||
4362 | } |
||
4363 | else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
||
4364 | { |
||
4365 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
4366 | { |
||
4367 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4368 | |||
4369 | /* Abort DMA Xfer if any */ |
||
4370 | if (hi2c->hdmatx != NULL) |
||
4371 | { |
||
4372 | /* Set the I2C DMA Abort callback : |
||
4373 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
4374 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
||
4375 | |||
4376 | /* Abort DMA TX */ |
||
4377 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
||
4378 | { |
||
4379 | /* Call Directly XferAbortCallback function in case of error */ |
||
4380 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
||
4381 | } |
||
4382 | } |
||
4383 | } |
||
4384 | } |
||
4385 | else |
||
4386 | { |
||
4387 | /* Nothing to do */ |
||
4388 | } |
||
4389 | |||
4390 | /* Check if the I2C is already enabled */ |
||
4391 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4392 | { |
||
4393 | /* Enable I2C peripheral */ |
||
4394 | __HAL_I2C_ENABLE(hi2c); |
||
4395 | } |
||
4396 | |||
4397 | /* Disable Pos */ |
||
4398 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
4399 | |||
4400 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
||
4401 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
||
4402 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
4403 | |||
4404 | /* Prepare transfer parameters */ |
||
4405 | hi2c->pBuffPtr = pData; |
||
4406 | hi2c->XferCount = Size; |
||
4407 | hi2c->XferSize = hi2c->XferCount; |
||
4408 | hi2c->XferOptions = XferOptions; |
||
4409 | |||
4410 | /* Set the I2C DMA transfer complete callback */ |
||
4411 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
||
4412 | |||
4413 | /* Set the DMA error callback */ |
||
4414 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
||
4415 | |||
4416 | /* Set the unused DMA callbacks to NULL */ |
||
4417 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
||
4418 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
4419 | |||
4420 | /* Enable the DMA channel */ |
||
4421 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
||
4422 | |||
4423 | if (dmaxferstatus == HAL_OK) |
||
4424 | { |
||
4425 | /* Enable Address Acknowledge */ |
||
4426 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4427 | |||
4428 | /* Clear ADDR flag */ |
||
4429 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
4430 | |||
4431 | /* Process Unlocked */ |
||
4432 | __HAL_UNLOCK(hi2c); |
||
4433 | |||
4434 | /* Enable DMA Request */ |
||
4435 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
4436 | |||
4437 | /* Note : The I2C interrupts must be enabled after unlocking current process |
||
4438 | to avoid the risk of I2C interrupt handle execution before current |
||
4439 | process unlock */ |
||
4440 | /* Enable EVT and ERR interrupt */ |
||
4441 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4442 | |||
4443 | return HAL_OK; |
||
4444 | } |
||
4445 | else |
||
4446 | { |
||
4447 | /* Update I2C state */ |
||
4448 | hi2c->State = HAL_I2C_STATE_READY; |
||
4449 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4450 | |||
4451 | /* Update I2C error code */ |
||
4452 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
4453 | |||
4454 | /* Process Unlocked */ |
||
4455 | __HAL_UNLOCK(hi2c); |
||
4456 | |||
4457 | return HAL_ERROR; |
||
4458 | } |
||
4459 | } |
||
4460 | else |
||
4461 | { |
||
4462 | return HAL_BUSY; |
||
4463 | } |
||
4464 | } |
||
4465 | |||
4466 | /** |
||
4467 | * @brief Enable the Address listen mode with Interrupt. |
||
4468 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4469 | * the configuration information for the specified I2C. |
||
4470 | * @retval HAL status |
||
4471 | */ |
||
4472 | HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) |
||
4473 | { |
||
4474 | if (hi2c->State == HAL_I2C_STATE_READY) |
||
4475 | { |
||
4476 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
4477 | |||
4478 | /* Check if the I2C is already enabled */ |
||
4479 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
||
4480 | { |
||
4481 | /* Enable I2C peripheral */ |
||
4482 | __HAL_I2C_ENABLE(hi2c); |
||
4483 | } |
||
4484 | |||
4485 | /* Enable Address Acknowledge */ |
||
4486 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4487 | |||
4488 | /* Enable EVT and ERR interrupt */ |
||
4489 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4490 | |||
4491 | return HAL_OK; |
||
4492 | } |
||
4493 | else |
||
4494 | { |
||
4495 | return HAL_BUSY; |
||
4496 | } |
||
4497 | } |
||
4498 | |||
4499 | /** |
||
4500 | * @brief Disable the Address listen mode with Interrupt. |
||
4501 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4502 | * the configuration information for the specified I2C. |
||
4503 | * @retval HAL status |
||
4504 | */ |
||
4505 | HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) |
||
4506 | { |
||
4507 | /* Declaration of tmp to prevent undefined behavior of volatile usage */ |
||
4508 | uint32_t tmp; |
||
4509 | |||
4510 | /* Disable Address listen mode only if a transfer is not ongoing */ |
||
4511 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
||
4512 | { |
||
4513 | tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; |
||
4514 | hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); |
||
4515 | hi2c->State = HAL_I2C_STATE_READY; |
||
4516 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
4517 | |||
4518 | /* Disable Address Acknowledge */ |
||
4519 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4520 | |||
4521 | /* Disable EVT and ERR interrupt */ |
||
4522 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
4523 | |||
4524 | return HAL_OK; |
||
4525 | } |
||
4526 | else |
||
4527 | { |
||
4528 | return HAL_BUSY; |
||
4529 | } |
||
4530 | } |
||
4531 | |||
4532 | /** |
||
4533 | * @brief Abort a master I2C IT or DMA process communication with Interrupt. |
||
4534 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4535 | * the configuration information for the specified I2C. |
||
4536 | * @param DevAddress Target device address: The device 7 bits address value |
||
4537 | * in datasheet must be shifted to the left before calling the interface |
||
4538 | * @retval HAL status |
||
4539 | */ |
||
4540 | HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) |
||
4541 | { |
||
4542 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
4543 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
4544 | |||
4545 | /* Prevent unused argument(s) compilation warning */ |
||
4546 | UNUSED(DevAddress); |
||
4547 | |||
4548 | /* Abort Master transfer during Receive or Transmit process */ |
||
4549 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER)) |
||
4550 | { |
||
4551 | /* Process Locked */ |
||
4552 | __HAL_LOCK(hi2c); |
||
4553 | |||
4554 | hi2c->PreviousState = I2C_STATE_NONE; |
||
4555 | hi2c->State = HAL_I2C_STATE_ABORT; |
||
4556 | |||
4557 | /* Disable Acknowledge */ |
||
4558 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
4559 | |||
4560 | /* Generate Stop */ |
||
4561 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
4562 | |||
4563 | hi2c->XferCount = 0U; |
||
4564 | |||
4565 | /* Disable EVT, BUF and ERR interrupt */ |
||
4566 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
4567 | |||
4568 | /* Process Unlocked */ |
||
4569 | __HAL_UNLOCK(hi2c); |
||
4570 | |||
4571 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
4572 | I2C_ITError(hi2c); |
||
4573 | |||
4574 | return HAL_OK; |
||
4575 | } |
||
4576 | else |
||
4577 | { |
||
4578 | /* Wrong usage of abort function */ |
||
4579 | /* This function should be used only in case of abort monitored by master device */ |
||
4580 | /* Or periphal is not in busy state, mean there is no active sequence to be abort */ |
||
4581 | return HAL_ERROR; |
||
4582 | } |
||
4583 | } |
||
4584 | |||
4585 | /** |
||
4586 | * @} |
||
4587 | */ |
||
4588 | |||
4589 | /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
||
4590 | * @{ |
||
4591 | */ |
||
4592 | |||
4593 | /** |
||
4594 | * @brief This function handles I2C event interrupt request. |
||
4595 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4596 | * the configuration information for the specified I2C. |
||
4597 | * @retval None |
||
4598 | */ |
||
4599 | void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) |
||
4600 | { |
||
4601 | uint32_t sr1itflags; |
||
4602 | uint32_t sr2itflags = 0U; |
||
4603 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
||
4604 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
4605 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
4606 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
4607 | |||
4608 | /* Master or Memory mode selected */ |
||
4609 | if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) |
||
4610 | { |
||
4611 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
||
4612 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
4613 | |||
4614 | /* Exit IRQ event until Start Bit detected in case of Other frame requested */ |
||
4615 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) |
||
4616 | { |
||
4617 | return; |
||
4618 | } |
||
4619 | |||
4620 | /* SB Set ----------------------------------------------------------------*/ |
||
4621 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4622 | { |
||
4623 | /* Convert OTHER_xxx XferOptions if any */ |
||
4624 | I2C_ConvertOtherXferOptions(hi2c); |
||
4625 | |||
4626 | I2C_Master_SB(hi2c); |
||
4627 | } |
||
4628 | /* ADD10 Set -------------------------------------------------------------*/ |
||
4629 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4630 | { |
||
4631 | I2C_Master_ADD10(hi2c); |
||
4632 | } |
||
4633 | /* ADDR Set --------------------------------------------------------------*/ |
||
4634 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4635 | { |
||
4636 | I2C_Master_ADDR(hi2c); |
||
4637 | } |
||
4638 | /* I2C in mode Transmitter -----------------------------------------------*/ |
||
4639 | else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) |
||
4640 | { |
||
4641 | /* Do not check buffer and BTF flag if a Xfer DMA is on going */ |
||
4642 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) |
||
4643 | { |
||
4644 | /* TXE set and BTF reset -----------------------------------------------*/ |
||
4645 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
||
4646 | { |
||
4647 | I2C_MasterTransmit_TXE(hi2c); |
||
4648 | } |
||
4649 | /* BTF set -------------------------------------------------------------*/ |
||
4650 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4651 | { |
||
4652 | if (CurrentMode == HAL_I2C_MODE_MASTER) |
||
4653 | { |
||
4654 | I2C_MasterTransmit_BTF(hi2c); |
||
4655 | } |
||
4656 | else /* HAL_I2C_MODE_MEM */ |
||
4657 | { |
||
4658 | I2C_MemoryTransmit_TXE_BTF(hi2c); |
||
4659 | } |
||
4660 | } |
||
4661 | else |
||
4662 | { |
||
4663 | /* Do nothing */ |
||
4664 | } |
||
4665 | } |
||
4666 | } |
||
4667 | /* I2C in mode Receiver --------------------------------------------------*/ |
||
4668 | else |
||
4669 | { |
||
4670 | /* Do not check buffer and BTF flag if a Xfer DMA is on going */ |
||
4671 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) |
||
4672 | { |
||
4673 | /* RXNE set and BTF reset -----------------------------------------------*/ |
||
4674 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
||
4675 | { |
||
4676 | I2C_MasterReceive_RXNE(hi2c); |
||
4677 | } |
||
4678 | /* BTF set -------------------------------------------------------------*/ |
||
4679 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4680 | { |
||
4681 | I2C_MasterReceive_BTF(hi2c); |
||
4682 | } |
||
4683 | else |
||
4684 | { |
||
4685 | /* Do nothing */ |
||
4686 | } |
||
4687 | } |
||
4688 | } |
||
4689 | } |
||
4690 | /* Slave mode selected */ |
||
4691 | else |
||
4692 | { |
||
4693 | /* If an error is detected, read only SR1 register to prevent */ |
||
4694 | /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ |
||
4695 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
4696 | { |
||
4697 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
4698 | } |
||
4699 | else |
||
4700 | { |
||
4701 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
||
4702 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
4703 | } |
||
4704 | |||
4705 | /* ADDR set --------------------------------------------------------------*/ |
||
4706 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4707 | { |
||
4708 | /* Now time to read SR2, this will clear ADDR flag automatically */ |
||
4709 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
4710 | { |
||
4711 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
||
4712 | } |
||
4713 | I2C_Slave_ADDR(hi2c, sr2itflags); |
||
4714 | } |
||
4715 | /* STOPF set --------------------------------------------------------------*/ |
||
4716 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4717 | { |
||
4718 | I2C_Slave_STOPF(hi2c); |
||
4719 | } |
||
4720 | /* I2C in mode Transmitter -----------------------------------------------*/ |
||
4721 | else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
||
4722 | { |
||
4723 | /* TXE set and BTF reset -----------------------------------------------*/ |
||
4724 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
||
4725 | { |
||
4726 | I2C_SlaveTransmit_TXE(hi2c); |
||
4727 | } |
||
4728 | /* BTF set -------------------------------------------------------------*/ |
||
4729 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4730 | { |
||
4731 | I2C_SlaveTransmit_BTF(hi2c); |
||
4732 | } |
||
4733 | else |
||
4734 | { |
||
4735 | /* Do nothing */ |
||
4736 | } |
||
4737 | } |
||
4738 | /* I2C in mode Receiver --------------------------------------------------*/ |
||
4739 | else |
||
4740 | { |
||
4741 | /* RXNE set and BTF reset ----------------------------------------------*/ |
||
4742 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
||
4743 | { |
||
4744 | I2C_SlaveReceive_RXNE(hi2c); |
||
4745 | } |
||
4746 | /* BTF set -------------------------------------------------------------*/ |
||
4747 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
||
4748 | { |
||
4749 | I2C_SlaveReceive_BTF(hi2c); |
||
4750 | } |
||
4751 | else |
||
4752 | { |
||
4753 | /* Do nothing */ |
||
4754 | } |
||
4755 | } |
||
4756 | } |
||
4757 | } |
||
4758 | |||
4759 | /** |
||
4760 | * @brief This function handles I2C error interrupt request. |
||
4761 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4762 | * the configuration information for the specified I2C. |
||
4763 | * @retval None |
||
4764 | */ |
||
4765 | void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) |
||
4766 | { |
||
4767 | HAL_I2C_ModeTypeDef tmp1; |
||
4768 | uint32_t tmp2; |
||
4769 | HAL_I2C_StateTypeDef tmp3; |
||
4770 | uint32_t tmp4; |
||
4771 | uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); |
||
4772 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
||
4773 | uint32_t error = HAL_I2C_ERROR_NONE; |
||
4774 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
4775 | |||
4776 | /* I2C Bus error interrupt occurred ----------------------------------------*/ |
||
4777 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
||
4778 | { |
||
4779 | error |= HAL_I2C_ERROR_BERR; |
||
4780 | |||
4781 | /* Clear BERR flag */ |
||
4782 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); |
||
4783 | } |
||
4784 | |||
4785 | /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ |
||
4786 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
||
4787 | { |
||
4788 | error |= HAL_I2C_ERROR_ARLO; |
||
4789 | |||
4790 | /* Clear ARLO flag */ |
||
4791 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); |
||
4792 | } |
||
4793 | |||
4794 | /* I2C Acknowledge failure error interrupt occurred ------------------------*/ |
||
4795 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
||
4796 | { |
||
4797 | tmp1 = CurrentMode; |
||
4798 | tmp2 = hi2c->XferCount; |
||
4799 | tmp3 = hi2c->State; |
||
4800 | tmp4 = hi2c->PreviousState; |
||
4801 | if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ |
||
4802 | ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ |
||
4803 | ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) |
||
4804 | { |
||
4805 | I2C_Slave_AF(hi2c); |
||
4806 | } |
||
4807 | else |
||
4808 | { |
||
4809 | /* Clear AF flag */ |
||
4810 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
4811 | |||
4812 | error |= HAL_I2C_ERROR_AF; |
||
4813 | |||
4814 | /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ |
||
4815 | if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) |
||
4816 | { |
||
4817 | /* Generate Stop */ |
||
4818 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
4819 | } |
||
4820 | } |
||
4821 | } |
||
4822 | |||
4823 | /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ |
||
4824 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
||
4825 | { |
||
4826 | error |= HAL_I2C_ERROR_OVR; |
||
4827 | /* Clear OVR flag */ |
||
4828 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); |
||
4829 | } |
||
4830 | |||
4831 | /* Call the Error Callback in case of Error detected -----------------------*/ |
||
4832 | if (error != HAL_I2C_ERROR_NONE) |
||
4833 | { |
||
4834 | hi2c->ErrorCode |= error; |
||
4835 | I2C_ITError(hi2c); |
||
4836 | } |
||
4837 | } |
||
4838 | |||
4839 | /** |
||
4840 | * @brief Master Tx Transfer completed callback. |
||
4841 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4842 | * the configuration information for the specified I2C. |
||
4843 | * @retval None |
||
4844 | */ |
||
4845 | __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
4846 | { |
||
4847 | /* Prevent unused argument(s) compilation warning */ |
||
4848 | UNUSED(hi2c); |
||
4849 | |||
4850 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4851 | the HAL_I2C_MasterTxCpltCallback could be implemented in the user file |
||
4852 | */ |
||
4853 | } |
||
4854 | |||
4855 | /** |
||
4856 | * @brief Master Rx Transfer completed callback. |
||
4857 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4858 | * the configuration information for the specified I2C. |
||
4859 | * @retval None |
||
4860 | */ |
||
4861 | __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
4862 | { |
||
4863 | /* Prevent unused argument(s) compilation warning */ |
||
4864 | UNUSED(hi2c); |
||
4865 | |||
4866 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4867 | the HAL_I2C_MasterRxCpltCallback could be implemented in the user file |
||
4868 | */ |
||
4869 | } |
||
4870 | |||
4871 | /** @brief Slave Tx Transfer completed callback. |
||
4872 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4873 | * the configuration information for the specified I2C. |
||
4874 | * @retval None |
||
4875 | */ |
||
4876 | __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
4877 | { |
||
4878 | /* Prevent unused argument(s) compilation warning */ |
||
4879 | UNUSED(hi2c); |
||
4880 | |||
4881 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4882 | the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file |
||
4883 | */ |
||
4884 | } |
||
4885 | |||
4886 | /** |
||
4887 | * @brief Slave Rx Transfer completed callback. |
||
4888 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4889 | * the configuration information for the specified I2C. |
||
4890 | * @retval None |
||
4891 | */ |
||
4892 | __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
4893 | { |
||
4894 | /* Prevent unused argument(s) compilation warning */ |
||
4895 | UNUSED(hi2c); |
||
4896 | |||
4897 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4898 | the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file |
||
4899 | */ |
||
4900 | } |
||
4901 | |||
4902 | /** |
||
4903 | * @brief Slave Address Match callback. |
||
4904 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4905 | * the configuration information for the specified I2C. |
||
4906 | * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition |
||
4907 | * @param AddrMatchCode Address Match Code |
||
4908 | * @retval None |
||
4909 | */ |
||
4910 | __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) |
||
4911 | { |
||
4912 | /* Prevent unused argument(s) compilation warning */ |
||
4913 | UNUSED(hi2c); |
||
4914 | UNUSED(TransferDirection); |
||
4915 | UNUSED(AddrMatchCode); |
||
4916 | |||
4917 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4918 | the HAL_I2C_AddrCallback() could be implemented in the user file |
||
4919 | */ |
||
4920 | } |
||
4921 | |||
4922 | /** |
||
4923 | * @brief Listen Complete callback. |
||
4924 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4925 | * the configuration information for the specified I2C. |
||
4926 | * @retval None |
||
4927 | */ |
||
4928 | __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) |
||
4929 | { |
||
4930 | /* Prevent unused argument(s) compilation warning */ |
||
4931 | UNUSED(hi2c); |
||
4932 | |||
4933 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4934 | the HAL_I2C_ListenCpltCallback() could be implemented in the user file |
||
4935 | */ |
||
4936 | } |
||
4937 | |||
4938 | /** |
||
4939 | * @brief Memory Tx Transfer completed callback. |
||
4940 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4941 | * the configuration information for the specified I2C. |
||
4942 | * @retval None |
||
4943 | */ |
||
4944 | __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
4945 | { |
||
4946 | /* Prevent unused argument(s) compilation warning */ |
||
4947 | UNUSED(hi2c); |
||
4948 | |||
4949 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4950 | the HAL_I2C_MemTxCpltCallback could be implemented in the user file |
||
4951 | */ |
||
4952 | } |
||
4953 | |||
4954 | /** |
||
4955 | * @brief Memory Rx Transfer completed callback. |
||
4956 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4957 | * the configuration information for the specified I2C. |
||
4958 | * @retval None |
||
4959 | */ |
||
4960 | __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) |
||
4961 | { |
||
4962 | /* Prevent unused argument(s) compilation warning */ |
||
4963 | UNUSED(hi2c); |
||
4964 | |||
4965 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4966 | the HAL_I2C_MemRxCpltCallback could be implemented in the user file |
||
4967 | */ |
||
4968 | } |
||
4969 | |||
4970 | /** |
||
4971 | * @brief I2C error callback. |
||
4972 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4973 | * the configuration information for the specified I2C. |
||
4974 | * @retval None |
||
4975 | */ |
||
4976 | __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) |
||
4977 | { |
||
4978 | /* Prevent unused argument(s) compilation warning */ |
||
4979 | UNUSED(hi2c); |
||
4980 | |||
4981 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4982 | the HAL_I2C_ErrorCallback could be implemented in the user file |
||
4983 | */ |
||
4984 | } |
||
4985 | |||
4986 | /** |
||
4987 | * @brief I2C abort callback. |
||
4988 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
4989 | * the configuration information for the specified I2C. |
||
4990 | * @retval None |
||
4991 | */ |
||
4992 | __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) |
||
4993 | { |
||
4994 | /* Prevent unused argument(s) compilation warning */ |
||
4995 | UNUSED(hi2c); |
||
4996 | |||
4997 | /* NOTE : This function should not be modified, when the callback is needed, |
||
4998 | the HAL_I2C_AbortCpltCallback could be implemented in the user file |
||
4999 | */ |
||
5000 | } |
||
5001 | |||
5002 | /** |
||
5003 | * @} |
||
5004 | */ |
||
5005 | |||
5006 | /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions |
||
5007 | * @brief Peripheral State, Mode and Error functions |
||
5008 | * |
||
5009 | @verbatim |
||
5010 | =============================================================================== |
||
5011 | ##### Peripheral State, Mode and Error functions ##### |
||
5012 | =============================================================================== |
||
5013 | [..] |
||
5014 | This subsection permit to get in run-time the status of the peripheral |
||
5015 | and the data flow. |
||
5016 | |||
5017 | @endverbatim |
||
5018 | * @{ |
||
5019 | */ |
||
5020 | |||
5021 | /** |
||
5022 | * @brief Return the I2C handle state. |
||
5023 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5024 | * the configuration information for the specified I2C. |
||
5025 | * @retval HAL state |
||
5026 | */ |
||
5027 | HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) |
||
5028 | { |
||
5029 | /* Return I2C handle state */ |
||
5030 | return hi2c->State; |
||
5031 | } |
||
5032 | |||
5033 | /** |
||
5034 | * @brief Returns the I2C Master, Slave, Memory or no mode. |
||
5035 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5036 | * the configuration information for I2C module |
||
5037 | * @retval HAL mode |
||
5038 | */ |
||
5039 | HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) |
||
5040 | { |
||
5041 | return hi2c->Mode; |
||
5042 | } |
||
5043 | |||
5044 | /** |
||
5045 | * @brief Return the I2C error code. |
||
5046 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5047 | * the configuration information for the specified I2C. |
||
5048 | * @retval I2C Error Code |
||
5049 | */ |
||
5050 | uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) |
||
5051 | { |
||
5052 | return hi2c->ErrorCode; |
||
5053 | } |
||
5054 | |||
5055 | /** |
||
5056 | * @} |
||
5057 | */ |
||
5058 | |||
5059 | /** |
||
5060 | * @} |
||
5061 | */ |
||
5062 | |||
5063 | /** @addtogroup I2C_Private_Functions |
||
5064 | * @{ |
||
5065 | */ |
||
5066 | |||
5067 | /** |
||
5068 | * @brief Handle TXE flag for Master |
||
5069 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5070 | * the configuration information for I2C module |
||
5071 | * @retval None |
||
5072 | */ |
||
5073 | static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) |
||
5074 | { |
||
5075 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5076 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
5077 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
5078 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
5079 | |||
5080 | if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
||
5081 | { |
||
5082 | /* Call TxCpltCallback() directly if no stop mode is set */ |
||
5083 | if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
||
5084 | { |
||
5085 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5086 | |||
5087 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
||
5088 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5089 | hi2c->State = HAL_I2C_STATE_READY; |
||
5090 | |||
5091 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5092 | hi2c->MasterTxCpltCallback(hi2c); |
||
5093 | #else |
||
5094 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
5095 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5096 | } |
||
5097 | else /* Generate Stop condition then Call TxCpltCallback() */ |
||
5098 | { |
||
5099 | /* Disable EVT, BUF and ERR interrupt */ |
||
5100 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5101 | |||
5102 | /* Generate Stop */ |
||
5103 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5104 | |||
5105 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5106 | hi2c->State = HAL_I2C_STATE_READY; |
||
5107 | |||
5108 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5109 | { |
||
5110 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5111 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5112 | hi2c->MemTxCpltCallback(hi2c); |
||
5113 | #else |
||
5114 | HAL_I2C_MemTxCpltCallback(hi2c); |
||
5115 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5116 | } |
||
5117 | else |
||
5118 | { |
||
5119 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5120 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5121 | hi2c->MasterTxCpltCallback(hi2c); |
||
5122 | #else |
||
5123 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
5124 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5125 | } |
||
5126 | } |
||
5127 | } |
||
5128 | else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ |
||
5129 | ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) |
||
5130 | { |
||
5131 | if (hi2c->XferCount == 0U) |
||
5132 | { |
||
5133 | /* Disable BUF interrupt */ |
||
5134 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5135 | } |
||
5136 | else |
||
5137 | { |
||
5138 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5139 | { |
||
5140 | I2C_MemoryTransmit_TXE_BTF(hi2c); |
||
5141 | } |
||
5142 | else |
||
5143 | { |
||
5144 | /* Write data to DR */ |
||
5145 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
5146 | |||
5147 | /* Increment Buffer pointer */ |
||
5148 | hi2c->pBuffPtr++; |
||
5149 | |||
5150 | /* Update counter */ |
||
5151 | hi2c->XferCount--; |
||
5152 | } |
||
5153 | } |
||
5154 | } |
||
5155 | else |
||
5156 | { |
||
5157 | /* Do nothing */ |
||
5158 | } |
||
5159 | } |
||
5160 | |||
5161 | /** |
||
5162 | * @brief Handle BTF flag for Master transmitter |
||
5163 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5164 | * the configuration information for I2C module |
||
5165 | * @retval None |
||
5166 | */ |
||
5167 | static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) |
||
5168 | { |
||
5169 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5170 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
5171 | |||
5172 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
||
5173 | { |
||
5174 | if (hi2c->XferCount != 0U) |
||
5175 | { |
||
5176 | /* Write data to DR */ |
||
5177 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
5178 | |||
5179 | /* Increment Buffer pointer */ |
||
5180 | hi2c->pBuffPtr++; |
||
5181 | |||
5182 | /* Update counter */ |
||
5183 | hi2c->XferCount--; |
||
5184 | } |
||
5185 | else |
||
5186 | { |
||
5187 | /* Call TxCpltCallback() directly if no stop mode is set */ |
||
5188 | if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
||
5189 | { |
||
5190 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5191 | |||
5192 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
||
5193 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5194 | hi2c->State = HAL_I2C_STATE_READY; |
||
5195 | |||
5196 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5197 | hi2c->MasterTxCpltCallback(hi2c); |
||
5198 | #else |
||
5199 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
5200 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5201 | } |
||
5202 | else /* Generate Stop condition then Call TxCpltCallback() */ |
||
5203 | { |
||
5204 | /* Disable EVT, BUF and ERR interrupt */ |
||
5205 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5206 | |||
5207 | /* Generate Stop */ |
||
5208 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5209 | |||
5210 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5211 | hi2c->State = HAL_I2C_STATE_READY; |
||
5212 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5213 | |||
5214 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5215 | hi2c->MasterTxCpltCallback(hi2c); |
||
5216 | #else |
||
5217 | HAL_I2C_MasterTxCpltCallback(hi2c); |
||
5218 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5219 | } |
||
5220 | } |
||
5221 | } |
||
5222 | else |
||
5223 | { |
||
5224 | /* Do nothing */ |
||
5225 | } |
||
5226 | } |
||
5227 | |||
5228 | /** |
||
5229 | * @brief Handle TXE and BTF flag for Memory transmitter |
||
5230 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5231 | * the configuration information for I2C module |
||
5232 | * @retval None |
||
5233 | */ |
||
5234 | static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) |
||
5235 | { |
||
5236 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5237 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
5238 | |||
5239 | if (hi2c->EventCount == 0U) |
||
5240 | { |
||
5241 | /* If Memory address size is 8Bit */ |
||
5242 | if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) |
||
5243 | { |
||
5244 | /* Send Memory Address */ |
||
5245 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
||
5246 | |||
5247 | hi2c->EventCount += 2U; |
||
5248 | } |
||
5249 | /* If Memory address size is 16Bit */ |
||
5250 | else |
||
5251 | { |
||
5252 | /* Send MSB of Memory Address */ |
||
5253 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); |
||
5254 | |||
5255 | hi2c->EventCount++; |
||
5256 | } |
||
5257 | } |
||
5258 | else if (hi2c->EventCount == 1U) |
||
5259 | { |
||
5260 | /* Send LSB of Memory Address */ |
||
5261 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
||
5262 | |||
5263 | hi2c->EventCount++; |
||
5264 | } |
||
5265 | else if (hi2c->EventCount == 2U) |
||
5266 | { |
||
5267 | if (CurrentState == HAL_I2C_STATE_BUSY_RX) |
||
5268 | { |
||
5269 | /* Generate Restart */ |
||
5270 | hi2c->Instance->CR1 |= I2C_CR1_START; |
||
5271 | } |
||
5272 | else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
||
5273 | { |
||
5274 | /* Write data to DR */ |
||
5275 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
5276 | |||
5277 | /* Increment Buffer pointer */ |
||
5278 | hi2c->pBuffPtr++; |
||
5279 | |||
5280 | /* Update counter */ |
||
5281 | hi2c->XferCount--; |
||
5282 | } |
||
5283 | else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
||
5284 | { |
||
5285 | /* Generate Stop condition then Call TxCpltCallback() */ |
||
5286 | /* Disable EVT, BUF and ERR interrupt */ |
||
5287 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5288 | |||
5289 | /* Generate Stop */ |
||
5290 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5291 | |||
5292 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5293 | hi2c->State = HAL_I2C_STATE_READY; |
||
5294 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5295 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5296 | hi2c->MemTxCpltCallback(hi2c); |
||
5297 | #else |
||
5298 | HAL_I2C_MemTxCpltCallback(hi2c); |
||
5299 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5300 | } |
||
5301 | else |
||
5302 | { |
||
5303 | /* Do nothing */ |
||
5304 | } |
||
5305 | } |
||
5306 | else |
||
5307 | { |
||
5308 | /* Do nothing */ |
||
5309 | } |
||
5310 | } |
||
5311 | |||
5312 | /** |
||
5313 | * @brief Handle RXNE flag for Master |
||
5314 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5315 | * the configuration information for I2C module |
||
5316 | * @retval None |
||
5317 | */ |
||
5318 | static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) |
||
5319 | { |
||
5320 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
||
5321 | { |
||
5322 | uint32_t tmp; |
||
5323 | |||
5324 | tmp = hi2c->XferCount; |
||
5325 | if (tmp > 3U) |
||
5326 | { |
||
5327 | /* Read data from DR */ |
||
5328 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5329 | |||
5330 | /* Increment Buffer pointer */ |
||
5331 | hi2c->pBuffPtr++; |
||
5332 | |||
5333 | /* Update counter */ |
||
5334 | hi2c->XferCount--; |
||
5335 | |||
5336 | if (hi2c->XferCount == (uint16_t)3) |
||
5337 | { |
||
5338 | /* Disable BUF interrupt, this help to treat correctly the last 4 bytes |
||
5339 | on BTF subroutine */ |
||
5340 | /* Disable BUF interrupt */ |
||
5341 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5342 | } |
||
5343 | } |
||
5344 | else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) |
||
5345 | { |
||
5346 | if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) |
||
5347 | { |
||
5348 | /* Disable Acknowledge */ |
||
5349 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5350 | |||
5351 | /* Disable EVT, BUF and ERR interrupt */ |
||
5352 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5353 | |||
5354 | /* Read data from DR */ |
||
5355 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5356 | |||
5357 | /* Increment Buffer pointer */ |
||
5358 | hi2c->pBuffPtr++; |
||
5359 | |||
5360 | /* Update counter */ |
||
5361 | hi2c->XferCount--; |
||
5362 | |||
5363 | hi2c->State = HAL_I2C_STATE_READY; |
||
5364 | |||
5365 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5366 | { |
||
5367 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5368 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5369 | |||
5370 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5371 | hi2c->MemRxCpltCallback(hi2c); |
||
5372 | #else |
||
5373 | HAL_I2C_MemRxCpltCallback(hi2c); |
||
5374 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5375 | } |
||
5376 | else |
||
5377 | { |
||
5378 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5379 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
||
5380 | |||
5381 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5382 | hi2c->MasterRxCpltCallback(hi2c); |
||
5383 | #else |
||
5384 | HAL_I2C_MasterRxCpltCallback(hi2c); |
||
5385 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5386 | } |
||
5387 | } |
||
5388 | else |
||
5389 | { |
||
5390 | /* Disable EVT, BUF and ERR interrupt */ |
||
5391 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5392 | |||
5393 | /* Read data from DR */ |
||
5394 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5395 | |||
5396 | /* Increment Buffer pointer */ |
||
5397 | hi2c->pBuffPtr++; |
||
5398 | |||
5399 | /* Update counter */ |
||
5400 | hi2c->XferCount--; |
||
5401 | |||
5402 | hi2c->State = HAL_I2C_STATE_READY; |
||
5403 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5404 | |||
5405 | /* Call user error callback */ |
||
5406 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5407 | hi2c->ErrorCallback(hi2c); |
||
5408 | #else |
||
5409 | HAL_I2C_ErrorCallback(hi2c); |
||
5410 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5411 | } |
||
5412 | } |
||
5413 | else |
||
5414 | { |
||
5415 | /* Do nothing */ |
||
5416 | } |
||
5417 | } |
||
5418 | } |
||
5419 | |||
5420 | /** |
||
5421 | * @brief Handle BTF flag for Master receiver |
||
5422 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5423 | * the configuration information for I2C module |
||
5424 | * @retval None |
||
5425 | */ |
||
5426 | static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) |
||
5427 | { |
||
5428 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5429 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
5430 | |||
5431 | if (hi2c->XferCount == 4U) |
||
5432 | { |
||
5433 | /* Disable BUF interrupt, this help to treat correctly the last 2 bytes |
||
5434 | on BTF subroutine if there is a reception delay between N-1 and N byte */ |
||
5435 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5436 | |||
5437 | /* Read data from DR */ |
||
5438 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5439 | |||
5440 | /* Increment Buffer pointer */ |
||
5441 | hi2c->pBuffPtr++; |
||
5442 | |||
5443 | /* Update counter */ |
||
5444 | hi2c->XferCount--; |
||
5445 | } |
||
5446 | else if (hi2c->XferCount == 3U) |
||
5447 | { |
||
5448 | /* Disable BUF interrupt, this help to treat correctly the last 2 bytes |
||
5449 | on BTF subroutine if there is a reception delay between N-1 and N byte */ |
||
5450 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5451 | |||
5452 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) |
||
5453 | { |
||
5454 | /* Disable Acknowledge */ |
||
5455 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5456 | } |
||
5457 | |||
5458 | /* Read data from DR */ |
||
5459 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5460 | |||
5461 | /* Increment Buffer pointer */ |
||
5462 | hi2c->pBuffPtr++; |
||
5463 | |||
5464 | /* Update counter */ |
||
5465 | hi2c->XferCount--; |
||
5466 | } |
||
5467 | else if (hi2c->XferCount == 2U) |
||
5468 | { |
||
5469 | /* Prepare next transfer or stop current transfer */ |
||
5470 | if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) |
||
5471 | { |
||
5472 | /* Disable Acknowledge */ |
||
5473 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5474 | } |
||
5475 | else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) |
||
5476 | { |
||
5477 | /* Enable Acknowledge */ |
||
5478 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5479 | } |
||
5480 | else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP) |
||
5481 | { |
||
5482 | /* Generate Stop */ |
||
5483 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5484 | } |
||
5485 | else |
||
5486 | { |
||
5487 | /* Do nothing */ |
||
5488 | } |
||
5489 | |||
5490 | /* Read data from DR */ |
||
5491 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5492 | |||
5493 | /* Increment Buffer pointer */ |
||
5494 | hi2c->pBuffPtr++; |
||
5495 | |||
5496 | /* Update counter */ |
||
5497 | hi2c->XferCount--; |
||
5498 | |||
5499 | /* Read data from DR */ |
||
5500 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5501 | |||
5502 | /* Increment Buffer pointer */ |
||
5503 | hi2c->pBuffPtr++; |
||
5504 | |||
5505 | /* Update counter */ |
||
5506 | hi2c->XferCount--; |
||
5507 | |||
5508 | /* Disable EVT and ERR interrupt */ |
||
5509 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
5510 | |||
5511 | hi2c->State = HAL_I2C_STATE_READY; |
||
5512 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5513 | { |
||
5514 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5515 | hi2c->PreviousState = I2C_STATE_NONE; |
||
5516 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5517 | hi2c->MemRxCpltCallback(hi2c); |
||
5518 | #else |
||
5519 | HAL_I2C_MemRxCpltCallback(hi2c); |
||
5520 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5521 | } |
||
5522 | else |
||
5523 | { |
||
5524 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
5525 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
||
5526 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5527 | hi2c->MasterRxCpltCallback(hi2c); |
||
5528 | #else |
||
5529 | HAL_I2C_MasterRxCpltCallback(hi2c); |
||
5530 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5531 | } |
||
5532 | } |
||
5533 | else |
||
5534 | { |
||
5535 | /* Read data from DR */ |
||
5536 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5537 | |||
5538 | /* Increment Buffer pointer */ |
||
5539 | hi2c->pBuffPtr++; |
||
5540 | |||
5541 | /* Update counter */ |
||
5542 | hi2c->XferCount--; |
||
5543 | } |
||
5544 | } |
||
5545 | |||
5546 | /** |
||
5547 | * @brief Handle SB flag for Master |
||
5548 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5549 | * the configuration information for I2C module |
||
5550 | * @retval None |
||
5551 | */ |
||
5552 | static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) |
||
5553 | { |
||
5554 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
5555 | { |
||
5556 | if (hi2c->EventCount == 0U) |
||
5557 | { |
||
5558 | /* Send slave address */ |
||
5559 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
||
5560 | } |
||
5561 | else |
||
5562 | { |
||
5563 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
||
5564 | } |
||
5565 | } |
||
5566 | else |
||
5567 | { |
||
5568 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
||
5569 | { |
||
5570 | /* Send slave 7 Bits address */ |
||
5571 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
||
5572 | { |
||
5573 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
||
5574 | } |
||
5575 | else |
||
5576 | { |
||
5577 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
||
5578 | } |
||
5579 | |||
5580 | if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) |
||
5581 | || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) |
||
5582 | { |
||
5583 | /* Enable DMA Request */ |
||
5584 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
5585 | } |
||
5586 | } |
||
5587 | else |
||
5588 | { |
||
5589 | if (hi2c->EventCount == 0U) |
||
5590 | { |
||
5591 | /* Send header of slave address */ |
||
5592 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); |
||
5593 | } |
||
5594 | else if (hi2c->EventCount == 1U) |
||
5595 | { |
||
5596 | /* Send header of slave address */ |
||
5597 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); |
||
5598 | } |
||
5599 | else |
||
5600 | { |
||
5601 | /* Do nothing */ |
||
5602 | } |
||
5603 | } |
||
5604 | } |
||
5605 | } |
||
5606 | |||
5607 | /** |
||
5608 | * @brief Handle ADD10 flag for Master |
||
5609 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5610 | * the configuration information for I2C module |
||
5611 | * @retval None |
||
5612 | */ |
||
5613 | static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) |
||
5614 | { |
||
5615 | /* Send slave address */ |
||
5616 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); |
||
5617 | |||
5618 | if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL)) |
||
5619 | { |
||
5620 | if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL)) |
||
5621 | { |
||
5622 | /* Enable DMA Request */ |
||
5623 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
5624 | } |
||
5625 | } |
||
5626 | } |
||
5627 | |||
5628 | /** |
||
5629 | * @brief Handle ADDR flag for Master |
||
5630 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5631 | * the configuration information for I2C module |
||
5632 | * @retval None |
||
5633 | */ |
||
5634 | static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) |
||
5635 | { |
||
5636 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
5637 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
5638 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
5639 | uint32_t Prev_State = hi2c->PreviousState; |
||
5640 | |||
5641 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
||
5642 | { |
||
5643 | if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) |
||
5644 | { |
||
5645 | /* Clear ADDR flag */ |
||
5646 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5647 | } |
||
5648 | else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) |
||
5649 | { |
||
5650 | /* Clear ADDR flag */ |
||
5651 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5652 | |||
5653 | /* Generate Restart */ |
||
5654 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
5655 | |||
5656 | hi2c->EventCount++; |
||
5657 | } |
||
5658 | else |
||
5659 | { |
||
5660 | if (hi2c->XferCount == 0U) |
||
5661 | { |
||
5662 | /* Clear ADDR flag */ |
||
5663 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5664 | |||
5665 | /* Generate Stop */ |
||
5666 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5667 | } |
||
5668 | else if (hi2c->XferCount == 1U) |
||
5669 | { |
||
5670 | if (CurrentXferOptions == I2C_NO_OPTION_FRAME) |
||
5671 | { |
||
5672 | /* Disable Acknowledge */ |
||
5673 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5674 | |||
5675 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
5676 | { |
||
5677 | /* Disable Acknowledge */ |
||
5678 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5679 | |||
5680 | /* Clear ADDR flag */ |
||
5681 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5682 | } |
||
5683 | else |
||
5684 | { |
||
5685 | /* Clear ADDR flag */ |
||
5686 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5687 | |||
5688 | /* Generate Stop */ |
||
5689 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5690 | } |
||
5691 | } |
||
5692 | /* Prepare next transfer or stop current transfer */ |
||
5693 | else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ |
||
5694 | && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) |
||
5695 | { |
||
5696 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) |
||
5697 | { |
||
5698 | /* Disable Acknowledge */ |
||
5699 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5700 | } |
||
5701 | else |
||
5702 | { |
||
5703 | /* Enable Acknowledge */ |
||
5704 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5705 | } |
||
5706 | |||
5707 | /* Clear ADDR flag */ |
||
5708 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5709 | } |
||
5710 | else |
||
5711 | { |
||
5712 | /* Disable Acknowledge */ |
||
5713 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5714 | |||
5715 | /* Clear ADDR flag */ |
||
5716 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5717 | |||
5718 | /* Generate Stop */ |
||
5719 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
5720 | } |
||
5721 | } |
||
5722 | else if (hi2c->XferCount == 2U) |
||
5723 | { |
||
5724 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) |
||
5725 | { |
||
5726 | /* Disable Acknowledge */ |
||
5727 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5728 | |||
5729 | /* Enable Pos */ |
||
5730 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
||
5731 | } |
||
5732 | else |
||
5733 | { |
||
5734 | /* Enable Acknowledge */ |
||
5735 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5736 | } |
||
5737 | |||
5738 | if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) |
||
5739 | { |
||
5740 | /* Enable Last DMA bit */ |
||
5741 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
5742 | } |
||
5743 | |||
5744 | /* Clear ADDR flag */ |
||
5745 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5746 | } |
||
5747 | else |
||
5748 | { |
||
5749 | /* Enable Acknowledge */ |
||
5750 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5751 | |||
5752 | if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) |
||
5753 | { |
||
5754 | /* Enable Last DMA bit */ |
||
5755 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
5756 | } |
||
5757 | |||
5758 | /* Clear ADDR flag */ |
||
5759 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5760 | } |
||
5761 | |||
5762 | /* Reset Event counter */ |
||
5763 | hi2c->EventCount = 0U; |
||
5764 | } |
||
5765 | } |
||
5766 | else |
||
5767 | { |
||
5768 | /* Clear ADDR flag */ |
||
5769 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
5770 | } |
||
5771 | } |
||
5772 | |||
5773 | /** |
||
5774 | * @brief Handle TXE flag for Slave |
||
5775 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5776 | * the configuration information for I2C module |
||
5777 | * @retval None |
||
5778 | */ |
||
5779 | static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) |
||
5780 | { |
||
5781 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5782 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
5783 | |||
5784 | if (hi2c->XferCount != 0U) |
||
5785 | { |
||
5786 | /* Write data to DR */ |
||
5787 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
5788 | |||
5789 | /* Increment Buffer pointer */ |
||
5790 | hi2c->pBuffPtr++; |
||
5791 | |||
5792 | /* Update counter */ |
||
5793 | hi2c->XferCount--; |
||
5794 | |||
5795 | if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
||
5796 | { |
||
5797 | /* Last Byte is received, disable Interrupt */ |
||
5798 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5799 | |||
5800 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
5801 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
||
5802 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
5803 | |||
5804 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
5805 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5806 | hi2c->SlaveTxCpltCallback(hi2c); |
||
5807 | #else |
||
5808 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
||
5809 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5810 | } |
||
5811 | } |
||
5812 | } |
||
5813 | |||
5814 | /** |
||
5815 | * @brief Handle BTF flag for Slave transmitter |
||
5816 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5817 | * the configuration information for I2C module |
||
5818 | * @retval None |
||
5819 | */ |
||
5820 | static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) |
||
5821 | { |
||
5822 | if (hi2c->XferCount != 0U) |
||
5823 | { |
||
5824 | /* Write data to DR */ |
||
5825 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
||
5826 | |||
5827 | /* Increment Buffer pointer */ |
||
5828 | hi2c->pBuffPtr++; |
||
5829 | |||
5830 | /* Update counter */ |
||
5831 | hi2c->XferCount--; |
||
5832 | } |
||
5833 | } |
||
5834 | |||
5835 | /** |
||
5836 | * @brief Handle RXNE flag for Slave |
||
5837 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5838 | * the configuration information for I2C module |
||
5839 | * @retval None |
||
5840 | */ |
||
5841 | static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) |
||
5842 | { |
||
5843 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
5844 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
5845 | |||
5846 | if (hi2c->XferCount != 0U) |
||
5847 | { |
||
5848 | /* Read data from DR */ |
||
5849 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5850 | |||
5851 | /* Increment Buffer pointer */ |
||
5852 | hi2c->pBuffPtr++; |
||
5853 | |||
5854 | /* Update counter */ |
||
5855 | hi2c->XferCount--; |
||
5856 | |||
5857 | if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
||
5858 | { |
||
5859 | /* Last Byte is received, disable Interrupt */ |
||
5860 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
||
5861 | |||
5862 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
5863 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
||
5864 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
5865 | |||
5866 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
5867 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5868 | hi2c->SlaveRxCpltCallback(hi2c); |
||
5869 | #else |
||
5870 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
5871 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5872 | } |
||
5873 | } |
||
5874 | } |
||
5875 | |||
5876 | /** |
||
5877 | * @brief Handle BTF flag for Slave receiver |
||
5878 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5879 | * the configuration information for I2C module |
||
5880 | * @retval None |
||
5881 | */ |
||
5882 | static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) |
||
5883 | { |
||
5884 | if (hi2c->XferCount != 0U) |
||
5885 | { |
||
5886 | /* Read data from DR */ |
||
5887 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
5888 | |||
5889 | /* Increment Buffer pointer */ |
||
5890 | hi2c->pBuffPtr++; |
||
5891 | |||
5892 | /* Update counter */ |
||
5893 | hi2c->XferCount--; |
||
5894 | } |
||
5895 | } |
||
5896 | |||
5897 | /** |
||
5898 | * @brief Handle ADD flag for Slave |
||
5899 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5900 | * the configuration information for I2C module |
||
5901 | * @param IT2Flags Interrupt2 flags to handle. |
||
5902 | * @retval None |
||
5903 | */ |
||
5904 | static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) |
||
5905 | { |
||
5906 | uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; |
||
5907 | uint16_t SlaveAddrCode; |
||
5908 | |||
5909 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
5910 | { |
||
5911 | /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ |
||
5912 | __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); |
||
5913 | |||
5914 | /* Transfer Direction requested by Master */ |
||
5915 | if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) |
||
5916 | { |
||
5917 | TransferDirection = I2C_DIRECTION_TRANSMIT; |
||
5918 | } |
||
5919 | |||
5920 | if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) |
||
5921 | { |
||
5922 | SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; |
||
5923 | } |
||
5924 | else |
||
5925 | { |
||
5926 | SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; |
||
5927 | } |
||
5928 | |||
5929 | /* Process Unlocked */ |
||
5930 | __HAL_UNLOCK(hi2c); |
||
5931 | |||
5932 | /* Call Slave Addr callback */ |
||
5933 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
5934 | hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); |
||
5935 | #else |
||
5936 | HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); |
||
5937 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
5938 | } |
||
5939 | else |
||
5940 | { |
||
5941 | /* Clear ADDR flag */ |
||
5942 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
||
5943 | |||
5944 | /* Process Unlocked */ |
||
5945 | __HAL_UNLOCK(hi2c); |
||
5946 | } |
||
5947 | } |
||
5948 | |||
5949 | /** |
||
5950 | * @brief Handle STOPF flag for Slave |
||
5951 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
5952 | * the configuration information for I2C module |
||
5953 | * @retval None |
||
5954 | */ |
||
5955 | static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) |
||
5956 | { |
||
5957 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
5958 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
5959 | |||
5960 | /* Disable EVT, BUF and ERR interrupt */ |
||
5961 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
5962 | |||
5963 | /* Clear STOPF flag */ |
||
5964 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
||
5965 | |||
5966 | /* Disable Acknowledge */ |
||
5967 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
5968 | |||
5969 | /* If a DMA is ongoing, Update handle size context */ |
||
5970 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
5971 | { |
||
5972 | if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
||
5973 | { |
||
5974 | hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx)); |
||
5975 | |||
5976 | if (hi2c->XferCount != 0U) |
||
5977 | { |
||
5978 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
||
5979 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
5980 | } |
||
5981 | |||
5982 | /* Disable, stop the current DMA */ |
||
5983 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
5984 | |||
5985 | /* Abort DMA Xfer if any */ |
||
5986 | if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) |
||
5987 | { |
||
5988 | /* Set the I2C DMA Abort callback : |
||
5989 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
5990 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
||
5991 | |||
5992 | /* Abort DMA RX */ |
||
5993 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
||
5994 | { |
||
5995 | /* Call Directly XferAbortCallback function in case of error */ |
||
5996 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
||
5997 | } |
||
5998 | } |
||
5999 | } |
||
6000 | else |
||
6001 | { |
||
6002 | hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx)); |
||
6003 | |||
6004 | if (hi2c->XferCount != 0U) |
||
6005 | { |
||
6006 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
||
6007 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
6008 | } |
||
6009 | |||
6010 | /* Disable, stop the current DMA */ |
||
6011 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
6012 | |||
6013 | /* Abort DMA Xfer if any */ |
||
6014 | if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) |
||
6015 | { |
||
6016 | /* Set the I2C DMA Abort callback : |
||
6017 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
6018 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
||
6019 | |||
6020 | /* Abort DMA TX */ |
||
6021 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
||
6022 | { |
||
6023 | /* Call Directly XferAbortCallback function in case of error */ |
||
6024 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
||
6025 | } |
||
6026 | } |
||
6027 | } |
||
6028 | } |
||
6029 | |||
6030 | /* All data are not transferred, so set error code accordingly */ |
||
6031 | if (hi2c->XferCount != 0U) |
||
6032 | { |
||
6033 | /* Store Last receive data if any */ |
||
6034 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
||
6035 | { |
||
6036 | /* Read data from DR */ |
||
6037 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6038 | |||
6039 | /* Increment Buffer pointer */ |
||
6040 | hi2c->pBuffPtr++; |
||
6041 | |||
6042 | /* Update counter */ |
||
6043 | hi2c->XferCount--; |
||
6044 | } |
||
6045 | |||
6046 | /* Store Last receive data if any */ |
||
6047 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
6048 | { |
||
6049 | /* Read data from DR */ |
||
6050 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6051 | |||
6052 | /* Increment Buffer pointer */ |
||
6053 | hi2c->pBuffPtr++; |
||
6054 | |||
6055 | /* Update counter */ |
||
6056 | hi2c->XferCount--; |
||
6057 | } |
||
6058 | |||
6059 | if (hi2c->XferCount != 0U) |
||
6060 | { |
||
6061 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
||
6062 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
6063 | } |
||
6064 | } |
||
6065 | |||
6066 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
6067 | { |
||
6068 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6069 | I2C_ITError(hi2c); |
||
6070 | } |
||
6071 | else |
||
6072 | { |
||
6073 | if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) |
||
6074 | { |
||
6075 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
6076 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6077 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
6078 | |||
6079 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6080 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6081 | hi2c->SlaveRxCpltCallback(hi2c); |
||
6082 | #else |
||
6083 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
6084 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6085 | } |
||
6086 | |||
6087 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
||
6088 | { |
||
6089 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
6090 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6091 | hi2c->State = HAL_I2C_STATE_READY; |
||
6092 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6093 | |||
6094 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
||
6095 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6096 | hi2c->ListenCpltCallback(hi2c); |
||
6097 | #else |
||
6098 | HAL_I2C_ListenCpltCallback(hi2c); |
||
6099 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6100 | } |
||
6101 | else |
||
6102 | { |
||
6103 | if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) |
||
6104 | { |
||
6105 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6106 | hi2c->State = HAL_I2C_STATE_READY; |
||
6107 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6108 | |||
6109 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6110 | hi2c->SlaveRxCpltCallback(hi2c); |
||
6111 | #else |
||
6112 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
6113 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6114 | } |
||
6115 | } |
||
6116 | } |
||
6117 | } |
||
6118 | |||
6119 | /** |
||
6120 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6121 | * the configuration information for I2C module |
||
6122 | * @retval None |
||
6123 | */ |
||
6124 | static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) |
||
6125 | { |
||
6126 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
||
6127 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
6128 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
6129 | |||
6130 | if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ |
||
6131 | (CurrentState == HAL_I2C_STATE_LISTEN)) |
||
6132 | { |
||
6133 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
6134 | |||
6135 | /* Disable EVT, BUF and ERR interrupt */ |
||
6136 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
6137 | |||
6138 | /* Clear AF flag */ |
||
6139 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
6140 | |||
6141 | /* Disable Acknowledge */ |
||
6142 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6143 | |||
6144 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6145 | hi2c->State = HAL_I2C_STATE_READY; |
||
6146 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6147 | |||
6148 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
||
6149 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6150 | hi2c->ListenCpltCallback(hi2c); |
||
6151 | #else |
||
6152 | HAL_I2C_ListenCpltCallback(hi2c); |
||
6153 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6154 | } |
||
6155 | else if (CurrentState == HAL_I2C_STATE_BUSY_TX) |
||
6156 | { |
||
6157 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
6158 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
||
6159 | hi2c->State = HAL_I2C_STATE_READY; |
||
6160 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6161 | |||
6162 | /* Disable EVT, BUF and ERR interrupt */ |
||
6163 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
6164 | |||
6165 | /* Clear AF flag */ |
||
6166 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
6167 | |||
6168 | /* Disable Acknowledge */ |
||
6169 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6170 | |||
6171 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6172 | hi2c->SlaveTxCpltCallback(hi2c); |
||
6173 | #else |
||
6174 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
||
6175 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6176 | } |
||
6177 | else |
||
6178 | { |
||
6179 | /* Clear AF flag only */ |
||
6180 | /* State Listen, but XferOptions == FIRST or NEXT */ |
||
6181 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
6182 | } |
||
6183 | } |
||
6184 | |||
6185 | /** |
||
6186 | * @brief I2C interrupts error process |
||
6187 | * @param hi2c I2C handle. |
||
6188 | * @retval None |
||
6189 | */ |
||
6190 | static void I2C_ITError(I2C_HandleTypeDef *hi2c) |
||
6191 | { |
||
6192 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
6193 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
6194 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
6195 | uint32_t CurrentError; |
||
6196 | |||
6197 | if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) |
||
6198 | { |
||
6199 | /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ |
||
6200 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
||
6201 | } |
||
6202 | |||
6203 | if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
6204 | { |
||
6205 | /* keep HAL_I2C_STATE_LISTEN */ |
||
6206 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6207 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
6208 | } |
||
6209 | else |
||
6210 | { |
||
6211 | /* If state is an abort treatment on going, don't change state */ |
||
6212 | /* This change will be do later */ |
||
6213 | if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) |
||
6214 | { |
||
6215 | hi2c->State = HAL_I2C_STATE_READY; |
||
6216 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6217 | } |
||
6218 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6219 | } |
||
6220 | |||
6221 | /* Abort DMA transfer */ |
||
6222 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
||
6223 | { |
||
6224 | hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; |
||
6225 | |||
6226 | if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) |
||
6227 | { |
||
6228 | /* Set the DMA Abort callback : |
||
6229 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
6230 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
||
6231 | |||
6232 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
||
6233 | { |
||
6234 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
6235 | __HAL_I2C_DISABLE(hi2c); |
||
6236 | |||
6237 | hi2c->State = HAL_I2C_STATE_READY; |
||
6238 | |||
6239 | /* Call Directly XferAbortCallback function in case of error */ |
||
6240 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
||
6241 | } |
||
6242 | } |
||
6243 | else |
||
6244 | { |
||
6245 | /* Set the DMA Abort callback : |
||
6246 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
||
6247 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
||
6248 | |||
6249 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
||
6250 | { |
||
6251 | /* Store Last receive data if any */ |
||
6252 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
6253 | { |
||
6254 | /* Read data from DR */ |
||
6255 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6256 | |||
6257 | /* Increment Buffer pointer */ |
||
6258 | hi2c->pBuffPtr++; |
||
6259 | } |
||
6260 | |||
6261 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
6262 | __HAL_I2C_DISABLE(hi2c); |
||
6263 | |||
6264 | hi2c->State = HAL_I2C_STATE_READY; |
||
6265 | |||
6266 | /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ |
||
6267 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
||
6268 | } |
||
6269 | } |
||
6270 | } |
||
6271 | else if (hi2c->State == HAL_I2C_STATE_ABORT) |
||
6272 | { |
||
6273 | hi2c->State = HAL_I2C_STATE_READY; |
||
6274 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
6275 | |||
6276 | /* Store Last receive data if any */ |
||
6277 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
6278 | { |
||
6279 | /* Read data from DR */ |
||
6280 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6281 | |||
6282 | /* Increment Buffer pointer */ |
||
6283 | hi2c->pBuffPtr++; |
||
6284 | } |
||
6285 | |||
6286 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
6287 | __HAL_I2C_DISABLE(hi2c); |
||
6288 | |||
6289 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6290 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6291 | hi2c->AbortCpltCallback(hi2c); |
||
6292 | #else |
||
6293 | HAL_I2C_AbortCpltCallback(hi2c); |
||
6294 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6295 | } |
||
6296 | else |
||
6297 | { |
||
6298 | /* Store Last receive data if any */ |
||
6299 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
||
6300 | { |
||
6301 | /* Read data from DR */ |
||
6302 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
||
6303 | |||
6304 | /* Increment Buffer pointer */ |
||
6305 | hi2c->pBuffPtr++; |
||
6306 | } |
||
6307 | |||
6308 | /* Call user error callback */ |
||
6309 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6310 | hi2c->ErrorCallback(hi2c); |
||
6311 | #else |
||
6312 | HAL_I2C_ErrorCallback(hi2c); |
||
6313 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6314 | } |
||
6315 | |||
6316 | /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ |
||
6317 | CurrentError = hi2c->ErrorCode; |
||
6318 | |||
6319 | if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ |
||
6320 | ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ |
||
6321 | ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ |
||
6322 | ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) |
||
6323 | { |
||
6324 | /* Disable EVT, BUF and ERR interrupt */ |
||
6325 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
||
6326 | } |
||
6327 | |||
6328 | /* So may inform upper layer that listen phase is stopped */ |
||
6329 | /* during NACK error treatment */ |
||
6330 | CurrentState = hi2c->State; |
||
6331 | if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) |
||
6332 | { |
||
6333 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
||
6334 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6335 | hi2c->State = HAL_I2C_STATE_READY; |
||
6336 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6337 | |||
6338 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
||
6339 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6340 | hi2c->ListenCpltCallback(hi2c); |
||
6341 | #else |
||
6342 | HAL_I2C_ListenCpltCallback(hi2c); |
||
6343 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6344 | } |
||
6345 | } |
||
6346 | |||
6347 | /** |
||
6348 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6349 | * the configuration information for I2C module |
||
6350 | * @param DevAddress Target device address: The device 7 bits address value |
||
6351 | * in datasheet must be shifted to the left before calling the interface |
||
6352 | * @param Timeout Timeout duration |
||
6353 | * @param Tickstart Tick start value |
||
6354 | * @retval HAL status |
||
6355 | */ |
||
6356 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
||
6357 | { |
||
6358 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
6359 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
6360 | |||
6361 | /* Generate Start condition if first transfer */ |
||
6362 | if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
||
6363 | { |
||
6364 | /* Generate Start */ |
||
6365 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6366 | } |
||
6367 | else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) |
||
6368 | { |
||
6369 | /* Generate ReStart */ |
||
6370 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6371 | } |
||
6372 | else |
||
6373 | { |
||
6374 | /* Do nothing */ |
||
6375 | } |
||
6376 | |||
6377 | /* Wait until SB flag is set */ |
||
6378 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6379 | { |
||
6380 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6381 | { |
||
6382 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6383 | } |
||
6384 | return HAL_TIMEOUT; |
||
6385 | } |
||
6386 | |||
6387 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
||
6388 | { |
||
6389 | /* Send slave address */ |
||
6390 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
6391 | } |
||
6392 | else |
||
6393 | { |
||
6394 | /* Send header of slave address */ |
||
6395 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
||
6396 | |||
6397 | /* Wait until ADD10 flag is set */ |
||
6398 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
||
6399 | { |
||
6400 | return HAL_ERROR; |
||
6401 | } |
||
6402 | |||
6403 | /* Send slave address */ |
||
6404 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
||
6405 | } |
||
6406 | |||
6407 | /* Wait until ADDR flag is set */ |
||
6408 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6409 | { |
||
6410 | return HAL_ERROR; |
||
6411 | } |
||
6412 | |||
6413 | return HAL_OK; |
||
6414 | } |
||
6415 | |||
6416 | /** |
||
6417 | * @brief Master sends target device address for read request. |
||
6418 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6419 | * the configuration information for I2C module |
||
6420 | * @param DevAddress Target device address: The device 7 bits address value |
||
6421 | * in datasheet must be shifted to the left before calling the interface |
||
6422 | * @param Timeout Timeout duration |
||
6423 | * @param Tickstart Tick start value |
||
6424 | * @retval HAL status |
||
6425 | */ |
||
6426 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
||
6427 | { |
||
6428 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
6429 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
6430 | |||
6431 | /* Enable Acknowledge */ |
||
6432 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6433 | |||
6434 | /* Generate Start condition if first transfer */ |
||
6435 | if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
||
6436 | { |
||
6437 | /* Generate Start */ |
||
6438 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6439 | } |
||
6440 | else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) |
||
6441 | { |
||
6442 | /* Generate ReStart */ |
||
6443 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6444 | } |
||
6445 | else |
||
6446 | { |
||
6447 | /* Do nothing */ |
||
6448 | } |
||
6449 | |||
6450 | /* Wait until SB flag is set */ |
||
6451 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6452 | { |
||
6453 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6454 | { |
||
6455 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6456 | } |
||
6457 | return HAL_TIMEOUT; |
||
6458 | } |
||
6459 | |||
6460 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
||
6461 | { |
||
6462 | /* Send slave address */ |
||
6463 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
||
6464 | } |
||
6465 | else |
||
6466 | { |
||
6467 | /* Send header of slave address */ |
||
6468 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
||
6469 | |||
6470 | /* Wait until ADD10 flag is set */ |
||
6471 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
||
6472 | { |
||
6473 | return HAL_ERROR; |
||
6474 | } |
||
6475 | |||
6476 | /* Send slave address */ |
||
6477 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
||
6478 | |||
6479 | /* Wait until ADDR flag is set */ |
||
6480 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6481 | { |
||
6482 | return HAL_ERROR; |
||
6483 | } |
||
6484 | |||
6485 | /* Clear ADDR flag */ |
||
6486 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6487 | |||
6488 | /* Generate Restart */ |
||
6489 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6490 | |||
6491 | /* Wait until SB flag is set */ |
||
6492 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6493 | { |
||
6494 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6495 | { |
||
6496 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6497 | } |
||
6498 | return HAL_TIMEOUT; |
||
6499 | } |
||
6500 | |||
6501 | /* Send header of slave address */ |
||
6502 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); |
||
6503 | } |
||
6504 | |||
6505 | /* Wait until ADDR flag is set */ |
||
6506 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6507 | { |
||
6508 | return HAL_ERROR; |
||
6509 | } |
||
6510 | |||
6511 | return HAL_OK; |
||
6512 | } |
||
6513 | |||
6514 | /** |
||
6515 | * @brief Master sends target device address followed by internal memory address for write request. |
||
6516 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6517 | * the configuration information for I2C module |
||
6518 | * @param DevAddress Target device address: The device 7 bits address value |
||
6519 | * in datasheet must be shifted to the left before calling the interface |
||
6520 | * @param MemAddress Internal memory address |
||
6521 | * @param MemAddSize Size of internal memory address |
||
6522 | * @param Timeout Timeout duration |
||
6523 | * @param Tickstart Tick start value |
||
6524 | * @retval HAL status |
||
6525 | */ |
||
6526 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
||
6527 | { |
||
6528 | /* Generate Start */ |
||
6529 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6530 | |||
6531 | /* Wait until SB flag is set */ |
||
6532 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6533 | { |
||
6534 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6535 | { |
||
6536 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6537 | } |
||
6538 | return HAL_TIMEOUT; |
||
6539 | } |
||
6540 | |||
6541 | /* Send slave address */ |
||
6542 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
6543 | |||
6544 | /* Wait until ADDR flag is set */ |
||
6545 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6546 | { |
||
6547 | return HAL_ERROR; |
||
6548 | } |
||
6549 | |||
6550 | /* Clear ADDR flag */ |
||
6551 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6552 | |||
6553 | /* Wait until TXE flag is set */ |
||
6554 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6555 | { |
||
6556 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6557 | { |
||
6558 | /* Generate Stop */ |
||
6559 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6560 | } |
||
6561 | return HAL_ERROR; |
||
6562 | } |
||
6563 | |||
6564 | /* If Memory address size is 8Bit */ |
||
6565 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
||
6566 | { |
||
6567 | /* Send Memory Address */ |
||
6568 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
6569 | } |
||
6570 | /* If Memory address size is 16Bit */ |
||
6571 | else |
||
6572 | { |
||
6573 | /* Send MSB of Memory Address */ |
||
6574 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
||
6575 | |||
6576 | /* Wait until TXE flag is set */ |
||
6577 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6578 | { |
||
6579 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6580 | { |
||
6581 | /* Generate Stop */ |
||
6582 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6583 | } |
||
6584 | return HAL_ERROR; |
||
6585 | } |
||
6586 | |||
6587 | /* Send LSB of Memory Address */ |
||
6588 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
6589 | } |
||
6590 | |||
6591 | return HAL_OK; |
||
6592 | } |
||
6593 | |||
6594 | /** |
||
6595 | * @brief Master sends target device address followed by internal memory address for read request. |
||
6596 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6597 | * the configuration information for I2C module |
||
6598 | * @param DevAddress Target device address: The device 7 bits address value |
||
6599 | * in datasheet must be shifted to the left before calling the interface |
||
6600 | * @param MemAddress Internal memory address |
||
6601 | * @param MemAddSize Size of internal memory address |
||
6602 | * @param Timeout Timeout duration |
||
6603 | * @param Tickstart Tick start value |
||
6604 | * @retval HAL status |
||
6605 | */ |
||
6606 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
||
6607 | { |
||
6608 | /* Enable Acknowledge */ |
||
6609 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6610 | |||
6611 | /* Generate Start */ |
||
6612 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6613 | |||
6614 | /* Wait until SB flag is set */ |
||
6615 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6616 | { |
||
6617 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6618 | { |
||
6619 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6620 | } |
||
6621 | return HAL_TIMEOUT; |
||
6622 | } |
||
6623 | |||
6624 | /* Send slave address */ |
||
6625 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
||
6626 | |||
6627 | /* Wait until ADDR flag is set */ |
||
6628 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6629 | { |
||
6630 | return HAL_ERROR; |
||
6631 | } |
||
6632 | |||
6633 | /* Clear ADDR flag */ |
||
6634 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
||
6635 | |||
6636 | /* Wait until TXE flag is set */ |
||
6637 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6638 | { |
||
6639 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6640 | { |
||
6641 | /* Generate Stop */ |
||
6642 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6643 | } |
||
6644 | return HAL_ERROR; |
||
6645 | } |
||
6646 | |||
6647 | /* If Memory address size is 8Bit */ |
||
6648 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
||
6649 | { |
||
6650 | /* Send Memory Address */ |
||
6651 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
6652 | } |
||
6653 | /* If Memory address size is 16Bit */ |
||
6654 | else |
||
6655 | { |
||
6656 | /* Send MSB of Memory Address */ |
||
6657 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
||
6658 | |||
6659 | /* Wait until TXE flag is set */ |
||
6660 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6661 | { |
||
6662 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6663 | { |
||
6664 | /* Generate Stop */ |
||
6665 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6666 | } |
||
6667 | return HAL_ERROR; |
||
6668 | } |
||
6669 | |||
6670 | /* Send LSB of Memory Address */ |
||
6671 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
||
6672 | } |
||
6673 | |||
6674 | /* Wait until TXE flag is set */ |
||
6675 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
||
6676 | { |
||
6677 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
||
6678 | { |
||
6679 | /* Generate Stop */ |
||
6680 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6681 | } |
||
6682 | return HAL_ERROR; |
||
6683 | } |
||
6684 | |||
6685 | /* Generate Restart */ |
||
6686 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
||
6687 | |||
6688 | /* Wait until SB flag is set */ |
||
6689 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
||
6690 | { |
||
6691 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
||
6692 | { |
||
6693 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
||
6694 | } |
||
6695 | return HAL_TIMEOUT; |
||
6696 | } |
||
6697 | |||
6698 | /* Send slave address */ |
||
6699 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
||
6700 | |||
6701 | /* Wait until ADDR flag is set */ |
||
6702 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
||
6703 | { |
||
6704 | return HAL_ERROR; |
||
6705 | } |
||
6706 | |||
6707 | return HAL_OK; |
||
6708 | } |
||
6709 | |||
6710 | /** |
||
6711 | * @brief DMA I2C process complete callback. |
||
6712 | * @param hdma DMA handle |
||
6713 | * @retval None |
||
6714 | */ |
||
6715 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) |
||
6716 | { |
||
6717 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
6718 | |||
6719 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
6720 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
6721 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
||
6722 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
||
6723 | |||
6724 | /* Disable EVT and ERR interrupt */ |
||
6725 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
6726 | |||
6727 | /* Clear Complete callback */ |
||
6728 | if (hi2c->hdmatx != NULL) |
||
6729 | { |
||
6730 | hi2c->hdmatx->XferCpltCallback = NULL; |
||
6731 | } |
||
6732 | if (hi2c->hdmarx != NULL) |
||
6733 | { |
||
6734 | hi2c->hdmarx->XferCpltCallback = NULL; |
||
6735 | } |
||
6736 | |||
6737 | if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) |
||
6738 | { |
||
6739 | /* Disable DMA Request */ |
||
6740 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
6741 | |||
6742 | hi2c->XferCount = 0U; |
||
6743 | |||
6744 | if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) |
||
6745 | { |
||
6746 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
6747 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
||
6748 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
6749 | |||
6750 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6751 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6752 | hi2c->SlaveTxCpltCallback(hi2c); |
||
6753 | #else |
||
6754 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
||
6755 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6756 | } |
||
6757 | else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) |
||
6758 | { |
||
6759 | /* Set state at HAL_I2C_STATE_LISTEN */ |
||
6760 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
||
6761 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
6762 | |||
6763 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6764 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6765 | hi2c->SlaveRxCpltCallback(hi2c); |
||
6766 | #else |
||
6767 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
||
6768 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6769 | } |
||
6770 | else |
||
6771 | { |
||
6772 | /* Do nothing */ |
||
6773 | } |
||
6774 | |||
6775 | /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ |
||
6776 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
6777 | } |
||
6778 | /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ |
||
6779 | else if (hi2c->Mode != HAL_I2C_MODE_NONE) |
||
6780 | { |
||
6781 | if (hi2c->XferCount == (uint16_t)1) |
||
6782 | { |
||
6783 | /* Disable Acknowledge */ |
||
6784 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6785 | } |
||
6786 | |||
6787 | /* Disable EVT and ERR interrupt */ |
||
6788 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
||
6789 | |||
6790 | /* Prepare next transfer or stop current transfer */ |
||
6791 | if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) |
||
6792 | { |
||
6793 | /* Generate Stop */ |
||
6794 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
6795 | } |
||
6796 | |||
6797 | /* Disable Last DMA */ |
||
6798 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
||
6799 | |||
6800 | /* Disable DMA Request */ |
||
6801 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
||
6802 | |||
6803 | hi2c->XferCount = 0U; |
||
6804 | |||
6805 | /* Check if Errors has been detected during transfer */ |
||
6806 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
||
6807 | { |
||
6808 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6809 | hi2c->ErrorCallback(hi2c); |
||
6810 | #else |
||
6811 | HAL_I2C_ErrorCallback(hi2c); |
||
6812 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6813 | } |
||
6814 | else |
||
6815 | { |
||
6816 | hi2c->State = HAL_I2C_STATE_READY; |
||
6817 | |||
6818 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
||
6819 | { |
||
6820 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6821 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6822 | |||
6823 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6824 | hi2c->MemRxCpltCallback(hi2c); |
||
6825 | #else |
||
6826 | HAL_I2C_MemRxCpltCallback(hi2c); |
||
6827 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6828 | } |
||
6829 | else |
||
6830 | { |
||
6831 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6832 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
||
6833 | |||
6834 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6835 | hi2c->MasterRxCpltCallback(hi2c); |
||
6836 | #else |
||
6837 | HAL_I2C_MasterRxCpltCallback(hi2c); |
||
6838 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6839 | } |
||
6840 | } |
||
6841 | } |
||
6842 | else |
||
6843 | { |
||
6844 | /* Do nothing */ |
||
6845 | } |
||
6846 | } |
||
6847 | |||
6848 | /** |
||
6849 | * @brief DMA I2C communication error callback. |
||
6850 | * @param hdma DMA handle |
||
6851 | * @retval None |
||
6852 | */ |
||
6853 | static void I2C_DMAError(DMA_HandleTypeDef *hdma) |
||
6854 | { |
||
6855 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
6856 | |||
6857 | /* Clear Complete callback */ |
||
6858 | if (hi2c->hdmatx != NULL) |
||
6859 | { |
||
6860 | hi2c->hdmatx->XferCpltCallback = NULL; |
||
6861 | } |
||
6862 | if (hi2c->hdmarx != NULL) |
||
6863 | { |
||
6864 | hi2c->hdmarx->XferCpltCallback = NULL; |
||
6865 | } |
||
6866 | |||
6867 | /* Disable Acknowledge */ |
||
6868 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6869 | |||
6870 | hi2c->XferCount = 0U; |
||
6871 | hi2c->State = HAL_I2C_STATE_READY; |
||
6872 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6873 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
||
6874 | |||
6875 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6876 | hi2c->ErrorCallback(hi2c); |
||
6877 | #else |
||
6878 | HAL_I2C_ErrorCallback(hi2c); |
||
6879 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6880 | } |
||
6881 | |||
6882 | /** |
||
6883 | * @brief DMA I2C communication abort callback |
||
6884 | * (To be called at end of DMA Abort procedure). |
||
6885 | * @param hdma DMA handle. |
||
6886 | * @retval None |
||
6887 | */ |
||
6888 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) |
||
6889 | { |
||
6890 | __IO uint32_t count = 0U; |
||
6891 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
||
6892 | |||
6893 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
||
6894 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
||
6895 | |||
6896 | /* During abort treatment, check that there is no pending STOP request */ |
||
6897 | /* Wait until STOP flag is reset */ |
||
6898 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
||
6899 | do |
||
6900 | { |
||
6901 | if (count == 0U) |
||
6902 | { |
||
6903 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
6904 | break; |
||
6905 | } |
||
6906 | count--; |
||
6907 | } |
||
6908 | while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); |
||
6909 | |||
6910 | /* Clear Complete callback */ |
||
6911 | if (hi2c->hdmatx != NULL) |
||
6912 | { |
||
6913 | hi2c->hdmatx->XferCpltCallback = NULL; |
||
6914 | } |
||
6915 | if (hi2c->hdmarx != NULL) |
||
6916 | { |
||
6917 | hi2c->hdmarx->XferCpltCallback = NULL; |
||
6918 | } |
||
6919 | |||
6920 | /* Disable Acknowledge */ |
||
6921 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6922 | |||
6923 | hi2c->XferCount = 0U; |
||
6924 | |||
6925 | /* Reset XferAbortCallback */ |
||
6926 | if (hi2c->hdmatx != NULL) |
||
6927 | { |
||
6928 | hi2c->hdmatx->XferAbortCallback = NULL; |
||
6929 | } |
||
6930 | if (hi2c->hdmarx != NULL) |
||
6931 | { |
||
6932 | hi2c->hdmarx->XferAbortCallback = NULL; |
||
6933 | } |
||
6934 | |||
6935 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
||
6936 | __HAL_I2C_DISABLE(hi2c); |
||
6937 | |||
6938 | /* Check if come from abort from user */ |
||
6939 | if (hi2c->State == HAL_I2C_STATE_ABORT) |
||
6940 | { |
||
6941 | hi2c->State = HAL_I2C_STATE_READY; |
||
6942 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6943 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
||
6944 | |||
6945 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6946 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6947 | hi2c->AbortCpltCallback(hi2c); |
||
6948 | #else |
||
6949 | HAL_I2C_AbortCpltCallback(hi2c); |
||
6950 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6951 | } |
||
6952 | else |
||
6953 | { |
||
6954 | if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
||
6955 | { |
||
6956 | /* Renable I2C peripheral */ |
||
6957 | __HAL_I2C_ENABLE(hi2c); |
||
6958 | |||
6959 | /* Enable Acknowledge */ |
||
6960 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
||
6961 | |||
6962 | /* keep HAL_I2C_STATE_LISTEN */ |
||
6963 | hi2c->PreviousState = I2C_STATE_NONE; |
||
6964 | hi2c->State = HAL_I2C_STATE_LISTEN; |
||
6965 | } |
||
6966 | else |
||
6967 | { |
||
6968 | hi2c->State = HAL_I2C_STATE_READY; |
||
6969 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
6970 | } |
||
6971 | |||
6972 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
||
6973 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
||
6974 | hi2c->ErrorCallback(hi2c); |
||
6975 | #else |
||
6976 | HAL_I2C_ErrorCallback(hi2c); |
||
6977 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
||
6978 | } |
||
6979 | } |
||
6980 | |||
6981 | /** |
||
6982 | * @brief This function handles I2C Communication Timeout. |
||
6983 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
6984 | * the configuration information for I2C module |
||
6985 | * @param Flag specifies the I2C flag to check. |
||
6986 | * @param Status The new Flag status (SET or RESET). |
||
6987 | * @param Timeout Timeout duration |
||
6988 | * @param Tickstart Tick start value |
||
6989 | * @retval HAL status |
||
6990 | */ |
||
6991 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) |
||
6992 | { |
||
6993 | /* Wait until flag is set */ |
||
6994 | while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) |
||
6995 | { |
||
6996 | /* Check for the Timeout */ |
||
6997 | if (Timeout != HAL_MAX_DELAY) |
||
6998 | { |
||
6999 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7000 | { |
||
7001 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7002 | hi2c->State = HAL_I2C_STATE_READY; |
||
7003 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7004 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7005 | |||
7006 | /* Process Unlocked */ |
||
7007 | __HAL_UNLOCK(hi2c); |
||
7008 | |||
7009 | return HAL_ERROR; |
||
7010 | } |
||
7011 | } |
||
7012 | } |
||
7013 | return HAL_OK; |
||
7014 | } |
||
7015 | |||
7016 | /** |
||
7017 | * @brief This function handles I2C Communication Timeout for Master addressing phase. |
||
7018 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7019 | * the configuration information for I2C module |
||
7020 | * @param Flag specifies the I2C flag to check. |
||
7021 | * @param Timeout Timeout duration |
||
7022 | * @param Tickstart Tick start value |
||
7023 | * @retval HAL status |
||
7024 | */ |
||
7025 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) |
||
7026 | { |
||
7027 | while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) |
||
7028 | { |
||
7029 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
||
7030 | { |
||
7031 | /* Generate Stop */ |
||
7032 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
||
7033 | |||
7034 | /* Clear AF Flag */ |
||
7035 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
7036 | |||
7037 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7038 | hi2c->State = HAL_I2C_STATE_READY; |
||
7039 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7040 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
7041 | |||
7042 | /* Process Unlocked */ |
||
7043 | __HAL_UNLOCK(hi2c); |
||
7044 | |||
7045 | return HAL_ERROR; |
||
7046 | } |
||
7047 | |||
7048 | /* Check for the Timeout */ |
||
7049 | if (Timeout != HAL_MAX_DELAY) |
||
7050 | { |
||
7051 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7052 | { |
||
7053 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7054 | hi2c->State = HAL_I2C_STATE_READY; |
||
7055 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7056 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7057 | |||
7058 | /* Process Unlocked */ |
||
7059 | __HAL_UNLOCK(hi2c); |
||
7060 | |||
7061 | return HAL_ERROR; |
||
7062 | } |
||
7063 | } |
||
7064 | } |
||
7065 | return HAL_OK; |
||
7066 | } |
||
7067 | |||
7068 | /** |
||
7069 | * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. |
||
7070 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7071 | * the configuration information for the specified I2C. |
||
7072 | * @param Timeout Timeout duration |
||
7073 | * @param Tickstart Tick start value |
||
7074 | * @retval HAL status |
||
7075 | */ |
||
7076 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
7077 | { |
||
7078 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) |
||
7079 | { |
||
7080 | /* Check if a NACK is detected */ |
||
7081 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
||
7082 | { |
||
7083 | return HAL_ERROR; |
||
7084 | } |
||
7085 | |||
7086 | /* Check for the Timeout */ |
||
7087 | if (Timeout != HAL_MAX_DELAY) |
||
7088 | { |
||
7089 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7090 | { |
||
7091 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7092 | hi2c->State = HAL_I2C_STATE_READY; |
||
7093 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7094 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7095 | |||
7096 | /* Process Unlocked */ |
||
7097 | __HAL_UNLOCK(hi2c); |
||
7098 | |||
7099 | return HAL_ERROR; |
||
7100 | } |
||
7101 | } |
||
7102 | } |
||
7103 | return HAL_OK; |
||
7104 | } |
||
7105 | |||
7106 | /** |
||
7107 | * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. |
||
7108 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7109 | * the configuration information for the specified I2C. |
||
7110 | * @param Timeout Timeout duration |
||
7111 | * @param Tickstart Tick start value |
||
7112 | * @retval HAL status |
||
7113 | */ |
||
7114 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
7115 | { |
||
7116 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) |
||
7117 | { |
||
7118 | /* Check if a NACK is detected */ |
||
7119 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
||
7120 | { |
||
7121 | return HAL_ERROR; |
||
7122 | } |
||
7123 | |||
7124 | /* Check for the Timeout */ |
||
7125 | if (Timeout != HAL_MAX_DELAY) |
||
7126 | { |
||
7127 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7128 | { |
||
7129 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7130 | hi2c->State = HAL_I2C_STATE_READY; |
||
7131 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7132 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7133 | |||
7134 | /* Process Unlocked */ |
||
7135 | __HAL_UNLOCK(hi2c); |
||
7136 | |||
7137 | return HAL_ERROR; |
||
7138 | } |
||
7139 | } |
||
7140 | } |
||
7141 | return HAL_OK; |
||
7142 | } |
||
7143 | |||
7144 | /** |
||
7145 | * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. |
||
7146 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7147 | * the configuration information for the specified I2C. |
||
7148 | * @param Timeout Timeout duration |
||
7149 | * @param Tickstart Tick start value |
||
7150 | * @retval HAL status |
||
7151 | */ |
||
7152 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
7153 | { |
||
7154 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) |
||
7155 | { |
||
7156 | /* Check if a NACK is detected */ |
||
7157 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
||
7158 | { |
||
7159 | return HAL_ERROR; |
||
7160 | } |
||
7161 | |||
7162 | /* Check for the Timeout */ |
||
7163 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7164 | { |
||
7165 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7166 | hi2c->State = HAL_I2C_STATE_READY; |
||
7167 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7168 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7169 | |||
7170 | /* Process Unlocked */ |
||
7171 | __HAL_UNLOCK(hi2c); |
||
7172 | |||
7173 | return HAL_ERROR; |
||
7174 | } |
||
7175 | } |
||
7176 | return HAL_OK; |
||
7177 | } |
||
7178 | |||
7179 | /** |
||
7180 | * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. |
||
7181 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7182 | * the configuration information for the specified I2C. |
||
7183 | * @retval HAL status |
||
7184 | */ |
||
7185 | static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) |
||
7186 | { |
||
7187 | __IO uint32_t count = 0U; |
||
7188 | |||
7189 | /* Wait until STOP flag is reset */ |
||
7190 | count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); |
||
7191 | do |
||
7192 | { |
||
7193 | count--; |
||
7194 | if (count == 0U) |
||
7195 | { |
||
7196 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7197 | |||
7198 | return HAL_ERROR; |
||
7199 | } |
||
7200 | } |
||
7201 | while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); |
||
7202 | |||
7203 | return HAL_OK; |
||
7204 | } |
||
7205 | |||
7206 | /** |
||
7207 | * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. |
||
7208 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7209 | * the configuration information for the specified I2C. |
||
7210 | * @param Timeout Timeout duration |
||
7211 | * @param Tickstart Tick start value |
||
7212 | * @retval HAL status |
||
7213 | */ |
||
7214 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
||
7215 | { |
||
7216 | |||
7217 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) |
||
7218 | { |
||
7219 | /* Check if a STOPF is detected */ |
||
7220 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) |
||
7221 | { |
||
7222 | /* Clear STOP Flag */ |
||
7223 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
||
7224 | |||
7225 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7226 | hi2c->State = HAL_I2C_STATE_READY; |
||
7227 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7228 | hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; |
||
7229 | |||
7230 | /* Process Unlocked */ |
||
7231 | __HAL_UNLOCK(hi2c); |
||
7232 | |||
7233 | return HAL_ERROR; |
||
7234 | } |
||
7235 | |||
7236 | /* Check for the Timeout */ |
||
7237 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
||
7238 | { |
||
7239 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7240 | hi2c->State = HAL_I2C_STATE_READY; |
||
7241 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7242 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
||
7243 | |||
7244 | /* Process Unlocked */ |
||
7245 | __HAL_UNLOCK(hi2c); |
||
7246 | |||
7247 | return HAL_ERROR; |
||
7248 | } |
||
7249 | } |
||
7250 | return HAL_OK; |
||
7251 | } |
||
7252 | |||
7253 | /** |
||
7254 | * @brief This function handles Acknowledge failed detection during an I2C Communication. |
||
7255 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||
7256 | * the configuration information for the specified I2C. |
||
7257 | * @retval HAL status |
||
7258 | */ |
||
7259 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) |
||
7260 | { |
||
7261 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
||
7262 | { |
||
7263 | /* Clear NACKF Flag */ |
||
7264 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
||
7265 | |||
7266 | hi2c->PreviousState = I2C_STATE_NONE; |
||
7267 | hi2c->State = HAL_I2C_STATE_READY; |
||
7268 | hi2c->Mode = HAL_I2C_MODE_NONE; |
||
7269 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
||
7270 | |||
7271 | /* Process Unlocked */ |
||
7272 | __HAL_UNLOCK(hi2c); |
||
7273 | |||
7274 | return HAL_ERROR; |
||
7275 | } |
||
7276 | return HAL_OK; |
||
7277 | } |
||
7278 | |||
7279 | /** |
||
7280 | * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. |
||
7281 | * @param hi2c I2C handle. |
||
7282 | * @retval None |
||
7283 | */ |
||
7284 | static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) |
||
7285 | { |
||
7286 | /* if user set XferOptions to I2C_OTHER_FRAME */ |
||
7287 | /* it request implicitly to generate a restart condition */ |
||
7288 | /* set XferOptions to I2C_FIRST_FRAME */ |
||
7289 | if (hi2c->XferOptions == I2C_OTHER_FRAME) |
||
7290 | { |
||
7291 | hi2c->XferOptions = I2C_FIRST_FRAME; |
||
7292 | } |
||
7293 | /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ |
||
7294 | /* it request implicitly to generate a restart condition */ |
||
7295 | /* then generate a stop condition at the end of transfer */ |
||
7296 | /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ |
||
7297 | else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) |
||
7298 | { |
||
7299 | hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; |
||
7300 | } |
||
7301 | else |
||
7302 | { |
||
7303 | /* Nothing to do */ |
||
7304 | } |
||
7305 | } |
||
7306 | |||
7307 | /** |
||
7308 | * @} |
||
7309 | */ |
||
7310 | |||
7311 | #endif /* HAL_I2C_MODULE_ENABLED */ |
||
7312 | /** |
||
7313 | * @} |
||
7314 | */ |
||
7315 | |||
7316 | /** |
||
7317 | * @} |
||
7318 | */ |
||
7319 | |||
7320 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |